From nobody Sun May 19 07:16:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651839854944720.4152278926465; Fri, 6 May 2022 05:24:14 -0700 (PDT) Received: from localhost ([::1]:48094 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmx0F-000108-DA for importer@patchew.org; Fri, 06 May 2022 08:24:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43438) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmwvF-0005xn-Cu; Fri, 06 May 2022 08:19:01 -0400 Received: from [187.72.171.209] (port=63199 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmwvD-0005am-KU; Fri, 06 May 2022 08:19:01 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Fri, 6 May 2022 09:18:47 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 9D699801008; Fri, 6 May 2022 09:18:46 -0300 (-03) From: "Lucas Mateus Castro(alqotel)" To: qemu-ppc@nongnu.org Cc: richard.henderson@linaro.org, Joel Stanley , "Lucas Mateus Castro (alqotel)" , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Daniel Henrique Barboza , David Gibson , Greg Kurz , qemu-devel@nongnu.org (open list:All patches CC here) Subject: [RFC PATCH v2 1/7] target/ppc: Implement xxm[tf]acc and xxsetaccz Date: Fri, 6 May 2022 09:18:38 -0300 Message-Id: <20220506121844.18969-2-lucas.araujo@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506121844.18969-1-lucas.araujo@eldorado.org.br> References: <20220506121844.18969-1-lucas.araujo@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 06 May 2022 12:18:47.0082 (UTC) FILETIME=[6F9EF0A0:01D86143] X-Host-Lookup-Failed: Reverse DNS lookup failed for 187.72.171.209 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=187.72.171.209; envelope-from=lucas.araujo@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1651839856545100001 Content-Type: text/plain; charset="utf-8" From: "Lucas Mateus Castro (alqotel)" Implement the following PowerISA v3.1 instructions: xxmfacc: VSX Move From Accumulator xxmtacc: VSX Move To Accumulator xxsetaccz: VSX Set Accumulator to Zero The PowerISA 3.1 mentions that for the current version of the architecture, "the hardware implementation provides the effect of ACC[i] and VSRs 4*i to 4*i + 3 logically containing the same data" and "The Accumulators introduce no new logical state at this time" (page 501). For now it seems unnecessary to create new structures, so this patch just uses ACC[i] as VSRs 4*i to 4*i+3 and therefore move to and from accumulators are no-ops. Signed-off-by: Lucas Mateus Castro (alqotel) Reviewed-by: Richard Henderson --- target/ppc/cpu.h | 5 +++++ target/ppc/insn32.decode | 9 +++++++++ target/ppc/translate/vsx-impl.c.inc | 31 +++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 48596cfb25..10c6d7ae43 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2659,6 +2659,11 @@ static inline int vsr_full_offset(int i) return offsetof(CPUPPCState, vsr[i].u64[0]); } =20 +static inline int acc_full_offset(int i) +{ + return vsr_full_offset(i * 4); +} + static inline int fpr_offset(int i) { return vsr64_offset(i, true); diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 39372fe673..7a76bedfa6 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -151,6 +151,9 @@ &X_vrt_frbp vrt frbp @X_vrt_frbp ...... vrt:5 ..... ....0 .......... . &X_vrt_frb= p frbp=3D%x_frbp =20 +&X_a ra +@X_a ...... ra:3 .. ..... ..... .......... . &X_a + %xx_xt 0:1 21:5 %xx_xb 1:1 11:5 %xx_xa 2:1 16:5 @@ -710,3 +713,9 @@ XVTLSBB 111100 ... -- 00010 ..... 111011011 . -= @XX2_bf_xb &XL_s s:uint8_t @XL_s ......-------------- s:1 .......... - &XL_s RFEBB 010011-------------- . 0010010010 - @XL_s + +## Accumulator Instructions + +XXMFACC 011111 ... -- 00000 ----- 0010110001 - @X_a +XXMTACC 011111 ... -- 00001 ----- 0010110001 - @X_a +XXSETACCZ 011111 ... -- 00011 ----- 0010110001 - @X_a diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx= -impl.c.inc index 3692740736..dc8875d5d3 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -2787,6 +2787,37 @@ static bool trans_XVCVBF16SPN(DisasContext *ctx, arg= _XX2 *a) return true; } =20 + /* + * The PowerISA 3.1 mentions that for the current version of the + * architecture, "the hardware implementation provides the effect of + * ACC[i] and VSRs 4*i to 4*i + 3 logically containing the same data" + * and "The Accumulators introduce no new logical state at this time" + * (page 501). For now it seems unnecessary to create new structures, + * so ACC[i] is the same as VSRs 4*i to 4*i+3 and therefore + * move to and from accumulators are no-ops. + */ +static bool trans_XXMFACC(DisasContext *ctx, arg_X_a *a) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VSX(ctx); + return true; +} + +static bool trans_XXMTACC(DisasContext *ctx, arg_X_a *a) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VSX(ctx); + return true; +} + +static bool trans_XXSETACCZ(DisasContext *ctx, arg_X_a *a) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VSX(ctx); + tcg_gen_gvec_dup_imm(MO_64, acc_full_offset(a->ra), 64, 64, 0); + return true; +} + #undef GEN_XX2FORM #undef GEN_XX3FORM #undef GEN_XX2IFORM --=20 2.31.1 From nobody Sun May 19 07:16:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651840253496613.4706842673235; Fri, 6 May 2022 05:30:53 -0700 (PDT) Received: from localhost ([::1]:58846 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmx6i-0008TP-4N for importer@patchew.org; Fri, 06 May 2022 08:30:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43468) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmwvI-00064b-FN; Fri, 06 May 2022 08:19:04 -0400 Received: from [187.72.171.209] (port=63199 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmwvG-0005am-8R; Fri, 06 May 2022 08:19:04 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Fri, 6 May 2022 09:18:47 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 204258000CB; Fri, 6 May 2022 09:18:47 -0300 (-03) From: "Lucas Mateus Castro(alqotel)" To: qemu-ppc@nongnu.org Cc: richard.henderson@linaro.org, Joel Stanley , "Lucas Mateus Castro (alqotel)" , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Daniel Henrique Barboza , David Gibson , Greg Kurz , qemu-devel@nongnu.org (open list:All patches CC here) Subject: [RFC PATCH v2 2/7] target/ppc: Implemented xvi*ger* instructions Date: Fri, 6 May 2022 09:18:39 -0300 Message-Id: <20220506121844.18969-3-lucas.araujo@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506121844.18969-1-lucas.araujo@eldorado.org.br> References: <20220506121844.18969-1-lucas.araujo@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 06 May 2022 12:18:47.0614 (UTC) FILETIME=[6FF01DE0:01D86143] X-Host-Lookup-Failed: Reverse DNS lookup failed for 187.72.171.209 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=187.72.171.209; envelope-from=lucas.araujo@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1651840254193100001 Content-Type: text/plain; charset="utf-8" From: "Lucas Mateus Castro (alqotel)" Implement the following PowerISA v3.1 instructions: xvi4ger8: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) xvi4ger8pp: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) Positive multiply, Positive accumulate xvi8ger4: VSX Vector 4-bit Signed Integer GER (rank-8 update) xvi8ger4pp: VSX Vector 4-bit Signed Integer GER (rank-8 update) Positive multiply, Positive accumulate xvi8ger4spp: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) with Saturate Positive multiply, Positive accumulate xvi16ger2: VSX Vector 16-bit Signed Integer GER (rank-2 update) xvi16ger2pp: VSX Vector 16-bit Signed Integer GER (rank-2 update) Positive multiply, Positive accumulate xvi16ger2s: VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation xvi16ger2spp: VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation Positive multiply, Positive accumulate Signed-off-by: Lucas Mateus Castro (alqotel) Reviewed-by or do I sent without them so you can review the changes? Reviewed-by: Richard Henderson --- target/ppc/cpu.h | 1 + target/ppc/helper.h | 9 ++ target/ppc/insn32.decode | 15 ++++ target/ppc/int_helper.c | 130 ++++++++++++++++++++++++++++ target/ppc/internal.h | 15 ++++ target/ppc/translate/vsx-impl.c.inc | 42 +++++++++ 6 files changed, 212 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 10c6d7ae43..348a898950 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -238,6 +238,7 @@ typedef union _ppc_vsr_t { =20 typedef ppc_vsr_t ppc_avr_t; typedef ppc_vsr_t ppc_fprp_t; +typedef ppc_vsr_t ppc_acc_t; =20 #if !defined(CONFIG_USER_ONLY) /* Software TLB cache */ diff --git a/target/ppc/helper.h b/target/ppc/helper.h index aa6773c4a5..61217e0a10 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -537,6 +537,15 @@ DEF_HELPER_5(XXBLENDVB, void, vsr, vsr, vsr, vsr, i32) DEF_HELPER_5(XXBLENDVH, void, vsr, vsr, vsr, vsr, i32) DEF_HELPER_5(XXBLENDVW, void, vsr, vsr, vsr, vsr, i32) DEF_HELPER_5(XXBLENDVD, void, vsr, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVI4GER8, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVI4GER8PP, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVI8GER4, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVI8GER4PP, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVI8GER4SPP, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVI16GER2, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVI16GER2S, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVI16GER2PP, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVI16GER2SPP, void, env, vsr, vsr, vsr, i32) =20 DEF_HELPER_2(efscfsi, i32, env, i32) DEF_HELPER_2(efscfui, i32, env, i32) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 7a76bedfa6..62fb0214f4 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -170,6 +170,9 @@ &XX3 xt xa xb @XX3 ...... ..... ..... ..... ........ ... &XX3 xt=3D= %xx_xt xa=3D%xx_xa xb=3D%xx_xb =20 +%xx_at 23:3 +@XX3_at ...... ... .. ..... ..... ........ ... &XX3 xt=3D= %xx_at xb=3D%xx_xb + &XX3_dm xt xa xb dm @XX3_dm ...... ..... ..... ..... . dm:2 ..... ... &XX3_dm xt= =3D%xx_xt xa=3D%xx_xa xb=3D%xx_xb =20 @@ -719,3 +722,15 @@ RFEBB 010011-------------- . 0010010010 - = @XL_s XXMFACC 011111 ... -- 00000 ----- 0010110001 - @X_a XXMTACC 011111 ... -- 00001 ----- 0010110001 - @X_a XXSETACCZ 011111 ... -- 00011 ----- 0010110001 - @X_a + +## Vector GER instruction + +XVI4GER8 111011 ... -- ..... ..... 00100011 ..- @XX3_at xa=3D%xx_xa +XVI4GER8PP 111011 ... -- ..... ..... 00100010 ..- @XX3_at xa=3D%xx_xa +XVI8GER4 111011 ... -- ..... ..... 00000011 ..- @XX3_at xa=3D%xx_xa +XVI8GER4PP 111011 ... -- ..... ..... 00000010 ..- @XX3_at xa=3D%xx_xa +XVI16GER2 111011 ... -- ..... ..... 01001011 ..- @XX3_at xa=3D%xx_xa +XVI16GER2PP 111011 ... -- ..... ..... 01101011 ..- @XX3_at xa=3D%xx_xa +XVI8GER4SPP 111011 ... -- ..... ..... 01100011 ..- @XX3_at xa=3D%xx_xa +XVI16GER2S 111011 ... -- ..... ..... 00101011 ..- @XX3_at xa=3D%xx_xa +XVI16GER2SPP 111011 ... -- ..... ..... 00101010 ..- @XX3_at xa=3D%xx_xa diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 8c1674510b..32a7d99718 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -782,6 +782,136 @@ VCT(uxs, cvtsduw, u32) VCT(sxs, cvtsdsw, s32) #undef VCT =20 +typedef int64_t do_ger(uint32_t, uint32_t, uint32_t); + +static int64_t ger_rank8(uint32_t a, uint32_t b, uint32_t mask) +{ + int64_t psum =3D 0; + for (int i =3D 0; i < 8; i++, mask >>=3D 1) { + if (mask & 1) { + psum +=3D sextract32(a, 4 * i, 4) * sextract32(b, 4 * i, 4); + } + } + return psum; +} + +static int64_t ger_rank4(uint32_t a, uint32_t b, uint32_t mask) +{ + int64_t psum =3D 0; + for (int i =3D 0; i < 4; i++, mask >>=3D 1) { + if (mask & 1) { + psum +=3D sextract32(a, 8 * i, 8) * (int64_t)extract32(b, 8 * = i, 8); + } + } + return psum; +} + +static int64_t ger_rank2(uint32_t a, uint32_t b, uint32_t mask) +{ + int64_t psum =3D 0; + for (int i =3D 0; i < 2; i++, mask >>=3D 1) { + if (mask & 1) { + psum +=3D sextract32(a, 16 * i, 16) * sextract32(b, 16 * i, 16= ); + } + } + return psum; +} + +static void xviger(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, ppc_acc_t= *at, + uint32_t mask, bool sat, bool acc, do_ger ger) +{ + uint8_t pmsk =3D FIELD_EX32(mask, GER_MSK, PMSK), + xmsk =3D FIELD_EX32(mask, GER_MSK, XMSK), + ymsk =3D FIELD_EX32(mask, GER_MSK, YMSK); + uint8_t xmsk_bit, ymsk_bit; + int64_t psum; + int i, j; + for (i =3D 0, xmsk_bit =3D 1 << 3; i < 4; i++, xmsk_bit >>=3D 1) { + for (j =3D 0, ymsk_bit =3D 1 << 3; j < 4; j++, ymsk_bit >>=3D 1) { + if ((xmsk_bit & xmsk) && (ymsk_bit & ymsk)) { + psum =3D ger(a->VsrW(i), b->VsrW(j), pmsk); + if (acc) { + psum +=3D at[i].VsrSW(j); + } + if (sat && psum > INT32_MAX) { + set_vscr_sat(env); + at[i].VsrSW(j) =3D INT32_MAX; + } else if (sat && psum < INT32_MIN) { + set_vscr_sat(env); + at[i].VsrSW(j) =3D INT32_MIN; + } else { + at[i].VsrSW(j) =3D (int32_t) psum; + } + } else { + at[i].VsrSW(j) =3D 0; + } + } + } +} + +QEMU_FLATTEN +void helper_XVI4GER8(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + xviger(env, a, b, at, mask, false, false, ger_rank8); +} + +QEMU_FLATTEN +void helper_XVI4GER8PP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + xviger(env, a, b, at, mask, false, true, ger_rank8); +} + +QEMU_FLATTEN +void helper_XVI8GER4(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + xviger(env, a, b, at, mask, false, false, ger_rank4); +} + +QEMU_FLATTEN +void helper_XVI8GER4PP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + xviger(env, a, b, at, mask, false, true, ger_rank4); +} + +QEMU_FLATTEN +void helper_XVI8GER4SPP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + xviger(env, a, b, at, mask, true, true, ger_rank4); +} + +QEMU_FLATTEN +void helper_XVI16GER2(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + xviger(env, a, b, at, mask, false, false, ger_rank2); +} + +QEMU_FLATTEN +void helper_XVI16GER2S(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + xviger(env, a, b, at, mask, true, false, ger_rank2); +} + +QEMU_FLATTEN +void helper_XVI16GER2PP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + xviger(env, a, b, at, mask, false, true, ger_rank2); +} + +QEMU_FLATTEN +void helper_XVI16GER2SPP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + xviger(env, a, b, at, mask, true, true, ger_rank2); +} + target_ulong helper_vclzlsbb(ppc_avr_t *r) { target_ulong count =3D 0; diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 8094e0b033..2add128cd1 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -18,6 +18,8 @@ #ifndef PPC_INTERNAL_H #define PPC_INTERNAL_H =20 +#include "hw/registerfields.h" + #define FUNC_MASK(name, ret_type, size, max_val) \ static inline ret_type name(uint##size##_t start, \ uint##size##_t end) \ @@ -291,4 +293,17 @@ G_NORETURN void ppc_cpu_do_unaligned_access(CPUState *= cs, vaddr addr, uintptr_t retaddr); #endif =20 +FIELD(GER_MSK, XMSK, 0, 4) +FIELD(GER_MSK, YMSK, 4, 4) +FIELD(GER_MSK, PMSK, 8, 8) + +static inline int ger_pack_masks(int pmsk, int ymsk, int xmsk) +{ + int msk =3D 0; + msk =3D FIELD_DP32(msk, GER_MSK, XMSK, xmsk); + msk =3D FIELD_DP32(msk, GER_MSK, YMSK, ymsk); + msk =3D FIELD_DP32(msk, GER_MSK, PMSK, pmsk); + return msk; +} + #endif /* PPC_INTERNAL_H */ diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx= -impl.c.inc index dc8875d5d3..829e04fc87 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -17,6 +17,13 @@ static inline TCGv_ptr gen_vsr_ptr(int reg) return r; } =20 +static inline TCGv_ptr gen_acc_ptr(int reg) +{ + TCGv_ptr r =3D tcg_temp_new_ptr(); + tcg_gen_addi_ptr(r, cpu_env, acc_full_offset(reg)); + return r; +} + #define VSX_LOAD_SCALAR(name, operation) \ static void gen_##name(DisasContext *ctx) \ { \ @@ -2818,6 +2825,41 @@ static bool trans_XXSETACCZ(DisasContext *ctx, arg_X= _a *a) return true; } =20 +static bool do_ger_XX3(DisasContext *ctx, arg_XX3 *a, + void (*helper)(TCGv_env, TCGv_ptr, TCGv_ptr, + TCGv_ptr, TCGv_i32)) +{ + uint32_t mask; + TCGv_ptr xt, xa, xb; + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VSX(ctx); + if (unlikely((a->xa / 4 =3D=3D a->xt) || (a->xb / 4 =3D=3D a->xt))) { + gen_invalid(ctx); + return true; + } + + xt =3D gen_acc_ptr(a->xt); + xa =3D gen_vsr_ptr(a->xa); + xb =3D gen_vsr_ptr(a->xb); + + mask =3D 0xFFFFFFFF; + helper(cpu_env, xa, xb, xt, tcg_constant_i32(mask)); + tcg_temp_free_ptr(xt); + tcg_temp_free_ptr(xa); + tcg_temp_free_ptr(xb); + return true; +} + +TRANS(XVI4GER8, do_ger_XX3, gen_helper_XVI4GER8) +TRANS(XVI4GER8PP, do_ger_XX3, gen_helper_XVI4GER8PP) +TRANS(XVI8GER4, do_ger_XX3, gen_helper_XVI8GER4) +TRANS(XVI8GER4PP, do_ger_XX3, gen_helper_XVI8GER4PP) +TRANS(XVI8GER4SPP, do_ger_XX3, gen_helper_XVI8GER4SPP) +TRANS(XVI16GER2, do_ger_XX3, gen_helper_XVI16GER2) +TRANS(XVI16GER2PP, do_ger_XX3, gen_helper_XVI16GER2PP) +TRANS(XVI16GER2S, do_ger_XX3, gen_helper_XVI16GER2S) +TRANS(XVI16GER2SPP, do_ger_XX3, gen_helper_XVI16GER2SPP) + #undef GEN_XX2FORM #undef GEN_XX3FORM #undef GEN_XX2IFORM --=20 2.31.1 From nobody Sun May 19 07:16:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651839847106834.5752130007608; Fri, 6 May 2022 05:24:07 -0700 (PDT) Received: from localhost ([::1]:47742 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmx09-0000lW-1R for importer@patchew.org; Fri, 06 May 2022 08:24:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43482) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmwvL-0006BO-1z; Fri, 06 May 2022 08:19:07 -0400 Received: from [187.72.171.209] (port=63199 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmwvJ-0005am-EG; Fri, 06 May 2022 08:19:06 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Fri, 6 May 2022 09:18:48 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id A1C988000CB; Fri, 6 May 2022 09:18:47 -0300 (-03) From: "Lucas Mateus Castro(alqotel)" To: qemu-ppc@nongnu.org Cc: richard.henderson@linaro.org, Joel Stanley , "Lucas Mateus Castro (alqotel)" , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Daniel Henrique Barboza , David Gibson , Greg Kurz , qemu-devel@nongnu.org (open list:All patches CC here) Subject: [RFC PATCH v2 3/7] target/ppc: Implemented pmxvi*ger* instructions Date: Fri, 6 May 2022 09:18:40 -0300 Message-Id: <20220506121844.18969-4-lucas.araujo@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506121844.18969-1-lucas.araujo@eldorado.org.br> References: <20220506121844.18969-1-lucas.araujo@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 06 May 2022 12:18:48.0067 (UTC) FILETIME=[70353D30:01D86143] X-Host-Lookup-Failed: Reverse DNS lookup failed for 187.72.171.209 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=187.72.171.209; envelope-from=lucas.araujo@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1651839849517100001 Content-Type: text/plain; charset="utf-8" From: "Lucas Mateus Castro (alqotel)" Implement the following PowerISA v3.1 instructions: pmxvi4ger8: Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) pmxvi4ger8pp: Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) Positive multiply, Positive accumulate pmxvi8ger4: Prefixed Masked VSX Vector 4-bit Signed Integer GER (rank-8 update) pmxvi8ger4pp: Prefixed Masked VSX Vector 4-bit Signed Integer GER (rank-8 update) Positive multiply, Positive accumulate pmxvi8ger4spp: Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) with Saturate Positive multiply, Positive accumulate pmxvi16ger2: Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) pmxvi16ger2pp: Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) Positive multiply, Positive accumulate pmxvi16ger2s: Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation pmxvi16ger2spp: Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation Positive multiply, Positive accumulate Signed-off-by: Lucas Mateus Castro (alqotel) Reviewed-by: Richard Henderson --- target/ppc/insn64.decode | 30 +++++++++++++++++++++++++++++ target/ppc/translate/vsx-impl.c.inc | 28 +++++++++++++++++++++++++-- 2 files changed, 56 insertions(+), 2 deletions(-) diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index 691e8fe6c0..7b65f71a02 100644 --- a/target/ppc/insn64.decode +++ b/target/ppc/insn64.decode @@ -68,6 +68,15 @@ ...... ..... ..... ..... ..... .. .... \ &8RR_XX4_uim3 xt=3D%8rr_xx_xt xa=3D%8rr_xx_xa xb=3D%8rr_xx= _xb xc=3D%8rr_xx_xc =20 +# Format MMIRR:XX3 +&MMIRR_XX3 xa xb xt pmsk xmsk ymsk +%xx3_xa 2:1 16:5 +%xx3_xb 1:1 11:5 +%xx3_at 23:3 +@MMIRR_XX3 ...... .. .... .. . . ........ xmsk:4 ymsk:4 \ + ...... ... .. ..... ..... ........ ... \ + &MMIRR_XX3 xa=3D%xx3_xa xb=3D%xx3_xb xt=3D%xx3_at + ### Fixed-Point Load Instructions =20 PLBZ 000001 10 0--.-- .................. \ @@ -115,6 +124,27 @@ PSTFS 000001 10 0--.-- .................. \ PSTFD 000001 10 0--.-- .................. \ 110110 ..... ..... ................ @PLS_D =20 +## Vector GER instruction + +PMXVI4GER8 000001 11 1001 -- - - pmsk:8 ........ \ + 111011 ... -- ..... ..... 00100011 ..- @MMIRR_XX3 +PMXVI4GER8PP 000001 11 1001 -- - - pmsk:8 ........ \ + 111011 ... -- ..... ..... 00100010 ..- @MMIRR_XX3 +PMXVI8GER4 000001 11 1001 -- - - pmsk:4 ---- ........ \ + 111011 ... -- ..... ..... 00000011 ..- @MMIRR_XX3 +PMXVI8GER4PP 000001 11 1001 -- - - pmsk:4 ---- ........ \ + 111011 ... -- ..... ..... 00000010 ..- @MMIRR_XX3 +PMXVI16GER2 000001 11 1001 -- - - pmsk:2 ------ ........ \ + 111011 ... -- ..... ..... 01001011 ..- @MMIRR_XX3 +PMXVI16GER2PP 000001 11 1001 -- - - pmsk:2 ------ ........ \ + 111011 ... -- ..... ..... 01101011 ..- @MMIRR_XX3 +PMXVI8GER4SPP 000001 11 1001 -- - - pmsk:4 ---- ........ \ + 111011 ... -- ..... ..... 01100011 ..- @MMIRR_XX3 +PMXVI16GER2S 000001 11 1001 -- - - pmsk:2 ------ ........ \ + 111011 ... -- ..... ..... 00101011 ..- @MMIRR_XX3 +PMXVI16GER2SPP 000001 11 1001 -- - - pmsk:2 ------ ........ \ + 111011 ... -- ..... ..... 00101010 ..- @MMIRR_XX3 + ### Prefixed No-operation Instruction =20 @PNOP 000001 11 0000-- 000000000000000000 \ diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx= -impl.c.inc index 829e04fc87..06bc83c03a 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -2825,7 +2825,7 @@ static bool trans_XXSETACCZ(DisasContext *ctx, arg_X_= a *a) return true; } =20 -static bool do_ger_XX3(DisasContext *ctx, arg_XX3 *a, +static bool do_ger_MMIRR_XX3(DisasContext *ctx, arg_MMIRR_XX3 *a, void (*helper)(TCGv_env, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32)) { @@ -2842,12 +2842,26 @@ static bool do_ger_XX3(DisasContext *ctx, arg_XX3 *= a, xa =3D gen_vsr_ptr(a->xa); xb =3D gen_vsr_ptr(a->xb); =20 - mask =3D 0xFFFFFFFF; + mask =3D ger_pack_masks(a->pmsk, a->ymsk, a->xmsk); helper(cpu_env, xa, xb, xt, tcg_constant_i32(mask)); tcg_temp_free_ptr(xt); tcg_temp_free_ptr(xa); tcg_temp_free_ptr(xb); return true; + +} +static bool do_ger_XX3(DisasContext *ctx, arg_XX3 *a, + void (*helper)(TCGv_env, TCGv_ptr, TCGv_ptr, + TCGv_ptr, TCGv_i32)) +{ + arg_MMIRR_XX3 m; + m.xa =3D a->xa; + m.xb =3D a->xb; + m.xt =3D a->xt; + m.pmsk =3D 0xFF; + m.ymsk =3D 0xF; + m.xmsk =3D 0xF; + return do_ger_MMIRR_XX3(ctx, &m, helper); } =20 TRANS(XVI4GER8, do_ger_XX3, gen_helper_XVI4GER8) @@ -2860,6 +2874,16 @@ TRANS(XVI16GER2PP, do_ger_XX3, gen_helper_XVI16GER2P= P) TRANS(XVI16GER2S, do_ger_XX3, gen_helper_XVI16GER2S) TRANS(XVI16GER2SPP, do_ger_XX3, gen_helper_XVI16GER2SPP) =20 +TRANS64(PMXVI4GER8, do_ger_MMIRR_XX3, gen_helper_XVI4GER8) +TRANS64(PMXVI4GER8PP, do_ger_MMIRR_XX3, gen_helper_XVI4GER8PP) +TRANS64(PMXVI8GER4, do_ger_MMIRR_XX3, gen_helper_XVI8GER4) +TRANS64(PMXVI8GER4PP, do_ger_MMIRR_XX3, gen_helper_XVI8GER4PP) +TRANS64(PMXVI8GER4SPP, do_ger_MMIRR_XX3, gen_helper_XVI8GER4SPP) +TRANS64(PMXVI16GER2, do_ger_MMIRR_XX3, gen_helper_XVI16GER2) +TRANS64(PMXVI16GER2PP, do_ger_MMIRR_XX3, gen_helper_XVI16GER2PP) +TRANS64(PMXVI16GER2S, do_ger_MMIRR_XX3, gen_helper_XVI16GER2S) +TRANS64(PMXVI16GER2SPP, do_ger_MMIRR_XX3, gen_helper_XVI16GER2SPP) + #undef GEN_XX2FORM #undef GEN_XX3FORM #undef GEN_XX2IFORM --=20 2.31.1 From nobody Sun May 19 07:16:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165184085923048.35253491023866; Fri, 6 May 2022 05:40:59 -0700 (PDT) Received: from localhost ([::1]:43566 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmxGT-0003Df-B5 for importer@patchew.org; Fri, 06 May 2022 08:40:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43502) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmwvO-0006Jk-7d; Fri, 06 May 2022 08:19:10 -0400 Received: from [187.72.171.209] (port=63199 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmwvM-0005am-2l; Fri, 06 May 2022 08:19:09 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Fri, 6 May 2022 09:18:48 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 23A8B8000CB; Fri, 6 May 2022 09:18:48 -0300 (-03) From: "Lucas Mateus Castro(alqotel)" To: qemu-ppc@nongnu.org Cc: richard.henderson@linaro.org, Joel Stanley , "Lucas Mateus Castro (alqotel)" , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Daniel Henrique Barboza , David Gibson , Greg Kurz , qemu-devel@nongnu.org (open list:All patches CC here) Subject: [RFC PATCH v2 4/7] target/ppc: Implemented xvf*ger* Date: Fri, 6 May 2022 09:18:41 -0300 Message-Id: <20220506121844.18969-5-lucas.araujo@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506121844.18969-1-lucas.araujo@eldorado.org.br> References: <20220506121844.18969-1-lucas.araujo@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 06 May 2022 12:18:48.0570 (UTC) FILETIME=[7081FDA0:01D86143] X-Host-Lookup-Failed: Reverse DNS lookup failed for 187.72.171.209 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=187.72.171.209; envelope-from=lucas.araujo@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1651840861018100001 Content-Type: text/plain; charset="utf-8" From: "Lucas Mateus Castro (alqotel)" Implement the following PowerISA v3.1 instructions: xvf32ger: VSX Vector 32-bit Floating-Point GER (rank-1 update) xvf32gernn: VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate xvf32gernp: VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate xvf32gerpn: VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate xvf32gerpp: VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate xvf64ger: VSX Vector 64-bit Floating-Point GER (rank-1 update) xvf64gernn: VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate xvf64gernp: VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate xvf64gerpn: VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate xvf64gerpp: VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate Signed-off-by: Lucas Mateus Castro (alqotel) --- target/ppc/cpu.h | 4 + target/ppc/fpu_helper.c | 178 ++++++++++++++++++++++++++++ target/ppc/helper.h | 10 ++ target/ppc/insn32.decode | 13 ++ target/ppc/translate/vsx-impl.c.inc | 12 ++ 5 files changed, 217 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 348a898950..eb50ad699e 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2639,6 +2639,8 @@ static inline bool lsw_reg_in_range(int start, int nr= egs, int rx) #define VsrSW(i) s32[i] #define VsrD(i) u64[i] #define VsrSD(i) s64[i] +#define VsrSF(i) f32[i] +#define VsrDF(i) f64[i] #else #define VsrB(i) u8[15 - (i)] #define VsrSB(i) s8[15 - (i)] @@ -2648,6 +2650,8 @@ static inline bool lsw_reg_in_range(int start, int nr= egs, int rx) #define VsrSW(i) s32[3 - (i)] #define VsrD(i) u64[1 - (i)] #define VsrSD(i) s64[1 - (i)] +#define VsrSF(i) f32[3 - (i)] +#define VsrDF(i) f64[1 - (i)] #endif =20 static inline int vsr64_offset(int i, bool high) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index f6c8318a71..138b30d08f 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -3462,3 +3462,181 @@ void helper_xssubqp(CPUPPCState *env, uint32_t opco= de, *xt =3D t; do_float_check_status(env, GETPC()); } + +static void set_rounding_mode_rn(CPUPPCState *env) +{ + uint8_t rmode =3D (env->fpscr & FP_RN) >> FPSCR_RN0; + switch (rmode) { + case 0: + set_float_rounding_mode(float_round_nearest_even, &env->fp_status); + break; + case 1: + set_float_rounding_mode(float_round_to_zero, &env->fp_status); + break; + case 2: + set_float_rounding_mode(float_round_up, &env->fp_status); + break; + case 3: + set_float_rounding_mode(float_round_down, &env->fp_status); + break; + default: + abort(); + } +} + +typedef void vsxger_zero(ppc_vsr_t *at, int, int); + +typedef void vsxger_muladd_f(ppc_vsr_t *, ppc_vsr_t *, ppc_vsr_t *, int, i= nt, + int flags, float_status *s); + +static void vsxger_muladd32(ppc_vsr_t *at, ppc_vsr_t *a, ppc_vsr_t *b, int= i, int j, + int flags, float_status *s) +{ + at[i].VsrSF(j) =3D float32_muladd(a->VsrSF(i), b->VsrSF(j), at[i].VsrS= F(j), flags, s); +} + +static void vsxger_mul32(ppc_vsr_t *at, ppc_vsr_t *a, ppc_vsr_t *b, int i,= int j, + int flags, float_status *s) +{ + at[i].VsrSF(j) =3D float32_mul(a->VsrSF(i), b->VsrSF(j), s); +} + +static void vsxger_zero32(ppc_vsr_t *at, int i, int j) +{ + at[i].VsrSF(j) =3D float32_zero; +} + +static void vsxger_muladd64(ppc_vsr_t *at, ppc_vsr_t *a, ppc_vsr_t *b, int= i, int j, + int flags, float_status *s) +{ + if (j >=3D 2) { + j -=3D 2; + at[i].VsrDF(j) =3D float64_muladd(a[i / 2].VsrDF(i % 2), b->VsrDF(= j), + at[i].VsrDF(j), flags, s); + } +} + +static void vsxger_mul64(ppc_vsr_t *at, ppc_vsr_t *a, ppc_vsr_t *b, int i,= int j, + int flags, float_status *s) +{ + if (j >=3D 2) { + j -=3D 2; + at[i].VsrDF(j) =3D float64_mul(a[i / 2].VsrDF(i % 2), b->VsrDF(j),= s); + } +} + +static void vsxger_zero64(ppc_vsr_t *at, int i, int j) +{ + if (j >=3D 2) { + j -=3D 2; + at[i].VsrDF(j) =3D float64_zero; + } +} + +static void vsxger(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, ppc_acc_t= *at, + uint32_t mask, bool acc, bool neg_mul, bool neg_acc, + vsxger_muladd_f mul, vsxger_muladd_f muladd, vsxger_zer= o zero) +{ + int i, j, xmsk_bit, ymsk_bit, op_flags; + uint8_t xmsk =3D mask & 0x0F; + uint8_t ymsk =3D (mask >> 4) & 0x0F; + float_status *excp_ptr =3D &env->fp_status; + op_flags =3D (neg_acc ^ neg_mul) ? float_muladd_negate_c : 0; + op_flags |=3D (neg_mul) ? float_muladd_negate_result : 0; + helper_reset_fpstatus(env); + set_rounding_mode_rn(env); + for (i =3D 0, xmsk_bit =3D 1 << 3; i < 4; i++, xmsk_bit >>=3D 1) { + for (j =3D 0, ymsk_bit =3D 1 << 3; j < 4; j++, ymsk_bit >>=3D 1) { + if ((xmsk_bit & xmsk) && (ymsk_bit & ymsk)) { + if (acc) { + muladd(at, a, b, i, j, op_flags, excp_ptr); + } else { + mul(at, a, b, i, j, op_flags, excp_ptr); + } + } else { + zero(at, i, j); + } + } + } + do_float_check_status(env, GETPC()); +} + +QEMU_FLATTEN +void helper_XVF32GER(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + vsxger(env, a, b, at, mask, false, false, false, vsxger_mul32, + vsxger_muladd32, vsxger_zero32); +} + +QEMU_FLATTEN +void helper_XVF32GERPP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + vsxger(env, a, b, at, mask, true, false, false, vsxger_mul32, + vsxger_muladd32, vsxger_zero32); +} + +QEMU_FLATTEN +void helper_XVF32GERPN(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + vsxger(env, a, b, at, mask, true, false, true, vsxger_mul32, + vsxger_muladd32, vsxger_zero32); +} + +QEMU_FLATTEN +void helper_XVF32GERNP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + vsxger(env, a, b, at, mask, true, true, false, vsxger_mul32, + vsxger_muladd32, vsxger_zero32); +} + +QEMU_FLATTEN +void helper_XVF32GERNN(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + vsxger(env, a, b, at, mask, true, true, true, vsxger_mul32, + vsxger_muladd32, vsxger_zero32); +} + +QEMU_FLATTEN +void helper_XVF64GER(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + vsxger(env, a, b, at, mask, false, false, false, vsxger_mul64, + vsxger_muladd64, vsxger_zero64); +} + +QEMU_FLATTEN +void helper_XVF64GERPP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + vsxger(env, a, b, at, mask, true, false, false, vsxger_mul64, + vsxger_muladd64, vsxger_zero64); +} + +QEMU_FLATTEN +void helper_XVF64GERPN(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + vsxger(env, a, b, at, mask, true, false, true, vsxger_mul64, + vsxger_muladd64, vsxger_zero64); +} + +QEMU_FLATTEN +void helper_XVF64GERNP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + vsxger(env, a, b, at, mask, true, true, false, vsxger_mul64, + vsxger_muladd64, vsxger_zero64); +} + +QEMU_FLATTEN +void helper_XVF64GERNN(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + vsxger(env, a, b, at, mask, true, true, true, vsxger_mul64, + vsxger_muladd64, vsxger_zero64); +} diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 61217e0a10..360aa74ed1 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -546,6 +546,16 @@ DEF_HELPER_5(XVI16GER2, void, env, vsr, vsr, vsr, i32) DEF_HELPER_5(XVI16GER2S, void, env, vsr, vsr, vsr, i32) DEF_HELPER_5(XVI16GER2PP, void, env, vsr, vsr, vsr, i32) DEF_HELPER_5(XVI16GER2SPP, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVF32GER, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVF32GERPP, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVF32GERPN, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVF32GERNP, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVF32GERNN, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVF64GER, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVF64GERPP, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVF64GERPN, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVF64GERNP, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVF64GERNN, void, env, vsr, vsr, vsr, i32) =20 DEF_HELPER_2(efscfsi, i32, env, i32) DEF_HELPER_2(efscfui, i32, env, i32) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 62fb0214f4..9a3581db2f 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -171,6 +171,7 @@ @XX3 ...... ..... ..... ..... ........ ... &XX3 xt=3D= %xx_xt xa=3D%xx_xa xb=3D%xx_xb =20 %xx_at 23:3 +%xx_xa_pair 2:1 17:4 !function=3Dtimes_2 @XX3_at ...... ... .. ..... ..... ........ ... &XX3 xt=3D= %xx_at xb=3D%xx_xb =20 &XX3_dm xt xa xb dm @@ -734,3 +735,15 @@ XVI16GER2PP 111011 ... -- ..... ..... 01101011 ..-= @XX3_at xa=3D%xx_xa XVI8GER4SPP 111011 ... -- ..... ..... 01100011 ..- @XX3_at xa=3D%xx_xa XVI16GER2S 111011 ... -- ..... ..... 00101011 ..- @XX3_at xa=3D%xx_xa XVI16GER2SPP 111011 ... -- ..... ..... 00101010 ..- @XX3_at xa=3D%xx_xa + +XVF32GER 111011 ... -- ..... ..... 00011011 ..- @XX3_at xa=3D%xx_xa +XVF32GERPP 111011 ... -- ..... ..... 00011010 ..- @XX3_at xa=3D%xx_xa +XVF32GERPN 111011 ... -- ..... ..... 10011010 ..- @XX3_at xa=3D%xx_xa +XVF32GERNP 111011 ... -- ..... ..... 01011010 ..- @XX3_at xa=3D%xx_xa +XVF32GERNN 111011 ... -- ..... ..... 11011010 ..- @XX3_at xa=3D%xx_xa + +XVF64GER 111011 ... -- .... 0 ..... 00111011 ..- @XX3_at xa=3D%xx_= xa_pair +XVF64GERPP 111011 ... -- .... 0 ..... 00111010 ..- @XX3_at xa=3D%xx_= xa_pair +XVF64GERPN 111011 ... -- .... 0 ..... 10111010 ..- @XX3_at xa=3D%xx_= xa_pair +XVF64GERNP 111011 ... -- .... 0 ..... 01111010 ..- @XX3_at xa=3D%xx_= xa_pair +XVF64GERNN 111011 ... -- .... 0 ..... 11111010 ..- @XX3_at xa=3D%xx_= xa_pair diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx= -impl.c.inc index 06bc83c03a..764c6ded70 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -2884,6 +2884,18 @@ TRANS64(PMXVI16GER2PP, do_ger_MMIRR_XX3, gen_helper_= XVI16GER2PP) TRANS64(PMXVI16GER2S, do_ger_MMIRR_XX3, gen_helper_XVI16GER2S) TRANS64(PMXVI16GER2SPP, do_ger_MMIRR_XX3, gen_helper_XVI16GER2SPP) =20 +TRANS(XVF32GER, do_ger_XX3, gen_helper_XVF32GER) +TRANS(XVF32GERPP, do_ger_XX3, gen_helper_XVF32GERPP) +TRANS(XVF32GERPN, do_ger_XX3, gen_helper_XVF32GERPN) +TRANS(XVF32GERNP, do_ger_XX3, gen_helper_XVF32GERNP) +TRANS(XVF32GERNN, do_ger_XX3, gen_helper_XVF32GERNN) + +TRANS(XVF64GER, do_ger_XX3, gen_helper_XVF64GER) +TRANS(XVF64GERPP, do_ger_XX3, gen_helper_XVF64GERPP) +TRANS(XVF64GERPN, do_ger_XX3, gen_helper_XVF64GERPN) +TRANS(XVF64GERNP, do_ger_XX3, gen_helper_XVF64GERNP) +TRANS(XVF64GERNN, do_ger_XX3, gen_helper_XVF64GERNN) + #undef GEN_XX2FORM #undef GEN_XX3FORM #undef GEN_XX2IFORM --=20 2.31.1 From nobody Sun May 19 07:16:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651840175564862.6851507256058; Fri, 6 May 2022 05:29:35 -0700 (PDT) Received: from localhost ([::1]:56810 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmx5R-00071g-7b for importer@patchew.org; Fri, 06 May 2022 08:29:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43532) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmwvR-0006RR-3h; Fri, 06 May 2022 08:19:13 -0400 Received: from [187.72.171.209] (port=63199 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmwvP-0005am-6c; Fri, 06 May 2022 08:19:12 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Fri, 6 May 2022 09:18:49 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 9EEF68000CB; Fri, 6 May 2022 09:18:48 -0300 (-03) From: "Lucas Mateus Castro(alqotel)" To: qemu-ppc@nongnu.org Cc: richard.henderson@linaro.org, Joel Stanley , "Lucas Mateus Castro (alqotel)" , Aurelien Jarno , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Daniel Henrique Barboza , David Gibson , Greg Kurz , qemu-devel@nongnu.org (open list:All patches CC here) Subject: [RFC PATCH v2 5/7] target/ppc: Implemented xvf16ger* Date: Fri, 6 May 2022 09:18:42 -0300 Message-Id: <20220506121844.18969-6-lucas.araujo@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506121844.18969-1-lucas.araujo@eldorado.org.br> References: <20220506121844.18969-1-lucas.araujo@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 06 May 2022 12:18:49.0134 (UTC) FILETIME=[70D80CE0:01D86143] X-Host-Lookup-Failed: Reverse DNS lookup failed for 187.72.171.209 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=187.72.171.209; envelope-from=lucas.araujo@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1651840176621100001 Content-Type: text/plain; charset="utf-8" From: "Lucas Mateus Castro (alqotel)" Implement the following PowerISA v3.1 instructions: xvf16ger2: VSX Vector 16-bit Floating-Point GER (rank-2 update) xvf16ger2nn: VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Negative accumulate xvf16ger2np: VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Positive accumulate xvf16ger2pn: VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Negative accumulate xvf16ger2pp: VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Positive accumulate Signed-off-by: Lucas Mateus Castro (alqotel) --- include/fpu/softfloat.h | 9 +++ target/ppc/cpu.h | 3 + target/ppc/fpu_helper.c | 85 +++++++++++++++++++++++++++++ target/ppc/helper.h | 5 ++ target/ppc/insn32.decode | 6 ++ target/ppc/translate/vsx-impl.c.inc | 6 ++ 6 files changed, 114 insertions(+) diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 3dcf20e3a2..63d7ff18f0 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -619,6 +619,15 @@ static inline float32 float32_chs(float32 a) return make_float32(float32_val(a) ^ 0x80000000); } =20 +static inline float32 float32_neg(float32 a) +{ + if (((a & 0x7f800000) =3D=3D 0x7f800000) && (a & 0x007fffff)) { + return a; + } else { + return float32_chs(a); + } +} + static inline bool float32_is_infinity(float32 a) { return (float32_val(a) & 0x7fffffff) =3D=3D 0x7f800000; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index eb50ad699e..c891a23830 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -227,6 +227,7 @@ typedef union _ppc_vsr_t { int16_t s16[8]; int32_t s32[4]; int64_t s64[2]; + float16 f16[8]; float32 f32[4]; float64 f64[2]; float128 f128; @@ -2639,6 +2640,7 @@ static inline bool lsw_reg_in_range(int start, int nr= egs, int rx) #define VsrSW(i) s32[i] #define VsrD(i) u64[i] #define VsrSD(i) s64[i] +#define VsrHF(i) f16[i] #define VsrSF(i) f32[i] #define VsrDF(i) f64[i] #else @@ -2650,6 +2652,7 @@ static inline bool lsw_reg_in_range(int start, int nr= egs, int rx) #define VsrSW(i) s32[3 - (i)] #define VsrD(i) u64[1 - (i)] #define VsrSD(i) s64[1 - (i)] +#define VsrHF(i) f16[7 - (i)] #define VsrSF(i) f32[3 - (i)] #define VsrDF(i) f64[1 - (i)] #endif diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 138b30d08f..6857be6ccc 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -3484,6 +3484,56 @@ static void set_rounding_mode_rn(CPUPPCState *env) } } =20 +typedef float64 extract_f16(float16, float_status *); + +static float64 extract_hf16(float16 in, float_status *fp_status) +{ + return float16_to_float64(in, true, fp_status); +} + +static void vsxger16(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask, bool acc, + bool neg_mul, bool neg_acc, extract_f16 extract) +{ + float32 msum, aux_acc; + float64 psum, va, vb, vc, vd; + int i, j, xmsk_bit, ymsk_bit; + uint8_t pmsk =3D FIELD_EX32(mask, GER_MSK, PMSK), + xmsk =3D FIELD_EX32(mask, GER_MSK, XMSK), + ymsk =3D FIELD_EX32(mask, GER_MSK, YMSK); + float_status *excp_ptr =3D &env->fp_status; + set_rounding_mode_rn(env); + for (i =3D 0, xmsk_bit =3D 1 << 3; i < 4; i++, xmsk_bit >>=3D 1) { + for (j =3D 0, ymsk_bit =3D 1 << 3; j < 4; j++, ymsk_bit >>=3D 1) { + if ((xmsk_bit & xmsk) && (ymsk_bit & ymsk)) { + va =3D !(pmsk & 2) ? float64_zero : extract(a->VsrHF(2 * i= ), excp_ptr); + vb =3D !(pmsk & 2) ? float64_zero : extract(b->VsrHF(2 * j= ), excp_ptr); + vc =3D !(pmsk & 1) ? float64_zero : extract(a->VsrHF(2 * i= + 1), excp_ptr); + vd =3D !(pmsk & 1) ? float64_zero : extract(b->VsrHF(2 * j= + 1), excp_ptr); + psum =3D float64_mul(va, vb, excp_ptr); + psum =3D float64r32_muladd(vc, vd, psum, 0, excp_ptr); + msum =3D float64_to_float32(psum, excp_ptr); + if (acc) { + if (neg_mul) { + msum =3D float32_neg(msum); + } + if (neg_acc) { + aux_acc =3D float32_neg(at[i].VsrSF(j)); + } else { + aux_acc =3D at[i].VsrSF(j); + } + at[i].VsrSF(j) =3D float32_add(msum, aux_acc, excp_ptr= ); + } else { + at[i].VsrSF(j) =3D msum; + } + } else { + at[i].VsrSF(j) =3D float32_zero; + } + } + } + do_float_check_status(env, GETPC()); +} + typedef void vsxger_zero(ppc_vsr_t *at, int, int); =20 typedef void vsxger_muladd_f(ppc_vsr_t *, ppc_vsr_t *, ppc_vsr_t *, int, i= nt, @@ -3561,6 +3611,41 @@ static void vsxger(CPUPPCState *env, ppc_vsr_t *a, p= pc_vsr_t *b, ppc_acc_t *at, do_float_check_status(env, GETPC()); } =20 +QEMU_FLATTEN +void helper_XVF16GER2(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + vsxger16(env, a, b, at, mask, false, false, false, extract_hf16); +} + +QEMU_FLATTEN +void helper_XVF16GER2PP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + vsxger16(env, a, b, at, mask, true, false, false, extract_hf16); +} + +QEMU_FLATTEN +void helper_XVF16GER2PN(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + vsxger16(env, a, b, at, mask, true, false, true, extract_hf16); +} + +QEMU_FLATTEN +void helper_XVF16GER2NP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + vsxger16(env, a, b, at, mask, true, true, false, extract_hf16); +} + +QEMU_FLATTEN +void helper_XVF16GER2NN(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + vsxger16(env, a, b, at, mask, true, true, true, extract_hf16); +} + QEMU_FLATTEN void helper_XVF32GER(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, ppc_acc_t *at, uint32_t mask) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 360aa74ed1..5f2f574d30 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -546,6 +546,11 @@ DEF_HELPER_5(XVI16GER2, void, env, vsr, vsr, vsr, i32) DEF_HELPER_5(XVI16GER2S, void, env, vsr, vsr, vsr, i32) DEF_HELPER_5(XVI16GER2PP, void, env, vsr, vsr, vsr, i32) DEF_HELPER_5(XVI16GER2SPP, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVF16GER2, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVF16GER2PP, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVF16GER2PN, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVF16GER2NP, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVF16GER2NN, void, env, vsr, vsr, vsr, i32) DEF_HELPER_5(XVF32GER, void, env, vsr, vsr, vsr, i32) DEF_HELPER_5(XVF32GERPP, void, env, vsr, vsr, vsr, i32) DEF_HELPER_5(XVF32GERPN, void, env, vsr, vsr, vsr, i32) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 9a3581db2f..bbd4bc80f8 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -736,6 +736,12 @@ XVI8GER4SPP 111011 ... -- ..... ..... 01100011 ..-= @XX3_at xa=3D%xx_xa XVI16GER2S 111011 ... -- ..... ..... 00101011 ..- @XX3_at xa=3D%xx_xa XVI16GER2SPP 111011 ... -- ..... ..... 00101010 ..- @XX3_at xa=3D%xx_xa =20 +XVF16GER2 111011 ... -- ..... ..... 00010011 ..- @XX3_at xa=3D%xx_xa +XVF16GER2PP 111011 ... -- ..... ..... 00010010 ..- @XX3_at xa=3D%xx_xa +XVF16GER2PN 111011 ... -- ..... ..... 10010010 ..- @XX3_at xa=3D%xx_xa +XVF16GER2NP 111011 ... -- ..... ..... 01010010 ..- @XX3_at xa=3D%xx_xa +XVF16GER2NN 111011 ... -- ..... ..... 11010010 ..- @XX3_at xa=3D%xx_xa + XVF32GER 111011 ... -- ..... ..... 00011011 ..- @XX3_at xa=3D%xx_xa XVF32GERPP 111011 ... -- ..... ..... 00011010 ..- @XX3_at xa=3D%xx_xa XVF32GERPN 111011 ... -- ..... ..... 10011010 ..- @XX3_at xa=3D%xx_xa diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx= -impl.c.inc index 764c6ded70..a8155b8bee 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -2884,6 +2884,12 @@ TRANS64(PMXVI16GER2PP, do_ger_MMIRR_XX3, gen_helper_= XVI16GER2PP) TRANS64(PMXVI16GER2S, do_ger_MMIRR_XX3, gen_helper_XVI16GER2S) TRANS64(PMXVI16GER2SPP, do_ger_MMIRR_XX3, gen_helper_XVI16GER2SPP) =20 +TRANS(XVF16GER2, do_ger_XX3, gen_helper_XVF16GER2) +TRANS(XVF16GER2PP, do_ger_XX3, gen_helper_XVF16GER2PP) +TRANS(XVF16GER2PN, do_ger_XX3, gen_helper_XVF16GER2PN) +TRANS(XVF16GER2NP, do_ger_XX3, gen_helper_XVF16GER2NP) +TRANS(XVF16GER2NN, do_ger_XX3, gen_helper_XVF16GER2NN) + TRANS(XVF32GER, do_ger_XX3, gen_helper_XVF32GER) TRANS(XVF32GERPP, do_ger_XX3, gen_helper_XVF32GERPP) TRANS(XVF32GERPN, do_ger_XX3, gen_helper_XVF32GERPN) --=20 2.31.1 From nobody Sun May 19 07:16:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651839866233201.9449351850285; Fri, 6 May 2022 05:24:26 -0700 (PDT) Received: from localhost ([::1]:48342 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmx0S-0001AC-L1 for importer@patchew.org; Fri, 06 May 2022 08:24:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43554) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmwvT-0006Z8-Pc; Fri, 06 May 2022 08:19:15 -0400 Received: from [187.72.171.209] (port=63199 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmwvS-0005am-0B; Fri, 06 May 2022 08:19:15 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Fri, 6 May 2022 09:18:49 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 33B418000CB; Fri, 6 May 2022 09:18:49 -0300 (-03) From: "Lucas Mateus Castro(alqotel)" To: qemu-ppc@nongnu.org Cc: richard.henderson@linaro.org, Joel Stanley , "Lucas Mateus Castro (alqotel)" , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Daniel Henrique Barboza , David Gibson , Greg Kurz , qemu-devel@nongnu.org (open list:All patches CC here) Subject: [RFC PATCH v2 6/7] target/ppc: Implemented pmxvf*ger* Date: Fri, 6 May 2022 09:18:43 -0300 Message-Id: <20220506121844.18969-7-lucas.araujo@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506121844.18969-1-lucas.araujo@eldorado.org.br> References: <20220506121844.18969-1-lucas.araujo@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 06 May 2022 12:18:49.0665 (UTC) FILETIME=[71291310:01D86143] X-Host-Lookup-Failed: Reverse DNS lookup failed for 187.72.171.209 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=187.72.171.209; envelope-from=lucas.araujo@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1651839868753100001 Content-Type: text/plain; charset="utf-8" From: "Lucas Mateus Castro (alqotel)" Implement the following PowerISA v3.1 instructions: pmxvf16ger2: Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) pmxvf16ger2nn: Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Negative accumulate pmxvf16ger2np: Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Positive accumulate pmxvf16ger2pn: Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Negative accumulate pmxvf16ger2pp: Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Positive accumulate pmxvf32ger: Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) pmxvf32gernn: Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate pmxvf32gernp: Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate pmxvf32gerpn: Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate pmxvf32gerpp: Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate pmxvf64ger: Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) pmxvf64gernn: Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate pmxvf64gernp: Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate pmxvf64gerpn: Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate pmxvf64gerpp: Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate Signed-off-by: Lucas Mateus Castro (alqotel) Reviewed-by: Richard Henderson --- target/ppc/insn64.decode | 38 +++++++++++++++++++++++++++++ target/ppc/translate/vsx-impl.c.inc | 18 ++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index 7b65f71a02..a12f11044c 100644 --- a/target/ppc/insn64.decode +++ b/target/ppc/insn64.decode @@ -73,10 +73,15 @@ %xx3_xa 2:1 16:5 %xx3_xb 1:1 11:5 %xx3_at 23:3 +%xx3_xa_pair 2:1 17:4 !function=3Dtimes_2 @MMIRR_XX3 ...... .. .... .. . . ........ xmsk:4 ymsk:4 \ ...... ... .. ..... ..... ........ ... \ &MMIRR_XX3 xa=3D%xx3_xa xb=3D%xx3_xb xt=3D%xx3_at =20 +@MMIRR_XX3_NO_P ...... .. .... .. . . ........ xmsk:4 .... \ + ...... ... .. ..... ..... ........ ... \ + &MMIRR_XX3 xb=3D%xx3_xb xt=3D%xx3_at pmsk=3D1 + ### Fixed-Point Load Instructions =20 PLBZ 000001 10 0--.-- .................. \ @@ -145,6 +150,39 @@ PMXVI16GER2S 000001 11 1001 -- - - pmsk:2 ------ ..= ...... \ PMXVI16GER2SPP 000001 11 1001 -- - - pmsk:2 ------ ........ \ 111011 ... -- ..... ..... 00101010 ..- @MMIRR_XX3 =20 +PMXVF16GER2 000001 11 1001 -- - - pmsk:2 ------ ........ \ + 111011 ... -- ..... ..... 00010011 ..- @MMIRR_XX3 +PMXVF16GER2PP 000001 11 1001 -- - - pmsk:2 ------ ........ \ + 111011 ... -- ..... ..... 00010010 ..- @MMIRR_XX3 +PMXVF16GER2PN 000001 11 1001 -- - - pmsk:2 ------ ........ \ + 111011 ... -- ..... ..... 10010010 ..- @MMIRR_XX3 +PMXVF16GER2NP 000001 11 1001 -- - - pmsk:2 ------ ........ \ + 111011 ... -- ..... ..... 01010010 ..- @MMIRR_XX3 +PMXVF16GER2NN 000001 11 1001 -- - - pmsk:2 ------ ........ \ + 111011 ... -- ..... ..... 11010010 ..- @MMIRR_XX3 + +PMXVF32GER 000001 11 1001 -- - - -------- .... ymsk:4 \ + 111011 ... -- ..... ..... 00011011 ..- @MMIRR_XX3_NO_P xa= =3D%xx3_xa +PMXVF32GERPP 000001 11 1001 -- - - -------- .... ymsk:4 \ + 111011 ... -- ..... ..... 00011010 ..- @MMIRR_XX3_NO_P xa= =3D%xx3_xa +PMXVF32GERPN 000001 11 1001 -- - - -------- .... ymsk:4 \ + 111011 ... -- ..... ..... 10011010 ..- @MMIRR_XX3_NO_P xa= =3D%xx3_xa +PMXVF32GERNP 000001 11 1001 -- - - -------- .... ymsk:4 \ + 111011 ... -- ..... ..... 01011010 ..- @MMIRR_XX3_NO_P xa= =3D%xx3_xa +PMXVF32GERNN 000001 11 1001 -- - - -------- .... ymsk:4 \ + 111011 ... -- ..... ..... 11011010 ..- @MMIRR_XX3_NO_P xa= =3D%xx3_xa + +PMXVF64GER 000001 11 1001 -- - - -------- .... ymsk:2 -- \ + 111011 ... -- ....0 ..... 00111011 ..- @MMIRR_XX3_NO_P xa= =3D%xx3_xa_pair +PMXVF64GERPP 000001 11 1001 -- - - -------- .... ymsk:2 -- \ + 111011 ... -- ....0 ..... 00111010 ..- @MMIRR_XX3_NO_P xa= =3D%xx3_xa_pair +PMXVF64GERPN 000001 11 1001 -- - - -------- .... ymsk:2 -- \ + 111011 ... -- ....0 ..... 10111010 ..- @MMIRR_XX3_NO_P xa= =3D%xx3_xa_pair +PMXVF64GERNP 000001 11 1001 -- - - -------- .... ymsk:2 -- \ + 111011 ... -- ....0 ..... 01111010 ..- @MMIRR_XX3_NO_P xa= =3D%xx3_xa_pair +PMXVF64GERNN 000001 11 1001 -- - - -------- .... ymsk:2 -- \ + 111011 ... -- ....0 ..... 11111010 ..- @MMIRR_XX3_NO_P xa= =3D%xx3_xa_pair + ### Prefixed No-operation Instruction =20 @PNOP 000001 11 0000-- 000000000000000000 \ diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx= -impl.c.inc index a8155b8bee..00eed2b1b9 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -2902,6 +2902,24 @@ TRANS(XVF64GERPN, do_ger_XX3, gen_helper_XVF64GERPN) TRANS(XVF64GERNP, do_ger_XX3, gen_helper_XVF64GERNP) TRANS(XVF64GERNN, do_ger_XX3, gen_helper_XVF64GERNN) =20 +TRANS64(PMXVF16GER2, do_ger_MMIRR_XX3, gen_helper_XVF16GER2) +TRANS64(PMXVF16GER2PP, do_ger_MMIRR_XX3, gen_helper_XVF16GER2PP) +TRANS64(PMXVF16GER2PN, do_ger_MMIRR_XX3, gen_helper_XVF16GER2PN) +TRANS64(PMXVF16GER2NP, do_ger_MMIRR_XX3, gen_helper_XVF16GER2NP) +TRANS64(PMXVF16GER2NN, do_ger_MMIRR_XX3, gen_helper_XVF16GER2NN) + +TRANS64(PMXVF32GER, do_ger_MMIRR_XX3, gen_helper_XVF32GER) +TRANS64(PMXVF32GERPP, do_ger_MMIRR_XX3, gen_helper_XVF32GERPP) +TRANS64(PMXVF32GERPN, do_ger_MMIRR_XX3, gen_helper_XVF32GERPN) +TRANS64(PMXVF32GERNP, do_ger_MMIRR_XX3, gen_helper_XVF32GERNP) +TRANS64(PMXVF32GERNN, do_ger_MMIRR_XX3, gen_helper_XVF32GERNN) + +TRANS64(PMXVF64GER, do_ger_MMIRR_XX3, gen_helper_XVF64GER) +TRANS64(PMXVF64GERPP, do_ger_MMIRR_XX3, gen_helper_XVF64GERPP) +TRANS64(PMXVF64GERPN, do_ger_MMIRR_XX3, gen_helper_XVF64GERPN) +TRANS64(PMXVF64GERNP, do_ger_MMIRR_XX3, gen_helper_XVF64GERNP) +TRANS64(PMXVF64GERNN, do_ger_MMIRR_XX3, gen_helper_XVF64GERNN) + #undef GEN_XX2FORM #undef GEN_XX3FORM #undef GEN_XX2IFORM --=20 2.31.1 From nobody Sun May 19 07:16:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165184036471831.78698447825684; Fri, 6 May 2022 05:32:44 -0700 (PDT) Received: from localhost ([::1]:60656 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmx8V-0001J1-Mx for importer@patchew.org; Fri, 06 May 2022 08:32:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43790) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmwwW-0007KN-P3; Fri, 06 May 2022 08:20:21 -0400 Received: from [187.72.171.209] (port=47457 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmwwU-0005uX-QS; Fri, 06 May 2022 08:20:20 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Fri, 6 May 2022 09:18:50 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id AC3B5801008; Fri, 6 May 2022 09:18:49 -0300 (-03) From: "Lucas Mateus Castro(alqotel)" To: qemu-ppc@nongnu.org Cc: richard.henderson@linaro.org, Joel Stanley , "Lucas Mateus Castro (alqotel)" , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Daniel Henrique Barboza , David Gibson , Greg Kurz , qemu-devel@nongnu.org (open list:All patches CC here) Subject: [RFC PATCH v2 7/7] target/ppc: Implemented [pm]xvbf16ger2* Date: Fri, 6 May 2022 09:18:44 -0300 Message-Id: <20220506121844.18969-8-lucas.araujo@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506121844.18969-1-lucas.araujo@eldorado.org.br> References: <20220506121844.18969-1-lucas.araujo@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 06 May 2022 12:18:50.0134 (UTC) FILETIME=[7170A360:01D86143] X-Host-Lookup-Failed: Reverse DNS lookup failed for 187.72.171.209 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=187.72.171.209; envelope-from=lucas.araujo@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1651840365210100001 Content-Type: text/plain; charset="utf-8" From: "Lucas Mateus Castro (alqotel)" Implement the following PowerISA v3.1 instructions: xvbf16ger2: VSX Vector bfloat16 GER (rank-2 update) xvbf16ger2nn: VSX Vector bfloat16 GER (rank-2 update) Negative multiply, Negative accumulate xvbf16ger2np: VSX Vector bfloat16 GER (rank-2 update) Negative multiply, Positive accumulate xvbf16ger2pn: VSX Vector bfloat16 GER (rank-2 update) Positive multiply, Negative accumulate xvbf16ger2pp: VSX Vector bfloat16 GER (rank-2 update) Positive multiply, Positive accumulate pmxvbf16ger2: Prefixed Masked VSX Vector bfloat16 GER (rank-2 update) pmxvbf16ger2nn: Prefixed Masked VSX Vector bfloat16 GER (rank-2 update) Negative multiply, Negative accumulate pmxvbf16ger2np: Prefixed Masked VSX Vector bfloat16 GER (rank-2 update) Negative multiply, Positive accumulate pmxvbf16ger2pn: Prefixed Masked VSX Vector bfloat16 GER (rank-2 update) Positive multiply, Negative accumulate pmxvbf16ger2pp: Prefixed Masked VSX Vector bfloat16 GER (rank-2 update) Positive multiply, Positive accumulate Signed-off-by: Lucas Mateus Castro (alqotel) Reviewed-by: Richard Henderson --- There's a discrepancy between this implementation and mambo/the hardware where implementing it with float64_mul then float64r32_muladd sometimes results in an incorrect result after an underflow, but implementing with float32_mul then float32_muladd results in incorrect signal in some 0 or infinite results. I've not been able to solve this --- target/ppc/fpu_helper.c | 40 +++++++++++++++++++++++++++++ target/ppc/helper.h | 5 ++++ target/ppc/insn32.decode | 6 +++++ target/ppc/insn64.decode | 11 ++++++++ target/ppc/translate/vsx-impl.c.inc | 12 +++++++++ 5 files changed, 74 insertions(+) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 6857be6ccc..0882702301 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -3491,6 +3491,11 @@ static float64 extract_hf16(float16 in, float_status= *fp_status) return float16_to_float64(in, true, fp_status); } =20 +static float64 extract_bf16(bfloat16 in, float_status *fp_status) +{ + return bfloat16_to_float64(in, fp_status); +} + static void vsxger16(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, ppc_acc_t *at, uint32_t mask, bool acc, bool neg_mul, bool neg_acc, extract_f16 extract) @@ -3611,6 +3616,41 @@ static void vsxger(CPUPPCState *env, ppc_vsr_t *a, p= pc_vsr_t *b, ppc_acc_t *at, do_float_check_status(env, GETPC()); } =20 +QEMU_FLATTEN +void helper_XVBF16GER2(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + vsxger16(env, a, b, at, mask, false, false, false, extract_bf16); +} + +QEMU_FLATTEN +void helper_XVBF16GER2PP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + vsxger16(env, a, b, at, mask, true, false, false, extract_bf16); +} + +QEMU_FLATTEN +void helper_XVBF16GER2PN(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + vsxger16(env, a, b, at, mask, true, false, true, extract_bf16); +} + +QEMU_FLATTEN +void helper_XVBF16GER2NP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + vsxger16(env, a, b, at, mask, true, true, false, extract_bf16); +} + +QEMU_FLATTEN +void helper_XVBF16GER2NN(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, + ppc_acc_t *at, uint32_t mask) +{ + vsxger16(env, a, b, at, mask, true, true, true, extract_bf16); +} + QEMU_FLATTEN void helper_XVF16GER2(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, ppc_acc_t *at, uint32_t mask) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 5f2f574d30..59e6b74f94 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -551,6 +551,11 @@ DEF_HELPER_5(XVF16GER2PP, void, env, vsr, vsr, vsr, i3= 2) DEF_HELPER_5(XVF16GER2PN, void, env, vsr, vsr, vsr, i32) DEF_HELPER_5(XVF16GER2NP, void, env, vsr, vsr, vsr, i32) DEF_HELPER_5(XVF16GER2NN, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVBF16GER2, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVBF16GER2PP, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVBF16GER2PN, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVBF16GER2NP, void, env, vsr, vsr, vsr, i32) +DEF_HELPER_5(XVBF16GER2NN, void, env, vsr, vsr, vsr, i32) DEF_HELPER_5(XVF32GER, void, env, vsr, vsr, vsr, i32) DEF_HELPER_5(XVF32GERPP, void, env, vsr, vsr, vsr, i32) DEF_HELPER_5(XVF32GERPN, void, env, vsr, vsr, vsr, i32) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index bbd4bc80f8..2090c17268 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -736,6 +736,12 @@ XVI8GER4SPP 111011 ... -- ..... ..... 01100011 ..-= @XX3_at xa=3D%xx_xa XVI16GER2S 111011 ... -- ..... ..... 00101011 ..- @XX3_at xa=3D%xx_xa XVI16GER2SPP 111011 ... -- ..... ..... 00101010 ..- @XX3_at xa=3D%xx_xa =20 +XVBF16GER2 111011 ... -- ..... ..... 00110011 ..- @XX3_at xa=3D%xx_xa +XVBF16GER2PP 111011 ... -- ..... ..... 00110010 ..- @XX3_at xa=3D%xx_xa +XVBF16GER2PN 111011 ... -- ..... ..... 10110010 ..- @XX3_at xa=3D%xx_xa +XVBF16GER2NP 111011 ... -- ..... ..... 01110010 ..- @XX3_at xa=3D%xx_xa +XVBF16GER2NN 111011 ... -- ..... ..... 11110010 ..- @XX3_at xa=3D%xx_xa + XVF16GER2 111011 ... -- ..... ..... 00010011 ..- @XX3_at xa=3D%xx_xa XVF16GER2PP 111011 ... -- ..... ..... 00010010 ..- @XX3_at xa=3D%xx_xa XVF16GER2PN 111011 ... -- ..... ..... 10010010 ..- @XX3_at xa=3D%xx_xa diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index a12f11044c..78738924c6 100644 --- a/target/ppc/insn64.decode +++ b/target/ppc/insn64.decode @@ -150,6 +150,17 @@ PMXVI16GER2S 000001 11 1001 -- - - pmsk:2 ------ ..= ...... \ PMXVI16GER2SPP 000001 11 1001 -- - - pmsk:2 ------ ........ \ 111011 ... -- ..... ..... 00101010 ..- @MMIRR_XX3 =20 +PMXVBF16GER2 000001 11 1001 -- - - pmsk:2 ------ ........ \ + 111011 ... -- ..... ..... 00110011 ..- @MMIRR_XX3 +PMXVBF16GER2PP 000001 11 1001 -- - - pmsk:2 ------ ........ \ + 111011 ... -- ..... ..... 00110010 ..- @MMIRR_XX3 +PMXVBF16GER2PN 000001 11 1001 -- - - pmsk:2 ------ ........ \ + 111011 ... -- ..... ..... 10110010 ..- @MMIRR_XX3 +PMXVBF16GER2NP 000001 11 1001 -- - - pmsk:2 ------ ........ \ + 111011 ... -- ..... ..... 01110010 ..- @MMIRR_XX3 +PMXVBF16GER2NN 000001 11 1001 -- - - pmsk:2 ------ ........ \ + 111011 ... -- ..... ..... 11110010 ..- @MMIRR_XX3 + PMXVF16GER2 000001 11 1001 -- - - pmsk:2 ------ ........ \ 111011 ... -- ..... ..... 00010011 ..- @MMIRR_XX3 PMXVF16GER2PP 000001 11 1001 -- - - pmsk:2 ------ ........ \ diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx= -impl.c.inc index 00eed2b1b9..bb5b68ee06 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -2884,6 +2884,12 @@ TRANS64(PMXVI16GER2PP, do_ger_MMIRR_XX3, gen_helper_= XVI16GER2PP) TRANS64(PMXVI16GER2S, do_ger_MMIRR_XX3, gen_helper_XVI16GER2S) TRANS64(PMXVI16GER2SPP, do_ger_MMIRR_XX3, gen_helper_XVI16GER2SPP) =20 +TRANS(XVBF16GER2, do_ger_XX3, gen_helper_XVBF16GER2) +TRANS(XVBF16GER2PP, do_ger_XX3, gen_helper_XVBF16GER2PP) +TRANS(XVBF16GER2PN, do_ger_XX3, gen_helper_XVBF16GER2PN) +TRANS(XVBF16GER2NP, do_ger_XX3, gen_helper_XVBF16GER2NP) +TRANS(XVBF16GER2NN, do_ger_XX3, gen_helper_XVBF16GER2NN) + TRANS(XVF16GER2, do_ger_XX3, gen_helper_XVF16GER2) TRANS(XVF16GER2PP, do_ger_XX3, gen_helper_XVF16GER2PP) TRANS(XVF16GER2PN, do_ger_XX3, gen_helper_XVF16GER2PN) @@ -2902,6 +2908,12 @@ TRANS(XVF64GERPN, do_ger_XX3, gen_helper_XVF64GERPN) TRANS(XVF64GERNP, do_ger_XX3, gen_helper_XVF64GERNP) TRANS(XVF64GERNN, do_ger_XX3, gen_helper_XVF64GERNN) =20 +TRANS64(PMXVBF16GER2, do_ger_MMIRR_XX3, gen_helper_XVBF16GER2) +TRANS64(PMXVBF16GER2PP, do_ger_MMIRR_XX3, gen_helper_XVBF16GER2PP) +TRANS64(PMXVBF16GER2PN, do_ger_MMIRR_XX3, gen_helper_XVBF16GER2PN) +TRANS64(PMXVBF16GER2NP, do_ger_MMIRR_XX3, gen_helper_XVBF16GER2NP) +TRANS64(PMXVBF16GER2NN, do_ger_MMIRR_XX3, gen_helper_XVBF16GER2NN) + TRANS64(PMXVF16GER2, do_ger_MMIRR_XX3, gen_helper_XVF16GER2) TRANS64(PMXVF16GER2PP, do_ger_MMIRR_XX3, gen_helper_XVF16GER2PP) TRANS64(PMXVF16GER2PN, do_ger_MMIRR_XX3, gen_helper_XVF16GER2PN) --=20 2.31.1