[v5] target/arm: Cleanups, new features, new cpus

[PATCH v5 00/24] target/arm: Cleanups, new features, new cpus

Richard Henderson posted 24 patches 3 years, 9 months ago

Diff against v3 v4 v6
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git fetch https://github.com/patchew-project/qemu tags/patchew/20220505185006.200555-1-richard.henderson@linaro.org

Maintainers: Peter Maydell <peter.maydell@linaro.org>, Radoslaw Biernacki <rad@semihalf.com>, Leif Lindholm <leif@nuviainc.com>

There is a newer version of this series

docs/system/arm/emulation.rst |  10 +
docs/system/arm/virt.rst      |   2 +
target/arm/cpregs.h           |  11 +
target/arm/cpu.h              |  23 ++
target/arm/helper.h           |   1 +
target/arm/internals.h        |  16 +
target/arm/syndrome.h         |   5 +
target/arm/a32.decode         |  16 +-
target/arm/t32.decode         |  18 +-
hw/arm/sbsa-ref.c             |   2 +
hw/arm/virt.c                 |   2 +
target/arm/cpu.c              |  66 +++-
target/arm/cpu64.c            | 353 +++++++++++---------
target/arm/cpu_tcg.c          | 227 +++++++++----
target/arm/helper.c           | 600 ++++++++++++++++++++--------------
target/arm/op_helper.c        |  43 +++
target/arm/translate-a64.c    |  18 +
target/arm/translate.c        |  23 ++
18 files changed, 949 insertions(+), 487 deletions(-)

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[PATCH v5 00/24] target/arm: Cleanups, new features, new cpus

Posted by Richard Henderson 3 years, 9 months ago

Changes for v4:
  * Rebase on master, where the second third is upstream.
  * Add ARM_CP_EL3_NO_EL2_C_NZ flag, and use that in the
    two cpregs called out by rule RJFFP that become constant
    but not zero.
  * Set SCTLR_EL1.TSCXT for user-only.

Patches lacking review:
  01-target-arm-Handle-cpreg-registration-for-missing-.patch
  02-target-arm-Drop-EL3-no-EL2-fallbacks.patch
  20-target-arm-Enable-FEAT_CSV2_2-for-cpu-max.patch


r~


Richard Henderson (24):
  target/arm: Handle cpreg registration for missing EL
  target/arm: Drop EL3 no EL2 fallbacks
  target/arm: Merge zcr reginfo
  target/arm: Adjust definition of CONTEXTIDR_EL2
  target/arm: Move cortex impdef sysregs to cpu_tcg.c
  target/arm: Update qemu-system-arm -cpu max to cortex-a57
  target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
  target/arm: Split out aa32_max_features
  target/arm: Annotate arm_max_initfn with FEAT identifiers
  target/arm: Use field names for manipulating EL2 and EL3 modes
  target/arm: Enable FEAT_Debugv8p2 for -cpu max
  target/arm: Enable FEAT_Debugv8p4 for -cpu max
  target/arm: Add minimal RAS registers
  target/arm: Enable SCR and HCR bits for RAS
  target/arm: Implement virtual SError exceptions
  target/arm: Implement ESB instruction
  target/arm: Enable FEAT_RAS for -cpu max
  target/arm: Enable FEAT_IESB for -cpu max
  target/arm: Enable FEAT_CSV2 for -cpu max
  target/arm: Enable FEAT_CSV2_2 for -cpu max
  target/arm: Enable FEAT_CSV3 for -cpu max
  target/arm: Enable FEAT_DGH for -cpu max
  target/arm: Define cortex-a76
  target/arm: Define neoverse-n1

 docs/system/arm/emulation.rst |  10 +
 docs/system/arm/virt.rst      |   2 +
 target/arm/cpregs.h           |  11 +
 target/arm/cpu.h              |  23 ++
 target/arm/helper.h           |   1 +
 target/arm/internals.h        |  16 +
 target/arm/syndrome.h         |   5 +
 target/arm/a32.decode         |  16 +-
 target/arm/t32.decode         |  18 +-
 hw/arm/sbsa-ref.c             |   2 +
 hw/arm/virt.c                 |   2 +
 target/arm/cpu.c              |  66 +++-
 target/arm/cpu64.c            | 353 +++++++++++---------
 target/arm/cpu_tcg.c          | 227 +++++++++----
 target/arm/helper.c           | 600 ++++++++++++++++++++--------------
 target/arm/op_helper.c        |  43 +++
 target/arm/translate-a64.c    |  18 +
 target/arm/translate.c        |  23 ++
 18 files changed, 949 insertions(+), 487 deletions(-)

-- 
2.34.1