It's not possible to provide the guest with the Security extensions

(TrustZone) when using KVM or HVF, because the hardware

virtualization extensions don't permit running EL3 guest code.

However, we weren't checking for this combination, with the result

that QEMU would assert if you tried it:

$ qemu-system-aarch64 -enable-kvm -machine virt,secure=on -cpu host -display none

Unexpected error in object_property_find_err() at ../../qom/object.c:1304:

qemu-system-aarch64: Property 'host-arm-cpu.secure-memory' not found

Aborted

Check for this combination of options and report an error, in the

same way we already do for attempts to give a KVM or HVF guest the

Virtualization or MTE extensions. Now we will report:

qemu-system-aarch64: mach-virt: KVM does not support providing Security extensions (TrustZone) to the guest CPU

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/961

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20220404155301.566542-1-peter.maydell@linaro.org

---

hw/arm/virt.c | 7 +++++++

1 file changed, 7 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/virt.c

+++ b/hw/arm/virt.c

@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)

exit(1);

}

+ if (vms->secure && (kvm_enabled() || hvf_enabled())) {

+ error_report("mach-virt: %s does not support providing "

+ "Security extensions (TrustZone) to the guest CPU",

+ kvm_enabled() ? "KVM" : "HVF");

+ exit(1);

+ }

+

if (vms->virt && (kvm_enabled() || hvf_enabled())) {

error_report("mach-virt: %s does not support providing "

"Virtualization extensions to the guest CPU",

--

2.25.1

From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>

Break out header file to allow embedding of the the TTC.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Luc Michel <luc@lmichel.fr>

Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>

Message-id: 20220331222017.2914409-2-edgar.iglesias@gmail.com

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

include/hw/timer/cadence_ttc.h | 54 ++++++++++++++++++++++++++++++++++

hw/timer/cadence_ttc.c | 32 ++------------------

2 files changed, 56 insertions(+), 30 deletions(-)

create mode 100644 include/hw/timer/cadence_ttc.h

diff --git a/include/hw/timer/cadence_ttc.h b/include/hw/timer/cadence_ttc.h

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/include/hw/timer/cadence_ttc.h

@@ -XXX,XX +XXX,XX @@

+/*

+ * Xilinx Zynq cadence TTC model

+ *

+ * Copyright (c) 2011 Xilinx Inc.

+ * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)

+ * Copyright (c) 2012 PetaLogix Pty Ltd.

+ * Written By Haibing Ma

+ * M. Habib

+ *

+ * This program is free software; you can redistribute it and/or

+ * modify it under the terms of the GNU General Public License

+ * as published by the Free Software Foundation; either version

+ * 2 of the License, or (at your option) any later version.

+ *

+ * You should have received a copy of the GNU General Public License along

+ * with this program; if not, see <http://www.gnu.org/licenses/>.

+ */

+#ifndef HW_TIMER_CADENCE_TTC_H

+#define HW_TIMER_CADENCE_TTC_H

+

+#include "hw/sysbus.h"

+#include "qemu/timer.h"

+

+typedef struct {

+ QEMUTimer *timer;

+ int freq;

+

+ uint32_t reg_clock;

+ uint32_t reg_count;

+ uint32_t reg_value;

+ uint16_t reg_interval;

+ uint16_t reg_match[3];

+ uint32_t reg_intr;

+ uint32_t reg_intr_en;

+ uint32_t reg_event_ctrl;

+ uint32_t reg_event;

+

+ uint64_t cpu_time;

+ unsigned int cpu_time_valid;

+

+ qemu_irq irq;

+} CadenceTimerState;

+

+#define TYPE_CADENCE_TTC "cadence_ttc"

+OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)

+

+struct CadenceTTCState {

+ SysBusDevice parent_obj;

+

+ MemoryRegion iomem;

+ CadenceTimerState timer[3];

+};

+

+#endif

diff --git a/hw/timer/cadence_ttc.c b/hw/timer/cadence_ttc.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/timer/cadence_ttc.c

+++ b/hw/timer/cadence_ttc.c

@@ -XXX,XX +XXX,XX @@

#include "qemu/timer.h"

#include "qom/object.h"

+#include "hw/timer/cadence_ttc.h"

+

#ifdef CADENCE_TTC_ERR_DEBUG

#define DB_PRINT(...) do { \

fprintf(stderr, ": %s: ", __func__); \

@@ -XXX,XX +XXX,XX @@

#define CLOCK_CTRL_PS_EN 0x00000001

#define CLOCK_CTRL_PS_V 0x0000001e

-typedef struct {

- QEMUTimer *timer;

- int freq;

-

- uint32_t reg_clock;

- uint32_t reg_count;

- uint32_t reg_value;

- uint16_t reg_interval;

- uint16_t reg_match[3];

- uint32_t reg_intr;

- uint32_t reg_intr_en;

- uint32_t reg_event_ctrl;

- uint32_t reg_event;

-

- uint64_t cpu_time;

- unsigned int cpu_time_valid;

-

- qemu_irq irq;

-} CadenceTimerState;

-

-#define TYPE_CADENCE_TTC "cadence_ttc"

-OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)

-

-struct CadenceTTCState {

- SysBusDevice parent_obj;

-

- MemoryRegion iomem;

- CadenceTimerState timer[3];

-};

-

static void cadence_timer_update(CadenceTimerState *s)

{

qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en));

--

2.25.1