1 | First arm pullreq for 7.1. The bulk of this is the qemu_split_irq | 1 | Just flushing my target-arm queue since I won't be working next week :-) |
---|---|---|---|
2 | removal. | ||
3 | 2 | ||
4 | I have enough stuff in my to-review queue that I expect to do another | ||
5 | pullreq early next week, but 31 patches is enough to not hang on to. | ||
6 | |||
7 | thanks | ||
8 | -- PMM | 3 | -- PMM |
9 | 4 | ||
10 | The following changes since commit 9c125d17e9402c232c46610802e5931b3639d77b: | 5 | The following changes since commit b3cd3b5a66f0dddfe3d5ba2bef13cd4f5b89cde9: |
11 | 6 | ||
12 | Merge tag 'pull-tcg-20220420' of https://gitlab.com/rth7680/qemu into staging (2022-04-20 16:43:11 -0700) | 7 | Merge tag 'pull-riscv-to-apply-20220610' of github.com:alistair23/qemu into staging (2022-06-09 22:08:27 -0700) |
13 | 8 | ||
14 | are available in the Git repository at: | 9 | are available in the Git repository at: |
15 | 10 | ||
16 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220421 | 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220610 |
17 | 12 | ||
18 | for you to fetch changes up to 5b415dd61bdbf61fb4be0e9f1a7172b8bce682c6: | 13 | for you to fetch changes up to 90c072e063737e9e8f431489bbd334452f89056e: |
19 | 14 | ||
20 | hw/arm: Use bit fields for NPCM7XX PWRON STRAPs (2022-04-21 11:37:05 +0100) | 15 | semihosting/config: Merge --semihosting-config option groups (2022-06-10 14:32:36 +0100) |
21 | 16 | ||
22 | ---------------------------------------------------------------- | 17 | ---------------------------------------------------------------- |
23 | target-arm queue: | 18 | * refactor exception routing code |
24 | * hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF | 19 | * fix SCR_EL3 RAO/RAZ bits |
25 | * versal: Add the Cortex-R5s in the Real-Time Processing Unit (RPU) subsystem | 20 | * gdbstub: Don't use GDB syscalls if no GDB is attached |
26 | * versal: model enough of the Clock/Reset Low-power domain (CRL) to allow control of the Cortex-R5s | 21 | * semihosting/config: Merge --semihosting-config option groups |
27 | * xlnx-zynqmp: Connect 4 TTC timers | 22 | * tests/qtest: Reduce npcm7xx_sdhci test image size |
28 | * exynos4210: Refactor GIC/combiner code to stop using qemu_split_irq | ||
29 | * realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ' | ||
30 | * stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ' | ||
31 | * hw/core/irq: remove unused 'qemu_irq_split' function | ||
32 | * npcm7xx: use symbolic constants for PWRON STRAP bit fields | ||
33 | * virt: document impact of gic-version on max CPUs | ||
34 | 23 | ||
35 | ---------------------------------------------------------------- | 24 | ---------------------------------------------------------------- |
36 | Edgar E. Iglesias (6): | 25 | Hao Wu (1): |
37 | timer: cadence_ttc: Break out header file to allow embedding | 26 | tests/qtest: Reduce npcm7xx_sdhci test image size |
38 | hw/arm/xlnx-zynqmp: Connect 4 TTC timers | ||
39 | hw/arm: versal: Create an APU CPU Cluster | ||
40 | hw/arm: versal: Add the Cortex-R5Fs | ||
41 | hw/misc: Add a model of the Xilinx Versal CRL | ||
42 | hw/arm: versal: Connect the CRL | ||
43 | 27 | ||
44 | Hao Wu (2): | 28 | Peter Maydell (2): |
45 | hw/misc: Add PWRON STRAP bit fields in GCR module | 29 | gdbstub: Don't use GDB syscalls if no GDB is attached |
46 | hw/arm: Use bit fields for NPCM7XX PWRON STRAPs | 30 | semihosting/config: Merge --semihosting-config option groups |
47 | 31 | ||
48 | Heinrich Schuchardt (1): | 32 | Richard Henderson (25): |
49 | hw/arm/virt: impact of gic-version on max CPUs | 33 | target/arm: Mark exception helpers as noreturn |
34 | target/arm: Add coproc parameter to syn_fp_access_trap | ||
35 | target/arm: Move exception_target_el out of line | ||
36 | target/arm: Move arm_singlestep_active out of line | ||
37 | target/arm: Move arm_generate_debug_exceptions out of line | ||
38 | target/arm: Use is_a64 in arm_generate_debug_exceptions | ||
39 | target/arm: Move exception_bkpt_insn to debug_helper.c | ||
40 | target/arm: Move arm_debug_exception_fsr to debug_helper.c | ||
41 | target/arm: Rename helper_exception_with_syndrome | ||
42 | target/arm: Introduce gen_exception_insn_el_v | ||
43 | target/arm: Rename gen_exception_insn to gen_exception_insn_el | ||
44 | target/arm: Introduce gen_exception_insn | ||
45 | target/arm: Create helper_exception_swstep | ||
46 | target/arm: Remove TBFLAG_ANY.DEBUG_TARGET_EL | ||
47 | target/arm: Move gen_exception to translate.c | ||
48 | target/arm: Rename gen_exception to gen_exception_el | ||
49 | target/arm: Introduce gen_exception | ||
50 | target/arm: Introduce gen_exception_el_v | ||
51 | target/arm: Introduce helper_exception_with_syndrome | ||
52 | target/arm: Remove default_exception_el | ||
53 | target/arm: Create raise_exception_debug | ||
54 | target/arm: Move arm_debug_target_el to debug_helper.c | ||
55 | target/arm: Fix Secure PL1 tests in fp_exception_el | ||
56 | target/arm: Adjust format test in scr_write | ||
57 | target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12] | ||
50 | 58 | ||
51 | Peter Maydell (19): | 59 | target/arm/cpu.h | 133 ++--------------------- |
52 | hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF | 60 | target/arm/helper.h | 8 +- |
53 | hw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom OR-gate device | 61 | target/arm/internals.h | 43 +------- |
54 | hw/intc/exynos4210_gic: Remove unused TYPE_EXYNOS4210_IRQ_GATE | 62 | target/arm/syndrome.h | 7 +- |
55 | hw/arm/exynos4210: Put a9mpcore device into state struct | 63 | target/arm/translate.h | 43 ++------ |
56 | hw/arm/exynos4210: Drop int_gic_irq[] from Exynos4210Irq struct | 64 | gdbstub.c | 14 ++- |
57 | hw/arm/exynos4210: Coalesce board_irqs and irq_table | 65 | semihosting/config.c | 1 + |
58 | hw/arm/exynos4210: Fix code style nit in combiner_grp_to_gic_id[] | 66 | target/arm/debug_helper.c | 220 +++++++++++++++++++++++++++++++++++++-- |
59 | hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.c | 67 | target/arm/helper.c | 53 ++++------ |
60 | hw/arm/exynos4210: Put external GIC into state struct | 68 | target/arm/op_helper.c | 52 +++++---- |
61 | hw/arm/exynos4210: Drop ext_gic_irq[] from Exynos4210Irq struct | 69 | target/arm/translate-a64.c | 34 +++--- |
62 | hw/arm/exynos4210: Move exynos4210_combiner_get_gpioin() into exynos4210.c | 70 | target/arm/translate-m-nocp.c | 15 ++- |
63 | hw/arm/exynos4210: Delete unused macro definitions | 71 | target/arm/translate-mve.c | 3 +- |
64 | hw/arm/exynos4210: Use TYPE_SPLIT_IRQ in exynos4210_init_board_irqs() | 72 | target/arm/translate-vfp.c | 18 +++- |
65 | hw/arm/exynos4210: Fill in irq_table[] for internal-combiner-only IRQ lines | 73 | target/arm/translate.c | 106 ++++++++++--------- |
66 | hw/arm/exynos4210: Connect MCT_G0 and MCT_G1 to both combiners | 74 | tests/qtest/npcm7xx_sdhci-test.c | 2 +- |
67 | hw/arm/exynos4210: Don't connect multiple lines to external GIC inputs | 75 | 16 files changed, 390 insertions(+), 362 deletions(-) |
68 | hw/arm/exynos4210: Fold combiner splits into exynos4210_init_board_irqs() | ||
69 | hw/arm/exynos4210: Put combiners into state struct | ||
70 | hw/arm/exynos4210: Drop Exynos4210Irq struct | ||
71 | |||
72 | Zongyuan Li (3): | ||
73 | hw/arm/realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ' | ||
74 | hw/arm/stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ' | ||
75 | hw/core/irq: remove unused 'qemu_irq_split' function | ||
76 | |||
77 | docs/system/arm/virt.rst | 4 +- | ||
78 | include/hw/arm/exynos4210.h | 50 ++-- | ||
79 | include/hw/arm/xlnx-versal.h | 16 ++ | ||
80 | include/hw/arm/xlnx-zynqmp.h | 4 + | ||
81 | include/hw/intc/exynos4210_combiner.h | 57 +++++ | ||
82 | include/hw/intc/exynos4210_gic.h | 43 ++++ | ||
83 | include/hw/irq.h | 5 - | ||
84 | include/hw/misc/npcm7xx_gcr.h | 30 +++ | ||
85 | include/hw/misc/xlnx-versal-crl.h | 235 +++++++++++++++++++ | ||
86 | include/hw/timer/cadence_ttc.h | 54 +++++ | ||
87 | hw/arm/exynos4210.c | 430 ++++++++++++++++++++++++++++++---- | ||
88 | hw/arm/npcm7xx_boards.c | 24 +- | ||
89 | hw/arm/realview.c | 33 ++- | ||
90 | hw/arm/stellaris.c | 15 +- | ||
91 | hw/arm/virt.c | 7 + | ||
92 | hw/arm/xlnx-versal-virt.c | 6 +- | ||
93 | hw/arm/xlnx-versal.c | 99 +++++++- | ||
94 | hw/arm/xlnx-zynqmp.c | 22 ++ | ||
95 | hw/core/irq.c | 15 -- | ||
96 | hw/intc/exynos4210_combiner.c | 108 +-------- | ||
97 | hw/intc/exynos4210_gic.c | 344 +-------------------------- | ||
98 | hw/misc/xlnx-versal-crl.c | 421 +++++++++++++++++++++++++++++++++ | ||
99 | hw/timer/cadence_ttc.c | 32 +-- | ||
100 | MAINTAINERS | 2 +- | ||
101 | hw/misc/meson.build | 1 + | ||
102 | 25 files changed, 1457 insertions(+), 600 deletions(-) | ||
103 | create mode 100644 include/hw/intc/exynos4210_combiner.h | ||
104 | create mode 100644 include/hw/intc/exynos4210_gic.h | ||
105 | create mode 100644 include/hw/misc/xlnx-versal-crl.h | ||
106 | create mode 100644 include/hw/timer/cadence_ttc.h | ||
107 | create mode 100644 hw/misc/xlnx-versal-crl.c | diff view generated by jsdifflib |
1 | From: Zongyuan Li <zongyuan.li@smartx.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Message-id: 20220324181557.203805-3-zongyuan.li@smartx.com | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20220609202901.1177572-2-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 7 | --- |
8 | hw/arm/stellaris.c | 15 +++++++++++++-- | 8 | target/arm/helper.h | 6 +++--- |
9 | 1 file changed, 13 insertions(+), 2 deletions(-) | 9 | 1 file changed, 3 insertions(+), 3 deletions(-) |
10 | 10 | ||
11 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c | 11 | diff --git a/target/arm/helper.h b/target/arm/helper.h |
12 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/arm/stellaris.c | 13 | --- a/target/arm/helper.h |
14 | +++ b/hw/arm/stellaris.c | 14 | +++ b/target/arm/helper.h |
15 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32) |
16 | 16 | ||
17 | #include "qemu/osdep.h" | 17 | DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, |
18 | #include "qapi/error.h" | 18 | i32, i32, i32, i32) |
19 | +#include "hw/core/split-irq.h" | 19 | -DEF_HELPER_2(exception_internal, void, env, i32) |
20 | #include "hw/sysbus.h" | 20 | -DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32) |
21 | #include "hw/sd/sd.h" | 21 | -DEF_HELPER_2(exception_bkpt_insn, void, env, i32) |
22 | #include "hw/ssi/ssi.h" | 22 | +DEF_HELPER_2(exception_internal, noreturn, env, i32) |
23 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) | 23 | +DEF_HELPER_4(exception_with_syndrome, noreturn, env, i32, i32, i32) |
24 | DeviceState *ssddev; | 24 | +DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) |
25 | DriveInfo *dinfo; | 25 | DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) |
26 | DeviceState *carddev; | 26 | DEF_HELPER_1(setend, void, env) |
27 | + DeviceState *gpio_d_splitter; | 27 | DEF_HELPER_2(wfi, void, env, i32) |
28 | BlockBackend *blk; | ||
29 | |||
30 | /* | ||
31 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) | ||
32 | &error_fatal); | ||
33 | |||
34 | ssddev = ssi_create_peripheral(bus, "ssd0323"); | ||
35 | - gpio_out[GPIO_D][0] = qemu_irq_split( | ||
36 | - qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0), | ||
37 | + | ||
38 | + gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ); | ||
39 | + qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2); | ||
40 | + qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal); | ||
41 | + qdev_connect_gpio_out( | ||
42 | + gpio_d_splitter, 0, | ||
43 | + qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0)); | ||
44 | + qdev_connect_gpio_out( | ||
45 | + gpio_d_splitter, 1, | ||
46 | qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); | ||
47 | + gpio_out[GPIO_D][0] = qdev_get_gpio_in(gpio_d_splitter, 0); | ||
48 | + | ||
49 | gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); | ||
50 | |||
51 | /* Make sure the select pin is high. */ | ||
52 | -- | 28 | -- |
53 | 2.25.1 | 29 | 2.25.1 | diff view generated by jsdifflib |
1 | Switch the creation of the combiner devices to the new-style | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | "embedded in state struct" approach, so we can easily refer | ||
3 | to the object elsewhere during realize. | ||
4 | 2 | ||
3 | With ARMv8, this field is always RES0. | ||
4 | With ARMv7, targeting EL2 and TA=0, it is always 0xA. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220609202901.1177572-3-richard.henderson@linaro.org | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20220404154658.565020-18-peter.maydell@linaro.org | ||
8 | --- | 10 | --- |
9 | include/hw/arm/exynos4210.h | 3 ++ | 11 | target/arm/syndrome.h | 7 ++++--- |
10 | include/hw/intc/exynos4210_combiner.h | 57 +++++++++++++++++++++++++++ | 12 | target/arm/translate-a64.c | 3 ++- |
11 | hw/arm/exynos4210.c | 20 +++++----- | 13 | target/arm/translate-vfp.c | 14 ++++++++++++-- |
12 | hw/intc/exynos4210_combiner.c | 31 +-------------- | 14 | 3 files changed, 18 insertions(+), 6 deletions(-) |
13 | 4 files changed, 72 insertions(+), 39 deletions(-) | ||
14 | create mode 100644 include/hw/intc/exynos4210_combiner.h | ||
15 | 15 | ||
16 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | 16 | diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h |
17 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/arm/exynos4210.h | 18 | --- a/target/arm/syndrome.h |
19 | +++ b/include/hw/arm/exynos4210.h | 19 | +++ b/target/arm/syndrome.h |
20 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, |
21 | #include "hw/sysbus.h" | 21 | | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; |
22 | #include "hw/cpu/a9mpcore.h" | 22 | } |
23 | #include "hw/intc/exynos4210_gic.h" | 23 | |
24 | +#include "hw/intc/exynos4210_combiner.h" | 24 | -static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) |
25 | #include "hw/core/split-irq.h" | 25 | +static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit, |
26 | #include "target/arm/cpu-qom.h" | 26 | + int coproc) |
27 | #include "qom/object.h" | 27 | { |
28 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { | 28 | - /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 coproc == 0xa */ |
29 | qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; | 29 | + /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 */ |
30 | A9MPPrivState a9mpcore; | 30 | return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) |
31 | Exynos4210GicState ext_gic; | 31 | | (is_16bit ? 0 : ARM_EL_IL) |
32 | + Exynos4210CombinerState int_combiner; | 32 | - | (cv << 24) | (cond << 20) | 0xa; |
33 | + Exynos4210CombinerState ext_combiner; | 33 | + | (cv << 24) | (cond << 20) | coproc; |
34 | SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS]; | 34 | } |
35 | }; | 35 | |
36 | 36 | static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit) | |
37 | diff --git a/include/hw/intc/exynos4210_combiner.h b/include/hw/intc/exynos4210_combiner.h | 37 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
38 | new file mode 100644 | 38 | index XXXXXXX..XXXXXXX 100644 |
39 | index XXXXXXX..XXXXXXX | 39 | --- a/target/arm/translate-a64.c |
40 | --- /dev/null | 40 | +++ b/target/arm/translate-a64.c |
41 | +++ b/include/hw/intc/exynos4210_combiner.h | 41 | @@ -XXX,XX +XXX,XX @@ static bool fp_access_check(DisasContext *s) |
42 | @@ -XXX,XX +XXX,XX @@ | 42 | s->fp_access_checked = true; |
43 | +/* | 43 | |
44 | + * Samsung exynos4210 Interrupt Combiner | 44 | gen_exception_insn(s, s->pc_curr, EXCP_UDEF, |
45 | + * | 45 | - syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); |
46 | + * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. | 46 | + syn_fp_access_trap(1, 0xe, false, 0), |
47 | + * All rights reserved. | 47 | + s->fp_excp_el); |
48 | + * | 48 | return false; |
49 | + * Evgeny Voevodin <e.voevodin@samsung.com> | 49 | } |
50 | + * | 50 | s->fp_access_checked = true; |
51 | + * This program is free software; you can redistribute it and/or modify it | 51 | diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c |
52 | + * under the terms of the GNU General Public License as published by the | 52 | index XXXXXXX..XXXXXXX 100644 |
53 | + * Free Software Foundation; either version 2 of the License, or (at your | 53 | --- a/target/arm/translate-vfp.c |
54 | + * option) any later version. | 54 | +++ b/target/arm/translate-vfp.c |
55 | + * | 55 | @@ -XXX,XX +XXX,XX @@ static void gen_update_fp_context(DisasContext *s) |
56 | + * This program is distributed in the hope that it will be useful, | 56 | static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled) |
57 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | 57 | { |
58 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | 58 | if (s->fp_excp_el) { |
59 | + * See the GNU General Public License for more details. | 59 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, |
60 | + * | 60 | - syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); |
61 | + * You should have received a copy of the GNU General Public License along | 61 | + /* |
62 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | 62 | + * The full syndrome is only used for HSR when HCPTR traps: |
63 | + */ | 63 | + * For v8, when TA==0, coproc is RES0. |
64 | + * For v7, any use of a Floating-point instruction or access | ||
65 | + * to a Floating-point Extension register that is trapped to | ||
66 | + * Hyp mode because of a trap configured in the HCPTR sets | ||
67 | + * this field to 0xA. | ||
68 | + */ | ||
69 | + int coproc = arm_dc_feature(s, ARM_FEATURE_V8) ? 0 : 0xa; | ||
70 | + uint32_t syn = syn_fp_access_trap(1, 0xe, false, coproc); | ||
64 | + | 71 | + |
65 | +#ifndef HW_INTC_EXYNOS4210_COMBINER | 72 | + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el); |
66 | +#define HW_INTC_EXYNOS4210_COMBINER | 73 | return false; |
67 | + | ||
68 | +#include "hw/sysbus.h" | ||
69 | + | ||
70 | +/* | ||
71 | + * State for each output signal of internal combiner | ||
72 | + */ | ||
73 | +typedef struct CombinerGroupState { | ||
74 | + uint8_t src_mask; /* 1 - source enabled, 0 - disabled */ | ||
75 | + uint8_t src_pending; /* Pending source interrupts before masking */ | ||
76 | +} CombinerGroupState; | ||
77 | + | ||
78 | +#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner" | ||
79 | +OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210CombinerState, EXYNOS4210_COMBINER) | ||
80 | + | ||
81 | +/* Number of groups and total number of interrupts for the internal combiner */ | ||
82 | +#define IIC_NGRP 64 | ||
83 | +#define IIC_NIRQ (IIC_NGRP * 8) | ||
84 | +#define IIC_REGSET_SIZE 0x41 | ||
85 | + | ||
86 | +struct Exynos4210CombinerState { | ||
87 | + SysBusDevice parent_obj; | ||
88 | + | ||
89 | + MemoryRegion iomem; | ||
90 | + | ||
91 | + struct CombinerGroupState group[IIC_NGRP]; | ||
92 | + uint32_t reg_set[IIC_REGSET_SIZE]; | ||
93 | + uint32_t icipsr[2]; | ||
94 | + uint32_t external; /* 1 means that this combiner is external */ | ||
95 | + | ||
96 | + qemu_irq output_irq[IIC_NGRP]; | ||
97 | +}; | ||
98 | + | ||
99 | +#endif | ||
100 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
101 | index XXXXXXX..XXXXXXX 100644 | ||
102 | --- a/hw/arm/exynos4210.c | ||
103 | +++ b/hw/arm/exynos4210.c | ||
104 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
105 | } | 74 | } |
106 | 75 | ||
107 | /* Internal Interrupt Combiner */ | ||
108 | - dev = qdev_new("exynos4210.combiner"); | ||
109 | - busdev = SYS_BUS_DEVICE(dev); | ||
110 | - sysbus_realize_and_unref(busdev, &error_fatal); | ||
111 | + busdev = SYS_BUS_DEVICE(&s->int_combiner); | ||
112 | + sysbus_realize(busdev, &error_fatal); | ||
113 | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { | ||
114 | sysbus_connect_irq(busdev, n, | ||
115 | qdev_get_gpio_in(DEVICE(&s->a9mpcore), n)); | ||
116 | } | ||
117 | - exynos4210_combiner_get_gpioin(&s->irqs, dev, 0); | ||
118 | + exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->int_combiner), 0); | ||
119 | sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); | ||
120 | |||
121 | /* External Interrupt Combiner */ | ||
122 | - dev = qdev_new("exynos4210.combiner"); | ||
123 | - qdev_prop_set_uint32(dev, "external", 1); | ||
124 | - busdev = SYS_BUS_DEVICE(dev); | ||
125 | - sysbus_realize_and_unref(busdev, &error_fatal); | ||
126 | + qdev_prop_set_uint32(DEVICE(&s->ext_combiner), "external", 1); | ||
127 | + busdev = SYS_BUS_DEVICE(&s->ext_combiner); | ||
128 | + sysbus_realize(busdev, &error_fatal); | ||
129 | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { | ||
130 | sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n)); | ||
131 | } | ||
132 | - exynos4210_combiner_get_gpioin(&s->irqs, dev, 1); | ||
133 | + exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->ext_combiner), 1); | ||
134 | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); | ||
135 | |||
136 | /* Initialize board IRQs. */ | ||
137 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj) | ||
138 | |||
139 | object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); | ||
140 | object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC); | ||
141 | + object_initialize_child(obj, "int-combiner", &s->int_combiner, | ||
142 | + TYPE_EXYNOS4210_COMBINER); | ||
143 | + object_initialize_child(obj, "ext-combiner", &s->ext_combiner, | ||
144 | + TYPE_EXYNOS4210_COMBINER); | ||
145 | } | ||
146 | |||
147 | static void exynos4210_class_init(ObjectClass *klass, void *data) | ||
148 | diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c | ||
149 | index XXXXXXX..XXXXXXX 100644 | ||
150 | --- a/hw/intc/exynos4210_combiner.c | ||
151 | +++ b/hw/intc/exynos4210_combiner.c | ||
152 | @@ -XXX,XX +XXX,XX @@ | ||
153 | #include "hw/sysbus.h" | ||
154 | #include "migration/vmstate.h" | ||
155 | #include "qemu/module.h" | ||
156 | - | ||
157 | +#include "hw/intc/exynos4210_combiner.h" | ||
158 | #include "hw/arm/exynos4210.h" | ||
159 | #include "hw/hw.h" | ||
160 | #include "hw/irq.h" | ||
161 | @@ -XXX,XX +XXX,XX @@ | ||
162 | #define DPRINTF(fmt, ...) do {} while (0) | ||
163 | #endif | ||
164 | |||
165 | -#define IIC_NGRP 64 /* Internal Interrupt Combiner | ||
166 | - Groups number */ | ||
167 | -#define IIC_NIRQ (IIC_NGRP * 8)/* Internal Interrupt Combiner | ||
168 | - Interrupts number */ | ||
169 | #define IIC_REGION_SIZE 0x108 /* Size of memory mapped region */ | ||
170 | -#define IIC_REGSET_SIZE 0x41 | ||
171 | - | ||
172 | -/* | ||
173 | - * State for each output signal of internal combiner | ||
174 | - */ | ||
175 | -typedef struct CombinerGroupState { | ||
176 | - uint8_t src_mask; /* 1 - source enabled, 0 - disabled */ | ||
177 | - uint8_t src_pending; /* Pending source interrupts before masking */ | ||
178 | -} CombinerGroupState; | ||
179 | - | ||
180 | -#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner" | ||
181 | -OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210CombinerState, EXYNOS4210_COMBINER) | ||
182 | - | ||
183 | -struct Exynos4210CombinerState { | ||
184 | - SysBusDevice parent_obj; | ||
185 | - | ||
186 | - MemoryRegion iomem; | ||
187 | - | ||
188 | - struct CombinerGroupState group[IIC_NGRP]; | ||
189 | - uint32_t reg_set[IIC_REGSET_SIZE]; | ||
190 | - uint32_t icipsr[2]; | ||
191 | - uint32_t external; /* 1 means that this combiner is external */ | ||
192 | - | ||
193 | - qemu_irq output_irq[IIC_NGRP]; | ||
194 | -}; | ||
195 | |||
196 | static const VMStateDescription vmstate_exynos4210_combiner_group_state = { | ||
197 | .name = "exynos4210.combiner.groupstate", | ||
198 | -- | 76 | -- |
199 | 2.25.1 | 77 | 2.25.1 | diff view generated by jsdifflib |
1 | It's not possible to provide the guest with the Security extensions | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | (TrustZone) when using KVM or HVF, because the hardware | ||
3 | virtualization extensions don't permit running EL3 guest code. | ||
4 | However, we weren't checking for this combination, with the result | ||
5 | that QEMU would assert if you tried it: | ||
6 | 2 | ||
7 | $ qemu-system-aarch64 -enable-kvm -machine virt,secure=on -cpu host -display none | 3 | Move the function to op_helper.c, near raise_exception. |
8 | Unexpected error in object_property_find_err() at ../../qom/object.c:1304: | ||
9 | qemu-system-aarch64: Property 'host-arm-cpu.secure-memory' not found | ||
10 | Aborted | ||
11 | 4 | ||
12 | Check for this combination of options and report an error, in the | 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
13 | same way we already do for attempts to give a KVM or HVF guest the | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
14 | Virtualization or MTE extensions. Now we will report: | 7 | Message-id: 20220609202901.1177572-4-richard.henderson@linaro.org |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | target/arm/internals.h | 16 +--------------- | ||
11 | target/arm/op_helper.c | 15 +++++++++++++++ | ||
12 | 2 files changed, 16 insertions(+), 15 deletions(-) | ||
15 | 13 | ||
16 | qemu-system-aarch64: mach-virt: KVM does not support providing Security extensions (TrustZone) to the guest CPU | 14 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
17 | |||
18 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/961 | ||
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
20 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
21 | Message-id: 20220404155301.566542-1-peter.maydell@linaro.org | ||
22 | --- | ||
23 | hw/arm/virt.c | 7 +++++++ | ||
24 | 1 file changed, 7 insertions(+) | ||
25 | |||
26 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
28 | --- a/hw/arm/virt.c | 16 | --- a/target/arm/internals.h |
29 | +++ b/hw/arm/virt.c | 17 | +++ b/target/arm/internals.h |
30 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | 18 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, |
31 | exit(1); | 19 | int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx); |
32 | } | 20 | int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx); |
33 | 21 | ||
34 | + if (vms->secure && (kvm_enabled() || hvf_enabled())) { | 22 | -static inline int exception_target_el(CPUARMState *env) |
35 | + error_report("mach-virt: %s does not support providing " | 23 | -{ |
36 | + "Security extensions (TrustZone) to the guest CPU", | 24 | - int target_el = MAX(1, arm_current_el(env)); |
37 | + kvm_enabled() ? "KVM" : "HVF"); | 25 | - |
38 | + exit(1); | 26 | - /* |
27 | - * No such thing as secure EL1 if EL3 is aarch32, | ||
28 | - * so update the target EL to EL3 in this case. | ||
29 | - */ | ||
30 | - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { | ||
31 | - target_el = 3; | ||
32 | - } | ||
33 | - | ||
34 | - return target_el; | ||
35 | -} | ||
36 | - | ||
37 | /* Determine if allocation tags are available. */ | ||
38 | static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, | ||
39 | uint64_t sctlr) | ||
40 | @@ -XXX,XX +XXX,XX @@ void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); | ||
41 | bool el_is_in_host(CPUARMState *env, int el); | ||
42 | |||
43 | void aa32_max_features(ARMCPU *cpu); | ||
44 | +int exception_target_el(CPUARMState *env); | ||
45 | |||
46 | /* Powers of 2 for sve_vq_map et al. */ | ||
47 | #define SVE_VQ_POW2_MAP \ | ||
48 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/target/arm/op_helper.c | ||
51 | +++ b/target/arm/op_helper.c | ||
52 | @@ -XXX,XX +XXX,XX @@ | ||
53 | #define SIGNBIT (uint32_t)0x80000000 | ||
54 | #define SIGNBIT64 ((uint64_t)1 << 63) | ||
55 | |||
56 | +int exception_target_el(CPUARMState *env) | ||
57 | +{ | ||
58 | + int target_el = MAX(1, arm_current_el(env)); | ||
59 | + | ||
60 | + /* | ||
61 | + * No such thing as secure EL1 if EL3 is aarch32, | ||
62 | + * so update the target EL to EL3 in this case. | ||
63 | + */ | ||
64 | + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { | ||
65 | + target_el = 3; | ||
39 | + } | 66 | + } |
40 | + | 67 | + |
41 | if (vms->virt && (kvm_enabled() || hvf_enabled())) { | 68 | + return target_el; |
42 | error_report("mach-virt: %s does not support providing " | 69 | +} |
43 | "Virtualization extensions to the guest CPU", | 70 | + |
71 | void raise_exception(CPUARMState *env, uint32_t excp, | ||
72 | uint32_t syndrome, uint32_t target_el) | ||
73 | { | ||
44 | -- | 74 | -- |
45 | 2.25.1 | 75 | 2.25.1 | diff view generated by jsdifflib |
1 | The only time we use the ext_gic_irq[] array in the Exynos4210Irq | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | struct is during realize of the SoC -- we initialize it with the | ||
3 | input IRQs of the external GIC device, and then connect those to | ||
4 | outputs of other devices further on in realize (including in the | ||
5 | exynos4210_init_board_irqs() function). Now that the ext_gic object | ||
6 | is easily accessible as s->ext_gic we can make the connections | ||
7 | directly from one device to the other without going via this array. | ||
8 | 2 | ||
3 | Move the function to debug_helper.c, and the | ||
4 | declaration to internals.h. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220609202901.1177572-5-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20220404154658.565020-10-peter.maydell@linaro.org | ||
12 | --- | 10 | --- |
13 | include/hw/arm/exynos4210.h | 1 - | 11 | target/arm/cpu.h | 10 ---------- |
14 | hw/arm/exynos4210.c | 12 ++++++------ | 12 | target/arm/internals.h | 1 + |
15 | 2 files changed, 6 insertions(+), 7 deletions(-) | 13 | target/arm/debug_helper.c | 12 ++++++++++++ |
14 | 3 files changed, 13 insertions(+), 10 deletions(-) | ||
16 | 15 | ||
17 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | 16 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
18 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/include/hw/arm/exynos4210.h | 18 | --- a/target/arm/cpu.h |
20 | +++ b/include/hw/arm/exynos4210.h | 19 | +++ b/target/arm/cpu.h |
21 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_generate_debug_exceptions(CPUARMState *env) |
22 | typedef struct Exynos4210Irq { | ||
23 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
24 | qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; | ||
25 | - qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ]; | ||
26 | } Exynos4210Irq; | ||
27 | |||
28 | struct Exynos4210State { | ||
29 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/hw/arm/exynos4210.c | ||
32 | +++ b/hw/arm/exynos4210.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
34 | { | ||
35 | uint32_t grp, bit, irq_id, n; | ||
36 | Exynos4210Irq *is = &s->irqs; | ||
37 | + DeviceState *extgicdev = DEVICE(&s->ext_gic); | ||
38 | |||
39 | for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { | ||
40 | irq_id = 0; | ||
41 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
42 | } | ||
43 | if (irq_id) { | ||
44 | s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
45 | - is->ext_gic_irq[irq_id - 32]); | ||
46 | + qdev_get_gpio_in(extgicdev, | ||
47 | + irq_id - 32)); | ||
48 | } else { | ||
49 | s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
50 | is->ext_combiner_irq[n]); | ||
51 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
52 | |||
53 | if (irq_id) { | ||
54 | s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
55 | - is->ext_gic_irq[irq_id - 32]); | ||
56 | + qdev_get_gpio_in(extgicdev, | ||
57 | + irq_id - 32)); | ||
58 | } | ||
59 | } | 21 | } |
60 | } | 22 | } |
61 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | 23 | |
62 | sysbus_connect_irq(busdev, n, | 24 | -/* Is single-stepping active? (Note that the "is EL_D AArch64?" check |
63 | qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1)); | 25 | - * implicitly means this always returns false in pre-v8 CPUs.) |
64 | } | 26 | - */ |
65 | - for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { | 27 | -static inline bool arm_singlestep_active(CPUARMState *env) |
66 | - s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->ext_gic), n); | 28 | -{ |
67 | - } | 29 | - return extract32(env->cp15.mdscr_el1, 0, 1) |
68 | 30 | - && arm_el_is_aa64(env, arm_debug_target_el(env)) | |
69 | /* Internal Interrupt Combiner */ | 31 | - && arm_generate_debug_exceptions(env); |
70 | dev = qdev_new("exynos4210.combiner"); | 32 | -} |
71 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | 33 | - |
72 | busdev = SYS_BUS_DEVICE(dev); | 34 | static inline bool arm_sctlr_b(CPUARMState *env) |
73 | sysbus_realize_and_unref(busdev, &error_fatal); | 35 | { |
74 | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { | 36 | return |
75 | - sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]); | 37 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
76 | + sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n)); | 38 | index XXXXXXX..XXXXXXX 100644 |
77 | } | 39 | --- a/target/arm/internals.h |
78 | exynos4210_combiner_get_gpioin(&s->irqs, dev, 1); | 40 | +++ b/target/arm/internals.h |
79 | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); | 41 | @@ -XXX,XX +XXX,XX @@ bool el_is_in_host(CPUARMState *env, int el); |
42 | |||
43 | void aa32_max_features(ARMCPU *cpu); | ||
44 | int exception_target_el(CPUARMState *env); | ||
45 | +bool arm_singlestep_active(CPUARMState *env); | ||
46 | |||
47 | /* Powers of 2 for sve_vq_map et al. */ | ||
48 | #define SVE_VQ_POW2_MAP \ | ||
49 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c | ||
50 | index XXXXXXX..XXXXXXX 100644 | ||
51 | --- a/target/arm/debug_helper.c | ||
52 | +++ b/target/arm/debug_helper.c | ||
53 | @@ -XXX,XX +XXX,XX @@ | ||
54 | #include "exec/exec-all.h" | ||
55 | #include "exec/helper-proto.h" | ||
56 | |||
57 | + | ||
58 | +/* | ||
59 | + * Is single-stepping active? (Note that the "is EL_D AArch64?" check | ||
60 | + * implicitly means this always returns false in pre-v8 CPUs.) | ||
61 | + */ | ||
62 | +bool arm_singlestep_active(CPUARMState *env) | ||
63 | +{ | ||
64 | + return extract32(env->cp15.mdscr_el1, 0, 1) | ||
65 | + && arm_el_is_aa64(env, arm_debug_target_el(env)) | ||
66 | + && arm_generate_debug_exceptions(env); | ||
67 | +} | ||
68 | + | ||
69 | /* Return true if the linked breakpoint entry lbn passes its checks */ | ||
70 | static bool linked_bp_matches(ARMCPU *cpu, int lbn) | ||
71 | { | ||
80 | -- | 72 | -- |
81 | 2.25.1 | 73 | 2.25.1 | diff view generated by jsdifflib |
1 | The function exynos4210_init_board_irqs() currently lives in | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | exynos4210_gic.c, but it isn't really part of the exynos4210.gic | ||
3 | device -- it is a function that implements (some of) the wiring up of | ||
4 | interrupts between the SoC's GIC and combiner components. This means | ||
5 | it fits better in exynos4210.c, which is the SoC-level code. Move it | ||
6 | there. Similarly, exynos4210_git_irq() is used almost only in the | ||
7 | SoC-level code, so move it too. | ||
8 | 2 | ||
3 | Move arm_generate_debug_exceptions and its two subroutines, | ||
4 | {aa32,aa64}_generate_debug_exceptions into debug_helper.c, | ||
5 | and the one interface declaration to internals.h. | ||
6 | |||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20220609202901.1177572-6-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20220404154658.565020-8-peter.maydell@linaro.org | ||
12 | --- | 11 | --- |
13 | include/hw/arm/exynos4210.h | 4 - | 12 | target/arm/cpu.h | 91 ------------------------------------- |
14 | hw/arm/exynos4210.c | 202 +++++++++++++++++++++++++++++++++++ | 13 | target/arm/internals.h | 1 + |
15 | hw/intc/exynos4210_gic.c | 204 ------------------------------------ | 14 | target/arm/debug_helper.c | 94 +++++++++++++++++++++++++++++++++++++++ |
16 | 3 files changed, 202 insertions(+), 208 deletions(-) | 15 | 3 files changed, 95 insertions(+), 91 deletions(-) |
17 | 16 | ||
18 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | 17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
19 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/include/hw/arm/exynos4210.h | 19 | --- a/target/arm/cpu.h |
21 | +++ b/include/hw/arm/exynos4210.h | 20 | +++ b/target/arm/cpu.h |
22 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC) | 21 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) |
23 | void exynos4210_write_secondary(ARMCPU *cpu, | 22 | return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; |
24 | const struct arm_boot_info *info); | 23 | } |
25 | 24 | ||
26 | -/* Initialize board IRQs. | 25 | -/* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ |
27 | - * These IRQs contain splitted Int/External Combiner and External Gic IRQs */ | 26 | -static inline bool aa64_generate_debug_exceptions(CPUARMState *env) |
28 | -void exynos4210_init_board_irqs(Exynos4210State *s); | 27 | -{ |
29 | - | 28 | - int cur_el = arm_current_el(env); |
30 | /* Get IRQ number from exynos4210 IRQ subsystem stub. | 29 | - int debug_el; |
31 | * To identify IRQ source use internal combiner group and bit number | 30 | - |
32 | * grp - group number | 31 | - if (cur_el == 3) { |
33 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | 32 | - return false; |
33 | - } | ||
34 | - | ||
35 | - /* MDCR_EL3.SDD disables debug events from Secure state */ | ||
36 | - if (arm_is_secure_below_el3(env) | ||
37 | - && extract32(env->cp15.mdcr_el3, 16, 1)) { | ||
38 | - return false; | ||
39 | - } | ||
40 | - | ||
41 | - /* | ||
42 | - * Same EL to same EL debug exceptions need MDSCR_KDE enabled | ||
43 | - * while not masking the (D)ebug bit in DAIF. | ||
44 | - */ | ||
45 | - debug_el = arm_debug_target_el(env); | ||
46 | - | ||
47 | - if (cur_el == debug_el) { | ||
48 | - return extract32(env->cp15.mdscr_el1, 13, 1) | ||
49 | - && !(env->daif & PSTATE_D); | ||
50 | - } | ||
51 | - | ||
52 | - /* Otherwise the debug target needs to be a higher EL */ | ||
53 | - return debug_el > cur_el; | ||
54 | -} | ||
55 | - | ||
56 | -static inline bool aa32_generate_debug_exceptions(CPUARMState *env) | ||
57 | -{ | ||
58 | - int el = arm_current_el(env); | ||
59 | - | ||
60 | - if (el == 0 && arm_el_is_aa64(env, 1)) { | ||
61 | - return aa64_generate_debug_exceptions(env); | ||
62 | - } | ||
63 | - | ||
64 | - if (arm_is_secure(env)) { | ||
65 | - int spd; | ||
66 | - | ||
67 | - if (el == 0 && (env->cp15.sder & 1)) { | ||
68 | - /* SDER.SUIDEN means debug exceptions from Secure EL0 | ||
69 | - * are always enabled. Otherwise they are controlled by | ||
70 | - * SDCR.SPD like those from other Secure ELs. | ||
71 | - */ | ||
72 | - return true; | ||
73 | - } | ||
74 | - | ||
75 | - spd = extract32(env->cp15.mdcr_el3, 14, 2); | ||
76 | - switch (spd) { | ||
77 | - case 1: | ||
78 | - /* SPD == 0b01 is reserved, but behaves as 0b00. */ | ||
79 | - case 0: | ||
80 | - /* For 0b00 we return true if external secure invasive debug | ||
81 | - * is enabled. On real hardware this is controlled by external | ||
82 | - * signals to the core. QEMU always permits debug, and behaves | ||
83 | - * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. | ||
84 | - */ | ||
85 | - return true; | ||
86 | - case 2: | ||
87 | - return false; | ||
88 | - case 3: | ||
89 | - return true; | ||
90 | - } | ||
91 | - } | ||
92 | - | ||
93 | - return el != 2; | ||
94 | -} | ||
95 | - | ||
96 | -/* Return true if debugging exceptions are currently enabled. | ||
97 | - * This corresponds to what in ARM ARM pseudocode would be | ||
98 | - * if UsingAArch32() then | ||
99 | - * return AArch32.GenerateDebugExceptions() | ||
100 | - * else | ||
101 | - * return AArch64.GenerateDebugExceptions() | ||
102 | - * We choose to push the if() down into this function for clarity, | ||
103 | - * since the pseudocode has it at all callsites except for the one in | ||
104 | - * CheckSoftwareStep(), where it is elided because both branches would | ||
105 | - * always return the same value. | ||
106 | - */ | ||
107 | -static inline bool arm_generate_debug_exceptions(CPUARMState *env) | ||
108 | -{ | ||
109 | - if (env->aarch64) { | ||
110 | - return aa64_generate_debug_exceptions(env); | ||
111 | - } else { | ||
112 | - return aa32_generate_debug_exceptions(env); | ||
113 | - } | ||
114 | -} | ||
115 | - | ||
116 | static inline bool arm_sctlr_b(CPUARMState *env) | ||
117 | { | ||
118 | return | ||
119 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
34 | index XXXXXXX..XXXXXXX 100644 | 120 | index XXXXXXX..XXXXXXX 100644 |
35 | --- a/hw/arm/exynos4210.c | 121 | --- a/target/arm/internals.h |
36 | +++ b/hw/arm/exynos4210.c | 122 | +++ b/target/arm/internals.h |
123 | @@ -XXX,XX +XXX,XX @@ bool el_is_in_host(CPUARMState *env, int el); | ||
124 | void aa32_max_features(ARMCPU *cpu); | ||
125 | int exception_target_el(CPUARMState *env); | ||
126 | bool arm_singlestep_active(CPUARMState *env); | ||
127 | +bool arm_generate_debug_exceptions(CPUARMState *env); | ||
128 | |||
129 | /* Powers of 2 for sve_vq_map et al. */ | ||
130 | #define SVE_VQ_POW2_MAP \ | ||
131 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c | ||
132 | index XXXXXXX..XXXXXXX 100644 | ||
133 | --- a/target/arm/debug_helper.c | ||
134 | +++ b/target/arm/debug_helper.c | ||
37 | @@ -XXX,XX +XXX,XX @@ | 135 | @@ -XXX,XX +XXX,XX @@ |
38 | #define EXYNOS4210_PL330_BASE1_ADDR 0x12690000 | 136 | #include "exec/helper-proto.h" |
39 | #define EXYNOS4210_PL330_BASE2_ADDR 0x12850000 | 137 | |
40 | 138 | ||
41 | +enum ExtGicId { | 139 | +/* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ |
42 | + EXT_GIC_ID_MDMA_LCD0 = 66, | 140 | +static bool aa64_generate_debug_exceptions(CPUARMState *env) |
43 | + EXT_GIC_ID_PDMA0, | 141 | +{ |
44 | + EXT_GIC_ID_PDMA1, | 142 | + int cur_el = arm_current_el(env); |
45 | + EXT_GIC_ID_TIMER0, | 143 | + int debug_el; |
46 | + EXT_GIC_ID_TIMER1, | 144 | + |
47 | + EXT_GIC_ID_TIMER2, | 145 | + if (cur_el == 3) { |
48 | + EXT_GIC_ID_TIMER3, | 146 | + return false; |
49 | + EXT_GIC_ID_TIMER4, | 147 | + } |
50 | + EXT_GIC_ID_MCT_L0, | 148 | + |
51 | + EXT_GIC_ID_WDT, | 149 | + /* MDCR_EL3.SDD disables debug events from Secure state */ |
52 | + EXT_GIC_ID_RTC_ALARM, | 150 | + if (arm_is_secure_below_el3(env) |
53 | + EXT_GIC_ID_RTC_TIC, | 151 | + && extract32(env->cp15.mdcr_el3, 16, 1)) { |
54 | + EXT_GIC_ID_GPIO_XB, | 152 | + return false; |
55 | + EXT_GIC_ID_GPIO_XA, | 153 | + } |
56 | + EXT_GIC_ID_MCT_L1, | 154 | + |
57 | + EXT_GIC_ID_IEM_APC, | 155 | + /* |
58 | + EXT_GIC_ID_IEM_IEC, | 156 | + * Same EL to same EL debug exceptions need MDSCR_KDE enabled |
59 | + EXT_GIC_ID_NFC, | 157 | + * while not masking the (D)ebug bit in DAIF. |
60 | + EXT_GIC_ID_UART0, | 158 | + */ |
61 | + EXT_GIC_ID_UART1, | 159 | + debug_el = arm_debug_target_el(env); |
62 | + EXT_GIC_ID_UART2, | 160 | + |
63 | + EXT_GIC_ID_UART3, | 161 | + if (cur_el == debug_el) { |
64 | + EXT_GIC_ID_UART4, | 162 | + return extract32(env->cp15.mdscr_el1, 13, 1) |
65 | + EXT_GIC_ID_MCT_G0, | 163 | + && !(env->daif & PSTATE_D); |
66 | + EXT_GIC_ID_I2C0, | 164 | + } |
67 | + EXT_GIC_ID_I2C1, | 165 | + |
68 | + EXT_GIC_ID_I2C2, | 166 | + /* Otherwise the debug target needs to be a higher EL */ |
69 | + EXT_GIC_ID_I2C3, | 167 | + return debug_el > cur_el; |
70 | + EXT_GIC_ID_I2C4, | 168 | +} |
71 | + EXT_GIC_ID_I2C5, | 169 | + |
72 | + EXT_GIC_ID_I2C6, | 170 | +static bool aa32_generate_debug_exceptions(CPUARMState *env) |
73 | + EXT_GIC_ID_I2C7, | 171 | +{ |
74 | + EXT_GIC_ID_SPI0, | 172 | + int el = arm_current_el(env); |
75 | + EXT_GIC_ID_SPI1, | 173 | + |
76 | + EXT_GIC_ID_SPI2, | 174 | + if (el == 0 && arm_el_is_aa64(env, 1)) { |
77 | + EXT_GIC_ID_MCT_G1, | 175 | + return aa64_generate_debug_exceptions(env); |
78 | + EXT_GIC_ID_USB_HOST, | 176 | + } |
79 | + EXT_GIC_ID_USB_DEVICE, | 177 | + |
80 | + EXT_GIC_ID_MODEMIF, | 178 | + if (arm_is_secure(env)) { |
81 | + EXT_GIC_ID_HSMMC0, | 179 | + int spd; |
82 | + EXT_GIC_ID_HSMMC1, | 180 | + |
83 | + EXT_GIC_ID_HSMMC2, | 181 | + if (el == 0 && (env->cp15.sder & 1)) { |
84 | + EXT_GIC_ID_HSMMC3, | 182 | + /* |
85 | + EXT_GIC_ID_SDMMC, | 183 | + * SDER.SUIDEN means debug exceptions from Secure EL0 |
86 | + EXT_GIC_ID_MIPI_CSI_4LANE, | 184 | + * are always enabled. Otherwise they are controlled by |
87 | + EXT_GIC_ID_MIPI_DSI_4LANE, | 185 | + * SDCR.SPD like those from other Secure ELs. |
88 | + EXT_GIC_ID_MIPI_CSI_2LANE, | 186 | + */ |
89 | + EXT_GIC_ID_MIPI_DSI_2LANE, | 187 | + return true; |
90 | + EXT_GIC_ID_ONENAND_AUDI, | 188 | + } |
91 | + EXT_GIC_ID_ROTATOR, | 189 | + |
92 | + EXT_GIC_ID_FIMC0, | 190 | + spd = extract32(env->cp15.mdcr_el3, 14, 2); |
93 | + EXT_GIC_ID_FIMC1, | 191 | + switch (spd) { |
94 | + EXT_GIC_ID_FIMC2, | 192 | + case 1: |
95 | + EXT_GIC_ID_FIMC3, | 193 | + /* SPD == 0b01 is reserved, but behaves as 0b00. */ |
96 | + EXT_GIC_ID_JPEG, | 194 | + case 0: |
97 | + EXT_GIC_ID_2D, | 195 | + /* |
98 | + EXT_GIC_ID_PCIe, | 196 | + * For 0b00 we return true if external secure invasive debug |
99 | + EXT_GIC_ID_MIXER, | 197 | + * is enabled. On real hardware this is controlled by external |
100 | + EXT_GIC_ID_HDMI, | 198 | + * signals to the core. QEMU always permits debug, and behaves |
101 | + EXT_GIC_ID_HDMI_I2C, | 199 | + * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. |
102 | + EXT_GIC_ID_MFC, | 200 | + */ |
103 | + EXT_GIC_ID_TVENC, | 201 | + return true; |
104 | +}; | 202 | + case 2: |
105 | + | 203 | + return false; |
106 | +enum ExtInt { | 204 | + case 3: |
107 | + EXT_GIC_ID_EXTINT0 = 48, | 205 | + return true; |
108 | + EXT_GIC_ID_EXTINT1, | 206 | + } |
109 | + EXT_GIC_ID_EXTINT2, | 207 | + } |
110 | + EXT_GIC_ID_EXTINT3, | 208 | + |
111 | + EXT_GIC_ID_EXTINT4, | 209 | + return el != 2; |
112 | + EXT_GIC_ID_EXTINT5, | 210 | +} |
113 | + EXT_GIC_ID_EXTINT6, | ||
114 | + EXT_GIC_ID_EXTINT7, | ||
115 | + EXT_GIC_ID_EXTINT8, | ||
116 | + EXT_GIC_ID_EXTINT9, | ||
117 | + EXT_GIC_ID_EXTINT10, | ||
118 | + EXT_GIC_ID_EXTINT11, | ||
119 | + EXT_GIC_ID_EXTINT12, | ||
120 | + EXT_GIC_ID_EXTINT13, | ||
121 | + EXT_GIC_ID_EXTINT14, | ||
122 | + EXT_GIC_ID_EXTINT15 | ||
123 | +}; | ||
124 | + | 211 | + |
125 | +/* | 212 | +/* |
126 | + * External GIC sources which are not from External Interrupt Combiner or | 213 | + * Return true if debugging exceptions are currently enabled. |
127 | + * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ, | 214 | + * This corresponds to what in ARM ARM pseudocode would be |
128 | + * which is INTG16 in Internal Interrupt Combiner. | 215 | + * if UsingAArch32() then |
216 | + * return AArch32.GenerateDebugExceptions() | ||
217 | + * else | ||
218 | + * return AArch64.GenerateDebugExceptions() | ||
219 | + * We choose to push the if() down into this function for clarity, | ||
220 | + * since the pseudocode has it at all callsites except for the one in | ||
221 | + * CheckSoftwareStep(), where it is elided because both branches would | ||
222 | + * always return the same value. | ||
129 | + */ | 223 | + */ |
130 | + | 224 | +bool arm_generate_debug_exceptions(CPUARMState *env) |
131 | +static const uint32_t | ||
132 | +combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
133 | + /* int combiner groups 16-19 */ | ||
134 | + { }, { }, { }, { }, | ||
135 | + /* int combiner group 20 */ | ||
136 | + { 0, EXT_GIC_ID_MDMA_LCD0 }, | ||
137 | + /* int combiner group 21 */ | ||
138 | + { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 }, | ||
139 | + /* int combiner group 22 */ | ||
140 | + { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2, | ||
141 | + EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 }, | ||
142 | + /* int combiner group 23 */ | ||
143 | + { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC }, | ||
144 | + /* int combiner group 24 */ | ||
145 | + { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA }, | ||
146 | + /* int combiner group 25 */ | ||
147 | + { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC }, | ||
148 | + /* int combiner group 26 */ | ||
149 | + { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3, | ||
150 | + EXT_GIC_ID_UART4 }, | ||
151 | + /* int combiner group 27 */ | ||
152 | + { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3, | ||
153 | + EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6, | ||
154 | + EXT_GIC_ID_I2C7 }, | ||
155 | + /* int combiner group 28 */ | ||
156 | + { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST}, | ||
157 | + /* int combiner group 29 */ | ||
158 | + { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2, | ||
159 | + EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC }, | ||
160 | + /* int combiner group 30 */ | ||
161 | + { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE }, | ||
162 | + /* int combiner group 31 */ | ||
163 | + { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE }, | ||
164 | + /* int combiner group 32 */ | ||
165 | + { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 }, | ||
166 | + /* int combiner group 33 */ | ||
167 | + { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 }, | ||
168 | + /* int combiner group 34 */ | ||
169 | + { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, | ||
170 | + /* int combiner group 35 */ | ||
171 | + { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
172 | + /* int combiner group 36 */ | ||
173 | + { EXT_GIC_ID_MIXER }, | ||
174 | + /* int combiner group 37 */ | ||
175 | + { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6, | ||
176 | + EXT_GIC_ID_EXTINT7 }, | ||
177 | + /* groups 38-50 */ | ||
178 | + { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, | ||
179 | + /* int combiner group 51 */ | ||
180 | + { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
181 | + /* group 52 */ | ||
182 | + { }, | ||
183 | + /* int combiner group 53 */ | ||
184 | + { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
185 | + /* groups 54-63 */ | ||
186 | + { }, { }, { }, { }, { }, { }, { }, { }, { }, { } | ||
187 | +}; | ||
188 | + | ||
189 | +/* | ||
190 | + * Initialize board IRQs. | ||
191 | + * These IRQs contain splitted Int/External Combiner and External Gic IRQs. | ||
192 | + */ | ||
193 | +static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
194 | +{ | 225 | +{ |
195 | + uint32_t grp, bit, irq_id, n; | 226 | + if (env->aarch64) { |
196 | + Exynos4210Irq *is = &s->irqs; | 227 | + return aa64_generate_debug_exceptions(env); |
197 | + | 228 | + } else { |
198 | + for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { | 229 | + return aa32_generate_debug_exceptions(env); |
199 | + irq_id = 0; | ||
200 | + if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) || | ||
201 | + n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) { | ||
202 | + /* MCT_G0 is passed to External GIC */ | ||
203 | + irq_id = EXT_GIC_ID_MCT_G0; | ||
204 | + } | ||
205 | + if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) || | ||
206 | + n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) { | ||
207 | + /* MCT_G1 is passed to External and GIC */ | ||
208 | + irq_id = EXT_GIC_ID_MCT_G1; | ||
209 | + } | ||
210 | + if (irq_id) { | ||
211 | + s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
212 | + is->ext_gic_irq[irq_id - 32]); | ||
213 | + } else { | ||
214 | + s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
215 | + is->ext_combiner_irq[n]); | ||
216 | + } | ||
217 | + } | ||
218 | + for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { | ||
219 | + /* these IDs are passed to Internal Combiner and External GIC */ | ||
220 | + grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n); | ||
221 | + bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); | ||
222 | + irq_id = combiner_grp_to_gic_id[grp - | ||
223 | + EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; | ||
224 | + | ||
225 | + if (irq_id) { | ||
226 | + s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
227 | + is->ext_gic_irq[irq_id - 32]); | ||
228 | + } | ||
229 | + } | 230 | + } |
230 | +} | 231 | +} |
231 | + | 232 | + |
232 | +/* | 233 | /* |
233 | + * Get IRQ number from exynos4210 IRQ subsystem stub. | 234 | * Is single-stepping active? (Note that the "is EL_D AArch64?" check |
234 | + * To identify IRQ source use internal combiner group and bit number | 235 | * implicitly means this always returns false in pre-v8 CPUs.) |
235 | + * grp - group number | ||
236 | + * bit - bit number inside group | ||
237 | + */ | ||
238 | +uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) | ||
239 | +{ | ||
240 | + return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); | ||
241 | +} | ||
242 | + | ||
243 | static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, | ||
244 | 0x09, 0x00, 0x00, 0x00 }; | ||
245 | |||
246 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | ||
247 | index XXXXXXX..XXXXXXX 100644 | ||
248 | --- a/hw/intc/exynos4210_gic.c | ||
249 | +++ b/hw/intc/exynos4210_gic.c | ||
250 | @@ -XXX,XX +XXX,XX @@ | ||
251 | #include "hw/arm/exynos4210.h" | ||
252 | #include "qom/object.h" | ||
253 | |||
254 | -enum ExtGicId { | ||
255 | - EXT_GIC_ID_MDMA_LCD0 = 66, | ||
256 | - EXT_GIC_ID_PDMA0, | ||
257 | - EXT_GIC_ID_PDMA1, | ||
258 | - EXT_GIC_ID_TIMER0, | ||
259 | - EXT_GIC_ID_TIMER1, | ||
260 | - EXT_GIC_ID_TIMER2, | ||
261 | - EXT_GIC_ID_TIMER3, | ||
262 | - EXT_GIC_ID_TIMER4, | ||
263 | - EXT_GIC_ID_MCT_L0, | ||
264 | - EXT_GIC_ID_WDT, | ||
265 | - EXT_GIC_ID_RTC_ALARM, | ||
266 | - EXT_GIC_ID_RTC_TIC, | ||
267 | - EXT_GIC_ID_GPIO_XB, | ||
268 | - EXT_GIC_ID_GPIO_XA, | ||
269 | - EXT_GIC_ID_MCT_L1, | ||
270 | - EXT_GIC_ID_IEM_APC, | ||
271 | - EXT_GIC_ID_IEM_IEC, | ||
272 | - EXT_GIC_ID_NFC, | ||
273 | - EXT_GIC_ID_UART0, | ||
274 | - EXT_GIC_ID_UART1, | ||
275 | - EXT_GIC_ID_UART2, | ||
276 | - EXT_GIC_ID_UART3, | ||
277 | - EXT_GIC_ID_UART4, | ||
278 | - EXT_GIC_ID_MCT_G0, | ||
279 | - EXT_GIC_ID_I2C0, | ||
280 | - EXT_GIC_ID_I2C1, | ||
281 | - EXT_GIC_ID_I2C2, | ||
282 | - EXT_GIC_ID_I2C3, | ||
283 | - EXT_GIC_ID_I2C4, | ||
284 | - EXT_GIC_ID_I2C5, | ||
285 | - EXT_GIC_ID_I2C6, | ||
286 | - EXT_GIC_ID_I2C7, | ||
287 | - EXT_GIC_ID_SPI0, | ||
288 | - EXT_GIC_ID_SPI1, | ||
289 | - EXT_GIC_ID_SPI2, | ||
290 | - EXT_GIC_ID_MCT_G1, | ||
291 | - EXT_GIC_ID_USB_HOST, | ||
292 | - EXT_GIC_ID_USB_DEVICE, | ||
293 | - EXT_GIC_ID_MODEMIF, | ||
294 | - EXT_GIC_ID_HSMMC0, | ||
295 | - EXT_GIC_ID_HSMMC1, | ||
296 | - EXT_GIC_ID_HSMMC2, | ||
297 | - EXT_GIC_ID_HSMMC3, | ||
298 | - EXT_GIC_ID_SDMMC, | ||
299 | - EXT_GIC_ID_MIPI_CSI_4LANE, | ||
300 | - EXT_GIC_ID_MIPI_DSI_4LANE, | ||
301 | - EXT_GIC_ID_MIPI_CSI_2LANE, | ||
302 | - EXT_GIC_ID_MIPI_DSI_2LANE, | ||
303 | - EXT_GIC_ID_ONENAND_AUDI, | ||
304 | - EXT_GIC_ID_ROTATOR, | ||
305 | - EXT_GIC_ID_FIMC0, | ||
306 | - EXT_GIC_ID_FIMC1, | ||
307 | - EXT_GIC_ID_FIMC2, | ||
308 | - EXT_GIC_ID_FIMC3, | ||
309 | - EXT_GIC_ID_JPEG, | ||
310 | - EXT_GIC_ID_2D, | ||
311 | - EXT_GIC_ID_PCIe, | ||
312 | - EXT_GIC_ID_MIXER, | ||
313 | - EXT_GIC_ID_HDMI, | ||
314 | - EXT_GIC_ID_HDMI_I2C, | ||
315 | - EXT_GIC_ID_MFC, | ||
316 | - EXT_GIC_ID_TVENC, | ||
317 | -}; | ||
318 | - | ||
319 | -enum ExtInt { | ||
320 | - EXT_GIC_ID_EXTINT0 = 48, | ||
321 | - EXT_GIC_ID_EXTINT1, | ||
322 | - EXT_GIC_ID_EXTINT2, | ||
323 | - EXT_GIC_ID_EXTINT3, | ||
324 | - EXT_GIC_ID_EXTINT4, | ||
325 | - EXT_GIC_ID_EXTINT5, | ||
326 | - EXT_GIC_ID_EXTINT6, | ||
327 | - EXT_GIC_ID_EXTINT7, | ||
328 | - EXT_GIC_ID_EXTINT8, | ||
329 | - EXT_GIC_ID_EXTINT9, | ||
330 | - EXT_GIC_ID_EXTINT10, | ||
331 | - EXT_GIC_ID_EXTINT11, | ||
332 | - EXT_GIC_ID_EXTINT12, | ||
333 | - EXT_GIC_ID_EXTINT13, | ||
334 | - EXT_GIC_ID_EXTINT14, | ||
335 | - EXT_GIC_ID_EXTINT15 | ||
336 | -}; | ||
337 | - | ||
338 | -/* | ||
339 | - * External GIC sources which are not from External Interrupt Combiner or | ||
340 | - * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ, | ||
341 | - * which is INTG16 in Internal Interrupt Combiner. | ||
342 | - */ | ||
343 | - | ||
344 | -static const uint32_t | ||
345 | -combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
346 | - /* int combiner groups 16-19 */ | ||
347 | - { }, { }, { }, { }, | ||
348 | - /* int combiner group 20 */ | ||
349 | - { 0, EXT_GIC_ID_MDMA_LCD0 }, | ||
350 | - /* int combiner group 21 */ | ||
351 | - { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 }, | ||
352 | - /* int combiner group 22 */ | ||
353 | - { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2, | ||
354 | - EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 }, | ||
355 | - /* int combiner group 23 */ | ||
356 | - { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC }, | ||
357 | - /* int combiner group 24 */ | ||
358 | - { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA }, | ||
359 | - /* int combiner group 25 */ | ||
360 | - { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC }, | ||
361 | - /* int combiner group 26 */ | ||
362 | - { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3, | ||
363 | - EXT_GIC_ID_UART4 }, | ||
364 | - /* int combiner group 27 */ | ||
365 | - { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3, | ||
366 | - EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6, | ||
367 | - EXT_GIC_ID_I2C7 }, | ||
368 | - /* int combiner group 28 */ | ||
369 | - { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST}, | ||
370 | - /* int combiner group 29 */ | ||
371 | - { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2, | ||
372 | - EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC }, | ||
373 | - /* int combiner group 30 */ | ||
374 | - { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE }, | ||
375 | - /* int combiner group 31 */ | ||
376 | - { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE }, | ||
377 | - /* int combiner group 32 */ | ||
378 | - { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 }, | ||
379 | - /* int combiner group 33 */ | ||
380 | - { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 }, | ||
381 | - /* int combiner group 34 */ | ||
382 | - { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, | ||
383 | - /* int combiner group 35 */ | ||
384 | - { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
385 | - /* int combiner group 36 */ | ||
386 | - { EXT_GIC_ID_MIXER }, | ||
387 | - /* int combiner group 37 */ | ||
388 | - { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6, | ||
389 | - EXT_GIC_ID_EXTINT7 }, | ||
390 | - /* groups 38-50 */ | ||
391 | - { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, | ||
392 | - /* int combiner group 51 */ | ||
393 | - { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
394 | - /* group 52 */ | ||
395 | - { }, | ||
396 | - /* int combiner group 53 */ | ||
397 | - { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
398 | - /* groups 54-63 */ | ||
399 | - { }, { }, { }, { }, { }, { }, { }, { }, { }, { } | ||
400 | -}; | ||
401 | - | ||
402 | #define EXYNOS4210_GIC_NIRQ 160 | ||
403 | |||
404 | #define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE 0x10000 | ||
405 | @@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
406 | #define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100 | ||
407 | #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000 | ||
408 | |||
409 | -/* | ||
410 | - * Initialize board IRQs. | ||
411 | - * These IRQs contain splitted Int/External Combiner and External Gic IRQs. | ||
412 | - */ | ||
413 | -void exynos4210_init_board_irqs(Exynos4210State *s) | ||
414 | -{ | ||
415 | - uint32_t grp, bit, irq_id, n; | ||
416 | - Exynos4210Irq *is = &s->irqs; | ||
417 | - | ||
418 | - for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { | ||
419 | - irq_id = 0; | ||
420 | - if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) || | ||
421 | - n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) { | ||
422 | - /* MCT_G0 is passed to External GIC */ | ||
423 | - irq_id = EXT_GIC_ID_MCT_G0; | ||
424 | - } | ||
425 | - if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) || | ||
426 | - n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) { | ||
427 | - /* MCT_G1 is passed to External and GIC */ | ||
428 | - irq_id = EXT_GIC_ID_MCT_G1; | ||
429 | - } | ||
430 | - if (irq_id) { | ||
431 | - s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
432 | - is->ext_gic_irq[irq_id - 32]); | ||
433 | - } else { | ||
434 | - s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
435 | - is->ext_combiner_irq[n]); | ||
436 | - } | ||
437 | - } | ||
438 | - for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { | ||
439 | - /* these IDs are passed to Internal Combiner and External GIC */ | ||
440 | - grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n); | ||
441 | - bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); | ||
442 | - irq_id = combiner_grp_to_gic_id[grp - | ||
443 | - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; | ||
444 | - | ||
445 | - if (irq_id) { | ||
446 | - s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
447 | - is->ext_gic_irq[irq_id - 32]); | ||
448 | - } | ||
449 | - } | ||
450 | -} | ||
451 | - | ||
452 | -/* | ||
453 | - * Get IRQ number from exynos4210 IRQ subsystem stub. | ||
454 | - * To identify IRQ source use internal combiner group and bit number | ||
455 | - * grp - group number | ||
456 | - * bit - bit number inside group | ||
457 | - */ | ||
458 | -uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) | ||
459 | -{ | ||
460 | - return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); | ||
461 | -} | ||
462 | - | ||
463 | -/********* GIC part *********/ | ||
464 | - | ||
465 | #define TYPE_EXYNOS4210_GIC "exynos4210.gic" | ||
466 | OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC) | ||
467 | |||
468 | -- | 236 | -- |
469 | 2.25.1 | 237 | 2.25.1 | diff view generated by jsdifflib |
1 | Fix a missing set of spaces around '-' in the definition of | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | combiner_grp_to_gic_id[]. We're about to move this code, so | ||
3 | fix the style issue first to keep checkpatch happy with the | ||
4 | code-motion patch. | ||
5 | 2 | ||
3 | Use the accessor rather than the raw structure member. | ||
4 | |||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20220609202901.1177572-7-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220404154658.565020-7-peter.maydell@linaro.org | ||
9 | --- | 9 | --- |
10 | hw/intc/exynos4210_gic.c | 2 +- | 10 | target/arm/debug_helper.c | 2 +- |
11 | 1 file changed, 1 insertion(+), 1 deletion(-) | 11 | 1 file changed, 1 insertion(+), 1 deletion(-) |
12 | 12 | ||
13 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | 13 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c |
14 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/intc/exynos4210_gic.c | 15 | --- a/target/arm/debug_helper.c |
16 | +++ b/hw/intc/exynos4210_gic.c | 16 | +++ b/target/arm/debug_helper.c |
17 | @@ -XXX,XX +XXX,XX @@ enum ExtInt { | 17 | @@ -XXX,XX +XXX,XX @@ static bool aa32_generate_debug_exceptions(CPUARMState *env) |
18 | */ | 18 | */ |
19 | 19 | bool arm_generate_debug_exceptions(CPUARMState *env) | |
20 | static const uint32_t | 20 | { |
21 | -combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | 21 | - if (env->aarch64) { |
22 | +combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | 22 | + if (is_a64(env)) { |
23 | /* int combiner groups 16-19 */ | 23 | return aa64_generate_debug_exceptions(env); |
24 | { }, { }, { }, { }, | 24 | } else { |
25 | /* int combiner group 20 */ | 25 | return aa32_generate_debug_exceptions(env); |
26 | -- | 26 | -- |
27 | 2.25.1 | 27 | 2.25.1 | diff view generated by jsdifflib |
1 | In exynos4210_init_board_irqs(), use the TYPE_SPLIT_IRQ device | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | instead of qemu_irq_split(). | ||
3 | 2 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20220609202901.1177572-8-richard.henderson@linaro.org | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20220404154658.565020-13-peter.maydell@linaro.org | ||
7 | --- | 7 | --- |
8 | include/hw/arm/exynos4210.h | 9 ++++++++ | 8 | target/arm/debug_helper.c | 31 +++++++++++++++++++++++++++++++ |
9 | hw/arm/exynos4210.c | 41 +++++++++++++++++++++++++++++-------- | 9 | target/arm/op_helper.c | 29 ----------------------------- |
10 | 2 files changed, 42 insertions(+), 8 deletions(-) | 10 | 2 files changed, 31 insertions(+), 29 deletions(-) |
11 | 11 | ||
12 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | 12 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c |
13 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/include/hw/arm/exynos4210.h | 14 | --- a/target/arm/debug_helper.c |
15 | +++ b/include/hw/arm/exynos4210.h | 15 | +++ b/target/arm/debug_helper.c |
16 | @@ -XXX,XX +XXX,XX @@ | 16 | @@ -XXX,XX +XXX,XX @@ void arm_debug_excp_handler(CPUState *cs) |
17 | #include "hw/sysbus.h" | 17 | } |
18 | #include "hw/cpu/a9mpcore.h" | 18 | } |
19 | #include "hw/intc/exynos4210_gic.h" | ||
20 | +#include "hw/core/split-irq.h" | ||
21 | #include "target/arm/cpu-qom.h" | ||
22 | #include "qom/object.h" | ||
23 | |||
24 | @@ -XXX,XX +XXX,XX @@ | ||
25 | |||
26 | #define EXYNOS4210_NUM_DMA 3 | ||
27 | 19 | ||
28 | +/* | 20 | +/* |
29 | + * We need one splitter for every external combiner input, plus | 21 | + * Raise an EXCP_BKPT with the specified syndrome register value, |
30 | + * one for every non-zero entry in combiner_grp_to_gic_id[]. | 22 | + * targeting the correct exception level for debug exceptions. |
31 | + * We'll assert in exynos4210_init_board_irqs() if this is wrong. | ||
32 | + */ | 23 | + */ |
33 | +#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 60) | 24 | +void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) |
25 | +{ | ||
26 | + int debug_el = arm_debug_target_el(env); | ||
27 | + int cur_el = arm_current_el(env); | ||
34 | + | 28 | + |
35 | typedef struct Exynos4210Irq { | 29 | + /* FSR will only be used if the debug target EL is AArch32. */ |
36 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | 30 | + env->exception.fsr = arm_debug_exception_fsr(env); |
37 | qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; | 31 | + /* |
38 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { | 32 | + * FAR is UNKNOWN: clear vaddress to avoid potentially exposing |
39 | qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; | 33 | + * values to the guest that it shouldn't be able to see at its |
40 | A9MPPrivState a9mpcore; | 34 | + * exception/security level. |
41 | Exynos4210GicState ext_gic; | 35 | + */ |
42 | + SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS]; | 36 | + env->exception.vaddress = 0; |
43 | }; | 37 | + /* |
44 | 38 | + * Other kinds of architectural debug exception are ignored if | |
45 | #define TYPE_EXYNOS4210_SOC "exynos4210" | 39 | + * they target an exception level below the current one (in QEMU |
46 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | 40 | + * this is checked by arm_generate_debug_exceptions()). Breakpoint |
41 | + * instructions are special because they always generate an exception | ||
42 | + * to somewhere: if they can't go to the configured debug exception | ||
43 | + * level they are taken to the current exception level. | ||
44 | + */ | ||
45 | + if (debug_el < cur_el) { | ||
46 | + debug_el = cur_el; | ||
47 | + } | ||
48 | + raise_exception(env, EXCP_BKPT, syndrome, debug_el); | ||
49 | +} | ||
50 | + | ||
51 | #if !defined(CONFIG_USER_ONLY) | ||
52 | |||
53 | vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) | ||
54 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | 55 | index XXXXXXX..XXXXXXX 100644 |
48 | --- a/hw/arm/exynos4210.c | 56 | --- a/target/arm/op_helper.c |
49 | +++ b/hw/arm/exynos4210.c | 57 | +++ b/target/arm/op_helper.c |
50 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | 58 | @@ -XXX,XX +XXX,XX @@ void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp, |
51 | uint32_t grp, bit, irq_id, n; | 59 | raise_exception(env, excp, syndrome, target_el); |
52 | Exynos4210Irq *is = &s->irqs; | ||
53 | DeviceState *extgicdev = DEVICE(&s->ext_gic); | ||
54 | + int splitcount = 0; | ||
55 | + DeviceState *splitter; | ||
56 | |||
57 | for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { | ||
58 | irq_id = 0; | ||
59 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
60 | /* MCT_G1 is passed to External and GIC */ | ||
61 | irq_id = EXT_GIC_ID_MCT_G1; | ||
62 | } | ||
63 | + | ||
64 | + assert(splitcount < EXYNOS4210_NUM_SPLITTERS); | ||
65 | + splitter = DEVICE(&s->splitter[splitcount]); | ||
66 | + qdev_prop_set_uint16(splitter, "num-lines", 2); | ||
67 | + qdev_realize(splitter, NULL, &error_abort); | ||
68 | + splitcount++; | ||
69 | + s->irq_table[n] = qdev_get_gpio_in(splitter, 0); | ||
70 | + qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); | ||
71 | if (irq_id) { | ||
72 | - s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
73 | - qdev_get_gpio_in(extgicdev, | ||
74 | - irq_id - 32)); | ||
75 | + qdev_connect_gpio_out(splitter, 1, | ||
76 | + qdev_get_gpio_in(extgicdev, irq_id - 32)); | ||
77 | } else { | ||
78 | - s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
79 | - is->ext_combiner_irq[n]); | ||
80 | + qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]); | ||
81 | } | ||
82 | } | ||
83 | for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { | ||
84 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
85 | EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; | ||
86 | |||
87 | if (irq_id) { | ||
88 | - s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
89 | - qdev_get_gpio_in(extgicdev, | ||
90 | - irq_id - 32)); | ||
91 | + assert(splitcount < EXYNOS4210_NUM_SPLITTERS); | ||
92 | + splitter = DEVICE(&s->splitter[splitcount]); | ||
93 | + qdev_prop_set_uint16(splitter, "num-lines", 2); | ||
94 | + qdev_realize(splitter, NULL, &error_abort); | ||
95 | + splitcount++; | ||
96 | + s->irq_table[n] = qdev_get_gpio_in(splitter, 0); | ||
97 | + qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); | ||
98 | + qdev_connect_gpio_out(splitter, 1, | ||
99 | + qdev_get_gpio_in(extgicdev, irq_id - 32)); | ||
100 | } | ||
101 | } | ||
102 | + /* | ||
103 | + * We check this here to avoid a more obscure assert later when | ||
104 | + * qdev_assert_realized_properly() checks that we realized every | ||
105 | + * child object we initialized. | ||
106 | + */ | ||
107 | + assert(splitcount == EXYNOS4210_NUM_SPLITTERS); | ||
108 | } | 60 | } |
109 | 61 | ||
110 | /* | 62 | -/* Raise an EXCP_BKPT with the specified syndrome register value, |
111 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj) | 63 | - * targeting the correct exception level for debug exceptions. |
112 | object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ); | 64 | - */ |
113 | } | 65 | -void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) |
114 | 66 | -{ | |
115 | + for (i = 0; i < ARRAY_SIZE(s->splitter); i++) { | 67 | - int debug_el = arm_debug_target_el(env); |
116 | + g_autofree char *name = g_strdup_printf("irq-splitter%d", i); | 68 | - int cur_el = arm_current_el(env); |
117 | + object_initialize_child(obj, name, &s->splitter[i], TYPE_SPLIT_IRQ); | 69 | - |
118 | + } | 70 | - /* FSR will only be used if the debug target EL is AArch32. */ |
119 | + | 71 | - env->exception.fsr = arm_debug_exception_fsr(env); |
120 | object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); | 72 | - /* FAR is UNKNOWN: clear vaddress to avoid potentially exposing |
121 | object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC); | 73 | - * values to the guest that it shouldn't be able to see at its |
122 | } | 74 | - * exception/security level. |
75 | - */ | ||
76 | - env->exception.vaddress = 0; | ||
77 | - /* | ||
78 | - * Other kinds of architectural debug exception are ignored if | ||
79 | - * they target an exception level below the current one (in QEMU | ||
80 | - * this is checked by arm_generate_debug_exceptions()). Breakpoint | ||
81 | - * instructions are special because they always generate an exception | ||
82 | - * to somewhere: if they can't go to the configured debug exception | ||
83 | - * level they are taken to the current exception level. | ||
84 | - */ | ||
85 | - if (debug_el < cur_el) { | ||
86 | - debug_el = cur_el; | ||
87 | - } | ||
88 | - raise_exception(env, EXCP_BKPT, syndrome, debug_el); | ||
89 | -} | ||
90 | - | ||
91 | uint32_t HELPER(cpsr_read)(CPUARMState *env) | ||
92 | { | ||
93 | return cpsr_read(env) & ~CPSR_EXEC; | ||
123 | -- | 94 | -- |
124 | 2.25.1 | 95 | 2.25.1 | diff view generated by jsdifflib |
1 | Now we have removed the only use of TYPE_EXYNOS4210_IRQ_GATE we can | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | delete the device entirely. | ||
3 | 2 | ||
3 | This function now now only used in debug_helper.c, so there is | ||
4 | no reason to have a declaration in a header. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220609202901.1177572-9-richard.henderson@linaro.org | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> | ||
6 | Message-id: 20220404154658.565020-3-peter.maydell@linaro.org | ||
7 | --- | 10 | --- |
8 | hw/intc/exynos4210_gic.c | 107 --------------------------------------- | 11 | target/arm/internals.h | 25 ------------------------- |
9 | 1 file changed, 107 deletions(-) | 12 | target/arm/debug_helper.c | 26 ++++++++++++++++++++++++++ |
13 | 2 files changed, 26 insertions(+), 25 deletions(-) | ||
10 | 14 | ||
11 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | 15 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
12 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/intc/exynos4210_gic.c | 17 | --- a/target/arm/internals.h |
14 | +++ b/hw/intc/exynos4210_gic.c | 18 | +++ b/target/arm/internals.h |
15 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_register_types(void) | 19 | @@ -XXX,XX +XXX,XX @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) |
20 | return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; | ||
16 | } | 21 | } |
17 | 22 | ||
18 | type_init(exynos4210_gic_register_types) | 23 | -/* Return the FSR value for a debug exception (watchpoint, hardware |
24 | - * breakpoint or BKPT insn) targeting the specified exception level. | ||
25 | - */ | ||
26 | -static inline uint32_t arm_debug_exception_fsr(CPUARMState *env) | ||
27 | -{ | ||
28 | - ARMMMUFaultInfo fi = { .type = ARMFault_Debug }; | ||
29 | - int target_el = arm_debug_target_el(env); | ||
30 | - bool using_lpae = false; | ||
19 | - | 31 | - |
20 | -/* IRQ OR Gate struct. | 32 | - if (target_el == 2 || arm_el_is_aa64(env, target_el)) { |
21 | - * | 33 | - using_lpae = true; |
22 | - * This device models an OR gate. There are n_in input qdev gpio lines and one | 34 | - } else { |
23 | - * output sysbus IRQ line. The output IRQ level is formed as OR between all | 35 | - if (arm_feature(env, ARM_FEATURE_LPAE) && |
24 | - * gpio inputs. | 36 | - (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { |
25 | - */ | 37 | - using_lpae = true; |
26 | - | ||
27 | -#define TYPE_EXYNOS4210_IRQ_GATE "exynos4210.irq_gate" | ||
28 | -OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210IRQGateState, EXYNOS4210_IRQ_GATE) | ||
29 | - | ||
30 | -struct Exynos4210IRQGateState { | ||
31 | - SysBusDevice parent_obj; | ||
32 | - | ||
33 | - uint32_t n_in; /* inputs amount */ | ||
34 | - uint32_t *level; /* input levels */ | ||
35 | - qemu_irq out; /* output IRQ */ | ||
36 | -}; | ||
37 | - | ||
38 | -static Property exynos4210_irq_gate_properties[] = { | ||
39 | - DEFINE_PROP_UINT32("n_in", Exynos4210IRQGateState, n_in, 1), | ||
40 | - DEFINE_PROP_END_OF_LIST(), | ||
41 | -}; | ||
42 | - | ||
43 | -static const VMStateDescription vmstate_exynos4210_irq_gate = { | ||
44 | - .name = "exynos4210.irq_gate", | ||
45 | - .version_id = 2, | ||
46 | - .minimum_version_id = 2, | ||
47 | - .fields = (VMStateField[]) { | ||
48 | - VMSTATE_VBUFFER_UINT32(level, Exynos4210IRQGateState, 1, NULL, n_in), | ||
49 | - VMSTATE_END_OF_LIST() | ||
50 | - } | ||
51 | -}; | ||
52 | - | ||
53 | -/* Process a change in IRQ input. */ | ||
54 | -static void exynos4210_irq_gate_handler(void *opaque, int irq, int level) | ||
55 | -{ | ||
56 | - Exynos4210IRQGateState *s = (Exynos4210IRQGateState *)opaque; | ||
57 | - uint32_t i; | ||
58 | - | ||
59 | - assert(irq < s->n_in); | ||
60 | - | ||
61 | - s->level[irq] = level; | ||
62 | - | ||
63 | - for (i = 0; i < s->n_in; i++) { | ||
64 | - if (s->level[i] >= 1) { | ||
65 | - qemu_irq_raise(s->out); | ||
66 | - return; | ||
67 | - } | 38 | - } |
68 | - } | 39 | - } |
69 | - | 40 | - |
70 | - qemu_irq_lower(s->out); | 41 | - if (using_lpae) { |
42 | - return arm_fi_to_lfsc(&fi); | ||
43 | - } else { | ||
44 | - return arm_fi_to_sfsc(&fi); | ||
45 | - } | ||
71 | -} | 46 | -} |
72 | - | 47 | - |
73 | -static void exynos4210_irq_gate_reset(DeviceState *d) | 48 | /** |
74 | -{ | 49 | * arm_num_brps: Return number of implemented breakpoints. |
75 | - Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(d); | 50 | * Note that the ID register BRPS field is "number of bps - 1", |
76 | - | 51 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c |
77 | - memset(s->level, 0, s->n_in * sizeof(*s->level)); | 52 | index XXXXXXX..XXXXXXX 100644 |
78 | -} | 53 | --- a/target/arm/debug_helper.c |
79 | - | 54 | +++ b/target/arm/debug_helper.c |
80 | -/* | 55 | @@ -XXX,XX +XXX,XX @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) |
81 | - * IRQ Gate initialization. | 56 | return check_watchpoints(cpu); |
82 | - */ | 57 | } |
83 | -static void exynos4210_irq_gate_init(Object *obj) | 58 | |
84 | -{ | 59 | +/* |
85 | - Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(obj); | 60 | + * Return the FSR value for a debug exception (watchpoint, hardware |
86 | - SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | 61 | + * breakpoint or BKPT insn) targeting the specified exception level. |
87 | - | 62 | + */ |
88 | - sysbus_init_irq(sbd, &s->out); | 63 | +static uint32_t arm_debug_exception_fsr(CPUARMState *env) |
89 | -} | 64 | +{ |
90 | - | 65 | + ARMMMUFaultInfo fi = { .type = ARMFault_Debug }; |
91 | -static void exynos4210_irq_gate_realize(DeviceState *dev, Error **errp) | 66 | + int target_el = arm_debug_target_el(env); |
92 | -{ | 67 | + bool using_lpae = false; |
93 | - Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(dev); | 68 | + |
94 | - | 69 | + if (target_el == 2 || arm_el_is_aa64(env, target_el)) { |
95 | - /* Allocate general purpose input signals and connect a handler to each of | 70 | + using_lpae = true; |
96 | - * them */ | 71 | + } else { |
97 | - qdev_init_gpio_in(dev, exynos4210_irq_gate_handler, s->n_in); | 72 | + if (arm_feature(env, ARM_FEATURE_LPAE) && |
98 | - | 73 | + (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { |
99 | - s->level = g_malloc0(s->n_in * sizeof(*s->level)); | 74 | + using_lpae = true; |
100 | -} | 75 | + } |
101 | - | 76 | + } |
102 | -static void exynos4210_irq_gate_class_init(ObjectClass *klass, void *data) | 77 | + |
103 | -{ | 78 | + if (using_lpae) { |
104 | - DeviceClass *dc = DEVICE_CLASS(klass); | 79 | + return arm_fi_to_lfsc(&fi); |
105 | - | 80 | + } else { |
106 | - dc->reset = exynos4210_irq_gate_reset; | 81 | + return arm_fi_to_sfsc(&fi); |
107 | - dc->vmsd = &vmstate_exynos4210_irq_gate; | 82 | + } |
108 | - device_class_set_props(dc, exynos4210_irq_gate_properties); | 83 | +} |
109 | - dc->realize = exynos4210_irq_gate_realize; | 84 | + |
110 | -} | 85 | void arm_debug_excp_handler(CPUState *cs) |
111 | - | 86 | { |
112 | -static const TypeInfo exynos4210_irq_gate_info = { | 87 | /* |
113 | - .name = TYPE_EXYNOS4210_IRQ_GATE, | ||
114 | - .parent = TYPE_SYS_BUS_DEVICE, | ||
115 | - .instance_size = sizeof(Exynos4210IRQGateState), | ||
116 | - .instance_init = exynos4210_irq_gate_init, | ||
117 | - .class_init = exynos4210_irq_gate_class_init, | ||
118 | -}; | ||
119 | - | ||
120 | -static void exynos4210_irq_gate_register_types(void) | ||
121 | -{ | ||
122 | - type_register_static(&exynos4210_irq_gate_info); | ||
123 | -} | ||
124 | - | ||
125 | -type_init(exynos4210_irq_gate_register_types) | ||
126 | -- | 88 | -- |
127 | 2.25.1 | 89 | 2.25.1 | diff view generated by jsdifflib |
1 | The Exynos4210 SoC device currently uses a custom device | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | "exynos4210.irq_gate" to model the OR gate that feeds each CPU's IRQ | ||
3 | line. We have a standard TYPE_OR_IRQ device for this now, so use | ||
4 | that instead. | ||
5 | 2 | ||
6 | (This is a migration compatibility break, but that is OK for this | 3 | Rename to helper_exception_with_syndrome_el, to emphasize |
7 | machine type.) | 4 | that the target el is a parameter. |
8 | 5 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220609202901.1177572-10-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20220404154658.565020-2-peter.maydell@linaro.org | ||
12 | --- | 10 | --- |
13 | include/hw/arm/exynos4210.h | 1 + | 11 | target/arm/helper.h | 2 +- |
14 | hw/arm/exynos4210.c | 31 ++++++++++++++++--------------- | 12 | target/arm/translate.h | 6 +++--- |
15 | 2 files changed, 17 insertions(+), 15 deletions(-) | 13 | target/arm/op_helper.c | 6 +++--- |
14 | target/arm/translate.c | 6 +++--- | ||
15 | 4 files changed, 10 insertions(+), 10 deletions(-) | ||
16 | 16 | ||
17 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | 17 | diff --git a/target/arm/helper.h b/target/arm/helper.h |
18 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/include/hw/arm/exynos4210.h | 19 | --- a/target/arm/helper.h |
20 | +++ b/include/hw/arm/exynos4210.h | 20 | +++ b/target/arm/helper.h |
21 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { | 21 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32) |
22 | MemoryRegion bootreg_mem; | 22 | DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, |
23 | I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; | 23 | i32, i32, i32, i32) |
24 | qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; | 24 | DEF_HELPER_2(exception_internal, noreturn, env, i32) |
25 | + qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; | 25 | -DEF_HELPER_4(exception_with_syndrome, noreturn, env, i32, i32, i32) |
26 | }; | 26 | +DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) |
27 | 27 | DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) | |
28 | #define TYPE_EXYNOS4210_SOC "exynos4210" | 28 | DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) |
29 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | 29 | DEF_HELPER_1(setend, void, env) |
30 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
30 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
31 | --- a/hw/arm/exynos4210.c | 32 | --- a/target/arm/translate.h |
32 | +++ b/hw/arm/exynos4210.c | 33 | +++ b/target/arm/translate.h |
33 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | 34 | @@ -XXX,XX +XXX,XX @@ static inline void gen_ss_advance(DisasContext *s) |
35 | static inline void gen_exception(int excp, uint32_t syndrome, | ||
36 | uint32_t target_el) | ||
34 | { | 37 | { |
35 | Exynos4210State *s = EXYNOS4210_SOC(socdev); | 38 | - gen_helper_exception_with_syndrome(cpu_env, tcg_constant_i32(excp), |
36 | MemoryRegion *system_mem = get_system_memory(); | 39 | - tcg_constant_i32(syndrome), |
37 | - qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; | 40 | - tcg_constant_i32(target_el)); |
38 | SysBusDevice *busdev; | 41 | + gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), |
39 | DeviceState *dev, *uart[4], *pl330[3]; | 42 | + tcg_constant_i32(syndrome), |
40 | int i, n; | 43 | + tcg_constant_i32(target_el)); |
41 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
42 | |||
43 | /* IRQ Gate */ | ||
44 | for (i = 0; i < EXYNOS4210_NCPUS; i++) { | ||
45 | - dev = qdev_new("exynos4210.irq_gate"); | ||
46 | - qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS); | ||
47 | - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | ||
48 | - /* Get IRQ Gate input in gate_irq */ | ||
49 | - for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) { | ||
50 | - gate_irq[i][n] = qdev_get_gpio_in(dev, n); | ||
51 | - } | ||
52 | - busdev = SYS_BUS_DEVICE(dev); | ||
53 | - | ||
54 | - /* Connect IRQ Gate output to CPU's IRQ line */ | ||
55 | - sysbus_connect_irq(busdev, 0, | ||
56 | - qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); | ||
57 | + DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]); | ||
58 | + object_property_set_int(OBJECT(orgate), "num-lines", | ||
59 | + EXYNOS4210_IRQ_GATE_NINPUTS, | ||
60 | + &error_abort); | ||
61 | + qdev_realize(orgate, NULL, &error_abort); | ||
62 | + qdev_connect_gpio_out(orgate, 0, | ||
63 | + qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); | ||
64 | } | ||
65 | |||
66 | /* Private memory region and Internal GIC */ | ||
67 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
68 | sysbus_realize_and_unref(busdev, &error_fatal); | ||
69 | sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); | ||
70 | for (n = 0; n < EXYNOS4210_NCPUS; n++) { | ||
71 | - sysbus_connect_irq(busdev, n, gate_irq[n][0]); | ||
72 | + sysbus_connect_irq(busdev, n, | ||
73 | + qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0)); | ||
74 | } | ||
75 | for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { | ||
76 | s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n); | ||
77 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
78 | /* Map Distributer interface */ | ||
79 | sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR); | ||
80 | for (n = 0; n < EXYNOS4210_NCPUS; n++) { | ||
81 | - sysbus_connect_irq(busdev, n, gate_irq[n][1]); | ||
82 | + sysbus_connect_irq(busdev, n, | ||
83 | + qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1)); | ||
84 | } | ||
85 | for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { | ||
86 | s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n); | ||
87 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj) | ||
88 | object_initialize_child(obj, name, orgate, TYPE_OR_IRQ); | ||
89 | g_free(name); | ||
90 | } | ||
91 | + | ||
92 | + for (i = 0; i < ARRAY_SIZE(s->cpu_irq_orgate); i++) { | ||
93 | + g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i); | ||
94 | + object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ); | ||
95 | + } | ||
96 | } | 44 | } |
97 | 45 | ||
98 | static void exynos4210_class_init(ObjectClass *klass, void *data) | 46 | /* Generate an architectural singlestep exception */ |
47 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/target/arm/op_helper.c | ||
50 | +++ b/target/arm/op_helper.c | ||
51 | @@ -XXX,XX +XXX,XX @@ void HELPER(yield)(CPUARMState *env) | ||
52 | * those EXCP values which are special cases for QEMU to interrupt | ||
53 | * execution and not to be used for exceptions which are passed to | ||
54 | * the guest (those must all have syndrome information and thus should | ||
55 | - * use exception_with_syndrome). | ||
56 | + * use exception_with_syndrome*). | ||
57 | */ | ||
58 | void HELPER(exception_internal)(CPUARMState *env, uint32_t excp) | ||
59 | { | ||
60 | @@ -XXX,XX +XXX,XX @@ void HELPER(exception_internal)(CPUARMState *env, uint32_t excp) | ||
61 | } | ||
62 | |||
63 | /* Raise an exception with the specified syndrome register value */ | ||
64 | -void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp, | ||
65 | - uint32_t syndrome, uint32_t target_el) | ||
66 | +void HELPER(exception_with_syndrome_el)(CPUARMState *env, uint32_t excp, | ||
67 | + uint32_t syndrome, uint32_t target_el) | ||
68 | { | ||
69 | raise_exception(env, excp, syndrome, target_el); | ||
70 | } | ||
71 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
72 | index XXXXXXX..XXXXXXX 100644 | ||
73 | --- a/target/arm/translate.c | ||
74 | +++ b/target/arm/translate.c | ||
75 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_el(DisasContext *s, int excp, uint32_t syn, | ||
76 | { | ||
77 | gen_set_condexec(s); | ||
78 | gen_set_pc_im(s, s->pc_curr); | ||
79 | - gen_helper_exception_with_syndrome(cpu_env, | ||
80 | - tcg_constant_i32(excp), | ||
81 | - tcg_constant_i32(syn), tcg_el); | ||
82 | + gen_helper_exception_with_syndrome_el(cpu_env, | ||
83 | + tcg_constant_i32(excp), | ||
84 | + tcg_constant_i32(syn), tcg_el); | ||
85 | s->base.is_jmp = DISAS_NORETURN; | ||
86 | } | ||
87 | |||
99 | -- | 88 | -- |
100 | 2.25.1 | 89 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Zongyuan Li <zongyuan.li@smartx.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com> | 3 | Create a function below gen_exception_insn that takes |
4 | the target_el as a TCGv_i32, replacing gen_exception_el. | ||
5 | |||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Message-id: 20220324181557.203805-5-zongyuan.li@smartx.com | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/811 | 8 | Message-id: 20220609202901.1177572-11-richard.henderson@linaro.org |
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 10 | --- |
9 | include/hw/irq.h | 5 ----- | 11 | target/arm/translate.c | 27 ++++++++++++--------------- |
10 | hw/core/irq.c | 15 --------------- | 12 | 1 file changed, 12 insertions(+), 15 deletions(-) |
11 | 2 files changed, 20 deletions(-) | ||
12 | 13 | ||
13 | diff --git a/include/hw/irq.h b/include/hw/irq.h | 14 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
14 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/include/hw/irq.h | 16 | --- a/target/arm/translate.c |
16 | +++ b/include/hw/irq.h | 17 | +++ b/target/arm/translate.c |
17 | @@ -XXX,XX +XXX,XX @@ void qemu_free_irq(qemu_irq irq); | 18 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp) |
18 | /* Returns a new IRQ with opposite polarity. */ | 19 | s->base.is_jmp = DISAS_NORETURN; |
19 | qemu_irq qemu_irq_invert(qemu_irq irq); | ||
20 | |||
21 | -/* Returns a new IRQ which feeds into both the passed IRQs. | ||
22 | - * It's probably better to use the TYPE_SPLIT_IRQ device instead. | ||
23 | - */ | ||
24 | -qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2); | ||
25 | - | ||
26 | /* For internal use in qtest. Similar to qemu_irq_split, but operating | ||
27 | on an existing vector of qemu_irq. */ | ||
28 | void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n); | ||
29 | diff --git a/hw/core/irq.c b/hw/core/irq.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/hw/core/irq.c | ||
32 | +++ b/hw/core/irq.c | ||
33 | @@ -XXX,XX +XXX,XX @@ qemu_irq qemu_irq_invert(qemu_irq irq) | ||
34 | return qemu_allocate_irq(qemu_notirq, irq, 0); | ||
35 | } | 20 | } |
36 | 21 | ||
37 | -static void qemu_splitirq(void *opaque, int line, int level) | 22 | -void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, |
23 | - uint32_t syn, uint32_t target_el) | ||
24 | +static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, | ||
25 | + uint32_t syn, TCGv_i32 tcg_el) | ||
26 | { | ||
27 | if (s->aarch64) { | ||
28 | gen_a64_set_pc_im(pc); | ||
29 | @@ -XXX,XX +XXX,XX @@ void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, | ||
30 | gen_set_condexec(s); | ||
31 | gen_set_pc_im(s, pc); | ||
32 | } | ||
33 | - gen_exception(excp, syn, target_el); | ||
34 | + gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), | ||
35 | + tcg_constant_i32(syn), tcg_el); | ||
36 | s->base.is_jmp = DISAS_NORETURN; | ||
37 | } | ||
38 | |||
39 | +void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, | ||
40 | + uint32_t syn, uint32_t target_el) | ||
41 | +{ | ||
42 | + gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el)); | ||
43 | +} | ||
44 | + | ||
45 | static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) | ||
46 | { | ||
47 | gen_set_condexec(s); | ||
48 | @@ -XXX,XX +XXX,XX @@ void unallocated_encoding(DisasContext *s) | ||
49 | default_exception_el(s)); | ||
50 | } | ||
51 | |||
52 | -static void gen_exception_el(DisasContext *s, int excp, uint32_t syn, | ||
53 | - TCGv_i32 tcg_el) | ||
38 | -{ | 54 | -{ |
39 | - struct IRQState **irq = opaque; | 55 | - gen_set_condexec(s); |
40 | - irq[0]->handler(irq[0]->opaque, irq[0]->n, level); | 56 | - gen_set_pc_im(s, s->pc_curr); |
41 | - irq[1]->handler(irq[1]->opaque, irq[1]->n, level); | 57 | - gen_helper_exception_with_syndrome_el(cpu_env, |
58 | - tcg_constant_i32(excp), | ||
59 | - tcg_constant_i32(syn), tcg_el); | ||
60 | - s->base.is_jmp = DISAS_NORETURN; | ||
42 | -} | 61 | -} |
43 | - | 62 | - |
44 | -qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2) | 63 | /* Force a TB lookup after an instruction that changes the CPU state. */ |
45 | -{ | 64 | void gen_lookup_tb(DisasContext *s) |
46 | - qemu_irq *s = g_new0(qemu_irq, 2); | ||
47 | - s[0] = irq1; | ||
48 | - s[1] = irq2; | ||
49 | - return qemu_allocate_irq(qemu_splitirq, s, 0); | ||
50 | -} | ||
51 | - | ||
52 | void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n) | ||
53 | { | 65 | { |
54 | int i; | 66 | @@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, |
67 | tcg_el = tcg_constant_i32(3); | ||
68 | } | ||
69 | |||
70 | - gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el); | ||
71 | + gen_exception_insn_el_v(s, s->pc_curr, EXCP_UDEF, | ||
72 | + syn_uncategorized(), tcg_el); | ||
73 | tcg_temp_free_i32(tcg_el); | ||
74 | return false; | ||
75 | } | ||
55 | -- | 76 | -- |
56 | 2.25.1 | 77 | 2.25.1 | diff view generated by jsdifflib |
1 | From: "Edgar E. Iglesias" <edgar.iglesias@amd.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Break out header file to allow embedding of the the TTC. | 3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | |
5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> | 5 | Message-id: 20220609202901.1177572-12-richard.henderson@linaro.org |
6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
7 | Reviewed-by: Luc Michel <luc@lmichel.fr> | ||
8 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> | ||
9 | Message-id: 20220331222017.2914409-2-edgar.iglesias@gmail.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 7 | --- |
12 | include/hw/timer/cadence_ttc.h | 54 ++++++++++++++++++++++++++++++++++ | 8 | target/arm/translate.h | 4 ++-- |
13 | hw/timer/cadence_ttc.c | 32 ++------------------ | 9 | target/arm/translate-a64.c | 36 ++++++++++++++++---------------- |
14 | 2 files changed, 56 insertions(+), 30 deletions(-) | 10 | target/arm/translate-m-nocp.c | 16 +++++++------- |
15 | create mode 100644 include/hw/timer/cadence_ttc.h | 11 | target/arm/translate-mve.c | 4 ++-- |
12 | target/arm/translate-vfp.c | 6 +++--- | ||
13 | target/arm/translate.c | 39 ++++++++++++++++++----------------- | ||
14 | 6 files changed, 53 insertions(+), 52 deletions(-) | ||
16 | 15 | ||
17 | diff --git a/include/hw/timer/cadence_ttc.h b/include/hw/timer/cadence_ttc.h | 16 | diff --git a/target/arm/translate.h b/target/arm/translate.h |
18 | new file mode 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
19 | index XXXXXXX..XXXXXXX | 18 | --- a/target/arm/translate.h |
20 | --- /dev/null | 19 | +++ b/target/arm/translate.h |
21 | +++ b/include/hw/timer/cadence_ttc.h | 20 | @@ -XXX,XX +XXX,XX @@ void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); |
22 | @@ -XXX,XX +XXX,XX @@ | 21 | void arm_gen_test_cc(int cc, TCGLabel *label); |
23 | +/* | 22 | MemOp pow2_align(unsigned i); |
24 | + * Xilinx Zynq cadence TTC model | 23 | void unallocated_encoding(DisasContext *s); |
25 | + * | 24 | -void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, |
26 | + * Copyright (c) 2011 Xilinx Inc. | 25 | - uint32_t syn, uint32_t target_el); |
27 | + * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) | 26 | +void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, |
28 | + * Copyright (c) 2012 PetaLogix Pty Ltd. | 27 | + uint32_t syn, uint32_t target_el); |
29 | + * Written By Haibing Ma | 28 | |
30 | + * M. Habib | 29 | /* Return state of Alternate Half-precision flag, caller frees result */ |
31 | + * | 30 | static inline TCGv_i32 get_ahp_flag(void) |
32 | + * This program is free software; you can redistribute it and/or | 31 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
33 | + * modify it under the terms of the GNU General Public License | 32 | index XXXXXXX..XXXXXXX 100644 |
34 | + * as published by the Free Software Foundation; either version | 33 | --- a/target/arm/translate-a64.c |
35 | + * 2 of the License, or (at your option) any later version. | 34 | +++ b/target/arm/translate-a64.c |
36 | + * | 35 | @@ -XXX,XX +XXX,XX @@ static bool fp_access_check(DisasContext *s) |
37 | + * You should have received a copy of the GNU General Public License along | 36 | assert(!s->fp_access_checked); |
38 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | 37 | s->fp_access_checked = true; |
39 | + */ | 38 | |
40 | +#ifndef HW_TIMER_CADENCE_TTC_H | 39 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, |
41 | +#define HW_TIMER_CADENCE_TTC_H | 40 | - syn_fp_access_trap(1, 0xe, false, 0), |
42 | + | 41 | - s->fp_excp_el); |
43 | +#include "hw/sysbus.h" | 42 | + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, |
44 | +#include "qemu/timer.h" | 43 | + syn_fp_access_trap(1, 0xe, false, 0), |
45 | + | 44 | + s->fp_excp_el); |
46 | +typedef struct { | 45 | return false; |
47 | + QEMUTimer *timer; | 46 | } |
48 | + int freq; | 47 | s->fp_access_checked = true; |
49 | + | 48 | @@ -XXX,XX +XXX,XX @@ bool sve_access_check(DisasContext *s) |
50 | + uint32_t reg_clock; | 49 | assert(!s->sve_access_checked); |
51 | + uint32_t reg_count; | 50 | s->sve_access_checked = true; |
52 | + uint32_t reg_value; | 51 | |
53 | + uint16_t reg_interval; | 52 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, |
54 | + uint16_t reg_match[3]; | 53 | - syn_sve_access_trap(), s->sve_excp_el); |
55 | + uint32_t reg_intr; | 54 | + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, |
56 | + uint32_t reg_intr_en; | 55 | + syn_sve_access_trap(), s->sve_excp_el); |
57 | + uint32_t reg_event_ctrl; | 56 | return false; |
58 | + uint32_t reg_event; | 57 | } |
59 | + | 58 | s->sve_access_checked = true; |
60 | + uint64_t cpu_time; | 59 | @@ -XXX,XX +XXX,XX @@ static void gen_sysreg_undef(DisasContext *s, bool isread, |
61 | + unsigned int cpu_time_valid; | 60 | } else { |
62 | + | 61 | syndrome = syn_uncategorized(); |
63 | + qemu_irq irq; | 62 | } |
64 | +} CadenceTimerState; | 63 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syndrome, |
65 | + | 64 | - default_exception_el(s)); |
66 | +#define TYPE_CADENCE_TTC "cadence_ttc" | 65 | + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syndrome, |
67 | +OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC) | 66 | + default_exception_el(s)); |
68 | + | 67 | } |
69 | +struct CadenceTTCState { | 68 | |
70 | + SysBusDevice parent_obj; | 69 | /* MRS - move from system register |
71 | + | 70 | @@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn) |
72 | + MemoryRegion iomem; | 71 | switch (op2_ll) { |
73 | + CadenceTimerState timer[3]; | 72 | case 1: /* SVC */ |
74 | +}; | 73 | gen_ss_advance(s); |
75 | + | 74 | - gen_exception_insn(s, s->base.pc_next, EXCP_SWI, |
76 | +#endif | 75 | - syn_aa64_svc(imm16), default_exception_el(s)); |
77 | diff --git a/hw/timer/cadence_ttc.c b/hw/timer/cadence_ttc.c | 76 | + gen_exception_insn_el(s, s->base.pc_next, EXCP_SWI, |
78 | index XXXXXXX..XXXXXXX 100644 | 77 | + syn_aa64_svc(imm16), default_exception_el(s)); |
79 | --- a/hw/timer/cadence_ttc.c | 78 | break; |
80 | +++ b/hw/timer/cadence_ttc.c | 79 | case 2: /* HVC */ |
81 | @@ -XXX,XX +XXX,XX @@ | 80 | if (s->current_el == 0) { |
82 | #include "qemu/timer.h" | 81 | @@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn) |
83 | #include "qom/object.h" | 82 | gen_a64_set_pc_im(s->pc_curr); |
84 | 83 | gen_helper_pre_hvc(cpu_env); | |
85 | +#include "hw/timer/cadence_ttc.h" | 84 | gen_ss_advance(s); |
86 | + | 85 | - gen_exception_insn(s, s->base.pc_next, EXCP_HVC, |
87 | #ifdef CADENCE_TTC_ERR_DEBUG | 86 | - syn_aa64_hvc(imm16), 2); |
88 | #define DB_PRINT(...) do { \ | 87 | + gen_exception_insn_el(s, s->base.pc_next, EXCP_HVC, |
89 | fprintf(stderr, ": %s: ", __func__); \ | 88 | + syn_aa64_hvc(imm16), 2); |
90 | @@ -XXX,XX +XXX,XX @@ | 89 | break; |
91 | #define CLOCK_CTRL_PS_EN 0x00000001 | 90 | case 3: /* SMC */ |
92 | #define CLOCK_CTRL_PS_V 0x0000001e | 91 | if (s->current_el == 0) { |
93 | 92 | @@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn) | |
94 | -typedef struct { | 93 | gen_a64_set_pc_im(s->pc_curr); |
95 | - QEMUTimer *timer; | 94 | gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16))); |
96 | - int freq; | 95 | gen_ss_advance(s); |
97 | - | 96 | - gen_exception_insn(s, s->base.pc_next, EXCP_SMC, |
98 | - uint32_t reg_clock; | 97 | - syn_aa64_smc(imm16), 3); |
99 | - uint32_t reg_count; | 98 | + gen_exception_insn_el(s, s->base.pc_next, EXCP_SMC, |
100 | - uint32_t reg_value; | 99 | + syn_aa64_smc(imm16), 3); |
101 | - uint16_t reg_interval; | 100 | break; |
102 | - uint16_t reg_match[3]; | 101 | default: |
103 | - uint32_t reg_intr; | 102 | unallocated_encoding(s); |
104 | - uint32_t reg_intr_en; | 103 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
105 | - uint32_t reg_event_ctrl; | 104 | * Illegal execution state. This has priority over BTI |
106 | - uint32_t reg_event; | 105 | * exceptions, but comes after instruction abort exceptions. |
107 | - | 106 | */ |
108 | - uint64_t cpu_time; | 107 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, |
109 | - unsigned int cpu_time_valid; | 108 | - syn_illegalstate(), default_exception_el(s)); |
110 | - | 109 | + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, |
111 | - qemu_irq irq; | 110 | + syn_illegalstate(), default_exception_el(s)); |
112 | -} CadenceTimerState; | 111 | return; |
113 | - | 112 | } |
114 | -#define TYPE_CADENCE_TTC "cadence_ttc" | 113 | |
115 | -OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC) | 114 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
116 | - | 115 | if (s->btype != 0 |
117 | -struct CadenceTTCState { | 116 | && s->guarded_page |
118 | - SysBusDevice parent_obj; | 117 | && !btype_destination_ok(insn, s->bt, s->btype)) { |
119 | - | 118 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, |
120 | - MemoryRegion iomem; | 119 | - syn_btitrap(s->btype), |
121 | - CadenceTimerState timer[3]; | 120 | - default_exception_el(s)); |
122 | -}; | 121 | + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, |
123 | - | 122 | + syn_btitrap(s->btype), |
124 | static void cadence_timer_update(CadenceTimerState *s) | 123 | + default_exception_el(s)); |
124 | return; | ||
125 | } | ||
126 | } else { | ||
127 | diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c | ||
128 | index XXXXXXX..XXXXXXX 100644 | ||
129 | --- a/target/arm/translate-m-nocp.c | ||
130 | +++ b/target/arm/translate-m-nocp.c | ||
131 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) | ||
132 | tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel); | ||
133 | |||
134 | if (s->fp_excp_el != 0) { | ||
135 | - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
136 | - syn_uncategorized(), s->fp_excp_el); | ||
137 | + gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, | ||
138 | + syn_uncategorized(), s->fp_excp_el); | ||
139 | return true; | ||
140 | } | ||
141 | |||
142 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
143 | if (!vfp_access_check_m(s, true)) { | ||
144 | /* | ||
145 | * This was only a conditional exception, so override | ||
146 | - * gen_exception_insn()'s default to DISAS_NORETURN | ||
147 | + * gen_exception_insn_el()'s default to DISAS_NORETURN | ||
148 | */ | ||
149 | s->base.is_jmp = DISAS_NEXT; | ||
150 | break; | ||
151 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, | ||
152 | if (!vfp_access_check_m(s, true)) { | ||
153 | /* | ||
154 | * This was only a conditional exception, so override | ||
155 | - * gen_exception_insn()'s default to DISAS_NORETURN | ||
156 | + * gen_exception_insn_el()'s default to DISAS_NORETURN | ||
157 | */ | ||
158 | s->base.is_jmp = DISAS_NEXT; | ||
159 | break; | ||
160 | @@ -XXX,XX +XXX,XX @@ static bool trans_NOCP(DisasContext *s, arg_nocp *a) | ||
161 | } | ||
162 | |||
163 | if (a->cp != 10) { | ||
164 | - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
165 | - syn_uncategorized(), default_exception_el(s)); | ||
166 | + gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, | ||
167 | + syn_uncategorized(), default_exception_el(s)); | ||
168 | return true; | ||
169 | } | ||
170 | |||
171 | if (s->fp_excp_el != 0) { | ||
172 | - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
173 | - syn_uncategorized(), s->fp_excp_el); | ||
174 | + gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, | ||
175 | + syn_uncategorized(), s->fp_excp_el); | ||
176 | return true; | ||
177 | } | ||
178 | |||
179 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
180 | index XXXXXXX..XXXXXXX 100644 | ||
181 | --- a/target/arm/translate-mve.c | ||
182 | +++ b/target/arm/translate-mve.c | ||
183 | @@ -XXX,XX +XXX,XX @@ bool mve_eci_check(DisasContext *s) | ||
184 | return true; | ||
185 | default: | ||
186 | /* Reserved value: INVSTATE UsageFault */ | ||
187 | - gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), | ||
188 | - default_exception_el(s)); | ||
189 | + gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), | ||
190 | + default_exception_el(s)); | ||
191 | return false; | ||
192 | } | ||
193 | } | ||
194 | diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c | ||
195 | index XXXXXXX..XXXXXXX 100644 | ||
196 | --- a/target/arm/translate-vfp.c | ||
197 | +++ b/target/arm/translate-vfp.c | ||
198 | @@ -XXX,XX +XXX,XX @@ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled) | ||
199 | int coproc = arm_dc_feature(s, ARM_FEATURE_V8) ? 0 : 0xa; | ||
200 | uint32_t syn = syn_fp_access_trap(1, 0xe, false, coproc); | ||
201 | |||
202 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el); | ||
203 | + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el); | ||
204 | return false; | ||
205 | } | ||
206 | |||
207 | @@ -XXX,XX +XXX,XX @@ bool vfp_access_check_m(DisasContext *s, bool skip_context_update) | ||
208 | * the encoding space handled by the patterns in m-nocp.decode, | ||
209 | * and for them we may need to raise NOCP here. | ||
210 | */ | ||
211 | - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
212 | - syn_uncategorized(), s->fp_excp_el); | ||
213 | + gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, | ||
214 | + syn_uncategorized(), s->fp_excp_el); | ||
215 | return false; | ||
216 | } | ||
217 | |||
218 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
219 | index XXXXXXX..XXXXXXX 100644 | ||
220 | --- a/target/arm/translate.c | ||
221 | +++ b/target/arm/translate.c | ||
222 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, | ||
223 | s->base.is_jmp = DISAS_NORETURN; | ||
224 | } | ||
225 | |||
226 | -void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, | ||
227 | - uint32_t syn, uint32_t target_el) | ||
228 | +void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, | ||
229 | + uint32_t syn, uint32_t target_el) | ||
125 | { | 230 | { |
126 | qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en)); | 231 | gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el)); |
232 | } | ||
233 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) | ||
234 | void unallocated_encoding(DisasContext *s) | ||
235 | { | ||
236 | /* Unallocated and reserved encodings are uncategorized */ | ||
237 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), | ||
238 | - default_exception_el(s)); | ||
239 | + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), | ||
240 | + default_exception_el(s)); | ||
241 | } | ||
242 | |||
243 | /* Force a TB lookup after an instruction that changes the CPU state. */ | ||
244 | @@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, | ||
245 | |||
246 | undef: | ||
247 | /* If we get here then some access check did not pass */ | ||
248 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, | ||
249 | - syn_uncategorized(), exc_target); | ||
250 | + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, | ||
251 | + syn_uncategorized(), exc_target); | ||
252 | return false; | ||
253 | } | ||
254 | |||
255 | @@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s, | ||
256 | * For the UNPREDICTABLE cases we choose to UNDEF. | ||
257 | */ | ||
258 | if (s->current_el == 1 && !s->ns && mode == ARM_CPU_MODE_MON) { | ||
259 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), 3); | ||
260 | + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, | ||
261 | + syn_uncategorized(), 3); | ||
262 | return; | ||
263 | } | ||
264 | |||
265 | @@ -XXX,XX +XXX,XX @@ static bool trans_WLS(DisasContext *s, arg_WLS *a) | ||
266 | * Do the check-and-raise-exception by hand. | ||
267 | */ | ||
268 | if (s->fp_excp_el) { | ||
269 | - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
270 | - syn_uncategorized(), s->fp_excp_el); | ||
271 | + gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, | ||
272 | + syn_uncategorized(), s->fp_excp_el); | ||
273 | return true; | ||
274 | } | ||
275 | } | ||
276 | @@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a) | ||
277 | tmp = load_cpu_field(v7m.ltpsize); | ||
278 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc); | ||
279 | tcg_temp_free_i32(tmp); | ||
280 | - gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), | ||
281 | - default_exception_el(s)); | ||
282 | + gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), | ||
283 | + default_exception_el(s)); | ||
284 | gen_set_label(skipexc); | ||
285 | } | ||
286 | |||
287 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
288 | * UsageFault exception. | ||
289 | */ | ||
290 | if (arm_dc_feature(s, ARM_FEATURE_M)) { | ||
291 | - gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), | ||
292 | - default_exception_el(s)); | ||
293 | + gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), | ||
294 | + default_exception_el(s)); | ||
295 | return; | ||
296 | } | ||
297 | |||
298 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
299 | * Illegal execution state. This has priority over BTI | ||
300 | * exceptions, but comes after instruction abort exceptions. | ||
301 | */ | ||
302 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, | ||
303 | - syn_illegalstate(), default_exception_el(s)); | ||
304 | + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, | ||
305 | + syn_illegalstate(), default_exception_el(s)); | ||
306 | return; | ||
307 | } | ||
308 | |||
309 | @@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
310 | * Illegal execution state. This has priority over BTI | ||
311 | * exceptions, but comes after instruction abort exceptions. | ||
312 | */ | ||
313 | - gen_exception_insn(dc, dc->pc_curr, EXCP_UDEF, | ||
314 | - syn_illegalstate(), default_exception_el(dc)); | ||
315 | + gen_exception_insn_el(dc, dc->pc_curr, EXCP_UDEF, | ||
316 | + syn_illegalstate(), default_exception_el(dc)); | ||
317 | return; | ||
318 | } | ||
319 | |||
320 | @@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
321 | */ | ||
322 | tcg_remove_ops_after(dc->insn_eci_rewind); | ||
323 | dc->condjmp = 0; | ||
324 | - gen_exception_insn(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategorized(), | ||
325 | - default_exception_el(dc)); | ||
326 | + gen_exception_insn_el(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategorized(), | ||
327 | + default_exception_el(dc)); | ||
328 | } | ||
329 | |||
330 | arm_post_translate_insn(dc); | ||
127 | -- | 331 | -- |
128 | 2.25.1 | 332 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Zongyuan Li <zongyuan.li@smartx.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com> | 3 | Create a new wrapper function that passes the default |
4 | exception target to gen_exception_insn_el. | ||
5 | |||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Message-id: 20220324181557.203805-2-zongyuan.li@smartx.com | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20220609202901.1177572-13-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 10 | --- |
8 | hw/arm/realview.c | 33 ++++++++++++++++++++++++--------- | 11 | target/arm/translate.h | 1 + |
9 | 1 file changed, 24 insertions(+), 9 deletions(-) | 12 | target/arm/translate-a64.c | 15 ++++++--------- |
13 | target/arm/translate-m-nocp.c | 3 +-- | ||
14 | target/arm/translate-mve.c | 3 +-- | ||
15 | target/arm/translate.c | 29 +++++++++++++---------------- | ||
16 | 5 files changed, 22 insertions(+), 29 deletions(-) | ||
10 | 17 | ||
11 | diff --git a/hw/arm/realview.c b/hw/arm/realview.c | 18 | diff --git a/target/arm/translate.h b/target/arm/translate.h |
12 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/arm/realview.c | 20 | --- a/target/arm/translate.h |
14 | +++ b/hw/arm/realview.c | 21 | +++ b/target/arm/translate.h |
15 | @@ -XXX,XX +XXX,XX @@ | 22 | @@ -XXX,XX +XXX,XX @@ MemOp pow2_align(unsigned i); |
16 | #include "hw/sysbus.h" | 23 | void unallocated_encoding(DisasContext *s); |
17 | #include "hw/arm/boot.h" | 24 | void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, |
18 | #include "hw/arm/primecell.h" | 25 | uint32_t syn, uint32_t target_el); |
19 | +#include "hw/core/split-irq.h" | 26 | +void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn); |
20 | #include "hw/net/lan9118.h" | 27 | |
21 | #include "hw/net/smc91c111.h" | 28 | /* Return state of Alternate Half-precision flag, caller frees result */ |
22 | #include "hw/pci/pci.h" | 29 | static inline TCGv_i32 get_ahp_flag(void) |
23 | +#include "hw/qdev-core.h" | 30 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
24 | #include "net/net.h" | 31 | index XXXXXXX..XXXXXXX 100644 |
25 | #include "sysemu/sysemu.h" | 32 | --- a/target/arm/translate-a64.c |
26 | #include "hw/boards.h" | 33 | +++ b/target/arm/translate-a64.c |
27 | @@ -XXX,XX +XXX,XX @@ static const int realview_board_id[] = { | 34 | @@ -XXX,XX +XXX,XX @@ static void gen_sysreg_undef(DisasContext *s, bool isread, |
28 | 0x76d | 35 | } else { |
29 | }; | 36 | syndrome = syn_uncategorized(); |
30 | 37 | } | |
31 | +static void split_irq_from_named(DeviceState *src, const char* outname, | 38 | - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syndrome, |
32 | + qemu_irq out1, qemu_irq out2) { | 39 | - default_exception_el(s)); |
33 | + DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ); | 40 | + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syndrome); |
34 | + | 41 | } |
35 | + qdev_prop_set_uint32(splitter, "num-lines", 2); | 42 | |
36 | + | 43 | /* MRS - move from system register |
37 | + qdev_realize_and_unref(splitter, NULL, &error_fatal); | 44 | @@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn) |
38 | + | 45 | switch (op2_ll) { |
39 | + qdev_connect_gpio_out(splitter, 0, out1); | 46 | case 1: /* SVC */ |
40 | + qdev_connect_gpio_out(splitter, 1, out2); | 47 | gen_ss_advance(s); |
41 | + qdev_connect_gpio_out_named(src, outname, 0, | 48 | - gen_exception_insn_el(s, s->base.pc_next, EXCP_SWI, |
42 | + qdev_get_gpio_in(splitter, 0)); | 49 | - syn_aa64_svc(imm16), default_exception_el(s)); |
50 | + gen_exception_insn(s, s->base.pc_next, EXCP_SWI, | ||
51 | + syn_aa64_svc(imm16)); | ||
52 | break; | ||
53 | case 2: /* HVC */ | ||
54 | if (s->current_el == 0) { | ||
55 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
56 | * Illegal execution state. This has priority over BTI | ||
57 | * exceptions, but comes after instruction abort exceptions. | ||
58 | */ | ||
59 | - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, | ||
60 | - syn_illegalstate(), default_exception_el(s)); | ||
61 | + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_illegalstate()); | ||
62 | return; | ||
63 | } | ||
64 | |||
65 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
66 | if (s->btype != 0 | ||
67 | && s->guarded_page | ||
68 | && !btype_destination_ok(insn, s->bt, s->btype)) { | ||
69 | - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, | ||
70 | - syn_btitrap(s->btype), | ||
71 | - default_exception_el(s)); | ||
72 | + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, | ||
73 | + syn_btitrap(s->btype)); | ||
74 | return; | ||
75 | } | ||
76 | } else { | ||
77 | diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c | ||
78 | index XXXXXXX..XXXXXXX 100644 | ||
79 | --- a/target/arm/translate-m-nocp.c | ||
80 | +++ b/target/arm/translate-m-nocp.c | ||
81 | @@ -XXX,XX +XXX,XX @@ static bool trans_NOCP(DisasContext *s, arg_nocp *a) | ||
82 | } | ||
83 | |||
84 | if (a->cp != 10) { | ||
85 | - gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, | ||
86 | - syn_uncategorized(), default_exception_el(s)); | ||
87 | + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized()); | ||
88 | return true; | ||
89 | } | ||
90 | |||
91 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
92 | index XXXXXXX..XXXXXXX 100644 | ||
93 | --- a/target/arm/translate-mve.c | ||
94 | +++ b/target/arm/translate-mve.c | ||
95 | @@ -XXX,XX +XXX,XX @@ bool mve_eci_check(DisasContext *s) | ||
96 | return true; | ||
97 | default: | ||
98 | /* Reserved value: INVSTATE UsageFault */ | ||
99 | - gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), | ||
100 | - default_exception_el(s)); | ||
101 | + gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized()); | ||
102 | return false; | ||
103 | } | ||
104 | } | ||
105 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
106 | index XXXXXXX..XXXXXXX 100644 | ||
107 | --- a/target/arm/translate.c | ||
108 | +++ b/target/arm/translate.c | ||
109 | @@ -XXX,XX +XXX,XX @@ void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, | ||
110 | gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el)); | ||
111 | } | ||
112 | |||
113 | +void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn) | ||
114 | +{ | ||
115 | + gen_exception_insn_el(s, pc, excp, syn, default_exception_el(s)); | ||
43 | +} | 116 | +} |
44 | + | 117 | + |
45 | static void realview_init(MachineState *machine, | 118 | static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) |
46 | enum realview_board_type board_type) | ||
47 | { | 119 | { |
48 | @@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine, | 120 | gen_set_condexec(s); |
49 | DeviceState *dev, *sysctl, *gpio2, *pl041; | 121 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) |
50 | SysBusDevice *busdev; | 122 | void unallocated_encoding(DisasContext *s) |
51 | qemu_irq pic[64]; | 123 | { |
52 | - qemu_irq mmc_irq[2]; | 124 | /* Unallocated and reserved encodings are uncategorized */ |
53 | PCIBus *pci_bus = NULL; | 125 | - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), |
54 | NICInfo *nd; | 126 | - default_exception_el(s)); |
55 | DriveInfo *dinfo; | 127 | + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized()); |
56 | @@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine, | 128 | } |
57 | * and the PL061 has them the other way about. Also the card | 129 | |
58 | * detect line is inverted. | 130 | /* Force a TB lookup after an instruction that changes the CPU state. */ |
131 | @@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, | ||
132 | * an exception and return false. Otherwise it will return true, | ||
133 | * and set *tgtmode and *regno appropriately. | ||
59 | */ | 134 | */ |
60 | - mmc_irq[0] = qemu_irq_split( | 135 | - int exc_target = default_exception_el(s); |
61 | - qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), | 136 | - |
62 | - qdev_get_gpio_in(gpio2, 1)); | 137 | /* These instructions are present only in ARMv8, or in ARMv7 with the |
63 | - mmc_irq[1] = qemu_irq_split( | 138 | * Virtualization Extensions. |
64 | - qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), | 139 | */ |
65 | - qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); | 140 | @@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, |
66 | - qdev_connect_gpio_out_named(dev, "card-read-only", 0, mmc_irq[0]); | 141 | |
67 | - qdev_connect_gpio_out_named(dev, "card-inserted", 0, mmc_irq[1]); | 142 | undef: |
68 | + split_irq_from_named(dev, "card-read-only", | 143 | /* If we get here then some access check did not pass */ |
69 | + qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), | 144 | - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, |
70 | + qdev_get_gpio_in(gpio2, 1)); | 145 | - syn_uncategorized(), exc_target); |
71 | + | 146 | + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized()); |
72 | + split_irq_from_named(dev, "card-inserted", | 147 | return false; |
73 | + qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), | 148 | } |
74 | + qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); | 149 | |
75 | + | 150 | @@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a) |
76 | dinfo = drive_get(IF_SD, 0, 0); | 151 | tmp = load_cpu_field(v7m.ltpsize); |
77 | if (dinfo) { | 152 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc); |
78 | DeviceState *card; | 153 | tcg_temp_free_i32(tmp); |
154 | - gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), | ||
155 | - default_exception_el(s)); | ||
156 | + gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized()); | ||
157 | gen_set_label(skipexc); | ||
158 | } | ||
159 | |||
160 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
161 | * UsageFault exception. | ||
162 | */ | ||
163 | if (arm_dc_feature(s, ARM_FEATURE_M)) { | ||
164 | - gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), | ||
165 | - default_exception_el(s)); | ||
166 | + gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized()); | ||
167 | return; | ||
168 | } | ||
169 | |||
170 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
171 | * Illegal execution state. This has priority over BTI | ||
172 | * exceptions, but comes after instruction abort exceptions. | ||
173 | */ | ||
174 | - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, | ||
175 | - syn_illegalstate(), default_exception_el(s)); | ||
176 | + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_illegalstate()); | ||
177 | return; | ||
178 | } | ||
179 | |||
180 | @@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
181 | * Illegal execution state. This has priority over BTI | ||
182 | * exceptions, but comes after instruction abort exceptions. | ||
183 | */ | ||
184 | - gen_exception_insn_el(dc, dc->pc_curr, EXCP_UDEF, | ||
185 | - syn_illegalstate(), default_exception_el(dc)); | ||
186 | + gen_exception_insn(dc, dc->pc_curr, EXCP_UDEF, syn_illegalstate()); | ||
187 | return; | ||
188 | } | ||
189 | |||
190 | @@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
191 | */ | ||
192 | tcg_remove_ops_after(dc->insn_eci_rewind); | ||
193 | dc->condjmp = 0; | ||
194 | - gen_exception_insn_el(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategorized(), | ||
195 | - default_exception_el(dc)); | ||
196 | + gen_exception_insn(dc, dc->pc_curr, EXCP_INVSTATE, | ||
197 | + syn_uncategorized()); | ||
198 | } | ||
199 | |||
200 | arm_post_translate_insn(dc); | ||
79 | -- | 201 | -- |
80 | 2.25.1 | 202 | 2.25.1 | diff view generated by jsdifflib |
1 | At this point, the function exynos4210_init_board_irqs() splits input | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | IRQ lines to connect them to the input combiner, output combiner and | ||
3 | external GIC. The function exynos4210_combiner_get_gpioin() splits | ||
4 | some of the combiner input lines further to connect them to multiple | ||
5 | different inputs on the combiner. | ||
6 | 2 | ||
7 | Because (unlike qemu_irq_split()) the TYPE_SPLIT_IRQ device has a | 3 | Move the computation from gen_swstep_exception into a helper. |
8 | configurable number of outputs, we can do all this in one place, by | ||
9 | making exynos4210_init_board_irqs() add extra outputs to the splitter | ||
10 | device when it must be connected to more than one input on each | ||
11 | combiner. | ||
12 | 4 | ||
13 | We do this with a new data structure, the combinermap, which is an | 5 | This fixes a bug when: |
14 | array each of whose elements is a list of the interrupt IDs on the | 6 | - MDSCR_EL1.KDE == 1 to enable debug exceptions within EL_D itself |
15 | combiner which must be tied together. As we loop through each | 7 | - we singlestep an ERET from EL_D to some lower EL |
16 | interrupt ID, if we find that it is the first one in one of these | ||
17 | lists, we configure the splitter device with eonugh extra outputs and | ||
18 | wire them up to the other interrupt IDs in the list. | ||
19 | 8 | ||
20 | Conveniently, for all the cases where this is necessary, the | 9 | Previously we were computing 'same el' based on the EL which |
21 | lowest-numbered interrupt ID in each group is in the range of the | 10 | executed the ERET instruction, whereas it ought to be computed |
22 | external combiner, so we only need to code for this in the first of | 11 | based on the EL to which ERET returned. This happens naturally |
23 | the two loops in exynos4210_init_board_irqs(). | 12 | with the new helper, which runs after EL has been changed. |
24 | 13 | ||
25 | The old code in exynos4210_combiner_get_gpioin() which is being | 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
26 | deleted here had several problems which don't exist in the new code | 15 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
27 | in its handling of the multi-core timer interrupts: | 16 | Message-id: 20220609202901.1177572-14-richard.henderson@linaro.org |
28 | (1) the case labels specified bits 4 ... 8, but bit '8' doesn't | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
29 | exist; these should have been 4 ... 7 | 18 | --- |
30 | (2) it used the input irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)] | 19 | target/arm/helper.h | 1 + |
31 | multiple times as the input of several different splitters, | 20 | target/arm/translate.h | 12 +++--------- |
32 | which isn't allowed | 21 | target/arm/debug_helper.c | 16 ++++++++++++++++ |
33 | (3) in an apparent cut-and-paste error, the cases for all the | 22 | 3 files changed, 20 insertions(+), 9 deletions(-) |
34 | multi-core timer inputs used "bit + 4" even though the | ||
35 | bit range for the case was (intended to be) 4 ... 7, which | ||
36 | meant it was looking at non-existent bits 8 ... 11. | ||
37 | None of these exist in the new code. | ||
38 | 23 | ||
39 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 24 | diff --git a/target/arm/helper.h b/target/arm/helper.h |
40 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
41 | Message-id: 20220404154658.565020-17-peter.maydell@linaro.org | ||
42 | --- | ||
43 | include/hw/arm/exynos4210.h | 6 +- | ||
44 | hw/arm/exynos4210.c | 178 +++++++++++++++++++++++------------- | ||
45 | 2 files changed, 119 insertions(+), 65 deletions(-) | ||
46 | |||
47 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | ||
48 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
49 | --- a/include/hw/arm/exynos4210.h | 26 | --- a/target/arm/helper.h |
50 | +++ b/include/hw/arm/exynos4210.h | 27 | +++ b/target/arm/helper.h |
51 | @@ -XXX,XX +XXX,XX @@ | 28 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, |
29 | DEF_HELPER_2(exception_internal, noreturn, env, i32) | ||
30 | DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) | ||
31 | DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) | ||
32 | +DEF_HELPER_2(exception_swstep, noreturn, env, i32) | ||
33 | DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) | ||
34 | DEF_HELPER_1(setend, void, env) | ||
35 | DEF_HELPER_2(wfi, void, env, i32) | ||
36 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/target/arm/translate.h | ||
39 | +++ b/target/arm/translate.h | ||
40 | @@ -XXX,XX +XXX,XX @@ static inline void gen_exception(int excp, uint32_t syndrome, | ||
41 | /* Generate an architectural singlestep exception */ | ||
42 | static inline void gen_swstep_exception(DisasContext *s, int isv, int ex) | ||
43 | { | ||
44 | - bool same_el = (s->debug_target_el == s->current_el); | ||
45 | - | ||
46 | - /* | ||
47 | - * If singlestep is targeting a lower EL than the current one, | ||
48 | - * then s->ss_active must be false and we can never get here. | ||
49 | - */ | ||
50 | - assert(s->debug_target_el >= s->current_el); | ||
51 | - | ||
52 | - gen_exception(EXCP_UDEF, syn_swstep(same_el, isv, ex), s->debug_target_el); | ||
53 | + /* Fill in the same_el field of the syndrome in the helper. */ | ||
54 | + uint32_t syn = syn_swstep(false, isv, ex); | ||
55 | + gen_helper_exception_swstep(cpu_env, tcg_constant_i32(syn)); | ||
56 | } | ||
52 | 57 | ||
53 | /* | 58 | /* |
54 | * We need one splitter for every external combiner input, plus | 59 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c |
55 | - * one for every non-zero entry in combiner_grp_to_gic_id[]. | ||
56 | + * one for every non-zero entry in combiner_grp_to_gic_id[], | ||
57 | + * minus one for every external combiner ID in second or later | ||
58 | + * places in a combinermap[] line. | ||
59 | * We'll assert in exynos4210_init_board_irqs() if this is wrong. | ||
60 | */ | ||
61 | -#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 54) | ||
62 | +#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38) | ||
63 | |||
64 | typedef struct Exynos4210Irq { | ||
65 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
66 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | 60 | index XXXXXXX..XXXXXXX 100644 |
68 | --- a/hw/arm/exynos4210.c | 61 | --- a/target/arm/debug_helper.c |
69 | +++ b/hw/arm/exynos4210.c | 62 | +++ b/target/arm/debug_helper.c |
70 | @@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | 63 | @@ -XXX,XX +XXX,XX @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) |
71 | #define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ | 64 | raise_exception(env, EXCP_BKPT, syndrome, debug_el); |
72 | ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) | 65 | } |
73 | 66 | ||
74 | +/* | 67 | +void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome) |
75 | + * Some interrupt lines go to multiple combiner inputs. | 68 | +{ |
76 | + * This data structure defines those: each array element is | 69 | + int debug_el = arm_debug_target_el(env); |
77 | + * a list of combiner inputs which are connected together; | 70 | + int cur_el = arm_current_el(env); |
78 | + * the one with the smallest interrupt ID value must be first. | ||
79 | + * As with combiner_grp_to_gic_id[], we rely on (0, 0) not being | ||
80 | + * wired to anything so we can use 0 as a terminator. | ||
81 | + */ | ||
82 | +#define IRQNO(G, B) EXYNOS4210_COMBINER_GET_IRQ_NUM(G, B) | ||
83 | +#define IRQNONE 0 | ||
84 | + | 71 | + |
85 | +#define COMBINERMAP_SIZE 16 | ||
86 | + | ||
87 | +static const int combinermap[COMBINERMAP_SIZE][6] = { | ||
88 | + /* MDNIE_LCD1 */ | ||
89 | + { IRQNO(0, 4), IRQNO(1, 0), IRQNONE }, | ||
90 | + { IRQNO(0, 5), IRQNO(1, 1), IRQNONE }, | ||
91 | + { IRQNO(0, 6), IRQNO(1, 2), IRQNONE }, | ||
92 | + { IRQNO(0, 7), IRQNO(1, 3), IRQNONE }, | ||
93 | + /* TMU */ | ||
94 | + { IRQNO(2, 4), IRQNO(3, 4), IRQNONE }, | ||
95 | + { IRQNO(2, 5), IRQNO(3, 5), IRQNONE }, | ||
96 | + { IRQNO(2, 6), IRQNO(3, 6), IRQNONE }, | ||
97 | + { IRQNO(2, 7), IRQNO(3, 7), IRQNONE }, | ||
98 | + /* LCD1 */ | ||
99 | + { IRQNO(11, 4), IRQNO(12, 0), IRQNONE }, | ||
100 | + { IRQNO(11, 5), IRQNO(12, 1), IRQNONE }, | ||
101 | + { IRQNO(11, 6), IRQNO(12, 2), IRQNONE }, | ||
102 | + { IRQNO(11, 7), IRQNO(12, 3), IRQNONE }, | ||
103 | + /* Multi-core timer */ | ||
104 | + { IRQNO(1, 4), IRQNO(12, 4), IRQNO(35, 4), IRQNO(51, 4), IRQNO(53, 4), IRQNONE }, | ||
105 | + { IRQNO(1, 5), IRQNO(12, 5), IRQNO(35, 5), IRQNO(51, 5), IRQNO(53, 5), IRQNONE }, | ||
106 | + { IRQNO(1, 6), IRQNO(12, 6), IRQNO(35, 6), IRQNO(51, 6), IRQNO(53, 6), IRQNONE }, | ||
107 | + { IRQNO(1, 7), IRQNO(12, 7), IRQNO(35, 7), IRQNO(51, 7), IRQNO(53, 7), IRQNONE }, | ||
108 | +}; | ||
109 | + | ||
110 | +#undef IRQNO | ||
111 | + | ||
112 | +static const int *combinermap_entry(int irq) | ||
113 | +{ | ||
114 | + /* | 72 | + /* |
115 | + * If the interrupt number passed in is the first entry in some | 73 | + * If singlestep is targeting a lower EL than the current one, then |
116 | + * line of the combinermap, return a pointer to that line; | 74 | + * DisasContext.ss_active must be false and we can never get here. |
117 | + * otherwise return NULL. | ||
118 | + */ | 75 | + */ |
119 | + int i; | 76 | + assert(debug_el >= cur_el); |
120 | + for (i = 0; i < COMBINERMAP_SIZE; i++) { | 77 | + if (debug_el == cur_el) { |
121 | + if (combinermap[i][0] == irq) { | 78 | + syndrome |= 1 << ARM_EL_EC_SHIFT; |
122 | + return combinermap[i]; | ||
123 | + } | ||
124 | + } | 79 | + } |
125 | + return NULL; | 80 | + raise_exception(env, EXCP_UDEF, syndrome, debug_el); |
126 | +} | 81 | +} |
127 | + | 82 | + |
128 | +static int mapline_size(const int *mapline) | 83 | #if !defined(CONFIG_USER_ONLY) |
129 | +{ | 84 | |
130 | + /* Return number of entries in this mapline in total */ | 85 | vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) |
131 | + int i = 0; | ||
132 | + | ||
133 | + if (!mapline) { | ||
134 | + /* Not in the map? IRQ goes to exactly one combiner input */ | ||
135 | + return 1; | ||
136 | + } | ||
137 | + while (*mapline != IRQNONE) { | ||
138 | + mapline++; | ||
139 | + i++; | ||
140 | + } | ||
141 | + return i; | ||
142 | +} | ||
143 | + | ||
144 | /* | ||
145 | * Initialize board IRQs. | ||
146 | * These IRQs contain splitted Int/External Combiner and External Gic IRQs. | ||
147 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
148 | DeviceState *extgicdev = DEVICE(&s->ext_gic); | ||
149 | int splitcount = 0; | ||
150 | DeviceState *splitter; | ||
151 | + const int *mapline; | ||
152 | + int numlines, splitin, in; | ||
153 | |||
154 | for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { | ||
155 | irq_id = 0; | ||
156 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
157 | irq_id = EXT_GIC_ID_MCT_G1; | ||
158 | } | ||
159 | |||
160 | + if (s->irq_table[n]) { | ||
161 | + /* | ||
162 | + * This must be some non-first entry in a combinermap line, | ||
163 | + * and we've already filled it in. | ||
164 | + */ | ||
165 | + continue; | ||
166 | + } | ||
167 | + mapline = combinermap_entry(n); | ||
168 | + /* | ||
169 | + * We need to connect the IRQ to multiple inputs on both combiners | ||
170 | + * and possibly also to the external GIC. | ||
171 | + */ | ||
172 | + numlines = 2 * mapline_size(mapline); | ||
173 | + if (irq_id) { | ||
174 | + numlines++; | ||
175 | + } | ||
176 | assert(splitcount < EXYNOS4210_NUM_SPLITTERS); | ||
177 | splitter = DEVICE(&s->splitter[splitcount]); | ||
178 | - qdev_prop_set_uint16(splitter, "num-lines", irq_id ? 3 : 2); | ||
179 | + qdev_prop_set_uint16(splitter, "num-lines", numlines); | ||
180 | qdev_realize(splitter, NULL, &error_abort); | ||
181 | splitcount++; | ||
182 | - s->irq_table[n] = qdev_get_gpio_in(splitter, 0); | ||
183 | - qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); | ||
184 | - qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]); | ||
185 | + | ||
186 | + in = n; | ||
187 | + splitin = 0; | ||
188 | + for (;;) { | ||
189 | + s->irq_table[in] = qdev_get_gpio_in(splitter, 0); | ||
190 | + qdev_connect_gpio_out(splitter, splitin, is->int_combiner_irq[in]); | ||
191 | + qdev_connect_gpio_out(splitter, splitin + 1, is->ext_combiner_irq[in]); | ||
192 | + splitin += 2; | ||
193 | + if (!mapline) { | ||
194 | + break; | ||
195 | + } | ||
196 | + mapline++; | ||
197 | + in = *mapline; | ||
198 | + if (in == IRQNONE) { | ||
199 | + break; | ||
200 | + } | ||
201 | + } | ||
202 | if (irq_id) { | ||
203 | - qdev_connect_gpio_out(splitter, 2, | ||
204 | + qdev_connect_gpio_out(splitter, splitin, | ||
205 | qdev_get_gpio_in(extgicdev, irq_id - 32)); | ||
206 | } | ||
207 | } | ||
208 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
209 | irq_id = combiner_grp_to_gic_id[grp - | ||
210 | EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; | ||
211 | |||
212 | + if (s->irq_table[n]) { | ||
213 | + /* | ||
214 | + * This must be some non-first entry in a combinermap line, | ||
215 | + * and we've already filled it in. | ||
216 | + */ | ||
217 | + continue; | ||
218 | + } | ||
219 | + | ||
220 | if (irq_id) { | ||
221 | assert(splitcount < EXYNOS4210_NUM_SPLITTERS); | ||
222 | splitter = DEVICE(&s->splitter[splitcount]); | ||
223 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, | ||
224 | DeviceState *dev, int ext) | ||
225 | { | ||
226 | int n; | ||
227 | - int bit; | ||
228 | int max; | ||
229 | qemu_irq *irq; | ||
230 | |||
231 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, | ||
232 | EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; | ||
233 | irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq; | ||
234 | |||
235 | - /* | ||
236 | - * Some IRQs of Int/External Combiner are going to two Combiners groups, | ||
237 | - * so let split them. | ||
238 | - */ | ||
239 | for (n = 0; n < max; n++) { | ||
240 | - | ||
241 | - bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); | ||
242 | - | ||
243 | - switch (n) { | ||
244 | - /* MDNIE_LCD1 INTG1 */ | ||
245 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ... | ||
246 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3): | ||
247 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
248 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]); | ||
249 | - continue; | ||
250 | - | ||
251 | - /* TMU INTG3 */ | ||
252 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4): | ||
253 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
254 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]); | ||
255 | - continue; | ||
256 | - | ||
257 | - /* LCD1 INTG12 */ | ||
258 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ... | ||
259 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3): | ||
260 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
261 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]); | ||
262 | - continue; | ||
263 | - | ||
264 | - /* Multi-Core Timer INTG12 */ | ||
265 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ... | ||
266 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8): | ||
267 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
268 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
269 | - continue; | ||
270 | - | ||
271 | - /* Multi-Core Timer INTG35 */ | ||
272 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ... | ||
273 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8): | ||
274 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
275 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
276 | - continue; | ||
277 | - | ||
278 | - /* Multi-Core Timer INTG51 */ | ||
279 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ... | ||
280 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8): | ||
281 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
282 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
283 | - continue; | ||
284 | - | ||
285 | - /* Multi-Core Timer INTG53 */ | ||
286 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ... | ||
287 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8): | ||
288 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
289 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
290 | - continue; | ||
291 | - } | ||
292 | - | ||
293 | irq[n] = qdev_get_gpio_in(dev, n); | ||
294 | } | ||
295 | } | ||
296 | -- | 86 | -- |
297 | 2.25.1 | 87 | 2.25.1 | diff view generated by jsdifflib |
1 | The exynos4210 code currently has two very similar arrays of IRQs: | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | * board_irqs is a field of the Exynos4210Irq struct which is filled | 3 | We no longer need this value during translation, |
4 | in by exynos4210_init_board_irqs() with the appropriate qemu_irqs | 4 | as it is now handled within the helpers. |
5 | for each IRQ the board/SoC can assert | ||
6 | * irq_table is a set of qemu_irqs pointed to from the | ||
7 | Exynos4210State struct. It's allocated in exynos4210_init_irq, | ||
8 | and the only behaviour these irqs have is that they pass on the | ||
9 | level to the equivalent board_irqs[] irq | ||
10 | 5 | ||
11 | The extra indirection through irq_table is unnecessary, so coalesce | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
12 | these into a single irq_table[] array as a direct field in | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
13 | Exynos4210State which exynos4210_init_board_irqs() fills in. | 8 | Message-id: 20220609202901.1177572-15-richard.henderson@linaro.org |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/cpu.h | 6 ++---- | ||
12 | target/arm/translate.h | 2 -- | ||
13 | target/arm/helper.c | 12 ++---------- | ||
14 | target/arm/translate-a64.c | 1 - | ||
15 | target/arm/translate.c | 1 - | ||
16 | 5 files changed, 4 insertions(+), 18 deletions(-) | ||
14 | 17 | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
17 | Message-id: 20220404154658.565020-6-peter.maydell@linaro.org | ||
18 | --- | ||
19 | include/hw/arm/exynos4210.h | 8 ++------ | ||
20 | hw/arm/exynos4210.c | 6 +----- | ||
21 | hw/intc/exynos4210_gic.c | 32 ++++++++------------------------ | ||
22 | 3 files changed, 11 insertions(+), 35 deletions(-) | ||
23 | |||
24 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | ||
25 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/include/hw/arm/exynos4210.h | 20 | --- a/target/arm/cpu.h |
27 | +++ b/include/hw/arm/exynos4210.h | 21 | +++ b/target/arm/cpu.h |
28 | @@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq { | 22 | @@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_ANY, BE_DATA, 3, 1) |
29 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | 23 | FIELD(TBFLAG_ANY, MMUIDX, 4, 4) |
30 | qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; | 24 | /* Target EL if we take a floating-point-disabled exception */ |
31 | qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ]; | 25 | FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) |
32 | - qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | 26 | -/* For A-profile only, target EL for debug exceptions. */ |
33 | } Exynos4210Irq; | 27 | -FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2) |
34 | 28 | /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ | |
35 | struct Exynos4210State { | 29 | -FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1) |
36 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { | 30 | -FIELD(TBFLAG_ANY, PSTATE__IL, 13, 1) |
37 | /*< public >*/ | 31 | +FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) |
38 | ARMCPU *cpu[EXYNOS4210_NCPUS]; | 32 | +FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) |
39 | Exynos4210Irq irqs; | 33 | |
40 | - qemu_irq *irq_table; | 34 | /* |
41 | + qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | 35 | * Bit usage when in AArch32 state, both A- and M-profile. |
42 | 36 | diff --git a/target/arm/translate.h b/target/arm/translate.h | |
43 | MemoryRegion chipid_mem; | 37 | index XXXXXXX..XXXXXXX 100644 |
44 | MemoryRegion iram_mem; | 38 | --- a/target/arm/translate.h |
45 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC) | 39 | +++ b/target/arm/translate.h |
46 | void exynos4210_write_secondary(ARMCPU *cpu, | 40 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { |
47 | const struct arm_boot_info *info); | 41 | */ |
48 | 42 | uint32_t svc_imm; | |
49 | -/* Initialize exynos4210 IRQ subsystem stub */ | 43 | int current_el; |
50 | -qemu_irq *exynos4210_init_irq(Exynos4210Irq *env); | 44 | - /* Debug target exception level for single-step exceptions */ |
45 | - int debug_target_el; | ||
46 | GHashTable *cp_regs; | ||
47 | uint64_t features; /* CPU features bits */ | ||
48 | bool aarch64; | ||
49 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
50 | index XXXXXXX..XXXXXXX 100644 | ||
51 | --- a/target/arm/helper.c | ||
52 | +++ b/target/arm/helper.c | ||
53 | @@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el, | ||
54 | return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); | ||
55 | } | ||
56 | |||
57 | -static CPUARMTBFlags rebuild_hflags_aprofile(CPUARMState *env) | ||
58 | -{ | ||
59 | - CPUARMTBFlags flags = {}; | ||
51 | - | 60 | - |
52 | /* Initialize board IRQs. | 61 | - DP_TBFLAG_ANY(flags, DEBUG_TARGET_EL, arm_debug_target_el(env)); |
53 | * These IRQs contain splitted Int/External Combiner and External Gic IRQs */ | 62 | - return flags; |
54 | -void exynos4210_init_board_irqs(Exynos4210Irq *s); | ||
55 | +void exynos4210_init_board_irqs(Exynos4210State *s); | ||
56 | |||
57 | /* Get IRQ number from exynos4210 IRQ subsystem stub. | ||
58 | * To identify IRQ source use internal combiner group and bit number | ||
59 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
60 | index XXXXXXX..XXXXXXX 100644 | ||
61 | --- a/hw/arm/exynos4210.c | ||
62 | +++ b/hw/arm/exynos4210.c | ||
63 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
64 | qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); | ||
65 | } | ||
66 | |||
67 | - /*** IRQs ***/ | ||
68 | - | ||
69 | - s->irq_table = exynos4210_init_irq(&s->irqs); | ||
70 | - | ||
71 | /* IRQ Gate */ | ||
72 | for (i = 0; i < EXYNOS4210_NCPUS; i++) { | ||
73 | DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]); | ||
74 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
75 | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); | ||
76 | |||
77 | /* Initialize board IRQs. */ | ||
78 | - exynos4210_init_board_irqs(&s->irqs); | ||
79 | + exynos4210_init_board_irqs(s); | ||
80 | |||
81 | /*** Memory ***/ | ||
82 | |||
83 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | ||
84 | index XXXXXXX..XXXXXXX 100644 | ||
85 | --- a/hw/intc/exynos4210_gic.c | ||
86 | +++ b/hw/intc/exynos4210_gic.c | ||
87 | @@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
88 | #define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100 | ||
89 | #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000 | ||
90 | |||
91 | -static void exynos4210_irq_handler(void *opaque, int irq, int level) | ||
92 | -{ | ||
93 | - Exynos4210Irq *s = (Exynos4210Irq *)opaque; | ||
94 | - | ||
95 | - /* Bypass */ | ||
96 | - qemu_set_irq(s->board_irqs[irq], level); | ||
97 | -} | 63 | -} |
98 | - | 64 | - |
99 | -/* | 65 | static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, |
100 | - * Initialize exynos4210 IRQ subsystem stub. | 66 | ARMMMUIdx mmu_idx) |
101 | - */ | ||
102 | -qemu_irq *exynos4210_init_irq(Exynos4210Irq *s) | ||
103 | -{ | ||
104 | - return qemu_allocate_irqs(exynos4210_irq_handler, s, | ||
105 | - EXYNOS4210_MAX_INT_COMBINER_IN_IRQ); | ||
106 | -} | ||
107 | - | ||
108 | /* | ||
109 | * Initialize board IRQs. | ||
110 | * These IRQs contain splitted Int/External Combiner and External Gic IRQs. | ||
111 | */ | ||
112 | -void exynos4210_init_board_irqs(Exynos4210Irq *s) | ||
113 | +void exynos4210_init_board_irqs(Exynos4210State *s) | ||
114 | { | 67 | { |
115 | uint32_t grp, bit, irq_id, n; | 68 | - CPUARMTBFlags flags = rebuild_hflags_aprofile(env); |
116 | + Exynos4210Irq *is = &s->irqs; | 69 | + CPUARMTBFlags flags = {}; |
117 | 70 | int el = arm_current_el(env); | |
118 | for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { | 71 | |
119 | irq_id = 0; | 72 | if (arm_sctlr(env, el) & SCTLR_A) { |
120 | @@ -XXX,XX +XXX,XX @@ void exynos4210_init_board_irqs(Exynos4210Irq *s) | 73 | @@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, |
121 | irq_id = EXT_GIC_ID_MCT_G1; | 74 | static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, |
122 | } | 75 | ARMMMUIdx mmu_idx) |
123 | if (irq_id) { | 76 | { |
124 | - s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n], | 77 | - CPUARMTBFlags flags = rebuild_hflags_aprofile(env); |
125 | - s->ext_gic_irq[irq_id-32]); | 78 | + CPUARMTBFlags flags = {}; |
126 | + s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | 79 | ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); |
127 | + is->ext_gic_irq[irq_id - 32]); | 80 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; |
128 | } else { | 81 | uint64_t sctlr; |
129 | - s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n], | 82 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
130 | - s->ext_combiner_irq[n]); | 83 | index XXXXXXX..XXXXXXX 100644 |
131 | + s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | 84 | --- a/target/arm/translate-a64.c |
132 | + is->ext_combiner_irq[n]); | 85 | +++ b/target/arm/translate-a64.c |
133 | } | 86 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, |
134 | } | 87 | dc->ss_active = EX_TBFLAG_ANY(tb_flags, SS_ACTIVE); |
135 | for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { | 88 | dc->pstate_ss = EX_TBFLAG_ANY(tb_flags, PSTATE__SS); |
136 | @@ -XXX,XX +XXX,XX @@ void exynos4210_init_board_irqs(Exynos4210Irq *s) | 89 | dc->is_ldex = false; |
137 | EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; | 90 | - dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL); |
138 | 91 | ||
139 | if (irq_id) { | 92 | /* Bound the number of insns to execute to those left on the page. */ |
140 | - s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n], | 93 | bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; |
141 | - s->ext_gic_irq[irq_id-32]); | 94 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
142 | + s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | 95 | index XXXXXXX..XXXXXXX 100644 |
143 | + is->ext_gic_irq[irq_id - 32]); | 96 | --- a/target/arm/translate.c |
144 | } | 97 | +++ b/target/arm/translate.c |
145 | } | 98 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) |
146 | } | 99 | dc->v7m_lspact = EX_TBFLAG_M32(tb_flags, LSPACT); |
100 | dc->mve_no_pred = EX_TBFLAG_M32(tb_flags, MVE_NO_PRED); | ||
101 | } else { | ||
102 | - dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL); | ||
103 | dc->sctlr_b = EX_TBFLAG_A32(tb_flags, SCTLR__B); | ||
104 | dc->hstr_active = EX_TBFLAG_A32(tb_flags, HSTR_ACTIVE); | ||
105 | dc->ns = EX_TBFLAG_A32(tb_flags, NS); | ||
147 | -- | 106 | -- |
148 | 2.25.1 | 107 | 2.25.1 | diff view generated by jsdifflib |
1 | From: "Edgar E. Iglesias" <edgar.iglesias@amd.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Add the Cortex-R5Fs of the Versal RPU (Real-time Processing Unit) | 3 | This function is not required by any other translation file. |
4 | subsystem. | ||
5 | 4 | ||
6 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> | 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20220406174303.2022038-3-edgar.iglesias@xilinx.com | 7 | Message-id: 20220609202901.1177572-16-richard.henderson@linaro.org |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 9 | --- |
11 | include/hw/arm/xlnx-versal.h | 10 ++++++++++ | 10 | target/arm/translate.h | 8 -------- |
12 | hw/arm/xlnx-versal-virt.c | 6 +++--- | 11 | target/arm/translate.c | 7 +++++++ |
13 | hw/arm/xlnx-versal.c | 36 ++++++++++++++++++++++++++++++++++++ | 12 | 2 files changed, 7 insertions(+), 8 deletions(-) |
14 | 3 files changed, 49 insertions(+), 3 deletions(-) | ||
15 | 13 | ||
16 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h | 14 | diff --git a/target/arm/translate.h b/target/arm/translate.h |
17 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/arm/xlnx-versal.h | 16 | --- a/target/arm/translate.h |
19 | +++ b/include/hw/arm/xlnx-versal.h | 17 | +++ b/target/arm/translate.h |
20 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ static inline void gen_ss_advance(DisasContext *s) |
21 | OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) | ||
22 | |||
23 | #define XLNX_VERSAL_NR_ACPUS 2 | ||
24 | +#define XLNX_VERSAL_NR_RCPUS 2 | ||
25 | #define XLNX_VERSAL_NR_UARTS 2 | ||
26 | #define XLNX_VERSAL_NR_GEMS 2 | ||
27 | #define XLNX_VERSAL_NR_ADMAS 8 | ||
28 | @@ -XXX,XX +XXX,XX @@ struct Versal { | ||
29 | VersalUsb2 usb; | ||
30 | } iou; | ||
31 | |||
32 | + /* Real-time Processing Unit. */ | ||
33 | + struct { | ||
34 | + MemoryRegion mr; | ||
35 | + MemoryRegion mr_ps_alias; | ||
36 | + | ||
37 | + CPUClusterState cluster; | ||
38 | + ARMCPU cpu[XLNX_VERSAL_NR_RCPUS]; | ||
39 | + } rpu; | ||
40 | + | ||
41 | struct { | ||
42 | qemu_or_irq irq_orgate; | ||
43 | XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; | ||
44 | diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/hw/arm/xlnx-versal-virt.c | ||
47 | +++ b/hw/arm/xlnx-versal-virt.c | ||
48 | @@ -XXX,XX +XXX,XX @@ static void versal_virt_machine_class_init(ObjectClass *oc, void *data) | ||
49 | |||
50 | mc->desc = "Xilinx Versal Virtual development board"; | ||
51 | mc->init = versal_virt_init; | ||
52 | - mc->min_cpus = XLNX_VERSAL_NR_ACPUS; | ||
53 | - mc->max_cpus = XLNX_VERSAL_NR_ACPUS; | ||
54 | - mc->default_cpus = XLNX_VERSAL_NR_ACPUS; | ||
55 | + mc->min_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS; | ||
56 | + mc->max_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS; | ||
57 | + mc->default_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS; | ||
58 | mc->no_cdrom = true; | ||
59 | mc->default_ram_id = "ddr"; | ||
60 | } | ||
61 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/hw/arm/xlnx-versal.c | ||
64 | +++ b/hw/arm/xlnx-versal.c | ||
65 | @@ -XXX,XX +XXX,XX @@ | ||
66 | #include "hw/sysbus.h" | ||
67 | |||
68 | #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") | ||
69 | +#define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") | ||
70 | #define GEM_REVISION 0x40070106 | ||
71 | |||
72 | #define VERSAL_NUM_PMC_APB_IRQS 3 | ||
73 | @@ -XXX,XX +XXX,XX @@ static void versal_create_apu_gic(Versal *s, qemu_irq *pic) | ||
74 | } | 19 | } |
75 | } | 20 | } |
76 | 21 | ||
77 | +static void versal_create_rpu_cpus(Versal *s) | 22 | -static inline void gen_exception(int excp, uint32_t syndrome, |
23 | - uint32_t target_el) | ||
24 | -{ | ||
25 | - gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), | ||
26 | - tcg_constant_i32(syndrome), | ||
27 | - tcg_constant_i32(target_el)); | ||
28 | -} | ||
29 | - | ||
30 | /* Generate an architectural singlestep exception */ | ||
31 | static inline void gen_swstep_exception(DisasContext *s, int isv, int ex) | ||
32 | { | ||
33 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/target/arm/translate.c | ||
36 | +++ b/target/arm/translate.c | ||
37 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp) | ||
38 | s->base.is_jmp = DISAS_NORETURN; | ||
39 | } | ||
40 | |||
41 | +static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) | ||
78 | +{ | 42 | +{ |
79 | + int i; | 43 | + gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), |
80 | + | 44 | + tcg_constant_i32(syndrome), |
81 | + object_initialize_child(OBJECT(s), "rpu-cluster", &s->lpd.rpu.cluster, | 45 | + tcg_constant_i32(target_el)); |
82 | + TYPE_CPU_CLUSTER); | ||
83 | + qdev_prop_set_uint32(DEVICE(&s->lpd.rpu.cluster), "cluster-id", 1); | ||
84 | + | ||
85 | + for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) { | ||
86 | + Object *obj; | ||
87 | + | ||
88 | + object_initialize_child(OBJECT(&s->lpd.rpu.cluster), | ||
89 | + "rpu-cpu[*]", &s->lpd.rpu.cpu[i], | ||
90 | + XLNX_VERSAL_RCPU_TYPE); | ||
91 | + obj = OBJECT(&s->lpd.rpu.cpu[i]); | ||
92 | + object_property_set_bool(obj, "start-powered-off", true, | ||
93 | + &error_abort); | ||
94 | + | ||
95 | + object_property_set_int(obj, "mp-affinity", 0x100 | i, &error_abort); | ||
96 | + object_property_set_int(obj, "core-count", ARRAY_SIZE(s->lpd.rpu.cpu), | ||
97 | + &error_abort); | ||
98 | + object_property_set_link(obj, "memory", OBJECT(&s->lpd.rpu.mr), | ||
99 | + &error_abort); | ||
100 | + qdev_realize(DEVICE(obj), NULL, &error_fatal); | ||
101 | + } | ||
102 | + | ||
103 | + qdev_realize(DEVICE(&s->lpd.rpu.cluster), NULL, &error_fatal); | ||
104 | +} | 46 | +} |
105 | + | 47 | + |
106 | static void versal_create_uarts(Versal *s, qemu_irq *pic) | 48 | static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, |
49 | uint32_t syn, TCGv_i32 tcg_el) | ||
107 | { | 50 | { |
108 | int i; | ||
109 | @@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp) | ||
110 | |||
111 | versal_create_apu_cpus(s); | ||
112 | versal_create_apu_gic(s, pic); | ||
113 | + versal_create_rpu_cpus(s); | ||
114 | versal_create_uarts(s, pic); | ||
115 | versal_create_usbs(s, pic); | ||
116 | versal_create_gems(s, pic); | ||
117 | @@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp) | ||
118 | |||
119 | memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0); | ||
120 | memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0); | ||
121 | + memory_region_add_subregion_overlap(&s->lpd.rpu.mr, 0, | ||
122 | + &s->lpd.rpu.mr_ps_alias, 0); | ||
123 | } | ||
124 | |||
125 | static void versal_init(Object *obj) | ||
126 | @@ -XXX,XX +XXX,XX @@ static void versal_init(Object *obj) | ||
127 | Versal *s = XLNX_VERSAL(obj); | ||
128 | |||
129 | memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX); | ||
130 | + memory_region_init(&s->lpd.rpu.mr, obj, "mr-rpu", UINT64_MAX); | ||
131 | memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX); | ||
132 | + memory_region_init_alias(&s->lpd.rpu.mr_ps_alias, OBJECT(s), | ||
133 | + "mr-rpu-ps-alias", &s->mr_ps, 0, UINT64_MAX); | ||
134 | } | ||
135 | |||
136 | static Property versal_properties[] = { | ||
137 | -- | 51 | -- |
138 | 2.25.1 | 52 | 2.25.1 | diff view generated by jsdifflib |
1 | Currently for the interrupts MCT_G0 and MCT_G1 which are | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | the only ones in the input range of the external combiner | ||
3 | and which are also wired to the external GIC, we connect | ||
4 | them only to the internal combiner and the external GIC. | ||
5 | This seems likely to be a bug, as all other interrupts | ||
6 | which are in the input range of both combiners are | ||
7 | connected to both combiners. (The fact that the code in | ||
8 | exynos4210_combiner_get_gpioin() is also trying to wire | ||
9 | up these inputs on both combiners also suggests this.) | ||
10 | 2 | ||
11 | Wire these interrupts up to both combiners, like the rest. | 3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20220609202901.1177572-17-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate.c | 18 +++++++++--------- | ||
9 | 1 file changed, 9 insertions(+), 9 deletions(-) | ||
12 | 10 | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-id: 20220404154658.565020-15-peter.maydell@linaro.org | ||
16 | --- | ||
17 | hw/arm/exynos4210.c | 7 +++---- | ||
18 | 1 file changed, 3 insertions(+), 4 deletions(-) | ||
19 | |||
20 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
21 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/hw/arm/exynos4210.c | 13 | --- a/target/arm/translate.c |
23 | +++ b/hw/arm/exynos4210.c | 14 | +++ b/target/arm/translate.c |
24 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | 15 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp) |
25 | 16 | s->base.is_jmp = DISAS_NORETURN; | |
26 | assert(splitcount < EXYNOS4210_NUM_SPLITTERS); | 17 | } |
27 | splitter = DEVICE(&s->splitter[splitcount]); | 18 | |
28 | - qdev_prop_set_uint16(splitter, "num-lines", 2); | 19 | -static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) |
29 | + qdev_prop_set_uint16(splitter, "num-lines", irq_id ? 3 : 2); | 20 | +static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el) |
30 | qdev_realize(splitter, NULL, &error_abort); | 21 | { |
31 | splitcount++; | 22 | gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), |
32 | s->irq_table[n] = qdev_get_gpio_in(splitter, 0); | 23 | tcg_constant_i32(syndrome), |
33 | qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); | 24 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) |
34 | + qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]); | 25 | switch (dc->base.is_jmp) { |
35 | if (irq_id) { | 26 | case DISAS_SWI: |
36 | - qdev_connect_gpio_out(splitter, 1, | 27 | gen_ss_advance(dc); |
37 | + qdev_connect_gpio_out(splitter, 2, | 28 | - gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), |
38 | qdev_get_gpio_in(extgicdev, irq_id - 32)); | 29 | - default_exception_el(dc)); |
39 | - } else { | 30 | + gen_exception_el(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), |
40 | - qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]); | 31 | + default_exception_el(dc)); |
32 | break; | ||
33 | case DISAS_HVC: | ||
34 | gen_ss_advance(dc); | ||
35 | - gen_exception(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2); | ||
36 | + gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2); | ||
37 | break; | ||
38 | case DISAS_SMC: | ||
39 | gen_ss_advance(dc); | ||
40 | - gen_exception(EXCP_SMC, syn_aa32_smc(), 3); | ||
41 | + gen_exception_el(EXCP_SMC, syn_aa32_smc(), 3); | ||
42 | break; | ||
43 | case DISAS_NEXT: | ||
44 | case DISAS_TOO_MANY: | ||
45 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | ||
46 | gen_helper_yield(cpu_env); | ||
47 | break; | ||
48 | case DISAS_SWI: | ||
49 | - gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), | ||
50 | - default_exception_el(dc)); | ||
51 | + gen_exception_el(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), | ||
52 | + default_exception_el(dc)); | ||
53 | break; | ||
54 | case DISAS_HVC: | ||
55 | - gen_exception(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2); | ||
56 | + gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2); | ||
57 | break; | ||
58 | case DISAS_SMC: | ||
59 | - gen_exception(EXCP_SMC, syn_aa32_smc(), 3); | ||
60 | + gen_exception_el(EXCP_SMC, syn_aa32_smc(), 3); | ||
61 | break; | ||
41 | } | 62 | } |
42 | } | 63 | } |
43 | for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { | ||
44 | -- | 64 | -- |
45 | 2.25.1 | 65 | 2.25.1 | diff view generated by jsdifflib |
1 | From: "Edgar E. Iglesias" <edgar.iglesias@amd.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Connect the 4 TTC timers on the ZynqMP. | 3 | Create a new wrapper function that passes the default |
4 | exception target to gen_exception_el. | ||
4 | 5 | ||
5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Reviewed-by: Luc Michel <luc@lmichel.fr> | 8 | Message-id: 20220609202901.1177572-18-richard.henderson@linaro.org |
8 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> | ||
9 | Message-id: 20220331222017.2914409-3-edgar.iglesias@gmail.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 10 | --- |
12 | include/hw/arm/xlnx-zynqmp.h | 4 ++++ | 11 | target/arm/translate.c | 11 +++++++---- |
13 | hw/arm/xlnx-zynqmp.c | 22 ++++++++++++++++++++++ | 12 | 1 file changed, 7 insertions(+), 4 deletions(-) |
14 | 2 files changed, 26 insertions(+) | ||
15 | 13 | ||
16 | diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h | 14 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
17 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/arm/xlnx-zynqmp.h | 16 | --- a/target/arm/translate.c |
19 | +++ b/include/hw/arm/xlnx-zynqmp.h | 17 | +++ b/target/arm/translate.c |
20 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el) |
21 | #include "hw/or-irq.h" | 19 | tcg_constant_i32(target_el)); |
22 | #include "hw/misc/xlnx-zynqmp-apu-ctrl.h" | ||
23 | #include "hw/misc/xlnx-zynqmp-crf.h" | ||
24 | +#include "hw/timer/cadence_ttc.h" | ||
25 | |||
26 | #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" | ||
27 | OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) | ||
28 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) | ||
29 | #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \ | ||
30 | XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE) | ||
31 | |||
32 | +#define XLNX_ZYNQMP_NUM_TTC 4 | ||
33 | + | ||
34 | /* | ||
35 | * Unimplemented mmio regions needed to boot some images. | ||
36 | */ | ||
37 | @@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState { | ||
38 | qemu_or_irq qspi_irq_orgate; | ||
39 | XlnxZynqMPAPUCtrl apu_ctrl; | ||
40 | XlnxZynqMPCRF crf; | ||
41 | + CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC]; | ||
42 | |||
43 | char *boot_cpu; | ||
44 | ARMCPU *boot_cpu_ptr; | ||
45 | diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c | ||
46 | index XXXXXXX..XXXXXXX 100644 | ||
47 | --- a/hw/arm/xlnx-zynqmp.c | ||
48 | +++ b/hw/arm/xlnx-zynqmp.c | ||
49 | @@ -XXX,XX +XXX,XX @@ | ||
50 | #define APU_ADDR 0xfd5c0000 | ||
51 | #define APU_IRQ 153 | ||
52 | |||
53 | +#define TTC0_ADDR 0xFF110000 | ||
54 | +#define TTC0_IRQ 36 | ||
55 | + | ||
56 | #define IPI_ADDR 0xFF300000 | ||
57 | #define IPI_IRQ 64 | ||
58 | |||
59 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic) | ||
60 | sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]); | ||
61 | } | 20 | } |
62 | 21 | ||
63 | +static void xlnx_zynqmp_create_ttc(XlnxZynqMPState *s, qemu_irq *gic) | 22 | +static void gen_exception(DisasContext *s, int excp, uint32_t syndrome) |
64 | +{ | 23 | +{ |
65 | + SysBusDevice *sbd; | 24 | + gen_exception_el(excp, syndrome, default_exception_el(s)); |
66 | + int i, irq; | ||
67 | + | ||
68 | + for (i = 0; i < XLNX_ZYNQMP_NUM_TTC; i++) { | ||
69 | + object_initialize_child(OBJECT(s), "ttc[*]", &s->ttc[i], | ||
70 | + TYPE_CADENCE_TTC); | ||
71 | + sbd = SYS_BUS_DEVICE(&s->ttc[i]); | ||
72 | + | ||
73 | + sysbus_realize(sbd, &error_fatal); | ||
74 | + sysbus_mmio_map(sbd, 0, TTC0_ADDR + i * 0x10000); | ||
75 | + for (irq = 0; irq < 3; irq++) { | ||
76 | + sysbus_connect_irq(sbd, irq, gic[TTC0_IRQ + i * 3 + irq]); | ||
77 | + } | ||
78 | + } | ||
79 | +} | 25 | +} |
80 | + | 26 | + |
81 | static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) | 27 | static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, |
28 | uint32_t syn, TCGv_i32 tcg_el) | ||
82 | { | 29 | { |
83 | static const struct UnimpInfo { | 30 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) |
84 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) | 31 | switch (dc->base.is_jmp) { |
85 | xlnx_zynqmp_create_efuse(s, gic_spi); | 32 | case DISAS_SWI: |
86 | xlnx_zynqmp_create_apu_ctrl(s, gic_spi); | 33 | gen_ss_advance(dc); |
87 | xlnx_zynqmp_create_crf(s, gic_spi); | 34 | - gen_exception_el(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), |
88 | + xlnx_zynqmp_create_ttc(s, gic_spi); | 35 | - default_exception_el(dc)); |
89 | xlnx_zynqmp_create_unimp_mmio(s); | 36 | + gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); |
90 | 37 | break; | |
91 | for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { | 38 | case DISAS_HVC: |
39 | gen_ss_advance(dc); | ||
40 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | ||
41 | gen_helper_yield(cpu_env); | ||
42 | break; | ||
43 | case DISAS_SWI: | ||
44 | - gen_exception_el(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), | ||
45 | - default_exception_el(dc)); | ||
46 | + gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); | ||
47 | break; | ||
48 | case DISAS_HVC: | ||
49 | gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2); | ||
92 | -- | 50 | -- |
93 | 2.25.1 | 51 | 2.25.1 | diff view generated by jsdifflib |
1 | From: "Edgar E. Iglesias" <edgar.iglesias@amd.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Connect the CRL (Clock Reset LPD) to the Versal SoC. | 3 | Split out a common helper function for gen_exception_el |
4 | and gen_exception_insn_el_v. | ||
4 | 5 | ||
5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Frederic Konrad <fkonrad@amd.com> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | 8 | Message-id: 20220609202901.1177572-19-richard.henderson@linaro.org |
8 | Message-id: 20220406174303.2022038-5-edgar.iglesias@xilinx.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | include/hw/arm/xlnx-versal.h | 4 +++ | 11 | target/arm/translate.c | 13 ++++++++----- |
12 | hw/arm/xlnx-versal.c | 54 ++++++++++++++++++++++++++++++++++-- | 12 | 1 file changed, 8 insertions(+), 5 deletions(-) |
13 | 2 files changed, 56 insertions(+), 2 deletions(-) | ||
14 | 13 | ||
15 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h | 14 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/include/hw/arm/xlnx-versal.h | 16 | --- a/target/arm/translate.c |
18 | +++ b/include/hw/arm/xlnx-versal.h | 17 | +++ b/target/arm/translate.c |
19 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp) |
20 | #include "hw/nvram/xlnx-versal-efuse.h" | 19 | s->base.is_jmp = DISAS_NORETURN; |
21 | #include "hw/ssi/xlnx-versal-ospi.h" | ||
22 | #include "hw/dma/xlnx_csu_dma.h" | ||
23 | +#include "hw/misc/xlnx-versal-crl.h" | ||
24 | #include "hw/misc/xlnx-versal-pmc-iou-slcr.h" | ||
25 | |||
26 | #define TYPE_XLNX_VERSAL "xlnx-versal" | ||
27 | @@ -XXX,XX +XXX,XX @@ struct Versal { | ||
28 | qemu_or_irq irq_orgate; | ||
29 | XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; | ||
30 | } xram; | ||
31 | + | ||
32 | + XlnxVersalCRL crl; | ||
33 | } lpd; | ||
34 | |||
35 | /* The Platform Management Controller subsystem. */ | ||
36 | @@ -XXX,XX +XXX,XX @@ struct Versal { | ||
37 | #define VERSAL_TIMER_NS_EL1_IRQ 14 | ||
38 | #define VERSAL_TIMER_NS_EL2_IRQ 10 | ||
39 | |||
40 | +#define VERSAL_CRL_IRQ 10 | ||
41 | #define VERSAL_UART0_IRQ_0 18 | ||
42 | #define VERSAL_UART1_IRQ_0 19 | ||
43 | #define VERSAL_USB0_IRQ_0 22 | ||
44 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/hw/arm/xlnx-versal.c | ||
47 | +++ b/hw/arm/xlnx-versal.c | ||
48 | @@ -XXX,XX +XXX,XX @@ static void versal_create_ospi(Versal *s, qemu_irq *pic) | ||
49 | qdev_connect_gpio_out(orgate, 0, pic[VERSAL_OSPI_IRQ]); | ||
50 | } | 20 | } |
51 | 21 | ||
52 | +static void versal_create_crl(Versal *s, qemu_irq *pic) | 22 | -static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el) |
53 | +{ | 23 | +static void gen_exception_el_v(int excp, uint32_t syndrome, TCGv_i32 tcg_el) |
54 | + SysBusDevice *sbd; | 24 | { |
55 | + int i; | 25 | gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), |
56 | + | 26 | - tcg_constant_i32(syndrome), |
57 | + object_initialize_child(OBJECT(s), "crl", &s->lpd.crl, | 27 | - tcg_constant_i32(target_el)); |
58 | + TYPE_XLNX_VERSAL_CRL); | 28 | + tcg_constant_i32(syndrome), tcg_el); |
59 | + sbd = SYS_BUS_DEVICE(&s->lpd.crl); | ||
60 | + | ||
61 | + for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) { | ||
62 | + g_autofree gchar *name = g_strdup_printf("cpu_r5[%d]", i); | ||
63 | + | ||
64 | + object_property_set_link(OBJECT(&s->lpd.crl), | ||
65 | + name, OBJECT(&s->lpd.rpu.cpu[i]), | ||
66 | + &error_abort); | ||
67 | + } | ||
68 | + | ||
69 | + for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) { | ||
70 | + g_autofree gchar *name = g_strdup_printf("gem[%d]", i); | ||
71 | + | ||
72 | + object_property_set_link(OBJECT(&s->lpd.crl), | ||
73 | + name, OBJECT(&s->lpd.iou.gem[i]), | ||
74 | + &error_abort); | ||
75 | + } | ||
76 | + | ||
77 | + for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) { | ||
78 | + g_autofree gchar *name = g_strdup_printf("adma[%d]", i); | ||
79 | + | ||
80 | + object_property_set_link(OBJECT(&s->lpd.crl), | ||
81 | + name, OBJECT(&s->lpd.iou.adma[i]), | ||
82 | + &error_abort); | ||
83 | + } | ||
84 | + | ||
85 | + for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) { | ||
86 | + g_autofree gchar *name = g_strdup_printf("uart[%d]", i); | ||
87 | + | ||
88 | + object_property_set_link(OBJECT(&s->lpd.crl), | ||
89 | + name, OBJECT(&s->lpd.iou.uart[i]), | ||
90 | + &error_abort); | ||
91 | + } | ||
92 | + | ||
93 | + object_property_set_link(OBJECT(&s->lpd.crl), | ||
94 | + "usb", OBJECT(&s->lpd.iou.usb), | ||
95 | + &error_abort); | ||
96 | + | ||
97 | + sysbus_realize(sbd, &error_fatal); | ||
98 | + memory_region_add_subregion(&s->mr_ps, MM_CRL, | ||
99 | + sysbus_mmio_get_region(sbd, 0)); | ||
100 | + sysbus_connect_irq(sbd, 0, pic[VERSAL_CRL_IRQ]); | ||
101 | +} | 29 | +} |
102 | + | 30 | + |
103 | /* This takes the board allocated linear DDR memory and creates aliases | 31 | +static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el) |
104 | * for each split DDR range/aperture on the Versal address map. | 32 | +{ |
105 | */ | 33 | + gen_exception_el_v(excp, syndrome, tcg_constant_i32(target_el)); |
106 | @@ -XXX,XX +XXX,XX @@ static void versal_unimp(Versal *s) | 34 | } |
107 | 35 | ||
108 | versal_unimp_area(s, "psm", &s->mr_ps, | 36 | static void gen_exception(DisasContext *s, int excp, uint32_t syndrome) |
109 | MM_PSM_START, MM_PSM_END - MM_PSM_START); | 37 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, |
110 | - versal_unimp_area(s, "crl", &s->mr_ps, | 38 | gen_set_condexec(s); |
111 | - MM_CRL, MM_CRL_SIZE); | 39 | gen_set_pc_im(s, pc); |
112 | versal_unimp_area(s, "crf", &s->mr_ps, | 40 | } |
113 | MM_FPD_CRF, MM_FPD_CRF_SIZE); | 41 | - gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), |
114 | versal_unimp_area(s, "apu", &s->mr_ps, | 42 | - tcg_constant_i32(syn), tcg_el); |
115 | @@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp) | 43 | + gen_exception_el_v(excp, syn, tcg_el); |
116 | versal_create_efuse(s, pic); | 44 | s->base.is_jmp = DISAS_NORETURN; |
117 | versal_create_pmc_iou_slcr(s, pic); | 45 | } |
118 | versal_create_ospi(s, pic); | ||
119 | + versal_create_crl(s, pic); | ||
120 | versal_map_ddr(s); | ||
121 | versal_unimp(s); | ||
122 | 46 | ||
123 | -- | 47 | -- |
124 | 2.25.1 | 48 | 2.25.1 | diff view generated by jsdifflib |
1 | From: "Edgar E. Iglesias" <edgar.iglesias@amd.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Create an APU CPU Cluster. This is in preparation to add the RPU. | 3 | With the helper we can use exception_target_el at runtime, |
4 | instead of default_exception_el at translate time. | ||
5 | While we're at it, remove the DisasContext parameter from | ||
6 | gen_exception, as it is no longer used. | ||
4 | 7 | ||
5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20220406174303.2022038-2-edgar.iglesias@xilinx.com | 10 | Message-id: 20220609202901.1177572-20-richard.henderson@linaro.org |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 12 | --- |
10 | include/hw/arm/xlnx-versal.h | 2 ++ | 13 | target/arm/helper.h | 1 + |
11 | hw/arm/xlnx-versal.c | 9 ++++++++- | 14 | target/arm/op_helper.c | 10 ++++++++++ |
12 | 2 files changed, 10 insertions(+), 1 deletion(-) | 15 | target/arm/translate.c | 18 +++++++++++++----- |
16 | 3 files changed, 24 insertions(+), 5 deletions(-) | ||
13 | 17 | ||
14 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h | 18 | diff --git a/target/arm/helper.h b/target/arm/helper.h |
15 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/include/hw/arm/xlnx-versal.h | 20 | --- a/target/arm/helper.h |
17 | +++ b/include/hw/arm/xlnx-versal.h | 21 | +++ b/target/arm/helper.h |
18 | @@ -XXX,XX +XXX,XX @@ | 22 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32) |
19 | 23 | DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, | |
20 | #include "hw/sysbus.h" | 24 | i32, i32, i32, i32) |
21 | #include "hw/arm/boot.h" | 25 | DEF_HELPER_2(exception_internal, noreturn, env, i32) |
22 | +#include "hw/cpu/cluster.h" | 26 | +DEF_HELPER_3(exception_with_syndrome, noreturn, env, i32, i32) |
23 | #include "hw/or-irq.h" | 27 | DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) |
24 | #include "hw/sd/sdhci.h" | 28 | DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) |
25 | #include "hw/intc/arm_gicv3.h" | 29 | DEF_HELPER_2(exception_swstep, noreturn, env, i32) |
26 | @@ -XXX,XX +XXX,XX @@ struct Versal { | 30 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c |
27 | struct { | ||
28 | struct { | ||
29 | MemoryRegion mr; | ||
30 | + CPUClusterState cluster; | ||
31 | ARMCPU cpu[XLNX_VERSAL_NR_ACPUS]; | ||
32 | GICv3State gic; | ||
33 | } apu; | ||
34 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | ||
35 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
36 | --- a/hw/arm/xlnx-versal.c | 32 | --- a/target/arm/op_helper.c |
37 | +++ b/hw/arm/xlnx-versal.c | 33 | +++ b/target/arm/op_helper.c |
38 | @@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s) | 34 | @@ -XXX,XX +XXX,XX @@ void HELPER(exception_with_syndrome_el)(CPUARMState *env, uint32_t excp, |
35 | raise_exception(env, excp, syndrome, target_el); | ||
36 | } | ||
37 | |||
38 | +/* | ||
39 | + * Raise an exception with the specified syndrome register value | ||
40 | + * to the default target el. | ||
41 | + */ | ||
42 | +void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp, | ||
43 | + uint32_t syndrome) | ||
44 | +{ | ||
45 | + raise_exception(env, excp, syndrome, exception_target_el(env)); | ||
46 | +} | ||
47 | + | ||
48 | uint32_t HELPER(cpsr_read)(CPUARMState *env) | ||
39 | { | 49 | { |
40 | int i; | 50 | return cpsr_read(env) & ~CPSR_EXEC; |
41 | 51 | diff --git a/target/arm/translate.c b/target/arm/translate.c | |
42 | + object_initialize_child(OBJECT(s), "apu-cluster", &s->fpd.apu.cluster, | 52 | index XXXXXXX..XXXXXXX 100644 |
43 | + TYPE_CPU_CLUSTER); | 53 | --- a/target/arm/translate.c |
44 | + qdev_prop_set_uint32(DEVICE(&s->fpd.apu.cluster), "cluster-id", 0); | 54 | +++ b/target/arm/translate.c |
45 | + | 55 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el) |
46 | for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) { | 56 | gen_exception_el_v(excp, syndrome, tcg_constant_i32(target_el)); |
47 | Object *obj; | ||
48 | |||
49 | - object_initialize_child(OBJECT(s), "apu-cpu[*]", &s->fpd.apu.cpu[i], | ||
50 | + object_initialize_child(OBJECT(&s->fpd.apu.cluster), | ||
51 | + "apu-cpu[*]", &s->fpd.apu.cpu[i], | ||
52 | XLNX_VERSAL_ACPU_TYPE); | ||
53 | obj = OBJECT(&s->fpd.apu.cpu[i]); | ||
54 | if (i) { | ||
55 | @@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s) | ||
56 | &error_abort); | ||
57 | qdev_realize(DEVICE(obj), NULL, &error_fatal); | ||
58 | } | ||
59 | + | ||
60 | + qdev_realize(DEVICE(&s->fpd.apu.cluster), NULL, &error_fatal); | ||
61 | } | 57 | } |
62 | 58 | ||
63 | static void versal_create_apu_gic(Versal *s, qemu_irq *pic) | 59 | -static void gen_exception(DisasContext *s, int excp, uint32_t syndrome) |
60 | +static void gen_exception(int excp, uint32_t syndrome) | ||
61 | { | ||
62 | - gen_exception_el(excp, syndrome, default_exception_el(s)); | ||
63 | + gen_helper_exception_with_syndrome(cpu_env, tcg_constant_i32(excp), | ||
64 | + tcg_constant_i32(syndrome)); | ||
65 | } | ||
66 | |||
67 | static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, | ||
68 | @@ -XXX,XX +XXX,XX @@ void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, | ||
69 | |||
70 | void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn) | ||
71 | { | ||
72 | - gen_exception_insn_el(s, pc, excp, syn, default_exception_el(s)); | ||
73 | + if (s->aarch64) { | ||
74 | + gen_a64_set_pc_im(pc); | ||
75 | + } else { | ||
76 | + gen_set_condexec(s); | ||
77 | + gen_set_pc_im(s, pc); | ||
78 | + } | ||
79 | + gen_exception(excp, syn); | ||
80 | + s->base.is_jmp = DISAS_NORETURN; | ||
81 | } | ||
82 | |||
83 | static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) | ||
84 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | ||
85 | switch (dc->base.is_jmp) { | ||
86 | case DISAS_SWI: | ||
87 | gen_ss_advance(dc); | ||
88 | - gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); | ||
89 | + gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); | ||
90 | break; | ||
91 | case DISAS_HVC: | ||
92 | gen_ss_advance(dc); | ||
93 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | ||
94 | gen_helper_yield(cpu_env); | ||
95 | break; | ||
96 | case DISAS_SWI: | ||
97 | - gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); | ||
98 | + gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); | ||
99 | break; | ||
100 | case DISAS_HVC: | ||
101 | gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2); | ||
64 | -- | 102 | -- |
65 | 2.25.1 | 103 | 2.25.1 | diff view generated by jsdifflib |
1 | The only time we use the int_combiner_irq[] and ext_combiner_irq[] | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | arrays in the Exynos4210Irq struct is during realize of the SoC -- we | ||
3 | initialize them with the input IRQs of the combiner devices, and then | ||
4 | connect those to outputs of other devices in | ||
5 | exynos4210_init_board_irqs(). Now that the combiner objects are | ||
6 | easily accessible as s->int_combiner and s->ext_combiner we can make | ||
7 | the connections directly from one device to the other without going | ||
8 | via these arrays. | ||
9 | 2 | ||
10 | Since these are the only two remaining elements of Exynos4210Irq, | 3 | This function is no longer used. At the same time, remove |
11 | we can remove that struct entirely. | 4 | DisasContext.secure_routed_to_el3, as it in turn becomes unused. |
12 | 5 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220609202901.1177572-21-richard.henderson@linaro.org | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-id: 20220404154658.565020-19-peter.maydell@linaro.org | ||
16 | --- | 10 | --- |
17 | include/hw/arm/exynos4210.h | 6 ------ | 11 | target/arm/translate.h | 16 ---------------- |
18 | hw/arm/exynos4210.c | 34 ++++++++-------------------------- | 12 | target/arm/translate-a64.c | 5 ----- |
19 | 2 files changed, 8 insertions(+), 32 deletions(-) | 13 | target/arm/translate.c | 5 ----- |
14 | 3 files changed, 26 deletions(-) | ||
20 | 15 | ||
21 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | 16 | diff --git a/target/arm/translate.h b/target/arm/translate.h |
22 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/include/hw/arm/exynos4210.h | 18 | --- a/target/arm/translate.h |
24 | +++ b/include/hw/arm/exynos4210.h | 19 | +++ b/target/arm/translate.h |
25 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { |
26 | */ | 21 | int fp_excp_el; /* FP exception EL or 0 if enabled */ |
27 | #define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38) | 22 | int sve_excp_el; /* SVE exception EL or 0 if enabled */ |
28 | 23 | int vl; /* current vector length in bytes */ | |
29 | -typedef struct Exynos4210Irq { | 24 | - /* Flag indicating that exceptions from secure mode are routed to EL3. */ |
30 | - qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | 25 | - bool secure_routed_to_el3; |
31 | - qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; | 26 | bool vfp_enabled; /* FP enabled via FPSCR.EN */ |
32 | -} Exynos4210Irq; | 27 | int vec_len; |
33 | - | 28 | int vec_stride; |
34 | struct Exynos4210State { | 29 | @@ -XXX,XX +XXX,XX @@ static inline int get_mem_index(DisasContext *s) |
35 | /*< private >*/ | 30 | return arm_to_core_mmu_idx(s->mmu_idx); |
36 | SysBusDevice parent_obj; | ||
37 | /*< public >*/ | ||
38 | ARMCPU *cpu[EXYNOS4210_NCPUS]; | ||
39 | - Exynos4210Irq irqs; | ||
40 | qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
41 | |||
42 | MemoryRegion chipid_mem; | ||
43 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/hw/arm/exynos4210.c | ||
46 | +++ b/hw/arm/exynos4210.c | ||
47 | @@ -XXX,XX +XXX,XX @@ static int mapline_size(const int *mapline) | ||
48 | static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
49 | { | ||
50 | uint32_t grp, bit, irq_id, n; | ||
51 | - Exynos4210Irq *is = &s->irqs; | ||
52 | DeviceState *extgicdev = DEVICE(&s->ext_gic); | ||
53 | + DeviceState *intcdev = DEVICE(&s->int_combiner); | ||
54 | + DeviceState *extcdev = DEVICE(&s->ext_combiner); | ||
55 | int splitcount = 0; | ||
56 | DeviceState *splitter; | ||
57 | const int *mapline; | ||
58 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
59 | splitin = 0; | ||
60 | for (;;) { | ||
61 | s->irq_table[in] = qdev_get_gpio_in(splitter, 0); | ||
62 | - qdev_connect_gpio_out(splitter, splitin, is->int_combiner_irq[in]); | ||
63 | - qdev_connect_gpio_out(splitter, splitin + 1, is->ext_combiner_irq[in]); | ||
64 | + qdev_connect_gpio_out(splitter, splitin, | ||
65 | + qdev_get_gpio_in(intcdev, in)); | ||
66 | + qdev_connect_gpio_out(splitter, splitin + 1, | ||
67 | + qdev_get_gpio_in(extcdev, in)); | ||
68 | splitin += 2; | ||
69 | if (!mapline) { | ||
70 | break; | ||
71 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
72 | qdev_realize(splitter, NULL, &error_abort); | ||
73 | splitcount++; | ||
74 | s->irq_table[n] = qdev_get_gpio_in(splitter, 0); | ||
75 | - qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); | ||
76 | + qdev_connect_gpio_out(splitter, 0, qdev_get_gpio_in(intcdev, n)); | ||
77 | qdev_connect_gpio_out(splitter, 1, | ||
78 | qdev_get_gpio_in(extgicdev, irq_id - 32)); | ||
79 | } else { | ||
80 | - s->irq_table[n] = is->int_combiner_irq[n]; | ||
81 | + s->irq_table[n] = qdev_get_gpio_in(intcdev, n); | ||
82 | } | ||
83 | } | ||
84 | /* | ||
85 | @@ -XXX,XX +XXX,XX @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) | ||
86 | return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); | ||
87 | } | 31 | } |
88 | 32 | ||
89 | -/* | 33 | -/* Function used to determine the target exception EL when otherwise not known |
90 | - * Get Combiner input GPIO into irqs structure | 34 | - * or default. |
91 | - */ | 35 | - */ |
92 | -static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, | 36 | -static inline int default_exception_el(DisasContext *s) |
93 | - DeviceState *dev, int ext) | ||
94 | -{ | 37 | -{ |
95 | - int n; | 38 | - /* If we are coming from secure EL0 in a system with a 32-bit EL3, then |
96 | - int max; | 39 | - * there is no secure EL1, so we route exceptions to EL3. Otherwise, |
97 | - qemu_irq *irq; | 40 | - * exceptions can only be routed to ELs above 1, so we target the higher of |
98 | - | 41 | - * 1 or the current EL. |
99 | - max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ : | 42 | - */ |
100 | - EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; | 43 | - return (s->mmu_idx == ARMMMUIdx_SE10_0 && s->secure_routed_to_el3) |
101 | - irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq; | 44 | - ? 3 : MAX(1, s->current_el); |
102 | - | ||
103 | - for (n = 0; n < max; n++) { | ||
104 | - irq[n] = qdev_get_gpio_in(dev, n); | ||
105 | - } | ||
106 | -} | 45 | -} |
107 | - | 46 | - |
108 | static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, | 47 | static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) |
109 | 0x09, 0x00, 0x00, 0x00 }; | 48 | { |
110 | 49 | /* We don't need to save all of the syndrome so we mask and shift | |
111 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | 50 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
112 | sysbus_connect_irq(busdev, n, | 51 | index XXXXXXX..XXXXXXX 100644 |
113 | qdev_get_gpio_in(DEVICE(&s->a9mpcore), n)); | 52 | --- a/target/arm/translate-a64.c |
114 | } | 53 | +++ b/target/arm/translate-a64.c |
115 | - exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->int_combiner), 0); | 54 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, |
116 | sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); | 55 | dc->condjmp = 0; |
117 | 56 | ||
118 | /* External Interrupt Combiner */ | 57 | dc->aarch64 = true; |
119 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | 58 | - /* If we are coming from secure EL0 in a system with a 32-bit EL3, then |
120 | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { | 59 | - * there is no secure EL1, so we route exceptions to EL3. |
121 | sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n)); | 60 | - */ |
122 | } | 61 | - dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) && |
123 | - exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->ext_combiner), 1); | 62 | - !arm_el_is_aa64(env, 3); |
124 | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); | 63 | dc->thumb = false; |
125 | 64 | dc->sctlr_b = 0; | |
126 | /* Initialize board IRQs. */ | 65 | dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE; |
66 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | ||
68 | --- a/target/arm/translate.c | ||
69 | +++ b/target/arm/translate.c | ||
70 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) | ||
71 | dc->condjmp = 0; | ||
72 | |||
73 | dc->aarch64 = false; | ||
74 | - /* If we are coming from secure EL0 in a system with a 32-bit EL3, then | ||
75 | - * there is no secure EL1, so we route exceptions to EL3. | ||
76 | - */ | ||
77 | - dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) && | ||
78 | - !arm_el_is_aa64(env, 3); | ||
79 | dc->thumb = EX_TBFLAG_AM32(tb_flags, THUMB); | ||
80 | dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE; | ||
81 | condexec = EX_TBFLAG_AM32(tb_flags, CONDEXEC); | ||
127 | -- | 82 | -- |
128 | 2.25.1 | 83 | 2.25.1 | diff view generated by jsdifflib |
1 | The function exynos4210_combiner_get_gpioin() currently lives in | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | exynos4210_combiner.c, but it isn't really part of the combiner | ||
3 | device itself -- it is a function that implements the wiring up of | ||
4 | some interrupt sources to multiple combiner inputs. Move it to live | ||
5 | with the other SoC-level code in exynos4210.c, along with a few | ||
6 | macros previously defined in exynos4210.h which are now used only | ||
7 | in exynos4210.c. | ||
8 | 2 | ||
3 | Handle the debug vs current el exception test in one place. | ||
4 | Leave EXCP_BKPT alone, since that treats debug < current differently. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220609202901.1177572-22-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20220404154658.565020-11-peter.maydell@linaro.org | ||
12 | --- | 10 | --- |
13 | include/hw/arm/exynos4210.h | 11 ----- | 11 | target/arm/debug_helper.c | 44 +++++++++++++++++++++------------------ |
14 | hw/arm/exynos4210.c | 82 +++++++++++++++++++++++++++++++++++ | 12 | 1 file changed, 24 insertions(+), 20 deletions(-) |
15 | hw/intc/exynos4210_combiner.c | 77 -------------------------------- | ||
16 | 3 files changed, 82 insertions(+), 88 deletions(-) | ||
17 | 13 | ||
18 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | 14 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c |
19 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/include/hw/arm/exynos4210.h | 16 | --- a/target/arm/debug_helper.c |
21 | +++ b/include/hw/arm/exynos4210.h | 17 | +++ b/target/arm/debug_helper.c |
22 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ |
23 | #define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \ | 19 | #include "exec/helper-proto.h" |
24 | (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8) | 20 | |
25 | |||
26 | -#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp)*8 + (bit)) | ||
27 | -#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8) | ||
28 | -#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ | ||
29 | - ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) | ||
30 | - | ||
31 | /* IRQs number for external and internal GIC */ | ||
32 | #define EXYNOS4210_EXT_GIC_NIRQ (160-32) | ||
33 | #define EXYNOS4210_INT_GIC_NIRQ 64 | ||
34 | @@ -XXX,XX +XXX,XX @@ void exynos4210_write_secondary(ARMCPU *cpu, | ||
35 | * bit - bit number inside group */ | ||
36 | uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit); | ||
37 | |||
38 | -/* | ||
39 | - * Get Combiner input GPIO into irqs structure | ||
40 | - */ | ||
41 | -void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev, | ||
42 | - int ext); | ||
43 | - | ||
44 | /* | ||
45 | * exynos4210 UART | ||
46 | */ | ||
47 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/hw/arm/exynos4210.c | ||
50 | +++ b/hw/arm/exynos4210.c | ||
51 | @@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
52 | { }, { }, { }, { }, { }, { }, { }, { }, { }, { } | ||
53 | }; | ||
54 | |||
55 | +#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp) * 8 + (bit)) | ||
56 | +#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8) | ||
57 | +#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ | ||
58 | + ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) | ||
59 | + | ||
60 | /* | ||
61 | * Initialize board IRQs. | ||
62 | * These IRQs contain splitted Int/External Combiner and External Gic IRQs. | ||
63 | @@ -XXX,XX +XXX,XX @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) | ||
64 | return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); | ||
65 | } | ||
66 | 21 | ||
67 | +/* | 22 | +/* |
68 | + * Get Combiner input GPIO into irqs structure | 23 | + * Raise an exception to the debug target el. |
24 | + * Modify syndrome to indicate when origin and target EL are the same. | ||
69 | + */ | 25 | + */ |
70 | +static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, | 26 | +G_NORETURN static void |
71 | + DeviceState *dev, int ext) | 27 | +raise_exception_debug(CPUARMState *env, uint32_t excp, uint32_t syndrome) |
72 | +{ | 28 | +{ |
73 | + int n; | 29 | + int debug_el = arm_debug_target_el(env); |
74 | + int bit; | 30 | + int cur_el = arm_current_el(env); |
75 | + int max; | ||
76 | + qemu_irq *irq; | ||
77 | + | ||
78 | + max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ : | ||
79 | + EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; | ||
80 | + irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq; | ||
81 | + | 31 | + |
82 | + /* | 32 | + /* |
83 | + * Some IRQs of Int/External Combiner are going to two Combiners groups, | 33 | + * If singlestep is targeting a lower EL than the current one, then |
84 | + * so let split them. | 34 | + * DisasContext.ss_active must be false and we can never get here. |
35 | + * Similarly for watchpoint and breakpoint matches. | ||
85 | + */ | 36 | + */ |
86 | + for (n = 0; n < max; n++) { | 37 | + assert(debug_el >= cur_el); |
87 | + | 38 | + syndrome |= (debug_el == cur_el) << ARM_EL_EC_SHIFT; |
88 | + bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); | 39 | + raise_exception(env, excp, syndrome, debug_el); |
89 | + | ||
90 | + switch (n) { | ||
91 | + /* MDNIE_LCD1 INTG1 */ | ||
92 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ... | ||
93 | + EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3): | ||
94 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
95 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]); | ||
96 | + continue; | ||
97 | + | ||
98 | + /* TMU INTG3 */ | ||
99 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4): | ||
100 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
101 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]); | ||
102 | + continue; | ||
103 | + | ||
104 | + /* LCD1 INTG12 */ | ||
105 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ... | ||
106 | + EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3): | ||
107 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
108 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]); | ||
109 | + continue; | ||
110 | + | ||
111 | + /* Multi-Core Timer INTG12 */ | ||
112 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ... | ||
113 | + EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8): | ||
114 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
115 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
116 | + continue; | ||
117 | + | ||
118 | + /* Multi-Core Timer INTG35 */ | ||
119 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ... | ||
120 | + EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8): | ||
121 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
122 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
123 | + continue; | ||
124 | + | ||
125 | + /* Multi-Core Timer INTG51 */ | ||
126 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ... | ||
127 | + EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8): | ||
128 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
129 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
130 | + continue; | ||
131 | + | ||
132 | + /* Multi-Core Timer INTG53 */ | ||
133 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ... | ||
134 | + EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8): | ||
135 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
136 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
137 | + continue; | ||
138 | + } | ||
139 | + | ||
140 | + irq[n] = qdev_get_gpio_in(dev, n); | ||
141 | + } | ||
142 | +} | 40 | +} |
143 | + | 41 | + |
144 | static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, | 42 | /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ |
145 | 0x09, 0x00, 0x00, 0x00 }; | 43 | static bool aa64_generate_debug_exceptions(CPUARMState *env) |
146 | 44 | { | |
147 | diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c | 45 | @@ -XXX,XX +XXX,XX @@ void arm_debug_excp_handler(CPUState *cs) |
148 | index XXXXXXX..XXXXXXX 100644 | 46 | if (wp_hit) { |
149 | --- a/hw/intc/exynos4210_combiner.c | 47 | if (wp_hit->flags & BP_CPU) { |
150 | +++ b/hw/intc/exynos4210_combiner.c | 48 | bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0; |
151 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_exynos4210_combiner = { | 49 | - bool same_el = arm_debug_target_el(env) == arm_current_el(env); |
50 | |||
51 | cs->watchpoint_hit = NULL; | ||
52 | |||
53 | env->exception.fsr = arm_debug_exception_fsr(env); | ||
54 | env->exception.vaddress = wp_hit->hitaddr; | ||
55 | - raise_exception(env, EXCP_DATA_ABORT, | ||
56 | - syn_watchpoint(same_el, 0, wnr), | ||
57 | - arm_debug_target_el(env)); | ||
58 | + raise_exception_debug(env, EXCP_DATA_ABORT, | ||
59 | + syn_watchpoint(0, 0, wnr)); | ||
60 | } | ||
61 | } else { | ||
62 | uint64_t pc = is_a64(env) ? env->pc : env->regs[15]; | ||
63 | - bool same_el = (arm_debug_target_el(env) == arm_current_el(env)); | ||
64 | |||
65 | /* | ||
66 | * (1) GDB breakpoints should be handled first. | ||
67 | @@ -XXX,XX +XXX,XX @@ void arm_debug_excp_handler(CPUState *cs) | ||
68 | * exception/security level. | ||
69 | */ | ||
70 | env->exception.vaddress = 0; | ||
71 | - raise_exception(env, EXCP_PREFETCH_ABORT, | ||
72 | - syn_breakpoint(same_el), | ||
73 | - arm_debug_target_el(env)); | ||
74 | + raise_exception_debug(env, EXCP_PREFETCH_ABORT, syn_breakpoint(0)); | ||
152 | } | 75 | } |
153 | }; | 76 | } |
154 | 77 | ||
155 | -/* | 78 | @@ -XXX,XX +XXX,XX @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) |
156 | - * Get Combiner input GPIO into irqs structure | 79 | |
157 | - */ | 80 | void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome) |
158 | -void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev, | 81 | { |
159 | - int ext) | 82 | - int debug_el = arm_debug_target_el(env); |
160 | -{ | 83 | - int cur_el = arm_current_el(env); |
161 | - int n; | ||
162 | - int bit; | ||
163 | - int max; | ||
164 | - qemu_irq *irq; | ||
165 | - | ||
166 | - max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ : | ||
167 | - EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; | ||
168 | - irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq; | ||
169 | - | 84 | - |
170 | - /* | 85 | - /* |
171 | - * Some IRQs of Int/External Combiner are going to two Combiners groups, | 86 | - * If singlestep is targeting a lower EL than the current one, then |
172 | - * so let split them. | 87 | - * DisasContext.ss_active must be false and we can never get here. |
173 | - */ | 88 | - */ |
174 | - for (n = 0; n < max; n++) { | 89 | - assert(debug_el >= cur_el); |
175 | - | 90 | - if (debug_el == cur_el) { |
176 | - bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); | 91 | - syndrome |= 1 << ARM_EL_EC_SHIFT; |
177 | - | ||
178 | - switch (n) { | ||
179 | - /* MDNIE_LCD1 INTG1 */ | ||
180 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ... | ||
181 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3): | ||
182 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
183 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]); | ||
184 | - continue; | ||
185 | - | ||
186 | - /* TMU INTG3 */ | ||
187 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4): | ||
188 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
189 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]); | ||
190 | - continue; | ||
191 | - | ||
192 | - /* LCD1 INTG12 */ | ||
193 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ... | ||
194 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3): | ||
195 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
196 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]); | ||
197 | - continue; | ||
198 | - | ||
199 | - /* Multi-Core Timer INTG12 */ | ||
200 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ... | ||
201 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8): | ||
202 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
203 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
204 | - continue; | ||
205 | - | ||
206 | - /* Multi-Core Timer INTG35 */ | ||
207 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ... | ||
208 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8): | ||
209 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
210 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
211 | - continue; | ||
212 | - | ||
213 | - /* Multi-Core Timer INTG51 */ | ||
214 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ... | ||
215 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8): | ||
216 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
217 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
218 | - continue; | ||
219 | - | ||
220 | - /* Multi-Core Timer INTG53 */ | ||
221 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ... | ||
222 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8): | ||
223 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
224 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
225 | - continue; | ||
226 | - } | ||
227 | - | ||
228 | - irq[n] = qdev_get_gpio_in(dev, n); | ||
229 | - } | 92 | - } |
230 | -} | 93 | - raise_exception(env, EXCP_UDEF, syndrome, debug_el); |
231 | - | 94 | + raise_exception_debug(env, EXCP_UDEF, syndrome); |
232 | static uint64_t | 95 | } |
233 | exynos4210_combiner_read(void *opaque, hwaddr offset, unsigned size) | 96 | |
234 | { | 97 | #if !defined(CONFIG_USER_ONLY) |
235 | -- | 98 | -- |
236 | 2.25.1 | 99 | 2.25.1 | diff view generated by jsdifflib |
1 | From: "Edgar E. Iglesias" <edgar.iglesias@amd.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Add a model of the Xilinx Versal CRL. | 3 | This function is no longer used outside debug_helper.c. |
4 | 4 | ||
5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> | 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Frederic Konrad <fkonrad@amd.com> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | 7 | Message-id: 20220609202901.1177572-23-richard.henderson@linaro.org |
8 | Message-id: 20220406174303.2022038-4-edgar.iglesias@xilinx.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 9 | --- |
11 | include/hw/misc/xlnx-versal-crl.h | 235 +++++++++++++++++ | 10 | target/arm/cpu.h | 21 --------------------- |
12 | hw/misc/xlnx-versal-crl.c | 421 ++++++++++++++++++++++++++++++ | 11 | target/arm/debug_helper.c | 21 +++++++++++++++++++++ |
13 | hw/misc/meson.build | 1 + | 12 | 2 files changed, 21 insertions(+), 21 deletions(-) |
14 | 3 files changed, 657 insertions(+) | ||
15 | create mode 100644 include/hw/misc/xlnx-versal-crl.h | ||
16 | create mode 100644 hw/misc/xlnx-versal-crl.c | ||
17 | 13 | ||
18 | diff --git a/include/hw/misc/xlnx-versal-crl.h b/include/hw/misc/xlnx-versal-crl.h | 14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
19 | new file mode 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
20 | index XXXXXXX..XXXXXXX | 16 | --- a/target/arm/cpu.h |
21 | --- /dev/null | 17 | +++ b/target/arm/cpu.h |
22 | +++ b/include/hw/misc/xlnx-versal-crl.h | 18 | @@ -XXX,XX +XXX,XX @@ typedef enum ARMASIdx { |
19 | ARMASIdx_TagS = 3, | ||
20 | } ARMASIdx; | ||
21 | |||
22 | -/* Return the Exception Level targeted by debug exceptions. */ | ||
23 | -static inline int arm_debug_target_el(CPUARMState *env) | ||
24 | -{ | ||
25 | - bool secure = arm_is_secure(env); | ||
26 | - bool route_to_el2 = false; | ||
27 | - | ||
28 | - if (arm_is_el2_enabled(env)) { | ||
29 | - route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || | ||
30 | - env->cp15.mdcr_el2 & MDCR_TDE; | ||
31 | - } | ||
32 | - | ||
33 | - if (route_to_el2) { | ||
34 | - return 2; | ||
35 | - } else if (arm_feature(env, ARM_FEATURE_EL3) && | ||
36 | - !arm_el_is_aa64(env, 3) && secure) { | ||
37 | - return 3; | ||
38 | - } else { | ||
39 | - return 1; | ||
40 | - } | ||
41 | -} | ||
42 | - | ||
43 | static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) | ||
44 | { | ||
45 | /* If all the CLIDR.Ctypem bits are 0 there are no caches, and | ||
46 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/target/arm/debug_helper.c | ||
49 | +++ b/target/arm/debug_helper.c | ||
23 | @@ -XXX,XX +XXX,XX @@ | 50 | @@ -XXX,XX +XXX,XX @@ |
24 | +/* | 51 | #include "exec/helper-proto.h" |
25 | + * QEMU model of the Clock-Reset-LPD (CRL). | 52 | |
26 | + * | 53 | |
27 | + * Copyright (c) 2022 Xilinx Inc. | 54 | +/* Return the Exception Level targeted by debug exceptions. */ |
28 | + * SPDX-License-Identifier: GPL-2.0-or-later | 55 | +static int arm_debug_target_el(CPUARMState *env) |
29 | + * | 56 | +{ |
30 | + * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 57 | + bool secure = arm_is_secure(env); |
31 | + */ | 58 | + bool route_to_el2 = false; |
32 | +#ifndef HW_MISC_XLNX_VERSAL_CRL_H | ||
33 | +#define HW_MISC_XLNX_VERSAL_CRL_H | ||
34 | + | 59 | + |
35 | +#include "hw/sysbus.h" | 60 | + if (arm_is_el2_enabled(env)) { |
36 | +#include "hw/register.h" | 61 | + route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || |
37 | +#include "target/arm/cpu.h" | 62 | + env->cp15.mdcr_el2 & MDCR_TDE; |
63 | + } | ||
38 | + | 64 | + |
39 | +#define TYPE_XLNX_VERSAL_CRL "xlnx,versal-crl" | 65 | + if (route_to_el2) { |
40 | +OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL) | 66 | + return 2; |
41 | + | 67 | + } else if (arm_feature(env, ARM_FEATURE_EL3) && |
42 | +REG32(ERR_CTRL, 0x0) | 68 | + !arm_el_is_aa64(env, 3) && secure) { |
43 | + FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1) | 69 | + return 3; |
44 | +REG32(IR_STATUS, 0x4) | ||
45 | + FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1) | ||
46 | +REG32(IR_MASK, 0x8) | ||
47 | + FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1) | ||
48 | +REG32(IR_ENABLE, 0xc) | ||
49 | + FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1) | ||
50 | +REG32(IR_DISABLE, 0x10) | ||
51 | + FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1) | ||
52 | +REG32(WPROT, 0x1c) | ||
53 | + FIELD(WPROT, ACTIVE, 0, 1) | ||
54 | +REG32(PLL_CLK_OTHER_DMN, 0x20) | ||
55 | + FIELD(PLL_CLK_OTHER_DMN, APLL_BYPASS, 0, 1) | ||
56 | +REG32(RPLL_CTRL, 0x40) | ||
57 | + FIELD(RPLL_CTRL, POST_SRC, 24, 3) | ||
58 | + FIELD(RPLL_CTRL, PRE_SRC, 20, 3) | ||
59 | + FIELD(RPLL_CTRL, CLKOUTDIV, 16, 2) | ||
60 | + FIELD(RPLL_CTRL, FBDIV, 8, 8) | ||
61 | + FIELD(RPLL_CTRL, BYPASS, 3, 1) | ||
62 | + FIELD(RPLL_CTRL, RESET, 0, 1) | ||
63 | +REG32(RPLL_CFG, 0x44) | ||
64 | + FIELD(RPLL_CFG, LOCK_DLY, 25, 7) | ||
65 | + FIELD(RPLL_CFG, LOCK_CNT, 13, 10) | ||
66 | + FIELD(RPLL_CFG, LFHF, 10, 2) | ||
67 | + FIELD(RPLL_CFG, CP, 5, 4) | ||
68 | + FIELD(RPLL_CFG, RES, 0, 4) | ||
69 | +REG32(RPLL_FRAC_CFG, 0x48) | ||
70 | + FIELD(RPLL_FRAC_CFG, ENABLED, 31, 1) | ||
71 | + FIELD(RPLL_FRAC_CFG, SEED, 22, 3) | ||
72 | + FIELD(RPLL_FRAC_CFG, ALGRTHM, 19, 1) | ||
73 | + FIELD(RPLL_FRAC_CFG, ORDER, 18, 1) | ||
74 | + FIELD(RPLL_FRAC_CFG, DATA, 0, 16) | ||
75 | +REG32(PLL_STATUS, 0x50) | ||
76 | + FIELD(PLL_STATUS, RPLL_STABLE, 2, 1) | ||
77 | + FIELD(PLL_STATUS, RPLL_LOCK, 0, 1) | ||
78 | +REG32(RPLL_TO_XPD_CTRL, 0x100) | ||
79 | + FIELD(RPLL_TO_XPD_CTRL, CLKACT, 25, 1) | ||
80 | + FIELD(RPLL_TO_XPD_CTRL, DIVISOR0, 8, 10) | ||
81 | +REG32(LPD_TOP_SWITCH_CTRL, 0x104) | ||
82 | + FIELD(LPD_TOP_SWITCH_CTRL, CLKACT_ADMA, 26, 1) | ||
83 | + FIELD(LPD_TOP_SWITCH_CTRL, CLKACT, 25, 1) | ||
84 | + FIELD(LPD_TOP_SWITCH_CTRL, DIVISOR0, 8, 10) | ||
85 | + FIELD(LPD_TOP_SWITCH_CTRL, SRCSEL, 0, 3) | ||
86 | +REG32(LPD_LSBUS_CTRL, 0x108) | ||
87 | + FIELD(LPD_LSBUS_CTRL, CLKACT, 25, 1) | ||
88 | + FIELD(LPD_LSBUS_CTRL, DIVISOR0, 8, 10) | ||
89 | + FIELD(LPD_LSBUS_CTRL, SRCSEL, 0, 3) | ||
90 | +REG32(CPU_R5_CTRL, 0x10c) | ||
91 | + FIELD(CPU_R5_CTRL, CLKACT_OCM2, 28, 1) | ||
92 | + FIELD(CPU_R5_CTRL, CLKACT_OCM, 27, 1) | ||
93 | + FIELD(CPU_R5_CTRL, CLKACT_CORE, 26, 1) | ||
94 | + FIELD(CPU_R5_CTRL, CLKACT, 25, 1) | ||
95 | + FIELD(CPU_R5_CTRL, DIVISOR0, 8, 10) | ||
96 | + FIELD(CPU_R5_CTRL, SRCSEL, 0, 3) | ||
97 | +REG32(IOU_SWITCH_CTRL, 0x114) | ||
98 | + FIELD(IOU_SWITCH_CTRL, CLKACT, 25, 1) | ||
99 | + FIELD(IOU_SWITCH_CTRL, DIVISOR0, 8, 10) | ||
100 | + FIELD(IOU_SWITCH_CTRL, SRCSEL, 0, 3) | ||
101 | +REG32(GEM0_REF_CTRL, 0x118) | ||
102 | + FIELD(GEM0_REF_CTRL, CLKACT_RX, 27, 1) | ||
103 | + FIELD(GEM0_REF_CTRL, CLKACT_TX, 26, 1) | ||
104 | + FIELD(GEM0_REF_CTRL, CLKACT, 25, 1) | ||
105 | + FIELD(GEM0_REF_CTRL, DIVISOR0, 8, 10) | ||
106 | + FIELD(GEM0_REF_CTRL, SRCSEL, 0, 3) | ||
107 | +REG32(GEM1_REF_CTRL, 0x11c) | ||
108 | + FIELD(GEM1_REF_CTRL, CLKACT_RX, 27, 1) | ||
109 | + FIELD(GEM1_REF_CTRL, CLKACT_TX, 26, 1) | ||
110 | + FIELD(GEM1_REF_CTRL, CLKACT, 25, 1) | ||
111 | + FIELD(GEM1_REF_CTRL, DIVISOR0, 8, 10) | ||
112 | + FIELD(GEM1_REF_CTRL, SRCSEL, 0, 3) | ||
113 | +REG32(GEM_TSU_REF_CTRL, 0x120) | ||
114 | + FIELD(GEM_TSU_REF_CTRL, CLKACT, 25, 1) | ||
115 | + FIELD(GEM_TSU_REF_CTRL, DIVISOR0, 8, 10) | ||
116 | + FIELD(GEM_TSU_REF_CTRL, SRCSEL, 0, 3) | ||
117 | +REG32(USB0_BUS_REF_CTRL, 0x124) | ||
118 | + FIELD(USB0_BUS_REF_CTRL, CLKACT, 25, 1) | ||
119 | + FIELD(USB0_BUS_REF_CTRL, DIVISOR0, 8, 10) | ||
120 | + FIELD(USB0_BUS_REF_CTRL, SRCSEL, 0, 3) | ||
121 | +REG32(UART0_REF_CTRL, 0x128) | ||
122 | + FIELD(UART0_REF_CTRL, CLKACT, 25, 1) | ||
123 | + FIELD(UART0_REF_CTRL, DIVISOR0, 8, 10) | ||
124 | + FIELD(UART0_REF_CTRL, SRCSEL, 0, 3) | ||
125 | +REG32(UART1_REF_CTRL, 0x12c) | ||
126 | + FIELD(UART1_REF_CTRL, CLKACT, 25, 1) | ||
127 | + FIELD(UART1_REF_CTRL, DIVISOR0, 8, 10) | ||
128 | + FIELD(UART1_REF_CTRL, SRCSEL, 0, 3) | ||
129 | +REG32(SPI0_REF_CTRL, 0x130) | ||
130 | + FIELD(SPI0_REF_CTRL, CLKACT, 25, 1) | ||
131 | + FIELD(SPI0_REF_CTRL, DIVISOR0, 8, 10) | ||
132 | + FIELD(SPI0_REF_CTRL, SRCSEL, 0, 3) | ||
133 | +REG32(SPI1_REF_CTRL, 0x134) | ||
134 | + FIELD(SPI1_REF_CTRL, CLKACT, 25, 1) | ||
135 | + FIELD(SPI1_REF_CTRL, DIVISOR0, 8, 10) | ||
136 | + FIELD(SPI1_REF_CTRL, SRCSEL, 0, 3) | ||
137 | +REG32(CAN0_REF_CTRL, 0x138) | ||
138 | + FIELD(CAN0_REF_CTRL, CLKACT, 25, 1) | ||
139 | + FIELD(CAN0_REF_CTRL, DIVISOR0, 8, 10) | ||
140 | + FIELD(CAN0_REF_CTRL, SRCSEL, 0, 3) | ||
141 | +REG32(CAN1_REF_CTRL, 0x13c) | ||
142 | + FIELD(CAN1_REF_CTRL, CLKACT, 25, 1) | ||
143 | + FIELD(CAN1_REF_CTRL, DIVISOR0, 8, 10) | ||
144 | + FIELD(CAN1_REF_CTRL, SRCSEL, 0, 3) | ||
145 | +REG32(I2C0_REF_CTRL, 0x140) | ||
146 | + FIELD(I2C0_REF_CTRL, CLKACT, 25, 1) | ||
147 | + FIELD(I2C0_REF_CTRL, DIVISOR0, 8, 10) | ||
148 | + FIELD(I2C0_REF_CTRL, SRCSEL, 0, 3) | ||
149 | +REG32(I2C1_REF_CTRL, 0x144) | ||
150 | + FIELD(I2C1_REF_CTRL, CLKACT, 25, 1) | ||
151 | + FIELD(I2C1_REF_CTRL, DIVISOR0, 8, 10) | ||
152 | + FIELD(I2C1_REF_CTRL, SRCSEL, 0, 3) | ||
153 | +REG32(DBG_LPD_CTRL, 0x148) | ||
154 | + FIELD(DBG_LPD_CTRL, CLKACT, 25, 1) | ||
155 | + FIELD(DBG_LPD_CTRL, DIVISOR0, 8, 10) | ||
156 | + FIELD(DBG_LPD_CTRL, SRCSEL, 0, 3) | ||
157 | +REG32(TIMESTAMP_REF_CTRL, 0x14c) | ||
158 | + FIELD(TIMESTAMP_REF_CTRL, CLKACT, 25, 1) | ||
159 | + FIELD(TIMESTAMP_REF_CTRL, DIVISOR0, 8, 10) | ||
160 | + FIELD(TIMESTAMP_REF_CTRL, SRCSEL, 0, 3) | ||
161 | +REG32(CRL_SAFETY_CHK, 0x150) | ||
162 | +REG32(PSM_REF_CTRL, 0x154) | ||
163 | + FIELD(PSM_REF_CTRL, DIVISOR0, 8, 10) | ||
164 | + FIELD(PSM_REF_CTRL, SRCSEL, 0, 3) | ||
165 | +REG32(DBG_TSTMP_CTRL, 0x158) | ||
166 | + FIELD(DBG_TSTMP_CTRL, CLKACT, 25, 1) | ||
167 | + FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 10) | ||
168 | + FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3) | ||
169 | +REG32(CPM_TOPSW_REF_CTRL, 0x15c) | ||
170 | + FIELD(CPM_TOPSW_REF_CTRL, CLKACT, 25, 1) | ||
171 | + FIELD(CPM_TOPSW_REF_CTRL, DIVISOR0, 8, 10) | ||
172 | + FIELD(CPM_TOPSW_REF_CTRL, SRCSEL, 0, 3) | ||
173 | +REG32(USB3_DUAL_REF_CTRL, 0x160) | ||
174 | + FIELD(USB3_DUAL_REF_CTRL, CLKACT, 25, 1) | ||
175 | + FIELD(USB3_DUAL_REF_CTRL, DIVISOR0, 8, 10) | ||
176 | + FIELD(USB3_DUAL_REF_CTRL, SRCSEL, 0, 3) | ||
177 | +REG32(RST_CPU_R5, 0x300) | ||
178 | + FIELD(RST_CPU_R5, RESET_PGE, 4, 1) | ||
179 | + FIELD(RST_CPU_R5, RESET_AMBA, 2, 1) | ||
180 | + FIELD(RST_CPU_R5, RESET_CPU1, 1, 1) | ||
181 | + FIELD(RST_CPU_R5, RESET_CPU0, 0, 1) | ||
182 | +REG32(RST_ADMA, 0x304) | ||
183 | + FIELD(RST_ADMA, RESET, 0, 1) | ||
184 | +REG32(RST_GEM0, 0x308) | ||
185 | + FIELD(RST_GEM0, RESET, 0, 1) | ||
186 | +REG32(RST_GEM1, 0x30c) | ||
187 | + FIELD(RST_GEM1, RESET, 0, 1) | ||
188 | +REG32(RST_SPARE, 0x310) | ||
189 | + FIELD(RST_SPARE, RESET, 0, 1) | ||
190 | +REG32(RST_USB0, 0x314) | ||
191 | + FIELD(RST_USB0, RESET, 0, 1) | ||
192 | +REG32(RST_UART0, 0x318) | ||
193 | + FIELD(RST_UART0, RESET, 0, 1) | ||
194 | +REG32(RST_UART1, 0x31c) | ||
195 | + FIELD(RST_UART1, RESET, 0, 1) | ||
196 | +REG32(RST_SPI0, 0x320) | ||
197 | + FIELD(RST_SPI0, RESET, 0, 1) | ||
198 | +REG32(RST_SPI1, 0x324) | ||
199 | + FIELD(RST_SPI1, RESET, 0, 1) | ||
200 | +REG32(RST_CAN0, 0x328) | ||
201 | + FIELD(RST_CAN0, RESET, 0, 1) | ||
202 | +REG32(RST_CAN1, 0x32c) | ||
203 | + FIELD(RST_CAN1, RESET, 0, 1) | ||
204 | +REG32(RST_I2C0, 0x330) | ||
205 | + FIELD(RST_I2C0, RESET, 0, 1) | ||
206 | +REG32(RST_I2C1, 0x334) | ||
207 | + FIELD(RST_I2C1, RESET, 0, 1) | ||
208 | +REG32(RST_DBG_LPD, 0x338) | ||
209 | + FIELD(RST_DBG_LPD, RPU_DBG1_RESET, 5, 1) | ||
210 | + FIELD(RST_DBG_LPD, RPU_DBG0_RESET, 4, 1) | ||
211 | + FIELD(RST_DBG_LPD, RESET_HSDP, 1, 1) | ||
212 | + FIELD(RST_DBG_LPD, RESET, 0, 1) | ||
213 | +REG32(RST_GPIO, 0x33c) | ||
214 | + FIELD(RST_GPIO, RESET, 0, 1) | ||
215 | +REG32(RST_TTC, 0x344) | ||
216 | + FIELD(RST_TTC, TTC3_RESET, 3, 1) | ||
217 | + FIELD(RST_TTC, TTC2_RESET, 2, 1) | ||
218 | + FIELD(RST_TTC, TTC1_RESET, 1, 1) | ||
219 | + FIELD(RST_TTC, TTC0_RESET, 0, 1) | ||
220 | +REG32(RST_TIMESTAMP, 0x348) | ||
221 | + FIELD(RST_TIMESTAMP, RESET, 0, 1) | ||
222 | +REG32(RST_SWDT, 0x34c) | ||
223 | + FIELD(RST_SWDT, RESET, 0, 1) | ||
224 | +REG32(RST_OCM, 0x350) | ||
225 | + FIELD(RST_OCM, RESET, 0, 1) | ||
226 | +REG32(RST_IPI, 0x354) | ||
227 | + FIELD(RST_IPI, RESET, 0, 1) | ||
228 | +REG32(RST_SYSMON, 0x358) | ||
229 | + FIELD(RST_SYSMON, SEQ_RST, 1, 1) | ||
230 | + FIELD(RST_SYSMON, CFG_RST, 0, 1) | ||
231 | +REG32(RST_FPD, 0x360) | ||
232 | + FIELD(RST_FPD, SRST, 1, 1) | ||
233 | + FIELD(RST_FPD, POR, 0, 1) | ||
234 | +REG32(PSM_RST_MODE, 0x370) | ||
235 | + FIELD(PSM_RST_MODE, WAKEUP, 2, 1) | ||
236 | + FIELD(PSM_RST_MODE, RST_MODE, 0, 2) | ||
237 | + | ||
238 | +#define CRL_R_MAX (R_PSM_RST_MODE + 1) | ||
239 | + | ||
240 | +#define RPU_MAX_CPU 2 | ||
241 | + | ||
242 | +struct XlnxVersalCRL { | ||
243 | + SysBusDevice parent_obj; | ||
244 | + qemu_irq irq; | ||
245 | + | ||
246 | + struct { | ||
247 | + ARMCPU *cpu_r5[RPU_MAX_CPU]; | ||
248 | + DeviceState *adma[8]; | ||
249 | + DeviceState *uart[2]; | ||
250 | + DeviceState *gem[2]; | ||
251 | + DeviceState *usb; | ||
252 | + } cfg; | ||
253 | + | ||
254 | + RegisterInfoArray *reg_array; | ||
255 | + uint32_t regs[CRL_R_MAX]; | ||
256 | + RegisterInfo regs_info[CRL_R_MAX]; | ||
257 | +}; | ||
258 | +#endif | ||
259 | diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c | ||
260 | new file mode 100644 | ||
261 | index XXXXXXX..XXXXXXX | ||
262 | --- /dev/null | ||
263 | +++ b/hw/misc/xlnx-versal-crl.c | ||
264 | @@ -XXX,XX +XXX,XX @@ | ||
265 | +/* | ||
266 | + * QEMU model of the Clock-Reset-LPD (CRL). | ||
267 | + * | ||
268 | + * Copyright (c) 2022 Advanced Micro Devices, Inc. | ||
269 | + * SPDX-License-Identifier: GPL-2.0-or-later | ||
270 | + * | ||
271 | + * Written by Edgar E. Iglesias <edgar.iglesias@amd.com> | ||
272 | + */ | ||
273 | + | ||
274 | +#include "qemu/osdep.h" | ||
275 | +#include "qapi/error.h" | ||
276 | +#include "qemu/log.h" | ||
277 | +#include "qemu/bitops.h" | ||
278 | +#include "migration/vmstate.h" | ||
279 | +#include "hw/qdev-properties.h" | ||
280 | +#include "hw/sysbus.h" | ||
281 | +#include "hw/irq.h" | ||
282 | +#include "hw/register.h" | ||
283 | +#include "hw/resettable.h" | ||
284 | + | ||
285 | +#include "target/arm/arm-powerctl.h" | ||
286 | +#include "hw/misc/xlnx-versal-crl.h" | ||
287 | + | ||
288 | +#ifndef XLNX_VERSAL_CRL_ERR_DEBUG | ||
289 | +#define XLNX_VERSAL_CRL_ERR_DEBUG 0 | ||
290 | +#endif | ||
291 | + | ||
292 | +static void crl_update_irq(XlnxVersalCRL *s) | ||
293 | +{ | ||
294 | + bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK]; | ||
295 | + qemu_set_irq(s->irq, pending); | ||
296 | +} | ||
297 | + | ||
298 | +static void crl_status_postw(RegisterInfo *reg, uint64_t val64) | ||
299 | +{ | ||
300 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
301 | + crl_update_irq(s); | ||
302 | +} | ||
303 | + | ||
304 | +static uint64_t crl_enable_prew(RegisterInfo *reg, uint64_t val64) | ||
305 | +{ | ||
306 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
307 | + uint32_t val = val64; | ||
308 | + | ||
309 | + s->regs[R_IR_MASK] &= ~val; | ||
310 | + crl_update_irq(s); | ||
311 | + return 0; | ||
312 | +} | ||
313 | + | ||
314 | +static uint64_t crl_disable_prew(RegisterInfo *reg, uint64_t val64) | ||
315 | +{ | ||
316 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
317 | + uint32_t val = val64; | ||
318 | + | ||
319 | + s->regs[R_IR_MASK] |= val; | ||
320 | + crl_update_irq(s); | ||
321 | + return 0; | ||
322 | +} | ||
323 | + | ||
324 | +static void crl_reset_dev(XlnxVersalCRL *s, DeviceState *dev, | ||
325 | + bool rst_old, bool rst_new) | ||
326 | +{ | ||
327 | + device_cold_reset(dev); | ||
328 | +} | ||
329 | + | ||
330 | +static void crl_reset_cpu(XlnxVersalCRL *s, ARMCPU *armcpu, | ||
331 | + bool rst_old, bool rst_new) | ||
332 | +{ | ||
333 | + if (rst_new) { | ||
334 | + arm_set_cpu_off(armcpu->mp_affinity); | ||
335 | + } else { | 70 | + } else { |
336 | + arm_set_cpu_on_and_reset(armcpu->mp_affinity); | 71 | + return 1; |
337 | + } | 72 | + } |
338 | +} | 73 | +} |
339 | + | 74 | + |
340 | +#define REGFIELD_RESET(type, s, reg, f, new_val, dev) { \ | 75 | /* |
341 | + bool old_f = ARRAY_FIELD_EX32((s)->regs, reg, f); \ | 76 | * Raise an exception to the debug target el. |
342 | + bool new_f = FIELD_EX32(new_val, reg, f); \ | 77 | * Modify syndrome to indicate when origin and target EL are the same. |
343 | + \ | ||
344 | + /* Detect edges. */ \ | ||
345 | + if (dev && old_f != new_f) { \ | ||
346 | + crl_reset_ ## type(s, dev, old_f, new_f); \ | ||
347 | + } \ | ||
348 | +} | ||
349 | + | ||
350 | +static uint64_t crl_rst_r5_prew(RegisterInfo *reg, uint64_t val64) | ||
351 | +{ | ||
352 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
353 | + | ||
354 | + REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU0, val64, s->cfg.cpu_r5[0]); | ||
355 | + REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU1, val64, s->cfg.cpu_r5[1]); | ||
356 | + return val64; | ||
357 | +} | ||
358 | + | ||
359 | +static uint64_t crl_rst_adma_prew(RegisterInfo *reg, uint64_t val64) | ||
360 | +{ | ||
361 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
362 | + int i; | ||
363 | + | ||
364 | + /* A single register fans out to all ADMA reset inputs. */ | ||
365 | + for (i = 0; i < ARRAY_SIZE(s->cfg.adma); i++) { | ||
366 | + REGFIELD_RESET(dev, s, RST_ADMA, RESET, val64, s->cfg.adma[i]); | ||
367 | + } | ||
368 | + return val64; | ||
369 | +} | ||
370 | + | ||
371 | +static uint64_t crl_rst_uart0_prew(RegisterInfo *reg, uint64_t val64) | ||
372 | +{ | ||
373 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
374 | + | ||
375 | + REGFIELD_RESET(dev, s, RST_UART0, RESET, val64, s->cfg.uart[0]); | ||
376 | + return val64; | ||
377 | +} | ||
378 | + | ||
379 | +static uint64_t crl_rst_uart1_prew(RegisterInfo *reg, uint64_t val64) | ||
380 | +{ | ||
381 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
382 | + | ||
383 | + REGFIELD_RESET(dev, s, RST_UART1, RESET, val64, s->cfg.uart[1]); | ||
384 | + return val64; | ||
385 | +} | ||
386 | + | ||
387 | +static uint64_t crl_rst_gem0_prew(RegisterInfo *reg, uint64_t val64) | ||
388 | +{ | ||
389 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
390 | + | ||
391 | + REGFIELD_RESET(dev, s, RST_GEM0, RESET, val64, s->cfg.gem[0]); | ||
392 | + return val64; | ||
393 | +} | ||
394 | + | ||
395 | +static uint64_t crl_rst_gem1_prew(RegisterInfo *reg, uint64_t val64) | ||
396 | +{ | ||
397 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
398 | + | ||
399 | + REGFIELD_RESET(dev, s, RST_GEM1, RESET, val64, s->cfg.gem[1]); | ||
400 | + return val64; | ||
401 | +} | ||
402 | + | ||
403 | +static uint64_t crl_rst_usb_prew(RegisterInfo *reg, uint64_t val64) | ||
404 | +{ | ||
405 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
406 | + | ||
407 | + REGFIELD_RESET(dev, s, RST_USB0, RESET, val64, s->cfg.usb); | ||
408 | + return val64; | ||
409 | +} | ||
410 | + | ||
411 | +static const RegisterAccessInfo crl_regs_info[] = { | ||
412 | + { .name = "ERR_CTRL", .addr = A_ERR_CTRL, | ||
413 | + },{ .name = "IR_STATUS", .addr = A_IR_STATUS, | ||
414 | + .w1c = 0x1, | ||
415 | + .post_write = crl_status_postw, | ||
416 | + },{ .name = "IR_MASK", .addr = A_IR_MASK, | ||
417 | + .reset = 0x1, | ||
418 | + .ro = 0x1, | ||
419 | + },{ .name = "IR_ENABLE", .addr = A_IR_ENABLE, | ||
420 | + .pre_write = crl_enable_prew, | ||
421 | + },{ .name = "IR_DISABLE", .addr = A_IR_DISABLE, | ||
422 | + .pre_write = crl_disable_prew, | ||
423 | + },{ .name = "WPROT", .addr = A_WPROT, | ||
424 | + },{ .name = "PLL_CLK_OTHER_DMN", .addr = A_PLL_CLK_OTHER_DMN, | ||
425 | + .reset = 0x1, | ||
426 | + .rsvd = 0xe, | ||
427 | + },{ .name = "RPLL_CTRL", .addr = A_RPLL_CTRL, | ||
428 | + .reset = 0x24809, | ||
429 | + .rsvd = 0xf88c00f6, | ||
430 | + },{ .name = "RPLL_CFG", .addr = A_RPLL_CFG, | ||
431 | + .reset = 0x2000000, | ||
432 | + .rsvd = 0x1801210, | ||
433 | + },{ .name = "RPLL_FRAC_CFG", .addr = A_RPLL_FRAC_CFG, | ||
434 | + .rsvd = 0x7e330000, | ||
435 | + },{ .name = "PLL_STATUS", .addr = A_PLL_STATUS, | ||
436 | + .reset = R_PLL_STATUS_RPLL_STABLE_MASK | | ||
437 | + R_PLL_STATUS_RPLL_LOCK_MASK, | ||
438 | + .rsvd = 0xfa, | ||
439 | + .ro = 0x5, | ||
440 | + },{ .name = "RPLL_TO_XPD_CTRL", .addr = A_RPLL_TO_XPD_CTRL, | ||
441 | + .reset = 0x2000100, | ||
442 | + .rsvd = 0xfdfc00ff, | ||
443 | + },{ .name = "LPD_TOP_SWITCH_CTRL", .addr = A_LPD_TOP_SWITCH_CTRL, | ||
444 | + .reset = 0x6000300, | ||
445 | + .rsvd = 0xf9fc00f8, | ||
446 | + },{ .name = "LPD_LSBUS_CTRL", .addr = A_LPD_LSBUS_CTRL, | ||
447 | + .reset = 0x2000800, | ||
448 | + .rsvd = 0xfdfc00f8, | ||
449 | + },{ .name = "CPU_R5_CTRL", .addr = A_CPU_R5_CTRL, | ||
450 | + .reset = 0xe000300, | ||
451 | + .rsvd = 0xe1fc00f8, | ||
452 | + },{ .name = "IOU_SWITCH_CTRL", .addr = A_IOU_SWITCH_CTRL, | ||
453 | + .reset = 0x2000500, | ||
454 | + .rsvd = 0xfdfc00f8, | ||
455 | + },{ .name = "GEM0_REF_CTRL", .addr = A_GEM0_REF_CTRL, | ||
456 | + .reset = 0xe000a00, | ||
457 | + .rsvd = 0xf1fc00f8, | ||
458 | + },{ .name = "GEM1_REF_CTRL", .addr = A_GEM1_REF_CTRL, | ||
459 | + .reset = 0xe000a00, | ||
460 | + .rsvd = 0xf1fc00f8, | ||
461 | + },{ .name = "GEM_TSU_REF_CTRL", .addr = A_GEM_TSU_REF_CTRL, | ||
462 | + .reset = 0x300, | ||
463 | + .rsvd = 0xfdfc00f8, | ||
464 | + },{ .name = "USB0_BUS_REF_CTRL", .addr = A_USB0_BUS_REF_CTRL, | ||
465 | + .reset = 0x2001900, | ||
466 | + .rsvd = 0xfdfc00f8, | ||
467 | + },{ .name = "UART0_REF_CTRL", .addr = A_UART0_REF_CTRL, | ||
468 | + .reset = 0xc00, | ||
469 | + .rsvd = 0xfdfc00f8, | ||
470 | + },{ .name = "UART1_REF_CTRL", .addr = A_UART1_REF_CTRL, | ||
471 | + .reset = 0xc00, | ||
472 | + .rsvd = 0xfdfc00f8, | ||
473 | + },{ .name = "SPI0_REF_CTRL", .addr = A_SPI0_REF_CTRL, | ||
474 | + .reset = 0x600, | ||
475 | + .rsvd = 0xfdfc00f8, | ||
476 | + },{ .name = "SPI1_REF_CTRL", .addr = A_SPI1_REF_CTRL, | ||
477 | + .reset = 0x600, | ||
478 | + .rsvd = 0xfdfc00f8, | ||
479 | + },{ .name = "CAN0_REF_CTRL", .addr = A_CAN0_REF_CTRL, | ||
480 | + .reset = 0xc00, | ||
481 | + .rsvd = 0xfdfc00f8, | ||
482 | + },{ .name = "CAN1_REF_CTRL", .addr = A_CAN1_REF_CTRL, | ||
483 | + .reset = 0xc00, | ||
484 | + .rsvd = 0xfdfc00f8, | ||
485 | + },{ .name = "I2C0_REF_CTRL", .addr = A_I2C0_REF_CTRL, | ||
486 | + .reset = 0xc00, | ||
487 | + .rsvd = 0xfdfc00f8, | ||
488 | + },{ .name = "I2C1_REF_CTRL", .addr = A_I2C1_REF_CTRL, | ||
489 | + .reset = 0xc00, | ||
490 | + .rsvd = 0xfdfc00f8, | ||
491 | + },{ .name = "DBG_LPD_CTRL", .addr = A_DBG_LPD_CTRL, | ||
492 | + .reset = 0x300, | ||
493 | + .rsvd = 0xfdfc00f8, | ||
494 | + },{ .name = "TIMESTAMP_REF_CTRL", .addr = A_TIMESTAMP_REF_CTRL, | ||
495 | + .reset = 0x2000c00, | ||
496 | + .rsvd = 0xfdfc00f8, | ||
497 | + },{ .name = "CRL_SAFETY_CHK", .addr = A_CRL_SAFETY_CHK, | ||
498 | + },{ .name = "PSM_REF_CTRL", .addr = A_PSM_REF_CTRL, | ||
499 | + .reset = 0xf04, | ||
500 | + .rsvd = 0xfffc00f8, | ||
501 | + },{ .name = "DBG_TSTMP_CTRL", .addr = A_DBG_TSTMP_CTRL, | ||
502 | + .reset = 0x300, | ||
503 | + .rsvd = 0xfdfc00f8, | ||
504 | + },{ .name = "CPM_TOPSW_REF_CTRL", .addr = A_CPM_TOPSW_REF_CTRL, | ||
505 | + .reset = 0x300, | ||
506 | + .rsvd = 0xfdfc00f8, | ||
507 | + },{ .name = "USB3_DUAL_REF_CTRL", .addr = A_USB3_DUAL_REF_CTRL, | ||
508 | + .reset = 0x3c00, | ||
509 | + .rsvd = 0xfdfc00f8, | ||
510 | + },{ .name = "RST_CPU_R5", .addr = A_RST_CPU_R5, | ||
511 | + .reset = 0x17, | ||
512 | + .rsvd = 0x8, | ||
513 | + .pre_write = crl_rst_r5_prew, | ||
514 | + },{ .name = "RST_ADMA", .addr = A_RST_ADMA, | ||
515 | + .reset = 0x1, | ||
516 | + .pre_write = crl_rst_adma_prew, | ||
517 | + },{ .name = "RST_GEM0", .addr = A_RST_GEM0, | ||
518 | + .reset = 0x1, | ||
519 | + .pre_write = crl_rst_gem0_prew, | ||
520 | + },{ .name = "RST_GEM1", .addr = A_RST_GEM1, | ||
521 | + .reset = 0x1, | ||
522 | + .pre_write = crl_rst_gem1_prew, | ||
523 | + },{ .name = "RST_SPARE", .addr = A_RST_SPARE, | ||
524 | + .reset = 0x1, | ||
525 | + },{ .name = "RST_USB0", .addr = A_RST_USB0, | ||
526 | + .reset = 0x1, | ||
527 | + .pre_write = crl_rst_usb_prew, | ||
528 | + },{ .name = "RST_UART0", .addr = A_RST_UART0, | ||
529 | + .reset = 0x1, | ||
530 | + .pre_write = crl_rst_uart0_prew, | ||
531 | + },{ .name = "RST_UART1", .addr = A_RST_UART1, | ||
532 | + .reset = 0x1, | ||
533 | + .pre_write = crl_rst_uart1_prew, | ||
534 | + },{ .name = "RST_SPI0", .addr = A_RST_SPI0, | ||
535 | + .reset = 0x1, | ||
536 | + },{ .name = "RST_SPI1", .addr = A_RST_SPI1, | ||
537 | + .reset = 0x1, | ||
538 | + },{ .name = "RST_CAN0", .addr = A_RST_CAN0, | ||
539 | + .reset = 0x1, | ||
540 | + },{ .name = "RST_CAN1", .addr = A_RST_CAN1, | ||
541 | + .reset = 0x1, | ||
542 | + },{ .name = "RST_I2C0", .addr = A_RST_I2C0, | ||
543 | + .reset = 0x1, | ||
544 | + },{ .name = "RST_I2C1", .addr = A_RST_I2C1, | ||
545 | + .reset = 0x1, | ||
546 | + },{ .name = "RST_DBG_LPD", .addr = A_RST_DBG_LPD, | ||
547 | + .reset = 0x33, | ||
548 | + .rsvd = 0xcc, | ||
549 | + },{ .name = "RST_GPIO", .addr = A_RST_GPIO, | ||
550 | + .reset = 0x1, | ||
551 | + },{ .name = "RST_TTC", .addr = A_RST_TTC, | ||
552 | + .reset = 0xf, | ||
553 | + },{ .name = "RST_TIMESTAMP", .addr = A_RST_TIMESTAMP, | ||
554 | + .reset = 0x1, | ||
555 | + },{ .name = "RST_SWDT", .addr = A_RST_SWDT, | ||
556 | + .reset = 0x1, | ||
557 | + },{ .name = "RST_OCM", .addr = A_RST_OCM, | ||
558 | + },{ .name = "RST_IPI", .addr = A_RST_IPI, | ||
559 | + },{ .name = "RST_FPD", .addr = A_RST_FPD, | ||
560 | + .reset = 0x3, | ||
561 | + },{ .name = "PSM_RST_MODE", .addr = A_PSM_RST_MODE, | ||
562 | + .reset = 0x1, | ||
563 | + .rsvd = 0xf8, | ||
564 | + } | ||
565 | +}; | ||
566 | + | ||
567 | +static void crl_reset_enter(Object *obj, ResetType type) | ||
568 | +{ | ||
569 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj); | ||
570 | + unsigned int i; | ||
571 | + | ||
572 | + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { | ||
573 | + register_reset(&s->regs_info[i]); | ||
574 | + } | ||
575 | +} | ||
576 | + | ||
577 | +static void crl_reset_hold(Object *obj) | ||
578 | +{ | ||
579 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj); | ||
580 | + | ||
581 | + crl_update_irq(s); | ||
582 | +} | ||
583 | + | ||
584 | +static const MemoryRegionOps crl_ops = { | ||
585 | + .read = register_read_memory, | ||
586 | + .write = register_write_memory, | ||
587 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
588 | + .valid = { | ||
589 | + .min_access_size = 4, | ||
590 | + .max_access_size = 4, | ||
591 | + }, | ||
592 | +}; | ||
593 | + | ||
594 | +static void crl_init(Object *obj) | ||
595 | +{ | ||
596 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj); | ||
597 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
598 | + int i; | ||
599 | + | ||
600 | + s->reg_array = | ||
601 | + register_init_block32(DEVICE(obj), crl_regs_info, | ||
602 | + ARRAY_SIZE(crl_regs_info), | ||
603 | + s->regs_info, s->regs, | ||
604 | + &crl_ops, | ||
605 | + XLNX_VERSAL_CRL_ERR_DEBUG, | ||
606 | + CRL_R_MAX * 4); | ||
607 | + sysbus_init_mmio(sbd, &s->reg_array->mem); | ||
608 | + sysbus_init_irq(sbd, &s->irq); | ||
609 | + | ||
610 | + for (i = 0; i < ARRAY_SIZE(s->cfg.cpu_r5); ++i) { | ||
611 | + object_property_add_link(obj, "cpu_r5[*]", TYPE_ARM_CPU, | ||
612 | + (Object **)&s->cfg.cpu_r5[i], | ||
613 | + qdev_prop_allow_set_link_before_realize, | ||
614 | + OBJ_PROP_LINK_STRONG); | ||
615 | + } | ||
616 | + | ||
617 | + for (i = 0; i < ARRAY_SIZE(s->cfg.adma); ++i) { | ||
618 | + object_property_add_link(obj, "adma[*]", TYPE_DEVICE, | ||
619 | + (Object **)&s->cfg.adma[i], | ||
620 | + qdev_prop_allow_set_link_before_realize, | ||
621 | + OBJ_PROP_LINK_STRONG); | ||
622 | + } | ||
623 | + | ||
624 | + for (i = 0; i < ARRAY_SIZE(s->cfg.uart); ++i) { | ||
625 | + object_property_add_link(obj, "uart[*]", TYPE_DEVICE, | ||
626 | + (Object **)&s->cfg.uart[i], | ||
627 | + qdev_prop_allow_set_link_before_realize, | ||
628 | + OBJ_PROP_LINK_STRONG); | ||
629 | + } | ||
630 | + | ||
631 | + for (i = 0; i < ARRAY_SIZE(s->cfg.gem); ++i) { | ||
632 | + object_property_add_link(obj, "gem[*]", TYPE_DEVICE, | ||
633 | + (Object **)&s->cfg.gem[i], | ||
634 | + qdev_prop_allow_set_link_before_realize, | ||
635 | + OBJ_PROP_LINK_STRONG); | ||
636 | + } | ||
637 | + | ||
638 | + object_property_add_link(obj, "usb", TYPE_DEVICE, | ||
639 | + (Object **)&s->cfg.gem[i], | ||
640 | + qdev_prop_allow_set_link_before_realize, | ||
641 | + OBJ_PROP_LINK_STRONG); | ||
642 | +} | ||
643 | + | ||
644 | +static void crl_finalize(Object *obj) | ||
645 | +{ | ||
646 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj); | ||
647 | + register_finalize_block(s->reg_array); | ||
648 | +} | ||
649 | + | ||
650 | +static const VMStateDescription vmstate_crl = { | ||
651 | + .name = TYPE_XLNX_VERSAL_CRL, | ||
652 | + .version_id = 1, | ||
653 | + .minimum_version_id = 1, | ||
654 | + .fields = (VMStateField[]) { | ||
655 | + VMSTATE_UINT32_ARRAY(regs, XlnxVersalCRL, CRL_R_MAX), | ||
656 | + VMSTATE_END_OF_LIST(), | ||
657 | + } | ||
658 | +}; | ||
659 | + | ||
660 | +static void crl_class_init(ObjectClass *klass, void *data) | ||
661 | +{ | ||
662 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
663 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
664 | + | ||
665 | + dc->vmsd = &vmstate_crl; | ||
666 | + | ||
667 | + rc->phases.enter = crl_reset_enter; | ||
668 | + rc->phases.hold = crl_reset_hold; | ||
669 | +} | ||
670 | + | ||
671 | +static const TypeInfo crl_info = { | ||
672 | + .name = TYPE_XLNX_VERSAL_CRL, | ||
673 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
674 | + .instance_size = sizeof(XlnxVersalCRL), | ||
675 | + .class_init = crl_class_init, | ||
676 | + .instance_init = crl_init, | ||
677 | + .instance_finalize = crl_finalize, | ||
678 | +}; | ||
679 | + | ||
680 | +static void crl_register_types(void) | ||
681 | +{ | ||
682 | + type_register_static(&crl_info); | ||
683 | +} | ||
684 | + | ||
685 | +type_init(crl_register_types) | ||
686 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
687 | index XXXXXXX..XXXXXXX 100644 | ||
688 | --- a/hw/misc/meson.build | ||
689 | +++ b/hw/misc/meson.build | ||
690 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) | ||
691 | softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c')) | ||
692 | specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c')) | ||
693 | specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c')) | ||
694 | +specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c')) | ||
695 | softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files( | ||
696 | 'xlnx-versal-xramc.c', | ||
697 | 'xlnx-versal-pmc-iou-slcr.c', | ||
698 | -- | 78 | -- |
699 | 2.25.1 | 79 | 2.25.1 | diff view generated by jsdifflib |
1 | In exynos4210_init_board_irqs(), the loop that handles IRQ lines that | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | are in a range that applies to the internal combiner only creates a | ||
3 | splitter for those interrupts which go to both the internal combiner | ||
4 | and to the external GIC, but it does nothing at all for the | ||
5 | interrupts which don't go to the external GIC, leaving the | ||
6 | irq_table[] array element empty for those. (This will result in | ||
7 | those interrupts simply being lost, not in a QEMU crash.) | ||
8 | 2 | ||
9 | I don't have a reliable datasheet for this SoC, but since we do wire | 3 | We were using arm_is_secure and is_a64, which are |
10 | up one interrupt line in this category (the HDMI I2C device on | 4 | tests against the current EL, as opposed to |
11 | interrupt 16,1), this seems like it must be a bug in the existing | 5 | arm_el_is_aa64 and arm_is_secure_below_el3, which |
12 | QEMU code. Fill in the irq_table[] entries where we're not splitting | 6 | can be applied to a different EL than current. |
13 | the IRQ to both the internal combiner and the external GIC with the | 7 | Consolidate the two tests. |
14 | IRQ line of the internal combiner. (That is, these IRQ lines go to | ||
15 | just one device, not multiple.) | ||
16 | 8 | ||
17 | This bug didn't have any visible guest effects because the only | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
18 | implemented device that was affected was the HDMI I2C controller, | 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
19 | and we never connect any I2C devices to that bus. | 11 | Message-id: 20220609202901.1177572-24-richard.henderson@linaro.org |
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | target/arm/helper.c | 23 +++++++++-------------- | ||
15 | 1 file changed, 9 insertions(+), 14 deletions(-) | ||
20 | 16 | ||
21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
22 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
23 | Message-id: 20220404154658.565020-14-peter.maydell@linaro.org | ||
24 | --- | ||
25 | hw/arm/exynos4210.c | 2 ++ | ||
26 | 1 file changed, 2 insertions(+) | ||
27 | |||
28 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/hw/arm/exynos4210.c | 19 | --- a/target/arm/helper.c |
31 | +++ b/hw/arm/exynos4210.c | 20 | +++ b/target/arm/helper.c |
32 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | 21 | @@ -XXX,XX +XXX,XX @@ int fp_exception_el(CPUARMState *env, int cur_el) |
33 | qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); | 22 | int fpen = FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN); |
34 | qdev_connect_gpio_out(splitter, 1, | 23 | |
35 | qdev_get_gpio_in(extgicdev, irq_id - 32)); | 24 | switch (fpen) { |
36 | + } else { | 25 | + case 1: |
37 | + s->irq_table[n] = is->int_combiner_irq[n]; | 26 | + if (cur_el != 0) { |
27 | + break; | ||
28 | + } | ||
29 | + /* fall through */ | ||
30 | case 0: | ||
31 | case 2: | ||
32 | - if (cur_el == 0 || cur_el == 1) { | ||
33 | - /* Trap to PL1, which might be EL1 or EL3 */ | ||
34 | - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { | ||
35 | - return 3; | ||
36 | - } | ||
37 | - return 1; | ||
38 | - } | ||
39 | - if (cur_el == 3 && !is_a64(env)) { | ||
40 | - /* Secure PL1 running at EL3 */ | ||
41 | + /* Trap from Secure PL0 or PL1 to Secure PL1. */ | ||
42 | + if (!arm_el_is_aa64(env, 3) | ||
43 | + && (cur_el == 3 || arm_is_secure_below_el3(env))) { | ||
44 | return 3; | ||
45 | } | ||
46 | - break; | ||
47 | - case 1: | ||
48 | - if (cur_el == 0) { | ||
49 | + if (cur_el <= 1) { | ||
50 | return 1; | ||
51 | } | ||
52 | break; | ||
53 | - case 3: | ||
54 | - break; | ||
38 | } | 55 | } |
39 | } | 56 | } |
40 | /* | 57 | |
41 | -- | 58 | -- |
42 | 2.25.1 | 59 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Hao Wu <wuhaotsh@google.com> | 1 | From: Hao Wu <wuhaotsh@google.com> |
---|---|---|---|
2 | 2 | ||
3 | This patch uses the defined fields to describe PWRON STRAPs for | 3 | Creating 1GB image for a simple qtest is unnecessary |
4 | better readability. | 4 | and could lead to failures. We reduce the image size |
5 | to 1MB to reduce the test overhead. | ||
5 | 6 | ||
6 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | 7 | Signed-off-by: Hao Wu <wuhaotsh@google.com> |
7 | Reviewed-by: Patrick Venture <venture@google.com> | 8 | Message-id: 20220609214125.4192212-1-wuhaotsh@google.com |
8 | Message-id: 20220411165842.3912945-3-wuhaotsh@google.com | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 11 | --- |
12 | hw/arm/npcm7xx_boards.c | 24 +++++++++++++++++++----- | 12 | tests/qtest/npcm7xx_sdhci-test.c | 2 +- |
13 | 1 file changed, 19 insertions(+), 5 deletions(-) | 13 | 1 file changed, 1 insertion(+), 1 deletion(-) |
14 | 14 | ||
15 | diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c | 15 | diff --git a/tests/qtest/npcm7xx_sdhci-test.c b/tests/qtest/npcm7xx_sdhci-test.c |
16 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/arm/npcm7xx_boards.c | 17 | --- a/tests/qtest/npcm7xx_sdhci-test.c |
18 | +++ b/hw/arm/npcm7xx_boards.c | 18 | +++ b/tests/qtest/npcm7xx_sdhci-test.c |
19 | @@ -XXX,XX +XXX,XX @@ | 19 | @@ -XXX,XX +XXX,XX @@ |
20 | #include "sysemu/sysemu.h" | 20 | #define NPCM7XX_REG_SIZE 0x100 |
21 | #include "sysemu/block-backend.h" | 21 | #define NPCM7XX_MMC_BA 0xF0842000 |
22 | 22 | #define NPCM7XX_BLK_SIZE 512 | |
23 | -#define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7 | 23 | -#define NPCM7XX_TEST_IMAGE_SIZE (1 << 30) |
24 | -#define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff | 24 | +#define NPCM7XX_TEST_IMAGE_SIZE (1 << 20) |
25 | -#define QUANTA_GBS_POWER_ON_STRAPS 0x000017ff | 25 | |
26 | -#define KUDO_BMC_POWER_ON_STRAPS 0x00001fff | 26 | char *sd_path; |
27 | -#define MORI_BMC_POWER_ON_STRAPS 0x00001fff | ||
28 | +#define NPCM7XX_POWER_ON_STRAPS_DEFAULT ( \ | ||
29 | + NPCM7XX_PWRON_STRAP_SPI0F18 | \ | ||
30 | + NPCM7XX_PWRON_STRAP_SFAB | \ | ||
31 | + NPCM7XX_PWRON_STRAP_BSPA | \ | ||
32 | + NPCM7XX_PWRON_STRAP_FUP(FUP_NORM_UART2) | \ | ||
33 | + NPCM7XX_PWRON_STRAP_SECEN | \ | ||
34 | + NPCM7XX_PWRON_STRAP_HIZ | \ | ||
35 | + NPCM7XX_PWRON_STRAP_ECC | \ | ||
36 | + NPCM7XX_PWRON_STRAP_RESERVE1 | \ | ||
37 | + NPCM7XX_PWRON_STRAP_J2EN | \ | ||
38 | + NPCM7XX_PWRON_STRAP_CKFRQ(CKFRQ_DEFAULT)) | ||
39 | + | ||
40 | +#define NPCM750_EVB_POWER_ON_STRAPS ( \ | ||
41 | + NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_J2EN) | ||
42 | +#define QUANTA_GSJ_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT | ||
43 | +#define QUANTA_GBS_POWER_ON_STRAPS ( \ | ||
44 | + NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_SFAB) | ||
45 | +#define KUDO_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT | ||
46 | +#define MORI_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT | ||
47 | |||
48 | static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin"; | ||
49 | 27 | ||
50 | -- | 28 | -- |
51 | 2.25.1 | 29 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Hao Wu <wuhaotsh@google.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Similar to the Aspeed code in include/misc/aspeed_scu.h, we define | 3 | Because reset always initializes the AA64 version, SCR_EL3, |
4 | the PWRON STRAP fields in their corresponding module for NPCM7XX. | 4 | test the mode of EL3 instead of the type of the cpreg. |
5 | 5 | ||
6 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Reviewed-by: Patrick Venture <venture@google.com> | 7 | Message-id: 20220609214657.1217913-2-richard.henderson@linaro.org |
8 | Message-id: 20220411165842.3912945-2-wuhaotsh@google.com | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 10 | --- |
12 | include/hw/misc/npcm7xx_gcr.h | 30 ++++++++++++++++++++++++++++++ | 11 | target/arm/helper.c | 14 ++++++++------ |
13 | 1 file changed, 30 insertions(+) | 12 | 1 file changed, 8 insertions(+), 6 deletions(-) |
14 | 13 | ||
15 | diff --git a/include/hw/misc/npcm7xx_gcr.h b/include/hw/misc/npcm7xx_gcr.h | 14 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/include/hw/misc/npcm7xx_gcr.h | 16 | --- a/target/arm/helper.c |
18 | +++ b/include/hw/misc/npcm7xx_gcr.h | 17 | +++ b/target/arm/helper.c |
19 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
20 | #include "exec/memory.h" | 19 | uint32_t valid_mask = 0x3fff; |
21 | #include "hw/sysbus.h" | 20 | ARMCPU *cpu = env_archcpu(env); |
22 | 21 | ||
23 | +/* | 22 | - if (ri->state == ARM_CP_STATE_AA64) { |
24 | + * NPCM7XX PWRON STRAP bit fields | 23 | - if (arm_feature(env, ARM_FEATURE_AARCH64) && |
25 | + * 12: SPI0 powered by VSBV3 at 1.8V | 24 | - !cpu_isar_feature(aa64_aa32_el1, cpu)) { |
26 | + * 11: System flash attached to BMC | 25 | - value |= SCR_FW | SCR_AW; /* these two bits are RES1. */ |
27 | + * 10: BSP alternative pins. | 26 | - } |
28 | + * 9:8: Flash UART command route enabled. | 27 | - valid_mask &= ~SCR_NET; |
29 | + * 7: Security enabled. | 28 | + /* |
30 | + * 6: HI-Z state control. | 29 | + * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always |
31 | + * 5: ECC disabled. | 30 | + * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64. |
32 | + * 4: Reserved | 31 | + * Instead, choose the format based on the mode of EL3. |
33 | + * 3: JTAG2 enabled. | 32 | + */ |
34 | + * 2:0: CPU and DRAM clock frequency. | 33 | + if (arm_el_is_aa64(env, 3)) { |
35 | + */ | 34 | + value |= SCR_FW | SCR_AW; /* RES1 */ |
36 | +#define NPCM7XX_PWRON_STRAP_SPI0F18 BIT(12) | 35 | + valid_mask &= ~SCR_NET; /* RES0 */ |
37 | +#define NPCM7XX_PWRON_STRAP_SFAB BIT(11) | 36 | |
38 | +#define NPCM7XX_PWRON_STRAP_BSPA BIT(10) | 37 | if (cpu_isar_feature(aa64_ras, cpu)) { |
39 | +#define NPCM7XX_PWRON_STRAP_FUP(x) ((x) << 8) | 38 | valid_mask |= SCR_TERR; |
40 | +#define FUP_NORM_UART2 3 | ||
41 | +#define FUP_PROG_UART3 2 | ||
42 | +#define FUP_PROG_UART2 1 | ||
43 | +#define FUP_NORM_UART3 0 | ||
44 | +#define NPCM7XX_PWRON_STRAP_SECEN BIT(7) | ||
45 | +#define NPCM7XX_PWRON_STRAP_HIZ BIT(6) | ||
46 | +#define NPCM7XX_PWRON_STRAP_ECC BIT(5) | ||
47 | +#define NPCM7XX_PWRON_STRAP_RESERVE1 BIT(4) | ||
48 | +#define NPCM7XX_PWRON_STRAP_J2EN BIT(3) | ||
49 | +#define NPCM7XX_PWRON_STRAP_CKFRQ(x) (x) | ||
50 | +#define CKFRQ_SKIPINIT 0x000 | ||
51 | +#define CKFRQ_DEFAULT 0x111 | ||
52 | + | ||
53 | /* | ||
54 | * Number of registers in our device state structure. Don't change this without | ||
55 | * incrementing the version_id in the vmstate. | ||
56 | -- | 39 | -- |
57 | 2.25.1 | 40 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Describe that the gic-version influences the maximum number of CPUs. | 3 | Since DDI0487F.a, the RW bit is RAO/WI. When specifically |
4 | targeting such a cpu, e.g. cortex-a76, it is legitimate to | ||
5 | ignore the bit within the secure monitor. | ||
4 | 6 | ||
5 | Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> | 7 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1062 |
6 | Message-id: 20220413231456.35811-1-heinrich.schuchardt@canonical.com | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | [PMM: minor punctuation tweaks] | 9 | Message-id: 20220609214657.1217913-3-richard.henderson@linaro.org |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 12 | --- |
11 | docs/system/arm/virt.rst | 4 ++-- | 13 | target/arm/cpu.h | 5 +++++ |
12 | 1 file changed, 2 insertions(+), 2 deletions(-) | 14 | target/arm/helper.c | 4 ++++ |
15 | 2 files changed, 9 insertions(+) | ||
13 | 16 | ||
14 | diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst | 17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
15 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/docs/system/arm/virt.rst | 19 | --- a/target/arm/cpu.h |
17 | +++ b/docs/system/arm/virt.rst | 20 | +++ b/target/arm/cpu.h |
18 | @@ -XXX,XX +XXX,XX @@ gic-version | 21 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) |
19 | Valid values are: | 22 | return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; |
20 | 23 | } | |
21 | ``2`` | 24 | |
22 | - GICv2 | 25 | +static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id) |
23 | + GICv2. Note that this limits the number of CPUs to 8. | 26 | +{ |
24 | ``3`` | 27 | + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2; |
25 | - GICv3 | 28 | +} |
26 | + GICv3. This allows up to 512 CPUs. | 29 | + |
27 | ``host`` | 30 | static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) |
28 | Use the same GIC version the host provides, when using KVM | 31 | { |
29 | ``max`` | 32 | return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0; |
33 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/target/arm/helper.c | ||
36 | +++ b/target/arm/helper.c | ||
37 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
38 | value |= SCR_FW | SCR_AW; /* RES1 */ | ||
39 | valid_mask &= ~SCR_NET; /* RES0 */ | ||
40 | |||
41 | + if (!cpu_isar_feature(aa64_aa32_el1, cpu) && | ||
42 | + !cpu_isar_feature(aa64_aa32_el2, cpu)) { | ||
43 | + value |= SCR_RW; /* RAO/WI */ | ||
44 | + } | ||
45 | if (cpu_isar_feature(aa64_ras, cpu)) { | ||
46 | valid_mask |= SCR_TERR; | ||
47 | } | ||
30 | -- | 48 | -- |
31 | 2.25.1 | 49 | 2.25.1 | diff view generated by jsdifflib |
1 | Switch the creation of the external GIC to the new-style "embedded in | 1 | In two places in gdbstub.c we look at gdbserver_state.init to decide |
---|---|---|---|
2 | state struct" approach, so we can easily refer to the object | 2 | whether we're going to do a semihosting syscall via the gdb remote |
3 | elsewhere during realize. | 3 | protocol: |
4 | * when setting up, if the user didn't explicitly select either | ||
5 | native semihosting or gdb semihosting, we autoselect, with the | ||
6 | intended behaviour "use gdb if gdb is connected" | ||
7 | * when the semihosting layer attempts to do a syscall via gdb, we | ||
8 | silently ignore it if the gdbstub wasn't actually set up | ||
4 | 9 | ||
10 | However, if the user's commandline sets up the gdbstub but tells QEMU | ||
11 | to start rather than waiting for a GDB to connect (eg using '-s' but | ||
12 | not '-S'), then we will have gdbserver_state.init true but no actual | ||
13 | connection; an attempt to use gdb syscalls will then crash because we | ||
14 | try to use gdbserver_state.c_cpu when it hasn't been set up: | ||
15 | |||
16 | #0 0x00007ffff6803ba8 in qemu_cpu_kick (cpu=0x0) at ../../softmmu/cpus.c:457 | ||
17 | #1 0x00007ffff6c03913 in gdb_do_syscallv (cb=0x7ffff6c19944 <common_semi_cb>, | ||
18 | fmt=0x7ffff7573b7e "", va=0x7ffff56294c0) at ../../gdbstub.c:2946 | ||
19 | #2 0x00007ffff6c19c3a in common_semi_gdb_syscall (cs=0x7ffff83fe060, | ||
20 | cb=0x7ffff6c19944 <common_semi_cb>, fmt=0x7ffff7573b75 "isatty,%x") | ||
21 | at ../../semihosting/arm-compat-semi.c:494 | ||
22 | #3 0x00007ffff6c1a064 in gdb_isattyfn (cs=0x7ffff83fe060, gf=0x7ffff86a3690) | ||
23 | at ../../semihosting/arm-compat-semi.c:636 | ||
24 | #4 0x00007ffff6c1b20f in do_common_semihosting (cs=0x7ffff83fe060) | ||
25 | at ../../semihosting/arm-compat-semi.c:967 | ||
26 | #5 0x00007ffff693a037 in handle_semihosting (cs=0x7ffff83fe060) | ||
27 | at ../../target/arm/helper.c:10316 | ||
28 | |||
29 | You can probably also get into this state via some odd | ||
30 | corner cases involving connecting a GDB and then telling it | ||
31 | to detach from all the vCPUs. | ||
32 | |||
33 | Abstract out the test into a new gdb_attached() function | ||
34 | which returns true only if there's actually a GDB connected | ||
35 | to the debug stub and attached to at least one vCPU. | ||
36 | |||
37 | Reported-by: Liviu Ionescu <ilg@livius.net> | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 38 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 39 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
7 | Message-id: 20220404154658.565020-9-peter.maydell@linaro.org | 40 | Reviewed-by: Luc Michel <luc@lmichel.fr> |
41 | Message-id: 20220526190053.521505-2-peter.maydell@linaro.org | ||
8 | --- | 42 | --- |
9 | include/hw/arm/exynos4210.h | 2 ++ | 43 | gdbstub.c | 14 +++++++++++--- |
10 | include/hw/intc/exynos4210_gic.h | 43 ++++++++++++++++++++++++++++++++ | 44 | 1 file changed, 11 insertions(+), 3 deletions(-) |
11 | hw/arm/exynos4210.c | 10 ++++---- | ||
12 | hw/intc/exynos4210_gic.c | 17 ++----------- | ||
13 | MAINTAINERS | 2 +- | ||
14 | 5 files changed, 53 insertions(+), 21 deletions(-) | ||
15 | create mode 100644 include/hw/intc/exynos4210_gic.h | ||
16 | 45 | ||
17 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | 46 | diff --git a/gdbstub.c b/gdbstub.c |
18 | index XXXXXXX..XXXXXXX 100644 | 47 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/include/hw/arm/exynos4210.h | 48 | --- a/gdbstub.c |
20 | +++ b/include/hw/arm/exynos4210.h | 49 | +++ b/gdbstub.c |
21 | @@ -XXX,XX +XXX,XX @@ | 50 | @@ -XXX,XX +XXX,XX @@ static int get_char(void) |
22 | #include "hw/or-irq.h" | 51 | } |
23 | #include "hw/sysbus.h" | 52 | #endif |
24 | #include "hw/cpu/a9mpcore.h" | 53 | |
25 | +#include "hw/intc/exynos4210_gic.h" | ||
26 | #include "target/arm/cpu-qom.h" | ||
27 | #include "qom/object.h" | ||
28 | |||
29 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { | ||
30 | qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; | ||
31 | qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; | ||
32 | A9MPPrivState a9mpcore; | ||
33 | + Exynos4210GicState ext_gic; | ||
34 | }; | ||
35 | |||
36 | #define TYPE_EXYNOS4210_SOC "exynos4210" | ||
37 | diff --git a/include/hw/intc/exynos4210_gic.h b/include/hw/intc/exynos4210_gic.h | ||
38 | new file mode 100644 | ||
39 | index XXXXXXX..XXXXXXX | ||
40 | --- /dev/null | ||
41 | +++ b/include/hw/intc/exynos4210_gic.h | ||
42 | @@ -XXX,XX +XXX,XX @@ | ||
43 | +/* | 54 | +/* |
44 | + * Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c | 55 | + * Return true if there is a GDB currently connected to the stub |
45 | + * | 56 | + * and attached to a CPU |
46 | + * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. | ||
47 | + * All rights reserved. | ||
48 | + * | ||
49 | + * Evgeny Voevodin <e.voevodin@samsung.com> | ||
50 | + * | ||
51 | + * This program is free software; you can redistribute it and/or modify it | ||
52 | + * under the terms of the GNU General Public License as published by the | ||
53 | + * Free Software Foundation; either version 2 of the License, or (at your | ||
54 | + * option) any later version. | ||
55 | + * | ||
56 | + * This program is distributed in the hope that it will be useful, | ||
57 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
58 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | ||
59 | + * See the GNU General Public License for more details. | ||
60 | + * | ||
61 | + * You should have received a copy of the GNU General Public License along | ||
62 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
63 | + */ | 57 | + */ |
64 | +#ifndef HW_INTC_EXYNOS4210_GIC_H | 58 | +static bool gdb_attached(void) |
65 | +#define HW_INTC_EXYNOS4210_GIC_H | 59 | +{ |
60 | + return gdbserver_state.init && gdbserver_state.c_cpu; | ||
61 | +} | ||
66 | + | 62 | + |
67 | +#include "hw/sysbus.h" | 63 | static enum { |
68 | + | 64 | GDB_SYS_UNKNOWN, |
69 | +#define TYPE_EXYNOS4210_GIC "exynos4210.gic" | 65 | GDB_SYS_ENABLED, |
70 | +OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC) | 66 | @@ -XXX,XX +XXX,XX @@ int use_gdb_syscalls(void) |
71 | + | 67 | /* -semihosting-config target=auto */ |
72 | +#define EXYNOS4210_GIC_NCPUS 2 | 68 | /* On the first call check if gdb is connected and remember. */ |
73 | + | 69 | if (gdb_syscall_mode == GDB_SYS_UNKNOWN) { |
74 | +struct Exynos4210GicState { | 70 | - gdb_syscall_mode = gdbserver_state.init ? |
75 | + SysBusDevice parent_obj; | 71 | - GDB_SYS_ENABLED : GDB_SYS_DISABLED; |
76 | + | 72 | + gdb_syscall_mode = gdb_attached() ? GDB_SYS_ENABLED : GDB_SYS_DISABLED; |
77 | + MemoryRegion cpu_container; | ||
78 | + MemoryRegion dist_container; | ||
79 | + MemoryRegion cpu_alias[EXYNOS4210_GIC_NCPUS]; | ||
80 | + MemoryRegion dist_alias[EXYNOS4210_GIC_NCPUS]; | ||
81 | + uint32_t num_cpu; | ||
82 | + DeviceState *gic; | ||
83 | +}; | ||
84 | + | ||
85 | +#endif | ||
86 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
87 | index XXXXXXX..XXXXXXX 100644 | ||
88 | --- a/hw/arm/exynos4210.c | ||
89 | +++ b/hw/arm/exynos4210.c | ||
90 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
91 | sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); | ||
92 | |||
93 | /* External GIC */ | ||
94 | - dev = qdev_new("exynos4210.gic"); | ||
95 | - qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); | ||
96 | - busdev = SYS_BUS_DEVICE(dev); | ||
97 | - sysbus_realize_and_unref(busdev, &error_fatal); | ||
98 | + qdev_prop_set_uint32(DEVICE(&s->ext_gic), "num-cpu", EXYNOS4210_NCPUS); | ||
99 | + busdev = SYS_BUS_DEVICE(&s->ext_gic); | ||
100 | + sysbus_realize(busdev, &error_fatal); | ||
101 | /* Map CPU interface */ | ||
102 | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); | ||
103 | /* Map Distributer interface */ | ||
104 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
105 | qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1)); | ||
106 | } | 73 | } |
107 | for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { | 74 | return gdb_syscall_mode == GDB_SYS_ENABLED; |
108 | - s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n); | 75 | } |
109 | + s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->ext_gic), n); | 76 | @@ -XXX,XX +XXX,XX @@ void gdb_do_syscallv(gdb_syscall_complete_cb cb, const char *fmt, va_list va) |
77 | target_ulong addr; | ||
78 | uint64_t i64; | ||
79 | |||
80 | - if (!gdbserver_state.init) { | ||
81 | + if (!gdb_attached()) { | ||
82 | return; | ||
110 | } | 83 | } |
111 | 84 | ||
112 | /* Internal Interrupt Combiner */ | ||
113 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj) | ||
114 | } | ||
115 | |||
116 | object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); | ||
117 | + object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC); | ||
118 | } | ||
119 | |||
120 | static void exynos4210_class_init(ObjectClass *klass, void *data) | ||
121 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | ||
122 | index XXXXXXX..XXXXXXX 100644 | ||
123 | --- a/hw/intc/exynos4210_gic.c | ||
124 | +++ b/hw/intc/exynos4210_gic.c | ||
125 | @@ -XXX,XX +XXX,XX @@ | ||
126 | #include "qemu/module.h" | ||
127 | #include "hw/irq.h" | ||
128 | #include "hw/qdev-properties.h" | ||
129 | +#include "hw/intc/exynos4210_gic.h" | ||
130 | #include "hw/arm/exynos4210.h" | ||
131 | #include "qom/object.h" | ||
132 | |||
133 | @@ -XXX,XX +XXX,XX @@ | ||
134 | #define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100 | ||
135 | #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000 | ||
136 | |||
137 | -#define TYPE_EXYNOS4210_GIC "exynos4210.gic" | ||
138 | -OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC) | ||
139 | - | ||
140 | -struct Exynos4210GicState { | ||
141 | - SysBusDevice parent_obj; | ||
142 | - | ||
143 | - MemoryRegion cpu_container; | ||
144 | - MemoryRegion dist_container; | ||
145 | - MemoryRegion cpu_alias[EXYNOS4210_NCPUS]; | ||
146 | - MemoryRegion dist_alias[EXYNOS4210_NCPUS]; | ||
147 | - uint32_t num_cpu; | ||
148 | - DeviceState *gic; | ||
149 | -}; | ||
150 | - | ||
151 | static void exynos4210_gic_set_irq(void *opaque, int irq, int level) | ||
152 | { | ||
153 | Exynos4210GicState *s = (Exynos4210GicState *)opaque; | ||
154 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_realize(DeviceState *dev, Error **errp) | ||
155 | * enough room for the cpu numbers. gcc 9.2.1 on 32-bit x86 | ||
156 | * doesn't figure this out, otherwise and gives spurious warnings. | ||
157 | */ | ||
158 | - assert(n <= EXYNOS4210_NCPUS); | ||
159 | + assert(n <= EXYNOS4210_GIC_NCPUS); | ||
160 | for (i = 0; i < n; i++) { | ||
161 | /* Map CPU interface per SMP Core */ | ||
162 | sprintf(cpu_alias_name, "%s%x", cpu_prefix, i); | ||
163 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
164 | index XXXXXXX..XXXXXXX 100644 | ||
165 | --- a/MAINTAINERS | ||
166 | +++ b/MAINTAINERS | ||
167 | @@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org> | ||
168 | L: qemu-arm@nongnu.org | ||
169 | S: Odd Fixes | ||
170 | F: hw/*/exynos* | ||
171 | -F: include/hw/arm/exynos4210.h | ||
172 | +F: include/hw/*/exynos* | ||
173 | |||
174 | Calxeda Highbank | ||
175 | M: Rob Herring <robh@kernel.org> | ||
176 | -- | 85 | -- |
177 | 2.25.1 | 86 | 2.25.1 |
87 | |||
88 | diff view generated by jsdifflib |
1 | The exynos4210 SoC mostly creates its child devices as if it were | 1 | Currently we mishandle the --semihosting-config option if the |
---|---|---|---|
2 | board code. This includes the a9mpcore object. Switch that to a | 2 | user specifies it on the command line more than once. For |
3 | new-style "embedded in the state struct" creation, because in the | 3 | example with: |
4 | next commit we're going to want to refer to the object again further | 4 | --semihosting-config target=gdb --semihosting-config arg=foo,arg=bar |
5 | down in the exynos4210_realize() function. | 5 | |
6 | the function qemu_semihosting_config_options() is called twice, once | ||
7 | for each argument. But that function expects to be called only once, | ||
8 | and it always unconditionally sets the semihosting.enabled, | ||
9 | semihost_chardev and semihosting.target variables. This means that | ||
10 | if any of those options were set anywhere except the last | ||
11 | --semihosting-config option on the command line, those settings are | ||
12 | ignored. In the example above, 'target=gdb' in the first option is | ||
13 | overridden by an implied default 'target=auto' in the second. | ||
14 | |||
15 | The QemuOptsList machinery has a flag for handling this kind of | ||
16 | "option group is setting global state": by setting | ||
17 | .merge_lists = true; | ||
18 | we make the machinery merge all the --semihosting-config arguments | ||
19 | the user passes into a single set of options and call our | ||
20 | qemu_semihosting_config_options() just once. | ||
6 | 21 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 23 | Reviewed-by: Luc Michel <luc@lmichel.fr> |
9 | Message-id: 20220404154658.565020-4-peter.maydell@linaro.org | 24 | Message-id: 20220526190053.521505-3-peter.maydell@linaro.org |
10 | --- | 25 | --- |
11 | include/hw/arm/exynos4210.h | 2 ++ | 26 | semihosting/config.c | 1 + |
12 | hw/arm/exynos4210.c | 11 ++++++----- | 27 | 1 file changed, 1 insertion(+) |
13 | 2 files changed, 8 insertions(+), 5 deletions(-) | ||
14 | 28 | ||
15 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | 29 | diff --git a/semihosting/config.c b/semihosting/config.c |
16 | index XXXXXXX..XXXXXXX 100644 | 30 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/include/hw/arm/exynos4210.h | 31 | --- a/semihosting/config.c |
18 | +++ b/include/hw/arm/exynos4210.h | 32 | +++ b/semihosting/config.c |
19 | @@ -XXX,XX +XXX,XX @@ | 33 | @@ -XXX,XX +XXX,XX @@ |
20 | 34 | ||
21 | #include "hw/or-irq.h" | 35 | QemuOptsList qemu_semihosting_config_opts = { |
22 | #include "hw/sysbus.h" | 36 | .name = "semihosting-config", |
23 | +#include "hw/cpu/a9mpcore.h" | 37 | + .merge_lists = true, |
24 | #include "target/arm/cpu-qom.h" | 38 | .implied_opt_name = "enable", |
25 | #include "qom/object.h" | 39 | .head = QTAILQ_HEAD_INITIALIZER(qemu_semihosting_config_opts.head), |
26 | 40 | .desc = { | |
27 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { | ||
28 | I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; | ||
29 | qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; | ||
30 | qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; | ||
31 | + A9MPPrivState a9mpcore; | ||
32 | }; | ||
33 | |||
34 | #define TYPE_EXYNOS4210_SOC "exynos4210" | ||
35 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/hw/arm/exynos4210.c | ||
38 | +++ b/hw/arm/exynos4210.c | ||
39 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
40 | } | ||
41 | |||
42 | /* Private memory region and Internal GIC */ | ||
43 | - dev = qdev_new(TYPE_A9MPCORE_PRIV); | ||
44 | - qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); | ||
45 | - busdev = SYS_BUS_DEVICE(dev); | ||
46 | - sysbus_realize_and_unref(busdev, &error_fatal); | ||
47 | + qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS); | ||
48 | + busdev = SYS_BUS_DEVICE(&s->a9mpcore); | ||
49 | + sysbus_realize(busdev, &error_fatal); | ||
50 | sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); | ||
51 | for (n = 0; n < EXYNOS4210_NCPUS; n++) { | ||
52 | sysbus_connect_irq(busdev, n, | ||
53 | qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0)); | ||
54 | } | ||
55 | for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { | ||
56 | - s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n); | ||
57 | + s->irqs.int_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->a9mpcore), n); | ||
58 | } | ||
59 | |||
60 | /* Cache controller */ | ||
61 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj) | ||
62 | g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i); | ||
63 | object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ); | ||
64 | } | ||
65 | + | ||
66 | + object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); | ||
67 | } | ||
68 | |||
69 | static void exynos4210_class_init(ObjectClass *klass, void *data) | ||
70 | -- | 41 | -- |
71 | 2.25.1 | 42 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The only time we use the int_gic_irq[] array in the Exynos4210Irq | ||
2 | struct is in the exynos4210_realize() function: we initialize it with | ||
3 | the GPIO inputs of the a9mpcore device, and then a bit later on we | ||
4 | connect those to the outputs of the internal combiner. Now that the | ||
5 | a9mpcore object is easily accessible as s->a9mpcore we can make the | ||
6 | connection directly from one device to the other without going via | ||
7 | this array. | ||
8 | 1 | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20220404154658.565020-5-peter.maydell@linaro.org | ||
12 | --- | ||
13 | include/hw/arm/exynos4210.h | 1 - | ||
14 | hw/arm/exynos4210.c | 6 ++---- | ||
15 | 2 files changed, 2 insertions(+), 5 deletions(-) | ||
16 | |||
17 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/include/hw/arm/exynos4210.h | ||
20 | +++ b/include/hw/arm/exynos4210.h | ||
21 | @@ -XXX,XX +XXX,XX @@ | ||
22 | typedef struct Exynos4210Irq { | ||
23 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
24 | qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; | ||
25 | - qemu_irq int_gic_irq[EXYNOS4210_INT_GIC_NIRQ]; | ||
26 | qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ]; | ||
27 | qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
28 | } Exynos4210Irq; | ||
29 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/hw/arm/exynos4210.c | ||
32 | +++ b/hw/arm/exynos4210.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
34 | sysbus_connect_irq(busdev, n, | ||
35 | qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0)); | ||
36 | } | ||
37 | - for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { | ||
38 | - s->irqs.int_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->a9mpcore), n); | ||
39 | - } | ||
40 | |||
41 | /* Cache controller */ | ||
42 | sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); | ||
43 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
44 | busdev = SYS_BUS_DEVICE(dev); | ||
45 | sysbus_realize_and_unref(busdev, &error_fatal); | ||
46 | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { | ||
47 | - sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]); | ||
48 | + sysbus_connect_irq(busdev, n, | ||
49 | + qdev_get_gpio_in(DEVICE(&s->a9mpcore), n)); | ||
50 | } | ||
51 | exynos4210_combiner_get_gpioin(&s->irqs, dev, 0); | ||
52 | sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); | ||
53 | -- | ||
54 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Delete a couple of #defines which are never used. | ||
2 | 1 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20220404154658.565020-12-peter.maydell@linaro.org | ||
6 | --- | ||
7 | include/hw/arm/exynos4210.h | 4 ---- | ||
8 | 1 file changed, 4 deletions(-) | ||
9 | |||
10 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/include/hw/arm/exynos4210.h | ||
13 | +++ b/include/hw/arm/exynos4210.h | ||
14 | @@ -XXX,XX +XXX,XX @@ | ||
15 | #define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \ | ||
16 | (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8) | ||
17 | |||
18 | -/* IRQs number for external and internal GIC */ | ||
19 | -#define EXYNOS4210_EXT_GIC_NIRQ (160-32) | ||
20 | -#define EXYNOS4210_INT_GIC_NIRQ 64 | ||
21 | - | ||
22 | #define EXYNOS4210_I2C_NUMBER 9 | ||
23 | |||
24 | #define EXYNOS4210_NUM_DMA 3 | ||
25 | -- | ||
26 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The combiner_grp_to_gic_id[] array includes the EXT_GIC_ID_MCT_G0 | ||
2 | and EXT_GIC_ID_MCT_G1 multiple times. This means that we will | ||
3 | connect multiple IRQs up to the same external GIC input, which | ||
4 | is not permitted. We do the same thing in the code in | ||
5 | exynos4210_init_board_irqs() because the conditionals selecting | ||
6 | an irq_id in the first loop match multiple interrupt IDs. | ||
7 | 1 | ||
8 | Overall we do this for interrupt IDs | ||
9 | (1, 4), (12, 4), (35, 4), (51, 4), (53, 4) for EXT_GIC_ID_MCT_G0 | ||
10 | and | ||
11 | (1, 5), (12, 5), (35, 5), (51, 5), (53, 5) for EXT_GIC_ID_MCT_G1 | ||
12 | |||
13 | These correspond to the cases for the multi-core timer that we are | ||
14 | wiring up to multiple inputs on the combiner in | ||
15 | exynos4210_combiner_get_gpioin(). That code already deals with all | ||
16 | these interrupt IDs being the same input source, so we don't need to | ||
17 | connect the external GIC interrupt for any of them except the first | ||
18 | (1, 4) and (1, 5). Remove the array entries and conditionals which | ||
19 | were incorrectly causing us to wire up extra lines. | ||
20 | |||
21 | This bug didn't cause any visible effects, because we only connect | ||
22 | up a device to the "primary" ID values (1, 4) and (1, 5), so the | ||
23 | extra lines would never be set to a level. | ||
24 | |||
25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
26 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
27 | Message-id: 20220404154658.565020-16-peter.maydell@linaro.org | ||
28 | --- | ||
29 | include/hw/arm/exynos4210.h | 2 +- | ||
30 | hw/arm/exynos4210.c | 12 +++++------- | ||
31 | 2 files changed, 6 insertions(+), 8 deletions(-) | ||
32 | |||
33 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/include/hw/arm/exynos4210.h | ||
36 | +++ b/include/hw/arm/exynos4210.h | ||
37 | @@ -XXX,XX +XXX,XX @@ | ||
38 | * one for every non-zero entry in combiner_grp_to_gic_id[]. | ||
39 | * We'll assert in exynos4210_init_board_irqs() if this is wrong. | ||
40 | */ | ||
41 | -#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 60) | ||
42 | +#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 54) | ||
43 | |||
44 | typedef struct Exynos4210Irq { | ||
45 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
46 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/hw/arm/exynos4210.c | ||
49 | +++ b/hw/arm/exynos4210.c | ||
50 | @@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
51 | /* int combiner group 34 */ | ||
52 | { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, | ||
53 | /* int combiner group 35 */ | ||
54 | - { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
55 | + { 0, 0, 0, EXT_GIC_ID_MCT_L1 }, | ||
56 | /* int combiner group 36 */ | ||
57 | { EXT_GIC_ID_MIXER }, | ||
58 | /* int combiner group 37 */ | ||
59 | @@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
60 | /* groups 38-50 */ | ||
61 | { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, | ||
62 | /* int combiner group 51 */ | ||
63 | - { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
64 | + { EXT_GIC_ID_MCT_L0 }, | ||
65 | /* group 52 */ | ||
66 | { }, | ||
67 | /* int combiner group 53 */ | ||
68 | - { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
69 | + { EXT_GIC_ID_WDT }, | ||
70 | /* groups 54-63 */ | ||
71 | { }, { }, { }, { }, { }, { }, { }, { }, { }, { } | ||
72 | }; | ||
73 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
74 | |||
75 | for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { | ||
76 | irq_id = 0; | ||
77 | - if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) || | ||
78 | - n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) { | ||
79 | + if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4)) { | ||
80 | /* MCT_G0 is passed to External GIC */ | ||
81 | irq_id = EXT_GIC_ID_MCT_G0; | ||
82 | } | ||
83 | - if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) || | ||
84 | - n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) { | ||
85 | + if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5)) { | ||
86 | /* MCT_G1 is passed to External and GIC */ | ||
87 | irq_id = EXT_GIC_ID_MCT_G1; | ||
88 | } | ||
89 | -- | ||
90 | 2.25.1 | diff view generated by jsdifflib |