1 | First arm pullreq for 7.1. The bulk of this is the qemu_split_irq | 1 | This is mostly RTH's tcg_constant refactoring work, plus a few |
---|---|---|---|
2 | removal. | 2 | other things. |
3 | |||
4 | I have enough stuff in my to-review queue that I expect to do another | ||
5 | pullreq early next week, but 31 patches is enough to not hang on to. | ||
6 | 3 | ||
7 | thanks | 4 | thanks |
8 | -- PMM | 5 | -- PMM |
9 | 6 | ||
10 | The following changes since commit 9c125d17e9402c232c46610802e5931b3639d77b: | 7 | The following changes since commit cf6f26d6f9b2015ee12b4604b79359e76784163a: |
11 | 8 | ||
12 | Merge tag 'pull-tcg-20220420' of https://gitlab.com/rth7680/qemu into staging (2022-04-20 16:43:11 -0700) | 9 | Merge tag 'kraxel-20220427-pull-request' of git://git.kraxel.org/qemu into staging (2022-04-27 10:49:28 -0700) |
13 | 10 | ||
14 | are available in the Git repository at: | 11 | are available in the Git repository at: |
15 | 12 | ||
16 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220421 | 13 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220428 |
17 | 14 | ||
18 | for you to fetch changes up to 5b415dd61bdbf61fb4be0e9f1a7172b8bce682c6: | 15 | for you to fetch changes up to f8e7163d9e6740b5cef02bf73a17a59d0bef8bdb: |
19 | 16 | ||
20 | hw/arm: Use bit fields for NPCM7XX PWRON STRAPs (2022-04-21 11:37:05 +0100) | 17 | hw/arm/smmuv3: Advertise support for SMMUv3.2-BBML2 (2022-04-28 13:59:23 +0100) |
21 | 18 | ||
22 | ---------------------------------------------------------------- | 19 | ---------------------------------------------------------------- |
23 | target-arm queue: | 20 | target-arm queue: |
24 | * hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF | 21 | * refactor to use tcg_constant where appropriate |
25 | * versal: Add the Cortex-R5s in the Real-Time Processing Unit (RPU) subsystem | 22 | * Advertise support for FEAT_TTL and FEAT_BBM level 2 |
26 | * versal: model enough of the Clock/Reset Low-power domain (CRL) to allow control of the Cortex-R5s | 23 | * smmuv3: Cache event fault record |
27 | * xlnx-zynqmp: Connect 4 TTC timers | 24 | * smmuv3: Add space in guest error message |
28 | * exynos4210: Refactor GIC/combiner code to stop using qemu_split_irq | 25 | * smmuv3: Advertise support for SMMUv3.2-BBML2 |
29 | * realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ' | ||
30 | * stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ' | ||
31 | * hw/core/irq: remove unused 'qemu_irq_split' function | ||
32 | * npcm7xx: use symbolic constants for PWRON STRAP bit fields | ||
33 | * virt: document impact of gic-version on max CPUs | ||
34 | 26 | ||
35 | ---------------------------------------------------------------- | 27 | ---------------------------------------------------------------- |
36 | Edgar E. Iglesias (6): | 28 | Damien Hedde (1): |
37 | timer: cadence_ttc: Break out header file to allow embedding | 29 | target/arm: Disable cryptographic instructions when neon is disabled |
38 | hw/arm/xlnx-zynqmp: Connect 4 TTC timers | ||
39 | hw/arm: versal: Create an APU CPU Cluster | ||
40 | hw/arm: versal: Add the Cortex-R5Fs | ||
41 | hw/misc: Add a model of the Xilinx Versal CRL | ||
42 | hw/arm: versal: Connect the CRL | ||
43 | 30 | ||
44 | Hao Wu (2): | 31 | Jean-Philippe Brucker (2): |
45 | hw/misc: Add PWRON STRAP bit fields in GCR module | 32 | hw/arm/smmuv3: Cache event fault record |
46 | hw/arm: Use bit fields for NPCM7XX PWRON STRAPs | 33 | hw/arm/smmuv3: Add space in guest error message |
47 | 34 | ||
48 | Heinrich Schuchardt (1): | 35 | Peter Maydell (3): |
49 | hw/arm/virt: impact of gic-version on max CPUs | 36 | target/arm: Advertise support for FEAT_TTL |
37 | target/arm: Advertise support for FEAT_BBM level 2 | ||
38 | hw/arm/smmuv3: Advertise support for SMMUv3.2-BBML2 | ||
50 | 39 | ||
51 | Peter Maydell (19): | 40 | Richard Henderson (48): |
52 | hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF | 41 | target/arm: Use tcg_constant in gen_probe_access |
53 | hw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom OR-gate device | 42 | target/arm: Use tcg_constant in gen_mte_check* |
54 | hw/intc/exynos4210_gic: Remove unused TYPE_EXYNOS4210_IRQ_GATE | 43 | target/arm: Use tcg_constant in gen_exception* |
55 | hw/arm/exynos4210: Put a9mpcore device into state struct | 44 | target/arm: Use tcg_constant in gen_adc_CC |
56 | hw/arm/exynos4210: Drop int_gic_irq[] from Exynos4210Irq struct | 45 | target/arm: Use tcg_constant in handle_msr_i |
57 | hw/arm/exynos4210: Coalesce board_irqs and irq_table | 46 | target/arm: Use tcg_constant in handle_sys |
58 | hw/arm/exynos4210: Fix code style nit in combiner_grp_to_gic_id[] | 47 | target/arm: Use tcg_constant in disas_exc |
59 | hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.c | 48 | target/arm: Use tcg_constant in gen_compare_and_swap_pair |
60 | hw/arm/exynos4210: Put external GIC into state struct | 49 | target/arm: Use tcg_constant in disas_ld_lit |
61 | hw/arm/exynos4210: Drop ext_gic_irq[] from Exynos4210Irq struct | 50 | target/arm: Use tcg_constant in disas_ldst_* |
62 | hw/arm/exynos4210: Move exynos4210_combiner_get_gpioin() into exynos4210.c | 51 | target/arm: Use tcg_constant in disas_add_sum_imm* |
63 | hw/arm/exynos4210: Delete unused macro definitions | 52 | target/arm: Use tcg_constant in disas_movw_imm |
64 | hw/arm/exynos4210: Use TYPE_SPLIT_IRQ in exynos4210_init_board_irqs() | 53 | target/arm: Use tcg_constant in shift_reg_imm |
65 | hw/arm/exynos4210: Fill in irq_table[] for internal-combiner-only IRQ lines | 54 | target/arm: Use tcg_constant in disas_cond_select |
66 | hw/arm/exynos4210: Connect MCT_G0 and MCT_G1 to both combiners | 55 | target/arm: Use tcg_constant in handle_{rev16,crc32} |
67 | hw/arm/exynos4210: Don't connect multiple lines to external GIC inputs | 56 | target/arm: Use tcg_constant in disas_data_proc_2src |
68 | hw/arm/exynos4210: Fold combiner splits into exynos4210_init_board_irqs() | 57 | target/arm: Use tcg_constant in disas_fp* |
69 | hw/arm/exynos4210: Put combiners into state struct | 58 | target/arm: Use tcg_constant in simd shift expanders |
70 | hw/arm/exynos4210: Drop Exynos4210Irq struct | 59 | target/arm: Use tcg_constant in simd fp/int conversion |
60 | target/arm: Use tcg_constant in 2misc expanders | ||
61 | target/arm: Use tcg_constant in balance of translate-a64.c | ||
62 | target/arm: Use tcg_constant for aa32 exceptions | ||
63 | target/arm: Use tcg_constant for disas_iwmmxt_insn | ||
64 | target/arm: Use tcg_constant for gen_{msr,mrs} | ||
65 | target/arm: Use tcg_constant for vector shift expanders | ||
66 | target/arm: Use tcg_constant for do_coproc_insn | ||
67 | target/arm: Use tcg_constant for gen_srs | ||
68 | target/arm: Use tcg_constant for op_s_{rri,rxi}_rot | ||
69 | target/arm: Use tcg_constant for MOVW, UMAAL, CRC32 | ||
70 | target/arm: Use tcg_constant for v7m MRS, MSR | ||
71 | target/arm: Use tcg_constant for TT, SAT, SMMLA | ||
72 | target/arm: Use tcg_constant in LDM, STM | ||
73 | target/arm: Use tcg_constant in CLRM, DLS, WLS, LE | ||
74 | target/arm: Use tcg_constant in trans_CPS_v7m | ||
75 | target/arm: Use tcg_constant in trans_CSEL | ||
76 | target/arm: Use tcg_constant for trans_INDEX_* | ||
77 | target/arm: Use tcg_constant in SINCDEC, INCDEC | ||
78 | target/arm: Use tcg_constant in FCPY, CPY | ||
79 | target/arm: Use tcg_constant in {incr, wrap}_last_active | ||
80 | target/arm: Use tcg_constant in do_clast_scalar | ||
81 | target/arm: Use tcg_constant in WHILE | ||
82 | target/arm: Use tcg_constant in LD1, ST1 | ||
83 | target/arm: Use tcg_constant in SUBR | ||
84 | target/arm: Use tcg_constant in do_zzi_{sat, ool}, do_fp_imm | ||
85 | target/arm: Use tcg_constant for predicate descriptors | ||
86 | target/arm: Use tcg_constant for do_brk{2,3} | ||
87 | target/arm: Use tcg_constant for vector descriptor | ||
88 | target/arm: Use field names for accessing DBGWCRn | ||
71 | 89 | ||
72 | Zongyuan Li (3): | 90 | docs/system/arm/emulation.rst | 2 + |
73 | hw/arm/realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ' | 91 | hw/arm/smmuv3-internal.h | 2 +- |
74 | hw/arm/stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ' | 92 | include/hw/arm/smmu-common.h | 1 + |
75 | hw/core/irq: remove unused 'qemu_irq_split' function | 93 | target/arm/internals.h | 12 ++ |
76 | 94 | hw/arm/smmuv3.c | 17 +-- | |
77 | docs/system/arm/virt.rst | 4 +- | 95 | target/arm/cpu.c | 9 ++ |
78 | include/hw/arm/exynos4210.h | 50 ++-- | 96 | target/arm/cpu64.c | 2 + |
79 | include/hw/arm/xlnx-versal.h | 16 ++ | 97 | target/arm/debug_helper.c | 10 +- |
80 | include/hw/arm/xlnx-zynqmp.h | 4 + | 98 | target/arm/helper.c | 8 +- |
81 | include/hw/intc/exynos4210_combiner.h | 57 +++++ | 99 | target/arm/kvm64.c | 14 +- |
82 | include/hw/intc/exynos4210_gic.h | 43 ++++ | 100 | target/arm/translate-a64.c | 301 +++++++++++++----------------------------- |
83 | include/hw/irq.h | 5 - | 101 | target/arm/translate-sve.c | 202 ++++++++++------------------ |
84 | include/hw/misc/npcm7xx_gcr.h | 30 +++ | 102 | target/arm/translate.c | 244 ++++++++++++---------------------- |
85 | include/hw/misc/xlnx-versal-crl.h | 235 +++++++++++++++++++ | 103 | 13 files changed, 293 insertions(+), 531 deletions(-) |
86 | include/hw/timer/cadence_ttc.h | 54 +++++ | ||
87 | hw/arm/exynos4210.c | 430 ++++++++++++++++++++++++++++++---- | ||
88 | hw/arm/npcm7xx_boards.c | 24 +- | ||
89 | hw/arm/realview.c | 33 ++- | ||
90 | hw/arm/stellaris.c | 15 +- | ||
91 | hw/arm/virt.c | 7 + | ||
92 | hw/arm/xlnx-versal-virt.c | 6 +- | ||
93 | hw/arm/xlnx-versal.c | 99 +++++++- | ||
94 | hw/arm/xlnx-zynqmp.c | 22 ++ | ||
95 | hw/core/irq.c | 15 -- | ||
96 | hw/intc/exynos4210_combiner.c | 108 +-------- | ||
97 | hw/intc/exynos4210_gic.c | 344 +-------------------------- | ||
98 | hw/misc/xlnx-versal-crl.c | 421 +++++++++++++++++++++++++++++++++ | ||
99 | hw/timer/cadence_ttc.c | 32 +-- | ||
100 | MAINTAINERS | 2 +- | ||
101 | hw/misc/meson.build | 1 + | ||
102 | 25 files changed, 1457 insertions(+), 600 deletions(-) | ||
103 | create mode 100644 include/hw/intc/exynos4210_combiner.h | ||
104 | create mode 100644 include/hw/intc/exynos4210_gic.h | ||
105 | create mode 100644 include/hw/misc/xlnx-versal-crl.h | ||
106 | create mode 100644 include/hw/timer/cadence_ttc.h | ||
107 | create mode 100644 hw/misc/xlnx-versal-crl.c | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-2-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate-a64.c | 12 ++++-------- | ||
9 | 1 file changed, 4 insertions(+), 8 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate-a64.c | ||
14 | +++ b/target/arm/translate-a64.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void gen_address_with_allocation_tag0(TCGv_i64 dst, TCGv_i64 src) | ||
16 | static void gen_probe_access(DisasContext *s, TCGv_i64 ptr, | ||
17 | MMUAccessType acc, int log2_size) | ||
18 | { | ||
19 | - TCGv_i32 t_acc = tcg_const_i32(acc); | ||
20 | - TCGv_i32 t_idx = tcg_const_i32(get_mem_index(s)); | ||
21 | - TCGv_i32 t_size = tcg_const_i32(1 << log2_size); | ||
22 | - | ||
23 | - gen_helper_probe_access(cpu_env, ptr, t_acc, t_idx, t_size); | ||
24 | - tcg_temp_free_i32(t_acc); | ||
25 | - tcg_temp_free_i32(t_idx); | ||
26 | - tcg_temp_free_i32(t_size); | ||
27 | + gen_helper_probe_access(cpu_env, ptr, | ||
28 | + tcg_constant_i32(acc), | ||
29 | + tcg_constant_i32(get_mem_index(s)), | ||
30 | + tcg_constant_i32(1 << log2_size)); | ||
31 | } | ||
32 | |||
33 | /* | ||
34 | -- | ||
35 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-3-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate-a64.c | 10 ++-------- | ||
9 | 1 file changed, 2 insertions(+), 8 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate-a64.c | ||
14 | +++ b/target/arm/translate-a64.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr, | ||
16 | int core_idx) | ||
17 | { | ||
18 | if (tag_checked && s->mte_active[is_unpriv]) { | ||
19 | - TCGv_i32 tcg_desc; | ||
20 | TCGv_i64 ret; | ||
21 | int desc = 0; | ||
22 | |||
23 | @@ -XXX,XX +XXX,XX @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr, | ||
24 | desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | ||
25 | desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); | ||
26 | desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << log2_size) - 1); | ||
27 | - tcg_desc = tcg_const_i32(desc); | ||
28 | |||
29 | ret = new_tmp_a64(s); | ||
30 | - gen_helper_mte_check(ret, cpu_env, tcg_desc, addr); | ||
31 | - tcg_temp_free_i32(tcg_desc); | ||
32 | + gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr); | ||
33 | |||
34 | return ret; | ||
35 | } | ||
36 | @@ -XXX,XX +XXX,XX @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, | ||
37 | bool tag_checked, int size) | ||
38 | { | ||
39 | if (tag_checked && s->mte_active[0]) { | ||
40 | - TCGv_i32 tcg_desc; | ||
41 | TCGv_i64 ret; | ||
42 | int desc = 0; | ||
43 | |||
44 | @@ -XXX,XX +XXX,XX @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, | ||
45 | desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | ||
46 | desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); | ||
47 | desc = FIELD_DP32(desc, MTEDESC, SIZEM1, size - 1); | ||
48 | - tcg_desc = tcg_const_i32(desc); | ||
49 | |||
50 | ret = new_tmp_a64(s); | ||
51 | - gen_helper_mte_check(ret, cpu_env, tcg_desc, addr); | ||
52 | - tcg_temp_free_i32(tcg_desc); | ||
53 | + gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr); | ||
54 | |||
55 | return ret; | ||
56 | } | ||
57 | -- | ||
58 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-4-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate-a64.c | 11 ++--------- | ||
9 | 1 file changed, 2 insertions(+), 9 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate-a64.c | ||
14 | +++ b/target/arm/translate-a64.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void gen_rebuild_hflags(DisasContext *s) | ||
16 | |||
17 | static void gen_exception_internal(int excp) | ||
18 | { | ||
19 | - TCGv_i32 tcg_excp = tcg_const_i32(excp); | ||
20 | - | ||
21 | assert(excp_is_internal(excp)); | ||
22 | - gen_helper_exception_internal(cpu_env, tcg_excp); | ||
23 | - tcg_temp_free_i32(tcg_excp); | ||
24 | + gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp)); | ||
25 | } | ||
26 | |||
27 | static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp) | ||
28 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp) | ||
29 | |||
30 | static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome) | ||
31 | { | ||
32 | - TCGv_i32 tcg_syn; | ||
33 | - | ||
34 | gen_a64_set_pc_im(s->pc_curr); | ||
35 | - tcg_syn = tcg_const_i32(syndrome); | ||
36 | - gen_helper_exception_bkpt_insn(cpu_env, tcg_syn); | ||
37 | - tcg_temp_free_i32(tcg_syn); | ||
38 | + gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syndrome)); | ||
39 | s->base.is_jmp = DISAS_NORETURN; | ||
40 | } | ||
41 | |||
42 | -- | ||
43 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Note that tmp was doing double-duty as zero | ||
4 | and then later as a temporary in its own right. | ||
5 | Split the use of 0 to a new variable 'zero'. | ||
6 | |||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Message-id: 20220426163043.100432-5-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/translate-a64.c | 26 +++++++++++++------------- | ||
13 | 1 file changed, 13 insertions(+), 13 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/translate-a64.c | ||
18 | +++ b/target/arm/translate-a64.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | ||
20 | static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | ||
21 | { | ||
22 | if (sf) { | ||
23 | - TCGv_i64 result, cf_64, vf_64, tmp; | ||
24 | - result = tcg_temp_new_i64(); | ||
25 | - cf_64 = tcg_temp_new_i64(); | ||
26 | - vf_64 = tcg_temp_new_i64(); | ||
27 | - tmp = tcg_const_i64(0); | ||
28 | + TCGv_i64 result = tcg_temp_new_i64(); | ||
29 | + TCGv_i64 cf_64 = tcg_temp_new_i64(); | ||
30 | + TCGv_i64 vf_64 = tcg_temp_new_i64(); | ||
31 | + TCGv_i64 tmp = tcg_temp_new_i64(); | ||
32 | + TCGv_i64 zero = tcg_constant_i64(0); | ||
33 | |||
34 | tcg_gen_extu_i32_i64(cf_64, cpu_CF); | ||
35 | - tcg_gen_add2_i64(result, cf_64, t0, tmp, cf_64, tmp); | ||
36 | - tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, tmp); | ||
37 | + tcg_gen_add2_i64(result, cf_64, t0, zero, cf_64, zero); | ||
38 | + tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, zero); | ||
39 | tcg_gen_extrl_i64_i32(cpu_CF, cf_64); | ||
40 | gen_set_NZ64(result); | ||
41 | |||
42 | @@ -XXX,XX +XXX,XX @@ static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | ||
43 | tcg_temp_free_i64(cf_64); | ||
44 | tcg_temp_free_i64(result); | ||
45 | } else { | ||
46 | - TCGv_i32 t0_32, t1_32, tmp; | ||
47 | - t0_32 = tcg_temp_new_i32(); | ||
48 | - t1_32 = tcg_temp_new_i32(); | ||
49 | - tmp = tcg_const_i32(0); | ||
50 | + TCGv_i32 t0_32 = tcg_temp_new_i32(); | ||
51 | + TCGv_i32 t1_32 = tcg_temp_new_i32(); | ||
52 | + TCGv_i32 tmp = tcg_temp_new_i32(); | ||
53 | + TCGv_i32 zero = tcg_constant_i32(0); | ||
54 | |||
55 | tcg_gen_extrl_i64_i32(t0_32, t0); | ||
56 | tcg_gen_extrl_i64_i32(t1_32, t1); | ||
57 | - tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, cpu_CF, tmp); | ||
58 | - tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, tmp); | ||
59 | + tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, zero, cpu_CF, zero); | ||
60 | + tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, zero); | ||
61 | |||
62 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | ||
63 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | ||
64 | -- | ||
65 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-6-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate-a64.c | 13 +++---------- | ||
9 | 1 file changed, 3 insertions(+), 10 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate-a64.c | ||
14 | +++ b/target/arm/translate-a64.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void gen_axflag(void) | ||
16 | static void handle_msr_i(DisasContext *s, uint32_t insn, | ||
17 | unsigned int op1, unsigned int op2, unsigned int crm) | ||
18 | { | ||
19 | - TCGv_i32 t1; | ||
20 | int op = op1 << 3 | op2; | ||
21 | |||
22 | /* End the TB by default, chaining is ok. */ | ||
23 | @@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn, | ||
24 | if (s->current_el == 0) { | ||
25 | goto do_unallocated; | ||
26 | } | ||
27 | - t1 = tcg_const_i32(crm & PSTATE_SP); | ||
28 | - gen_helper_msr_i_spsel(cpu_env, t1); | ||
29 | - tcg_temp_free_i32(t1); | ||
30 | + gen_helper_msr_i_spsel(cpu_env, tcg_constant_i32(crm & PSTATE_SP)); | ||
31 | break; | ||
32 | |||
33 | case 0x19: /* SSBS */ | ||
34 | @@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn, | ||
35 | break; | ||
36 | |||
37 | case 0x1e: /* DAIFSet */ | ||
38 | - t1 = tcg_const_i32(crm); | ||
39 | - gen_helper_msr_i_daifset(cpu_env, t1); | ||
40 | - tcg_temp_free_i32(t1); | ||
41 | + gen_helper_msr_i_daifset(cpu_env, tcg_constant_i32(crm)); | ||
42 | break; | ||
43 | |||
44 | case 0x1f: /* DAIFClear */ | ||
45 | - t1 = tcg_const_i32(crm); | ||
46 | - gen_helper_msr_i_daifclear(cpu_env, t1); | ||
47 | - tcg_temp_free_i32(t1); | ||
48 | + gen_helper_msr_i_daifclear(cpu_env, tcg_constant_i32(crm)); | ||
49 | /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */ | ||
50 | s->base.is_jmp = DISAS_UPDATE_EXIT; | ||
51 | break; | ||
52 | -- | ||
53 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-7-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate-a64.c | 31 +++++++++---------------------- | ||
9 | 1 file changed, 9 insertions(+), 22 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate-a64.c | ||
14 | +++ b/target/arm/translate-a64.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, | ||
16 | /* Emit code to perform further access permissions checks at | ||
17 | * runtime; this may result in an exception. | ||
18 | */ | ||
19 | - TCGv_ptr tmpptr; | ||
20 | - TCGv_i32 tcg_syn, tcg_isread; | ||
21 | uint32_t syndrome; | ||
22 | |||
23 | - gen_a64_set_pc_im(s->pc_curr); | ||
24 | - tmpptr = tcg_const_ptr(ri); | ||
25 | syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread); | ||
26 | - tcg_syn = tcg_const_i32(syndrome); | ||
27 | - tcg_isread = tcg_const_i32(isread); | ||
28 | - gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn, tcg_isread); | ||
29 | - tcg_temp_free_ptr(tmpptr); | ||
30 | - tcg_temp_free_i32(tcg_syn); | ||
31 | - tcg_temp_free_i32(tcg_isread); | ||
32 | + gen_a64_set_pc_im(s->pc_curr); | ||
33 | + gen_helper_access_check_cp_reg(cpu_env, | ||
34 | + tcg_constant_ptr(ri), | ||
35 | + tcg_constant_i32(syndrome), | ||
36 | + tcg_constant_i32(isread)); | ||
37 | } else if (ri->type & ARM_CP_RAISES_EXC) { | ||
38 | /* | ||
39 | * The readfn or writefn might raise an exception; | ||
40 | @@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, | ||
41 | case ARM_CP_DC_ZVA: | ||
42 | /* Writes clear the aligned block of memory which rt points into. */ | ||
43 | if (s->mte_active[0]) { | ||
44 | - TCGv_i32 t_desc; | ||
45 | int desc = 0; | ||
46 | |||
47 | desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); | ||
48 | desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | ||
49 | desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | ||
50 | - t_desc = tcg_const_i32(desc); | ||
51 | |||
52 | tcg_rt = new_tmp_a64(s); | ||
53 | - gen_helper_mte_check_zva(tcg_rt, cpu_env, t_desc, cpu_reg(s, rt)); | ||
54 | - tcg_temp_free_i32(t_desc); | ||
55 | + gen_helper_mte_check_zva(tcg_rt, cpu_env, | ||
56 | + tcg_constant_i32(desc), cpu_reg(s, rt)); | ||
57 | } else { | ||
58 | tcg_rt = clean_data_tbi(s, cpu_reg(s, rt)); | ||
59 | } | ||
60 | @@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, | ||
61 | if (ri->type & ARM_CP_CONST) { | ||
62 | tcg_gen_movi_i64(tcg_rt, ri->resetvalue); | ||
63 | } else if (ri->readfn) { | ||
64 | - TCGv_ptr tmpptr; | ||
65 | - tmpptr = tcg_const_ptr(ri); | ||
66 | - gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr); | ||
67 | - tcg_temp_free_ptr(tmpptr); | ||
68 | + gen_helper_get_cp_reg64(tcg_rt, cpu_env, tcg_constant_ptr(ri)); | ||
69 | } else { | ||
70 | tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset); | ||
71 | } | ||
72 | @@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, | ||
73 | /* If not forbidden by access permissions, treat as WI */ | ||
74 | return; | ||
75 | } else if (ri->writefn) { | ||
76 | - TCGv_ptr tmpptr; | ||
77 | - tmpptr = tcg_const_ptr(ri); | ||
78 | - gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt); | ||
79 | - tcg_temp_free_ptr(tmpptr); | ||
80 | + gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri), tcg_rt); | ||
81 | } else { | ||
82 | tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset); | ||
83 | } | ||
84 | -- | ||
85 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-8-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate-a64.c | 5 +---- | ||
9 | 1 file changed, 1 insertion(+), 4 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate-a64.c | ||
14 | +++ b/target/arm/translate-a64.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn) | ||
16 | int opc = extract32(insn, 21, 3); | ||
17 | int op2_ll = extract32(insn, 0, 5); | ||
18 | int imm16 = extract32(insn, 5, 16); | ||
19 | - TCGv_i32 tmp; | ||
20 | |||
21 | switch (opc) { | ||
22 | case 0: | ||
23 | @@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn) | ||
24 | break; | ||
25 | } | ||
26 | gen_a64_set_pc_im(s->pc_curr); | ||
27 | - tmp = tcg_const_i32(syn_aa64_smc(imm16)); | ||
28 | - gen_helper_pre_smc(cpu_env, tmp); | ||
29 | - tcg_temp_free_i32(tmp); | ||
30 | + gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16))); | ||
31 | gen_ss_advance(s); | ||
32 | gen_exception_insn(s, s->base.pc_next, EXCP_SMC, | ||
33 | syn_aa64_smc(imm16), 3); | ||
34 | -- | ||
35 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-9-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate-a64.c | 6 ++---- | ||
9 | 1 file changed, 2 insertions(+), 4 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate-a64.c | ||
14 | +++ b/target/arm/translate-a64.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, | ||
16 | tcg_temp_free_i64(cmp); | ||
17 | } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { | ||
18 | if (HAVE_CMPXCHG128) { | ||
19 | - TCGv_i32 tcg_rs = tcg_const_i32(rs); | ||
20 | + TCGv_i32 tcg_rs = tcg_constant_i32(rs); | ||
21 | if (s->be_data == MO_LE) { | ||
22 | gen_helper_casp_le_parallel(cpu_env, tcg_rs, | ||
23 | clean_addr, t1, t2); | ||
24 | @@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, | ||
25 | gen_helper_casp_be_parallel(cpu_env, tcg_rs, | ||
26 | clean_addr, t1, t2); | ||
27 | } | ||
28 | - tcg_temp_free_i32(tcg_rs); | ||
29 | } else { | ||
30 | gen_helper_exit_atomic(cpu_env); | ||
31 | s->base.is_jmp = DISAS_NORETURN; | ||
32 | @@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, | ||
33 | TCGv_i64 a2 = tcg_temp_new_i64(); | ||
34 | TCGv_i64 c1 = tcg_temp_new_i64(); | ||
35 | TCGv_i64 c2 = tcg_temp_new_i64(); | ||
36 | - TCGv_i64 zero = tcg_const_i64(0); | ||
37 | + TCGv_i64 zero = tcg_constant_i64(0); | ||
38 | |||
39 | /* Load the two words, in memory order. */ | ||
40 | tcg_gen_qemu_ld_i64(d1, clean_addr, memidx, | ||
41 | @@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, | ||
42 | tcg_temp_free_i64(a2); | ||
43 | tcg_temp_free_i64(c1); | ||
44 | tcg_temp_free_i64(c2); | ||
45 | - tcg_temp_free_i64(zero); | ||
46 | |||
47 | /* Write back the data from memory to Rs. */ | ||
48 | tcg_gen_mov_i64(s1, d1); | ||
49 | -- | ||
50 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-10-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate-a64.c | 3 +-- | ||
9 | 1 file changed, 1 insertion(+), 2 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate-a64.c | ||
14 | +++ b/target/arm/translate-a64.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void disas_ld_lit(DisasContext *s, uint32_t insn) | ||
16 | |||
17 | tcg_rt = cpu_reg(s, rt); | ||
18 | |||
19 | - clean_addr = tcg_const_i64(s->pc_curr + imm); | ||
20 | + clean_addr = tcg_constant_i64(s->pc_curr + imm); | ||
21 | if (is_vector) { | ||
22 | do_fp_ld(s, rt, clean_addr, size); | ||
23 | } else { | ||
24 | @@ -XXX,XX +XXX,XX @@ static void disas_ld_lit(DisasContext *s, uint32_t insn) | ||
25 | do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, | ||
26 | false, true, rt, iss_sf, false); | ||
27 | } | ||
28 | - tcg_temp_free_i64(clean_addr); | ||
29 | } | ||
30 | |||
31 | /* | ||
32 | -- | ||
33 | 2.25.1 | diff view generated by jsdifflib |
1 | In exynos4210_init_board_irqs(), the loop that handles IRQ lines that | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | are in a range that applies to the internal combiner only creates a | ||
3 | splitter for those interrupts which go to both the internal combiner | ||
4 | and to the external GIC, but it does nothing at all for the | ||
5 | interrupts which don't go to the external GIC, leaving the | ||
6 | irq_table[] array element empty for those. (This will result in | ||
7 | those interrupts simply being lost, not in a QEMU crash.) | ||
8 | 2 | ||
9 | I don't have a reliable datasheet for this SoC, but since we do wire | 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | up one interrupt line in this category (the HDMI I2C device on | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | interrupt 16,1), this seems like it must be a bug in the existing | 5 | Message-id: 20220426163043.100432-11-richard.henderson@linaro.org |
12 | QEMU code. Fill in the irq_table[] entries where we're not splitting | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | the IRQ to both the internal combiner and the external GIC with the | 7 | --- |
14 | IRQ line of the internal combiner. (That is, these IRQ lines go to | 8 | target/arm/translate-a64.c | 9 +++------ |
15 | just one device, not multiple.) | 9 | 1 file changed, 3 insertions(+), 6 deletions(-) |
16 | 10 | ||
17 | This bug didn't have any visible guest effects because the only | 11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
18 | implemented device that was affected was the HDMI I2C controller, | ||
19 | and we never connect any I2C devices to that bus. | ||
20 | |||
21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
22 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
23 | Message-id: 20220404154658.565020-14-peter.maydell@linaro.org | ||
24 | --- | ||
25 | hw/arm/exynos4210.c | 2 ++ | ||
26 | 1 file changed, 2 insertions(+) | ||
27 | |||
28 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/hw/arm/exynos4210.c | 13 | --- a/target/arm/translate-a64.c |
31 | +++ b/hw/arm/exynos4210.c | 14 | +++ b/target/arm/translate-a64.c |
32 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | 15 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) |
33 | qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); | 16 | mop = endian | size | align; |
34 | qdev_connect_gpio_out(splitter, 1, | 17 | |
35 | qdev_get_gpio_in(extgicdev, irq_id - 32)); | 18 | elements = (is_q ? 16 : 8) >> size; |
36 | + } else { | 19 | - tcg_ebytes = tcg_const_i64(1 << size); |
37 | + s->irq_table[n] = is->int_combiner_irq[n]; | 20 | + tcg_ebytes = tcg_constant_i64(1 << size); |
21 | for (r = 0; r < rpt; r++) { | ||
22 | int e; | ||
23 | for (e = 0; e < elements; e++) { | ||
24 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) | ||
25 | } | ||
38 | } | 26 | } |
39 | } | 27 | } |
40 | /* | 28 | - tcg_temp_free_i64(tcg_ebytes); |
29 | |||
30 | if (!is_store) { | ||
31 | /* For non-quad operations, setting a slice of the low | ||
32 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) | ||
33 | total); | ||
34 | mop = finalize_memop(s, scale); | ||
35 | |||
36 | - tcg_ebytes = tcg_const_i64(1 << scale); | ||
37 | + tcg_ebytes = tcg_constant_i64(1 << scale); | ||
38 | for (xs = 0; xs < selem; xs++) { | ||
39 | if (replicate) { | ||
40 | /* Load and replicate to all elements */ | ||
41 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) | ||
42 | tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); | ||
43 | rt = (rt + 1) % 32; | ||
44 | } | ||
45 | - tcg_temp_free_i64(tcg_ebytes); | ||
46 | |||
47 | if (is_postidx) { | ||
48 | if (rm == 31) { | ||
49 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) | ||
50 | |||
51 | if (is_zero) { | ||
52 | TCGv_i64 clean_addr = clean_data_tbi(s, addr); | ||
53 | - TCGv_i64 tcg_zero = tcg_const_i64(0); | ||
54 | + TCGv_i64 tcg_zero = tcg_constant_i64(0); | ||
55 | int mem_index = get_mem_index(s); | ||
56 | int i, n = (1 + is_pair) << LOG2_TAG_GRANULE; | ||
57 | |||
58 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) | ||
59 | tcg_gen_addi_i64(clean_addr, clean_addr, 8); | ||
60 | tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_UQ); | ||
61 | } | ||
62 | - tcg_temp_free_i64(tcg_zero); | ||
63 | } | ||
64 | |||
65 | if (index != 0) { | ||
41 | -- | 66 | -- |
42 | 2.25.1 | 67 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-12-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate-a64.c | 12 ++++-------- | ||
9 | 1 file changed, 4 insertions(+), 8 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate-a64.c | ||
14 | +++ b/target/arm/translate-a64.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void disas_add_sub_imm(DisasContext *s, uint32_t insn) | ||
16 | tcg_gen_addi_i64(tcg_result, tcg_rn, imm); | ||
17 | } | ||
18 | } else { | ||
19 | - TCGv_i64 tcg_imm = tcg_const_i64(imm); | ||
20 | + TCGv_i64 tcg_imm = tcg_constant_i64(imm); | ||
21 | if (sub_op) { | ||
22 | gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); | ||
23 | } else { | ||
24 | gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); | ||
25 | } | ||
26 | - tcg_temp_free_i64(tcg_imm); | ||
27 | } | ||
28 | |||
29 | if (is_64bit) { | ||
30 | @@ -XXX,XX +XXX,XX @@ static void disas_add_sub_imm_with_tags(DisasContext *s, uint32_t insn) | ||
31 | tcg_rd = cpu_reg_sp(s, rd); | ||
32 | |||
33 | if (s->ata) { | ||
34 | - TCGv_i32 offset = tcg_const_i32(imm); | ||
35 | - TCGv_i32 tag_offset = tcg_const_i32(uimm4); | ||
36 | - | ||
37 | - gen_helper_addsubg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset); | ||
38 | - tcg_temp_free_i32(tag_offset); | ||
39 | - tcg_temp_free_i32(offset); | ||
40 | + gen_helper_addsubg(tcg_rd, cpu_env, tcg_rn, | ||
41 | + tcg_constant_i32(imm), | ||
42 | + tcg_constant_i32(uimm4)); | ||
43 | } else { | ||
44 | tcg_gen_addi_i64(tcg_rd, tcg_rn, imm); | ||
45 | gen_address_with_allocation_tag0(tcg_rd, tcg_rd); | ||
46 | -- | ||
47 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-13-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate-a64.c | 5 +---- | ||
9 | 1 file changed, 1 insertion(+), 4 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate-a64.c | ||
14 | +++ b/target/arm/translate-a64.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void disas_movw_imm(DisasContext *s, uint32_t insn) | ||
16 | int opc = extract32(insn, 29, 2); | ||
17 | int pos = extract32(insn, 21, 2) << 4; | ||
18 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | ||
19 | - TCGv_i64 tcg_imm; | ||
20 | |||
21 | if (!sf && (pos >= 32)) { | ||
22 | unallocated_encoding(s); | ||
23 | @@ -XXX,XX +XXX,XX @@ static void disas_movw_imm(DisasContext *s, uint32_t insn) | ||
24 | tcg_gen_movi_i64(tcg_rd, imm); | ||
25 | break; | ||
26 | case 3: /* MOVK */ | ||
27 | - tcg_imm = tcg_const_i64(imm); | ||
28 | - tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16); | ||
29 | - tcg_temp_free_i64(tcg_imm); | ||
30 | + tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_constant_i64(imm), pos, 16); | ||
31 | if (!sf) { | ||
32 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | ||
33 | } | ||
34 | -- | ||
35 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Hao Wu <wuhaotsh@google.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This patch uses the defined fields to describe PWRON STRAPs for | 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
4 | better readability. | ||
5 | |||
6 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | ||
7 | Reviewed-by: Patrick Venture <venture@google.com> | ||
8 | Message-id: 20220411165842.3912945-3-wuhaotsh@google.com | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Message-id: 20220426163043.100432-14-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 7 | --- |
12 | hw/arm/npcm7xx_boards.c | 24 +++++++++++++++++++----- | 8 | target/arm/translate-a64.c | 6 +----- |
13 | 1 file changed, 19 insertions(+), 5 deletions(-) | 9 | 1 file changed, 1 insertion(+), 5 deletions(-) |
14 | 10 | ||
15 | diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c | 11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
16 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/arm/npcm7xx_boards.c | 13 | --- a/target/arm/translate-a64.c |
18 | +++ b/hw/arm/npcm7xx_boards.c | 14 | +++ b/target/arm/translate-a64.c |
19 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf, |
20 | #include "sysemu/sysemu.h" | 16 | if (shift_i == 0) { |
21 | #include "sysemu/block-backend.h" | 17 | tcg_gen_mov_i64(dst, src); |
22 | 18 | } else { | |
23 | -#define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7 | 19 | - TCGv_i64 shift_const; |
24 | -#define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff | 20 | - |
25 | -#define QUANTA_GBS_POWER_ON_STRAPS 0x000017ff | 21 | - shift_const = tcg_const_i64(shift_i); |
26 | -#define KUDO_BMC_POWER_ON_STRAPS 0x00001fff | 22 | - shift_reg(dst, src, sf, shift_type, shift_const); |
27 | -#define MORI_BMC_POWER_ON_STRAPS 0x00001fff | 23 | - tcg_temp_free_i64(shift_const); |
28 | +#define NPCM7XX_POWER_ON_STRAPS_DEFAULT ( \ | 24 | + shift_reg(dst, src, sf, shift_type, tcg_constant_i64(shift_i)); |
29 | + NPCM7XX_PWRON_STRAP_SPI0F18 | \ | 25 | } |
30 | + NPCM7XX_PWRON_STRAP_SFAB | \ | 26 | } |
31 | + NPCM7XX_PWRON_STRAP_BSPA | \ | ||
32 | + NPCM7XX_PWRON_STRAP_FUP(FUP_NORM_UART2) | \ | ||
33 | + NPCM7XX_PWRON_STRAP_SECEN | \ | ||
34 | + NPCM7XX_PWRON_STRAP_HIZ | \ | ||
35 | + NPCM7XX_PWRON_STRAP_ECC | \ | ||
36 | + NPCM7XX_PWRON_STRAP_RESERVE1 | \ | ||
37 | + NPCM7XX_PWRON_STRAP_J2EN | \ | ||
38 | + NPCM7XX_PWRON_STRAP_CKFRQ(CKFRQ_DEFAULT)) | ||
39 | + | ||
40 | +#define NPCM750_EVB_POWER_ON_STRAPS ( \ | ||
41 | + NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_J2EN) | ||
42 | +#define QUANTA_GSJ_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT | ||
43 | +#define QUANTA_GBS_POWER_ON_STRAPS ( \ | ||
44 | + NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_SFAB) | ||
45 | +#define KUDO_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT | ||
46 | +#define MORI_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT | ||
47 | |||
48 | static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin"; | ||
49 | 27 | ||
50 | -- | 28 | -- |
51 | 2.25.1 | 29 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-15-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate-a64.c | 3 +-- | ||
9 | 1 file changed, 1 insertion(+), 2 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate-a64.c | ||
14 | +++ b/target/arm/translate-a64.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void disas_cond_select(DisasContext *s, uint32_t insn) | ||
16 | tcg_rd = cpu_reg(s, rd); | ||
17 | |||
18 | a64_test_cc(&c, cond); | ||
19 | - zero = tcg_const_i64(0); | ||
20 | + zero = tcg_constant_i64(0); | ||
21 | |||
22 | if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) { | ||
23 | /* CSET & CSETM. */ | ||
24 | @@ -XXX,XX +XXX,XX @@ static void disas_cond_select(DisasContext *s, uint32_t insn) | ||
25 | tcg_gen_movcond_i64(c.cond, tcg_rd, c.value, zero, t_true, t_false); | ||
26 | } | ||
27 | |||
28 | - tcg_temp_free_i64(zero); | ||
29 | a64_free_cc(&c); | ||
30 | |||
31 | if (!sf) { | ||
32 | -- | ||
33 | 2.25.1 | diff view generated by jsdifflib |
1 | Switch the creation of the combiner devices to the new-style | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | "embedded in state struct" approach, so we can easily refer | ||
3 | to the object elsewhere during realize. | ||
4 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-16-richard.henderson@linaro.org | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20220404154658.565020-18-peter.maydell@linaro.org | ||
8 | --- | 7 | --- |
9 | include/hw/arm/exynos4210.h | 3 ++ | 8 | target/arm/translate-a64.c | 7 ++----- |
10 | include/hw/intc/exynos4210_combiner.h | 57 +++++++++++++++++++++++++++ | 9 | 1 file changed, 2 insertions(+), 5 deletions(-) |
11 | hw/arm/exynos4210.c | 20 +++++----- | ||
12 | hw/intc/exynos4210_combiner.c | 31 +-------------- | ||
13 | 4 files changed, 72 insertions(+), 39 deletions(-) | ||
14 | create mode 100644 include/hw/intc/exynos4210_combiner.h | ||
15 | 10 | ||
16 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | 11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
17 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/arm/exynos4210.h | 13 | --- a/target/arm/translate-a64.c |
19 | +++ b/include/hw/arm/exynos4210.h | 14 | +++ b/target/arm/translate-a64.c |
20 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ static void handle_rev16(DisasContext *s, unsigned int sf, |
21 | #include "hw/sysbus.h" | 16 | TCGv_i64 tcg_rd = cpu_reg(s, rd); |
22 | #include "hw/cpu/a9mpcore.h" | 17 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
23 | #include "hw/intc/exynos4210_gic.h" | 18 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); |
24 | +#include "hw/intc/exynos4210_combiner.h" | 19 | - TCGv_i64 mask = tcg_const_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00ff); |
25 | #include "hw/core/split-irq.h" | 20 | + TCGv_i64 mask = tcg_constant_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00ff); |
26 | #include "target/arm/cpu-qom.h" | 21 | |
27 | #include "qom/object.h" | 22 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 8); |
28 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { | 23 | tcg_gen_and_i64(tcg_rd, tcg_rn, mask); |
29 | qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; | 24 | @@ -XXX,XX +XXX,XX @@ static void handle_rev16(DisasContext *s, unsigned int sf, |
30 | A9MPPrivState a9mpcore; | 25 | tcg_gen_shli_i64(tcg_rd, tcg_rd, 8); |
31 | Exynos4210GicState ext_gic; | 26 | tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_tmp); |
32 | + Exynos4210CombinerState int_combiner; | 27 | |
33 | + Exynos4210CombinerState ext_combiner; | 28 | - tcg_temp_free_i64(mask); |
34 | SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS]; | 29 | tcg_temp_free_i64(tcg_tmp); |
35 | }; | 30 | } |
36 | 31 | ||
37 | diff --git a/include/hw/intc/exynos4210_combiner.h b/include/hw/intc/exynos4210_combiner.h | 32 | @@ -XXX,XX +XXX,XX @@ static void handle_crc32(DisasContext *s, |
38 | new file mode 100644 | ||
39 | index XXXXXXX..XXXXXXX | ||
40 | --- /dev/null | ||
41 | +++ b/include/hw/intc/exynos4210_combiner.h | ||
42 | @@ -XXX,XX +XXX,XX @@ | ||
43 | +/* | ||
44 | + * Samsung exynos4210 Interrupt Combiner | ||
45 | + * | ||
46 | + * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. | ||
47 | + * All rights reserved. | ||
48 | + * | ||
49 | + * Evgeny Voevodin <e.voevodin@samsung.com> | ||
50 | + * | ||
51 | + * This program is free software; you can redistribute it and/or modify it | ||
52 | + * under the terms of the GNU General Public License as published by the | ||
53 | + * Free Software Foundation; either version 2 of the License, or (at your | ||
54 | + * option) any later version. | ||
55 | + * | ||
56 | + * This program is distributed in the hope that it will be useful, | ||
57 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
58 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | ||
59 | + * See the GNU General Public License for more details. | ||
60 | + * | ||
61 | + * You should have received a copy of the GNU General Public License along | ||
62 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
63 | + */ | ||
64 | + | ||
65 | +#ifndef HW_INTC_EXYNOS4210_COMBINER | ||
66 | +#define HW_INTC_EXYNOS4210_COMBINER | ||
67 | + | ||
68 | +#include "hw/sysbus.h" | ||
69 | + | ||
70 | +/* | ||
71 | + * State for each output signal of internal combiner | ||
72 | + */ | ||
73 | +typedef struct CombinerGroupState { | ||
74 | + uint8_t src_mask; /* 1 - source enabled, 0 - disabled */ | ||
75 | + uint8_t src_pending; /* Pending source interrupts before masking */ | ||
76 | +} CombinerGroupState; | ||
77 | + | ||
78 | +#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner" | ||
79 | +OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210CombinerState, EXYNOS4210_COMBINER) | ||
80 | + | ||
81 | +/* Number of groups and total number of interrupts for the internal combiner */ | ||
82 | +#define IIC_NGRP 64 | ||
83 | +#define IIC_NIRQ (IIC_NGRP * 8) | ||
84 | +#define IIC_REGSET_SIZE 0x41 | ||
85 | + | ||
86 | +struct Exynos4210CombinerState { | ||
87 | + SysBusDevice parent_obj; | ||
88 | + | ||
89 | + MemoryRegion iomem; | ||
90 | + | ||
91 | + struct CombinerGroupState group[IIC_NGRP]; | ||
92 | + uint32_t reg_set[IIC_REGSET_SIZE]; | ||
93 | + uint32_t icipsr[2]; | ||
94 | + uint32_t external; /* 1 means that this combiner is external */ | ||
95 | + | ||
96 | + qemu_irq output_irq[IIC_NGRP]; | ||
97 | +}; | ||
98 | + | ||
99 | +#endif | ||
100 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
101 | index XXXXXXX..XXXXXXX 100644 | ||
102 | --- a/hw/arm/exynos4210.c | ||
103 | +++ b/hw/arm/exynos4210.c | ||
104 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
105 | } | 33 | } |
106 | 34 | ||
107 | /* Internal Interrupt Combiner */ | 35 | tcg_acc = cpu_reg(s, rn); |
108 | - dev = qdev_new("exynos4210.combiner"); | 36 | - tcg_bytes = tcg_const_i32(1 << sz); |
109 | - busdev = SYS_BUS_DEVICE(dev); | 37 | + tcg_bytes = tcg_constant_i32(1 << sz); |
110 | - sysbus_realize_and_unref(busdev, &error_fatal); | 38 | |
111 | + busdev = SYS_BUS_DEVICE(&s->int_combiner); | 39 | if (crc32c) { |
112 | + sysbus_realize(busdev, &error_fatal); | 40 | gen_helper_crc32c_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes); |
113 | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { | 41 | } else { |
114 | sysbus_connect_irq(busdev, n, | 42 | gen_helper_crc32_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes); |
115 | qdev_get_gpio_in(DEVICE(&s->a9mpcore), n)); | ||
116 | } | 43 | } |
117 | - exynos4210_combiner_get_gpioin(&s->irqs, dev, 0); | 44 | - |
118 | + exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->int_combiner), 0); | 45 | - tcg_temp_free_i32(tcg_bytes); |
119 | sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); | ||
120 | |||
121 | /* External Interrupt Combiner */ | ||
122 | - dev = qdev_new("exynos4210.combiner"); | ||
123 | - qdev_prop_set_uint32(dev, "external", 1); | ||
124 | - busdev = SYS_BUS_DEVICE(dev); | ||
125 | - sysbus_realize_and_unref(busdev, &error_fatal); | ||
126 | + qdev_prop_set_uint32(DEVICE(&s->ext_combiner), "external", 1); | ||
127 | + busdev = SYS_BUS_DEVICE(&s->ext_combiner); | ||
128 | + sysbus_realize(busdev, &error_fatal); | ||
129 | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { | ||
130 | sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n)); | ||
131 | } | ||
132 | - exynos4210_combiner_get_gpioin(&s->irqs, dev, 1); | ||
133 | + exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->ext_combiner), 1); | ||
134 | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); | ||
135 | |||
136 | /* Initialize board IRQs. */ | ||
137 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj) | ||
138 | |||
139 | object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); | ||
140 | object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC); | ||
141 | + object_initialize_child(obj, "int-combiner", &s->int_combiner, | ||
142 | + TYPE_EXYNOS4210_COMBINER); | ||
143 | + object_initialize_child(obj, "ext-combiner", &s->ext_combiner, | ||
144 | + TYPE_EXYNOS4210_COMBINER); | ||
145 | } | 46 | } |
146 | 47 | ||
147 | static void exynos4210_class_init(ObjectClass *klass, void *data) | 48 | /* Data-processing (2 source) |
148 | diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c | ||
149 | index XXXXXXX..XXXXXXX 100644 | ||
150 | --- a/hw/intc/exynos4210_combiner.c | ||
151 | +++ b/hw/intc/exynos4210_combiner.c | ||
152 | @@ -XXX,XX +XXX,XX @@ | ||
153 | #include "hw/sysbus.h" | ||
154 | #include "migration/vmstate.h" | ||
155 | #include "qemu/module.h" | ||
156 | - | ||
157 | +#include "hw/intc/exynos4210_combiner.h" | ||
158 | #include "hw/arm/exynos4210.h" | ||
159 | #include "hw/hw.h" | ||
160 | #include "hw/irq.h" | ||
161 | @@ -XXX,XX +XXX,XX @@ | ||
162 | #define DPRINTF(fmt, ...) do {} while (0) | ||
163 | #endif | ||
164 | |||
165 | -#define IIC_NGRP 64 /* Internal Interrupt Combiner | ||
166 | - Groups number */ | ||
167 | -#define IIC_NIRQ (IIC_NGRP * 8)/* Internal Interrupt Combiner | ||
168 | - Interrupts number */ | ||
169 | #define IIC_REGION_SIZE 0x108 /* Size of memory mapped region */ | ||
170 | -#define IIC_REGSET_SIZE 0x41 | ||
171 | - | ||
172 | -/* | ||
173 | - * State for each output signal of internal combiner | ||
174 | - */ | ||
175 | -typedef struct CombinerGroupState { | ||
176 | - uint8_t src_mask; /* 1 - source enabled, 0 - disabled */ | ||
177 | - uint8_t src_pending; /* Pending source interrupts before masking */ | ||
178 | -} CombinerGroupState; | ||
179 | - | ||
180 | -#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner" | ||
181 | -OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210CombinerState, EXYNOS4210_COMBINER) | ||
182 | - | ||
183 | -struct Exynos4210CombinerState { | ||
184 | - SysBusDevice parent_obj; | ||
185 | - | ||
186 | - MemoryRegion iomem; | ||
187 | - | ||
188 | - struct CombinerGroupState group[IIC_NGRP]; | ||
189 | - uint32_t reg_set[IIC_REGSET_SIZE]; | ||
190 | - uint32_t icipsr[2]; | ||
191 | - uint32_t external; /* 1 means that this combiner is external */ | ||
192 | - | ||
193 | - qemu_irq output_irq[IIC_NGRP]; | ||
194 | -}; | ||
195 | |||
196 | static const VMStateDescription vmstate_exynos4210_combiner_group_state = { | ||
197 | .name = "exynos4210.combiner.groupstate", | ||
198 | -- | 49 | -- |
199 | 2.25.1 | 50 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Existing temp usage treats t1 as both zero and as a | ||
4 | temporary. Rearrange to only require one temporary, | ||
5 | so remove t1 and rename t2. | ||
6 | |||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Message-id: 20220426163043.100432-17-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/translate-a64.c | 12 +++++------- | ||
13 | 1 file changed, 5 insertions(+), 7 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/translate-a64.c | ||
18 | +++ b/target/arm/translate-a64.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) | ||
20 | if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { | ||
21 | goto do_unallocated; | ||
22 | } else { | ||
23 | - TCGv_i64 t1 = tcg_const_i64(1); | ||
24 | - TCGv_i64 t2 = tcg_temp_new_i64(); | ||
25 | + TCGv_i64 t = tcg_temp_new_i64(); | ||
26 | |||
27 | - tcg_gen_extract_i64(t2, cpu_reg_sp(s, rn), 56, 4); | ||
28 | - tcg_gen_shl_i64(t1, t1, t2); | ||
29 | - tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t1); | ||
30 | + tcg_gen_extract_i64(t, cpu_reg_sp(s, rn), 56, 4); | ||
31 | + tcg_gen_shl_i64(t, tcg_constant_i64(1), t); | ||
32 | + tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t); | ||
33 | |||
34 | - tcg_temp_free_i64(t1); | ||
35 | - tcg_temp_free_i64(t2); | ||
36 | + tcg_temp_free_i64(t); | ||
37 | } | ||
38 | break; | ||
39 | case 8: /* LSLV */ | ||
40 | -- | ||
41 | 2.25.1 | diff view generated by jsdifflib |
1 | Switch the creation of the external GIC to the new-style "embedded in | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | state struct" approach, so we can easily refer to the object | ||
3 | elsewhere during realize. | ||
4 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-18-richard.henderson@linaro.org | ||
6 | [PMM: Restore incorrectly removed free of t_false in disas_fp_csel()] | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20220404154658.565020-9-peter.maydell@linaro.org | ||
8 | --- | 8 | --- |
9 | include/hw/arm/exynos4210.h | 2 ++ | 9 | target/arm/translate-a64.c | 23 +++++++---------------- |
10 | include/hw/intc/exynos4210_gic.h | 43 ++++++++++++++++++++++++++++++++ | 10 | 1 file changed, 7 insertions(+), 16 deletions(-) |
11 | hw/arm/exynos4210.c | 10 ++++---- | ||
12 | hw/intc/exynos4210_gic.c | 17 ++----------- | ||
13 | MAINTAINERS | 2 +- | ||
14 | 5 files changed, 53 insertions(+), 21 deletions(-) | ||
15 | create mode 100644 include/hw/intc/exynos4210_gic.h | ||
16 | 11 | ||
17 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | 12 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
18 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/include/hw/arm/exynos4210.h | 14 | --- a/target/arm/translate-a64.c |
20 | +++ b/include/hw/arm/exynos4210.h | 15 | +++ b/target/arm/translate-a64.c |
21 | @@ -XXX,XX +XXX,XX @@ | 16 | @@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, int size, |
22 | #include "hw/or-irq.h" | 17 | |
23 | #include "hw/sysbus.h" | 18 | tcg_vn = read_fp_dreg(s, rn); |
24 | #include "hw/cpu/a9mpcore.h" | 19 | if (cmp_with_zero) { |
25 | +#include "hw/intc/exynos4210_gic.h" | 20 | - tcg_vm = tcg_const_i64(0); |
26 | #include "target/arm/cpu-qom.h" | 21 | + tcg_vm = tcg_constant_i64(0); |
27 | #include "qom/object.h" | 22 | } else { |
28 | 23 | tcg_vm = read_fp_dreg(s, rm); | |
29 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { | 24 | } |
30 | qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; | 25 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn) |
31 | qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; | 26 | static void disas_fp_ccomp(DisasContext *s, uint32_t insn) |
32 | A9MPPrivState a9mpcore; | 27 | { |
33 | + Exynos4210GicState ext_gic; | 28 | unsigned int mos, type, rm, cond, rn, op, nzcv; |
34 | }; | 29 | - TCGv_i64 tcg_flags; |
35 | 30 | TCGLabel *label_continue = NULL; | |
36 | #define TYPE_EXYNOS4210_SOC "exynos4210" | 31 | int size; |
37 | diff --git a/include/hw/intc/exynos4210_gic.h b/include/hw/intc/exynos4210_gic.h | 32 | |
38 | new file mode 100644 | 33 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn) |
39 | index XXXXXXX..XXXXXXX | 34 | label_continue = gen_new_label(); |
40 | --- /dev/null | 35 | arm_gen_test_cc(cond, label_match); |
41 | +++ b/include/hw/intc/exynos4210_gic.h | 36 | /* nomatch: */ |
42 | @@ -XXX,XX +XXX,XX @@ | 37 | - tcg_flags = tcg_const_i64(nzcv << 28); |
43 | +/* | 38 | - gen_set_nzcv(tcg_flags); |
44 | + * Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c | 39 | - tcg_temp_free_i64(tcg_flags); |
45 | + * | 40 | + gen_set_nzcv(tcg_constant_i64(nzcv << 28)); |
46 | + * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. | 41 | tcg_gen_br(label_continue); |
47 | + * All rights reserved. | 42 | gen_set_label(label_match); |
48 | + * | ||
49 | + * Evgeny Voevodin <e.voevodin@samsung.com> | ||
50 | + * | ||
51 | + * This program is free software; you can redistribute it and/or modify it | ||
52 | + * under the terms of the GNU General Public License as published by the | ||
53 | + * Free Software Foundation; either version 2 of the License, or (at your | ||
54 | + * option) any later version. | ||
55 | + * | ||
56 | + * This program is distributed in the hope that it will be useful, | ||
57 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
58 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | ||
59 | + * See the GNU General Public License for more details. | ||
60 | + * | ||
61 | + * You should have received a copy of the GNU General Public License along | ||
62 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
63 | + */ | ||
64 | +#ifndef HW_INTC_EXYNOS4210_GIC_H | ||
65 | +#define HW_INTC_EXYNOS4210_GIC_H | ||
66 | + | ||
67 | +#include "hw/sysbus.h" | ||
68 | + | ||
69 | +#define TYPE_EXYNOS4210_GIC "exynos4210.gic" | ||
70 | +OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC) | ||
71 | + | ||
72 | +#define EXYNOS4210_GIC_NCPUS 2 | ||
73 | + | ||
74 | +struct Exynos4210GicState { | ||
75 | + SysBusDevice parent_obj; | ||
76 | + | ||
77 | + MemoryRegion cpu_container; | ||
78 | + MemoryRegion dist_container; | ||
79 | + MemoryRegion cpu_alias[EXYNOS4210_GIC_NCPUS]; | ||
80 | + MemoryRegion dist_alias[EXYNOS4210_GIC_NCPUS]; | ||
81 | + uint32_t num_cpu; | ||
82 | + DeviceState *gic; | ||
83 | +}; | ||
84 | + | ||
85 | +#endif | ||
86 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
87 | index XXXXXXX..XXXXXXX 100644 | ||
88 | --- a/hw/arm/exynos4210.c | ||
89 | +++ b/hw/arm/exynos4210.c | ||
90 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
91 | sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); | ||
92 | |||
93 | /* External GIC */ | ||
94 | - dev = qdev_new("exynos4210.gic"); | ||
95 | - qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); | ||
96 | - busdev = SYS_BUS_DEVICE(dev); | ||
97 | - sysbus_realize_and_unref(busdev, &error_fatal); | ||
98 | + qdev_prop_set_uint32(DEVICE(&s->ext_gic), "num-cpu", EXYNOS4210_NCPUS); | ||
99 | + busdev = SYS_BUS_DEVICE(&s->ext_gic); | ||
100 | + sysbus_realize(busdev, &error_fatal); | ||
101 | /* Map CPU interface */ | ||
102 | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); | ||
103 | /* Map Distributer interface */ | ||
104 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
105 | qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1)); | ||
106 | } | 43 | } |
107 | for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { | 44 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn) |
108 | - s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n); | 45 | static void disas_fp_csel(DisasContext *s, uint32_t insn) |
109 | + s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->ext_gic), n); | 46 | { |
47 | unsigned int mos, type, rm, cond, rn, rd; | ||
48 | - TCGv_i64 t_true, t_false, t_zero; | ||
49 | + TCGv_i64 t_true, t_false; | ||
50 | DisasCompare64 c; | ||
51 | MemOp sz; | ||
52 | |||
53 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn) | ||
54 | read_vec_element(s, t_false, rm, 0, sz); | ||
55 | |||
56 | a64_test_cc(&c, cond); | ||
57 | - t_zero = tcg_const_i64(0); | ||
58 | - tcg_gen_movcond_i64(c.cond, t_true, c.value, t_zero, t_true, t_false); | ||
59 | - tcg_temp_free_i64(t_zero); | ||
60 | + tcg_gen_movcond_i64(c.cond, t_true, c.value, tcg_constant_i64(0), | ||
61 | + t_true, t_false); | ||
62 | tcg_temp_free_i64(t_false); | ||
63 | a64_free_cc(&c); | ||
64 | |||
65 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn) | ||
66 | int type = extract32(insn, 22, 2); | ||
67 | int mos = extract32(insn, 29, 3); | ||
68 | uint64_t imm; | ||
69 | - TCGv_i64 tcg_res; | ||
70 | MemOp sz; | ||
71 | |||
72 | if (mos || imm5) { | ||
73 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn) | ||
110 | } | 74 | } |
111 | 75 | ||
112 | /* Internal Interrupt Combiner */ | 76 | imm = vfp_expand_imm(sz, imm8); |
113 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj) | 77 | - |
78 | - tcg_res = tcg_const_i64(imm); | ||
79 | - write_fp_dreg(s, rd, tcg_res); | ||
80 | - tcg_temp_free_i64(tcg_res); | ||
81 | + write_fp_dreg(s, rd, tcg_constant_i64(imm)); | ||
82 | } | ||
83 | |||
84 | /* Handle floating point <=> fixed point conversions. Note that we can | ||
85 | @@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, | ||
86 | |||
87 | tcg_fpstatus = fpstatus_ptr(type == 3 ? FPST_FPCR_F16 : FPST_FPCR); | ||
88 | |||
89 | - tcg_shift = tcg_const_i32(64 - scale); | ||
90 | + tcg_shift = tcg_constant_i32(64 - scale); | ||
91 | |||
92 | if (itof) { | ||
93 | TCGv_i64 tcg_int = cpu_reg(s, rn); | ||
94 | @@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, | ||
114 | } | 95 | } |
115 | 96 | ||
116 | object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); | 97 | tcg_temp_free_ptr(tcg_fpstatus); |
117 | + object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC); | 98 | - tcg_temp_free_i32(tcg_shift); |
118 | } | 99 | } |
119 | 100 | ||
120 | static void exynos4210_class_init(ObjectClass *klass, void *data) | 101 | /* Floating point <-> fixed point conversions |
121 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | ||
122 | index XXXXXXX..XXXXXXX 100644 | ||
123 | --- a/hw/intc/exynos4210_gic.c | ||
124 | +++ b/hw/intc/exynos4210_gic.c | ||
125 | @@ -XXX,XX +XXX,XX @@ | ||
126 | #include "qemu/module.h" | ||
127 | #include "hw/irq.h" | ||
128 | #include "hw/qdev-properties.h" | ||
129 | +#include "hw/intc/exynos4210_gic.h" | ||
130 | #include "hw/arm/exynos4210.h" | ||
131 | #include "qom/object.h" | ||
132 | |||
133 | @@ -XXX,XX +XXX,XX @@ | ||
134 | #define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100 | ||
135 | #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000 | ||
136 | |||
137 | -#define TYPE_EXYNOS4210_GIC "exynos4210.gic" | ||
138 | -OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC) | ||
139 | - | ||
140 | -struct Exynos4210GicState { | ||
141 | - SysBusDevice parent_obj; | ||
142 | - | ||
143 | - MemoryRegion cpu_container; | ||
144 | - MemoryRegion dist_container; | ||
145 | - MemoryRegion cpu_alias[EXYNOS4210_NCPUS]; | ||
146 | - MemoryRegion dist_alias[EXYNOS4210_NCPUS]; | ||
147 | - uint32_t num_cpu; | ||
148 | - DeviceState *gic; | ||
149 | -}; | ||
150 | - | ||
151 | static void exynos4210_gic_set_irq(void *opaque, int irq, int level) | ||
152 | { | ||
153 | Exynos4210GicState *s = (Exynos4210GicState *)opaque; | ||
154 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_realize(DeviceState *dev, Error **errp) | ||
155 | * enough room for the cpu numbers. gcc 9.2.1 on 32-bit x86 | ||
156 | * doesn't figure this out, otherwise and gives spurious warnings. | ||
157 | */ | ||
158 | - assert(n <= EXYNOS4210_NCPUS); | ||
159 | + assert(n <= EXYNOS4210_GIC_NCPUS); | ||
160 | for (i = 0; i < n; i++) { | ||
161 | /* Map CPU interface per SMP Core */ | ||
162 | sprintf(cpu_alias_name, "%s%x", cpu_prefix, i); | ||
163 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
164 | index XXXXXXX..XXXXXXX 100644 | ||
165 | --- a/MAINTAINERS | ||
166 | +++ b/MAINTAINERS | ||
167 | @@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org> | ||
168 | L: qemu-arm@nongnu.org | ||
169 | S: Odd Fixes | ||
170 | F: hw/*/exynos* | ||
171 | -F: include/hw/arm/exynos4210.h | ||
172 | +F: include/hw/*/exynos* | ||
173 | |||
174 | Calxeda Highbank | ||
175 | M: Rob Herring <robh@kernel.org> | ||
176 | -- | 102 | -- |
177 | 2.25.1 | 103 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Zongyuan Li <zongyuan.li@smartx.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com> | 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Message-id: 20220324181557.203805-5-zongyuan.li@smartx.com | 5 | Message-id: 20220426163043.100432-19-richard.henderson@linaro.org |
6 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/811 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 7 | --- |
9 | include/hw/irq.h | 5 ----- | 8 | target/arm/translate-a64.c | 21 +++++---------------- |
10 | hw/core/irq.c | 15 --------------- | 9 | 1 file changed, 5 insertions(+), 16 deletions(-) |
11 | 2 files changed, 20 deletions(-) | ||
12 | 10 | ||
13 | diff --git a/include/hw/irq.h b/include/hw/irq.h | 11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
14 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/include/hw/irq.h | 13 | --- a/target/arm/translate-a64.c |
16 | +++ b/include/hw/irq.h | 14 | +++ b/target/arm/translate-a64.c |
17 | @@ -XXX,XX +XXX,XX @@ void qemu_free_irq(qemu_irq irq); | 15 | @@ -XXX,XX +XXX,XX @@ static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src, |
18 | /* Returns a new IRQ with opposite polarity. */ | 16 | /* Deal with the rounding step */ |
19 | qemu_irq qemu_irq_invert(qemu_irq irq); | 17 | if (round) { |
20 | 18 | if (extended_result) { | |
21 | -/* Returns a new IRQ which feeds into both the passed IRQs. | 19 | - TCGv_i64 tcg_zero = tcg_const_i64(0); |
22 | - * It's probably better to use the TYPE_SPLIT_IRQ device instead. | 20 | + TCGv_i64 tcg_zero = tcg_constant_i64(0); |
23 | - */ | 21 | if (!is_u) { |
24 | -qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2); | 22 | /* take care of sign extending tcg_res */ |
25 | - | 23 | tcg_gen_sari_i64(tcg_src_hi, tcg_src, 63); |
26 | /* For internal use in qtest. Similar to qemu_irq_split, but operating | 24 | @@ -XXX,XX +XXX,XX @@ static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src, |
27 | on an existing vector of qemu_irq. */ | 25 | tcg_src, tcg_zero, |
28 | void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n); | 26 | tcg_rnd, tcg_zero); |
29 | diff --git a/hw/core/irq.c b/hw/core/irq.c | 27 | } |
30 | index XXXXXXX..XXXXXXX 100644 | 28 | - tcg_temp_free_i64(tcg_zero); |
31 | --- a/hw/core/irq.c | 29 | } else { |
32 | +++ b/hw/core/irq.c | 30 | tcg_gen_add_i64(tcg_src, tcg_src, tcg_rnd); |
33 | @@ -XXX,XX +XXX,XX @@ qemu_irq qemu_irq_invert(qemu_irq irq) | 31 | } |
34 | return qemu_allocate_irq(qemu_notirq, irq, 0); | 32 | @@ -XXX,XX +XXX,XX @@ static void handle_scalar_simd_shri(DisasContext *s, |
33 | } | ||
34 | |||
35 | if (round) { | ||
36 | - uint64_t round_const = 1ULL << (shift - 1); | ||
37 | - tcg_round = tcg_const_i64(round_const); | ||
38 | + tcg_round = tcg_constant_i64(1ULL << (shift - 1)); | ||
39 | } else { | ||
40 | tcg_round = NULL; | ||
41 | } | ||
42 | @@ -XXX,XX +XXX,XX @@ static void handle_scalar_simd_shri(DisasContext *s, | ||
43 | |||
44 | tcg_temp_free_i64(tcg_rn); | ||
45 | tcg_temp_free_i64(tcg_rd); | ||
46 | - if (round) { | ||
47 | - tcg_temp_free_i64(tcg_round); | ||
48 | - } | ||
35 | } | 49 | } |
36 | 50 | ||
37 | -static void qemu_splitirq(void *opaque, int line, int level) | 51 | /* SHL/SLI - Scalar shift left */ |
38 | -{ | 52 | @@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q, |
39 | - struct IRQState **irq = opaque; | 53 | tcg_final = tcg_const_i64(0); |
40 | - irq[0]->handler(irq[0]->opaque, irq[0]->n, level); | 54 | |
41 | - irq[1]->handler(irq[1]->opaque, irq[1]->n, level); | 55 | if (round) { |
42 | -} | 56 | - uint64_t round_const = 1ULL << (shift - 1); |
43 | - | 57 | - tcg_round = tcg_const_i64(round_const); |
44 | -qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2) | 58 | + tcg_round = tcg_constant_i64(1ULL << (shift - 1)); |
45 | -{ | 59 | } else { |
46 | - qemu_irq *s = g_new0(qemu_irq, 2); | 60 | tcg_round = NULL; |
47 | - s[0] = irq1; | 61 | } |
48 | - s[1] = irq2; | 62 | @@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q, |
49 | - return qemu_allocate_irq(qemu_splitirq, s, 0); | 63 | write_vec_element(s, tcg_final, rd, 1, MO_64); |
50 | -} | 64 | } |
51 | - | 65 | |
52 | void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n) | 66 | - if (round) { |
53 | { | 67 | - tcg_temp_free_i64(tcg_round); |
54 | int i; | 68 | - } |
69 | tcg_temp_free_i64(tcg_rn); | ||
70 | tcg_temp_free_i64(tcg_rd); | ||
71 | tcg_temp_free_i32(tcg_rd_narrowed); | ||
72 | @@ -XXX,XX +XXX,XX @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q, | ||
73 | } | ||
74 | |||
75 | if (size == 3) { | ||
76 | - TCGv_i64 tcg_shift = tcg_const_i64(shift); | ||
77 | + TCGv_i64 tcg_shift = tcg_constant_i64(shift); | ||
78 | static NeonGenTwo64OpEnvFn * const fns[2][2] = { | ||
79 | { gen_helper_neon_qshl_s64, gen_helper_neon_qshlu_s64 }, | ||
80 | { NULL, gen_helper_neon_qshl_u64 }, | ||
81 | @@ -XXX,XX +XXX,XX @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q, | ||
82 | |||
83 | tcg_temp_free_i64(tcg_op); | ||
84 | } | ||
85 | - tcg_temp_free_i64(tcg_shift); | ||
86 | clear_vec_high(s, is_q, rd); | ||
87 | } else { | ||
88 | - TCGv_i32 tcg_shift = tcg_const_i32(shift); | ||
89 | + TCGv_i32 tcg_shift = tcg_constant_i32(shift); | ||
90 | static NeonGenTwoOpEnvFn * const fns[2][2][3] = { | ||
91 | { | ||
92 | { gen_helper_neon_qshl_s8, | ||
93 | @@ -XXX,XX +XXX,XX @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q, | ||
94 | |||
95 | tcg_temp_free_i32(tcg_op); | ||
96 | } | ||
97 | - tcg_temp_free_i32(tcg_shift); | ||
98 | |||
99 | if (!scalar) { | ||
100 | clear_vec_high(s, is_q, rd); | ||
55 | -- | 101 | -- |
56 | 2.25.1 | 102 | 2.25.1 | diff view generated by jsdifflib |
1 | The exynos4210 SoC mostly creates its child devices as if it were | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | board code. This includes the a9mpcore object. Switch that to a | ||
3 | new-style "embedded in the state struct" creation, because in the | ||
4 | next commit we're going to want to refer to the object again further | ||
5 | down in the exynos4210_realize() function. | ||
6 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-20-richard.henderson@linaro.org | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20220404154658.565020-4-peter.maydell@linaro.org | ||
10 | --- | 7 | --- |
11 | include/hw/arm/exynos4210.h | 2 ++ | 8 | target/arm/translate-a64.c | 26 ++++++-------------------- |
12 | hw/arm/exynos4210.c | 11 ++++++----- | 9 | 1 file changed, 6 insertions(+), 20 deletions(-) |
13 | 2 files changed, 8 insertions(+), 5 deletions(-) | ||
14 | 10 | ||
15 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | 11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
16 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/include/hw/arm/exynos4210.h | 13 | --- a/target/arm/translate-a64.c |
18 | +++ b/include/hw/arm/exynos4210.h | 14 | +++ b/target/arm/translate-a64.c |
19 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn, |
20 | 16 | int pass; | |
21 | #include "hw/or-irq.h" | 17 | |
22 | #include "hw/sysbus.h" | 18 | if (fracbits || size == MO_64) { |
23 | +#include "hw/cpu/a9mpcore.h" | 19 | - tcg_shift = tcg_const_i32(fracbits); |
24 | #include "target/arm/cpu-qom.h" | 20 | + tcg_shift = tcg_constant_i32(fracbits); |
25 | #include "qom/object.h" | ||
26 | |||
27 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { | ||
28 | I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; | ||
29 | qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; | ||
30 | qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; | ||
31 | + A9MPPrivState a9mpcore; | ||
32 | }; | ||
33 | |||
34 | #define TYPE_EXYNOS4210_SOC "exynos4210" | ||
35 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/hw/arm/exynos4210.c | ||
38 | +++ b/hw/arm/exynos4210.c | ||
39 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
40 | } | 21 | } |
41 | 22 | ||
42 | /* Private memory region and Internal GIC */ | 23 | if (size == MO_64) { |
43 | - dev = qdev_new(TYPE_A9MPCORE_PRIV); | 24 | @@ -XXX,XX +XXX,XX @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn, |
44 | - qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); | ||
45 | - busdev = SYS_BUS_DEVICE(dev); | ||
46 | - sysbus_realize_and_unref(busdev, &error_fatal); | ||
47 | + qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS); | ||
48 | + busdev = SYS_BUS_DEVICE(&s->a9mpcore); | ||
49 | + sysbus_realize(busdev, &error_fatal); | ||
50 | sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); | ||
51 | for (n = 0; n < EXYNOS4210_NCPUS; n++) { | ||
52 | sysbus_connect_irq(busdev, n, | ||
53 | qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0)); | ||
54 | } | 25 | } |
55 | for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { | 26 | |
56 | - s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n); | 27 | tcg_temp_free_ptr(tcg_fpst); |
57 | + s->irqs.int_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->a9mpcore), n); | 28 | - if (tcg_shift) { |
29 | - tcg_temp_free_i32(tcg_shift); | ||
30 | - } | ||
31 | |||
32 | clear_vec_high(s, elements << size == 16, rd); | ||
33 | } | ||
34 | @@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, | ||
35 | tcg_fpstatus = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); | ||
36 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); | ||
37 | fracbits = (16 << size) - immhb; | ||
38 | - tcg_shift = tcg_const_i32(fracbits); | ||
39 | + tcg_shift = tcg_constant_i32(fracbits); | ||
40 | |||
41 | if (size == MO_64) { | ||
42 | int maxpass = is_scalar ? 1 : 2; | ||
43 | @@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, | ||
44 | } | ||
58 | } | 45 | } |
59 | 46 | ||
60 | /* Cache controller */ | 47 | - tcg_temp_free_i32(tcg_shift); |
61 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj) | 48 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); |
62 | g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i); | 49 | tcg_temp_free_ptr(tcg_fpstatus); |
63 | object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ); | 50 | tcg_temp_free_i32(tcg_rmode); |
64 | } | 51 | @@ -XXX,XX +XXX,XX @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u, |
65 | + | 52 | case 0x1c: /* FCVTAS */ |
66 | + object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); | 53 | case 0x3a: /* FCVTPS */ |
67 | } | 54 | case 0x3b: /* FCVTZS */ |
68 | 55 | - { | |
69 | static void exynos4210_class_init(ObjectClass *klass, void *data) | 56 | - TCGv_i32 tcg_shift = tcg_const_i32(0); |
57 | - gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | ||
58 | - tcg_temp_free_i32(tcg_shift); | ||
59 | + gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_constant_i32(0), tcg_fpstatus); | ||
60 | break; | ||
61 | - } | ||
62 | case 0x5a: /* FCVTNU */ | ||
63 | case 0x5b: /* FCVTMU */ | ||
64 | case 0x5c: /* FCVTAU */ | ||
65 | case 0x7a: /* FCVTPU */ | ||
66 | case 0x7b: /* FCVTZU */ | ||
67 | - { | ||
68 | - TCGv_i32 tcg_shift = tcg_const_i32(0); | ||
69 | - gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | ||
70 | - tcg_temp_free_i32(tcg_shift); | ||
71 | + gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_constant_i32(0), tcg_fpstatus); | ||
72 | break; | ||
73 | - } | ||
74 | case 0x18: /* FRINTN */ | ||
75 | case 0x19: /* FRINTM */ | ||
76 | case 0x38: /* FRINTP */ | ||
77 | @@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, | ||
78 | |||
79 | if (is_double) { | ||
80 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | ||
81 | - TCGv_i64 tcg_zero = tcg_const_i64(0); | ||
82 | + TCGv_i64 tcg_zero = tcg_constant_i64(0); | ||
83 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | ||
84 | NeonGenTwoDoubleOpFn *genfn; | ||
85 | bool swap = false; | ||
86 | @@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, | ||
87 | write_vec_element(s, tcg_res, rd, pass, MO_64); | ||
88 | } | ||
89 | tcg_temp_free_i64(tcg_res); | ||
90 | - tcg_temp_free_i64(tcg_zero); | ||
91 | tcg_temp_free_i64(tcg_op); | ||
92 | |||
93 | clear_vec_high(s, !is_scalar, rd); | ||
94 | } else { | ||
95 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | ||
96 | - TCGv_i32 tcg_zero = tcg_const_i32(0); | ||
97 | + TCGv_i32 tcg_zero = tcg_constant_i32(0); | ||
98 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | ||
99 | NeonGenTwoSingleOpFn *genfn; | ||
100 | bool swap = false; | ||
101 | @@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, | ||
102 | } | ||
103 | } | ||
104 | tcg_temp_free_i32(tcg_res); | ||
105 | - tcg_temp_free_i32(tcg_zero); | ||
106 | tcg_temp_free_i32(tcg_op); | ||
107 | if (!is_scalar) { | ||
108 | clear_vec_high(s, is_q, rd); | ||
70 | -- | 109 | -- |
71 | 2.25.1 | 110 | 2.25.1 | diff view generated by jsdifflib |
1 | The only time we use the ext_gic_irq[] array in the Exynos4210Irq | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | struct is during realize of the SoC -- we initialize it with the | ||
3 | input IRQs of the external GIC device, and then connect those to | ||
4 | outputs of other devices further on in realize (including in the | ||
5 | exynos4210_init_board_irqs() function). Now that the ext_gic object | ||
6 | is easily accessible as s->ext_gic we can make the connections | ||
7 | directly from one device to the other without going via this array. | ||
8 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-21-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20220404154658.565020-10-peter.maydell@linaro.org | ||
12 | --- | 7 | --- |
13 | include/hw/arm/exynos4210.h | 1 - | 8 | target/arm/translate-a64.c | 40 ++++++++++---------------------------- |
14 | hw/arm/exynos4210.c | 12 ++++++------ | 9 | 1 file changed, 10 insertions(+), 30 deletions(-) |
15 | 2 files changed, 6 insertions(+), 7 deletions(-) | ||
16 | 10 | ||
17 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | 11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
18 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/include/hw/arm/exynos4210.h | 13 | --- a/target/arm/translate-a64.c |
20 | +++ b/include/hw/arm/exynos4210.h | 14 | +++ b/target/arm/translate-a64.c |
21 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ static void handle_2misc_narrow(DisasContext *s, bool scalar, |
22 | typedef struct Exynos4210Irq { | 16 | int passes = scalar ? 1 : 2; |
23 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | 17 | |
24 | qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; | 18 | if (scalar) { |
25 | - qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ]; | 19 | - tcg_res[1] = tcg_const_i32(0); |
26 | } Exynos4210Irq; | 20 | + tcg_res[1] = tcg_constant_i32(0); |
27 | 21 | } | |
28 | struct Exynos4210State { | 22 | |
29 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | 23 | for (pass = 0; pass < passes; pass++) { |
30 | index XXXXXXX..XXXXXXX 100644 | 24 | @@ -XXX,XX +XXX,XX @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u, |
31 | --- a/hw/arm/exynos4210.c | 25 | } |
32 | +++ b/hw/arm/exynos4210.c | 26 | |
33 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | 27 | if (is_scalar) { |
34 | { | 28 | - TCGv_i64 tcg_zero = tcg_const_i64(0); |
35 | uint32_t grp, bit, irq_id, n; | 29 | - write_vec_element(s, tcg_zero, rd, 0, MO_64); |
36 | Exynos4210Irq *is = &s->irqs; | 30 | - tcg_temp_free_i64(tcg_zero); |
37 | + DeviceState *extgicdev = DEVICE(&s->ext_gic); | 31 | + write_vec_element(s, tcg_constant_i64(0), rd, 0, MO_64); |
38 | 32 | } | |
39 | for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { | 33 | write_vec_element_i32(s, tcg_rd, rd, pass, MO_32); |
40 | irq_id = 0; | ||
41 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
42 | } | 34 | } |
43 | if (irq_id) { | 35 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) |
44 | s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | 36 | case 0x1c: /* FCVTAS */ |
45 | - is->ext_gic_irq[irq_id - 32]); | 37 | case 0x3a: /* FCVTPS */ |
46 | + qdev_get_gpio_in(extgicdev, | 38 | case 0x3b: /* FCVTZS */ |
47 | + irq_id - 32)); | 39 | - { |
48 | } else { | 40 | - TCGv_i32 tcg_shift = tcg_const_i32(0); |
49 | s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | 41 | - gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); |
50 | is->ext_combiner_irq[n]); | 42 | - tcg_temp_free_i32(tcg_shift); |
51 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | 43 | + gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_constant_i32(0), |
52 | 44 | + tcg_fpstatus); | |
53 | if (irq_id) { | 45 | break; |
54 | s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | 46 | - } |
55 | - is->ext_gic_irq[irq_id - 32]); | 47 | case 0x5a: /* FCVTNU */ |
56 | + qdev_get_gpio_in(extgicdev, | 48 | case 0x5b: /* FCVTMU */ |
57 | + irq_id - 32)); | 49 | case 0x5c: /* FCVTAU */ |
50 | case 0x7a: /* FCVTPU */ | ||
51 | case 0x7b: /* FCVTZU */ | ||
52 | - { | ||
53 | - TCGv_i32 tcg_shift = tcg_const_i32(0); | ||
54 | - gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | ||
55 | - tcg_temp_free_i32(tcg_shift); | ||
56 | + gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_constant_i32(0), | ||
57 | + tcg_fpstatus); | ||
58 | break; | ||
59 | - } | ||
60 | default: | ||
61 | g_assert_not_reached(); | ||
62 | } | ||
63 | @@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q, | ||
64 | read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_64); | ||
65 | |||
66 | if (round) { | ||
67 | - uint64_t round_const = 1ULL << (shift - 1); | ||
68 | - tcg_round = tcg_const_i64(round_const); | ||
69 | + tcg_round = tcg_constant_i64(1ULL << (shift - 1)); | ||
70 | } else { | ||
71 | tcg_round = NULL; | ||
72 | } | ||
73 | @@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q, | ||
74 | } else { | ||
75 | write_vec_element(s, tcg_final, rd, 1, MO_64); | ||
76 | } | ||
77 | - if (round) { | ||
78 | - tcg_temp_free_i64(tcg_round); | ||
79 | - } | ||
80 | tcg_temp_free_i64(tcg_rn); | ||
81 | tcg_temp_free_i64(tcg_rd); | ||
82 | tcg_temp_free_i64(tcg_final); | ||
83 | @@ -XXX,XX +XXX,XX @@ static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u, | ||
58 | } | 84 | } |
59 | } | 85 | } |
60 | } | 86 | if (!is_q) { |
61 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | 87 | - tcg_res[1] = tcg_const_i64(0); |
62 | sysbus_connect_irq(busdev, n, | 88 | + tcg_res[1] = tcg_constant_i64(0); |
63 | qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1)); | ||
64 | } | 89 | } |
65 | - for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { | 90 | for (pass = 0; pass < 2; pass++) { |
66 | - s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->ext_gic), n); | 91 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); |
67 | - } | 92 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) |
68 | 93 | case 0x1c: /* FCVTAS */ | |
69 | /* Internal Interrupt Combiner */ | 94 | case 0x3a: /* FCVTPS */ |
70 | dev = qdev_new("exynos4210.combiner"); | 95 | case 0x3b: /* FCVTZS */ |
71 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | 96 | - { |
72 | busdev = SYS_BUS_DEVICE(dev); | 97 | - TCGv_i32 tcg_shift = tcg_const_i32(0); |
73 | sysbus_realize_and_unref(busdev, &error_fatal); | 98 | gen_helper_vfp_tosls(tcg_res, tcg_op, |
74 | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { | 99 | - tcg_shift, tcg_fpstatus); |
75 | - sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]); | 100 | - tcg_temp_free_i32(tcg_shift); |
76 | + sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n)); | 101 | + tcg_constant_i32(0), tcg_fpstatus); |
77 | } | 102 | break; |
78 | exynos4210_combiner_get_gpioin(&s->irqs, dev, 1); | 103 | - } |
79 | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); | 104 | case 0x5a: /* FCVTNU */ |
105 | case 0x5b: /* FCVTMU */ | ||
106 | case 0x5c: /* FCVTAU */ | ||
107 | case 0x7a: /* FCVTPU */ | ||
108 | case 0x7b: /* FCVTZU */ | ||
109 | - { | ||
110 | - TCGv_i32 tcg_shift = tcg_const_i32(0); | ||
111 | gen_helper_vfp_touls(tcg_res, tcg_op, | ||
112 | - tcg_shift, tcg_fpstatus); | ||
113 | - tcg_temp_free_i32(tcg_shift); | ||
114 | + tcg_constant_i32(0), tcg_fpstatus); | ||
115 | break; | ||
116 | - } | ||
117 | case 0x18: /* FRINTN */ | ||
118 | case 0x19: /* FRINTM */ | ||
119 | case 0x38: /* FRINTP */ | ||
80 | -- | 120 | -- |
81 | 2.25.1 | 121 | 2.25.1 | diff view generated by jsdifflib |
1 | At this point, the function exynos4210_init_board_irqs() splits input | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | IRQ lines to connect them to the input combiner, output combiner and | ||
3 | external GIC. The function exynos4210_combiner_get_gpioin() splits | ||
4 | some of the combiner input lines further to connect them to multiple | ||
5 | different inputs on the combiner. | ||
6 | 2 | ||
7 | Because (unlike qemu_irq_split()) the TYPE_SPLIT_IRQ device has a | 3 | Finish conversion of the file to tcg_constant_*. |
8 | configurable number of outputs, we can do all this in one place, by | ||
9 | making exynos4210_init_board_irqs() add extra outputs to the splitter | ||
10 | device when it must be connected to more than one input on each | ||
11 | combiner. | ||
12 | 4 | ||
13 | We do this with a new data structure, the combinermap, which is an | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
14 | array each of whose elements is a list of the interrupt IDs on the | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
15 | combiner which must be tied together. As we loop through each | 7 | Message-id: 20220426163043.100432-22-richard.henderson@linaro.org |
16 | interrupt ID, if we find that it is the first one in one of these | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | lists, we configure the splitter device with eonugh extra outputs and | 9 | --- |
18 | wire them up to the other interrupt IDs in the list. | 10 | target/arm/translate-a64.c | 20 ++++++++------------ |
11 | 1 file changed, 8 insertions(+), 12 deletions(-) | ||
19 | 12 | ||
20 | Conveniently, for all the cases where this is necessary, the | 13 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
21 | lowest-numbered interrupt ID in each group is in the range of the | ||
22 | external combiner, so we only need to code for this in the first of | ||
23 | the two loops in exynos4210_init_board_irqs(). | ||
24 | |||
25 | The old code in exynos4210_combiner_get_gpioin() which is being | ||
26 | deleted here had several problems which don't exist in the new code | ||
27 | in its handling of the multi-core timer interrupts: | ||
28 | (1) the case labels specified bits 4 ... 8, but bit '8' doesn't | ||
29 | exist; these should have been 4 ... 7 | ||
30 | (2) it used the input irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)] | ||
31 | multiple times as the input of several different splitters, | ||
32 | which isn't allowed | ||
33 | (3) in an apparent cut-and-paste error, the cases for all the | ||
34 | multi-core timer inputs used "bit + 4" even though the | ||
35 | bit range for the case was (intended to be) 4 ... 7, which | ||
36 | meant it was looking at non-existent bits 8 ... 11. | ||
37 | None of these exist in the new code. | ||
38 | |||
39 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
40 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
41 | Message-id: 20220404154658.565020-17-peter.maydell@linaro.org | ||
42 | --- | ||
43 | include/hw/arm/exynos4210.h | 6 +- | ||
44 | hw/arm/exynos4210.c | 178 +++++++++++++++++++++++------------- | ||
45 | 2 files changed, 119 insertions(+), 65 deletions(-) | ||
46 | |||
47 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | ||
48 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
49 | --- a/include/hw/arm/exynos4210.h | 15 | --- a/target/arm/translate-a64.c |
50 | +++ b/include/hw/arm/exynos4210.h | 16 | +++ b/target/arm/translate-a64.c |
51 | @@ -XXX,XX +XXX,XX @@ | 17 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) |
52 | |||
53 | /* | ||
54 | * We need one splitter for every external combiner input, plus | ||
55 | - * one for every non-zero entry in combiner_grp_to_gic_id[]. | ||
56 | + * one for every non-zero entry in combiner_grp_to_gic_id[], | ||
57 | + * minus one for every external combiner ID in second or later | ||
58 | + * places in a combinermap[] line. | ||
59 | * We'll assert in exynos4210_init_board_irqs() if this is wrong. | ||
60 | */ | ||
61 | -#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 54) | ||
62 | +#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38) | ||
63 | |||
64 | typedef struct Exynos4210Irq { | ||
65 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
66 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | ||
68 | --- a/hw/arm/exynos4210.c | ||
69 | +++ b/hw/arm/exynos4210.c | ||
70 | @@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
71 | #define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ | ||
72 | ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) | ||
73 | |||
74 | +/* | ||
75 | + * Some interrupt lines go to multiple combiner inputs. | ||
76 | + * This data structure defines those: each array element is | ||
77 | + * a list of combiner inputs which are connected together; | ||
78 | + * the one with the smallest interrupt ID value must be first. | ||
79 | + * As with combiner_grp_to_gic_id[], we rely on (0, 0) not being | ||
80 | + * wired to anything so we can use 0 as a terminator. | ||
81 | + */ | ||
82 | +#define IRQNO(G, B) EXYNOS4210_COMBINER_GET_IRQ_NUM(G, B) | ||
83 | +#define IRQNONE 0 | ||
84 | + | ||
85 | +#define COMBINERMAP_SIZE 16 | ||
86 | + | ||
87 | +static const int combinermap[COMBINERMAP_SIZE][6] = { | ||
88 | + /* MDNIE_LCD1 */ | ||
89 | + { IRQNO(0, 4), IRQNO(1, 0), IRQNONE }, | ||
90 | + { IRQNO(0, 5), IRQNO(1, 1), IRQNONE }, | ||
91 | + { IRQNO(0, 6), IRQNO(1, 2), IRQNONE }, | ||
92 | + { IRQNO(0, 7), IRQNO(1, 3), IRQNONE }, | ||
93 | + /* TMU */ | ||
94 | + { IRQNO(2, 4), IRQNO(3, 4), IRQNONE }, | ||
95 | + { IRQNO(2, 5), IRQNO(3, 5), IRQNONE }, | ||
96 | + { IRQNO(2, 6), IRQNO(3, 6), IRQNONE }, | ||
97 | + { IRQNO(2, 7), IRQNO(3, 7), IRQNONE }, | ||
98 | + /* LCD1 */ | ||
99 | + { IRQNO(11, 4), IRQNO(12, 0), IRQNONE }, | ||
100 | + { IRQNO(11, 5), IRQNO(12, 1), IRQNONE }, | ||
101 | + { IRQNO(11, 6), IRQNO(12, 2), IRQNONE }, | ||
102 | + { IRQNO(11, 7), IRQNO(12, 3), IRQNONE }, | ||
103 | + /* Multi-core timer */ | ||
104 | + { IRQNO(1, 4), IRQNO(12, 4), IRQNO(35, 4), IRQNO(51, 4), IRQNO(53, 4), IRQNONE }, | ||
105 | + { IRQNO(1, 5), IRQNO(12, 5), IRQNO(35, 5), IRQNO(51, 5), IRQNO(53, 5), IRQNONE }, | ||
106 | + { IRQNO(1, 6), IRQNO(12, 6), IRQNO(35, 6), IRQNO(51, 6), IRQNO(53, 6), IRQNONE }, | ||
107 | + { IRQNO(1, 7), IRQNO(12, 7), IRQNO(35, 7), IRQNO(51, 7), IRQNO(53, 7), IRQNONE }, | ||
108 | +}; | ||
109 | + | ||
110 | +#undef IRQNO | ||
111 | + | ||
112 | +static const int *combinermap_entry(int irq) | ||
113 | +{ | ||
114 | + /* | ||
115 | + * If the interrupt number passed in is the first entry in some | ||
116 | + * line of the combinermap, return a pointer to that line; | ||
117 | + * otherwise return NULL. | ||
118 | + */ | ||
119 | + int i; | ||
120 | + for (i = 0; i < COMBINERMAP_SIZE; i++) { | ||
121 | + if (combinermap[i][0] == irq) { | ||
122 | + return combinermap[i]; | ||
123 | + } | ||
124 | + } | ||
125 | + return NULL; | ||
126 | +} | ||
127 | + | ||
128 | +static int mapline_size(const int *mapline) | ||
129 | +{ | ||
130 | + /* Return number of entries in this mapline in total */ | ||
131 | + int i = 0; | ||
132 | + | ||
133 | + if (!mapline) { | ||
134 | + /* Not in the map? IRQ goes to exactly one combiner input */ | ||
135 | + return 1; | ||
136 | + } | ||
137 | + while (*mapline != IRQNONE) { | ||
138 | + mapline++; | ||
139 | + i++; | ||
140 | + } | ||
141 | + return i; | ||
142 | +} | ||
143 | + | ||
144 | /* | ||
145 | * Initialize board IRQs. | ||
146 | * These IRQs contain splitted Int/External Combiner and External Gic IRQs. | ||
147 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
148 | DeviceState *extgicdev = DEVICE(&s->ext_gic); | ||
149 | int splitcount = 0; | ||
150 | DeviceState *splitter; | ||
151 | + const int *mapline; | ||
152 | + int numlines, splitin, in; | ||
153 | |||
154 | for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { | ||
155 | irq_id = 0; | ||
156 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
157 | irq_id = EXT_GIC_ID_MCT_G1; | ||
158 | } | 18 | } |
159 | 19 | ||
160 | + if (s->irq_table[n]) { | 20 | if (is_scalar) { |
161 | + /* | 21 | - tcg_res[1] = tcg_const_i64(0); |
162 | + * This must be some non-first entry in a combinermap line, | 22 | + tcg_res[1] = tcg_constant_i64(0); |
163 | + * and we've already filled it in. | ||
164 | + */ | ||
165 | + continue; | ||
166 | + } | ||
167 | + mapline = combinermap_entry(n); | ||
168 | + /* | ||
169 | + * We need to connect the IRQ to multiple inputs on both combiners | ||
170 | + * and possibly also to the external GIC. | ||
171 | + */ | ||
172 | + numlines = 2 * mapline_size(mapline); | ||
173 | + if (irq_id) { | ||
174 | + numlines++; | ||
175 | + } | ||
176 | assert(splitcount < EXYNOS4210_NUM_SPLITTERS); | ||
177 | splitter = DEVICE(&s->splitter[splitcount]); | ||
178 | - qdev_prop_set_uint16(splitter, "num-lines", irq_id ? 3 : 2); | ||
179 | + qdev_prop_set_uint16(splitter, "num-lines", numlines); | ||
180 | qdev_realize(splitter, NULL, &error_abort); | ||
181 | splitcount++; | ||
182 | - s->irq_table[n] = qdev_get_gpio_in(splitter, 0); | ||
183 | - qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); | ||
184 | - qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]); | ||
185 | + | ||
186 | + in = n; | ||
187 | + splitin = 0; | ||
188 | + for (;;) { | ||
189 | + s->irq_table[in] = qdev_get_gpio_in(splitter, 0); | ||
190 | + qdev_connect_gpio_out(splitter, splitin, is->int_combiner_irq[in]); | ||
191 | + qdev_connect_gpio_out(splitter, splitin + 1, is->ext_combiner_irq[in]); | ||
192 | + splitin += 2; | ||
193 | + if (!mapline) { | ||
194 | + break; | ||
195 | + } | ||
196 | + mapline++; | ||
197 | + in = *mapline; | ||
198 | + if (in == IRQNONE) { | ||
199 | + break; | ||
200 | + } | ||
201 | + } | ||
202 | if (irq_id) { | ||
203 | - qdev_connect_gpio_out(splitter, 2, | ||
204 | + qdev_connect_gpio_out(splitter, splitin, | ||
205 | qdev_get_gpio_in(extgicdev, irq_id - 32)); | ||
206 | } | 23 | } |
207 | } | 24 | |
208 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | 25 | for (pass = 0; pass < 2; pass++) { |
209 | irq_id = combiner_grp_to_gic_id[grp - | 26 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_four_reg(DisasContext *s, uint32_t insn) |
210 | EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; | 27 | tcg_op2 = tcg_temp_new_i32(); |
211 | 28 | tcg_op3 = tcg_temp_new_i32(); | |
212 | + if (s->irq_table[n]) { | 29 | tcg_res = tcg_temp_new_i32(); |
213 | + /* | 30 | - tcg_zero = tcg_const_i32(0); |
214 | + * This must be some non-first entry in a combinermap line, | 31 | + tcg_zero = tcg_constant_i32(0); |
215 | + * and we've already filled it in. | 32 | |
216 | + */ | 33 | read_vec_element_i32(s, tcg_op1, rn, 3, MO_32); |
217 | + continue; | 34 | read_vec_element_i32(s, tcg_op2, rm, 3, MO_32); |
218 | + } | 35 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_four_reg(DisasContext *s, uint32_t insn) |
219 | + | 36 | tcg_temp_free_i32(tcg_op2); |
220 | if (irq_id) { | 37 | tcg_temp_free_i32(tcg_op3); |
221 | assert(splitcount < EXYNOS4210_NUM_SPLITTERS); | 38 | tcg_temp_free_i32(tcg_res); |
222 | splitter = DEVICE(&s->splitter[splitcount]); | 39 | - tcg_temp_free_i32(tcg_zero); |
223 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, | ||
224 | DeviceState *dev, int ext) | ||
225 | { | ||
226 | int n; | ||
227 | - int bit; | ||
228 | int max; | ||
229 | qemu_irq *irq; | ||
230 | |||
231 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, | ||
232 | EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; | ||
233 | irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq; | ||
234 | |||
235 | - /* | ||
236 | - * Some IRQs of Int/External Combiner are going to two Combiners groups, | ||
237 | - * so let split them. | ||
238 | - */ | ||
239 | for (n = 0; n < max; n++) { | ||
240 | - | ||
241 | - bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); | ||
242 | - | ||
243 | - switch (n) { | ||
244 | - /* MDNIE_LCD1 INTG1 */ | ||
245 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ... | ||
246 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3): | ||
247 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
248 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]); | ||
249 | - continue; | ||
250 | - | ||
251 | - /* TMU INTG3 */ | ||
252 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4): | ||
253 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
254 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]); | ||
255 | - continue; | ||
256 | - | ||
257 | - /* LCD1 INTG12 */ | ||
258 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ... | ||
259 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3): | ||
260 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
261 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]); | ||
262 | - continue; | ||
263 | - | ||
264 | - /* Multi-Core Timer INTG12 */ | ||
265 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ... | ||
266 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8): | ||
267 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
268 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
269 | - continue; | ||
270 | - | ||
271 | - /* Multi-Core Timer INTG35 */ | ||
272 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ... | ||
273 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8): | ||
274 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
275 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
276 | - continue; | ||
277 | - | ||
278 | - /* Multi-Core Timer INTG51 */ | ||
279 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ... | ||
280 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8): | ||
281 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
282 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
283 | - continue; | ||
284 | - | ||
285 | - /* Multi-Core Timer INTG53 */ | ||
286 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ... | ||
287 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8): | ||
288 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
289 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
290 | - continue; | ||
291 | - } | ||
292 | - | ||
293 | irq[n] = qdev_get_gpio_in(dev, n); | ||
294 | } | 40 | } |
295 | } | 41 | } |
42 | |||
43 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | ||
44 | gen_helper_yield(cpu_env); | ||
45 | break; | ||
46 | case DISAS_WFI: | ||
47 | - { | ||
48 | - /* This is a special case because we don't want to just halt the CPU | ||
49 | - * if trying to debug across a WFI. | ||
50 | + /* | ||
51 | + * This is a special case because we don't want to just halt | ||
52 | + * the CPU if trying to debug across a WFI. | ||
53 | */ | ||
54 | - TCGv_i32 tmp = tcg_const_i32(4); | ||
55 | - | ||
56 | gen_a64_set_pc_im(dc->base.pc_next); | ||
57 | - gen_helper_wfi(cpu_env, tmp); | ||
58 | - tcg_temp_free_i32(tmp); | ||
59 | - /* The helper doesn't necessarily throw an exception, but we | ||
60 | + gen_helper_wfi(cpu_env, tcg_constant_i32(4)); | ||
61 | + /* | ||
62 | + * The helper doesn't necessarily throw an exception, but we | ||
63 | * must go back to the main loop to check for interrupts anyway. | ||
64 | */ | ||
65 | tcg_gen_exit_tb(NULL, 0); | ||
66 | break; | ||
67 | } | ||
68 | - } | ||
69 | } | ||
70 | } | ||
71 | |||
296 | -- | 72 | -- |
297 | 2.25.1 | 73 | 2.25.1 | diff view generated by jsdifflib |
1 | Now we have removed the only use of TYPE_EXYNOS4210_IRQ_GATE we can | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | delete the device entirely. | ||
3 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-23-richard.henderson@linaro.org | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> | ||
6 | Message-id: 20220404154658.565020-3-peter.maydell@linaro.org | ||
7 | --- | 7 | --- |
8 | hw/intc/exynos4210_gic.c | 107 --------------------------------------- | 8 | target/arm/translate.c | 32 +++++++------------------------- |
9 | 1 file changed, 107 deletions(-) | 9 | 1 file changed, 7 insertions(+), 25 deletions(-) |
10 | 10 | ||
11 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | 11 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
12 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/intc/exynos4210_gic.c | 13 | --- a/target/arm/translate.c |
14 | +++ b/hw/intc/exynos4210_gic.c | 14 | +++ b/target/arm/translate.c |
15 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_register_types(void) | 15 | @@ -XXX,XX +XXX,XX @@ static void store_sp_checked(DisasContext *s, TCGv_i32 var) |
16 | |||
17 | void gen_set_cpsr(TCGv_i32 var, uint32_t mask) | ||
18 | { | ||
19 | - TCGv_i32 tmp_mask = tcg_const_i32(mask); | ||
20 | - gen_helper_cpsr_write(cpu_env, var, tmp_mask); | ||
21 | - tcg_temp_free_i32(tmp_mask); | ||
22 | + gen_helper_cpsr_write(cpu_env, var, tcg_constant_i32(mask)); | ||
16 | } | 23 | } |
17 | 24 | ||
18 | type_init(exynos4210_gic_register_types) | 25 | static void gen_rebuild_hflags(DisasContext *s, bool new_el) |
26 | @@ -XXX,XX +XXX,XX @@ static void gen_rebuild_hflags(DisasContext *s, bool new_el) | ||
27 | |||
28 | static void gen_exception_internal(int excp) | ||
29 | { | ||
30 | - TCGv_i32 tcg_excp = tcg_const_i32(excp); | ||
19 | - | 31 | - |
20 | -/* IRQ OR Gate struct. | 32 | assert(excp_is_internal(excp)); |
21 | - * | 33 | - gen_helper_exception_internal(cpu_env, tcg_excp); |
22 | - * This device models an OR gate. There are n_in input qdev gpio lines and one | 34 | - tcg_temp_free_i32(tcg_excp); |
23 | - * output sysbus IRQ line. The output IRQ level is formed as OR between all | 35 | + gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp)); |
24 | - * gpio inputs. | 36 | } |
25 | - */ | 37 | |
38 | static void gen_singlestep_exception(DisasContext *s) | ||
39 | @@ -XXX,XX +XXX,XX @@ static inline void gen_smc(DisasContext *s) | ||
40 | /* As with HVC, we may take an exception either before or after | ||
41 | * the insn executes. | ||
42 | */ | ||
43 | - TCGv_i32 tmp; | ||
26 | - | 44 | - |
27 | -#define TYPE_EXYNOS4210_IRQ_GATE "exynos4210.irq_gate" | 45 | gen_set_pc_im(s, s->pc_curr); |
28 | -OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210IRQGateState, EXYNOS4210_IRQ_GATE) | 46 | - tmp = tcg_const_i32(syn_aa32_smc()); |
47 | - gen_helper_pre_smc(cpu_env, tmp); | ||
48 | - tcg_temp_free_i32(tmp); | ||
49 | + gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa32_smc())); | ||
50 | gen_set_pc_im(s, s->base.pc_next); | ||
51 | s->base.is_jmp = DISAS_SMC; | ||
52 | } | ||
53 | @@ -XXX,XX +XXX,XX @@ void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, | ||
54 | |||
55 | static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) | ||
56 | { | ||
57 | - TCGv_i32 tcg_syn; | ||
29 | - | 58 | - |
30 | -struct Exynos4210IRQGateState { | 59 | gen_set_condexec(s); |
31 | - SysBusDevice parent_obj; | 60 | gen_set_pc_im(s, s->pc_curr); |
61 | - tcg_syn = tcg_const_i32(syn); | ||
62 | - gen_helper_exception_bkpt_insn(cpu_env, tcg_syn); | ||
63 | - tcg_temp_free_i32(tcg_syn); | ||
64 | + gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syn)); | ||
65 | s->base.is_jmp = DISAS_NORETURN; | ||
66 | } | ||
67 | |||
68 | @@ -XXX,XX +XXX,XX @@ void unallocated_encoding(DisasContext *s) | ||
69 | static void gen_exception_el(DisasContext *s, int excp, uint32_t syn, | ||
70 | TCGv_i32 tcg_el) | ||
71 | { | ||
72 | - TCGv_i32 tcg_excp; | ||
73 | - TCGv_i32 tcg_syn; | ||
32 | - | 74 | - |
33 | - uint32_t n_in; /* inputs amount */ | 75 | gen_set_condexec(s); |
34 | - uint32_t *level; /* input levels */ | 76 | gen_set_pc_im(s, s->pc_curr); |
35 | - qemu_irq out; /* output IRQ */ | 77 | - tcg_excp = tcg_const_i32(excp); |
36 | -}; | 78 | - tcg_syn = tcg_const_i32(syn); |
37 | - | 79 | - gen_helper_exception_with_syndrome(cpu_env, tcg_excp, tcg_syn, tcg_el); |
38 | -static Property exynos4210_irq_gate_properties[] = { | 80 | - tcg_temp_free_i32(tcg_syn); |
39 | - DEFINE_PROP_UINT32("n_in", Exynos4210IRQGateState, n_in, 1), | 81 | - tcg_temp_free_i32(tcg_excp); |
40 | - DEFINE_PROP_END_OF_LIST(), | 82 | + gen_helper_exception_with_syndrome(cpu_env, |
41 | -}; | 83 | + tcg_constant_i32(excp), |
42 | - | 84 | + tcg_constant_i32(syn), tcg_el); |
43 | -static const VMStateDescription vmstate_exynos4210_irq_gate = { | 85 | s->base.is_jmp = DISAS_NORETURN; |
44 | - .name = "exynos4210.irq_gate", | 86 | } |
45 | - .version_id = 2, | 87 | |
46 | - .minimum_version_id = 2, | ||
47 | - .fields = (VMStateField[]) { | ||
48 | - VMSTATE_VBUFFER_UINT32(level, Exynos4210IRQGateState, 1, NULL, n_in), | ||
49 | - VMSTATE_END_OF_LIST() | ||
50 | - } | ||
51 | -}; | ||
52 | - | ||
53 | -/* Process a change in IRQ input. */ | ||
54 | -static void exynos4210_irq_gate_handler(void *opaque, int irq, int level) | ||
55 | -{ | ||
56 | - Exynos4210IRQGateState *s = (Exynos4210IRQGateState *)opaque; | ||
57 | - uint32_t i; | ||
58 | - | ||
59 | - assert(irq < s->n_in); | ||
60 | - | ||
61 | - s->level[irq] = level; | ||
62 | - | ||
63 | - for (i = 0; i < s->n_in; i++) { | ||
64 | - if (s->level[i] >= 1) { | ||
65 | - qemu_irq_raise(s->out); | ||
66 | - return; | ||
67 | - } | ||
68 | - } | ||
69 | - | ||
70 | - qemu_irq_lower(s->out); | ||
71 | -} | ||
72 | - | ||
73 | -static void exynos4210_irq_gate_reset(DeviceState *d) | ||
74 | -{ | ||
75 | - Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(d); | ||
76 | - | ||
77 | - memset(s->level, 0, s->n_in * sizeof(*s->level)); | ||
78 | -} | ||
79 | - | ||
80 | -/* | ||
81 | - * IRQ Gate initialization. | ||
82 | - */ | ||
83 | -static void exynos4210_irq_gate_init(Object *obj) | ||
84 | -{ | ||
85 | - Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(obj); | ||
86 | - SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
87 | - | ||
88 | - sysbus_init_irq(sbd, &s->out); | ||
89 | -} | ||
90 | - | ||
91 | -static void exynos4210_irq_gate_realize(DeviceState *dev, Error **errp) | ||
92 | -{ | ||
93 | - Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(dev); | ||
94 | - | ||
95 | - /* Allocate general purpose input signals and connect a handler to each of | ||
96 | - * them */ | ||
97 | - qdev_init_gpio_in(dev, exynos4210_irq_gate_handler, s->n_in); | ||
98 | - | ||
99 | - s->level = g_malloc0(s->n_in * sizeof(*s->level)); | ||
100 | -} | ||
101 | - | ||
102 | -static void exynos4210_irq_gate_class_init(ObjectClass *klass, void *data) | ||
103 | -{ | ||
104 | - DeviceClass *dc = DEVICE_CLASS(klass); | ||
105 | - | ||
106 | - dc->reset = exynos4210_irq_gate_reset; | ||
107 | - dc->vmsd = &vmstate_exynos4210_irq_gate; | ||
108 | - device_class_set_props(dc, exynos4210_irq_gate_properties); | ||
109 | - dc->realize = exynos4210_irq_gate_realize; | ||
110 | -} | ||
111 | - | ||
112 | -static const TypeInfo exynos4210_irq_gate_info = { | ||
113 | - .name = TYPE_EXYNOS4210_IRQ_GATE, | ||
114 | - .parent = TYPE_SYS_BUS_DEVICE, | ||
115 | - .instance_size = sizeof(Exynos4210IRQGateState), | ||
116 | - .instance_init = exynos4210_irq_gate_init, | ||
117 | - .class_init = exynos4210_irq_gate_class_init, | ||
118 | -}; | ||
119 | - | ||
120 | -static void exynos4210_irq_gate_register_types(void) | ||
121 | -{ | ||
122 | - type_register_static(&exynos4210_irq_gate_info); | ||
123 | -} | ||
124 | - | ||
125 | -type_init(exynos4210_irq_gate_register_types) | ||
126 | -- | 88 | -- |
127 | 2.25.1 | 89 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-24-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate.c | 25 ++++++++++--------------- | ||
9 | 1 file changed, 10 insertions(+), 15 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate.c | ||
14 | +++ b/target/arm/translate.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) | ||
16 | gen_op_iwmmxt_movq_M0_wRn(wrd); | ||
17 | switch ((insn >> 6) & 3) { | ||
18 | case 0: | ||
19 | - tmp2 = tcg_const_i32(0xff); | ||
20 | - tmp3 = tcg_const_i32((insn & 7) << 3); | ||
21 | + tmp2 = tcg_constant_i32(0xff); | ||
22 | + tmp3 = tcg_constant_i32((insn & 7) << 3); | ||
23 | break; | ||
24 | case 1: | ||
25 | - tmp2 = tcg_const_i32(0xffff); | ||
26 | - tmp3 = tcg_const_i32((insn & 3) << 4); | ||
27 | + tmp2 = tcg_constant_i32(0xffff); | ||
28 | + tmp3 = tcg_constant_i32((insn & 3) << 4); | ||
29 | break; | ||
30 | case 2: | ||
31 | - tmp2 = tcg_const_i32(0xffffffff); | ||
32 | - tmp3 = tcg_const_i32((insn & 1) << 5); | ||
33 | + tmp2 = tcg_constant_i32(0xffffffff); | ||
34 | + tmp3 = tcg_constant_i32((insn & 1) << 5); | ||
35 | break; | ||
36 | default: | ||
37 | - tmp2 = NULL; | ||
38 | - tmp3 = NULL; | ||
39 | + g_assert_not_reached(); | ||
40 | } | ||
41 | gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3); | ||
42 | - tcg_temp_free_i32(tmp3); | ||
43 | - tcg_temp_free_i32(tmp2); | ||
44 | tcg_temp_free_i32(tmp); | ||
45 | gen_op_iwmmxt_movq_wRn_M0(wrd); | ||
46 | gen_op_iwmmxt_set_mup(); | ||
47 | @@ -XXX,XX +XXX,XX @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) | ||
48 | rd0 = (insn >> 16) & 0xf; | ||
49 | rd1 = (insn >> 0) & 0xf; | ||
50 | gen_op_iwmmxt_movq_M0_wRn(rd0); | ||
51 | - tmp = tcg_const_i32((insn >> 20) & 3); | ||
52 | iwmmxt_load_reg(cpu_V1, rd1); | ||
53 | - gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp); | ||
54 | - tcg_temp_free_i32(tmp); | ||
55 | + gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, | ||
56 | + tcg_constant_i32((insn >> 20) & 3)); | ||
57 | gen_op_iwmmxt_movq_wRn_M0(wrd); | ||
58 | gen_op_iwmmxt_set_mup(); | ||
59 | break; | ||
60 | @@ -XXX,XX +XXX,XX @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) | ||
61 | wrd = (insn >> 12) & 0xf; | ||
62 | rd0 = (insn >> 16) & 0xf; | ||
63 | gen_op_iwmmxt_movq_M0_wRn(rd0); | ||
64 | - tmp = tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f)); | ||
65 | + tmp = tcg_constant_i32(((insn >> 16) & 0xf0) | (insn & 0x0f)); | ||
66 | gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp); | ||
67 | - tcg_temp_free_i32(tmp); | ||
68 | gen_op_iwmmxt_movq_wRn_M0(wrd); | ||
69 | gen_op_iwmmxt_set_mup(); | ||
70 | gen_op_iwmmxt_set_cup(); | ||
71 | -- | ||
72 | 2.25.1 | diff view generated by jsdifflib |
1 | In exynos4210_init_board_irqs(), use the TYPE_SPLIT_IRQ device | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | instead of qemu_irq_split(). | ||
3 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-25-richard.henderson@linaro.org | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20220404154658.565020-13-peter.maydell@linaro.org | ||
7 | --- | 7 | --- |
8 | include/hw/arm/exynos4210.h | 9 ++++++++ | 8 | target/arm/translate.c | 22 +++++++++------------- |
9 | hw/arm/exynos4210.c | 41 +++++++++++++++++++++++++++++-------- | 9 | 1 file changed, 9 insertions(+), 13 deletions(-) |
10 | 2 files changed, 42 insertions(+), 8 deletions(-) | ||
11 | 10 | ||
12 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | 11 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
13 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/include/hw/arm/exynos4210.h | 13 | --- a/target/arm/translate.c |
15 | +++ b/include/hw/arm/exynos4210.h | 14 | +++ b/target/arm/translate.c |
16 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, |
17 | #include "hw/sysbus.h" | 16 | tcg_gen_sextract_i32(tcg_el, tcg_el, ctz32(SCR_EEL2), 1); |
18 | #include "hw/cpu/a9mpcore.h" | 17 | tcg_gen_addi_i32(tcg_el, tcg_el, 3); |
19 | #include "hw/intc/exynos4210_gic.h" | 18 | } else { |
20 | +#include "hw/core/split-irq.h" | 19 | - tcg_el = tcg_const_i32(3); |
21 | #include "target/arm/cpu-qom.h" | 20 | + tcg_el = tcg_constant_i32(3); |
22 | #include "qom/object.h" | 21 | } |
23 | 22 | ||
24 | @@ -XXX,XX +XXX,XX @@ | 23 | gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el); |
25 | 24 | @@ -XXX,XX +XXX,XX @@ undef: | |
26 | #define EXYNOS4210_NUM_DMA 3 | 25 | |
27 | 26 | static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn) | |
28 | +/* | 27 | { |
29 | + * We need one splitter for every external combiner input, plus | 28 | - TCGv_i32 tcg_reg, tcg_tgtmode, tcg_regno; |
30 | + * one for every non-zero entry in combiner_grp_to_gic_id[]. | 29 | + TCGv_i32 tcg_reg; |
31 | + * We'll assert in exynos4210_init_board_irqs() if this is wrong. | 30 | int tgtmode = 0, regno = 0; |
32 | + */ | 31 | |
33 | +#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 60) | 32 | if (!msr_banked_access_decode(s, r, sysm, rn, &tgtmode, ®no)) { |
34 | + | 33 | @@ -XXX,XX +XXX,XX @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn) |
35 | typedef struct Exynos4210Irq { | 34 | gen_set_condexec(s); |
36 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | 35 | gen_set_pc_im(s, s->pc_curr); |
37 | qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; | 36 | tcg_reg = load_reg(s, rn); |
38 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { | 37 | - tcg_tgtmode = tcg_const_i32(tgtmode); |
39 | qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; | 38 | - tcg_regno = tcg_const_i32(regno); |
40 | A9MPPrivState a9mpcore; | 39 | - gen_helper_msr_banked(cpu_env, tcg_reg, tcg_tgtmode, tcg_regno); |
41 | Exynos4210GicState ext_gic; | 40 | - tcg_temp_free_i32(tcg_tgtmode); |
42 | + SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS]; | 41 | - tcg_temp_free_i32(tcg_regno); |
43 | }; | 42 | + gen_helper_msr_banked(cpu_env, tcg_reg, |
44 | 43 | + tcg_constant_i32(tgtmode), | |
45 | #define TYPE_EXYNOS4210_SOC "exynos4210" | 44 | + tcg_constant_i32(regno)); |
46 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | 45 | tcg_temp_free_i32(tcg_reg); |
47 | index XXXXXXX..XXXXXXX 100644 | 46 | s->base.is_jmp = DISAS_UPDATE_EXIT; |
48 | --- a/hw/arm/exynos4210.c | ||
49 | +++ b/hw/arm/exynos4210.c | ||
50 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
51 | uint32_t grp, bit, irq_id, n; | ||
52 | Exynos4210Irq *is = &s->irqs; | ||
53 | DeviceState *extgicdev = DEVICE(&s->ext_gic); | ||
54 | + int splitcount = 0; | ||
55 | + DeviceState *splitter; | ||
56 | |||
57 | for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { | ||
58 | irq_id = 0; | ||
59 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
60 | /* MCT_G1 is passed to External and GIC */ | ||
61 | irq_id = EXT_GIC_ID_MCT_G1; | ||
62 | } | ||
63 | + | ||
64 | + assert(splitcount < EXYNOS4210_NUM_SPLITTERS); | ||
65 | + splitter = DEVICE(&s->splitter[splitcount]); | ||
66 | + qdev_prop_set_uint16(splitter, "num-lines", 2); | ||
67 | + qdev_realize(splitter, NULL, &error_abort); | ||
68 | + splitcount++; | ||
69 | + s->irq_table[n] = qdev_get_gpio_in(splitter, 0); | ||
70 | + qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); | ||
71 | if (irq_id) { | ||
72 | - s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
73 | - qdev_get_gpio_in(extgicdev, | ||
74 | - irq_id - 32)); | ||
75 | + qdev_connect_gpio_out(splitter, 1, | ||
76 | + qdev_get_gpio_in(extgicdev, irq_id - 32)); | ||
77 | } else { | ||
78 | - s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
79 | - is->ext_combiner_irq[n]); | ||
80 | + qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]); | ||
81 | } | ||
82 | } | ||
83 | for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { | ||
84 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
85 | EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; | ||
86 | |||
87 | if (irq_id) { | ||
88 | - s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
89 | - qdev_get_gpio_in(extgicdev, | ||
90 | - irq_id - 32)); | ||
91 | + assert(splitcount < EXYNOS4210_NUM_SPLITTERS); | ||
92 | + splitter = DEVICE(&s->splitter[splitcount]); | ||
93 | + qdev_prop_set_uint16(splitter, "num-lines", 2); | ||
94 | + qdev_realize(splitter, NULL, &error_abort); | ||
95 | + splitcount++; | ||
96 | + s->irq_table[n] = qdev_get_gpio_in(splitter, 0); | ||
97 | + qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); | ||
98 | + qdev_connect_gpio_out(splitter, 1, | ||
99 | + qdev_get_gpio_in(extgicdev, irq_id - 32)); | ||
100 | } | ||
101 | } | ||
102 | + /* | ||
103 | + * We check this here to avoid a more obscure assert later when | ||
104 | + * qdev_assert_realized_properly() checks that we realized every | ||
105 | + * child object we initialized. | ||
106 | + */ | ||
107 | + assert(splitcount == EXYNOS4210_NUM_SPLITTERS); | ||
108 | } | 47 | } |
109 | 48 | ||
110 | /* | 49 | static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn) |
111 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj) | 50 | { |
112 | object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ); | 51 | - TCGv_i32 tcg_reg, tcg_tgtmode, tcg_regno; |
113 | } | 52 | + TCGv_i32 tcg_reg; |
114 | 53 | int tgtmode = 0, regno = 0; | |
115 | + for (i = 0; i < ARRAY_SIZE(s->splitter); i++) { | 54 | |
116 | + g_autofree char *name = g_strdup_printf("irq-splitter%d", i); | 55 | if (!msr_banked_access_decode(s, r, sysm, rn, &tgtmode, ®no)) { |
117 | + object_initialize_child(obj, name, &s->splitter[i], TYPE_SPLIT_IRQ); | 56 | @@ -XXX,XX +XXX,XX @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn) |
118 | + } | 57 | gen_set_condexec(s); |
119 | + | 58 | gen_set_pc_im(s, s->pc_curr); |
120 | object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); | 59 | tcg_reg = tcg_temp_new_i32(); |
121 | object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC); | 60 | - tcg_tgtmode = tcg_const_i32(tgtmode); |
61 | - tcg_regno = tcg_const_i32(regno); | ||
62 | - gen_helper_mrs_banked(tcg_reg, cpu_env, tcg_tgtmode, tcg_regno); | ||
63 | - tcg_temp_free_i32(tcg_tgtmode); | ||
64 | - tcg_temp_free_i32(tcg_regno); | ||
65 | + gen_helper_mrs_banked(tcg_reg, cpu_env, | ||
66 | + tcg_constant_i32(tgtmode), | ||
67 | + tcg_constant_i32(regno)); | ||
68 | store_reg(s, rn, tcg_reg); | ||
69 | s->base.is_jmp = DISAS_UPDATE_EXIT; | ||
122 | } | 70 | } |
123 | -- | 71 | -- |
124 | 2.25.1 | 72 | 2.25.1 | diff view generated by jsdifflib |
1 | The function exynos4210_combiner_get_gpioin() currently lives in | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | exynos4210_combiner.c, but it isn't really part of the combiner | ||
3 | device itself -- it is a function that implements the wiring up of | ||
4 | some interrupt sources to multiple combiner inputs. Move it to live | ||
5 | with the other SoC-level code in exynos4210.c, along with a few | ||
6 | macros previously defined in exynos4210.h which are now used only | ||
7 | in exynos4210.c. | ||
8 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-26-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20220404154658.565020-11-peter.maydell@linaro.org | ||
12 | --- | 7 | --- |
13 | include/hw/arm/exynos4210.h | 11 ----- | 8 | target/arm/translate.c | 27 +++++++++------------------ |
14 | hw/arm/exynos4210.c | 82 +++++++++++++++++++++++++++++++++++ | 9 | 1 file changed, 9 insertions(+), 18 deletions(-) |
15 | hw/intc/exynos4210_combiner.c | 77 -------------------------------- | ||
16 | 3 files changed, 82 insertions(+), 88 deletions(-) | ||
17 | 10 | ||
18 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | 11 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
19 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/include/hw/arm/exynos4210.h | 13 | --- a/target/arm/translate.c |
21 | +++ b/include/hw/arm/exynos4210.h | 14 | +++ b/target/arm/translate.c |
22 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
23 | #define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \ | 16 | } \ |
24 | (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8) | 17 | static void gen_##NAME##0_vec(unsigned vece, TCGv_vec d, TCGv_vec a) \ |
25 | 18 | { \ | |
26 | -#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp)*8 + (bit)) | 19 | - TCGv_vec zero = tcg_const_zeros_vec_matching(d); \ |
27 | -#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8) | 20 | + TCGv_vec zero = tcg_constant_vec_matching(d, vece, 0); \ |
28 | -#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ | 21 | tcg_gen_cmp_vec(COND, vece, d, a, zero); \ |
29 | - ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) | 22 | - tcg_temp_free_vec(zero); \ |
30 | - | 23 | } \ |
31 | /* IRQs number for external and internal GIC */ | 24 | void gen_gvec_##NAME##0(unsigned vece, uint32_t d, uint32_t m, \ |
32 | #define EXYNOS4210_EXT_GIC_NIRQ (160-32) | 25 | uint32_t opr_sz, uint32_t max_sz) \ |
33 | #define EXYNOS4210_INT_GIC_NIRQ 64 | 26 | @@ -XXX,XX +XXX,XX @@ void gen_ushl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift) |
34 | @@ -XXX,XX +XXX,XX @@ void exynos4210_write_secondary(ARMCPU *cpu, | 27 | TCGv_i32 rval = tcg_temp_new_i32(); |
35 | * bit - bit number inside group */ | 28 | TCGv_i32 lsh = tcg_temp_new_i32(); |
36 | uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit); | 29 | TCGv_i32 rsh = tcg_temp_new_i32(); |
37 | 30 | - TCGv_i32 zero = tcg_const_i32(0); | |
38 | -/* | 31 | - TCGv_i32 max = tcg_const_i32(32); |
39 | - * Get Combiner input GPIO into irqs structure | 32 | + TCGv_i32 zero = tcg_constant_i32(0); |
40 | - */ | 33 | + TCGv_i32 max = tcg_constant_i32(32); |
41 | -void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev, | 34 | |
42 | - int ext); | 35 | /* |
43 | - | 36 | * Rely on the TCG guarantee that out of range shifts produce |
44 | /* | 37 | @@ -XXX,XX +XXX,XX @@ void gen_ushl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift) |
45 | * exynos4210 UART | 38 | tcg_temp_free_i32(rval); |
46 | */ | 39 | tcg_temp_free_i32(lsh); |
47 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | 40 | tcg_temp_free_i32(rsh); |
48 | index XXXXXXX..XXXXXXX 100644 | 41 | - tcg_temp_free_i32(zero); |
49 | --- a/hw/arm/exynos4210.c | 42 | - tcg_temp_free_i32(max); |
50 | +++ b/hw/arm/exynos4210.c | ||
51 | @@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
52 | { }, { }, { }, { }, { }, { }, { }, { }, { }, { } | ||
53 | }; | ||
54 | |||
55 | +#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp) * 8 + (bit)) | ||
56 | +#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8) | ||
57 | +#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ | ||
58 | + ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) | ||
59 | + | ||
60 | /* | ||
61 | * Initialize board IRQs. | ||
62 | * These IRQs contain splitted Int/External Combiner and External Gic IRQs. | ||
63 | @@ -XXX,XX +XXX,XX @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) | ||
64 | return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); | ||
65 | } | 43 | } |
66 | 44 | ||
67 | +/* | 45 | void gen_ushl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift) |
68 | + * Get Combiner input GPIO into irqs structure | 46 | @@ -XXX,XX +XXX,XX @@ void gen_ushl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift) |
69 | + */ | 47 | TCGv_i64 rval = tcg_temp_new_i64(); |
70 | +static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, | 48 | TCGv_i64 lsh = tcg_temp_new_i64(); |
71 | + DeviceState *dev, int ext) | 49 | TCGv_i64 rsh = tcg_temp_new_i64(); |
72 | +{ | 50 | - TCGv_i64 zero = tcg_const_i64(0); |
73 | + int n; | 51 | - TCGv_i64 max = tcg_const_i64(64); |
74 | + int bit; | 52 | + TCGv_i64 zero = tcg_constant_i64(0); |
75 | + int max; | 53 | + TCGv_i64 max = tcg_constant_i64(64); |
76 | + qemu_irq *irq; | 54 | |
77 | + | 55 | /* |
78 | + max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ : | 56 | * Rely on the TCG guarantee that out of range shifts produce |
79 | + EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; | 57 | @@ -XXX,XX +XXX,XX @@ void gen_ushl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift) |
80 | + irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq; | 58 | tcg_temp_free_i64(rval); |
81 | + | 59 | tcg_temp_free_i64(lsh); |
82 | + /* | 60 | tcg_temp_free_i64(rsh); |
83 | + * Some IRQs of Int/External Combiner are going to two Combiners groups, | 61 | - tcg_temp_free_i64(zero); |
84 | + * so let split them. | 62 | - tcg_temp_free_i64(max); |
85 | + */ | 63 | } |
86 | + for (n = 0; n < max; n++) { | 64 | |
87 | + | 65 | static void gen_ushl_vec(unsigned vece, TCGv_vec dst, |
88 | + bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); | 66 | @@ -XXX,XX +XXX,XX @@ void gen_sshl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift) |
89 | + | 67 | TCGv_i32 rval = tcg_temp_new_i32(); |
90 | + switch (n) { | 68 | TCGv_i32 lsh = tcg_temp_new_i32(); |
91 | + /* MDNIE_LCD1 INTG1 */ | 69 | TCGv_i32 rsh = tcg_temp_new_i32(); |
92 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ... | 70 | - TCGv_i32 zero = tcg_const_i32(0); |
93 | + EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3): | 71 | - TCGv_i32 max = tcg_const_i32(31); |
94 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | 72 | + TCGv_i32 zero = tcg_constant_i32(0); |
95 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]); | 73 | + TCGv_i32 max = tcg_constant_i32(31); |
96 | + continue; | 74 | |
97 | + | 75 | /* |
98 | + /* TMU INTG3 */ | 76 | * Rely on the TCG guarantee that out of range shifts produce |
99 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4): | 77 | @@ -XXX,XX +XXX,XX @@ void gen_sshl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift) |
100 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | 78 | tcg_temp_free_i32(rval); |
101 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]); | 79 | tcg_temp_free_i32(lsh); |
102 | + continue; | 80 | tcg_temp_free_i32(rsh); |
103 | + | 81 | - tcg_temp_free_i32(zero); |
104 | + /* LCD1 INTG12 */ | 82 | - tcg_temp_free_i32(max); |
105 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ... | 83 | } |
106 | + EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3): | 84 | |
107 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | 85 | void gen_sshl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift) |
108 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]); | 86 | @@ -XXX,XX +XXX,XX @@ void gen_sshl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift) |
109 | + continue; | 87 | TCGv_i64 rval = tcg_temp_new_i64(); |
110 | + | 88 | TCGv_i64 lsh = tcg_temp_new_i64(); |
111 | + /* Multi-Core Timer INTG12 */ | 89 | TCGv_i64 rsh = tcg_temp_new_i64(); |
112 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ... | 90 | - TCGv_i64 zero = tcg_const_i64(0); |
113 | + EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8): | 91 | - TCGv_i64 max = tcg_const_i64(63); |
114 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | 92 | + TCGv_i64 zero = tcg_constant_i64(0); |
115 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | 93 | + TCGv_i64 max = tcg_constant_i64(63); |
116 | + continue; | 94 | |
117 | + | 95 | /* |
118 | + /* Multi-Core Timer INTG35 */ | 96 | * Rely on the TCG guarantee that out of range shifts produce |
119 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ... | 97 | @@ -XXX,XX +XXX,XX @@ void gen_sshl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift) |
120 | + EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8): | 98 | tcg_temp_free_i64(rval); |
121 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | 99 | tcg_temp_free_i64(lsh); |
122 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | 100 | tcg_temp_free_i64(rsh); |
123 | + continue; | 101 | - tcg_temp_free_i64(zero); |
124 | + | 102 | - tcg_temp_free_i64(max); |
125 | + /* Multi-Core Timer INTG51 */ | 103 | } |
126 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ... | 104 | |
127 | + EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8): | 105 | static void gen_sshl_vec(unsigned vece, TCGv_vec dst, |
128 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
129 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
130 | + continue; | ||
131 | + | ||
132 | + /* Multi-Core Timer INTG53 */ | ||
133 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ... | ||
134 | + EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8): | ||
135 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
136 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
137 | + continue; | ||
138 | + } | ||
139 | + | ||
140 | + irq[n] = qdev_get_gpio_in(dev, n); | ||
141 | + } | ||
142 | +} | ||
143 | + | ||
144 | static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, | ||
145 | 0x09, 0x00, 0x00, 0x00 }; | ||
146 | |||
147 | diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c | ||
148 | index XXXXXXX..XXXXXXX 100644 | ||
149 | --- a/hw/intc/exynos4210_combiner.c | ||
150 | +++ b/hw/intc/exynos4210_combiner.c | ||
151 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_exynos4210_combiner = { | ||
152 | } | ||
153 | }; | ||
154 | |||
155 | -/* | ||
156 | - * Get Combiner input GPIO into irqs structure | ||
157 | - */ | ||
158 | -void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev, | ||
159 | - int ext) | ||
160 | -{ | ||
161 | - int n; | ||
162 | - int bit; | ||
163 | - int max; | ||
164 | - qemu_irq *irq; | ||
165 | - | ||
166 | - max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ : | ||
167 | - EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; | ||
168 | - irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq; | ||
169 | - | ||
170 | - /* | ||
171 | - * Some IRQs of Int/External Combiner are going to two Combiners groups, | ||
172 | - * so let split them. | ||
173 | - */ | ||
174 | - for (n = 0; n < max; n++) { | ||
175 | - | ||
176 | - bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); | ||
177 | - | ||
178 | - switch (n) { | ||
179 | - /* MDNIE_LCD1 INTG1 */ | ||
180 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ... | ||
181 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3): | ||
182 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
183 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]); | ||
184 | - continue; | ||
185 | - | ||
186 | - /* TMU INTG3 */ | ||
187 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4): | ||
188 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
189 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]); | ||
190 | - continue; | ||
191 | - | ||
192 | - /* LCD1 INTG12 */ | ||
193 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ... | ||
194 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3): | ||
195 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
196 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]); | ||
197 | - continue; | ||
198 | - | ||
199 | - /* Multi-Core Timer INTG12 */ | ||
200 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ... | ||
201 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8): | ||
202 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
203 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
204 | - continue; | ||
205 | - | ||
206 | - /* Multi-Core Timer INTG35 */ | ||
207 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ... | ||
208 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8): | ||
209 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
210 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
211 | - continue; | ||
212 | - | ||
213 | - /* Multi-Core Timer INTG51 */ | ||
214 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ... | ||
215 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8): | ||
216 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
217 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
218 | - continue; | ||
219 | - | ||
220 | - /* Multi-Core Timer INTG53 */ | ||
221 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ... | ||
222 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8): | ||
223 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
224 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
225 | - continue; | ||
226 | - } | ||
227 | - | ||
228 | - irq[n] = qdev_get_gpio_in(dev, n); | ||
229 | - } | ||
230 | -} | ||
231 | - | ||
232 | static uint64_t | ||
233 | exynos4210_combiner_read(void *opaque, hwaddr offset, unsigned size) | ||
234 | { | ||
235 | -- | 106 | -- |
236 | 2.25.1 | 107 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-27-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate.c | 43 +++++++++++++----------------------------- | ||
9 | 1 file changed, 13 insertions(+), 30 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate.c | ||
14 | +++ b/target/arm/translate.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, | ||
16 | * Note that on XScale all cp0..c13 registers do an access check | ||
17 | * call in order to handle c15_cpar. | ||
18 | */ | ||
19 | - TCGv_ptr tmpptr; | ||
20 | - TCGv_i32 tcg_syn, tcg_isread; | ||
21 | uint32_t syndrome; | ||
22 | |||
23 | /* Note that since we are an implementation which takes an | ||
24 | @@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, | ||
25 | |||
26 | gen_set_condexec(s); | ||
27 | gen_set_pc_im(s, s->pc_curr); | ||
28 | - tmpptr = tcg_const_ptr(ri); | ||
29 | - tcg_syn = tcg_const_i32(syndrome); | ||
30 | - tcg_isread = tcg_const_i32(isread); | ||
31 | - gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn, | ||
32 | - tcg_isread); | ||
33 | - tcg_temp_free_ptr(tmpptr); | ||
34 | - tcg_temp_free_i32(tcg_syn); | ||
35 | - tcg_temp_free_i32(tcg_isread); | ||
36 | + gen_helper_access_check_cp_reg(cpu_env, | ||
37 | + tcg_constant_ptr(ri), | ||
38 | + tcg_constant_i32(syndrome), | ||
39 | + tcg_constant_i32(isread)); | ||
40 | } else if (ri->type & ARM_CP_RAISES_EXC) { | ||
41 | /* | ||
42 | * The readfn or writefn might raise an exception; | ||
43 | @@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, | ||
44 | TCGv_i64 tmp64; | ||
45 | TCGv_i32 tmp; | ||
46 | if (ri->type & ARM_CP_CONST) { | ||
47 | - tmp64 = tcg_const_i64(ri->resetvalue); | ||
48 | + tmp64 = tcg_constant_i64(ri->resetvalue); | ||
49 | } else if (ri->readfn) { | ||
50 | - TCGv_ptr tmpptr; | ||
51 | tmp64 = tcg_temp_new_i64(); | ||
52 | - tmpptr = tcg_const_ptr(ri); | ||
53 | - gen_helper_get_cp_reg64(tmp64, cpu_env, tmpptr); | ||
54 | - tcg_temp_free_ptr(tmpptr); | ||
55 | + gen_helper_get_cp_reg64(tmp64, cpu_env, | ||
56 | + tcg_constant_ptr(ri)); | ||
57 | } else { | ||
58 | tmp64 = tcg_temp_new_i64(); | ||
59 | tcg_gen_ld_i64(tmp64, cpu_env, ri->fieldoffset); | ||
60 | @@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, | ||
61 | } else { | ||
62 | TCGv_i32 tmp; | ||
63 | if (ri->type & ARM_CP_CONST) { | ||
64 | - tmp = tcg_const_i32(ri->resetvalue); | ||
65 | + tmp = tcg_constant_i32(ri->resetvalue); | ||
66 | } else if (ri->readfn) { | ||
67 | - TCGv_ptr tmpptr; | ||
68 | tmp = tcg_temp_new_i32(); | ||
69 | - tmpptr = tcg_const_ptr(ri); | ||
70 | - gen_helper_get_cp_reg(tmp, cpu_env, tmpptr); | ||
71 | - tcg_temp_free_ptr(tmpptr); | ||
72 | + gen_helper_get_cp_reg(tmp, cpu_env, tcg_constant_ptr(ri)); | ||
73 | } else { | ||
74 | tmp = load_cpu_offset(ri->fieldoffset); | ||
75 | } | ||
76 | @@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, | ||
77 | tcg_temp_free_i32(tmplo); | ||
78 | tcg_temp_free_i32(tmphi); | ||
79 | if (ri->writefn) { | ||
80 | - TCGv_ptr tmpptr = tcg_const_ptr(ri); | ||
81 | - gen_helper_set_cp_reg64(cpu_env, tmpptr, tmp64); | ||
82 | - tcg_temp_free_ptr(tmpptr); | ||
83 | + gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri), | ||
84 | + tmp64); | ||
85 | } else { | ||
86 | tcg_gen_st_i64(tmp64, cpu_env, ri->fieldoffset); | ||
87 | } | ||
88 | tcg_temp_free_i64(tmp64); | ||
89 | } else { | ||
90 | + TCGv_i32 tmp = load_reg(s, rt); | ||
91 | if (ri->writefn) { | ||
92 | - TCGv_i32 tmp; | ||
93 | - TCGv_ptr tmpptr; | ||
94 | - tmp = load_reg(s, rt); | ||
95 | - tmpptr = tcg_const_ptr(ri); | ||
96 | - gen_helper_set_cp_reg(cpu_env, tmpptr, tmp); | ||
97 | - tcg_temp_free_ptr(tmpptr); | ||
98 | + gen_helper_set_cp_reg(cpu_env, tcg_constant_ptr(ri), tmp); | ||
99 | tcg_temp_free_i32(tmp); | ||
100 | } else { | ||
101 | - TCGv_i32 tmp = load_reg(s, rt); | ||
102 | store_cpu_offset(tmp, ri->fieldoffset, 4); | ||
103 | } | ||
104 | } | ||
105 | -- | ||
106 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-28-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate.c | 8 ++------ | ||
9 | 1 file changed, 2 insertions(+), 6 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate.c | ||
14 | +++ b/target/arm/translate.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s, | ||
16 | } | ||
17 | |||
18 | addr = tcg_temp_new_i32(); | ||
19 | - tmp = tcg_const_i32(mode); | ||
20 | /* get_r13_banked() will raise an exception if called from System mode */ | ||
21 | gen_set_condexec(s); | ||
22 | gen_set_pc_im(s, s->pc_curr); | ||
23 | - gen_helper_get_r13_banked(addr, cpu_env, tmp); | ||
24 | - tcg_temp_free_i32(tmp); | ||
25 | + gen_helper_get_r13_banked(addr, cpu_env, tcg_constant_i32(mode)); | ||
26 | switch (amode) { | ||
27 | case 0: /* DA */ | ||
28 | offset = -4; | ||
29 | @@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s, | ||
30 | abort(); | ||
31 | } | ||
32 | tcg_gen_addi_i32(addr, addr, offset); | ||
33 | - tmp = tcg_const_i32(mode); | ||
34 | - gen_helper_set_r13_banked(cpu_env, tmp, addr); | ||
35 | - tcg_temp_free_i32(tmp); | ||
36 | + gen_helper_set_r13_banked(cpu_env, tcg_constant_i32(mode), addr); | ||
37 | } | ||
38 | tcg_temp_free_i32(addr); | ||
39 | s->base.is_jmp = DISAS_UPDATE_EXIT; | ||
40 | -- | ||
41 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-29-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate.c | 11 +++++------ | ||
9 | 1 file changed, 5 insertions(+), 6 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate.c | ||
14 | +++ b/target/arm/translate.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static bool op_s_rri_rot(DisasContext *s, arg_s_rri_rot *a, | ||
16 | void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32), | ||
17 | int logic_cc, StoreRegKind kind) | ||
18 | { | ||
19 | - TCGv_i32 tmp1, tmp2; | ||
20 | + TCGv_i32 tmp1; | ||
21 | uint32_t imm; | ||
22 | |||
23 | imm = ror32(a->imm, a->rot); | ||
24 | if (logic_cc && a->rot) { | ||
25 | tcg_gen_movi_i32(cpu_CF, imm >> 31); | ||
26 | } | ||
27 | - tmp2 = tcg_const_i32(imm); | ||
28 | tmp1 = load_reg(s, a->rn); | ||
29 | |||
30 | - gen(tmp1, tmp1, tmp2); | ||
31 | - tcg_temp_free_i32(tmp2); | ||
32 | + gen(tmp1, tmp1, tcg_constant_i32(imm)); | ||
33 | |||
34 | if (logic_cc) { | ||
35 | gen_logic_CC(tmp1); | ||
36 | @@ -XXX,XX +XXX,XX @@ static bool op_s_rxi_rot(DisasContext *s, arg_s_rri_rot *a, | ||
37 | if (logic_cc && a->rot) { | ||
38 | tcg_gen_movi_i32(cpu_CF, imm >> 31); | ||
39 | } | ||
40 | - tmp = tcg_const_i32(imm); | ||
41 | |||
42 | - gen(tmp, tmp); | ||
43 | + tmp = tcg_temp_new_i32(); | ||
44 | + gen(tmp, tcg_constant_i32(imm)); | ||
45 | + | ||
46 | if (logic_cc) { | ||
47 | gen_logic_CC(tmp); | ||
48 | } | ||
49 | -- | ||
50 | 2.25.1 | diff view generated by jsdifflib |
1 | From: "Edgar E. Iglesias" <edgar.iglesias@amd.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Create an APU CPU Cluster. This is in preparation to add the RPU. | 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
4 | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | |
5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> | 5 | Message-id: 20220426163043.100432-30-richard.henderson@linaro.org |
6 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | ||
7 | Message-id: 20220406174303.2022038-2-edgar.iglesias@xilinx.com | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 7 | --- |
10 | include/hw/arm/xlnx-versal.h | 2 ++ | 8 | target/arm/translate.c | 11 +++-------- |
11 | hw/arm/xlnx-versal.c | 9 ++++++++- | 9 | 1 file changed, 3 insertions(+), 8 deletions(-) |
12 | 2 files changed, 10 insertions(+), 1 deletion(-) | ||
13 | 10 | ||
14 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h | 11 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
15 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/include/hw/arm/xlnx-versal.h | 13 | --- a/target/arm/translate.c |
17 | +++ b/include/hw/arm/xlnx-versal.h | 14 | +++ b/target/arm/translate.c |
18 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ static bool trans_ADR(DisasContext *s, arg_ri *a) |
19 | 16 | ||
20 | #include "hw/sysbus.h" | 17 | static bool trans_MOVW(DisasContext *s, arg_MOVW *a) |
21 | #include "hw/arm/boot.h" | ||
22 | +#include "hw/cpu/cluster.h" | ||
23 | #include "hw/or-irq.h" | ||
24 | #include "hw/sd/sdhci.h" | ||
25 | #include "hw/intc/arm_gicv3.h" | ||
26 | @@ -XXX,XX +XXX,XX @@ struct Versal { | ||
27 | struct { | ||
28 | struct { | ||
29 | MemoryRegion mr; | ||
30 | + CPUClusterState cluster; | ||
31 | ARMCPU cpu[XLNX_VERSAL_NR_ACPUS]; | ||
32 | GICv3State gic; | ||
33 | } apu; | ||
34 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/hw/arm/xlnx-versal.c | ||
37 | +++ b/hw/arm/xlnx-versal.c | ||
38 | @@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s) | ||
39 | { | 18 | { |
40 | int i; | 19 | - TCGv_i32 tmp; |
41 | 20 | - | |
42 | + object_initialize_child(OBJECT(s), "apu-cluster", &s->fpd.apu.cluster, | 21 | if (!ENABLE_ARCH_6T2) { |
43 | + TYPE_CPU_CLUSTER); | 22 | return false; |
44 | + qdev_prop_set_uint32(DEVICE(&s->fpd.apu.cluster), "cluster-id", 0); | ||
45 | + | ||
46 | for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) { | ||
47 | Object *obj; | ||
48 | |||
49 | - object_initialize_child(OBJECT(s), "apu-cpu[*]", &s->fpd.apu.cpu[i], | ||
50 | + object_initialize_child(OBJECT(&s->fpd.apu.cluster), | ||
51 | + "apu-cpu[*]", &s->fpd.apu.cpu[i], | ||
52 | XLNX_VERSAL_ACPU_TYPE); | ||
53 | obj = OBJECT(&s->fpd.apu.cpu[i]); | ||
54 | if (i) { | ||
55 | @@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s) | ||
56 | &error_abort); | ||
57 | qdev_realize(DEVICE(obj), NULL, &error_fatal); | ||
58 | } | 23 | } |
59 | + | 24 | |
60 | + qdev_realize(DEVICE(&s->fpd.apu.cluster), NULL, &error_fatal); | 25 | - tmp = tcg_const_i32(a->imm); |
26 | - store_reg(s, a->rd, tmp); | ||
27 | + store_reg(s, a->rd, tcg_constant_i32(a->imm)); | ||
28 | return true; | ||
61 | } | 29 | } |
62 | 30 | ||
63 | static void versal_create_apu_gic(Versal *s, qemu_irq *pic) | 31 | @@ -XXX,XX +XXX,XX @@ static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a) |
32 | t0 = load_reg(s, a->rm); | ||
33 | t1 = load_reg(s, a->rn); | ||
34 | tcg_gen_mulu2_i32(t0, t1, t0, t1); | ||
35 | - zero = tcg_const_i32(0); | ||
36 | + zero = tcg_constant_i32(0); | ||
37 | t2 = load_reg(s, a->ra); | ||
38 | tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero); | ||
39 | tcg_temp_free_i32(t2); | ||
40 | t2 = load_reg(s, a->rd); | ||
41 | tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero); | ||
42 | tcg_temp_free_i32(t2); | ||
43 | - tcg_temp_free_i32(zero); | ||
44 | store_reg(s, a->ra, t0); | ||
45 | store_reg(s, a->rd, t1); | ||
46 | return true; | ||
47 | @@ -XXX,XX +XXX,XX @@ static bool op_crc32(DisasContext *s, arg_rrr *a, bool c, MemOp sz) | ||
48 | default: | ||
49 | g_assert_not_reached(); | ||
50 | } | ||
51 | - t3 = tcg_const_i32(1 << sz); | ||
52 | + t3 = tcg_constant_i32(1 << sz); | ||
53 | if (c) { | ||
54 | gen_helper_crc32c(t1, t1, t2, t3); | ||
55 | } else { | ||
56 | gen_helper_crc32(t1, t1, t2, t3); | ||
57 | } | ||
58 | tcg_temp_free_i32(t2); | ||
59 | - tcg_temp_free_i32(t3); | ||
60 | store_reg(s, a->rd, t1); | ||
61 | return true; | ||
62 | } | ||
64 | -- | 63 | -- |
65 | 2.25.1 | 64 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-31-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate.c | 7 +++---- | ||
9 | 1 file changed, 3 insertions(+), 4 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate.c | ||
14 | +++ b/target/arm/translate.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a) | ||
16 | if (!arm_dc_feature(s, ARM_FEATURE_M)) { | ||
17 | return false; | ||
18 | } | ||
19 | - tmp = tcg_const_i32(a->sysm); | ||
20 | - gen_helper_v7m_mrs(tmp, cpu_env, tmp); | ||
21 | + tmp = tcg_temp_new_i32(); | ||
22 | + gen_helper_v7m_mrs(tmp, cpu_env, tcg_constant_i32(a->sysm)); | ||
23 | store_reg(s, a->rd, tmp); | ||
24 | return true; | ||
25 | } | ||
26 | @@ -XXX,XX +XXX,XX @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a) | ||
27 | if (!arm_dc_feature(s, ARM_FEATURE_M)) { | ||
28 | return false; | ||
29 | } | ||
30 | - addr = tcg_const_i32((a->mask << 10) | a->sysm); | ||
31 | + addr = tcg_constant_i32((a->mask << 10) | a->sysm); | ||
32 | reg = load_reg(s, a->rn); | ||
33 | gen_helper_v7m_msr(cpu_env, addr, reg); | ||
34 | - tcg_temp_free_i32(addr); | ||
35 | tcg_temp_free_i32(reg); | ||
36 | /* If we wrote to CONTROL, the EL might have changed */ | ||
37 | gen_rebuild_hflags(s, true); | ||
38 | -- | ||
39 | 2.25.1 | diff view generated by jsdifflib |
1 | The combiner_grp_to_gic_id[] array includes the EXT_GIC_ID_MCT_G0 | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | and EXT_GIC_ID_MCT_G1 multiple times. This means that we will | ||
3 | connect multiple IRQs up to the same external GIC input, which | ||
4 | is not permitted. We do the same thing in the code in | ||
5 | exynos4210_init_board_irqs() because the conditionals selecting | ||
6 | an irq_id in the first loop match multiple interrupt IDs. | ||
7 | 2 | ||
8 | Overall we do this for interrupt IDs | 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | (1, 4), (12, 4), (35, 4), (51, 4), (53, 4) for EXT_GIC_ID_MCT_G0 | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | and | 5 | Message-id: 20220426163043.100432-32-richard.henderson@linaro.org |
11 | (1, 5), (12, 5), (35, 5), (51, 5), (53, 5) for EXT_GIC_ID_MCT_G1 | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | ||
8 | target/arm/translate.c | 14 +++++--------- | ||
9 | 1 file changed, 5 insertions(+), 9 deletions(-) | ||
12 | 10 | ||
13 | These correspond to the cases for the multi-core timer that we are | 11 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
14 | wiring up to multiple inputs on the combiner in | ||
15 | exynos4210_combiner_get_gpioin(). That code already deals with all | ||
16 | these interrupt IDs being the same input source, so we don't need to | ||
17 | connect the external GIC interrupt for any of them except the first | ||
18 | (1, 4) and (1, 5). Remove the array entries and conditionals which | ||
19 | were incorrectly causing us to wire up extra lines. | ||
20 | |||
21 | This bug didn't cause any visible effects, because we only connect | ||
22 | up a device to the "primary" ID values (1, 4) and (1, 5), so the | ||
23 | extra lines would never be set to a level. | ||
24 | |||
25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
26 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
27 | Message-id: 20220404154658.565020-16-peter.maydell@linaro.org | ||
28 | --- | ||
29 | include/hw/arm/exynos4210.h | 2 +- | ||
30 | hw/arm/exynos4210.c | 12 +++++------- | ||
31 | 2 files changed, 6 insertions(+), 8 deletions(-) | ||
32 | |||
33 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | ||
34 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
35 | --- a/include/hw/arm/exynos4210.h | 13 | --- a/target/arm/translate.c |
36 | +++ b/include/hw/arm/exynos4210.h | 14 | +++ b/target/arm/translate.c |
37 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ static bool trans_TT(DisasContext *s, arg_TT *a) |
38 | * one for every non-zero entry in combiner_grp_to_gic_id[]. | 16 | } |
39 | * We'll assert in exynos4210_init_board_irqs() if this is wrong. | 17 | |
40 | */ | 18 | addr = load_reg(s, a->rn); |
41 | -#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 60) | 19 | - tmp = tcg_const_i32((a->A << 1) | a->T); |
42 | +#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 54) | 20 | - gen_helper_v7m_tt(tmp, cpu_env, addr, tmp); |
43 | 21 | + tmp = tcg_temp_new_i32(); | |
44 | typedef struct Exynos4210Irq { | 22 | + gen_helper_v7m_tt(tmp, cpu_env, addr, tcg_constant_i32((a->A << 1) | a->T)); |
45 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | 23 | tcg_temp_free_i32(addr); |
46 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | 24 | store_reg(s, a->rd, tmp); |
47 | index XXXXXXX..XXXXXXX 100644 | 25 | return true; |
48 | --- a/hw/arm/exynos4210.c | 26 | @@ -XXX,XX +XXX,XX @@ static bool trans_PKH(DisasContext *s, arg_PKH *a) |
49 | +++ b/hw/arm/exynos4210.c | 27 | static bool op_sat(DisasContext *s, arg_sat *a, |
50 | @@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | 28 | void (*gen)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32)) |
51 | /* int combiner group 34 */ | 29 | { |
52 | { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, | 30 | - TCGv_i32 tmp, satimm; |
53 | /* int combiner group 35 */ | 31 | + TCGv_i32 tmp; |
54 | - { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | 32 | int shift = a->imm; |
55 | + { 0, 0, 0, EXT_GIC_ID_MCT_L1 }, | 33 | |
56 | /* int combiner group 36 */ | 34 | if (!ENABLE_ARCH_6) { |
57 | { EXT_GIC_ID_MIXER }, | 35 | @@ -XXX,XX +XXX,XX @@ static bool op_sat(DisasContext *s, arg_sat *a, |
58 | /* int combiner group 37 */ | 36 | tcg_gen_shli_i32(tmp, tmp, shift); |
59 | @@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | 37 | } |
60 | /* groups 38-50 */ | 38 | |
61 | { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, | 39 | - satimm = tcg_const_i32(a->satimm); |
62 | /* int combiner group 51 */ | 40 | - gen(tmp, cpu_env, tmp, satimm); |
63 | - { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | 41 | - tcg_temp_free_i32(satimm); |
64 | + { EXT_GIC_ID_MCT_L0 }, | 42 | + gen(tmp, cpu_env, tmp, tcg_constant_i32(a->satimm)); |
65 | /* group 52 */ | 43 | |
66 | { }, | 44 | store_reg(s, a->rd, tmp); |
67 | /* int combiner group 53 */ | 45 | return true; |
68 | - { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | 46 | @@ -XXX,XX +XXX,XX @@ static bool op_smmla(DisasContext *s, arg_rrrr *a, bool round, bool sub) |
69 | + { EXT_GIC_ID_WDT }, | 47 | * a non-zero multiplicand lowpart, and the correct result |
70 | /* groups 54-63 */ | 48 | * lowpart for rounding. |
71 | { }, { }, { }, { }, { }, { }, { }, { }, { }, { } | 49 | */ |
72 | }; | 50 | - TCGv_i32 zero = tcg_const_i32(0); |
73 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | 51 | - tcg_gen_sub2_i32(t2, t1, zero, t3, t2, t1); |
74 | 52 | - tcg_temp_free_i32(zero); | |
75 | for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { | 53 | + tcg_gen_sub2_i32(t2, t1, tcg_constant_i32(0), t3, t2, t1); |
76 | irq_id = 0; | 54 | } else { |
77 | - if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) || | 55 | tcg_gen_add_i32(t1, t1, t3); |
78 | - n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) { | ||
79 | + if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4)) { | ||
80 | /* MCT_G0 is passed to External GIC */ | ||
81 | irq_id = EXT_GIC_ID_MCT_G0; | ||
82 | } | ||
83 | - if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) || | ||
84 | - n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) { | ||
85 | + if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5)) { | ||
86 | /* MCT_G1 is passed to External and GIC */ | ||
87 | irq_id = EXT_GIC_ID_MCT_G1; | ||
88 | } | 56 | } |
89 | -- | 57 | -- |
90 | 2.25.1 | 58 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-33-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate.c | 12 ++++-------- | ||
9 | 1 file changed, 4 insertions(+), 8 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate.c | ||
14 | +++ b/target/arm/translate.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n) | ||
16 | { | ||
17 | int i, j, n, list, mem_idx; | ||
18 | bool user = a->u; | ||
19 | - TCGv_i32 addr, tmp, tmp2; | ||
20 | + TCGv_i32 addr, tmp; | ||
21 | |||
22 | if (user) { | ||
23 | /* STM (user) */ | ||
24 | @@ -XXX,XX +XXX,XX @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n) | ||
25 | |||
26 | if (user && i != 15) { | ||
27 | tmp = tcg_temp_new_i32(); | ||
28 | - tmp2 = tcg_const_i32(i); | ||
29 | - gen_helper_get_user_reg(tmp, cpu_env, tmp2); | ||
30 | - tcg_temp_free_i32(tmp2); | ||
31 | + gen_helper_get_user_reg(tmp, cpu_env, tcg_constant_i32(i)); | ||
32 | } else { | ||
33 | tmp = load_reg(s, i); | ||
34 | } | ||
35 | @@ -XXX,XX +XXX,XX @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n) | ||
36 | bool loaded_base; | ||
37 | bool user = a->u; | ||
38 | bool exc_return = false; | ||
39 | - TCGv_i32 addr, tmp, tmp2, loaded_var; | ||
40 | + TCGv_i32 addr, tmp, loaded_var; | ||
41 | |||
42 | if (user) { | ||
43 | /* LDM (user), LDM (exception return) */ | ||
44 | @@ -XXX,XX +XXX,XX @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n) | ||
45 | tmp = tcg_temp_new_i32(); | ||
46 | gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); | ||
47 | if (user) { | ||
48 | - tmp2 = tcg_const_i32(i); | ||
49 | - gen_helper_set_user_reg(cpu_env, tmp2, tmp); | ||
50 | - tcg_temp_free_i32(tmp2); | ||
51 | + gen_helper_set_user_reg(cpu_env, tcg_constant_i32(i), tmp); | ||
52 | tcg_temp_free_i32(tmp); | ||
53 | } else if (i == a->rn) { | ||
54 | loaded_var = tmp; | ||
55 | -- | ||
56 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-34-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate.c | 16 +++++----------- | ||
9 | 1 file changed, 5 insertions(+), 11 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate.c | ||
14 | +++ b/target/arm/translate.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a) | ||
16 | |||
17 | s->eci_handled = true; | ||
18 | |||
19 | - zero = tcg_const_i32(0); | ||
20 | + zero = tcg_constant_i32(0); | ||
21 | for (i = 0; i < 15; i++) { | ||
22 | if (extract32(a->list, i, 1)) { | ||
23 | /* Clear R[i] */ | ||
24 | @@ -XXX,XX +XXX,XX @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a) | ||
25 | * Clear APSR (by calling the MSR helper with the same argument | ||
26 | * as for "MSR APSR_nzcvqg, Rn": mask = 0b1100, SYSM=0) | ||
27 | */ | ||
28 | - TCGv_i32 maskreg = tcg_const_i32(0xc << 8); | ||
29 | - gen_helper_v7m_msr(cpu_env, maskreg, zero); | ||
30 | - tcg_temp_free_i32(maskreg); | ||
31 | + gen_helper_v7m_msr(cpu_env, tcg_constant_i32(0xc00), zero); | ||
32 | } | ||
33 | - tcg_temp_free_i32(zero); | ||
34 | clear_eci_state(s); | ||
35 | return true; | ||
36 | } | ||
37 | @@ -XXX,XX +XXX,XX @@ static bool trans_DLS(DisasContext *s, arg_DLS *a) | ||
38 | store_reg(s, 14, tmp); | ||
39 | if (a->size != 4) { | ||
40 | /* DLSTP: set FPSCR.LTPSIZE */ | ||
41 | - tmp = tcg_const_i32(a->size); | ||
42 | - store_cpu_field(tmp, v7m.ltpsize); | ||
43 | + store_cpu_field(tcg_constant_i32(a->size), v7m.ltpsize); | ||
44 | s->base.is_jmp = DISAS_UPDATE_NOCHAIN; | ||
45 | } | ||
46 | return true; | ||
47 | @@ -XXX,XX +XXX,XX @@ static bool trans_WLS(DisasContext *s, arg_WLS *a) | ||
48 | */ | ||
49 | bool ok = vfp_access_check(s); | ||
50 | assert(ok); | ||
51 | - tmp = tcg_const_i32(a->size); | ||
52 | - store_cpu_field(tmp, v7m.ltpsize); | ||
53 | + store_cpu_field(tcg_constant_i32(a->size), v7m.ltpsize); | ||
54 | /* | ||
55 | * LTPSIZE updated, but MVE_NO_PRED will always be the same thing (0) | ||
56 | * when we take this upcoming exit from this TB, so gen_jmp_tb() is OK. | ||
57 | @@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a) | ||
58 | gen_set_label(loopend); | ||
59 | if (a->tp) { | ||
60 | /* Exits from tail-pred loops must reset LTPSIZE to 4 */ | ||
61 | - tmp = tcg_const_i32(4); | ||
62 | - store_cpu_field(tmp, v7m.ltpsize); | ||
63 | + store_cpu_field(tcg_constant_i32(4), v7m.ltpsize); | ||
64 | } | ||
65 | /* End TB, continuing to following insn */ | ||
66 | gen_jmp_tb(s, s->base.pc_next, 1); | ||
67 | -- | ||
68 | 2.25.1 | diff view generated by jsdifflib |
1 | The exynos4210 code currently has two very similar arrays of IRQs: | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | * board_irqs is a field of the Exynos4210Irq struct which is filled | 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
4 | in by exynos4210_init_board_irqs() with the appropriate qemu_irqs | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
5 | for each IRQ the board/SoC can assert | 5 | Message-id: 20220426163043.100432-35-richard.henderson@linaro.org |
6 | * irq_table is a set of qemu_irqs pointed to from the | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Exynos4210State struct. It's allocated in exynos4210_init_irq, | 7 | --- |
8 | and the only behaviour these irqs have is that they pass on the | 8 | target/arm/translate.c | 9 +++------ |
9 | level to the equivalent board_irqs[] irq | 9 | 1 file changed, 3 insertions(+), 6 deletions(-) |
10 | 10 | ||
11 | The extra indirection through irq_table is unnecessary, so coalesce | 11 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
12 | these into a single irq_table[] array as a direct field in | ||
13 | Exynos4210State which exynos4210_init_board_irqs() fills in. | ||
14 | |||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
17 | Message-id: 20220404154658.565020-6-peter.maydell@linaro.org | ||
18 | --- | ||
19 | include/hw/arm/exynos4210.h | 8 ++------ | ||
20 | hw/arm/exynos4210.c | 6 +----- | ||
21 | hw/intc/exynos4210_gic.c | 32 ++++++++------------------------ | ||
22 | 3 files changed, 11 insertions(+), 35 deletions(-) | ||
23 | |||
24 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | ||
25 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/include/hw/arm/exynos4210.h | 13 | --- a/target/arm/translate.c |
27 | +++ b/include/hw/arm/exynos4210.h | 14 | +++ b/target/arm/translate.c |
28 | @@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq { | 15 | @@ -XXX,XX +XXX,XX @@ static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a) |
29 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | 16 | return true; |
30 | qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; | ||
31 | qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ]; | ||
32 | - qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
33 | } Exynos4210Irq; | ||
34 | |||
35 | struct Exynos4210State { | ||
36 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { | ||
37 | /*< public >*/ | ||
38 | ARMCPU *cpu[EXYNOS4210_NCPUS]; | ||
39 | Exynos4210Irq irqs; | ||
40 | - qemu_irq *irq_table; | ||
41 | + qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
42 | |||
43 | MemoryRegion chipid_mem; | ||
44 | MemoryRegion iram_mem; | ||
45 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC) | ||
46 | void exynos4210_write_secondary(ARMCPU *cpu, | ||
47 | const struct arm_boot_info *info); | ||
48 | |||
49 | -/* Initialize exynos4210 IRQ subsystem stub */ | ||
50 | -qemu_irq *exynos4210_init_irq(Exynos4210Irq *env); | ||
51 | - | ||
52 | /* Initialize board IRQs. | ||
53 | * These IRQs contain splitted Int/External Combiner and External Gic IRQs */ | ||
54 | -void exynos4210_init_board_irqs(Exynos4210Irq *s); | ||
55 | +void exynos4210_init_board_irqs(Exynos4210State *s); | ||
56 | |||
57 | /* Get IRQ number from exynos4210 IRQ subsystem stub. | ||
58 | * To identify IRQ source use internal combiner group and bit number | ||
59 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
60 | index XXXXXXX..XXXXXXX 100644 | ||
61 | --- a/hw/arm/exynos4210.c | ||
62 | +++ b/hw/arm/exynos4210.c | ||
63 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
64 | qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); | ||
65 | } | 17 | } |
66 | 18 | ||
67 | - /*** IRQs ***/ | 19 | - tmp = tcg_const_i32(a->im); |
68 | - | 20 | + tmp = tcg_constant_i32(a->im); |
69 | - s->irq_table = exynos4210_init_irq(&s->irqs); | 21 | /* FAULTMASK */ |
70 | - | 22 | if (a->F) { |
71 | /* IRQ Gate */ | 23 | - addr = tcg_const_i32(19); |
72 | for (i = 0; i < EXYNOS4210_NCPUS; i++) { | 24 | + addr = tcg_constant_i32(19); |
73 | DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]); | 25 | gen_helper_v7m_msr(cpu_env, addr, tmp); |
74 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | 26 | - tcg_temp_free_i32(addr); |
75 | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); | ||
76 | |||
77 | /* Initialize board IRQs. */ | ||
78 | - exynos4210_init_board_irqs(&s->irqs); | ||
79 | + exynos4210_init_board_irqs(s); | ||
80 | |||
81 | /*** Memory ***/ | ||
82 | |||
83 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | ||
84 | index XXXXXXX..XXXXXXX 100644 | ||
85 | --- a/hw/intc/exynos4210_gic.c | ||
86 | +++ b/hw/intc/exynos4210_gic.c | ||
87 | @@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
88 | #define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100 | ||
89 | #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000 | ||
90 | |||
91 | -static void exynos4210_irq_handler(void *opaque, int irq, int level) | ||
92 | -{ | ||
93 | - Exynos4210Irq *s = (Exynos4210Irq *)opaque; | ||
94 | - | ||
95 | - /* Bypass */ | ||
96 | - qemu_set_irq(s->board_irqs[irq], level); | ||
97 | -} | ||
98 | - | ||
99 | -/* | ||
100 | - * Initialize exynos4210 IRQ subsystem stub. | ||
101 | - */ | ||
102 | -qemu_irq *exynos4210_init_irq(Exynos4210Irq *s) | ||
103 | -{ | ||
104 | - return qemu_allocate_irqs(exynos4210_irq_handler, s, | ||
105 | - EXYNOS4210_MAX_INT_COMBINER_IN_IRQ); | ||
106 | -} | ||
107 | - | ||
108 | /* | ||
109 | * Initialize board IRQs. | ||
110 | * These IRQs contain splitted Int/External Combiner and External Gic IRQs. | ||
111 | */ | ||
112 | -void exynos4210_init_board_irqs(Exynos4210Irq *s) | ||
113 | +void exynos4210_init_board_irqs(Exynos4210State *s) | ||
114 | { | ||
115 | uint32_t grp, bit, irq_id, n; | ||
116 | + Exynos4210Irq *is = &s->irqs; | ||
117 | |||
118 | for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { | ||
119 | irq_id = 0; | ||
120 | @@ -XXX,XX +XXX,XX @@ void exynos4210_init_board_irqs(Exynos4210Irq *s) | ||
121 | irq_id = EXT_GIC_ID_MCT_G1; | ||
122 | } | ||
123 | if (irq_id) { | ||
124 | - s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n], | ||
125 | - s->ext_gic_irq[irq_id-32]); | ||
126 | + s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
127 | + is->ext_gic_irq[irq_id - 32]); | ||
128 | } else { | ||
129 | - s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n], | ||
130 | - s->ext_combiner_irq[n]); | ||
131 | + s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
132 | + is->ext_combiner_irq[n]); | ||
133 | } | ||
134 | } | 27 | } |
135 | for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { | 28 | /* PRIMASK */ |
136 | @@ -XXX,XX +XXX,XX @@ void exynos4210_init_board_irqs(Exynos4210Irq *s) | 29 | if (a->I) { |
137 | EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; | 30 | - addr = tcg_const_i32(16); |
138 | 31 | + addr = tcg_constant_i32(16); | |
139 | if (irq_id) { | 32 | gen_helper_v7m_msr(cpu_env, addr, tmp); |
140 | - s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n], | 33 | - tcg_temp_free_i32(addr); |
141 | - s->ext_gic_irq[irq_id-32]); | ||
142 | + s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
143 | + is->ext_gic_irq[irq_id - 32]); | ||
144 | } | ||
145 | } | 34 | } |
35 | gen_rebuild_hflags(s, false); | ||
36 | - tcg_temp_free_i32(tmp); | ||
37 | gen_lookup_tb(s); | ||
38 | return true; | ||
146 | } | 39 | } |
147 | -- | 40 | -- |
148 | 2.25.1 | 41 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-36-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate.c | 7 +++---- | ||
9 | 1 file changed, 3 insertions(+), 4 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate.c | ||
14 | +++ b/target/arm/translate.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a) | ||
16 | } | ||
17 | |||
18 | /* In this insn input reg fields of 0b1111 mean "zero", not "PC" */ | ||
19 | + zero = tcg_constant_i32(0); | ||
20 | if (a->rn == 15) { | ||
21 | - rn = tcg_const_i32(0); | ||
22 | + rn = zero; | ||
23 | } else { | ||
24 | rn = load_reg(s, a->rn); | ||
25 | } | ||
26 | if (a->rm == 15) { | ||
27 | - rm = tcg_const_i32(0); | ||
28 | + rm = zero; | ||
29 | } else { | ||
30 | rm = load_reg(s, a->rm); | ||
31 | } | ||
32 | @@ -XXX,XX +XXX,XX @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a) | ||
33 | } | ||
34 | |||
35 | arm_test_cc(&c, a->fcond); | ||
36 | - zero = tcg_const_i32(0); | ||
37 | tcg_gen_movcond_i32(c.cond, rn, c.value, zero, rn, rm); | ||
38 | arm_free_cc(&c); | ||
39 | - tcg_temp_free_i32(zero); | ||
40 | |||
41 | store_reg(s, a->rd, rn); | ||
42 | tcg_temp_free_i32(rm); | ||
43 | -- | ||
44 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220426163043.100432-37-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate-sve.c | 12 ++++-------- | ||
9 | 1 file changed, 4 insertions(+), 8 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/translate-sve.c | ||
14 | +++ b/target/arm/translate-sve.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void do_index(DisasContext *s, int esz, int rd, | ||
16 | static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a) | ||
17 | { | ||
18 | if (sve_access_check(s)) { | ||
19 | - TCGv_i64 start = tcg_const_i64(a->imm1); | ||
20 | - TCGv_i64 incr = tcg_const_i64(a->imm2); | ||
21 | + TCGv_i64 start = tcg_constant_i64(a->imm1); | ||
22 | + TCGv_i64 incr = tcg_constant_i64(a->imm2); | ||
23 | do_index(s, a->esz, a->rd, start, incr); | ||
24 | - tcg_temp_free_i64(start); | ||
25 | - tcg_temp_free_i64(incr); | ||
26 | } | ||
27 | return true; | ||
28 | } | ||
29 | @@ -XXX,XX +XXX,XX @@ static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a) | ||
30 | static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_ir *a) | ||
31 | { | ||
32 | if (sve_access_check(s)) { | ||
33 | - TCGv_i64 start = tcg_const_i64(a->imm); | ||
34 | + TCGv_i64 start = tcg_constant_i64(a->imm); | ||
35 | TCGv_i64 incr = cpu_reg(s, a->rm); | ||
36 | do_index(s, a->esz, a->rd, start, incr); | ||
37 | - tcg_temp_free_i64(start); | ||
38 | } | ||
39 | return true; | ||
40 | } | ||
41 | @@ -XXX,XX +XXX,XX @@ static bool trans_INDEX_ri(DisasContext *s, arg_INDEX_ri *a) | ||
42 | { | ||
43 | if (sve_access_check(s)) { | ||
44 | TCGv_i64 start = cpu_reg(s, a->rn); | ||
45 | - TCGv_i64 incr = tcg_const_i64(a->imm); | ||
46 | + TCGv_i64 incr = tcg_constant_i64(a->imm); | ||
47 | do_index(s, a->esz, a->rd, start, incr); | ||
48 | - tcg_temp_free_i64(incr); | ||
49 | } | ||
50 | return true; | ||
51 | } | ||
52 | -- | ||
53 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Hao Wu <wuhaotsh@google.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Similar to the Aspeed code in include/misc/aspeed_scu.h, we define | 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
4 | the PWRON STRAP fields in their corresponding module for NPCM7XX. | ||
5 | |||
6 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | ||
7 | Reviewed-by: Patrick Venture <venture@google.com> | ||
8 | Message-id: 20220411165842.3912945-2-wuhaotsh@google.com | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Message-id: 20220426163043.100432-38-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 7 | --- |
12 | include/hw/misc/npcm7xx_gcr.h | 30 ++++++++++++++++++++++++++++++ | 8 | target/arm/translate-sve.c | 18 ++++++------------ |
13 | 1 file changed, 30 insertions(+) | 9 | 1 file changed, 6 insertions(+), 12 deletions(-) |
14 | 10 | ||
15 | diff --git a/include/hw/misc/npcm7xx_gcr.h b/include/hw/misc/npcm7xx_gcr.h | 11 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c |
16 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/include/hw/misc/npcm7xx_gcr.h | 13 | --- a/target/arm/translate-sve.c |
18 | +++ b/include/hw/misc/npcm7xx_gcr.h | 14 | +++ b/target/arm/translate-sve.c |
19 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ static bool trans_SINCDEC_r_32(DisasContext *s, arg_incdec_cnt *a) |
20 | #include "exec/memory.h" | 16 | tcg_gen_ext32s_i64(reg, reg); |
21 | #include "hw/sysbus.h" | 17 | } |
22 | 18 | } else { | |
23 | +/* | 19 | - TCGv_i64 t = tcg_const_i64(inc); |
24 | + * NPCM7XX PWRON STRAP bit fields | 20 | - do_sat_addsub_32(reg, t, a->u, a->d); |
25 | + * 12: SPI0 powered by VSBV3 at 1.8V | 21 | - tcg_temp_free_i64(t); |
26 | + * 11: System flash attached to BMC | 22 | + do_sat_addsub_32(reg, tcg_constant_i64(inc), a->u, a->d); |
27 | + * 10: BSP alternative pins. | 23 | } |
28 | + * 9:8: Flash UART command route enabled. | 24 | return true; |
29 | + * 7: Security enabled. | 25 | } |
30 | + * 6: HI-Z state control. | 26 | @@ -XXX,XX +XXX,XX @@ static bool trans_SINCDEC_r_64(DisasContext *s, arg_incdec_cnt *a) |
31 | + * 5: ECC disabled. | 27 | TCGv_i64 reg = cpu_reg(s, a->rd); |
32 | + * 4: Reserved | 28 | |
33 | + * 3: JTAG2 enabled. | 29 | if (inc != 0) { |
34 | + * 2:0: CPU and DRAM clock frequency. | 30 | - TCGv_i64 t = tcg_const_i64(inc); |
35 | + */ | 31 | - do_sat_addsub_64(reg, t, a->u, a->d); |
36 | +#define NPCM7XX_PWRON_STRAP_SPI0F18 BIT(12) | 32 | - tcg_temp_free_i64(t); |
37 | +#define NPCM7XX_PWRON_STRAP_SFAB BIT(11) | 33 | + do_sat_addsub_64(reg, tcg_constant_i64(inc), a->u, a->d); |
38 | +#define NPCM7XX_PWRON_STRAP_BSPA BIT(10) | 34 | } |
39 | +#define NPCM7XX_PWRON_STRAP_FUP(x) ((x) << 8) | 35 | return true; |
40 | +#define FUP_NORM_UART2 3 | 36 | } |
41 | +#define FUP_PROG_UART3 2 | 37 | @@ -XXX,XX +XXX,XX @@ static bool trans_INCDEC_v(DisasContext *s, arg_incdec2_cnt *a) |
42 | +#define FUP_PROG_UART2 1 | 38 | |
43 | +#define FUP_NORM_UART3 0 | 39 | if (inc != 0) { |
44 | +#define NPCM7XX_PWRON_STRAP_SECEN BIT(7) | 40 | if (sve_access_check(s)) { |
45 | +#define NPCM7XX_PWRON_STRAP_HIZ BIT(6) | 41 | - TCGv_i64 t = tcg_const_i64(a->d ? -inc : inc); |
46 | +#define NPCM7XX_PWRON_STRAP_ECC BIT(5) | 42 | tcg_gen_gvec_adds(a->esz, vec_full_reg_offset(s, a->rd), |
47 | +#define NPCM7XX_PWRON_STRAP_RESERVE1 BIT(4) | 43 | vec_full_reg_offset(s, a->rn), |
48 | +#define NPCM7XX_PWRON_STRAP_J2EN BIT(3) | 44 | - t, fullsz, fullsz); |
49 | +#define NPCM7XX_PWRON_STRAP_CKFRQ(x) (x) | 45 | - tcg_temp_free_i64(t); |
50 | +#define CKFRQ_SKIPINIT 0x000 | 46 | + tcg_constant_i64(a->d ? -inc : inc), |
51 | +#define CKFRQ_DEFAULT 0x111 | 47 | + fullsz, fullsz); |
52 | + | 48 | } |
53 | /* | 49 | } else { |
54 | * Number of registers in our device state structure. Don't change this without | 50 | do_mov_z(s, a->rd, a->rn); |
55 | * incrementing the version_id in the vmstate. | 51 | @@ -XXX,XX +XXX,XX @@ static bool trans_SINCDEC_v(DisasContext *s, arg_incdec2_cnt *a) |
52 | |||
53 | if (inc != 0) { | ||
54 | if (sve_access_check(s)) { | ||
55 | - TCGv_i64 t = tcg_const_i64(inc); | ||
56 | - do_sat_addsub_vec(s, a->esz, a->rd, a->rn, t, a->u, a->d); | ||
57 | - tcg_temp_free_i64(t); | ||
58 | + do_sat_addsub_vec(s, a->esz, a->rd, a->rn, | ||
59 | + tcg_constant_i64(inc), a->u, a->d); | ||
60 | } | ||
61 | } else { | ||
62 | do_mov_z(s, a->rd, a->rn); | ||
56 | -- | 63 | -- |
57 | 2.25.1 | 64 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Describe that the gic-version influences the maximum number of CPUs. | 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
4 | |||
5 | Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> | ||
6 | Message-id: 20220413231456.35811-1-heinrich.schuchardt@canonical.com | ||
7 | [PMM: minor punctuation tweaks] | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Message-id: 20220426163043.100432-39-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 7 | --- |
11 | docs/system/arm/virt.rst | 4 ++-- | 8 | target/arm/translate-sve.c | 13 ++++--------- |
12 | 1 file changed, 2 insertions(+), 2 deletions(-) | 9 | 1 file changed, 4 insertions(+), 9 deletions(-) |
13 | 10 | ||
14 | diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst | 11 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c |
15 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/docs/system/arm/virt.rst | 13 | --- a/target/arm/translate-sve.c |
17 | +++ b/docs/system/arm/virt.rst | 14 | +++ b/target/arm/translate-sve.c |
18 | @@ -XXX,XX +XXX,XX @@ gic-version | 15 | @@ -XXX,XX +XXX,XX @@ static bool trans_FCPY(DisasContext *s, arg_FCPY *a) |
19 | Valid values are: | 16 | if (sve_access_check(s)) { |
20 | 17 | /* Decode the VFP immediate. */ | |
21 | ``2`` | 18 | uint64_t imm = vfp_expand_imm(a->esz, a->imm); |
22 | - GICv2 | 19 | - TCGv_i64 t_imm = tcg_const_i64(imm); |
23 | + GICv2. Note that this limits the number of CPUs to 8. | 20 | - do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, t_imm); |
24 | ``3`` | 21 | - tcg_temp_free_i64(t_imm); |
25 | - GICv3 | 22 | + do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, tcg_constant_i64(imm)); |
26 | + GICv3. This allows up to 512 CPUs. | 23 | } |
27 | ``host`` | 24 | return true; |
28 | Use the same GIC version the host provides, when using KVM | 25 | } |
29 | ``max`` | 26 | @@ -XXX,XX +XXX,XX @@ static bool trans_CPY_m_i(DisasContext *s, arg_rpri_esz *a) |
27 | return false; | ||
28 | } | ||
29 | if (sve_access_check(s)) { | ||
30 | - TCGv_i64 t_imm = tcg_const_i64(a->imm); | ||
31 | - do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, t_imm); | ||
32 | - tcg_temp_free_i64(t_imm); | ||
33 | + do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, tcg_constant_i64(a->imm)); | ||
34 | } | ||
35 | return true; | ||
36 | } | ||
37 | @@ -XXX,XX +XXX,XX @@ static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_i *a) | ||
38 | } | ||
39 | if (sve_access_check(s)) { | ||
40 | unsigned vsz = vec_full_reg_size(s); | ||
41 | - TCGv_i64 t_imm = tcg_const_i64(a->imm); | ||
42 | tcg_gen_gvec_2i_ool(vec_full_reg_offset(s, a->rd), | ||
43 | pred_full_reg_offset(s, a->pg), | ||
44 | - t_imm, vsz, vsz, 0, fns[a->esz]); | ||
45 | - tcg_temp_free_i64(t_imm); | ||
46 | + tcg_constant_i64(a->imm), | ||
47 | + vsz, vsz, 0, fns[a->esz]); | ||
48 | } | ||
49 | return true; | ||
50 | } | ||
30 | -- | 51 | -- |
31 | 2.25.1 | 52 | 2.25.1 | diff view generated by jsdifflib |
1 | From: "Edgar E. Iglesias" <edgar.iglesias@amd.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Add the Cortex-R5Fs of the Versal RPU (Real-time Processing Unit) | 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
4 | subsystem. | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
5 | 5 | Message-id: 20220426163043.100432-40-richard.henderson@linaro.org | |
6 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> | ||
7 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | ||
8 | Message-id: 20220406174303.2022038-3-edgar.iglesias@xilinx.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 7 | --- |
11 | include/hw/arm/xlnx-versal.h | 10 ++++++++++ | 8 | target/arm/translate-sve.c | 12 ++++-------- |
12 | hw/arm/xlnx-versal-virt.c | 6 +++--- | 9 | 1 file changed, 4 insertions(+), 8 deletions(-) |
13 | hw/arm/xlnx-versal.c | 36 ++++++++++++++++++++++++++++++++++++ | ||
14 | 3 files changed, 49 insertions(+), 3 deletions(-) | ||
15 | 10 | ||
16 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h | 11 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c |
17 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/arm/xlnx-versal.h | 13 | --- a/target/arm/translate-sve.c |
19 | +++ b/include/hw/arm/xlnx-versal.h | 14 | +++ b/target/arm/translate-sve.c |
20 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ static void incr_last_active(DisasContext *s, TCGv_i32 last, int esz) |
21 | OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) | 16 | if (is_power_of_2(vsz)) { |
22 | 17 | tcg_gen_andi_i32(last, last, vsz - 1); | |
23 | #define XLNX_VERSAL_NR_ACPUS 2 | 18 | } else { |
24 | +#define XLNX_VERSAL_NR_RCPUS 2 | 19 | - TCGv_i32 max = tcg_const_i32(vsz); |
25 | #define XLNX_VERSAL_NR_UARTS 2 | 20 | - TCGv_i32 zero = tcg_const_i32(0); |
26 | #define XLNX_VERSAL_NR_GEMS 2 | 21 | + TCGv_i32 max = tcg_constant_i32(vsz); |
27 | #define XLNX_VERSAL_NR_ADMAS 8 | 22 | + TCGv_i32 zero = tcg_constant_i32(0); |
28 | @@ -XXX,XX +XXX,XX @@ struct Versal { | 23 | tcg_gen_movcond_i32(TCG_COND_GEU, last, last, max, zero, last); |
29 | VersalUsb2 usb; | 24 | - tcg_temp_free_i32(max); |
30 | } iou; | 25 | - tcg_temp_free_i32(zero); |
31 | |||
32 | + /* Real-time Processing Unit. */ | ||
33 | + struct { | ||
34 | + MemoryRegion mr; | ||
35 | + MemoryRegion mr_ps_alias; | ||
36 | + | ||
37 | + CPUClusterState cluster; | ||
38 | + ARMCPU cpu[XLNX_VERSAL_NR_RCPUS]; | ||
39 | + } rpu; | ||
40 | + | ||
41 | struct { | ||
42 | qemu_or_irq irq_orgate; | ||
43 | XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; | ||
44 | diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/hw/arm/xlnx-versal-virt.c | ||
47 | +++ b/hw/arm/xlnx-versal-virt.c | ||
48 | @@ -XXX,XX +XXX,XX @@ static void versal_virt_machine_class_init(ObjectClass *oc, void *data) | ||
49 | |||
50 | mc->desc = "Xilinx Versal Virtual development board"; | ||
51 | mc->init = versal_virt_init; | ||
52 | - mc->min_cpus = XLNX_VERSAL_NR_ACPUS; | ||
53 | - mc->max_cpus = XLNX_VERSAL_NR_ACPUS; | ||
54 | - mc->default_cpus = XLNX_VERSAL_NR_ACPUS; | ||
55 | + mc->min_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS; | ||
56 | + mc->max_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS; | ||
57 | + mc->default_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS; | ||
58 | mc->no_cdrom = true; | ||
59 | mc->default_ram_id = "ddr"; | ||
60 | } | ||
61 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/hw/arm/xlnx-versal.c | ||
64 | +++ b/hw/arm/xlnx-versal.c | ||
65 | @@ -XXX,XX +XXX,XX @@ | ||
66 | #include "hw/sysbus.h" | ||
67 | |||
68 | #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") | ||
69 | +#define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") | ||
70 | #define GEM_REVISION 0x40070106 | ||
71 | |||
72 | #define VERSAL_NUM_PMC_APB_IRQS 3 | ||
73 | @@ -XXX,XX +XXX,XX @@ static void versal_create_apu_gic(Versal *s, qemu_irq *pic) | ||
74 | } | 26 | } |
75 | } | 27 | } |
76 | 28 | ||
77 | +static void versal_create_rpu_cpus(Versal *s) | 29 | @@ -XXX,XX +XXX,XX @@ static void wrap_last_active(DisasContext *s, TCGv_i32 last, int esz) |
78 | +{ | 30 | if (is_power_of_2(vsz)) { |
79 | + int i; | 31 | tcg_gen_andi_i32(last, last, vsz - 1); |
80 | + | 32 | } else { |
81 | + object_initialize_child(OBJECT(s), "rpu-cluster", &s->lpd.rpu.cluster, | 33 | - TCGv_i32 max = tcg_const_i32(vsz - (1 << esz)); |
82 | + TYPE_CPU_CLUSTER); | 34 | - TCGv_i32 zero = tcg_const_i32(0); |
83 | + qdev_prop_set_uint32(DEVICE(&s->lpd.rpu.cluster), "cluster-id", 1); | 35 | + TCGv_i32 max = tcg_constant_i32(vsz - (1 << esz)); |
84 | + | 36 | + TCGv_i32 zero = tcg_constant_i32(0); |
85 | + for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) { | 37 | tcg_gen_movcond_i32(TCG_COND_LT, last, last, zero, max, last); |
86 | + Object *obj; | 38 | - tcg_temp_free_i32(max); |
87 | + | 39 | - tcg_temp_free_i32(zero); |
88 | + object_initialize_child(OBJECT(&s->lpd.rpu.cluster), | 40 | } |
89 | + "rpu-cpu[*]", &s->lpd.rpu.cpu[i], | ||
90 | + XLNX_VERSAL_RCPU_TYPE); | ||
91 | + obj = OBJECT(&s->lpd.rpu.cpu[i]); | ||
92 | + object_property_set_bool(obj, "start-powered-off", true, | ||
93 | + &error_abort); | ||
94 | + | ||
95 | + object_property_set_int(obj, "mp-affinity", 0x100 | i, &error_abort); | ||
96 | + object_property_set_int(obj, "core-count", ARRAY_SIZE(s->lpd.rpu.cpu), | ||
97 | + &error_abort); | ||
98 | + object_property_set_link(obj, "memory", OBJECT(&s->lpd.rpu.mr), | ||
99 | + &error_abort); | ||
100 | + qdev_realize(DEVICE(obj), NULL, &error_fatal); | ||
101 | + } | ||
102 | + | ||
103 | + qdev_realize(DEVICE(&s->lpd.rpu.cluster), NULL, &error_fatal); | ||
104 | +} | ||
105 | + | ||
106 | static void versal_create_uarts(Versal *s, qemu_irq *pic) | ||
107 | { | ||
108 | int i; | ||
109 | @@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp) | ||
110 | |||
111 | versal_create_apu_cpus(s); | ||
112 | versal_create_apu_gic(s, pic); | ||
113 | + versal_create_rpu_cpus(s); | ||
114 | versal_create_uarts(s, pic); | ||
115 | versal_create_usbs(s, pic); | ||
116 | versal_create_gems(s, pic); | ||
117 | @@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp) | ||
118 | |||
119 | memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0); | ||
120 | memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0); | ||
121 | + memory_region_add_subregion_overlap(&s->lpd.rpu.mr, 0, | ||
122 | + &s->lpd.rpu.mr_ps_alias, 0); | ||
123 | } | 41 | } |
124 | 42 | ||
125 | static void versal_init(Object *obj) | ||
126 | @@ -XXX,XX +XXX,XX @@ static void versal_init(Object *obj) | ||
127 | Versal *s = XLNX_VERSAL(obj); | ||
128 | |||
129 | memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX); | ||
130 | + memory_region_init(&s->lpd.rpu.mr, obj, "mr-rpu", UINT64_MAX); | ||
131 | memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX); | ||
132 | + memory_region_init_alias(&s->lpd.rpu.mr_ps_alias, OBJECT(s), | ||
133 | + "mr-rpu-ps-alias", &s->mr_ps, 0, UINT64_MAX); | ||
134 | } | ||
135 | |||
136 | static Property versal_properties[] = { | ||
137 | -- | 43 | -- |
138 | 2.25.1 | 44 | 2.25.1 | diff view generated by jsdifflib |
1 | Currently for the interrupts MCT_G0 and MCT_G1 which are | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | the only ones in the input range of the external combiner | ||
3 | and which are also wired to the external GIC, we connect | ||
4 | them only to the internal combiner and the external GIC. | ||
5 | This seems likely to be a bug, as all other interrupts | ||
6 | which are in the input range of both combiners are | ||
7 | connected to both combiners. (The fact that the code in | ||
8 | exynos4210_combiner_get_gpioin() is also trying to wire | ||
9 | up these inputs on both combiners also suggests this.) | ||
10 | 2 | ||
11 | Wire these interrupts up to both combiners, like the rest. | 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
12 | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | |
5 | Message-id: 20220426163043.100432-41-richard.henderson@linaro.org | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-id: 20220404154658.565020-15-peter.maydell@linaro.org | ||
16 | --- | 7 | --- |
17 | hw/arm/exynos4210.c | 7 +++---- | 8 | target/arm/translate-sve.c | 7 +++---- |
18 | 1 file changed, 3 insertions(+), 4 deletions(-) | 9 | 1 file changed, 3 insertions(+), 4 deletions(-) |
19 | 10 | ||
20 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | 11 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c |
21 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/hw/arm/exynos4210.c | 13 | --- a/target/arm/translate-sve.c |
23 | +++ b/hw/arm/exynos4210.c | 14 | +++ b/target/arm/translate-sve.c |
24 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | 15 | @@ -XXX,XX +XXX,XX @@ static void do_clast_scalar(DisasContext *s, int esz, int pg, int rm, |
25 | 16 | bool before, TCGv_i64 reg_val) | |
26 | assert(splitcount < EXYNOS4210_NUM_SPLITTERS); | 17 | { |
27 | splitter = DEVICE(&s->splitter[splitcount]); | 18 | TCGv_i32 last = tcg_temp_new_i32(); |
28 | - qdev_prop_set_uint16(splitter, "num-lines", 2); | 19 | - TCGv_i64 ele, cmp, zero; |
29 | + qdev_prop_set_uint16(splitter, "num-lines", irq_id ? 3 : 2); | 20 | + TCGv_i64 ele, cmp; |
30 | qdev_realize(splitter, NULL, &error_abort); | 21 | |
31 | splitcount++; | 22 | find_last_active(s, last, esz, pg); |
32 | s->irq_table[n] = qdev_get_gpio_in(splitter, 0); | 23 | |
33 | qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); | 24 | @@ -XXX,XX +XXX,XX @@ static void do_clast_scalar(DisasContext *s, int esz, int pg, int rm, |
34 | + qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]); | 25 | ele = load_last_active(s, last, rm, esz); |
35 | if (irq_id) { | 26 | tcg_temp_free_i32(last); |
36 | - qdev_connect_gpio_out(splitter, 1, | 27 | |
37 | + qdev_connect_gpio_out(splitter, 2, | 28 | - zero = tcg_const_i64(0); |
38 | qdev_get_gpio_in(extgicdev, irq_id - 32)); | 29 | - tcg_gen_movcond_i64(TCG_COND_GE, reg_val, cmp, zero, ele, reg_val); |
39 | - } else { | 30 | + tcg_gen_movcond_i64(TCG_COND_GE, reg_val, cmp, tcg_constant_i64(0), |
40 | - qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]); | 31 | + ele, reg_val); |
41 | } | 32 | |
42 | } | 33 | - tcg_temp_free_i64(zero); |
43 | for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { | 34 | tcg_temp_free_i64(cmp); |
35 | tcg_temp_free_i64(ele); | ||
36 | } | ||
44 | -- | 37 | -- |
45 | 2.25.1 | 38 | 2.25.1 | diff view generated by jsdifflib |
1 | The only time we use the int_combiner_irq[] and ext_combiner_irq[] | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | arrays in the Exynos4210Irq struct is during realize of the SoC -- we | ||
3 | initialize them with the input IRQs of the combiner devices, and then | ||
4 | connect those to outputs of other devices in | ||
5 | exynos4210_init_board_irqs(). Now that the combiner objects are | ||
6 | easily accessible as s->int_combiner and s->ext_combiner we can make | ||
7 | the connections directly from one device to the other without going | ||
8 | via these arrays. | ||
9 | 2 | ||
10 | Since these are the only two remaining elements of Exynos4210Irq, | 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
11 | we can remove that struct entirely. | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Message-id: 20220426163043.100432-42-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/translate-sve.c | 20 +++++++------------- | ||
9 | 1 file changed, 7 insertions(+), 13 deletions(-) | ||
12 | 10 | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c |
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-id: 20220404154658.565020-19-peter.maydell@linaro.org | ||
16 | --- | ||
17 | include/hw/arm/exynos4210.h | 6 ------ | ||
18 | hw/arm/exynos4210.c | 34 ++++++++-------------------------- | ||
19 | 2 files changed, 8 insertions(+), 32 deletions(-) | ||
20 | |||
21 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | ||
22 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/include/hw/arm/exynos4210.h | 13 | --- a/target/arm/translate-sve.c |
24 | +++ b/include/hw/arm/exynos4210.h | 14 | +++ b/target/arm/translate-sve.c |
25 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ static bool trans_CTERM(DisasContext *s, arg_CTERM *a) |
26 | */ | 16 | static bool trans_WHILE(DisasContext *s, arg_WHILE *a) |
27 | #define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38) | ||
28 | |||
29 | -typedef struct Exynos4210Irq { | ||
30 | - qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
31 | - qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; | ||
32 | -} Exynos4210Irq; | ||
33 | - | ||
34 | struct Exynos4210State { | ||
35 | /*< private >*/ | ||
36 | SysBusDevice parent_obj; | ||
37 | /*< public >*/ | ||
38 | ARMCPU *cpu[EXYNOS4210_NCPUS]; | ||
39 | - Exynos4210Irq irqs; | ||
40 | qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
41 | |||
42 | MemoryRegion chipid_mem; | ||
43 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/hw/arm/exynos4210.c | ||
46 | +++ b/hw/arm/exynos4210.c | ||
47 | @@ -XXX,XX +XXX,XX @@ static int mapline_size(const int *mapline) | ||
48 | static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
49 | { | 17 | { |
50 | uint32_t grp, bit, irq_id, n; | 18 | TCGv_i64 op0, op1, t0, t1, tmax; |
51 | - Exynos4210Irq *is = &s->irqs; | 19 | - TCGv_i32 t2, t3; |
52 | DeviceState *extgicdev = DEVICE(&s->ext_gic); | 20 | + TCGv_i32 t2; |
53 | + DeviceState *intcdev = DEVICE(&s->int_combiner); | 21 | TCGv_ptr ptr; |
54 | + DeviceState *extcdev = DEVICE(&s->ext_combiner); | 22 | unsigned vsz = vec_full_reg_size(s); |
55 | int splitcount = 0; | 23 | unsigned desc = 0; |
56 | DeviceState *splitter; | 24 | @@ -XXX,XX +XXX,XX @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a) |
57 | const int *mapline; | ||
58 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
59 | splitin = 0; | ||
60 | for (;;) { | ||
61 | s->irq_table[in] = qdev_get_gpio_in(splitter, 0); | ||
62 | - qdev_connect_gpio_out(splitter, splitin, is->int_combiner_irq[in]); | ||
63 | - qdev_connect_gpio_out(splitter, splitin + 1, is->ext_combiner_irq[in]); | ||
64 | + qdev_connect_gpio_out(splitter, splitin, | ||
65 | + qdev_get_gpio_in(intcdev, in)); | ||
66 | + qdev_connect_gpio_out(splitter, splitin + 1, | ||
67 | + qdev_get_gpio_in(extcdev, in)); | ||
68 | splitin += 2; | ||
69 | if (!mapline) { | ||
70 | break; | ||
71 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
72 | qdev_realize(splitter, NULL, &error_abort); | ||
73 | splitcount++; | ||
74 | s->irq_table[n] = qdev_get_gpio_in(splitter, 0); | ||
75 | - qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); | ||
76 | + qdev_connect_gpio_out(splitter, 0, qdev_get_gpio_in(intcdev, n)); | ||
77 | qdev_connect_gpio_out(splitter, 1, | ||
78 | qdev_get_gpio_in(extgicdev, irq_id - 32)); | ||
79 | } else { | ||
80 | - s->irq_table[n] = is->int_combiner_irq[n]; | ||
81 | + s->irq_table[n] = qdev_get_gpio_in(intcdev, n); | ||
82 | } | 25 | } |
83 | } | 26 | } |
84 | /* | 27 | |
85 | @@ -XXX,XX +XXX,XX @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) | 28 | - tmax = tcg_const_i64(vsz >> a->esz); |
86 | return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); | 29 | + tmax = tcg_constant_i64(vsz >> a->esz); |
30 | if (eq) { | ||
31 | /* Equality means one more iteration. */ | ||
32 | tcg_gen_addi_i64(t0, t0, 1); | ||
33 | @@ -XXX,XX +XXX,XX @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a) | ||
34 | |||
35 | /* Bound to the maximum. */ | ||
36 | tcg_gen_umin_i64(t0, t0, tmax); | ||
37 | - tcg_temp_free_i64(tmax); | ||
38 | |||
39 | /* Set the count to zero if the condition is false. */ | ||
40 | tcg_gen_movi_i64(t1, 0); | ||
41 | @@ -XXX,XX +XXX,XX @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a) | ||
42 | |||
43 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8); | ||
44 | desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); | ||
45 | - t3 = tcg_const_i32(desc); | ||
46 | |||
47 | ptr = tcg_temp_new_ptr(); | ||
48 | tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd)); | ||
49 | |||
50 | if (a->lt) { | ||
51 | - gen_helper_sve_whilel(t2, ptr, t2, t3); | ||
52 | + gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc)); | ||
53 | } else { | ||
54 | - gen_helper_sve_whileg(t2, ptr, t2, t3); | ||
55 | + gen_helper_sve_whileg(t2, ptr, t2, tcg_constant_i32(desc)); | ||
56 | } | ||
57 | do_pred_flags(t2); | ||
58 | |||
59 | tcg_temp_free_ptr(ptr); | ||
60 | tcg_temp_free_i32(t2); | ||
61 | - tcg_temp_free_i32(t3); | ||
62 | return true; | ||
87 | } | 63 | } |
88 | 64 | ||
89 | -/* | 65 | static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a) |
90 | - * Get Combiner input GPIO into irqs structure | 66 | { |
91 | - */ | 67 | TCGv_i64 op0, op1, diff, t1, tmax; |
92 | -static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, | 68 | - TCGv_i32 t2, t3; |
93 | - DeviceState *dev, int ext) | 69 | + TCGv_i32 t2; |
94 | -{ | 70 | TCGv_ptr ptr; |
95 | - int n; | 71 | unsigned vsz = vec_full_reg_size(s); |
96 | - int max; | 72 | unsigned desc = 0; |
97 | - qemu_irq *irq; | 73 | @@ -XXX,XX +XXX,XX @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a) |
98 | - | 74 | op0 = read_cpu_reg(s, a->rn, 1); |
99 | - max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ : | 75 | op1 = read_cpu_reg(s, a->rm, 1); |
100 | - EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; | 76 | |
101 | - irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq; | 77 | - tmax = tcg_const_i64(vsz); |
102 | - | 78 | + tmax = tcg_constant_i64(vsz); |
103 | - for (n = 0; n < max; n++) { | 79 | diff = tcg_temp_new_i64(); |
104 | - irq[n] = qdev_get_gpio_in(dev, n); | 80 | |
105 | - } | 81 | if (a->rw) { |
106 | -} | 82 | @@ -XXX,XX +XXX,XX @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a) |
107 | - | 83 | |
108 | static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, | 84 | /* Bound to the maximum. */ |
109 | 0x09, 0x00, 0x00, 0x00 }; | 85 | tcg_gen_umin_i64(diff, diff, tmax); |
110 | 86 | - tcg_temp_free_i64(tmax); | |
111 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | 87 | |
112 | sysbus_connect_irq(busdev, n, | 88 | /* Since we're bounded, pass as a 32-bit type. */ |
113 | qdev_get_gpio_in(DEVICE(&s->a9mpcore), n)); | 89 | t2 = tcg_temp_new_i32(); |
114 | } | 90 | @@ -XXX,XX +XXX,XX @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a) |
115 | - exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->int_combiner), 0); | 91 | |
116 | sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); | 92 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8); |
117 | 93 | desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); | |
118 | /* External Interrupt Combiner */ | 94 | - t3 = tcg_const_i32(desc); |
119 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | 95 | |
120 | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { | 96 | ptr = tcg_temp_new_ptr(); |
121 | sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n)); | 97 | tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd)); |
122 | } | 98 | |
123 | - exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->ext_combiner), 1); | 99 | - gen_helper_sve_whilel(t2, ptr, t2, t3); |
124 | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); | 100 | + gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc)); |
125 | 101 | do_pred_flags(t2); | |
126 | /* Initialize board IRQs. */ | 102 | |
103 | tcg_temp_free_ptr(ptr); | ||
104 | tcg_temp_free_i32(t2); | ||
105 | - tcg_temp_free_i32(t3); | ||
106 | return true; | ||
107 | } | ||
108 | |||
127 | -- | 109 | -- |
128 | 2.25.1 | 110 | 2.25.1 | diff view generated by jsdifflib |
1 | From: "Edgar E. Iglesias" <edgar.iglesias@amd.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Connect the 4 TTC timers on the ZynqMP. | 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
4 | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | |
5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> | 5 | Message-id: 20220426163043.100432-43-richard.henderson@linaro.org |
6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
7 | Reviewed-by: Luc Michel <luc@lmichel.fr> | ||
8 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> | ||
9 | Message-id: 20220331222017.2914409-3-edgar.iglesias@gmail.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 7 | --- |
12 | include/hw/arm/xlnx-zynqmp.h | 4 ++++ | 8 | target/arm/translate-sve.c | 12 ++++-------- |
13 | hw/arm/xlnx-zynqmp.c | 22 ++++++++++++++++++++++ | 9 | 1 file changed, 4 insertions(+), 8 deletions(-) |
14 | 2 files changed, 26 insertions(+) | ||
15 | 10 | ||
16 | diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h | 11 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c |
17 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/arm/xlnx-zynqmp.h | 13 | --- a/target/arm/translate-sve.c |
19 | +++ b/include/hw/arm/xlnx-zynqmp.h | 14 | +++ b/target/arm/translate-sve.c |
20 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a) |
21 | #include "hw/or-irq.h" | 16 | gen_helper_gvec_mem_scatter *fn = NULL; |
22 | #include "hw/misc/xlnx-zynqmp-apu-ctrl.h" | 17 | bool be = s->be_data == MO_BE; |
23 | #include "hw/misc/xlnx-zynqmp-crf.h" | 18 | bool mte = s->mte_active[0]; |
24 | +#include "hw/timer/cadence_ttc.h" | 19 | - TCGv_i64 imm; |
25 | 20 | ||
26 | #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" | 21 | if (a->esz < a->msz || (a->esz == a->msz && !a->u)) { |
27 | OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) | 22 | return false; |
28 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) | 23 | @@ -XXX,XX +XXX,XX @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a) |
29 | #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \ | 24 | /* Treat LD1_zpiz (zn[x] + imm) the same way as LD1_zprz (rn + zm[x]) |
30 | XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE) | 25 | * by loading the immediate into the scalar parameter. |
31 | 26 | */ | |
32 | +#define XLNX_ZYNQMP_NUM_TTC 4 | 27 | - imm = tcg_const_i64(a->imm << a->msz); |
33 | + | 28 | - do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, a->msz, false, fn); |
34 | /* | 29 | - tcg_temp_free_i64(imm); |
35 | * Unimplemented mmio regions needed to boot some images. | 30 | + do_mem_zpz(s, a->rd, a->pg, a->rn, 0, |
36 | */ | 31 | + tcg_constant_i64(a->imm << a->msz), a->msz, false, fn); |
37 | @@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState { | 32 | return true; |
38 | qemu_or_irq qspi_irq_orgate; | ||
39 | XlnxZynqMPAPUCtrl apu_ctrl; | ||
40 | XlnxZynqMPCRF crf; | ||
41 | + CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC]; | ||
42 | |||
43 | char *boot_cpu; | ||
44 | ARMCPU *boot_cpu_ptr; | ||
45 | diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c | ||
46 | index XXXXXXX..XXXXXXX 100644 | ||
47 | --- a/hw/arm/xlnx-zynqmp.c | ||
48 | +++ b/hw/arm/xlnx-zynqmp.c | ||
49 | @@ -XXX,XX +XXX,XX @@ | ||
50 | #define APU_ADDR 0xfd5c0000 | ||
51 | #define APU_IRQ 153 | ||
52 | |||
53 | +#define TTC0_ADDR 0xFF110000 | ||
54 | +#define TTC0_IRQ 36 | ||
55 | + | ||
56 | #define IPI_ADDR 0xFF300000 | ||
57 | #define IPI_IRQ 64 | ||
58 | |||
59 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic) | ||
60 | sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]); | ||
61 | } | 33 | } |
62 | 34 | ||
63 | +static void xlnx_zynqmp_create_ttc(XlnxZynqMPState *s, qemu_irq *gic) | 35 | @@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a) |
64 | +{ | 36 | gen_helper_gvec_mem_scatter *fn = NULL; |
65 | + SysBusDevice *sbd; | 37 | bool be = s->be_data == MO_BE; |
66 | + int i, irq; | 38 | bool mte = s->mte_active[0]; |
67 | + | 39 | - TCGv_i64 imm; |
68 | + for (i = 0; i < XLNX_ZYNQMP_NUM_TTC; i++) { | 40 | |
69 | + object_initialize_child(OBJECT(s), "ttc[*]", &s->ttc[i], | 41 | if (a->esz < a->msz) { |
70 | + TYPE_CADENCE_TTC); | 42 | return false; |
71 | + sbd = SYS_BUS_DEVICE(&s->ttc[i]); | 43 | @@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a) |
72 | + | 44 | /* Treat ST1_zpiz (zn[x] + imm) the same way as ST1_zprz (rn + zm[x]) |
73 | + sysbus_realize(sbd, &error_fatal); | 45 | * by loading the immediate into the scalar parameter. |
74 | + sysbus_mmio_map(sbd, 0, TTC0_ADDR + i * 0x10000); | 46 | */ |
75 | + for (irq = 0; irq < 3; irq++) { | 47 | - imm = tcg_const_i64(a->imm << a->msz); |
76 | + sysbus_connect_irq(sbd, irq, gic[TTC0_IRQ + i * 3 + irq]); | 48 | - do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, a->msz, true, fn); |
77 | + } | 49 | - tcg_temp_free_i64(imm); |
78 | + } | 50 | + do_mem_zpz(s, a->rd, a->pg, a->rn, 0, |
79 | +} | 51 | + tcg_constant_i64(a->imm << a->msz), a->msz, true, fn); |
80 | + | 52 | return true; |
81 | static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) | 53 | } |
82 | { | 54 | |
83 | static const struct UnimpInfo { | ||
84 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) | ||
85 | xlnx_zynqmp_create_efuse(s, gic_spi); | ||
86 | xlnx_zynqmp_create_apu_ctrl(s, gic_spi); | ||
87 | xlnx_zynqmp_create_crf(s, gic_spi); | ||
88 | + xlnx_zynqmp_create_ttc(s, gic_spi); | ||
89 | xlnx_zynqmp_create_unimp_mmio(s); | ||
90 | |||
91 | for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { | ||
92 | -- | 55 | -- |
93 | 2.25.1 | 56 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Zongyuan Li <zongyuan.li@smartx.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com> | 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Message-id: 20220324181557.203805-3-zongyuan.li@smartx.com | 5 | Message-id: 20220426163043.100432-44-richard.henderson@linaro.org |
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 7 | --- |
8 | hw/arm/stellaris.c | 15 +++++++++++++-- | 8 | target/arm/translate-sve.c | 4 +--- |
9 | 1 file changed, 13 insertions(+), 2 deletions(-) | 9 | 1 file changed, 1 insertion(+), 3 deletions(-) |
10 | 10 | ||
11 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c | 11 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c |
12 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/arm/stellaris.c | 13 | --- a/target/arm/translate-sve.c |
14 | +++ b/hw/arm/stellaris.c | 14 | +++ b/target/arm/translate-sve.c |
15 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a) |
16 | 16 | } | |
17 | #include "qemu/osdep.h" | 17 | if (sve_access_check(s)) { |
18 | #include "qapi/error.h" | 18 | unsigned vsz = vec_full_reg_size(s); |
19 | +#include "hw/core/split-irq.h" | 19 | - TCGv_i64 c = tcg_const_i64(a->imm); |
20 | #include "hw/sysbus.h" | 20 | tcg_gen_gvec_2s(vec_full_reg_offset(s, a->rd), |
21 | #include "hw/sd/sd.h" | 21 | vec_full_reg_offset(s, a->rn), |
22 | #include "hw/ssi/ssi.h" | 22 | - vsz, vsz, c, &op[a->esz]); |
23 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) | 23 | - tcg_temp_free_i64(c); |
24 | DeviceState *ssddev; | 24 | + vsz, vsz, tcg_constant_i64(a->imm), &op[a->esz]); |
25 | DriveInfo *dinfo; | 25 | } |
26 | DeviceState *carddev; | 26 | return true; |
27 | + DeviceState *gpio_d_splitter; | 27 | } |
28 | BlockBackend *blk; | ||
29 | |||
30 | /* | ||
31 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) | ||
32 | &error_fatal); | ||
33 | |||
34 | ssddev = ssi_create_peripheral(bus, "ssd0323"); | ||
35 | - gpio_out[GPIO_D][0] = qemu_irq_split( | ||
36 | - qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0), | ||
37 | + | ||
38 | + gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ); | ||
39 | + qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2); | ||
40 | + qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal); | ||
41 | + qdev_connect_gpio_out( | ||
42 | + gpio_d_splitter, 0, | ||
43 | + qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0)); | ||
44 | + qdev_connect_gpio_out( | ||
45 | + gpio_d_splitter, 1, | ||
46 | qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); | ||
47 | + gpio_out[GPIO_D][0] = qdev_get_gpio_in(gpio_d_splitter, 0); | ||
48 | + | ||
49 | gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); | ||
50 | |||
51 | /* Make sure the select pin is high. */ | ||
52 | -- | 28 | -- |
53 | 2.25.1 | 29 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Zongyuan Li <zongyuan.li@smartx.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com> | 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Message-id: 20220324181557.203805-2-zongyuan.li@smartx.com | 5 | Message-id: 20220426163043.100432-45-richard.henderson@linaro.org |
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 7 | --- |
8 | hw/arm/realview.c | 33 ++++++++++++++++++++++++--------- | 8 | target/arm/translate-sve.c | 15 +++++---------- |
9 | 1 file changed, 24 insertions(+), 9 deletions(-) | 9 | 1 file changed, 5 insertions(+), 10 deletions(-) |
10 | 10 | ||
11 | diff --git a/hw/arm/realview.c b/hw/arm/realview.c | 11 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c |
12 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/arm/realview.c | 13 | --- a/target/arm/translate-sve.c |
14 | +++ b/hw/arm/realview.c | 14 | +++ b/target/arm/translate-sve.c |
15 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, bool u, bool d) |
16 | #include "hw/sysbus.h" | 16 | return false; |
17 | #include "hw/arm/boot.h" | 17 | } |
18 | #include "hw/arm/primecell.h" | 18 | if (sve_access_check(s)) { |
19 | +#include "hw/core/split-irq.h" | 19 | - TCGv_i64 val = tcg_const_i64(a->imm); |
20 | #include "hw/net/lan9118.h" | 20 | - do_sat_addsub_vec(s, a->esz, a->rd, a->rn, val, u, d); |
21 | #include "hw/net/smc91c111.h" | 21 | - tcg_temp_free_i64(val); |
22 | #include "hw/pci/pci.h" | 22 | + do_sat_addsub_vec(s, a->esz, a->rd, a->rn, |
23 | +#include "hw/qdev-core.h" | 23 | + tcg_constant_i64(a->imm), u, d); |
24 | #include "net/net.h" | 24 | } |
25 | #include "sysemu/sysemu.h" | 25 | return true; |
26 | #include "hw/boards.h" | 26 | } |
27 | @@ -XXX,XX +XXX,XX @@ static const int realview_board_id[] = { | 27 | @@ -XXX,XX +XXX,XX @@ static bool do_zzi_ool(DisasContext *s, arg_rri_esz *a, gen_helper_gvec_2i *fn) |
28 | 0x76d | ||
29 | }; | ||
30 | |||
31 | +static void split_irq_from_named(DeviceState *src, const char* outname, | ||
32 | + qemu_irq out1, qemu_irq out2) { | ||
33 | + DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ); | ||
34 | + | ||
35 | + qdev_prop_set_uint32(splitter, "num-lines", 2); | ||
36 | + | ||
37 | + qdev_realize_and_unref(splitter, NULL, &error_fatal); | ||
38 | + | ||
39 | + qdev_connect_gpio_out(splitter, 0, out1); | ||
40 | + qdev_connect_gpio_out(splitter, 1, out2); | ||
41 | + qdev_connect_gpio_out_named(src, outname, 0, | ||
42 | + qdev_get_gpio_in(splitter, 0)); | ||
43 | +} | ||
44 | + | ||
45 | static void realview_init(MachineState *machine, | ||
46 | enum realview_board_type board_type) | ||
47 | { | 28 | { |
48 | @@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine, | 29 | if (sve_access_check(s)) { |
49 | DeviceState *dev, *sysctl, *gpio2, *pl041; | 30 | unsigned vsz = vec_full_reg_size(s); |
50 | SysBusDevice *busdev; | 31 | - TCGv_i64 c = tcg_const_i64(a->imm); |
51 | qemu_irq pic[64]; | 32 | - |
52 | - qemu_irq mmc_irq[2]; | 33 | tcg_gen_gvec_2i_ool(vec_full_reg_offset(s, a->rd), |
53 | PCIBus *pci_bus = NULL; | 34 | vec_full_reg_offset(s, a->rn), |
54 | NICInfo *nd; | 35 | - c, vsz, vsz, 0, fn); |
55 | DriveInfo *dinfo; | 36 | - tcg_temp_free_i64(c); |
56 | @@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine, | 37 | + tcg_constant_i64(a->imm), vsz, vsz, 0, fn); |
57 | * and the PL061 has them the other way about. Also the card | 38 | } |
58 | * detect line is inverted. | 39 | return true; |
59 | */ | 40 | } |
60 | - mmc_irq[0] = qemu_irq_split( | 41 | @@ -XXX,XX +XXX,XX @@ static void do_fp_scalar(DisasContext *s, int zd, int zn, int pg, bool is_fp16, |
61 | - qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), | 42 | static void do_fp_imm(DisasContext *s, arg_rpri_esz *a, uint64_t imm, |
62 | - qdev_get_gpio_in(gpio2, 1)); | 43 | gen_helper_sve_fp2scalar *fn) |
63 | - mmc_irq[1] = qemu_irq_split( | 44 | { |
64 | - qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), | 45 | - TCGv_i64 temp = tcg_const_i64(imm); |
65 | - qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); | 46 | - do_fp_scalar(s, a->rd, a->rn, a->pg, a->esz == MO_16, temp, fn); |
66 | - qdev_connect_gpio_out_named(dev, "card-read-only", 0, mmc_irq[0]); | 47 | - tcg_temp_free_i64(temp); |
67 | - qdev_connect_gpio_out_named(dev, "card-inserted", 0, mmc_irq[1]); | 48 | + do_fp_scalar(s, a->rd, a->rn, a->pg, a->esz == MO_16, |
68 | + split_irq_from_named(dev, "card-read-only", | 49 | + tcg_constant_i64(imm), fn); |
69 | + qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), | 50 | } |
70 | + qdev_get_gpio_in(gpio2, 1)); | 51 | |
71 | + | 52 | #define DO_FP_IMM(NAME, name, const0, const1) \ |
72 | + split_irq_from_named(dev, "card-inserted", | ||
73 | + qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), | ||
74 | + qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); | ||
75 | + | ||
76 | dinfo = drive_get(IF_SD, 0, 0); | ||
77 | if (dinfo) { | ||
78 | DeviceState *card; | ||
79 | -- | 53 | -- |
80 | 2.25.1 | 54 | 2.25.1 | diff view generated by jsdifflib |
1 | The Exynos4210 SoC device currently uses a custom device | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | "exynos4210.irq_gate" to model the OR gate that feeds each CPU's IRQ | ||
3 | line. We have a standard TYPE_OR_IRQ device for this now, so use | ||
4 | that instead. | ||
5 | 2 | ||
6 | (This is a migration compatibility break, but that is OK for this | 3 | In these cases, 't' did double-duty as zero source and |
7 | machine type.) | 4 | temporary destination. Split the two uses. |
8 | 5 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Message-id: 20220426163043.100432-46-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20220404154658.565020-2-peter.maydell@linaro.org | ||
12 | --- | 10 | --- |
13 | include/hw/arm/exynos4210.h | 1 + | 11 | target/arm/translate-sve.c | 17 ++++++++--------- |
14 | hw/arm/exynos4210.c | 31 ++++++++++++++++--------------- | 12 | 1 file changed, 8 insertions(+), 9 deletions(-) |
15 | 2 files changed, 17 insertions(+), 15 deletions(-) | ||
16 | 13 | ||
17 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | 14 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c |
18 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/include/hw/arm/exynos4210.h | 16 | --- a/target/arm/translate-sve.c |
20 | +++ b/include/hw/arm/exynos4210.h | 17 | +++ b/target/arm/translate-sve.c |
21 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { | 18 | @@ -XXX,XX +XXX,XX @@ static void do_predtest(DisasContext *s, int dofs, int gofs, int words) |
22 | MemoryRegion bootreg_mem; | ||
23 | I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; | ||
24 | qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; | ||
25 | + qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; | ||
26 | }; | ||
27 | |||
28 | #define TYPE_EXYNOS4210_SOC "exynos4210" | ||
29 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/hw/arm/exynos4210.c | ||
32 | +++ b/hw/arm/exynos4210.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
34 | { | 19 | { |
35 | Exynos4210State *s = EXYNOS4210_SOC(socdev); | 20 | TCGv_ptr dptr = tcg_temp_new_ptr(); |
36 | MemoryRegion *system_mem = get_system_memory(); | 21 | TCGv_ptr gptr = tcg_temp_new_ptr(); |
37 | - qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; | 22 | - TCGv_i32 t; |
38 | SysBusDevice *busdev; | 23 | + TCGv_i32 t = tcg_temp_new_i32(); |
39 | DeviceState *dev, *uart[4], *pl330[3]; | 24 | |
40 | int i, n; | 25 | tcg_gen_addi_ptr(dptr, cpu_env, dofs); |
41 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | 26 | tcg_gen_addi_ptr(gptr, cpu_env, gofs); |
42 | 27 | - t = tcg_const_i32(words); | |
43 | /* IRQ Gate */ | 28 | |
44 | for (i = 0; i < EXYNOS4210_NCPUS; i++) { | 29 | - gen_helper_sve_predtest(t, dptr, gptr, t); |
45 | - dev = qdev_new("exynos4210.irq_gate"); | 30 | + gen_helper_sve_predtest(t, dptr, gptr, tcg_constant_i32(words)); |
46 | - qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS); | 31 | tcg_temp_free_ptr(dptr); |
47 | - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | 32 | tcg_temp_free_ptr(gptr); |
48 | - /* Get IRQ Gate input in gate_irq */ | 33 | |
49 | - for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) { | 34 | @@ -XXX,XX +XXX,XX @@ static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a, |
50 | - gate_irq[i][n] = qdev_get_gpio_in(dev, n); | 35 | |
51 | - } | 36 | tcg_gen_addi_ptr(t_pd, cpu_env, pred_full_reg_offset(s, a->rd)); |
52 | - busdev = SYS_BUS_DEVICE(dev); | 37 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->rn)); |
53 | - | 38 | - t = tcg_const_i32(desc); |
54 | - /* Connect IRQ Gate output to CPU's IRQ line */ | 39 | + t = tcg_temp_new_i32(); |
55 | - sysbus_connect_irq(busdev, 0, | 40 | |
56 | - qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); | 41 | - gen_fn(t, t_pd, t_pg, t); |
57 | + DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]); | 42 | + gen_fn(t, t_pd, t_pg, tcg_constant_i32(desc)); |
58 | + object_property_set_int(OBJECT(orgate), "num-lines", | 43 | tcg_temp_free_ptr(t_pd); |
59 | + EXYNOS4210_IRQ_GATE_NINPUTS, | 44 | tcg_temp_free_ptr(t_pg); |
60 | + &error_abort); | 45 | |
61 | + qdev_realize(orgate, NULL, &error_abort); | 46 | @@ -XXX,XX +XXX,XX @@ static bool do_ppzz_flags(DisasContext *s, arg_rprr_esz *a, |
62 | + qdev_connect_gpio_out(orgate, 0, | ||
63 | + qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); | ||
64 | } | 47 | } |
65 | 48 | ||
66 | /* Private memory region and Internal GIC */ | 49 | vsz = vec_full_reg_size(s); |
67 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | 50 | - t = tcg_const_i32(simd_desc(vsz, vsz, 0)); |
68 | sysbus_realize_and_unref(busdev, &error_fatal); | 51 | + t = tcg_temp_new_i32(); |
69 | sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); | 52 | pd = tcg_temp_new_ptr(); |
70 | for (n = 0; n < EXYNOS4210_NCPUS; n++) { | 53 | zn = tcg_temp_new_ptr(); |
71 | - sysbus_connect_irq(busdev, n, gate_irq[n][0]); | 54 | zm = tcg_temp_new_ptr(); |
72 | + sysbus_connect_irq(busdev, n, | 55 | @@ -XXX,XX +XXX,XX @@ static bool do_ppzz_flags(DisasContext *s, arg_rprr_esz *a, |
73 | + qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0)); | 56 | tcg_gen_addi_ptr(zm, cpu_env, vec_full_reg_offset(s, a->rm)); |
57 | tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg)); | ||
58 | |||
59 | - gen_fn(t, pd, zn, zm, pg, t); | ||
60 | + gen_fn(t, pd, zn, zm, pg, tcg_constant_i32(simd_desc(vsz, vsz, 0))); | ||
61 | |||
62 | tcg_temp_free_ptr(pd); | ||
63 | tcg_temp_free_ptr(zn); | ||
64 | @@ -XXX,XX +XXX,XX @@ static bool do_ppzi_flags(DisasContext *s, arg_rpri_esz *a, | ||
74 | } | 65 | } |
75 | for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { | 66 | |
76 | s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n); | 67 | vsz = vec_full_reg_size(s); |
77 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | 68 | - t = tcg_const_i32(simd_desc(vsz, vsz, a->imm)); |
78 | /* Map Distributer interface */ | 69 | + t = tcg_temp_new_i32(); |
79 | sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR); | 70 | pd = tcg_temp_new_ptr(); |
80 | for (n = 0; n < EXYNOS4210_NCPUS; n++) { | 71 | zn = tcg_temp_new_ptr(); |
81 | - sysbus_connect_irq(busdev, n, gate_irq[n][1]); | 72 | pg = tcg_temp_new_ptr(); |
82 | + sysbus_connect_irq(busdev, n, | 73 | @@ -XXX,XX +XXX,XX @@ static bool do_ppzi_flags(DisasContext *s, arg_rpri_esz *a, |
83 | + qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1)); | 74 | tcg_gen_addi_ptr(zn, cpu_env, vec_full_reg_offset(s, a->rn)); |
84 | } | 75 | tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg)); |
85 | for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { | 76 | |
86 | s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n); | 77 | - gen_fn(t, pd, zn, pg, t); |
87 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj) | 78 | + gen_fn(t, pd, zn, pg, tcg_constant_i32(simd_desc(vsz, vsz, a->imm))); |
88 | object_initialize_child(obj, name, orgate, TYPE_OR_IRQ); | 79 | |
89 | g_free(name); | 80 | tcg_temp_free_ptr(pd); |
90 | } | 81 | tcg_temp_free_ptr(zn); |
91 | + | ||
92 | + for (i = 0; i < ARRAY_SIZE(s->cpu_irq_orgate); i++) { | ||
93 | + g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i); | ||
94 | + object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ); | ||
95 | + } | ||
96 | } | ||
97 | |||
98 | static void exynos4210_class_init(ObjectClass *klass, void *data) | ||
99 | -- | 82 | -- |
100 | 2.25.1 | 83 | 2.25.1 | diff view generated by jsdifflib |
1 | From: "Edgar E. Iglesias" <edgar.iglesias@amd.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Connect the CRL (Clock Reset LPD) to the Versal SoC. | 3 | In these cases, 't' did double-duty as zero source and |
4 | temporary destination. Split the two uses and narrow | ||
5 | the scope of the temp. | ||
4 | 6 | ||
5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Reviewed-by: Frederic Konrad <fkonrad@amd.com> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | 9 | Message-id: 20220426163043.100432-47-richard.henderson@linaro.org |
8 | Message-id: 20220406174303.2022038-5-edgar.iglesias@xilinx.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 11 | --- |
11 | include/hw/arm/xlnx-versal.h | 4 +++ | 12 | target/arm/translate-sve.c | 18 ++++++++++-------- |
12 | hw/arm/xlnx-versal.c | 54 ++++++++++++++++++++++++++++++++++-- | 13 | 1 file changed, 10 insertions(+), 8 deletions(-) |
13 | 2 files changed, 56 insertions(+), 2 deletions(-) | ||
14 | 14 | ||
15 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h | 15 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c |
16 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/include/hw/arm/xlnx-versal.h | 17 | --- a/target/arm/translate-sve.c |
18 | +++ b/include/hw/arm/xlnx-versal.h | 18 | +++ b/target/arm/translate-sve.c |
19 | @@ -XXX,XX +XXX,XX @@ | 19 | @@ -XXX,XX +XXX,XX @@ static bool do_brk3(DisasContext *s, arg_rprr_s *a, |
20 | #include "hw/nvram/xlnx-versal-efuse.h" | 20 | TCGv_ptr n = tcg_temp_new_ptr(); |
21 | #include "hw/ssi/xlnx-versal-ospi.h" | 21 | TCGv_ptr m = tcg_temp_new_ptr(); |
22 | #include "hw/dma/xlnx_csu_dma.h" | 22 | TCGv_ptr g = tcg_temp_new_ptr(); |
23 | +#include "hw/misc/xlnx-versal-crl.h" | 23 | - TCGv_i32 t = tcg_const_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz)); |
24 | #include "hw/misc/xlnx-versal-pmc-iou-slcr.h" | 24 | + TCGv_i32 desc = tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz)); |
25 | 25 | ||
26 | #define TYPE_XLNX_VERSAL "xlnx-versal" | 26 | tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd)); |
27 | @@ -XXX,XX +XXX,XX @@ struct Versal { | 27 | tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn)); |
28 | qemu_or_irq irq_orgate; | 28 | @@ -XXX,XX +XXX,XX @@ static bool do_brk3(DisasContext *s, arg_rprr_s *a, |
29 | XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; | 29 | tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg)); |
30 | } xram; | 30 | |
31 | + | 31 | if (a->s) { |
32 | + XlnxVersalCRL crl; | 32 | - fn_s(t, d, n, m, g, t); |
33 | } lpd; | 33 | + TCGv_i32 t = tcg_temp_new_i32(); |
34 | 34 | + fn_s(t, d, n, m, g, desc); | |
35 | /* The Platform Management Controller subsystem. */ | 35 | do_pred_flags(t); |
36 | @@ -XXX,XX +XXX,XX @@ struct Versal { | 36 | + tcg_temp_free_i32(t); |
37 | #define VERSAL_TIMER_NS_EL1_IRQ 14 | 37 | } else { |
38 | #define VERSAL_TIMER_NS_EL2_IRQ 10 | 38 | - fn(d, n, m, g, t); |
39 | 39 | + fn(d, n, m, g, desc); | |
40 | +#define VERSAL_CRL_IRQ 10 | 40 | } |
41 | #define VERSAL_UART0_IRQ_0 18 | 41 | tcg_temp_free_ptr(d); |
42 | #define VERSAL_UART1_IRQ_0 19 | 42 | tcg_temp_free_ptr(n); |
43 | #define VERSAL_USB0_IRQ_0 22 | 43 | tcg_temp_free_ptr(m); |
44 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | 44 | tcg_temp_free_ptr(g); |
45 | index XXXXXXX..XXXXXXX 100644 | 45 | - tcg_temp_free_i32(t); |
46 | --- a/hw/arm/xlnx-versal.c | 46 | return true; |
47 | +++ b/hw/arm/xlnx-versal.c | ||
48 | @@ -XXX,XX +XXX,XX @@ static void versal_create_ospi(Versal *s, qemu_irq *pic) | ||
49 | qdev_connect_gpio_out(orgate, 0, pic[VERSAL_OSPI_IRQ]); | ||
50 | } | 47 | } |
51 | 48 | ||
52 | +static void versal_create_crl(Versal *s, qemu_irq *pic) | 49 | @@ -XXX,XX +XXX,XX @@ static bool do_brk2(DisasContext *s, arg_rpr_s *a, |
53 | +{ | 50 | TCGv_ptr d = tcg_temp_new_ptr(); |
54 | + SysBusDevice *sbd; | 51 | TCGv_ptr n = tcg_temp_new_ptr(); |
55 | + int i; | 52 | TCGv_ptr g = tcg_temp_new_ptr(); |
56 | + | 53 | - TCGv_i32 t = tcg_const_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz)); |
57 | + object_initialize_child(OBJECT(s), "crl", &s->lpd.crl, | 54 | + TCGv_i32 desc = tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz)); |
58 | + TYPE_XLNX_VERSAL_CRL); | 55 | |
59 | + sbd = SYS_BUS_DEVICE(&s->lpd.crl); | 56 | tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd)); |
60 | + | 57 | tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn)); |
61 | + for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) { | 58 | tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg)); |
62 | + g_autofree gchar *name = g_strdup_printf("cpu_r5[%d]", i); | 59 | |
63 | + | 60 | if (a->s) { |
64 | + object_property_set_link(OBJECT(&s->lpd.crl), | 61 | - fn_s(t, d, n, g, t); |
65 | + name, OBJECT(&s->lpd.rpu.cpu[i]), | 62 | + TCGv_i32 t = tcg_temp_new_i32(); |
66 | + &error_abort); | 63 | + fn_s(t, d, n, g, desc); |
67 | + } | 64 | do_pred_flags(t); |
68 | + | 65 | + tcg_temp_free_i32(t); |
69 | + for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) { | 66 | } else { |
70 | + g_autofree gchar *name = g_strdup_printf("gem[%d]", i); | 67 | - fn(d, n, g, t); |
71 | + | 68 | + fn(d, n, g, desc); |
72 | + object_property_set_link(OBJECT(&s->lpd.crl), | 69 | } |
73 | + name, OBJECT(&s->lpd.iou.gem[i]), | 70 | tcg_temp_free_ptr(d); |
74 | + &error_abort); | 71 | tcg_temp_free_ptr(n); |
75 | + } | 72 | tcg_temp_free_ptr(g); |
76 | + | 73 | - tcg_temp_free_i32(t); |
77 | + for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) { | 74 | return true; |
78 | + g_autofree gchar *name = g_strdup_printf("adma[%d]", i); | 75 | } |
79 | + | ||
80 | + object_property_set_link(OBJECT(&s->lpd.crl), | ||
81 | + name, OBJECT(&s->lpd.iou.adma[i]), | ||
82 | + &error_abort); | ||
83 | + } | ||
84 | + | ||
85 | + for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) { | ||
86 | + g_autofree gchar *name = g_strdup_printf("uart[%d]", i); | ||
87 | + | ||
88 | + object_property_set_link(OBJECT(&s->lpd.crl), | ||
89 | + name, OBJECT(&s->lpd.iou.uart[i]), | ||
90 | + &error_abort); | ||
91 | + } | ||
92 | + | ||
93 | + object_property_set_link(OBJECT(&s->lpd.crl), | ||
94 | + "usb", OBJECT(&s->lpd.iou.usb), | ||
95 | + &error_abort); | ||
96 | + | ||
97 | + sysbus_realize(sbd, &error_fatal); | ||
98 | + memory_region_add_subregion(&s->mr_ps, MM_CRL, | ||
99 | + sysbus_mmio_get_region(sbd, 0)); | ||
100 | + sysbus_connect_irq(sbd, 0, pic[VERSAL_CRL_IRQ]); | ||
101 | +} | ||
102 | + | ||
103 | /* This takes the board allocated linear DDR memory and creates aliases | ||
104 | * for each split DDR range/aperture on the Versal address map. | ||
105 | */ | ||
106 | @@ -XXX,XX +XXX,XX @@ static void versal_unimp(Versal *s) | ||
107 | |||
108 | versal_unimp_area(s, "psm", &s->mr_ps, | ||
109 | MM_PSM_START, MM_PSM_END - MM_PSM_START); | ||
110 | - versal_unimp_area(s, "crl", &s->mr_ps, | ||
111 | - MM_CRL, MM_CRL_SIZE); | ||
112 | versal_unimp_area(s, "crf", &s->mr_ps, | ||
113 | MM_FPD_CRF, MM_FPD_CRF_SIZE); | ||
114 | versal_unimp_area(s, "apu", &s->mr_ps, | ||
115 | @@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp) | ||
116 | versal_create_efuse(s, pic); | ||
117 | versal_create_pmc_iou_slcr(s, pic); | ||
118 | versal_create_ospi(s, pic); | ||
119 | + versal_create_crl(s, pic); | ||
120 | versal_map_ddr(s); | ||
121 | versal_unimp(s); | ||
122 | 76 | ||
123 | -- | 77 | -- |
124 | 2.25.1 | 78 | 2.25.1 | diff view generated by jsdifflib |
1 | From: "Edgar E. Iglesias" <edgar.iglesias@amd.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Add a model of the Xilinx Versal CRL. | 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
4 | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | |
5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> | 5 | Message-id: 20220426163043.100432-48-richard.henderson@linaro.org |
6 | Reviewed-by: Frederic Konrad <fkonrad@amd.com> | ||
7 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | ||
8 | Message-id: 20220406174303.2022038-4-edgar.iglesias@xilinx.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 7 | --- |
11 | include/hw/misc/xlnx-versal-crl.h | 235 +++++++++++++++++ | 8 | target/arm/translate-sve.c | 54 ++++++++++---------------------------- |
12 | hw/misc/xlnx-versal-crl.c | 421 ++++++++++++++++++++++++++++++ | 9 | 1 file changed, 14 insertions(+), 40 deletions(-) |
13 | hw/misc/meson.build | 1 + | ||
14 | 3 files changed, 657 insertions(+) | ||
15 | create mode 100644 include/hw/misc/xlnx-versal-crl.h | ||
16 | create mode 100644 hw/misc/xlnx-versal-crl.c | ||
17 | 10 | ||
18 | diff --git a/include/hw/misc/xlnx-versal-crl.h b/include/hw/misc/xlnx-versal-crl.h | 11 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c |
19 | new file mode 100644 | ||
20 | index XXXXXXX..XXXXXXX | ||
21 | --- /dev/null | ||
22 | +++ b/include/hw/misc/xlnx-versal-crl.h | ||
23 | @@ -XXX,XX +XXX,XX @@ | ||
24 | +/* | ||
25 | + * QEMU model of the Clock-Reset-LPD (CRL). | ||
26 | + * | ||
27 | + * Copyright (c) 2022 Xilinx Inc. | ||
28 | + * SPDX-License-Identifier: GPL-2.0-or-later | ||
29 | + * | ||
30 | + * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
31 | + */ | ||
32 | +#ifndef HW_MISC_XLNX_VERSAL_CRL_H | ||
33 | +#define HW_MISC_XLNX_VERSAL_CRL_H | ||
34 | + | ||
35 | +#include "hw/sysbus.h" | ||
36 | +#include "hw/register.h" | ||
37 | +#include "target/arm/cpu.h" | ||
38 | + | ||
39 | +#define TYPE_XLNX_VERSAL_CRL "xlnx,versal-crl" | ||
40 | +OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL) | ||
41 | + | ||
42 | +REG32(ERR_CTRL, 0x0) | ||
43 | + FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1) | ||
44 | +REG32(IR_STATUS, 0x4) | ||
45 | + FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1) | ||
46 | +REG32(IR_MASK, 0x8) | ||
47 | + FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1) | ||
48 | +REG32(IR_ENABLE, 0xc) | ||
49 | + FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1) | ||
50 | +REG32(IR_DISABLE, 0x10) | ||
51 | + FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1) | ||
52 | +REG32(WPROT, 0x1c) | ||
53 | + FIELD(WPROT, ACTIVE, 0, 1) | ||
54 | +REG32(PLL_CLK_OTHER_DMN, 0x20) | ||
55 | + FIELD(PLL_CLK_OTHER_DMN, APLL_BYPASS, 0, 1) | ||
56 | +REG32(RPLL_CTRL, 0x40) | ||
57 | + FIELD(RPLL_CTRL, POST_SRC, 24, 3) | ||
58 | + FIELD(RPLL_CTRL, PRE_SRC, 20, 3) | ||
59 | + FIELD(RPLL_CTRL, CLKOUTDIV, 16, 2) | ||
60 | + FIELD(RPLL_CTRL, FBDIV, 8, 8) | ||
61 | + FIELD(RPLL_CTRL, BYPASS, 3, 1) | ||
62 | + FIELD(RPLL_CTRL, RESET, 0, 1) | ||
63 | +REG32(RPLL_CFG, 0x44) | ||
64 | + FIELD(RPLL_CFG, LOCK_DLY, 25, 7) | ||
65 | + FIELD(RPLL_CFG, LOCK_CNT, 13, 10) | ||
66 | + FIELD(RPLL_CFG, LFHF, 10, 2) | ||
67 | + FIELD(RPLL_CFG, CP, 5, 4) | ||
68 | + FIELD(RPLL_CFG, RES, 0, 4) | ||
69 | +REG32(RPLL_FRAC_CFG, 0x48) | ||
70 | + FIELD(RPLL_FRAC_CFG, ENABLED, 31, 1) | ||
71 | + FIELD(RPLL_FRAC_CFG, SEED, 22, 3) | ||
72 | + FIELD(RPLL_FRAC_CFG, ALGRTHM, 19, 1) | ||
73 | + FIELD(RPLL_FRAC_CFG, ORDER, 18, 1) | ||
74 | + FIELD(RPLL_FRAC_CFG, DATA, 0, 16) | ||
75 | +REG32(PLL_STATUS, 0x50) | ||
76 | + FIELD(PLL_STATUS, RPLL_STABLE, 2, 1) | ||
77 | + FIELD(PLL_STATUS, RPLL_LOCK, 0, 1) | ||
78 | +REG32(RPLL_TO_XPD_CTRL, 0x100) | ||
79 | + FIELD(RPLL_TO_XPD_CTRL, CLKACT, 25, 1) | ||
80 | + FIELD(RPLL_TO_XPD_CTRL, DIVISOR0, 8, 10) | ||
81 | +REG32(LPD_TOP_SWITCH_CTRL, 0x104) | ||
82 | + FIELD(LPD_TOP_SWITCH_CTRL, CLKACT_ADMA, 26, 1) | ||
83 | + FIELD(LPD_TOP_SWITCH_CTRL, CLKACT, 25, 1) | ||
84 | + FIELD(LPD_TOP_SWITCH_CTRL, DIVISOR0, 8, 10) | ||
85 | + FIELD(LPD_TOP_SWITCH_CTRL, SRCSEL, 0, 3) | ||
86 | +REG32(LPD_LSBUS_CTRL, 0x108) | ||
87 | + FIELD(LPD_LSBUS_CTRL, CLKACT, 25, 1) | ||
88 | + FIELD(LPD_LSBUS_CTRL, DIVISOR0, 8, 10) | ||
89 | + FIELD(LPD_LSBUS_CTRL, SRCSEL, 0, 3) | ||
90 | +REG32(CPU_R5_CTRL, 0x10c) | ||
91 | + FIELD(CPU_R5_CTRL, CLKACT_OCM2, 28, 1) | ||
92 | + FIELD(CPU_R5_CTRL, CLKACT_OCM, 27, 1) | ||
93 | + FIELD(CPU_R5_CTRL, CLKACT_CORE, 26, 1) | ||
94 | + FIELD(CPU_R5_CTRL, CLKACT, 25, 1) | ||
95 | + FIELD(CPU_R5_CTRL, DIVISOR0, 8, 10) | ||
96 | + FIELD(CPU_R5_CTRL, SRCSEL, 0, 3) | ||
97 | +REG32(IOU_SWITCH_CTRL, 0x114) | ||
98 | + FIELD(IOU_SWITCH_CTRL, CLKACT, 25, 1) | ||
99 | + FIELD(IOU_SWITCH_CTRL, DIVISOR0, 8, 10) | ||
100 | + FIELD(IOU_SWITCH_CTRL, SRCSEL, 0, 3) | ||
101 | +REG32(GEM0_REF_CTRL, 0x118) | ||
102 | + FIELD(GEM0_REF_CTRL, CLKACT_RX, 27, 1) | ||
103 | + FIELD(GEM0_REF_CTRL, CLKACT_TX, 26, 1) | ||
104 | + FIELD(GEM0_REF_CTRL, CLKACT, 25, 1) | ||
105 | + FIELD(GEM0_REF_CTRL, DIVISOR0, 8, 10) | ||
106 | + FIELD(GEM0_REF_CTRL, SRCSEL, 0, 3) | ||
107 | +REG32(GEM1_REF_CTRL, 0x11c) | ||
108 | + FIELD(GEM1_REF_CTRL, CLKACT_RX, 27, 1) | ||
109 | + FIELD(GEM1_REF_CTRL, CLKACT_TX, 26, 1) | ||
110 | + FIELD(GEM1_REF_CTRL, CLKACT, 25, 1) | ||
111 | + FIELD(GEM1_REF_CTRL, DIVISOR0, 8, 10) | ||
112 | + FIELD(GEM1_REF_CTRL, SRCSEL, 0, 3) | ||
113 | +REG32(GEM_TSU_REF_CTRL, 0x120) | ||
114 | + FIELD(GEM_TSU_REF_CTRL, CLKACT, 25, 1) | ||
115 | + FIELD(GEM_TSU_REF_CTRL, DIVISOR0, 8, 10) | ||
116 | + FIELD(GEM_TSU_REF_CTRL, SRCSEL, 0, 3) | ||
117 | +REG32(USB0_BUS_REF_CTRL, 0x124) | ||
118 | + FIELD(USB0_BUS_REF_CTRL, CLKACT, 25, 1) | ||
119 | + FIELD(USB0_BUS_REF_CTRL, DIVISOR0, 8, 10) | ||
120 | + FIELD(USB0_BUS_REF_CTRL, SRCSEL, 0, 3) | ||
121 | +REG32(UART0_REF_CTRL, 0x128) | ||
122 | + FIELD(UART0_REF_CTRL, CLKACT, 25, 1) | ||
123 | + FIELD(UART0_REF_CTRL, DIVISOR0, 8, 10) | ||
124 | + FIELD(UART0_REF_CTRL, SRCSEL, 0, 3) | ||
125 | +REG32(UART1_REF_CTRL, 0x12c) | ||
126 | + FIELD(UART1_REF_CTRL, CLKACT, 25, 1) | ||
127 | + FIELD(UART1_REF_CTRL, DIVISOR0, 8, 10) | ||
128 | + FIELD(UART1_REF_CTRL, SRCSEL, 0, 3) | ||
129 | +REG32(SPI0_REF_CTRL, 0x130) | ||
130 | + FIELD(SPI0_REF_CTRL, CLKACT, 25, 1) | ||
131 | + FIELD(SPI0_REF_CTRL, DIVISOR0, 8, 10) | ||
132 | + FIELD(SPI0_REF_CTRL, SRCSEL, 0, 3) | ||
133 | +REG32(SPI1_REF_CTRL, 0x134) | ||
134 | + FIELD(SPI1_REF_CTRL, CLKACT, 25, 1) | ||
135 | + FIELD(SPI1_REF_CTRL, DIVISOR0, 8, 10) | ||
136 | + FIELD(SPI1_REF_CTRL, SRCSEL, 0, 3) | ||
137 | +REG32(CAN0_REF_CTRL, 0x138) | ||
138 | + FIELD(CAN0_REF_CTRL, CLKACT, 25, 1) | ||
139 | + FIELD(CAN0_REF_CTRL, DIVISOR0, 8, 10) | ||
140 | + FIELD(CAN0_REF_CTRL, SRCSEL, 0, 3) | ||
141 | +REG32(CAN1_REF_CTRL, 0x13c) | ||
142 | + FIELD(CAN1_REF_CTRL, CLKACT, 25, 1) | ||
143 | + FIELD(CAN1_REF_CTRL, DIVISOR0, 8, 10) | ||
144 | + FIELD(CAN1_REF_CTRL, SRCSEL, 0, 3) | ||
145 | +REG32(I2C0_REF_CTRL, 0x140) | ||
146 | + FIELD(I2C0_REF_CTRL, CLKACT, 25, 1) | ||
147 | + FIELD(I2C0_REF_CTRL, DIVISOR0, 8, 10) | ||
148 | + FIELD(I2C0_REF_CTRL, SRCSEL, 0, 3) | ||
149 | +REG32(I2C1_REF_CTRL, 0x144) | ||
150 | + FIELD(I2C1_REF_CTRL, CLKACT, 25, 1) | ||
151 | + FIELD(I2C1_REF_CTRL, DIVISOR0, 8, 10) | ||
152 | + FIELD(I2C1_REF_CTRL, SRCSEL, 0, 3) | ||
153 | +REG32(DBG_LPD_CTRL, 0x148) | ||
154 | + FIELD(DBG_LPD_CTRL, CLKACT, 25, 1) | ||
155 | + FIELD(DBG_LPD_CTRL, DIVISOR0, 8, 10) | ||
156 | + FIELD(DBG_LPD_CTRL, SRCSEL, 0, 3) | ||
157 | +REG32(TIMESTAMP_REF_CTRL, 0x14c) | ||
158 | + FIELD(TIMESTAMP_REF_CTRL, CLKACT, 25, 1) | ||
159 | + FIELD(TIMESTAMP_REF_CTRL, DIVISOR0, 8, 10) | ||
160 | + FIELD(TIMESTAMP_REF_CTRL, SRCSEL, 0, 3) | ||
161 | +REG32(CRL_SAFETY_CHK, 0x150) | ||
162 | +REG32(PSM_REF_CTRL, 0x154) | ||
163 | + FIELD(PSM_REF_CTRL, DIVISOR0, 8, 10) | ||
164 | + FIELD(PSM_REF_CTRL, SRCSEL, 0, 3) | ||
165 | +REG32(DBG_TSTMP_CTRL, 0x158) | ||
166 | + FIELD(DBG_TSTMP_CTRL, CLKACT, 25, 1) | ||
167 | + FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 10) | ||
168 | + FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3) | ||
169 | +REG32(CPM_TOPSW_REF_CTRL, 0x15c) | ||
170 | + FIELD(CPM_TOPSW_REF_CTRL, CLKACT, 25, 1) | ||
171 | + FIELD(CPM_TOPSW_REF_CTRL, DIVISOR0, 8, 10) | ||
172 | + FIELD(CPM_TOPSW_REF_CTRL, SRCSEL, 0, 3) | ||
173 | +REG32(USB3_DUAL_REF_CTRL, 0x160) | ||
174 | + FIELD(USB3_DUAL_REF_CTRL, CLKACT, 25, 1) | ||
175 | + FIELD(USB3_DUAL_REF_CTRL, DIVISOR0, 8, 10) | ||
176 | + FIELD(USB3_DUAL_REF_CTRL, SRCSEL, 0, 3) | ||
177 | +REG32(RST_CPU_R5, 0x300) | ||
178 | + FIELD(RST_CPU_R5, RESET_PGE, 4, 1) | ||
179 | + FIELD(RST_CPU_R5, RESET_AMBA, 2, 1) | ||
180 | + FIELD(RST_CPU_R5, RESET_CPU1, 1, 1) | ||
181 | + FIELD(RST_CPU_R5, RESET_CPU0, 0, 1) | ||
182 | +REG32(RST_ADMA, 0x304) | ||
183 | + FIELD(RST_ADMA, RESET, 0, 1) | ||
184 | +REG32(RST_GEM0, 0x308) | ||
185 | + FIELD(RST_GEM0, RESET, 0, 1) | ||
186 | +REG32(RST_GEM1, 0x30c) | ||
187 | + FIELD(RST_GEM1, RESET, 0, 1) | ||
188 | +REG32(RST_SPARE, 0x310) | ||
189 | + FIELD(RST_SPARE, RESET, 0, 1) | ||
190 | +REG32(RST_USB0, 0x314) | ||
191 | + FIELD(RST_USB0, RESET, 0, 1) | ||
192 | +REG32(RST_UART0, 0x318) | ||
193 | + FIELD(RST_UART0, RESET, 0, 1) | ||
194 | +REG32(RST_UART1, 0x31c) | ||
195 | + FIELD(RST_UART1, RESET, 0, 1) | ||
196 | +REG32(RST_SPI0, 0x320) | ||
197 | + FIELD(RST_SPI0, RESET, 0, 1) | ||
198 | +REG32(RST_SPI1, 0x324) | ||
199 | + FIELD(RST_SPI1, RESET, 0, 1) | ||
200 | +REG32(RST_CAN0, 0x328) | ||
201 | + FIELD(RST_CAN0, RESET, 0, 1) | ||
202 | +REG32(RST_CAN1, 0x32c) | ||
203 | + FIELD(RST_CAN1, RESET, 0, 1) | ||
204 | +REG32(RST_I2C0, 0x330) | ||
205 | + FIELD(RST_I2C0, RESET, 0, 1) | ||
206 | +REG32(RST_I2C1, 0x334) | ||
207 | + FIELD(RST_I2C1, RESET, 0, 1) | ||
208 | +REG32(RST_DBG_LPD, 0x338) | ||
209 | + FIELD(RST_DBG_LPD, RPU_DBG1_RESET, 5, 1) | ||
210 | + FIELD(RST_DBG_LPD, RPU_DBG0_RESET, 4, 1) | ||
211 | + FIELD(RST_DBG_LPD, RESET_HSDP, 1, 1) | ||
212 | + FIELD(RST_DBG_LPD, RESET, 0, 1) | ||
213 | +REG32(RST_GPIO, 0x33c) | ||
214 | + FIELD(RST_GPIO, RESET, 0, 1) | ||
215 | +REG32(RST_TTC, 0x344) | ||
216 | + FIELD(RST_TTC, TTC3_RESET, 3, 1) | ||
217 | + FIELD(RST_TTC, TTC2_RESET, 2, 1) | ||
218 | + FIELD(RST_TTC, TTC1_RESET, 1, 1) | ||
219 | + FIELD(RST_TTC, TTC0_RESET, 0, 1) | ||
220 | +REG32(RST_TIMESTAMP, 0x348) | ||
221 | + FIELD(RST_TIMESTAMP, RESET, 0, 1) | ||
222 | +REG32(RST_SWDT, 0x34c) | ||
223 | + FIELD(RST_SWDT, RESET, 0, 1) | ||
224 | +REG32(RST_OCM, 0x350) | ||
225 | + FIELD(RST_OCM, RESET, 0, 1) | ||
226 | +REG32(RST_IPI, 0x354) | ||
227 | + FIELD(RST_IPI, RESET, 0, 1) | ||
228 | +REG32(RST_SYSMON, 0x358) | ||
229 | + FIELD(RST_SYSMON, SEQ_RST, 1, 1) | ||
230 | + FIELD(RST_SYSMON, CFG_RST, 0, 1) | ||
231 | +REG32(RST_FPD, 0x360) | ||
232 | + FIELD(RST_FPD, SRST, 1, 1) | ||
233 | + FIELD(RST_FPD, POR, 0, 1) | ||
234 | +REG32(PSM_RST_MODE, 0x370) | ||
235 | + FIELD(PSM_RST_MODE, WAKEUP, 2, 1) | ||
236 | + FIELD(PSM_RST_MODE, RST_MODE, 0, 2) | ||
237 | + | ||
238 | +#define CRL_R_MAX (R_PSM_RST_MODE + 1) | ||
239 | + | ||
240 | +#define RPU_MAX_CPU 2 | ||
241 | + | ||
242 | +struct XlnxVersalCRL { | ||
243 | + SysBusDevice parent_obj; | ||
244 | + qemu_irq irq; | ||
245 | + | ||
246 | + struct { | ||
247 | + ARMCPU *cpu_r5[RPU_MAX_CPU]; | ||
248 | + DeviceState *adma[8]; | ||
249 | + DeviceState *uart[2]; | ||
250 | + DeviceState *gem[2]; | ||
251 | + DeviceState *usb; | ||
252 | + } cfg; | ||
253 | + | ||
254 | + RegisterInfoArray *reg_array; | ||
255 | + uint32_t regs[CRL_R_MAX]; | ||
256 | + RegisterInfo regs_info[CRL_R_MAX]; | ||
257 | +}; | ||
258 | +#endif | ||
259 | diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c | ||
260 | new file mode 100644 | ||
261 | index XXXXXXX..XXXXXXX | ||
262 | --- /dev/null | ||
263 | +++ b/hw/misc/xlnx-versal-crl.c | ||
264 | @@ -XXX,XX +XXX,XX @@ | ||
265 | +/* | ||
266 | + * QEMU model of the Clock-Reset-LPD (CRL). | ||
267 | + * | ||
268 | + * Copyright (c) 2022 Advanced Micro Devices, Inc. | ||
269 | + * SPDX-License-Identifier: GPL-2.0-or-later | ||
270 | + * | ||
271 | + * Written by Edgar E. Iglesias <edgar.iglesias@amd.com> | ||
272 | + */ | ||
273 | + | ||
274 | +#include "qemu/osdep.h" | ||
275 | +#include "qapi/error.h" | ||
276 | +#include "qemu/log.h" | ||
277 | +#include "qemu/bitops.h" | ||
278 | +#include "migration/vmstate.h" | ||
279 | +#include "hw/qdev-properties.h" | ||
280 | +#include "hw/sysbus.h" | ||
281 | +#include "hw/irq.h" | ||
282 | +#include "hw/register.h" | ||
283 | +#include "hw/resettable.h" | ||
284 | + | ||
285 | +#include "target/arm/arm-powerctl.h" | ||
286 | +#include "hw/misc/xlnx-versal-crl.h" | ||
287 | + | ||
288 | +#ifndef XLNX_VERSAL_CRL_ERR_DEBUG | ||
289 | +#define XLNX_VERSAL_CRL_ERR_DEBUG 0 | ||
290 | +#endif | ||
291 | + | ||
292 | +static void crl_update_irq(XlnxVersalCRL *s) | ||
293 | +{ | ||
294 | + bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK]; | ||
295 | + qemu_set_irq(s->irq, pending); | ||
296 | +} | ||
297 | + | ||
298 | +static void crl_status_postw(RegisterInfo *reg, uint64_t val64) | ||
299 | +{ | ||
300 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
301 | + crl_update_irq(s); | ||
302 | +} | ||
303 | + | ||
304 | +static uint64_t crl_enable_prew(RegisterInfo *reg, uint64_t val64) | ||
305 | +{ | ||
306 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
307 | + uint32_t val = val64; | ||
308 | + | ||
309 | + s->regs[R_IR_MASK] &= ~val; | ||
310 | + crl_update_irq(s); | ||
311 | + return 0; | ||
312 | +} | ||
313 | + | ||
314 | +static uint64_t crl_disable_prew(RegisterInfo *reg, uint64_t val64) | ||
315 | +{ | ||
316 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
317 | + uint32_t val = val64; | ||
318 | + | ||
319 | + s->regs[R_IR_MASK] |= val; | ||
320 | + crl_update_irq(s); | ||
321 | + return 0; | ||
322 | +} | ||
323 | + | ||
324 | +static void crl_reset_dev(XlnxVersalCRL *s, DeviceState *dev, | ||
325 | + bool rst_old, bool rst_new) | ||
326 | +{ | ||
327 | + device_cold_reset(dev); | ||
328 | +} | ||
329 | + | ||
330 | +static void crl_reset_cpu(XlnxVersalCRL *s, ARMCPU *armcpu, | ||
331 | + bool rst_old, bool rst_new) | ||
332 | +{ | ||
333 | + if (rst_new) { | ||
334 | + arm_set_cpu_off(armcpu->mp_affinity); | ||
335 | + } else { | ||
336 | + arm_set_cpu_on_and_reset(armcpu->mp_affinity); | ||
337 | + } | ||
338 | +} | ||
339 | + | ||
340 | +#define REGFIELD_RESET(type, s, reg, f, new_val, dev) { \ | ||
341 | + bool old_f = ARRAY_FIELD_EX32((s)->regs, reg, f); \ | ||
342 | + bool new_f = FIELD_EX32(new_val, reg, f); \ | ||
343 | + \ | ||
344 | + /* Detect edges. */ \ | ||
345 | + if (dev && old_f != new_f) { \ | ||
346 | + crl_reset_ ## type(s, dev, old_f, new_f); \ | ||
347 | + } \ | ||
348 | +} | ||
349 | + | ||
350 | +static uint64_t crl_rst_r5_prew(RegisterInfo *reg, uint64_t val64) | ||
351 | +{ | ||
352 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
353 | + | ||
354 | + REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU0, val64, s->cfg.cpu_r5[0]); | ||
355 | + REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU1, val64, s->cfg.cpu_r5[1]); | ||
356 | + return val64; | ||
357 | +} | ||
358 | + | ||
359 | +static uint64_t crl_rst_adma_prew(RegisterInfo *reg, uint64_t val64) | ||
360 | +{ | ||
361 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
362 | + int i; | ||
363 | + | ||
364 | + /* A single register fans out to all ADMA reset inputs. */ | ||
365 | + for (i = 0; i < ARRAY_SIZE(s->cfg.adma); i++) { | ||
366 | + REGFIELD_RESET(dev, s, RST_ADMA, RESET, val64, s->cfg.adma[i]); | ||
367 | + } | ||
368 | + return val64; | ||
369 | +} | ||
370 | + | ||
371 | +static uint64_t crl_rst_uart0_prew(RegisterInfo *reg, uint64_t val64) | ||
372 | +{ | ||
373 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
374 | + | ||
375 | + REGFIELD_RESET(dev, s, RST_UART0, RESET, val64, s->cfg.uart[0]); | ||
376 | + return val64; | ||
377 | +} | ||
378 | + | ||
379 | +static uint64_t crl_rst_uart1_prew(RegisterInfo *reg, uint64_t val64) | ||
380 | +{ | ||
381 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
382 | + | ||
383 | + REGFIELD_RESET(dev, s, RST_UART1, RESET, val64, s->cfg.uart[1]); | ||
384 | + return val64; | ||
385 | +} | ||
386 | + | ||
387 | +static uint64_t crl_rst_gem0_prew(RegisterInfo *reg, uint64_t val64) | ||
388 | +{ | ||
389 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
390 | + | ||
391 | + REGFIELD_RESET(dev, s, RST_GEM0, RESET, val64, s->cfg.gem[0]); | ||
392 | + return val64; | ||
393 | +} | ||
394 | + | ||
395 | +static uint64_t crl_rst_gem1_prew(RegisterInfo *reg, uint64_t val64) | ||
396 | +{ | ||
397 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
398 | + | ||
399 | + REGFIELD_RESET(dev, s, RST_GEM1, RESET, val64, s->cfg.gem[1]); | ||
400 | + return val64; | ||
401 | +} | ||
402 | + | ||
403 | +static uint64_t crl_rst_usb_prew(RegisterInfo *reg, uint64_t val64) | ||
404 | +{ | ||
405 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
406 | + | ||
407 | + REGFIELD_RESET(dev, s, RST_USB0, RESET, val64, s->cfg.usb); | ||
408 | + return val64; | ||
409 | +} | ||
410 | + | ||
411 | +static const RegisterAccessInfo crl_regs_info[] = { | ||
412 | + { .name = "ERR_CTRL", .addr = A_ERR_CTRL, | ||
413 | + },{ .name = "IR_STATUS", .addr = A_IR_STATUS, | ||
414 | + .w1c = 0x1, | ||
415 | + .post_write = crl_status_postw, | ||
416 | + },{ .name = "IR_MASK", .addr = A_IR_MASK, | ||
417 | + .reset = 0x1, | ||
418 | + .ro = 0x1, | ||
419 | + },{ .name = "IR_ENABLE", .addr = A_IR_ENABLE, | ||
420 | + .pre_write = crl_enable_prew, | ||
421 | + },{ .name = "IR_DISABLE", .addr = A_IR_DISABLE, | ||
422 | + .pre_write = crl_disable_prew, | ||
423 | + },{ .name = "WPROT", .addr = A_WPROT, | ||
424 | + },{ .name = "PLL_CLK_OTHER_DMN", .addr = A_PLL_CLK_OTHER_DMN, | ||
425 | + .reset = 0x1, | ||
426 | + .rsvd = 0xe, | ||
427 | + },{ .name = "RPLL_CTRL", .addr = A_RPLL_CTRL, | ||
428 | + .reset = 0x24809, | ||
429 | + .rsvd = 0xf88c00f6, | ||
430 | + },{ .name = "RPLL_CFG", .addr = A_RPLL_CFG, | ||
431 | + .reset = 0x2000000, | ||
432 | + .rsvd = 0x1801210, | ||
433 | + },{ .name = "RPLL_FRAC_CFG", .addr = A_RPLL_FRAC_CFG, | ||
434 | + .rsvd = 0x7e330000, | ||
435 | + },{ .name = "PLL_STATUS", .addr = A_PLL_STATUS, | ||
436 | + .reset = R_PLL_STATUS_RPLL_STABLE_MASK | | ||
437 | + R_PLL_STATUS_RPLL_LOCK_MASK, | ||
438 | + .rsvd = 0xfa, | ||
439 | + .ro = 0x5, | ||
440 | + },{ .name = "RPLL_TO_XPD_CTRL", .addr = A_RPLL_TO_XPD_CTRL, | ||
441 | + .reset = 0x2000100, | ||
442 | + .rsvd = 0xfdfc00ff, | ||
443 | + },{ .name = "LPD_TOP_SWITCH_CTRL", .addr = A_LPD_TOP_SWITCH_CTRL, | ||
444 | + .reset = 0x6000300, | ||
445 | + .rsvd = 0xf9fc00f8, | ||
446 | + },{ .name = "LPD_LSBUS_CTRL", .addr = A_LPD_LSBUS_CTRL, | ||
447 | + .reset = 0x2000800, | ||
448 | + .rsvd = 0xfdfc00f8, | ||
449 | + },{ .name = "CPU_R5_CTRL", .addr = A_CPU_R5_CTRL, | ||
450 | + .reset = 0xe000300, | ||
451 | + .rsvd = 0xe1fc00f8, | ||
452 | + },{ .name = "IOU_SWITCH_CTRL", .addr = A_IOU_SWITCH_CTRL, | ||
453 | + .reset = 0x2000500, | ||
454 | + .rsvd = 0xfdfc00f8, | ||
455 | + },{ .name = "GEM0_REF_CTRL", .addr = A_GEM0_REF_CTRL, | ||
456 | + .reset = 0xe000a00, | ||
457 | + .rsvd = 0xf1fc00f8, | ||
458 | + },{ .name = "GEM1_REF_CTRL", .addr = A_GEM1_REF_CTRL, | ||
459 | + .reset = 0xe000a00, | ||
460 | + .rsvd = 0xf1fc00f8, | ||
461 | + },{ .name = "GEM_TSU_REF_CTRL", .addr = A_GEM_TSU_REF_CTRL, | ||
462 | + .reset = 0x300, | ||
463 | + .rsvd = 0xfdfc00f8, | ||
464 | + },{ .name = "USB0_BUS_REF_CTRL", .addr = A_USB0_BUS_REF_CTRL, | ||
465 | + .reset = 0x2001900, | ||
466 | + .rsvd = 0xfdfc00f8, | ||
467 | + },{ .name = "UART0_REF_CTRL", .addr = A_UART0_REF_CTRL, | ||
468 | + .reset = 0xc00, | ||
469 | + .rsvd = 0xfdfc00f8, | ||
470 | + },{ .name = "UART1_REF_CTRL", .addr = A_UART1_REF_CTRL, | ||
471 | + .reset = 0xc00, | ||
472 | + .rsvd = 0xfdfc00f8, | ||
473 | + },{ .name = "SPI0_REF_CTRL", .addr = A_SPI0_REF_CTRL, | ||
474 | + .reset = 0x600, | ||
475 | + .rsvd = 0xfdfc00f8, | ||
476 | + },{ .name = "SPI1_REF_CTRL", .addr = A_SPI1_REF_CTRL, | ||
477 | + .reset = 0x600, | ||
478 | + .rsvd = 0xfdfc00f8, | ||
479 | + },{ .name = "CAN0_REF_CTRL", .addr = A_CAN0_REF_CTRL, | ||
480 | + .reset = 0xc00, | ||
481 | + .rsvd = 0xfdfc00f8, | ||
482 | + },{ .name = "CAN1_REF_CTRL", .addr = A_CAN1_REF_CTRL, | ||
483 | + .reset = 0xc00, | ||
484 | + .rsvd = 0xfdfc00f8, | ||
485 | + },{ .name = "I2C0_REF_CTRL", .addr = A_I2C0_REF_CTRL, | ||
486 | + .reset = 0xc00, | ||
487 | + .rsvd = 0xfdfc00f8, | ||
488 | + },{ .name = "I2C1_REF_CTRL", .addr = A_I2C1_REF_CTRL, | ||
489 | + .reset = 0xc00, | ||
490 | + .rsvd = 0xfdfc00f8, | ||
491 | + },{ .name = "DBG_LPD_CTRL", .addr = A_DBG_LPD_CTRL, | ||
492 | + .reset = 0x300, | ||
493 | + .rsvd = 0xfdfc00f8, | ||
494 | + },{ .name = "TIMESTAMP_REF_CTRL", .addr = A_TIMESTAMP_REF_CTRL, | ||
495 | + .reset = 0x2000c00, | ||
496 | + .rsvd = 0xfdfc00f8, | ||
497 | + },{ .name = "CRL_SAFETY_CHK", .addr = A_CRL_SAFETY_CHK, | ||
498 | + },{ .name = "PSM_REF_CTRL", .addr = A_PSM_REF_CTRL, | ||
499 | + .reset = 0xf04, | ||
500 | + .rsvd = 0xfffc00f8, | ||
501 | + },{ .name = "DBG_TSTMP_CTRL", .addr = A_DBG_TSTMP_CTRL, | ||
502 | + .reset = 0x300, | ||
503 | + .rsvd = 0xfdfc00f8, | ||
504 | + },{ .name = "CPM_TOPSW_REF_CTRL", .addr = A_CPM_TOPSW_REF_CTRL, | ||
505 | + .reset = 0x300, | ||
506 | + .rsvd = 0xfdfc00f8, | ||
507 | + },{ .name = "USB3_DUAL_REF_CTRL", .addr = A_USB3_DUAL_REF_CTRL, | ||
508 | + .reset = 0x3c00, | ||
509 | + .rsvd = 0xfdfc00f8, | ||
510 | + },{ .name = "RST_CPU_R5", .addr = A_RST_CPU_R5, | ||
511 | + .reset = 0x17, | ||
512 | + .rsvd = 0x8, | ||
513 | + .pre_write = crl_rst_r5_prew, | ||
514 | + },{ .name = "RST_ADMA", .addr = A_RST_ADMA, | ||
515 | + .reset = 0x1, | ||
516 | + .pre_write = crl_rst_adma_prew, | ||
517 | + },{ .name = "RST_GEM0", .addr = A_RST_GEM0, | ||
518 | + .reset = 0x1, | ||
519 | + .pre_write = crl_rst_gem0_prew, | ||
520 | + },{ .name = "RST_GEM1", .addr = A_RST_GEM1, | ||
521 | + .reset = 0x1, | ||
522 | + .pre_write = crl_rst_gem1_prew, | ||
523 | + },{ .name = "RST_SPARE", .addr = A_RST_SPARE, | ||
524 | + .reset = 0x1, | ||
525 | + },{ .name = "RST_USB0", .addr = A_RST_USB0, | ||
526 | + .reset = 0x1, | ||
527 | + .pre_write = crl_rst_usb_prew, | ||
528 | + },{ .name = "RST_UART0", .addr = A_RST_UART0, | ||
529 | + .reset = 0x1, | ||
530 | + .pre_write = crl_rst_uart0_prew, | ||
531 | + },{ .name = "RST_UART1", .addr = A_RST_UART1, | ||
532 | + .reset = 0x1, | ||
533 | + .pre_write = crl_rst_uart1_prew, | ||
534 | + },{ .name = "RST_SPI0", .addr = A_RST_SPI0, | ||
535 | + .reset = 0x1, | ||
536 | + },{ .name = "RST_SPI1", .addr = A_RST_SPI1, | ||
537 | + .reset = 0x1, | ||
538 | + },{ .name = "RST_CAN0", .addr = A_RST_CAN0, | ||
539 | + .reset = 0x1, | ||
540 | + },{ .name = "RST_CAN1", .addr = A_RST_CAN1, | ||
541 | + .reset = 0x1, | ||
542 | + },{ .name = "RST_I2C0", .addr = A_RST_I2C0, | ||
543 | + .reset = 0x1, | ||
544 | + },{ .name = "RST_I2C1", .addr = A_RST_I2C1, | ||
545 | + .reset = 0x1, | ||
546 | + },{ .name = "RST_DBG_LPD", .addr = A_RST_DBG_LPD, | ||
547 | + .reset = 0x33, | ||
548 | + .rsvd = 0xcc, | ||
549 | + },{ .name = "RST_GPIO", .addr = A_RST_GPIO, | ||
550 | + .reset = 0x1, | ||
551 | + },{ .name = "RST_TTC", .addr = A_RST_TTC, | ||
552 | + .reset = 0xf, | ||
553 | + },{ .name = "RST_TIMESTAMP", .addr = A_RST_TIMESTAMP, | ||
554 | + .reset = 0x1, | ||
555 | + },{ .name = "RST_SWDT", .addr = A_RST_SWDT, | ||
556 | + .reset = 0x1, | ||
557 | + },{ .name = "RST_OCM", .addr = A_RST_OCM, | ||
558 | + },{ .name = "RST_IPI", .addr = A_RST_IPI, | ||
559 | + },{ .name = "RST_FPD", .addr = A_RST_FPD, | ||
560 | + .reset = 0x3, | ||
561 | + },{ .name = "PSM_RST_MODE", .addr = A_PSM_RST_MODE, | ||
562 | + .reset = 0x1, | ||
563 | + .rsvd = 0xf8, | ||
564 | + } | ||
565 | +}; | ||
566 | + | ||
567 | +static void crl_reset_enter(Object *obj, ResetType type) | ||
568 | +{ | ||
569 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj); | ||
570 | + unsigned int i; | ||
571 | + | ||
572 | + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { | ||
573 | + register_reset(&s->regs_info[i]); | ||
574 | + } | ||
575 | +} | ||
576 | + | ||
577 | +static void crl_reset_hold(Object *obj) | ||
578 | +{ | ||
579 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj); | ||
580 | + | ||
581 | + crl_update_irq(s); | ||
582 | +} | ||
583 | + | ||
584 | +static const MemoryRegionOps crl_ops = { | ||
585 | + .read = register_read_memory, | ||
586 | + .write = register_write_memory, | ||
587 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
588 | + .valid = { | ||
589 | + .min_access_size = 4, | ||
590 | + .max_access_size = 4, | ||
591 | + }, | ||
592 | +}; | ||
593 | + | ||
594 | +static void crl_init(Object *obj) | ||
595 | +{ | ||
596 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj); | ||
597 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
598 | + int i; | ||
599 | + | ||
600 | + s->reg_array = | ||
601 | + register_init_block32(DEVICE(obj), crl_regs_info, | ||
602 | + ARRAY_SIZE(crl_regs_info), | ||
603 | + s->regs_info, s->regs, | ||
604 | + &crl_ops, | ||
605 | + XLNX_VERSAL_CRL_ERR_DEBUG, | ||
606 | + CRL_R_MAX * 4); | ||
607 | + sysbus_init_mmio(sbd, &s->reg_array->mem); | ||
608 | + sysbus_init_irq(sbd, &s->irq); | ||
609 | + | ||
610 | + for (i = 0; i < ARRAY_SIZE(s->cfg.cpu_r5); ++i) { | ||
611 | + object_property_add_link(obj, "cpu_r5[*]", TYPE_ARM_CPU, | ||
612 | + (Object **)&s->cfg.cpu_r5[i], | ||
613 | + qdev_prop_allow_set_link_before_realize, | ||
614 | + OBJ_PROP_LINK_STRONG); | ||
615 | + } | ||
616 | + | ||
617 | + for (i = 0; i < ARRAY_SIZE(s->cfg.adma); ++i) { | ||
618 | + object_property_add_link(obj, "adma[*]", TYPE_DEVICE, | ||
619 | + (Object **)&s->cfg.adma[i], | ||
620 | + qdev_prop_allow_set_link_before_realize, | ||
621 | + OBJ_PROP_LINK_STRONG); | ||
622 | + } | ||
623 | + | ||
624 | + for (i = 0; i < ARRAY_SIZE(s->cfg.uart); ++i) { | ||
625 | + object_property_add_link(obj, "uart[*]", TYPE_DEVICE, | ||
626 | + (Object **)&s->cfg.uart[i], | ||
627 | + qdev_prop_allow_set_link_before_realize, | ||
628 | + OBJ_PROP_LINK_STRONG); | ||
629 | + } | ||
630 | + | ||
631 | + for (i = 0; i < ARRAY_SIZE(s->cfg.gem); ++i) { | ||
632 | + object_property_add_link(obj, "gem[*]", TYPE_DEVICE, | ||
633 | + (Object **)&s->cfg.gem[i], | ||
634 | + qdev_prop_allow_set_link_before_realize, | ||
635 | + OBJ_PROP_LINK_STRONG); | ||
636 | + } | ||
637 | + | ||
638 | + object_property_add_link(obj, "usb", TYPE_DEVICE, | ||
639 | + (Object **)&s->cfg.gem[i], | ||
640 | + qdev_prop_allow_set_link_before_realize, | ||
641 | + OBJ_PROP_LINK_STRONG); | ||
642 | +} | ||
643 | + | ||
644 | +static void crl_finalize(Object *obj) | ||
645 | +{ | ||
646 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj); | ||
647 | + register_finalize_block(s->reg_array); | ||
648 | +} | ||
649 | + | ||
650 | +static const VMStateDescription vmstate_crl = { | ||
651 | + .name = TYPE_XLNX_VERSAL_CRL, | ||
652 | + .version_id = 1, | ||
653 | + .minimum_version_id = 1, | ||
654 | + .fields = (VMStateField[]) { | ||
655 | + VMSTATE_UINT32_ARRAY(regs, XlnxVersalCRL, CRL_R_MAX), | ||
656 | + VMSTATE_END_OF_LIST(), | ||
657 | + } | ||
658 | +}; | ||
659 | + | ||
660 | +static void crl_class_init(ObjectClass *klass, void *data) | ||
661 | +{ | ||
662 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
663 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
664 | + | ||
665 | + dc->vmsd = &vmstate_crl; | ||
666 | + | ||
667 | + rc->phases.enter = crl_reset_enter; | ||
668 | + rc->phases.hold = crl_reset_hold; | ||
669 | +} | ||
670 | + | ||
671 | +static const TypeInfo crl_info = { | ||
672 | + .name = TYPE_XLNX_VERSAL_CRL, | ||
673 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
674 | + .instance_size = sizeof(XlnxVersalCRL), | ||
675 | + .class_init = crl_class_init, | ||
676 | + .instance_init = crl_init, | ||
677 | + .instance_finalize = crl_finalize, | ||
678 | +}; | ||
679 | + | ||
680 | +static void crl_register_types(void) | ||
681 | +{ | ||
682 | + type_register_static(&crl_info); | ||
683 | +} | ||
684 | + | ||
685 | +type_init(crl_register_types) | ||
686 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
687 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
688 | --- a/hw/misc/meson.build | 13 | --- a/target/arm/translate-sve.c |
689 | +++ b/hw/misc/meson.build | 14 | +++ b/target/arm/translate-sve.c |
690 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) | 15 | @@ -XXX,XX +XXX,XX @@ static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a, |
691 | softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c')) | 16 | return true; |
692 | specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c')) | 17 | } |
693 | specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c')) | 18 | |
694 | +specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c')) | 19 | - desc = tcg_const_i32(simd_desc(vsz, vsz, 0)); |
695 | softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files( | 20 | + desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); |
696 | 'xlnx-versal-xramc.c', | 21 | temp = tcg_temp_new_i64(); |
697 | 'xlnx-versal-pmc-iou-slcr.c', | 22 | t_zn = tcg_temp_new_ptr(); |
23 | t_pg = tcg_temp_new_ptr(); | ||
24 | @@ -XXX,XX +XXX,XX @@ static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a, | ||
25 | fn(temp, t_zn, t_pg, desc); | ||
26 | tcg_temp_free_ptr(t_zn); | ||
27 | tcg_temp_free_ptr(t_pg); | ||
28 | - tcg_temp_free_i32(desc); | ||
29 | |||
30 | write_fp_dreg(s, a->rd, temp); | ||
31 | tcg_temp_free_i64(temp); | ||
32 | @@ -XXX,XX +XXX,XX @@ static void do_index(DisasContext *s, int esz, int rd, | ||
33 | TCGv_i64 start, TCGv_i64 incr) | ||
34 | { | ||
35 | unsigned vsz = vec_full_reg_size(s); | ||
36 | - TCGv_i32 desc = tcg_const_i32(simd_desc(vsz, vsz, 0)); | ||
37 | + TCGv_i32 desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); | ||
38 | TCGv_ptr t_zd = tcg_temp_new_ptr(); | ||
39 | |||
40 | tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd)); | ||
41 | @@ -XXX,XX +XXX,XX @@ static void do_index(DisasContext *s, int esz, int rd, | ||
42 | tcg_temp_free_i32(i32); | ||
43 | } | ||
44 | tcg_temp_free_ptr(t_zd); | ||
45 | - tcg_temp_free_i32(desc); | ||
46 | } | ||
47 | |||
48 | static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a) | ||
49 | @@ -XXX,XX +XXX,XX @@ static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn, | ||
50 | nptr = tcg_temp_new_ptr(); | ||
51 | tcg_gen_addi_ptr(dptr, cpu_env, vec_full_reg_offset(s, rd)); | ||
52 | tcg_gen_addi_ptr(nptr, cpu_env, vec_full_reg_offset(s, rn)); | ||
53 | - desc = tcg_const_i32(simd_desc(vsz, vsz, 0)); | ||
54 | + desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); | ||
55 | |||
56 | switch (esz) { | ||
57 | case MO_8: | ||
58 | @@ -XXX,XX +XXX,XX @@ static void do_sat_addsub_vec(DisasContext *s, int esz, int rd, int rn, | ||
59 | |||
60 | tcg_temp_free_ptr(dptr); | ||
61 | tcg_temp_free_ptr(nptr); | ||
62 | - tcg_temp_free_i32(desc); | ||
63 | } | ||
64 | |||
65 | static bool trans_CNT_r(DisasContext *s, arg_CNT_r *a) | ||
66 | @@ -XXX,XX +XXX,XX @@ static void do_cpy_m(DisasContext *s, int esz, int rd, int rn, int pg, | ||
67 | gen_helper_sve_cpy_m_s, gen_helper_sve_cpy_m_d, | ||
68 | }; | ||
69 | unsigned vsz = vec_full_reg_size(s); | ||
70 | - TCGv_i32 desc = tcg_const_i32(simd_desc(vsz, vsz, 0)); | ||
71 | + TCGv_i32 desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); | ||
72 | TCGv_ptr t_zd = tcg_temp_new_ptr(); | ||
73 | TCGv_ptr t_zn = tcg_temp_new_ptr(); | ||
74 | TCGv_ptr t_pg = tcg_temp_new_ptr(); | ||
75 | @@ -XXX,XX +XXX,XX @@ static void do_cpy_m(DisasContext *s, int esz, int rd, int rn, int pg, | ||
76 | tcg_temp_free_ptr(t_zd); | ||
77 | tcg_temp_free_ptr(t_zn); | ||
78 | tcg_temp_free_ptr(t_pg); | ||
79 | - tcg_temp_free_i32(desc); | ||
80 | } | ||
81 | |||
82 | static bool trans_FCPY(DisasContext *s, arg_FCPY *a) | ||
83 | @@ -XXX,XX +XXX,XX @@ static void do_insr_i64(DisasContext *s, arg_rrr_esz *a, TCGv_i64 val) | ||
84 | gen_helper_sve_insr_s, gen_helper_sve_insr_d, | ||
85 | }; | ||
86 | unsigned vsz = vec_full_reg_size(s); | ||
87 | - TCGv_i32 desc = tcg_const_i32(simd_desc(vsz, vsz, 0)); | ||
88 | + TCGv_i32 desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); | ||
89 | TCGv_ptr t_zd = tcg_temp_new_ptr(); | ||
90 | TCGv_ptr t_zn = tcg_temp_new_ptr(); | ||
91 | |||
92 | @@ -XXX,XX +XXX,XX @@ static void do_insr_i64(DisasContext *s, arg_rrr_esz *a, TCGv_i64 val) | ||
93 | |||
94 | tcg_temp_free_ptr(t_zd); | ||
95 | tcg_temp_free_ptr(t_zn); | ||
96 | - tcg_temp_free_i32(desc); | ||
97 | } | ||
98 | |||
99 | static bool trans_INSR_f(DisasContext *s, arg_rrr_esz *a) | ||
100 | @@ -XXX,XX +XXX,XX @@ static bool do_perm_pred3(DisasContext *s, arg_rrr_esz *a, bool high_odd, | ||
101 | TCGv_ptr t_d = tcg_temp_new_ptr(); | ||
102 | TCGv_ptr t_n = tcg_temp_new_ptr(); | ||
103 | TCGv_ptr t_m = tcg_temp_new_ptr(); | ||
104 | - TCGv_i32 t_desc; | ||
105 | uint32_t desc = 0; | ||
106 | |||
107 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz); | ||
108 | @@ -XXX,XX +XXX,XX @@ static bool do_perm_pred3(DisasContext *s, arg_rrr_esz *a, bool high_odd, | ||
109 | tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd)); | ||
110 | tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn)); | ||
111 | tcg_gen_addi_ptr(t_m, cpu_env, pred_full_reg_offset(s, a->rm)); | ||
112 | - t_desc = tcg_const_i32(desc); | ||
113 | |||
114 | - fn(t_d, t_n, t_m, t_desc); | ||
115 | + fn(t_d, t_n, t_m, tcg_constant_i32(desc)); | ||
116 | |||
117 | tcg_temp_free_ptr(t_d); | ||
118 | tcg_temp_free_ptr(t_n); | ||
119 | tcg_temp_free_ptr(t_m); | ||
120 | - tcg_temp_free_i32(t_desc); | ||
121 | return true; | ||
122 | } | ||
123 | |||
124 | @@ -XXX,XX +XXX,XX @@ static bool do_perm_pred2(DisasContext *s, arg_rr_esz *a, bool high_odd, | ||
125 | unsigned vsz = pred_full_reg_size(s); | ||
126 | TCGv_ptr t_d = tcg_temp_new_ptr(); | ||
127 | TCGv_ptr t_n = tcg_temp_new_ptr(); | ||
128 | - TCGv_i32 t_desc; | ||
129 | uint32_t desc = 0; | ||
130 | |||
131 | tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd)); | ||
132 | @@ -XXX,XX +XXX,XX @@ static bool do_perm_pred2(DisasContext *s, arg_rr_esz *a, bool high_odd, | ||
133 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz); | ||
134 | desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); | ||
135 | desc = FIELD_DP32(desc, PREDDESC, DATA, high_odd); | ||
136 | - t_desc = tcg_const_i32(desc); | ||
137 | |||
138 | - fn(t_d, t_n, t_desc); | ||
139 | + fn(t_d, t_n, tcg_constant_i32(desc)); | ||
140 | |||
141 | - tcg_temp_free_i32(t_desc); | ||
142 | tcg_temp_free_ptr(t_d); | ||
143 | tcg_temp_free_ptr(t_n); | ||
144 | return true; | ||
145 | @@ -XXX,XX +XXX,XX @@ static void find_last_active(DisasContext *s, TCGv_i32 ret, int esz, int pg) | ||
146 | * round up, as we do elsewhere, because we need the exact size. | ||
147 | */ | ||
148 | TCGv_ptr t_p = tcg_temp_new_ptr(); | ||
149 | - TCGv_i32 t_desc; | ||
150 | unsigned desc = 0; | ||
151 | |||
152 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s)); | ||
153 | desc = FIELD_DP32(desc, PREDDESC, ESZ, esz); | ||
154 | |||
155 | tcg_gen_addi_ptr(t_p, cpu_env, pred_full_reg_offset(s, pg)); | ||
156 | - t_desc = tcg_const_i32(desc); | ||
157 | |||
158 | - gen_helper_sve_last_active_element(ret, t_p, t_desc); | ||
159 | + gen_helper_sve_last_active_element(ret, t_p, tcg_constant_i32(desc)); | ||
160 | |||
161 | - tcg_temp_free_i32(t_desc); | ||
162 | tcg_temp_free_ptr(t_p); | ||
163 | } | ||
164 | |||
165 | @@ -XXX,XX +XXX,XX @@ static void do_cntp(DisasContext *s, TCGv_i64 val, int esz, int pn, int pg) | ||
166 | TCGv_ptr t_pn = tcg_temp_new_ptr(); | ||
167 | TCGv_ptr t_pg = tcg_temp_new_ptr(); | ||
168 | unsigned desc = 0; | ||
169 | - TCGv_i32 t_desc; | ||
170 | |||
171 | desc = FIELD_DP32(desc, PREDDESC, OPRSZ, psz); | ||
172 | desc = FIELD_DP32(desc, PREDDESC, ESZ, esz); | ||
173 | |||
174 | tcg_gen_addi_ptr(t_pn, cpu_env, pred_full_reg_offset(s, pn)); | ||
175 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); | ||
176 | - t_desc = tcg_const_i32(desc); | ||
177 | |||
178 | - gen_helper_sve_cntp(val, t_pn, t_pg, t_desc); | ||
179 | + gen_helper_sve_cntp(val, t_pn, t_pg, tcg_constant_i32(desc)); | ||
180 | tcg_temp_free_ptr(t_pn); | ||
181 | tcg_temp_free_ptr(t_pg); | ||
182 | - tcg_temp_free_i32(t_desc); | ||
183 | } | ||
184 | } | ||
185 | |||
186 | @@ -XXX,XX +XXX,XX @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a, | ||
187 | { | ||
188 | unsigned vsz = vec_full_reg_size(s); | ||
189 | unsigned p2vsz = pow2ceil(vsz); | ||
190 | - TCGv_i32 t_desc = tcg_const_i32(simd_desc(vsz, vsz, p2vsz)); | ||
191 | + TCGv_i32 t_desc = tcg_constant_i32(simd_desc(vsz, vsz, p2vsz)); | ||
192 | TCGv_ptr t_zn, t_pg, status; | ||
193 | TCGv_i64 temp; | ||
194 | |||
195 | @@ -XXX,XX +XXX,XX @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a, | ||
196 | tcg_temp_free_ptr(t_zn); | ||
197 | tcg_temp_free_ptr(t_pg); | ||
198 | tcg_temp_free_ptr(status); | ||
199 | - tcg_temp_free_i32(t_desc); | ||
200 | |||
201 | write_fp_dreg(s, a->rd, temp); | ||
202 | tcg_temp_free_i64(temp); | ||
203 | @@ -XXX,XX +XXX,XX @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a) | ||
204 | tcg_gen_addi_ptr(t_rm, cpu_env, vec_full_reg_offset(s, a->rm)); | ||
205 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg)); | ||
206 | t_fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); | ||
207 | - t_desc = tcg_const_i32(simd_desc(vsz, vsz, 0)); | ||
208 | + t_desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); | ||
209 | |||
210 | fns[a->esz - 1](t_val, t_val, t_rm, t_pg, t_fpst, t_desc); | ||
211 | |||
212 | - tcg_temp_free_i32(t_desc); | ||
213 | tcg_temp_free_ptr(t_fpst); | ||
214 | tcg_temp_free_ptr(t_pg); | ||
215 | tcg_temp_free_ptr(t_rm); | ||
216 | @@ -XXX,XX +XXX,XX @@ static void do_fp_scalar(DisasContext *s, int zd, int zn, int pg, bool is_fp16, | ||
217 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); | ||
218 | |||
219 | status = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR); | ||
220 | - desc = tcg_const_i32(simd_desc(vsz, vsz, 0)); | ||
221 | + desc = tcg_constant_i32(simd_desc(vsz, vsz, 0)); | ||
222 | fn(t_zd, t_zn, t_pg, scalar, status, desc); | ||
223 | |||
224 | - tcg_temp_free_i32(desc); | ||
225 | tcg_temp_free_ptr(status); | ||
226 | tcg_temp_free_ptr(t_pg); | ||
227 | tcg_temp_free_ptr(t_zn); | ||
228 | @@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, | ||
229 | { | ||
230 | unsigned vsz = vec_full_reg_size(s); | ||
231 | TCGv_ptr t_pg; | ||
232 | - TCGv_i32 t_desc; | ||
233 | int desc = 0; | ||
234 | |||
235 | /* | ||
236 | @@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, | ||
237 | } | ||
238 | |||
239 | desc = simd_desc(vsz, vsz, zt | desc); | ||
240 | - t_desc = tcg_const_i32(desc); | ||
241 | t_pg = tcg_temp_new_ptr(); | ||
242 | |||
243 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); | ||
244 | - fn(cpu_env, t_pg, addr, t_desc); | ||
245 | + fn(cpu_env, t_pg, addr, tcg_constant_i32(desc)); | ||
246 | |||
247 | tcg_temp_free_ptr(t_pg); | ||
248 | - tcg_temp_free_i32(t_desc); | ||
249 | } | ||
250 | |||
251 | /* Indexed by [mte][be][dtype][nreg] */ | ||
252 | @@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm, | ||
253 | TCGv_ptr t_zm = tcg_temp_new_ptr(); | ||
254 | TCGv_ptr t_pg = tcg_temp_new_ptr(); | ||
255 | TCGv_ptr t_zt = tcg_temp_new_ptr(); | ||
256 | - TCGv_i32 t_desc; | ||
257 | int desc = 0; | ||
258 | |||
259 | if (s->mte_active[0]) { | ||
260 | @@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm, | ||
261 | desc <<= SVE_MTEDESC_SHIFT; | ||
262 | } | ||
263 | desc = simd_desc(vsz, vsz, desc | scale); | ||
264 | - t_desc = tcg_const_i32(desc); | ||
265 | |||
266 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); | ||
267 | tcg_gen_addi_ptr(t_zm, cpu_env, vec_full_reg_offset(s, zm)); | ||
268 | tcg_gen_addi_ptr(t_zt, cpu_env, vec_full_reg_offset(s, zt)); | ||
269 | - fn(cpu_env, t_zt, t_pg, t_zm, scalar, t_desc); | ||
270 | + fn(cpu_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc)); | ||
271 | |||
272 | tcg_temp_free_ptr(t_zt); | ||
273 | tcg_temp_free_ptr(t_zm); | ||
274 | tcg_temp_free_ptr(t_pg); | ||
275 | - tcg_temp_free_i32(t_desc); | ||
276 | } | ||
277 | |||
278 | /* Indexed by [mte][be][ff][xs][u][msz]. */ | ||
698 | -- | 279 | -- |
699 | 2.25.1 | 280 | 2.25.1 | diff view generated by jsdifflib |
1 | From: "Edgar E. Iglesias" <edgar.iglesias@amd.com> | 1 | From: Damien Hedde <damien.hedde@greensocs.com> |
---|---|---|---|
2 | 2 | ||
3 | Break out header file to allow embedding of the the TTC. | 3 | As of now, cryptographic instructions ISAR fields are never cleared so |
4 | we can end up with a cpu with cryptographic instructions but no | ||
5 | floating-point/neon instructions which is not a possible configuration | ||
6 | according to Arm specifications. | ||
4 | 7 | ||
5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> | 8 | In QEMU, we have 3 kinds of cpus regarding cryptographic instructions: |
6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 9 | + no support |
7 | Reviewed-by: Luc Michel <luc@lmichel.fr> | 10 | + cortex-a57/a72: cryptographic extension is optional, |
8 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> | 11 | floating-point/neon is not. |
9 | Message-id: 20220331222017.2914409-2-edgar.iglesias@gmail.com | 12 | + cortex-a53: crytographic extension is optional as well as |
13 | floating-point/neon. But cryptographic requires | ||
14 | floating-point/neon support. | ||
15 | |||
16 | Therefore we can safely clear the ISAR fields when neon is disabled. | ||
17 | |||
18 | Note that other Arm cpus seem to follow this. For example cortex-a55 is | ||
19 | like cortex-a53 and cortex-a76/cortex-a710 are like cortex-a57/a72. | ||
20 | |||
21 | Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> | ||
22 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
23 | Message-id: 20220427090117.6954-1-damien.hedde@greensocs.com | ||
24 | [PMM: fixed commit message typos] | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 26 | --- |
12 | include/hw/timer/cadence_ttc.h | 54 ++++++++++++++++++++++++++++++++++ | 27 | target/arm/cpu.c | 9 +++++++++ |
13 | hw/timer/cadence_ttc.c | 32 ++------------------ | 28 | 1 file changed, 9 insertions(+) |
14 | 2 files changed, 56 insertions(+), 30 deletions(-) | ||
15 | create mode 100644 include/hw/timer/cadence_ttc.h | ||
16 | 29 | ||
17 | diff --git a/include/hw/timer/cadence_ttc.h b/include/hw/timer/cadence_ttc.h | 30 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
18 | new file mode 100644 | ||
19 | index XXXXXXX..XXXXXXX | ||
20 | --- /dev/null | ||
21 | +++ b/include/hw/timer/cadence_ttc.h | ||
22 | @@ -XXX,XX +XXX,XX @@ | ||
23 | +/* | ||
24 | + * Xilinx Zynq cadence TTC model | ||
25 | + * | ||
26 | + * Copyright (c) 2011 Xilinx Inc. | ||
27 | + * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) | ||
28 | + * Copyright (c) 2012 PetaLogix Pty Ltd. | ||
29 | + * Written By Haibing Ma | ||
30 | + * M. Habib | ||
31 | + * | ||
32 | + * This program is free software; you can redistribute it and/or | ||
33 | + * modify it under the terms of the GNU General Public License | ||
34 | + * as published by the Free Software Foundation; either version | ||
35 | + * 2 of the License, or (at your option) any later version. | ||
36 | + * | ||
37 | + * You should have received a copy of the GNU General Public License along | ||
38 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
39 | + */ | ||
40 | +#ifndef HW_TIMER_CADENCE_TTC_H | ||
41 | +#define HW_TIMER_CADENCE_TTC_H | ||
42 | + | ||
43 | +#include "hw/sysbus.h" | ||
44 | +#include "qemu/timer.h" | ||
45 | + | ||
46 | +typedef struct { | ||
47 | + QEMUTimer *timer; | ||
48 | + int freq; | ||
49 | + | ||
50 | + uint32_t reg_clock; | ||
51 | + uint32_t reg_count; | ||
52 | + uint32_t reg_value; | ||
53 | + uint16_t reg_interval; | ||
54 | + uint16_t reg_match[3]; | ||
55 | + uint32_t reg_intr; | ||
56 | + uint32_t reg_intr_en; | ||
57 | + uint32_t reg_event_ctrl; | ||
58 | + uint32_t reg_event; | ||
59 | + | ||
60 | + uint64_t cpu_time; | ||
61 | + unsigned int cpu_time_valid; | ||
62 | + | ||
63 | + qemu_irq irq; | ||
64 | +} CadenceTimerState; | ||
65 | + | ||
66 | +#define TYPE_CADENCE_TTC "cadence_ttc" | ||
67 | +OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC) | ||
68 | + | ||
69 | +struct CadenceTTCState { | ||
70 | + SysBusDevice parent_obj; | ||
71 | + | ||
72 | + MemoryRegion iomem; | ||
73 | + CadenceTimerState timer[3]; | ||
74 | +}; | ||
75 | + | ||
76 | +#endif | ||
77 | diff --git a/hw/timer/cadence_ttc.c b/hw/timer/cadence_ttc.c | ||
78 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
79 | --- a/hw/timer/cadence_ttc.c | 32 | --- a/target/arm/cpu.c |
80 | +++ b/hw/timer/cadence_ttc.c | 33 | +++ b/target/arm/cpu.c |
81 | @@ -XXX,XX +XXX,XX @@ | 34 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
82 | #include "qemu/timer.h" | 35 | unset_feature(env, ARM_FEATURE_NEON); |
83 | #include "qom/object.h" | 36 | |
84 | 37 | t = cpu->isar.id_aa64isar0; | |
85 | +#include "hw/timer/cadence_ttc.h" | 38 | + t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); |
86 | + | 39 | + t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); |
87 | #ifdef CADENCE_TTC_ERR_DEBUG | 40 | + t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); |
88 | #define DB_PRINT(...) do { \ | 41 | + t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); |
89 | fprintf(stderr, ": %s: ", __func__); \ | 42 | + t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); |
90 | @@ -XXX,XX +XXX,XX @@ | 43 | + t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); |
91 | #define CLOCK_CTRL_PS_EN 0x00000001 | 44 | t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); |
92 | #define CLOCK_CTRL_PS_V 0x0000001e | 45 | cpu->isar.id_aa64isar0 = t; |
93 | 46 | ||
94 | -typedef struct { | 47 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
95 | - QEMUTimer *timer; | 48 | cpu->isar.id_aa64pfr0 = t; |
96 | - int freq; | 49 | |
97 | - | 50 | u = cpu->isar.id_isar5; |
98 | - uint32_t reg_clock; | 51 | + u = FIELD_DP32(u, ID_ISAR5, AES, 0); |
99 | - uint32_t reg_count; | 52 | + u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); |
100 | - uint32_t reg_value; | 53 | + u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); |
101 | - uint16_t reg_interval; | 54 | u = FIELD_DP32(u, ID_ISAR5, RDM, 0); |
102 | - uint16_t reg_match[3]; | 55 | u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); |
103 | - uint32_t reg_intr; | 56 | cpu->isar.id_isar5 = u; |
104 | - uint32_t reg_intr_en; | ||
105 | - uint32_t reg_event_ctrl; | ||
106 | - uint32_t reg_event; | ||
107 | - | ||
108 | - uint64_t cpu_time; | ||
109 | - unsigned int cpu_time_valid; | ||
110 | - | ||
111 | - qemu_irq irq; | ||
112 | -} CadenceTimerState; | ||
113 | - | ||
114 | -#define TYPE_CADENCE_TTC "cadence_ttc" | ||
115 | -OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC) | ||
116 | - | ||
117 | -struct CadenceTTCState { | ||
118 | - SysBusDevice parent_obj; | ||
119 | - | ||
120 | - MemoryRegion iomem; | ||
121 | - CadenceTimerState timer[3]; | ||
122 | -}; | ||
123 | - | ||
124 | static void cadence_timer_update(CadenceTimerState *s) | ||
125 | { | ||
126 | qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en)); | ||
127 | -- | 57 | -- |
128 | 2.25.1 | 58 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | While defining these names, use the correct field width of 5 not 4 for | ||
4 | DBGWCR.MASK. This typo prevented setting a watchpoint larger than 32k. | ||
5 | |||
6 | Reported-by: Chris Howard <cvz185@web.de> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
9 | Message-id: 20220427051926.295223-1-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/internals.h | 12 ++++++++++++ | ||
13 | target/arm/debug_helper.c | 10 +++++----- | ||
14 | target/arm/helper.c | 8 ++++---- | ||
15 | target/arm/kvm64.c | 14 +++++++------- | ||
16 | 4 files changed, 28 insertions(+), 16 deletions(-) | ||
17 | |||
18 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/arm/internals.h | ||
21 | +++ b/target/arm/internals.h | ||
22 | @@ -XXX,XX +XXX,XX @@ FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ | ||
23 | */ | ||
24 | #define FNC_RETURN_MIN_MAGIC 0xfefffffe | ||
25 | |||
26 | +/* Bit definitions for DBGWCRn and DBGWCRn_EL1 */ | ||
27 | +FIELD(DBGWCR, E, 0, 1) | ||
28 | +FIELD(DBGWCR, PAC, 1, 2) | ||
29 | +FIELD(DBGWCR, LSC, 3, 2) | ||
30 | +FIELD(DBGWCR, BAS, 5, 8) | ||
31 | +FIELD(DBGWCR, HMC, 13, 1) | ||
32 | +FIELD(DBGWCR, SSC, 14, 2) | ||
33 | +FIELD(DBGWCR, LBN, 16, 4) | ||
34 | +FIELD(DBGWCR, WT, 20, 1) | ||
35 | +FIELD(DBGWCR, MASK, 24, 5) | ||
36 | +FIELD(DBGWCR, SSCE, 29, 1) | ||
37 | + | ||
38 | /* We use a few fake FSR values for internal purposes in M profile. | ||
39 | * M profile cores don't have A/R format FSRs, but currently our | ||
40 | * get_phys_addr() code assumes A/R profile and reports failures via | ||
41 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/target/arm/debug_helper.c | ||
44 | +++ b/target/arm/debug_helper.c | ||
45 | @@ -XXX,XX +XXX,XX @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp) | ||
46 | * Non-Secure to simplify the code slightly compared to the full | ||
47 | * table in the ARM ARM. | ||
48 | */ | ||
49 | - pac = extract64(cr, 1, 2); | ||
50 | - hmc = extract64(cr, 13, 1); | ||
51 | - ssc = extract64(cr, 14, 2); | ||
52 | + pac = FIELD_EX64(cr, DBGWCR, PAC); | ||
53 | + hmc = FIELD_EX64(cr, DBGWCR, HMC); | ||
54 | + ssc = FIELD_EX64(cr, DBGWCR, SSC); | ||
55 | |||
56 | switch (ssc) { | ||
57 | case 0: | ||
58 | @@ -XXX,XX +XXX,XX @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp) | ||
59 | g_assert_not_reached(); | ||
60 | } | ||
61 | |||
62 | - wt = extract64(cr, 20, 1); | ||
63 | - lbn = extract64(cr, 16, 4); | ||
64 | + wt = FIELD_EX64(cr, DBGWCR, WT); | ||
65 | + lbn = FIELD_EX64(cr, DBGWCR, LBN); | ||
66 | |||
67 | if (wt && !linked_bp_matches(cpu, lbn)) { | ||
68 | return false; | ||
69 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
70 | index XXXXXXX..XXXXXXX 100644 | ||
71 | --- a/target/arm/helper.c | ||
72 | +++ b/target/arm/helper.c | ||
73 | @@ -XXX,XX +XXX,XX @@ void hw_watchpoint_update(ARMCPU *cpu, int n) | ||
74 | env->cpu_watchpoint[n] = NULL; | ||
75 | } | ||
76 | |||
77 | - if (!extract64(wcr, 0, 1)) { | ||
78 | + if (!FIELD_EX64(wcr, DBGWCR, E)) { | ||
79 | /* E bit clear : watchpoint disabled */ | ||
80 | return; | ||
81 | } | ||
82 | |||
83 | - switch (extract64(wcr, 3, 2)) { | ||
84 | + switch (FIELD_EX64(wcr, DBGWCR, LSC)) { | ||
85 | case 0: | ||
86 | /* LSC 00 is reserved and must behave as if the wp is disabled */ | ||
87 | return; | ||
88 | @@ -XXX,XX +XXX,XX @@ void hw_watchpoint_update(ARMCPU *cpu, int n) | ||
89 | * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, | ||
90 | * thus generating a watchpoint for every byte in the masked region. | ||
91 | */ | ||
92 | - mask = extract64(wcr, 24, 4); | ||
93 | + mask = FIELD_EX64(wcr, DBGWCR, MASK); | ||
94 | if (mask == 1 || mask == 2) { | ||
95 | /* Reserved values of MASK; we must act as if the mask value was | ||
96 | * some non-reserved value, or as if the watchpoint were disabled. | ||
97 | @@ -XXX,XX +XXX,XX @@ void hw_watchpoint_update(ARMCPU *cpu, int n) | ||
98 | wvr &= ~(len - 1); | ||
99 | } else { | ||
100 | /* Watchpoint covers bytes defined by the byte address select bits */ | ||
101 | - int bas = extract64(wcr, 5, 8); | ||
102 | + int bas = FIELD_EX64(wcr, DBGWCR, BAS); | ||
103 | int basstart; | ||
104 | |||
105 | if (extract64(wvr, 2, 1)) { | ||
106 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
107 | index XXXXXXX..XXXXXXX 100644 | ||
108 | --- a/target/arm/kvm64.c | ||
109 | +++ b/target/arm/kvm64.c | ||
110 | @@ -XXX,XX +XXX,XX @@ static int insert_hw_watchpoint(target_ulong addr, | ||
111 | target_ulong len, int type) | ||
112 | { | ||
113 | HWWatchpoint wp = { | ||
114 | - .wcr = 1, /* E=1, enable */ | ||
115 | + .wcr = R_DBGWCR_E_MASK, /* E=1, enable */ | ||
116 | .wvr = addr & (~0x7ULL), | ||
117 | .details = { .vaddr = addr, .len = len } | ||
118 | }; | ||
119 | @@ -XXX,XX +XXX,XX @@ static int insert_hw_watchpoint(target_ulong addr, | ||
120 | * HMC=0 SSC=0 PAC=3 will hit EL0 or EL1, any security state, | ||
121 | * valid whether EL3 is implemented or not | ||
122 | */ | ||
123 | - wp.wcr = deposit32(wp.wcr, 1, 2, 3); | ||
124 | + wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, PAC, 3); | ||
125 | |||
126 | switch (type) { | ||
127 | case GDB_WATCHPOINT_READ: | ||
128 | - wp.wcr = deposit32(wp.wcr, 3, 2, 1); | ||
129 | + wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 1); | ||
130 | wp.details.flags = BP_MEM_READ; | ||
131 | break; | ||
132 | case GDB_WATCHPOINT_WRITE: | ||
133 | - wp.wcr = deposit32(wp.wcr, 3, 2, 2); | ||
134 | + wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 2); | ||
135 | wp.details.flags = BP_MEM_WRITE; | ||
136 | break; | ||
137 | case GDB_WATCHPOINT_ACCESS: | ||
138 | - wp.wcr = deposit32(wp.wcr, 3, 2, 3); | ||
139 | + wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 3); | ||
140 | wp.details.flags = BP_MEM_ACCESS; | ||
141 | break; | ||
142 | default: | ||
143 | @@ -XXX,XX +XXX,XX @@ static int insert_hw_watchpoint(target_ulong addr, | ||
144 | int bits = ctz64(len); | ||
145 | |||
146 | wp.wvr &= ~((1 << bits) - 1); | ||
147 | - wp.wcr = deposit32(wp.wcr, 24, 4, bits); | ||
148 | - wp.wcr = deposit32(wp.wcr, 5, 8, 0xff); | ||
149 | + wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, MASK, bits); | ||
150 | + wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, BAS, 0xff); | ||
151 | } else { | ||
152 | return -ENOBUFS; | ||
153 | } | ||
154 | -- | ||
155 | 2.25.1 | ||
156 | |||
157 | diff view generated by jsdifflib |
1 | It's not possible to provide the guest with the Security extensions | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | (TrustZone) when using KVM or HVF, because the hardware | ||
3 | virtualization extensions don't permit running EL3 guest code. | ||
4 | However, we weren't checking for this combination, with the result | ||
5 | that QEMU would assert if you tried it: | ||
6 | 2 | ||
7 | $ qemu-system-aarch64 -enable-kvm -machine virt,secure=on -cpu host -display none | 3 | The Record bit in the Context Descriptor tells the SMMU to report fault |
8 | Unexpected error in object_property_find_err() at ../../qom/object.c:1304: | 4 | events to the event queue. Since we don't cache the Record bit at the |
9 | qemu-system-aarch64: Property 'host-arm-cpu.secure-memory' not found | 5 | moment, access faults from a cached Context Descriptor are never |
10 | Aborted | 6 | reported. Store the Record bit in the cached SMMUTransCfg. |
11 | 7 | ||
12 | Check for this combination of options and report an error, in the | 8 | Fixes: 9bde7f0674fe ("hw/arm/smmuv3: Implement translate callback") |
13 | same way we already do for attempts to give a KVM or HVF guest the | 9 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> |
14 | Virtualization or MTE extensions. Now we will report: | 10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
11 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
12 | Message-id: 20220427111543.124620-1-jean-philippe@linaro.org | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | hw/arm/smmuv3-internal.h | 1 - | ||
16 | include/hw/arm/smmu-common.h | 1 + | ||
17 | hw/arm/smmuv3.c | 14 +++++++------- | ||
18 | 3 files changed, 8 insertions(+), 8 deletions(-) | ||
15 | 19 | ||
16 | qemu-system-aarch64: mach-virt: KVM does not support providing Security extensions (TrustZone) to the guest CPU | 20 | diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h |
17 | |||
18 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/961 | ||
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
20 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
21 | Message-id: 20220404155301.566542-1-peter.maydell@linaro.org | ||
22 | --- | ||
23 | hw/arm/virt.c | 7 +++++++ | ||
24 | 1 file changed, 7 insertions(+) | ||
25 | |||
26 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
28 | --- a/hw/arm/virt.c | 22 | --- a/hw/arm/smmuv3-internal.h |
29 | +++ b/hw/arm/virt.c | 23 | +++ b/hw/arm/smmuv3-internal.h |
30 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | 24 | @@ -XXX,XX +XXX,XX @@ typedef struct SMMUEventInfo { |
31 | exit(1); | 25 | SMMUEventType type; |
26 | uint32_t sid; | ||
27 | bool recorded; | ||
28 | - bool record_trans_faults; | ||
29 | bool inval_ste_allowed; | ||
30 | union { | ||
31 | struct { | ||
32 | diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/include/hw/arm/smmu-common.h | ||
35 | +++ b/include/hw/arm/smmu-common.h | ||
36 | @@ -XXX,XX +XXX,XX @@ typedef struct SMMUTransCfg { | ||
37 | bool disabled; /* smmu is disabled */ | ||
38 | bool bypassed; /* translation is bypassed */ | ||
39 | bool aborted; /* translation is aborted */ | ||
40 | + bool record_faults; /* record fault events */ | ||
41 | uint64_t ttb; /* TT base address */ | ||
42 | uint8_t oas; /* output address width */ | ||
43 | uint8_t tbi; /* Top Byte Ignore */ | ||
44 | diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/hw/arm/smmuv3.c | ||
47 | +++ b/hw/arm/smmuv3.c | ||
48 | @@ -XXX,XX +XXX,XX @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event) | ||
49 | trace_smmuv3_decode_cd_tt(i, tt->tsz, tt->ttb, tt->granule_sz, tt->had); | ||
32 | } | 50 | } |
33 | 51 | ||
34 | + if (vms->secure && (kvm_enabled() || hvf_enabled())) { | 52 | - event->record_trans_faults = CD_R(cd); |
35 | + error_report("mach-virt: %s does not support providing " | 53 | + cfg->record_faults = CD_R(cd); |
36 | + "Security extensions (TrustZone) to the guest CPU", | 54 | |
37 | + kvm_enabled() ? "KVM" : "HVF"); | 55 | return 0; |
38 | + exit(1); | 56 | |
39 | + } | 57 | @@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, |
40 | + | 58 | |
41 | if (vms->virt && (kvm_enabled() || hvf_enabled())) { | 59 | tt = select_tt(cfg, addr); |
42 | error_report("mach-virt: %s does not support providing " | 60 | if (!tt) { |
43 | "Virtualization extensions to the guest CPU", | 61 | - if (event.record_trans_faults) { |
62 | + if (cfg->record_faults) { | ||
63 | event.type = SMMU_EVT_F_TRANSLATION; | ||
64 | event.u.f_translation.addr = addr; | ||
65 | event.u.f_translation.rnw = flag & 0x1; | ||
66 | @@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, | ||
67 | if (cached_entry) { | ||
68 | if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) { | ||
69 | status = SMMU_TRANS_ERROR; | ||
70 | - if (event.record_trans_faults) { | ||
71 | + if (cfg->record_faults) { | ||
72 | event.type = SMMU_EVT_F_PERMISSION; | ||
73 | event.u.f_permission.addr = addr; | ||
74 | event.u.f_permission.rnw = flag & 0x1; | ||
75 | @@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, | ||
76 | event.u.f_walk_eabt.addr2 = ptw_info.addr; | ||
77 | break; | ||
78 | case SMMU_PTW_ERR_TRANSLATION: | ||
79 | - if (event.record_trans_faults) { | ||
80 | + if (cfg->record_faults) { | ||
81 | event.type = SMMU_EVT_F_TRANSLATION; | ||
82 | event.u.f_translation.addr = addr; | ||
83 | event.u.f_translation.rnw = flag & 0x1; | ||
84 | } | ||
85 | break; | ||
86 | case SMMU_PTW_ERR_ADDR_SIZE: | ||
87 | - if (event.record_trans_faults) { | ||
88 | + if (cfg->record_faults) { | ||
89 | event.type = SMMU_EVT_F_ADDR_SIZE; | ||
90 | event.u.f_addr_size.addr = addr; | ||
91 | event.u.f_addr_size.rnw = flag & 0x1; | ||
92 | } | ||
93 | break; | ||
94 | case SMMU_PTW_ERR_ACCESS: | ||
95 | - if (event.record_trans_faults) { | ||
96 | + if (cfg->record_faults) { | ||
97 | event.type = SMMU_EVT_F_ACCESS; | ||
98 | event.u.f_access.addr = addr; | ||
99 | event.u.f_access.rnw = flag & 0x1; | ||
100 | } | ||
101 | break; | ||
102 | case SMMU_PTW_ERR_PERMISSION: | ||
103 | - if (event.record_trans_faults) { | ||
104 | + if (cfg->record_faults) { | ||
105 | event.type = SMMU_EVT_F_PERMISSION; | ||
106 | event.u.f_permission.addr = addr; | ||
107 | event.u.f_permission.rnw = flag & 0x1; | ||
44 | -- | 108 | -- |
45 | 2.25.1 | 109 | 2.25.1 | diff view generated by jsdifflib |
1 | Fix a missing set of spaces around '-' in the definition of | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | combiner_grp_to_gic_id[]. We're about to move this code, so | ||
3 | fix the style issue first to keep checkpatch happy with the | ||
4 | code-motion patch. | ||
5 | 2 | ||
3 | Make the translation error message prettier by adding a missing space | ||
4 | before the parenthesis. | ||
5 | |||
6 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
9 | Message-id: 20220427111543.124620-2-jean-philippe@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220404154658.565020-7-peter.maydell@linaro.org | ||
9 | --- | 11 | --- |
10 | hw/intc/exynos4210_gic.c | 2 +- | 12 | hw/arm/smmuv3.c | 2 +- |
11 | 1 file changed, 1 insertion(+), 1 deletion(-) | 13 | 1 file changed, 1 insertion(+), 1 deletion(-) |
12 | 14 | ||
13 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | 15 | diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c |
14 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/intc/exynos4210_gic.c | 17 | --- a/hw/arm/smmuv3.c |
16 | +++ b/hw/intc/exynos4210_gic.c | 18 | +++ b/hw/arm/smmuv3.c |
17 | @@ -XXX,XX +XXX,XX @@ enum ExtInt { | 19 | @@ -XXX,XX +XXX,XX @@ epilogue: |
18 | */ | 20 | break; |
19 | 21 | case SMMU_TRANS_ERROR: | |
20 | static const uint32_t | 22 | qemu_log_mask(LOG_GUEST_ERROR, |
21 | -combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | 23 | - "%s translation failed for iova=0x%"PRIx64"(%s)\n", |
22 | +combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | 24 | + "%s translation failed for iova=0x%"PRIx64" (%s)\n", |
23 | /* int combiner groups 16-19 */ | 25 | mr->parent_obj.name, addr, smmu_event_string(event.type)); |
24 | { }, { }, { }, { }, | 26 | smmuv3_record_event(s, &event); |
25 | /* int combiner group 20 */ | 27 | break; |
26 | -- | 28 | -- |
27 | 2.25.1 | 29 | 2.25.1 | diff view generated by jsdifflib |
1 | The function exynos4210_init_board_irqs() currently lives in | 1 | The Arm FEAT_TTL architectural feature allows the guest to provide an |
---|---|---|---|
2 | exynos4210_gic.c, but it isn't really part of the exynos4210.gic | 2 | optional hint in an AArch64 TLB invalidate operation about which |
3 | device -- it is a function that implements (some of) the wiring up of | 3 | translation table level holds the leaf entry for the address being |
4 | interrupts between the SoC's GIC and combiner components. This means | 4 | invalidated. QEMU's TLB implementation doesn't need that hint, and |
5 | it fits better in exynos4210.c, which is the SoC-level code. Move it | 5 | we correctly ignore the (previously RES0) bits in TLB invalidate |
6 | there. Similarly, exynos4210_git_irq() is used almost only in the | 6 | operation values that are now used for the TTL field. So we can |
7 | SoC-level code, so move it too. | 7 | simply advertise support for it in our 'max' CPU. |
8 | 8 | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
11 | Message-id: 20220404154658.565020-8-peter.maydell@linaro.org | 11 | Message-id: 20220426160422.2353158-2-peter.maydell@linaro.org |
12 | --- | 12 | --- |
13 | include/hw/arm/exynos4210.h | 4 - | 13 | docs/system/arm/emulation.rst | 1 + |
14 | hw/arm/exynos4210.c | 202 +++++++++++++++++++++++++++++++++++ | 14 | target/arm/cpu64.c | 1 + |
15 | hw/intc/exynos4210_gic.c | 204 ------------------------------------ | 15 | 2 files changed, 2 insertions(+) |
16 | 3 files changed, 202 insertions(+), 208 deletions(-) | ||
17 | 16 | ||
18 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | 17 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
19 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/include/hw/arm/exynos4210.h | 19 | --- a/docs/system/arm/emulation.rst |
21 | +++ b/include/hw/arm/exynos4210.h | 20 | +++ b/docs/system/arm/emulation.rst |
22 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC) | 21 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
23 | void exynos4210_write_secondary(ARMCPU *cpu, | 22 | - FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain) |
24 | const struct arm_boot_info *info); | 23 | - FEAT_TLBIRANGE (TLB invalidate range instructions) |
25 | 24 | - FEAT_TTCNP (Translation table Common not private translations) | |
26 | -/* Initialize board IRQs. | 25 | +- FEAT_TTL (Translation Table Level) |
27 | - * These IRQs contain splitted Int/External Combiner and External Gic IRQs */ | 26 | - FEAT_TTST (Small translation tables) |
28 | -void exynos4210_init_board_irqs(Exynos4210State *s); | 27 | - FEAT_UAO (Unprivileged Access Override control) |
29 | - | 28 | - FEAT_VHE (Virtualization Host Extensions) |
30 | /* Get IRQ number from exynos4210 IRQ subsystem stub. | 29 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
31 | * To identify IRQ source use internal combiner group and bit number | ||
32 | * grp - group number | ||
33 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | 30 | index XXXXXXX..XXXXXXX 100644 |
35 | --- a/hw/arm/exynos4210.c | 31 | --- a/target/arm/cpu64.c |
36 | +++ b/hw/arm/exynos4210.c | 32 | +++ b/target/arm/cpu64.c |
37 | @@ -XXX,XX +XXX,XX @@ | 33 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) |
38 | #define EXYNOS4210_PL330_BASE1_ADDR 0x12690000 | 34 | t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ |
39 | #define EXYNOS4210_PL330_BASE2_ADDR 0x12850000 | 35 | t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ |
40 | 36 | t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ | |
41 | +enum ExtGicId { | 37 | + t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ |
42 | + EXT_GIC_ID_MDMA_LCD0 = 66, | 38 | cpu->isar.id_aa64mmfr2 = t; |
43 | + EXT_GIC_ID_PDMA0, | 39 | |
44 | + EXT_GIC_ID_PDMA1, | 40 | t = cpu->isar.id_aa64zfr0; |
45 | + EXT_GIC_ID_TIMER0, | ||
46 | + EXT_GIC_ID_TIMER1, | ||
47 | + EXT_GIC_ID_TIMER2, | ||
48 | + EXT_GIC_ID_TIMER3, | ||
49 | + EXT_GIC_ID_TIMER4, | ||
50 | + EXT_GIC_ID_MCT_L0, | ||
51 | + EXT_GIC_ID_WDT, | ||
52 | + EXT_GIC_ID_RTC_ALARM, | ||
53 | + EXT_GIC_ID_RTC_TIC, | ||
54 | + EXT_GIC_ID_GPIO_XB, | ||
55 | + EXT_GIC_ID_GPIO_XA, | ||
56 | + EXT_GIC_ID_MCT_L1, | ||
57 | + EXT_GIC_ID_IEM_APC, | ||
58 | + EXT_GIC_ID_IEM_IEC, | ||
59 | + EXT_GIC_ID_NFC, | ||
60 | + EXT_GIC_ID_UART0, | ||
61 | + EXT_GIC_ID_UART1, | ||
62 | + EXT_GIC_ID_UART2, | ||
63 | + EXT_GIC_ID_UART3, | ||
64 | + EXT_GIC_ID_UART4, | ||
65 | + EXT_GIC_ID_MCT_G0, | ||
66 | + EXT_GIC_ID_I2C0, | ||
67 | + EXT_GIC_ID_I2C1, | ||
68 | + EXT_GIC_ID_I2C2, | ||
69 | + EXT_GIC_ID_I2C3, | ||
70 | + EXT_GIC_ID_I2C4, | ||
71 | + EXT_GIC_ID_I2C5, | ||
72 | + EXT_GIC_ID_I2C6, | ||
73 | + EXT_GIC_ID_I2C7, | ||
74 | + EXT_GIC_ID_SPI0, | ||
75 | + EXT_GIC_ID_SPI1, | ||
76 | + EXT_GIC_ID_SPI2, | ||
77 | + EXT_GIC_ID_MCT_G1, | ||
78 | + EXT_GIC_ID_USB_HOST, | ||
79 | + EXT_GIC_ID_USB_DEVICE, | ||
80 | + EXT_GIC_ID_MODEMIF, | ||
81 | + EXT_GIC_ID_HSMMC0, | ||
82 | + EXT_GIC_ID_HSMMC1, | ||
83 | + EXT_GIC_ID_HSMMC2, | ||
84 | + EXT_GIC_ID_HSMMC3, | ||
85 | + EXT_GIC_ID_SDMMC, | ||
86 | + EXT_GIC_ID_MIPI_CSI_4LANE, | ||
87 | + EXT_GIC_ID_MIPI_DSI_4LANE, | ||
88 | + EXT_GIC_ID_MIPI_CSI_2LANE, | ||
89 | + EXT_GIC_ID_MIPI_DSI_2LANE, | ||
90 | + EXT_GIC_ID_ONENAND_AUDI, | ||
91 | + EXT_GIC_ID_ROTATOR, | ||
92 | + EXT_GIC_ID_FIMC0, | ||
93 | + EXT_GIC_ID_FIMC1, | ||
94 | + EXT_GIC_ID_FIMC2, | ||
95 | + EXT_GIC_ID_FIMC3, | ||
96 | + EXT_GIC_ID_JPEG, | ||
97 | + EXT_GIC_ID_2D, | ||
98 | + EXT_GIC_ID_PCIe, | ||
99 | + EXT_GIC_ID_MIXER, | ||
100 | + EXT_GIC_ID_HDMI, | ||
101 | + EXT_GIC_ID_HDMI_I2C, | ||
102 | + EXT_GIC_ID_MFC, | ||
103 | + EXT_GIC_ID_TVENC, | ||
104 | +}; | ||
105 | + | ||
106 | +enum ExtInt { | ||
107 | + EXT_GIC_ID_EXTINT0 = 48, | ||
108 | + EXT_GIC_ID_EXTINT1, | ||
109 | + EXT_GIC_ID_EXTINT2, | ||
110 | + EXT_GIC_ID_EXTINT3, | ||
111 | + EXT_GIC_ID_EXTINT4, | ||
112 | + EXT_GIC_ID_EXTINT5, | ||
113 | + EXT_GIC_ID_EXTINT6, | ||
114 | + EXT_GIC_ID_EXTINT7, | ||
115 | + EXT_GIC_ID_EXTINT8, | ||
116 | + EXT_GIC_ID_EXTINT9, | ||
117 | + EXT_GIC_ID_EXTINT10, | ||
118 | + EXT_GIC_ID_EXTINT11, | ||
119 | + EXT_GIC_ID_EXTINT12, | ||
120 | + EXT_GIC_ID_EXTINT13, | ||
121 | + EXT_GIC_ID_EXTINT14, | ||
122 | + EXT_GIC_ID_EXTINT15 | ||
123 | +}; | ||
124 | + | ||
125 | +/* | ||
126 | + * External GIC sources which are not from External Interrupt Combiner or | ||
127 | + * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ, | ||
128 | + * which is INTG16 in Internal Interrupt Combiner. | ||
129 | + */ | ||
130 | + | ||
131 | +static const uint32_t | ||
132 | +combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
133 | + /* int combiner groups 16-19 */ | ||
134 | + { }, { }, { }, { }, | ||
135 | + /* int combiner group 20 */ | ||
136 | + { 0, EXT_GIC_ID_MDMA_LCD0 }, | ||
137 | + /* int combiner group 21 */ | ||
138 | + { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 }, | ||
139 | + /* int combiner group 22 */ | ||
140 | + { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2, | ||
141 | + EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 }, | ||
142 | + /* int combiner group 23 */ | ||
143 | + { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC }, | ||
144 | + /* int combiner group 24 */ | ||
145 | + { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA }, | ||
146 | + /* int combiner group 25 */ | ||
147 | + { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC }, | ||
148 | + /* int combiner group 26 */ | ||
149 | + { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3, | ||
150 | + EXT_GIC_ID_UART4 }, | ||
151 | + /* int combiner group 27 */ | ||
152 | + { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3, | ||
153 | + EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6, | ||
154 | + EXT_GIC_ID_I2C7 }, | ||
155 | + /* int combiner group 28 */ | ||
156 | + { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST}, | ||
157 | + /* int combiner group 29 */ | ||
158 | + { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2, | ||
159 | + EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC }, | ||
160 | + /* int combiner group 30 */ | ||
161 | + { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE }, | ||
162 | + /* int combiner group 31 */ | ||
163 | + { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE }, | ||
164 | + /* int combiner group 32 */ | ||
165 | + { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 }, | ||
166 | + /* int combiner group 33 */ | ||
167 | + { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 }, | ||
168 | + /* int combiner group 34 */ | ||
169 | + { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, | ||
170 | + /* int combiner group 35 */ | ||
171 | + { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
172 | + /* int combiner group 36 */ | ||
173 | + { EXT_GIC_ID_MIXER }, | ||
174 | + /* int combiner group 37 */ | ||
175 | + { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6, | ||
176 | + EXT_GIC_ID_EXTINT7 }, | ||
177 | + /* groups 38-50 */ | ||
178 | + { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, | ||
179 | + /* int combiner group 51 */ | ||
180 | + { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
181 | + /* group 52 */ | ||
182 | + { }, | ||
183 | + /* int combiner group 53 */ | ||
184 | + { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
185 | + /* groups 54-63 */ | ||
186 | + { }, { }, { }, { }, { }, { }, { }, { }, { }, { } | ||
187 | +}; | ||
188 | + | ||
189 | +/* | ||
190 | + * Initialize board IRQs. | ||
191 | + * These IRQs contain splitted Int/External Combiner and External Gic IRQs. | ||
192 | + */ | ||
193 | +static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
194 | +{ | ||
195 | + uint32_t grp, bit, irq_id, n; | ||
196 | + Exynos4210Irq *is = &s->irqs; | ||
197 | + | ||
198 | + for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { | ||
199 | + irq_id = 0; | ||
200 | + if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) || | ||
201 | + n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) { | ||
202 | + /* MCT_G0 is passed to External GIC */ | ||
203 | + irq_id = EXT_GIC_ID_MCT_G0; | ||
204 | + } | ||
205 | + if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) || | ||
206 | + n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) { | ||
207 | + /* MCT_G1 is passed to External and GIC */ | ||
208 | + irq_id = EXT_GIC_ID_MCT_G1; | ||
209 | + } | ||
210 | + if (irq_id) { | ||
211 | + s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
212 | + is->ext_gic_irq[irq_id - 32]); | ||
213 | + } else { | ||
214 | + s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
215 | + is->ext_combiner_irq[n]); | ||
216 | + } | ||
217 | + } | ||
218 | + for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { | ||
219 | + /* these IDs are passed to Internal Combiner and External GIC */ | ||
220 | + grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n); | ||
221 | + bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); | ||
222 | + irq_id = combiner_grp_to_gic_id[grp - | ||
223 | + EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; | ||
224 | + | ||
225 | + if (irq_id) { | ||
226 | + s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
227 | + is->ext_gic_irq[irq_id - 32]); | ||
228 | + } | ||
229 | + } | ||
230 | +} | ||
231 | + | ||
232 | +/* | ||
233 | + * Get IRQ number from exynos4210 IRQ subsystem stub. | ||
234 | + * To identify IRQ source use internal combiner group and bit number | ||
235 | + * grp - group number | ||
236 | + * bit - bit number inside group | ||
237 | + */ | ||
238 | +uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) | ||
239 | +{ | ||
240 | + return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); | ||
241 | +} | ||
242 | + | ||
243 | static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, | ||
244 | 0x09, 0x00, 0x00, 0x00 }; | ||
245 | |||
246 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | ||
247 | index XXXXXXX..XXXXXXX 100644 | ||
248 | --- a/hw/intc/exynos4210_gic.c | ||
249 | +++ b/hw/intc/exynos4210_gic.c | ||
250 | @@ -XXX,XX +XXX,XX @@ | ||
251 | #include "hw/arm/exynos4210.h" | ||
252 | #include "qom/object.h" | ||
253 | |||
254 | -enum ExtGicId { | ||
255 | - EXT_GIC_ID_MDMA_LCD0 = 66, | ||
256 | - EXT_GIC_ID_PDMA0, | ||
257 | - EXT_GIC_ID_PDMA1, | ||
258 | - EXT_GIC_ID_TIMER0, | ||
259 | - EXT_GIC_ID_TIMER1, | ||
260 | - EXT_GIC_ID_TIMER2, | ||
261 | - EXT_GIC_ID_TIMER3, | ||
262 | - EXT_GIC_ID_TIMER4, | ||
263 | - EXT_GIC_ID_MCT_L0, | ||
264 | - EXT_GIC_ID_WDT, | ||
265 | - EXT_GIC_ID_RTC_ALARM, | ||
266 | - EXT_GIC_ID_RTC_TIC, | ||
267 | - EXT_GIC_ID_GPIO_XB, | ||
268 | - EXT_GIC_ID_GPIO_XA, | ||
269 | - EXT_GIC_ID_MCT_L1, | ||
270 | - EXT_GIC_ID_IEM_APC, | ||
271 | - EXT_GIC_ID_IEM_IEC, | ||
272 | - EXT_GIC_ID_NFC, | ||
273 | - EXT_GIC_ID_UART0, | ||
274 | - EXT_GIC_ID_UART1, | ||
275 | - EXT_GIC_ID_UART2, | ||
276 | - EXT_GIC_ID_UART3, | ||
277 | - EXT_GIC_ID_UART4, | ||
278 | - EXT_GIC_ID_MCT_G0, | ||
279 | - EXT_GIC_ID_I2C0, | ||
280 | - EXT_GIC_ID_I2C1, | ||
281 | - EXT_GIC_ID_I2C2, | ||
282 | - EXT_GIC_ID_I2C3, | ||
283 | - EXT_GIC_ID_I2C4, | ||
284 | - EXT_GIC_ID_I2C5, | ||
285 | - EXT_GIC_ID_I2C6, | ||
286 | - EXT_GIC_ID_I2C7, | ||
287 | - EXT_GIC_ID_SPI0, | ||
288 | - EXT_GIC_ID_SPI1, | ||
289 | - EXT_GIC_ID_SPI2, | ||
290 | - EXT_GIC_ID_MCT_G1, | ||
291 | - EXT_GIC_ID_USB_HOST, | ||
292 | - EXT_GIC_ID_USB_DEVICE, | ||
293 | - EXT_GIC_ID_MODEMIF, | ||
294 | - EXT_GIC_ID_HSMMC0, | ||
295 | - EXT_GIC_ID_HSMMC1, | ||
296 | - EXT_GIC_ID_HSMMC2, | ||
297 | - EXT_GIC_ID_HSMMC3, | ||
298 | - EXT_GIC_ID_SDMMC, | ||
299 | - EXT_GIC_ID_MIPI_CSI_4LANE, | ||
300 | - EXT_GIC_ID_MIPI_DSI_4LANE, | ||
301 | - EXT_GIC_ID_MIPI_CSI_2LANE, | ||
302 | - EXT_GIC_ID_MIPI_DSI_2LANE, | ||
303 | - EXT_GIC_ID_ONENAND_AUDI, | ||
304 | - EXT_GIC_ID_ROTATOR, | ||
305 | - EXT_GIC_ID_FIMC0, | ||
306 | - EXT_GIC_ID_FIMC1, | ||
307 | - EXT_GIC_ID_FIMC2, | ||
308 | - EXT_GIC_ID_FIMC3, | ||
309 | - EXT_GIC_ID_JPEG, | ||
310 | - EXT_GIC_ID_2D, | ||
311 | - EXT_GIC_ID_PCIe, | ||
312 | - EXT_GIC_ID_MIXER, | ||
313 | - EXT_GIC_ID_HDMI, | ||
314 | - EXT_GIC_ID_HDMI_I2C, | ||
315 | - EXT_GIC_ID_MFC, | ||
316 | - EXT_GIC_ID_TVENC, | ||
317 | -}; | ||
318 | - | ||
319 | -enum ExtInt { | ||
320 | - EXT_GIC_ID_EXTINT0 = 48, | ||
321 | - EXT_GIC_ID_EXTINT1, | ||
322 | - EXT_GIC_ID_EXTINT2, | ||
323 | - EXT_GIC_ID_EXTINT3, | ||
324 | - EXT_GIC_ID_EXTINT4, | ||
325 | - EXT_GIC_ID_EXTINT5, | ||
326 | - EXT_GIC_ID_EXTINT6, | ||
327 | - EXT_GIC_ID_EXTINT7, | ||
328 | - EXT_GIC_ID_EXTINT8, | ||
329 | - EXT_GIC_ID_EXTINT9, | ||
330 | - EXT_GIC_ID_EXTINT10, | ||
331 | - EXT_GIC_ID_EXTINT11, | ||
332 | - EXT_GIC_ID_EXTINT12, | ||
333 | - EXT_GIC_ID_EXTINT13, | ||
334 | - EXT_GIC_ID_EXTINT14, | ||
335 | - EXT_GIC_ID_EXTINT15 | ||
336 | -}; | ||
337 | - | ||
338 | -/* | ||
339 | - * External GIC sources which are not from External Interrupt Combiner or | ||
340 | - * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ, | ||
341 | - * which is INTG16 in Internal Interrupt Combiner. | ||
342 | - */ | ||
343 | - | ||
344 | -static const uint32_t | ||
345 | -combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
346 | - /* int combiner groups 16-19 */ | ||
347 | - { }, { }, { }, { }, | ||
348 | - /* int combiner group 20 */ | ||
349 | - { 0, EXT_GIC_ID_MDMA_LCD0 }, | ||
350 | - /* int combiner group 21 */ | ||
351 | - { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 }, | ||
352 | - /* int combiner group 22 */ | ||
353 | - { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2, | ||
354 | - EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 }, | ||
355 | - /* int combiner group 23 */ | ||
356 | - { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC }, | ||
357 | - /* int combiner group 24 */ | ||
358 | - { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA }, | ||
359 | - /* int combiner group 25 */ | ||
360 | - { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC }, | ||
361 | - /* int combiner group 26 */ | ||
362 | - { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3, | ||
363 | - EXT_GIC_ID_UART4 }, | ||
364 | - /* int combiner group 27 */ | ||
365 | - { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3, | ||
366 | - EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6, | ||
367 | - EXT_GIC_ID_I2C7 }, | ||
368 | - /* int combiner group 28 */ | ||
369 | - { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST}, | ||
370 | - /* int combiner group 29 */ | ||
371 | - { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2, | ||
372 | - EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC }, | ||
373 | - /* int combiner group 30 */ | ||
374 | - { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE }, | ||
375 | - /* int combiner group 31 */ | ||
376 | - { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE }, | ||
377 | - /* int combiner group 32 */ | ||
378 | - { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 }, | ||
379 | - /* int combiner group 33 */ | ||
380 | - { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 }, | ||
381 | - /* int combiner group 34 */ | ||
382 | - { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, | ||
383 | - /* int combiner group 35 */ | ||
384 | - { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
385 | - /* int combiner group 36 */ | ||
386 | - { EXT_GIC_ID_MIXER }, | ||
387 | - /* int combiner group 37 */ | ||
388 | - { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6, | ||
389 | - EXT_GIC_ID_EXTINT7 }, | ||
390 | - /* groups 38-50 */ | ||
391 | - { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, | ||
392 | - /* int combiner group 51 */ | ||
393 | - { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
394 | - /* group 52 */ | ||
395 | - { }, | ||
396 | - /* int combiner group 53 */ | ||
397 | - { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
398 | - /* groups 54-63 */ | ||
399 | - { }, { }, { }, { }, { }, { }, { }, { }, { }, { } | ||
400 | -}; | ||
401 | - | ||
402 | #define EXYNOS4210_GIC_NIRQ 160 | ||
403 | |||
404 | #define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE 0x10000 | ||
405 | @@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
406 | #define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100 | ||
407 | #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000 | ||
408 | |||
409 | -/* | ||
410 | - * Initialize board IRQs. | ||
411 | - * These IRQs contain splitted Int/External Combiner and External Gic IRQs. | ||
412 | - */ | ||
413 | -void exynos4210_init_board_irqs(Exynos4210State *s) | ||
414 | -{ | ||
415 | - uint32_t grp, bit, irq_id, n; | ||
416 | - Exynos4210Irq *is = &s->irqs; | ||
417 | - | ||
418 | - for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { | ||
419 | - irq_id = 0; | ||
420 | - if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) || | ||
421 | - n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) { | ||
422 | - /* MCT_G0 is passed to External GIC */ | ||
423 | - irq_id = EXT_GIC_ID_MCT_G0; | ||
424 | - } | ||
425 | - if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) || | ||
426 | - n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) { | ||
427 | - /* MCT_G1 is passed to External and GIC */ | ||
428 | - irq_id = EXT_GIC_ID_MCT_G1; | ||
429 | - } | ||
430 | - if (irq_id) { | ||
431 | - s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
432 | - is->ext_gic_irq[irq_id - 32]); | ||
433 | - } else { | ||
434 | - s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
435 | - is->ext_combiner_irq[n]); | ||
436 | - } | ||
437 | - } | ||
438 | - for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { | ||
439 | - /* these IDs are passed to Internal Combiner and External GIC */ | ||
440 | - grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n); | ||
441 | - bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); | ||
442 | - irq_id = combiner_grp_to_gic_id[grp - | ||
443 | - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; | ||
444 | - | ||
445 | - if (irq_id) { | ||
446 | - s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
447 | - is->ext_gic_irq[irq_id - 32]); | ||
448 | - } | ||
449 | - } | ||
450 | -} | ||
451 | - | ||
452 | -/* | ||
453 | - * Get IRQ number from exynos4210 IRQ subsystem stub. | ||
454 | - * To identify IRQ source use internal combiner group and bit number | ||
455 | - * grp - group number | ||
456 | - * bit - bit number inside group | ||
457 | - */ | ||
458 | -uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) | ||
459 | -{ | ||
460 | - return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); | ||
461 | -} | ||
462 | - | ||
463 | -/********* GIC part *********/ | ||
464 | - | ||
465 | #define TYPE_EXYNOS4210_GIC "exynos4210.gic" | ||
466 | OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC) | ||
467 | |||
468 | -- | 41 | -- |
469 | 2.25.1 | 42 | 2.25.1 | diff view generated by jsdifflib |
1 | Delete a couple of #defines which are never used. | 1 | The description in the Arm ARM of the requirements of FEAT_BBM is |
---|---|---|---|
2 | admirably clear on the guarantees it provides software, but slightly | ||
3 | more obscure on what that means for implementations. The description | ||
4 | of the equivalent SMMU feature in the SMMU specification (IHI0070D.b | ||
5 | section 3.21.1) is perhaps a bit more detailed and includes some | ||
6 | example valid implementation choices. (The SMMU version of this | ||
7 | feature is slightly tighter than the CPU version: the CPU is permitted | ||
8 | to raise TLB Conflict aborts in some situations that the SMMU may | ||
9 | not. This doesn't matter for QEMU because we don't want to do TLB | ||
10 | Conflict aborts anyway.) | ||
11 | |||
12 | The informal summary of FEAT_BBM is that it is about permitting an OS | ||
13 | to switch a range of memory between "covered by a huge page" and | ||
14 | "covered by a sequence of normal pages" without having to engage in | ||
15 | the 'break-before-make' dance that has traditionally been | ||
16 | necessary. The 'break-before-make' sequence is: | ||
17 | |||
18 | * replace the old translation table entry with an invalid entry | ||
19 | * execute a DSB insn | ||
20 | * execute a broadcast TLB invalidate insn | ||
21 | * execute a DSB insn | ||
22 | * write the new translation table entry | ||
23 | * execute a DSB insn | ||
24 | |||
25 | The point of this is to ensure that no TLB can simultaneously contain | ||
26 | TLB entries for the old and the new entry, which would traditionally | ||
27 | be UNPREDICTABLE (allowing the CPU to generate a TLB Conflict fault | ||
28 | or to use a random mishmash of values from the old and the new | ||
29 | entry). FEAT_BBM level 2 says "for the specific case where the only | ||
30 | thing that changed is the size of the block, the TLB is guaranteed | ||
31 | not to do weird things even if there are multiple entries for an | ||
32 | address", which means that software can now do: | ||
33 | |||
34 | * replace old translation table entry with new entry | ||
35 | * DSB | ||
36 | * broadcast TLB invalidate | ||
37 | * DSB | ||
38 | |||
39 | As the SMMU spec notes, valid ways to do this include: | ||
40 | |||
41 | * if there are multiple entries in the TLB for an address, | ||
42 | choose one of them and use it, ignoring the others | ||
43 | * if there are multiple entries in the TLB for an address, | ||
44 | throw them all out and do a page table walk to get a new one | ||
45 | |||
46 | QEMU's page table walk implementation for Arm CPUs already meets the | ||
47 | requirements for FEAT_BBM level 2. When we cache an entry in our TCG | ||
48 | TLB, we do so only for the specific (non-huge) page that the address | ||
49 | is in, and there is no way for the TLB data structure to ever have | ||
50 | more than one TLB entry for that page. (We handle huge pages only in | ||
51 | that we track what part of the address space is covered by huge pages | ||
52 | so that a TLB invalidate operation for an address in a huge page | ||
53 | results in an invalidation of the whole TLB.) We ignore the Contiguous | ||
54 | bit in page table entries, so we don't have to do anything for the | ||
55 | parts of FEAT_BBM that deal with changis to the Contiguous bit. | ||
56 | |||
57 | FEAT_BBM level 2 also requires that the nT bit in block descriptors | ||
58 | must be ignored; since commit 39a1fd25287f5dece5 we do this. | ||
59 | |||
60 | It's therefore safe for QEMU to advertise FEAT_BBM level 2 by | ||
61 | setting ID_AA64MMFR2_EL1.BBM to 2. | ||
2 | 62 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 63 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 64 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20220404154658.565020-12-peter.maydell@linaro.org | 65 | Message-id: 20220426160422.2353158-3-peter.maydell@linaro.org |
6 | --- | 66 | --- |
7 | include/hw/arm/exynos4210.h | 4 ---- | 67 | docs/system/arm/emulation.rst | 1 + |
8 | 1 file changed, 4 deletions(-) | 68 | target/arm/cpu64.c | 1 + |
69 | 2 files changed, 2 insertions(+) | ||
9 | 70 | ||
10 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | 71 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
11 | index XXXXXXX..XXXXXXX 100644 | 72 | index XXXXXXX..XXXXXXX 100644 |
12 | --- a/include/hw/arm/exynos4210.h | 73 | --- a/docs/system/arm/emulation.rst |
13 | +++ b/include/hw/arm/exynos4210.h | 74 | +++ b/docs/system/arm/emulation.rst |
14 | @@ -XXX,XX +XXX,XX @@ | 75 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
15 | #define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \ | 76 | - FEAT_AA32HPD (AArch32 hierarchical permission disables) |
16 | (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8) | 77 | - FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions) |
17 | 78 | - FEAT_AES (AESD and AESE instructions) | |
18 | -/* IRQs number for external and internal GIC */ | 79 | +- FEAT_BBM at level 2 (Translation table break-before-make levels) |
19 | -#define EXYNOS4210_EXT_GIC_NIRQ (160-32) | 80 | - FEAT_BF16 (AArch64 BFloat16 instructions) |
20 | -#define EXYNOS4210_INT_GIC_NIRQ 64 | 81 | - FEAT_BTI (Branch Target Identification) |
21 | - | 82 | - FEAT_DIT (Data Independent Timing instructions) |
22 | #define EXYNOS4210_I2C_NUMBER 9 | 83 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
23 | 84 | index XXXXXXX..XXXXXXX 100644 | |
24 | #define EXYNOS4210_NUM_DMA 3 | 85 | --- a/target/arm/cpu64.c |
86 | +++ b/target/arm/cpu64.c | ||
87 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
88 | t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ | ||
89 | t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ | ||
90 | t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ | ||
91 | + t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ | ||
92 | cpu->isar.id_aa64mmfr2 = t; | ||
93 | |||
94 | t = cpu->isar.id_aa64zfr0; | ||
25 | -- | 95 | -- |
26 | 2.25.1 | 96 | 2.25.1 | diff view generated by jsdifflib |
1 | The only time we use the int_gic_irq[] array in the Exynos4210Irq | 1 | The Arm SMMUv3 includes an optional feature equivalent to the CPU |
---|---|---|---|
2 | struct is in the exynos4210_realize() function: we initialize it with | 2 | FEAT_BBM, which permits an OS to switch a range of memory between |
3 | the GPIO inputs of the a9mpcore device, and then a bit later on we | 3 | "covered by a huge page" and "covered by a sequence of normal pages" |
4 | connect those to the outputs of the internal combiner. Now that the | 4 | without having to engage in the traditional 'break-before-make' |
5 | a9mpcore object is easily accessible as s->a9mpcore we can make the | 5 | dance. (This is particularly important for the SMMU, because devices |
6 | connection directly from one device to the other without going via | 6 | performing I/O through an SMMU are less likely to be able to cope with |
7 | this array. | 7 | the window in the sequence where an access results in a translation |
8 | fault.) The SMMU spec explicitly notes that one of the valid ways to | ||
9 | be a BBM level 2 compliant implementation is: | ||
10 | * if there are multiple entries in the TLB for an address, | ||
11 | choose one of them and use it, ignoring the others | ||
12 | |||
13 | Our SMMU TLB implementation (unlike our CPU TLB) does allow multiple | ||
14 | TLB entries for an address, because the translation table level is | ||
15 | part of the SMMUIOTLBKey, and so our IOTLB hashtable can include | ||
16 | entries for the same address where the leaf was at different levels | ||
17 | (i.e. both hugepage and normal page). Our TLB lookup implementation in | ||
18 | smmu_iotlb_lookup() will always find the entry with the lowest level | ||
19 | (i.e. it prefers the hugepage over the normal page) and ignore any | ||
20 | others. TLB invalidation correctly removes all TLB entries matching | ||
21 | the specified address or address range (unless the guest specifies the | ||
22 | leaf level explicitly, in which case it gets what it asked for). So we | ||
23 | can validly advertise support for BBML level 2. | ||
24 | |||
25 | Note that we still can't yet advertise ourselves as an SMMU v3.2, | ||
26 | because v3.2 requires support for the S2FWB feature, which we don't | ||
27 | yet implement. | ||
8 | 28 | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 29 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 30 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
11 | Message-id: 20220404154658.565020-5-peter.maydell@linaro.org | 31 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
32 | Message-id: 20220426160422.2353158-4-peter.maydell@linaro.org | ||
12 | --- | 33 | --- |
13 | include/hw/arm/exynos4210.h | 1 - | 34 | hw/arm/smmuv3-internal.h | 1 + |
14 | hw/arm/exynos4210.c | 6 ++---- | 35 | hw/arm/smmuv3.c | 1 + |
15 | 2 files changed, 2 insertions(+), 5 deletions(-) | 36 | 2 files changed, 2 insertions(+) |
16 | 37 | ||
17 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | 38 | diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h |
18 | index XXXXXXX..XXXXXXX 100644 | 39 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/include/hw/arm/exynos4210.h | 40 | --- a/hw/arm/smmuv3-internal.h |
20 | +++ b/include/hw/arm/exynos4210.h | 41 | +++ b/hw/arm/smmuv3-internal.h |
21 | @@ -XXX,XX +XXX,XX @@ | 42 | @@ -XXX,XX +XXX,XX @@ REG32(IDR2, 0x8) |
22 | typedef struct Exynos4210Irq { | 43 | REG32(IDR3, 0xc) |
23 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | 44 | FIELD(IDR3, HAD, 2, 1); |
24 | qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; | 45 | FIELD(IDR3, RIL, 10, 1); |
25 | - qemu_irq int_gic_irq[EXYNOS4210_INT_GIC_NIRQ]; | 46 | + FIELD(IDR3, BBML, 11, 2); |
26 | qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ]; | 47 | REG32(IDR4, 0x10) |
27 | qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | 48 | REG32(IDR5, 0x14) |
28 | } Exynos4210Irq; | 49 | FIELD(IDR5, OAS, 0, 3); |
29 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | 50 | diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c |
30 | index XXXXXXX..XXXXXXX 100644 | 51 | index XXXXXXX..XXXXXXX 100644 |
31 | --- a/hw/arm/exynos4210.c | 52 | --- a/hw/arm/smmuv3.c |
32 | +++ b/hw/arm/exynos4210.c | 53 | +++ b/hw/arm/smmuv3.c |
33 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | 54 | @@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s) |
34 | sysbus_connect_irq(busdev, n, | 55 | |
35 | qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0)); | 56 | s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1); |
36 | } | 57 | s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1); |
37 | - for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { | 58 | + s->idr[3] = FIELD_DP32(s->idr[3], IDR3, BBML, 2); |
38 | - s->irqs.int_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->a9mpcore), n); | 59 | |
39 | - } | 60 | /* 4K, 16K and 64K granule support */ |
40 | 61 | s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1); | |
41 | /* Cache controller */ | ||
42 | sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); | ||
43 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
44 | busdev = SYS_BUS_DEVICE(dev); | ||
45 | sysbus_realize_and_unref(busdev, &error_fatal); | ||
46 | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { | ||
47 | - sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]); | ||
48 | + sysbus_connect_irq(busdev, n, | ||
49 | + qdev_get_gpio_in(DEVICE(&s->a9mpcore), n)); | ||
50 | } | ||
51 | exynos4210_combiner_get_gpioin(&s->irqs, dev, 0); | ||
52 | sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); | ||
53 | -- | 62 | -- |
54 | 2.25.1 | 63 | 2.25.1 | diff view generated by jsdifflib |