target/riscv/cpu.c | 9 +++++++++ target/riscv/cpu.h | 4 ++++ target/riscv/csr.c | 38 ++++++++++++++++++++++++++++++++++---- 3 files changed, 47 insertions(+), 4 deletions(-)
From: Frank Chang <frank.chang@sifive.com>
Allow user to set core's marchid, mvendorid, mipid CSRs through
-cpu command line option.
The default values of marchid and mipid are built with QEMU's version
numbers.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 9 +++++++++
target/riscv/cpu.h | 4 ++++
target/riscv/csr.c | 38 ++++++++++++++++++++++++++++++++++----
3 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ddda4906ff..84c3ff745a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -34,6 +34,11 @@
/* RISC-V CPU definitions */
+#define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \
+ (QEMU_VERSION_MINOR << 8) | \
+ (QEMU_VERSION_MICRO))
+#define RISCV_CPU_MIPID RISCV_CPU_MARCHID
+
static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
const char * const riscv_int_regnames[] = {
@@ -786,6 +791,10 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+ DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
+ DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
+ DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID),
+
DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c069fe85fa..3ab92deb4b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -370,6 +370,10 @@ struct RISCVCPUConfig {
bool ext_zve32f;
bool ext_zve64f;
+ uint32_t mvendorid;
+ uint64_t marchid;
+ uint64_t mipid;
+
/* Vendor-specific custom extensions */
bool ext_XVentanaCondOps;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 341c2e6f23..9a02038adb 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -603,6 +603,36 @@ static RISCVException write_ignore(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ CPUState *cs = env_cpu(env);
+ RISCVCPU *cpu = RISCV_CPU(cs);
+
+ *val = cpu->cfg.mvendorid;
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_marchid(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ CPUState *cs = env_cpu(env);
+ RISCVCPU *cpu = RISCV_CPU(cs);
+
+ *val = cpu->cfg.marchid;
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_mipid(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ CPUState *cs = env_cpu(env);
+ RISCVCPU *cpu = RISCV_CPU(cs);
+
+ *val = cpu->cfg.mipid;
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mhartid(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -3098,10 +3128,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
/* Machine Information Registers */
- [CSR_MVENDORID] = { "mvendorid", any, read_zero },
- [CSR_MARCHID] = { "marchid", any, read_zero },
- [CSR_MIMPID] = { "mimpid", any, read_zero },
- [CSR_MHARTID] = { "mhartid", any, read_mhartid },
+ [CSR_MVENDORID] = { "mvendorid", any, read_mvendorid },
+ [CSR_MARCHID] = { "marchid", any, read_marchid },
+ [CSR_MIMPID] = { "mimpid", any, read_mipid },
+ [CSR_MHARTID] = { "mhartid", any, read_mhartid },
/* Machine Trap Setup */
[CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus, NULL,
--
2.35.1On Wed, Apr 20, 2022 at 5:57 PM <frank.chang@sifive.com> wrote: > > From: Frank Chang <frank.chang@sifive.com> > > Allow user to set core's marchid, mvendorid, mipid CSRs through > -cpu command line option. > > The default values of marchid and mipid are built with QEMU's version > numbers. > > Signed-off-by: Frank Chang <frank.chang@sifive.com> > Reviewed-by: Jim Shu <jim.shu@sifive.com> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/cpu.c | 9 +++++++++ > target/riscv/cpu.h | 4 ++++ > target/riscv/csr.c | 38 ++++++++++++++++++++++++++++++++++---- > 3 files changed, 47 insertions(+), 4 deletions(-) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
On Thu, Apr 21, 2022 at 12:17 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > On Wed, Apr 20, 2022 at 5:57 PM <frank.chang@sifive.com> wrote: > > > > From: Frank Chang <frank.chang@sifive.com> > > > > Allow user to set core's marchid, mvendorid, mipid CSRs through > > -cpu command line option. > > > > The default values of marchid and mipid are built with QEMU's version > > numbers. > > > > Signed-off-by: Frank Chang <frank.chang@sifive.com> > > Reviewed-by: Jim Shu <jim.shu@sifive.com> > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > --- > > target/riscv/cpu.c | 9 +++++++++ > > target/riscv/cpu.h | 4 ++++ > > target/riscv/csr.c | 38 ++++++++++++++++++++++++++++++++++---- > > 3 files changed, 47 insertions(+), 4 deletions(-) > > > > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Do you mind rebasing this on https://github.com/alistair23/qemu/tree/riscv-to-apply.next ? I have sent a PR and hopefully it should be merged into master soon Alistair >
On Fri, Apr 22, 2022 at 8:48 AM Alistair Francis <alistair23@gmail.com> wrote: > On Thu, Apr 21, 2022 at 12:17 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > On Wed, Apr 20, 2022 at 5:57 PM <frank.chang@sifive.com> wrote: > > > > > > From: Frank Chang <frank.chang@sifive.com> > > > > > > Allow user to set core's marchid, mvendorid, mipid CSRs through > > > -cpu command line option. > > > > > > The default values of marchid and mipid are built with QEMU's version > > > numbers. > > > > > > Signed-off-by: Frank Chang <frank.chang@sifive.com> > > > Reviewed-by: Jim Shu <jim.shu@sifive.com> > > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > > --- > > > target/riscv/cpu.c | 9 +++++++++ > > > target/riscv/cpu.h | 4 ++++ > > > target/riscv/csr.c | 38 ++++++++++++++++++++++++++++++++++---- > > > 3 files changed, 47 insertions(+), 4 deletions(-) > > > > > > > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > > Do you mind rebasing this on > https://github.com/alistair23/qemu/tree/riscv-to-apply.next ? > Sure, will do. Regards, Frank Chang > > I have sent a PR and hopefully it should be merged into master soon > > Alistair > > > >
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