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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d21-20020a056a0010d500b004fd9ee64134sm20015057pfu.74.2022.04.20.02.57.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Apr 2022 02:57:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=lTprkEYlA1e+6K8+Mv+GxHs6vsO79SS53vFjjDAuPuE=; b=mVXLmFmuSfeN/mSxvwjKV7L+Wx5D3GexCGc/2mLRfEafjljECbxlU6cBaFy2RGMWaQ VyzS3dCTcYgx4EDiYa+yOiS+7AgeKJrIlnONyD1eH0YrL68L1gEJAfVfYSQciqkNBrgN 4RdrxaAw2i5Ymyl3UtCyv7BKLkUK3XxExzowQhqBRY5ZCNFmpucQmibYT2JBbLLeBklD N+J3TQKjXusGxdr2SKxflrx/SSipnlkcoOj5P6jpqTtA+wKODnRrBlmxeq2V5EUWLDM7 xE4jnHafFdS3Euc3UtFBTPhM+kjb7o4gfNP9xNtASNjHKzp9DvHbICB9/bRXCKvcG4FX mKlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=lTprkEYlA1e+6K8+Mv+GxHs6vsO79SS53vFjjDAuPuE=; b=iH/vMLLLIwDACJVbbCxlO93g0TKDHI2PAerCWpWX3tp1JfRvltJ8N6bYHgqyakLPNa esbKrnFDpcQrIOK14uQ/fGoPjzG4JfLX35+2TM0gnjsFYQ6PbJrPOp2k9lkUd3xRFrp3 8kVhdtoJoSkgP8sHZ4phVZoy8zWtEt/caTJLHzOJHenAxBCSJuzWWclvPvEM7ZG+zHig SdaTeA0ivBg5lCPa6brxmGobMmGpd9tyGKR5+u6unH0tjuFJPIsmE1J9DigILjmx1cYP shxvjFsI+9tAY371KJGaaHcBe/dDVFFD65fxYKQFBLjuQ0CKIWXq0xHl/llohM90u0tQ ShiA== X-Gm-Message-State: AOAM531qmY0lkOG72OS0U6NdwtqaKNNCMjPadXM2pYMhtQvebZ7zZr8k ll/43HB+1xIBM4JlVywpUC8Q7n9JUIDDSsH/ X-Google-Smtp-Source: ABdhPJwJfw8A01G4z8b7NsWkdYg5huBBDevY2PeXw1KiAR/A/ZxlLu2PwD7m+KjPH4GC/ULrJv7tVw== X-Received: by 2002:a17:903:120b:b0:154:c9f2:207b with SMTP id l11-20020a170903120b00b00154c9f2207bmr19888615plh.153.1650448642763; Wed, 20 Apr 2022 02:57:22 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Subject: [PATCH v2] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values Date: Wed, 20 Apr 2022 17:57:17 +0800 Message-Id: <20220420095718.26392-1-frank.chang@sifive.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Frank Chang , Bin Meng , Jim Shu , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1650448785883100001 Content-Type: text/plain; charset="utf-8" From: Frank Chang Allow user to set core's marchid, mvendorid, mipid CSRs through -cpu command line option. The default values of marchid and mipid are built with QEMU's version numbers. Signed-off-by: Frank Chang Reviewed-by: Jim Shu Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.c | 9 +++++++++ target/riscv/cpu.h | 4 ++++ target/riscv/csr.c | 38 ++++++++++++++++++++++++++++++++++---- 3 files changed, 47 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ddda4906ff..84c3ff745a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -34,6 +34,11 @@ =20 /* RISC-V CPU definitions */ =20 +#define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ + (QEMU_VERSION_MINOR << 8) | \ + (QEMU_VERSION_MICRO)) +#define RISCV_CPU_MIPID RISCV_CPU_MARCHID + static const char riscv_exts[26] =3D "IEMAFDQCLBJTPVNSUHKORWXYZG"; =20 const char * const riscv_int_regnames[] =3D { @@ -786,6 +791,10 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), =20 + DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), + DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID= ), + DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID), + DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c069fe85fa..3ab92deb4b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -370,6 +370,10 @@ struct RISCVCPUConfig { bool ext_zve32f; bool ext_zve64f; =20 + uint32_t mvendorid; + uint64_t marchid; + uint64_t mipid; + /* Vendor-specific custom extensions */ bool ext_XVentanaCondOps; =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 341c2e6f23..9a02038adb 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -603,6 +603,36 @@ static RISCVException write_ignore(CPURISCVState *env,= int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException read_mvendorid(CPURISCVState *env, int csrno, + target_ulong *val) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + *val =3D cpu->cfg.mvendorid; + return RISCV_EXCP_NONE; +} + +static RISCVException read_marchid(CPURISCVState *env, int csrno, + target_ulong *val) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + *val =3D cpu->cfg.marchid; + return RISCV_EXCP_NONE; +} + +static RISCVException read_mipid(CPURISCVState *env, int csrno, + target_ulong *val) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + *val =3D cpu->cfg.mipid; + return RISCV_EXCP_NONE; +} + static RISCVException read_mhartid(CPURISCVState *env, int csrno, target_ulong *val) { @@ -3098,10 +3128,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MINSTRETH] =3D { "minstreth", any32, read_instreth }, =20 /* Machine Information Registers */ - [CSR_MVENDORID] =3D { "mvendorid", any, read_zero }, - [CSR_MARCHID] =3D { "marchid", any, read_zero }, - [CSR_MIMPID] =3D { "mimpid", any, read_zero }, - [CSR_MHARTID] =3D { "mhartid", any, read_mhartid }, + [CSR_MVENDORID] =3D { "mvendorid", any, read_mvendorid }, + [CSR_MARCHID] =3D { "marchid", any, read_marchid }, + [CSR_MIMPID] =3D { "mimpid", any, read_mipid }, + [CSR_MHARTID] =3D { "mhartid", any, read_mhartid }, =20 /* Machine Trap Setup */ [CSR_MSTATUS] =3D { "mstatus", any, read_mstatus, write_m= status, NULL, --=20 2.35.1