Mostly straightforward bugfixes. The new Xilinx devices are

arguably 'new feature', but they're fixing a regression where

our changes to PSCI in commit 3f37979bf mean that EL3 guest

code now needs to talk to a proper emulated power-controller

device to turn on secondary CPUs; and it's not yet rc1 and

they only affect the Xilinx board, so it seems OK to me.

The following changes since commit 1d60bb4b14601e38ed17384277aa4c30c57925d3:

Merge tag 'pull-request-2022-03-15v2' of https://gitlab.com/thuth/qemu into staging (2022-03-16 10:43:58 +0000)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220318

for you to fetch changes up to 79d54c9eac04c554e3c081589542f801ace71797:

util/osdep: Remove some early cruft (2022-03-18 11:32:13 +0000)

* Fix sve2 ldnt1 and stnt1

* Fix pauth_check_trap vs SEL2

* Fix handling of LPAE block descriptors

* hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size

* hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init()

* nsis installer: List emulators in alphabetical order

* nsis installer: Suppress "ANSI targets are deprecated" warning

* nsis installer: Fix mouse-over descriptions for emulators

* hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset

* Improve M-profile vector table access logging

* Xilinx ZynqMP: model CRF and APU control

* Fix compile issues on modern Solaris

Andrew Deason (3):

util/osdep: Avoid madvise proto on modern Solaris

hw/i386/acpi-build: Avoid 'sun' identifier

util/osdep: Remove some early cruft

Edgar E. Iglesias (6):

hw/arm/xlnx-zynqmp: Add an unimplemented SERDES area

target/arm: Make rvbar settable after realize

hw/misc: Add a model of the Xilinx ZynqMP CRF

hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF

hw/misc: Add a model of the Xilinx ZynqMP APU Control

hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control

Eric Auger (2):

hw/intc: Rename CONFIG_ARM_GIC_TCG into CONFIG_ARM_GICV3_TCG

hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset

target/arm: Fix handling of LPAE block descriptors

hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size

hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init()

nsis installer: List emulators in alphabetical order

nsis installer: Suppress "ANSI targets are deprecated" warning

nsis installer: Fix mouse-over descriptions for emulators

target/arm: Log M-profile vector table accesses

target/arm: Log fault address for M-profile faults

Richard Henderson (2):

target/arm: Fix sve2 ldnt1 and stnt1

target/arm: Fix pauth_check_trap vs SEL2

meson.build | 23 ++-

include/hw/arm/xlnx-zynqmp.h | 4 +

include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 93 ++++++++++++

include/hw/misc/xlnx-zynqmp-crf.h | 211 ++++++++++++++++++++++++++

include/qemu/osdep.h | 8 +

target/arm/cpu.h | 3 +-

target/arm/sve.decode | 5 +-

hw/arm/virt.c | 7 +-

hw/arm/xlnx-zynqmp.c | 46 +++++-

hw/dma/xlnx_csu_dma.c | 1 +

hw/i386/acpi-build.c | 4 +-

hw/misc/npcm7xx_clk.c | 4 +-

hw/misc/xlnx-zynqmp-apu-ctrl.c | 253 +++++++++++++++++++++++++++++++

hw/misc/xlnx-zynqmp-crf.c | 266 +++++++++++++++++++++++++++++++++

target/arm/cpu.c | 17 ++-

target/arm/helper.c | 20 ++-

target/arm/m_helper.c | 11 ++

target/arm/pauth_helper.c | 2 +-

target/arm/translate-sve.c | 51 ++++++-

tests/tcg/aarch64/test-826.c | 50 +++++++

util/osdep.c | 10 --

hw/intc/Kconfig | 2 +-

hw/intc/meson.build | 4 +-

hw/misc/meson.build | 2 +

qemu.nsi | 8 +-

scripts/nsis.py | 17 ++-

tests/tcg/aarch64/Makefile.target | 4 +

tests/tcg/configure.sh | 4 +

28 files changed, 1084 insertions(+), 46 deletions(-)

create mode 100644 include/hw/misc/xlnx-zynqmp-apu-ctrl.h

create mode 100644 include/hw/misc/xlnx-zynqmp-crf.h

create mode 100644 hw/misc/xlnx-zynqmp-apu-ctrl.c

create mode 100644 hw/misc/xlnx-zynqmp-crf.c

create mode 100644 tests/tcg/aarch64/test-826.c

In commit 00f05c02f9e7342f we gave the TYPE_XLNX_CSU_DMA object its

own class struct, but forgot to update the TypeInfo::class_size

accordingly. This meant that not enough memory was allocated for the

class struct, and the initialization of xcdc->read in the class init

function wrote off the end of the memory. Add the missing line.

Found by running 'check-qtest-aarch64' with a clang

address-sanitizer build, which complains:

==2542634==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x61000000ab00 at pc 0x559a20aebc29 bp 0x7fff97df74d0 sp 0x7fff97df74c8

WRITE of size 8 at 0x61000000ab00 thread T0

#0 0x559a20aebc28 in xlnx_csu_dma_class_init /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../hw/dma/xlnx_csu_dma.c:722:16

#1 0x559a21bf297c in type_initialize /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:365:9

#2 0x559a21bf3442 in object_class_foreach_tramp /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1070:5

#3 0x7f09bcb641b7 in g_hash_table_foreach (/usr/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x401b7)

#4 0x559a21bf3c27 in object_class_foreach /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1092:5

#5 0x559a21bf3c27 in object_class_get_list /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1149:5

#6 0x559a2081a2fd in select_machine /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../softmmu/vl.c:1661:24

#7 0x559a2081a2fd in qemu_create_machine /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../softmmu/vl.c:2146:35

#8 0x559a2081a2fd in qemu_init /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../softmmu/vl.c:3706:5

#9 0x559a20720ed5 in main /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../softmmu/main.c:49:5

#10 0x7f09baec00b2 in __libc_start_main /build/glibc-sMfBJT/glibc-2.31/csu/../csu/libc-start.c:308:16

#11 0x559a2067673d in _start (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/qemu-system-aarch64+0xf4b73d)

0x61000000ab00 is located 0 bytes to the right of 192-byte region [0x61000000aa40,0x61000000ab00)

allocated by thread T0 here:

#0 0x559a206eeff2 in calloc (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/qemu-system-aarch64+0xfc3ff2)

#1 0x7f09bcb7bef0 in g_malloc0 (/usr/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x57ef0)

#2 0x559a21bf3442 in object_class_foreach_tramp /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1070:5

Fixes: 00f05c02f9e7342f ("hw/dma/xlnx_csu_dma: Support starting a read transfer through a class method")

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Message-id: 20220308150207.2546272-1-peter.maydell@linaro.org

---

hw/dma/xlnx_csu_dma.c | 1 +

1 file changed, 1 insertion(+)

diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c

--- a/hw/dma/xlnx_csu_dma.c

+++ b/hw/dma/xlnx_csu_dma.c

@@ -XXX,XX +XXX,XX @@ static const TypeInfo xlnx_csu_dma_info = {

.parent = TYPE_SYS_BUS_DEVICE,

.instance_size = sizeof(XlnxCSUDMA),

.class_init = xlnx_csu_dma_class_init,

+ .class_size = sizeof(XlnxCSUDMAClass),

.instance_init = xlnx_csu_dma_init,

.interfaces = (InterfaceInfo[]) {

{ TYPE_STREAM_SINK },

2.25.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Make the rvbar property settable after realize. This is done

in preparation to model the ZynqMP's runtime configurable rvbar.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Message-id: 20220316164645.2303510-3-edgar.iglesias@gmail.com

target/arm/cpu.h | 3 ++-

target/arm/cpu.c | 12 +++++++-----

target/arm/helper.c | 10 +++++++---

3 files changed, 16 insertions(+), 9 deletions(-)

uint32_t dcz_blocksize;

- uint64_t rvbar;

+ uint64_t rvbar_prop; /* Property/input signals. */

/* Configurable aspects of GIC cpu interface (which is part of the CPU) */

int gic_num_lrs; /* number of list registers */

diff --git a/target/arm/cpu.c b/target/arm/cpu.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.c

+++ b/target/arm/cpu.c

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)

} else {

env->pstate = PSTATE_MODE_EL1h;

}

- env->pc = cpu->rvbar;

+

+ /* Sample rvbar at reset. */

+ env->cp15.rvbar = cpu->rvbar_prop;

+ env->pc = env->cp15.rvbar;

#endif

} else {

#if defined(CONFIG_USER_ONLY)

@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_reset_cbar_property =

static Property arm_cpu_reset_hivecs_property =

DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);

-static Property arm_cpu_rvbar_property =

- DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);

#ifndef CONFIG_USER_ONLY

static Property arm_cpu_has_el2_property =

DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);

@@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj)

}

if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {

- qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property);

+ object_property_add_uint64_ptr(obj, "rvbar",

+ &cpu->rvbar_prop,

+ OBJ_PROP_FLAG_READWRITE);

}

#ifndef CONFIG_USER_ONLY

ARMCPRegInfo rvbar = {

.name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,

.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,

- .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar

+ .access = PL1_R,

+ .fieldoffset = offsetof(CPUARMState, cp15.rvbar),

};

define_one_arm_cp_reg(cpu, &rvbar);

}

@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)

ARMCPRegInfo rvbar = {

.name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,

.opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,

- .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar

+ .access = PL2_R,

+ .fieldoffset = offsetof(CPUARMState, cp15.rvbar),

};

define_one_arm_cp_reg(cpu, &rvbar);

}

@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)

ARMCPRegInfo el3_regs[] = {

{ .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,

.opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,

- .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar },

+ .access = PL3_R,

+ .fieldoffset = offsetof(CPUARMState, cp15.rvbar),

+ },

{ .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,

.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,

.access = PL3_RW,

2.25.1

For both ldnt1 and stnt1, the meaning of the Rn and Rm are different

from ld1 and st1: the vector and integer registers are reversed, and

the integer register 31 refers to XZR instead of SP.

Message-id: 20220308031655.240710-1-richard.henderson@linaro.org

target/arm/sve.decode | 5 ++-

target/arm/translate-sve.c | 51 +++++++++++++++++++++++++++++--

tests/tcg/aarch64/test-826.c | 50 ++++++++++++++++++++++++++++++

tests/tcg/aarch64/Makefile.target | 4 +++

tests/tcg/configure.sh | 4 +++

5 files changed, 109 insertions(+), 5 deletions(-)

create mode 100644 tests/tcg/aarch64/test-826.c

diff --git a/target/arm/sve.decode b/target/arm/sve.decode

--- a/target/arm/sve.decode

+++ b/target/arm/sve.decode

@@ -XXX,XX +XXX,XX @@ USDOT_zzzz 01000100 .. 0 ..... 011 110 ..... ..... @rda_rn_rm

### SVE2 Memory Gather Load Group

-# SVE2 64-bit gather non-temporal load

-# (scalar plus unpacked 32-bit unscaled offsets)

+# SVE2 64-bit gather non-temporal load (scalar plus 64-bit unscaled offsets)

LDNT1_zprz 1100010 msz:2 00 rm:5 1 u:1 0 pg:3 rn:5 rd:5 \

- &rprr_gather_load xs=0 esz=3 scale=0 ff=0

+ &rprr_gather_load xs=2 esz=3 scale=0 ff=0

# SVE2 32-bit gather non-temporal load (scalar plus 32-bit unscaled offsets)

LDNT1_zprz 1000010 msz:2 00 rm:5 10 u:1 pg:3 rn:5 rd:5 \

diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-sve.c

+++ b/target/arm/translate-sve.c

@@ -XXX,XX +XXX,XX @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a)

static bool trans_LDNT1_zprz(DisasContext *s, arg_LD1_zprz *a)

{

+ gen_helper_gvec_mem_scatter *fn = NULL;

+ bool be = s->be_data == MO_BE;

+ bool mte = s->mte_active[0];

+ if (a->esz < a->msz + !a->u) {

+ return false;

+ }

if (!dc_isar_feature(aa64_sve2, s)) {

return false;

}

- return trans_LD1_zprz(s, a);

+ if (!sve_access_check(s)) {

+ return true;

+ }

+ switch (a->esz) {

+ case MO_32:

+ fn = gather_load_fn32[mte][be][0][0][a->u][a->msz];

+ break;

+ case MO_64:

+ fn = gather_load_fn64[mte][be][0][2][a->u][a->msz];

+ break;

+ }

+ assert(fn != NULL);

+ do_mem_zpz(s, a->rd, a->pg, a->rn, 0,

+ cpu_reg(s, a->rm), a->msz, false, fn);

+ return true;

}

/* Indexed by [mte][be][xs][msz]. */

@@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a)

static bool trans_STNT1_zprz(DisasContext *s, arg_ST1_zprz *a)

{

+ gen_helper_gvec_mem_scatter *fn;

+ bool be = s->be_data == MO_BE;

+ bool mte = s->mte_active[0];

+

+ if (a->esz < a->msz) {

+ return false;

+ }

if (!dc_isar_feature(aa64_sve2, s)) {

return false;

}

- return trans_ST1_zprz(s, a);

+ if (!sve_access_check(s)) {

+ return true;

+ }

+

+ switch (a->esz) {

+ case MO_32:

+ fn = scatter_store_fn32[mte][be][0][a->msz];

+ break;

+ case MO_64:

+ fn = scatter_store_fn64[mte][be][2][a->msz];

+ break;

+ default:

+ g_assert_not_reached();

+ }

+

+ do_mem_zpz(s, a->rd, a->pg, a->rn, 0,

+ cpu_reg(s, a->rm), a->msz, true, fn);

+ return true;

}

/*

diff --git a/tests/tcg/aarch64/test-826.c b/tests/tcg/aarch64/test-826.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/tests/tcg/aarch64/test-826.c

@@ -XXX,XX +XXX,XX @@

+#include <sys/mman.h>

+#include <unistd.h>

+#include <signal.h>

+#include <stdlib.h>

+#include <stdio.h>

+#include <assert.h>

+

+static void *expected;

+

+void sigsegv(int sig, siginfo_t *info, void *vuc)

+{

+ ucontext_t *uc = vuc;

+

+ assert(info->si_addr == expected);

+ uc->uc_mcontext.pc += 4;

+int main()

+{

+ struct sigaction sa = {

+ .sa_sigaction = sigsegv,

+ .sa_flags = SA_SIGINFO

+ };

+

+ void *page;

+ long ofs;

+

+ if (sigaction(SIGSEGV, &sa, NULL) < 0) {

+ perror("sigaction");

+ return EXIT_FAILURE;

+ }

+

+ page = mmap(0, getpagesize(), PROT_NONE, MAP_PRIVATE | MAP_ANON, -1, 0);

+ if (page == MAP_FAILED) {

+ perror("mmap");

+ return EXIT_FAILURE;

+ }

+

+ ofs = 0x124;

+ expected = page + ofs;

+

+ asm("ptrue p0.d, vl1\n\t"

+ "dup z0.d, %0\n\t"

+ "ldnt1h {z1.d}, p0/z, [z0.d, %1]\n\t"

+ "dup z1.d, %1\n\t"

+ "ldnt1h {z0.d}, p0/z, [z1.d, %0]"

+ : : "r"(page), "r"(ofs) : "v0", "v1");

+

+ return EXIT_SUCCESS;

+}

diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target

index XXXXXXX..XXXXXXX 100644

--- a/tests/tcg/aarch64/Makefile.target

+++ b/tests/tcg/aarch64/Makefile.target

@@ -XXX,XX +XXX,XX @@ run-gdbstub-sve-ioctls: sve-ioctls

EXTRA_RUNS += run-gdbstub-sysregs run-gdbstub-sve-ioctls

endif

+endif

+ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_SVE2),)

+AARCH64_TESTS += test-826

+test-826: CFLAGS+=-march=armv8.1-a+sve2

endif

TESTS += $(AARCH64_TESTS)

diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh

index XXXXXXX..XXXXXXX 100755

--- a/tests/tcg/configure.sh

+++ b/tests/tcg/configure.sh

@@ -XXX,XX +XXX,XX @@ for target in $target_list; do

-march=armv8.1-a+sve -o $TMPE $TMPC; then

echo "CROSS_CC_HAS_SVE=y" >> $config_target_mak

fi

+ if do_compiler "$target_compiler" $target_compiler_cflags \

+ -march=armv8.1-a+sve2 -o $TMPE $TMPC; then

+ echo "CROSS_CC_HAS_SVE2=y" >> $config_target_mak

+ fi

if do_compiler "$target_compiler" $target_compiler_cflags \

-march=armv8.3-a -o $TMPE $TMPC; then

echo "CROSS_CC_HAS_ARMV8_3=y" >> $config_target_mak

2.25.1

LPAE descriptors come in three forms:

* table descriptors, giving the address of the next level page table

* page descriptors, which occur only at level 3 and describe the

mapping of one page (which might be 4K, 16K or 64K)

* block descriptors, which occur at higher page table levels, and

describe the mapping of huge pages

QEMU's page-table-walk code treats block and page entries

identically, simply ORing in a number of bits from the input virtual

address that depends on the level of the page table that we stopped

at; we depend on the previous masking of descaddr with descaddrmask

to have already cleared out the low bits of the descriptor word.

This is not quite right: the address field in a block descriptor is

smaller, and so there are bits which are valid address bits in a page

descriptor or a table descriptor but which are not supposed to be

part of the address in a block descriptor, and descaddrmask does not

clear them. We previously mostly got away with this because those

descriptor bits are RES0; however with FEAT_BBM (part of Armv8.4)

block descriptor bit 16 is defined to be the nT bit. No emulated

QEMU CPU has FEAT_BBM yet, but if the host CPU has it then we might

see it when using KVM or hvf.

Explicitly zero out all the descaddr bits we're about to OR vaddr

bits into.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/790

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20220304165628.2345765-1-peter.maydell@linaro.org

---

target/arm/helper.c | 10 ++++++++--

1 file changed, 8 insertions(+), 2 deletions(-)

@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,

indexmask = indexmask_grainsize;

continue;

}

- /* Block entry at level 1 or 2, or page entry at level 3.

+ /*

+ * Block entry at level 1 or 2, or page entry at level 3.

* These are basically the same thing, although the number

- * of bits we pull in from the vaddr varies.

+ * of bits we pull in from the vaddr varies. Note that although

+ * descaddrmask masks enough of the low bits of the descriptor

+ * to give a correct page or table address, the address field

+ * in a block descriptor is smaller; so we need to explicitly

+ * clear the lower bits here before ORing in the low vaddr bits.

*/

page_size = (1ULL << ((stride * (4 - level)) + 3));

+ descaddr &= ~(page_size - 1);

descaddr |= (address & (page_size - 1));

/* Extract attributes from the descriptor */

attrs = extract64(descriptor, 2, 10)

2.25.1

From: Andrew Deason <adeason@sinenomine.net>

The include for statvfs.h has not been needed since all statvfs calls

were removed in commit 4a1418e07bdc ("Unbreak large mem support by

removing kqemu").

The comment mentioning CONFIG_BSD hasn't made sense since an include

for config-host.h was removed in commit aafd75841001 ("util: Clean up

includes").

Remove this cruft.

Signed-off-by: Andrew Deason <adeason@sinenomine.net>

Message-id: 20220316035227.3702-4-adeason@sinenomine.net

util/osdep.c | 7 -------

1 file changed, 7 deletions(-)

diff --git a/util/osdep.c b/util/osdep.c

--- a/util/osdep.c

+++ b/util/osdep.c

@@ -XXX,XX +XXX,XX @@

*/

#include "qemu/osdep.h"

#include "qapi/error.h"

-

-/* Needed early for CONFIG_BSD etc. */

-

-#ifdef CONFIG_SOLARIS

-#include <sys/statvfs.h>

-#endif

-

#include "qemu-common.h"

#include "qemu/cutils.h"

#include "qemu/sockets.h"

2.25.1

From: Andrew Deason <adeason@sinenomine.net>

On Solaris, 'sun' is #define'd to 1, which causes errors if a variable

is named 'sun'. Slightly change the name of the var for the Slot User

Number so we can build on Solaris.

Reviewed-by: Ani Sinha <ani@anisinha.ca>

Signed-off-by: Andrew Deason <adeason@sinenomine.net>

Reviewed-by: Michael S. Tsirkin <mst@redhat.com>

Message-id: 20220316035227.3702-3-adeason@sinenomine.net

hw/i386/acpi-build.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c

--- a/hw/i386/acpi-build.c

+++ b/hw/i386/acpi-build.c

@@ -XXX,XX +XXX,XX @@ Aml *aml_pci_device_dsm(void)

Aml *bnum = aml_arg(4);

Aml *func = aml_arg(2);

Aml *rev = aml_arg(1);

- Aml *sun = aml_arg(5);

+ Aml *sunum = aml_arg(5);

method = aml_method("PDSM", 6, AML_SERIALIZED);

@@ -XXX,XX +XXX,XX @@ Aml *aml_pci_device_dsm(void)

UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");

ifctx = aml_if(aml_equal(aml_arg(0), UUID));

{

- aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sun), acpi_index));

+ aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));

ifctx1 = aml_if(aml_equal(func, zero));

{

uint8_t byte_list[1];

2.25.1

When arm_is_el2_enabled was introduced, we missed

updating pauth_check_trap.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20220315021205.342768-1-richard.henderson@linaro.org

target/arm/pauth_helper.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c

--- a/target/arm/pauth_helper.c

+++ b/target/arm/pauth_helper.c

@@ -XXX,XX +XXX,XX @@ static void QEMU_NORETURN pauth_trap(CPUARMState *env, int target_el,

static void pauth_check_trap(CPUARMState *env, int el, uintptr_t ra)

{

- if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {

+ if (el < 2 && arm_is_el2_enabled(env)) {

uint64_t hcr = arm_hcr_el2_eff(env);

bool trap = !(hcr & HCR_API);

if (el == 0) {

2.25.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Add a model of the Xilinx ZynqMP CRF. At the moment this

is mostly a stub model.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Message-id: 20220316164645.2303510-4-edgar.iglesias@gmail.com

include/hw/misc/xlnx-zynqmp-crf.h | 211 ++++++++++++++++++++++++

hw/misc/xlnx-zynqmp-crf.c | 266 ++++++++++++++++++++++++++++++

hw/misc/meson.build | 1 +

3 files changed, 478 insertions(+)

create mode 100644 include/hw/misc/xlnx-zynqmp-crf.h

create mode 100644 hw/misc/xlnx-zynqmp-crf.c

diff --git a/include/hw/misc/xlnx-zynqmp-crf.h b/include/hw/misc/xlnx-zynqmp-crf.h

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/include/hw/misc/xlnx-zynqmp-crf.h

@@ -XXX,XX +XXX,XX @@

+/*

+ * QEMU model of the CRF - Clock Reset FPD.

+ *

+ * Copyright (c) 2022 Xilinx Inc.

+ * SPDX-License-Identifier: GPL-2.0-or-later

+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>

+ */

+#ifndef HW_MISC_XLNX_ZYNQMP_CRF_H

+#define HW_MISC_XLNX_ZYNQMP_CRF_H

+

+#include "hw/sysbus.h"

+#include "hw/register.h"

+

+#define TYPE_XLNX_ZYNQMP_CRF "xlnx.zynqmp_crf"

+OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPCRF, XLNX_ZYNQMP_CRF)

+

+REG32(ERR_CTRL, 0x0)

+ FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)

+REG32(IR_STATUS, 0x4)

+ FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)

+REG32(IR_MASK, 0x8)

+ FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)

+REG32(IR_ENABLE, 0xc)

+ FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)

+REG32(IR_DISABLE, 0x10)

+ FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)

+REG32(CRF_WPROT, 0x1c)

+ FIELD(CRF_WPROT, ACTIVE, 0, 1)

+REG32(APLL_CTRL, 0x20)

+ FIELD(APLL_CTRL, POST_SRC, 24, 3)

+ FIELD(APLL_CTRL, PRE_SRC, 20, 3)

+ FIELD(APLL_CTRL, CLKOUTDIV, 17, 1)

+ FIELD(APLL_CTRL, DIV2, 16, 1)

+ FIELD(APLL_CTRL, FBDIV, 8, 7)

+ FIELD(APLL_CTRL, BYPASS, 3, 1)

+ FIELD(APLL_CTRL, RESET, 0, 1)

+REG32(APLL_CFG, 0x24)

+ FIELD(APLL_CFG, LOCK_DLY, 25, 7)

+ FIELD(APLL_CFG, LOCK_CNT, 13, 10)

+ FIELD(APLL_CFG, LFHF, 10, 2)

+ FIELD(APLL_CFG, CP, 5, 4)

+ FIELD(APLL_CFG, RES, 0, 4)

+REG32(APLL_FRAC_CFG, 0x28)

+ FIELD(APLL_FRAC_CFG, ENABLED, 31, 1)

+ FIELD(APLL_FRAC_CFG, SEED, 22, 3)

+ FIELD(APLL_FRAC_CFG, ALGRTHM, 19, 1)

+ FIELD(APLL_FRAC_CFG, ORDER, 18, 1)

+ FIELD(APLL_FRAC_CFG, DATA, 0, 16)

+REG32(DPLL_CTRL, 0x2c)

+ FIELD(DPLL_CTRL, POST_SRC, 24, 3)

+ FIELD(DPLL_CTRL, PRE_SRC, 20, 3)

+ FIELD(DPLL_CTRL, CLKOUTDIV, 17, 1)

+ FIELD(DPLL_CTRL, DIV2, 16, 1)

+ FIELD(DPLL_CTRL, FBDIV, 8, 7)

+ FIELD(DPLL_CTRL, BYPASS, 3, 1)

+ FIELD(DPLL_CTRL, RESET, 0, 1)

+REG32(DPLL_CFG, 0x30)

+ FIELD(DPLL_CFG, LOCK_DLY, 25, 7)

+ FIELD(DPLL_CFG, LOCK_CNT, 13, 10)

+ FIELD(DPLL_CFG, LFHF, 10, 2)

+ FIELD(DPLL_CFG, CP, 5, 4)

+ FIELD(DPLL_CFG, RES, 0, 4)

+REG32(DPLL_FRAC_CFG, 0x34)

+ FIELD(DPLL_FRAC_CFG, ENABLED, 31, 1)

+ FIELD(DPLL_FRAC_CFG, SEED, 22, 3)

+ FIELD(DPLL_FRAC_CFG, ALGRTHM, 19, 1)

+ FIELD(DPLL_FRAC_CFG, ORDER, 18, 1)

+ FIELD(DPLL_FRAC_CFG, DATA, 0, 16)

+REG32(VPLL_CTRL, 0x38)

+ FIELD(VPLL_CTRL, POST_SRC, 24, 3)

+ FIELD(VPLL_CTRL, PRE_SRC, 20, 3)

+ FIELD(VPLL_CTRL, CLKOUTDIV, 17, 1)

+ FIELD(VPLL_CTRL, DIV2, 16, 1)

+ FIELD(VPLL_CTRL, FBDIV, 8, 7)

+ FIELD(VPLL_CTRL, BYPASS, 3, 1)

+ FIELD(VPLL_CTRL, RESET, 0, 1)

+REG32(VPLL_CFG, 0x3c)

+ FIELD(VPLL_CFG, LOCK_DLY, 25, 7)

+ FIELD(VPLL_CFG, LOCK_CNT, 13, 10)

+ FIELD(VPLL_CFG, LFHF, 10, 2)

+ FIELD(VPLL_CFG, CP, 5, 4)

+ FIELD(VPLL_CFG, RES, 0, 4)

+REG32(VPLL_FRAC_CFG, 0x40)

+ FIELD(VPLL_FRAC_CFG, ENABLED, 31, 1)

+ FIELD(VPLL_FRAC_CFG, SEED, 22, 3)

+ FIELD(VPLL_FRAC_CFG, ALGRTHM, 19, 1)

+ FIELD(VPLL_FRAC_CFG, ORDER, 18, 1)

+ FIELD(VPLL_FRAC_CFG, DATA, 0, 16)

+REG32(PLL_STATUS, 0x44)