1 | Mostly straightforward bugfixes. The new Xilinx devices are | 1 | First arm pullreq for 7.1. The bulk of this is the qemu_split_irq |
---|---|---|---|
2 | arguably 'new feature', but they're fixing a regression where | 2 | removal. |
3 | our changes to PSCI in commit 3f37979bf mean that EL3 guest | 3 | |
4 | code now needs to talk to a proper emulated power-controller | 4 | I have enough stuff in my to-review queue that I expect to do another |
5 | device to turn on secondary CPUs; and it's not yet rc1 and | 5 | pullreq early next week, but 31 patches is enough to not hang on to. |
6 | they only affect the Xilinx board, so it seems OK to me. | ||
7 | 6 | ||
8 | thanks | 7 | thanks |
9 | -- PMM | 8 | -- PMM |
10 | 9 | ||
11 | The following changes since commit 1d60bb4b14601e38ed17384277aa4c30c57925d3: | 10 | The following changes since commit 9c125d17e9402c232c46610802e5931b3639d77b: |
12 | 11 | ||
13 | Merge tag 'pull-request-2022-03-15v2' of https://gitlab.com/thuth/qemu into staging (2022-03-16 10:43:58 +0000) | 12 | Merge tag 'pull-tcg-20220420' of https://gitlab.com/rth7680/qemu into staging (2022-04-20 16:43:11 -0700) |
14 | 13 | ||
15 | are available in the Git repository at: | 14 | are available in the Git repository at: |
16 | 15 | ||
17 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220318 | 16 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220421 |
18 | 17 | ||
19 | for you to fetch changes up to 79d54c9eac04c554e3c081589542f801ace71797: | 18 | for you to fetch changes up to 5b415dd61bdbf61fb4be0e9f1a7172b8bce682c6: |
20 | 19 | ||
21 | util/osdep: Remove some early cruft (2022-03-18 11:32:13 +0000) | 20 | hw/arm: Use bit fields for NPCM7XX PWRON STRAPs (2022-04-21 11:37:05 +0100) |
22 | 21 | ||
23 | ---------------------------------------------------------------- | 22 | ---------------------------------------------------------------- |
24 | target-arm queue: | 23 | target-arm queue: |
25 | * Fix sve2 ldnt1 and stnt1 | 24 | * hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF |
26 | * Fix pauth_check_trap vs SEL2 | 25 | * versal: Add the Cortex-R5s in the Real-Time Processing Unit (RPU) subsystem |
27 | * Fix handling of LPAE block descriptors | 26 | * versal: model enough of the Clock/Reset Low-power domain (CRL) to allow control of the Cortex-R5s |
28 | * hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size | 27 | * xlnx-zynqmp: Connect 4 TTC timers |
29 | * hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init() | 28 | * exynos4210: Refactor GIC/combiner code to stop using qemu_split_irq |
30 | * nsis installer: List emulators in alphabetical order | 29 | * realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ' |
31 | * nsis installer: Suppress "ANSI targets are deprecated" warning | 30 | * stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ' |
32 | * nsis installer: Fix mouse-over descriptions for emulators | 31 | * hw/core/irq: remove unused 'qemu_irq_split' function |
33 | * hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset | 32 | * npcm7xx: use symbolic constants for PWRON STRAP bit fields |
34 | * Improve M-profile vector table access logging | 33 | * virt: document impact of gic-version on max CPUs |
35 | * Xilinx ZynqMP: model CRF and APU control | ||
36 | * Fix compile issues on modern Solaris | ||
37 | 34 | ||
38 | ---------------------------------------------------------------- | 35 | ---------------------------------------------------------------- |
39 | Andrew Deason (3): | 36 | Edgar E. Iglesias (6): |
40 | util/osdep: Avoid madvise proto on modern Solaris | 37 | timer: cadence_ttc: Break out header file to allow embedding |
41 | hw/i386/acpi-build: Avoid 'sun' identifier | 38 | hw/arm/xlnx-zynqmp: Connect 4 TTC timers |
42 | util/osdep: Remove some early cruft | 39 | hw/arm: versal: Create an APU CPU Cluster |
40 | hw/arm: versal: Add the Cortex-R5Fs | ||
41 | hw/misc: Add a model of the Xilinx Versal CRL | ||
42 | hw/arm: versal: Connect the CRL | ||
43 | 43 | ||
44 | Edgar E. Iglesias (6): | 44 | Hao Wu (2): |
45 | hw/arm/xlnx-zynqmp: Add an unimplemented SERDES area | 45 | hw/misc: Add PWRON STRAP bit fields in GCR module |
46 | target/arm: Make rvbar settable after realize | 46 | hw/arm: Use bit fields for NPCM7XX PWRON STRAPs |
47 | hw/misc: Add a model of the Xilinx ZynqMP CRF | ||
48 | hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF | ||
49 | hw/misc: Add a model of the Xilinx ZynqMP APU Control | ||
50 | hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control | ||
51 | 47 | ||
52 | Eric Auger (2): | 48 | Heinrich Schuchardt (1): |
53 | hw/intc: Rename CONFIG_ARM_GIC_TCG into CONFIG_ARM_GICV3_TCG | 49 | hw/arm/virt: impact of gic-version on max CPUs |
54 | hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset | ||
55 | 50 | ||
56 | Peter Maydell (8): | 51 | Peter Maydell (19): |
57 | target/arm: Fix handling of LPAE block descriptors | 52 | hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF |
58 | hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size | 53 | hw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom OR-gate device |
59 | hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init() | 54 | hw/intc/exynos4210_gic: Remove unused TYPE_EXYNOS4210_IRQ_GATE |
60 | nsis installer: List emulators in alphabetical order | 55 | hw/arm/exynos4210: Put a9mpcore device into state struct |
61 | nsis installer: Suppress "ANSI targets are deprecated" warning | 56 | hw/arm/exynos4210: Drop int_gic_irq[] from Exynos4210Irq struct |
62 | nsis installer: Fix mouse-over descriptions for emulators | 57 | hw/arm/exynos4210: Coalesce board_irqs and irq_table |
63 | target/arm: Log M-profile vector table accesses | 58 | hw/arm/exynos4210: Fix code style nit in combiner_grp_to_gic_id[] |
64 | target/arm: Log fault address for M-profile faults | 59 | hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.c |
60 | hw/arm/exynos4210: Put external GIC into state struct | ||
61 | hw/arm/exynos4210: Drop ext_gic_irq[] from Exynos4210Irq struct | ||
62 | hw/arm/exynos4210: Move exynos4210_combiner_get_gpioin() into exynos4210.c | ||
63 | hw/arm/exynos4210: Delete unused macro definitions | ||
64 | hw/arm/exynos4210: Use TYPE_SPLIT_IRQ in exynos4210_init_board_irqs() | ||
65 | hw/arm/exynos4210: Fill in irq_table[] for internal-combiner-only IRQ lines | ||
66 | hw/arm/exynos4210: Connect MCT_G0 and MCT_G1 to both combiners | ||
67 | hw/arm/exynos4210: Don't connect multiple lines to external GIC inputs | ||
68 | hw/arm/exynos4210: Fold combiner splits into exynos4210_init_board_irqs() | ||
69 | hw/arm/exynos4210: Put combiners into state struct | ||
70 | hw/arm/exynos4210: Drop Exynos4210Irq struct | ||
65 | 71 | ||
66 | Richard Henderson (2): | 72 | Zongyuan Li (3): |
67 | target/arm: Fix sve2 ldnt1 and stnt1 | 73 | hw/arm/realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ' |
68 | target/arm: Fix pauth_check_trap vs SEL2 | 74 | hw/arm/stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ' |
75 | hw/core/irq: remove unused 'qemu_irq_split' function | ||
69 | 76 | ||
70 | meson.build | 23 ++- | 77 | docs/system/arm/virt.rst | 4 +- |
71 | include/hw/arm/xlnx-zynqmp.h | 4 + | 78 | include/hw/arm/exynos4210.h | 50 ++-- |
72 | include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 93 ++++++++++++ | 79 | include/hw/arm/xlnx-versal.h | 16 ++ |
73 | include/hw/misc/xlnx-zynqmp-crf.h | 211 ++++++++++++++++++++++++++ | 80 | include/hw/arm/xlnx-zynqmp.h | 4 + |
74 | include/qemu/osdep.h | 8 + | 81 | include/hw/intc/exynos4210_combiner.h | 57 +++++ |
75 | target/arm/cpu.h | 3 +- | 82 | include/hw/intc/exynos4210_gic.h | 43 ++++ |
76 | target/arm/sve.decode | 5 +- | 83 | include/hw/irq.h | 5 - |
77 | hw/arm/virt.c | 7 +- | 84 | include/hw/misc/npcm7xx_gcr.h | 30 +++ |
78 | hw/arm/xlnx-zynqmp.c | 46 +++++- | 85 | include/hw/misc/xlnx-versal-crl.h | 235 +++++++++++++++++++ |
79 | hw/dma/xlnx_csu_dma.c | 1 + | 86 | include/hw/timer/cadence_ttc.h | 54 +++++ |
80 | hw/i386/acpi-build.c | 4 +- | 87 | hw/arm/exynos4210.c | 430 ++++++++++++++++++++++++++++++---- |
81 | hw/misc/npcm7xx_clk.c | 4 +- | 88 | hw/arm/npcm7xx_boards.c | 24 +- |
82 | hw/misc/xlnx-zynqmp-apu-ctrl.c | 253 +++++++++++++++++++++++++++++++ | 89 | hw/arm/realview.c | 33 ++- |
83 | hw/misc/xlnx-zynqmp-crf.c | 266 +++++++++++++++++++++++++++++++++ | 90 | hw/arm/stellaris.c | 15 +- |
84 | target/arm/cpu.c | 17 ++- | 91 | hw/arm/virt.c | 7 + |
85 | target/arm/helper.c | 20 ++- | 92 | hw/arm/xlnx-versal-virt.c | 6 +- |
86 | target/arm/m_helper.c | 11 ++ | 93 | hw/arm/xlnx-versal.c | 99 +++++++- |
87 | target/arm/pauth_helper.c | 2 +- | 94 | hw/arm/xlnx-zynqmp.c | 22 ++ |
88 | target/arm/translate-sve.c | 51 ++++++- | 95 | hw/core/irq.c | 15 -- |
89 | tests/tcg/aarch64/test-826.c | 50 +++++++ | 96 | hw/intc/exynos4210_combiner.c | 108 +-------- |
90 | util/osdep.c | 10 -- | 97 | hw/intc/exynos4210_gic.c | 344 +-------------------------- |
91 | hw/intc/Kconfig | 2 +- | 98 | hw/misc/xlnx-versal-crl.c | 421 +++++++++++++++++++++++++++++++++ |
92 | hw/intc/meson.build | 4 +- | 99 | hw/timer/cadence_ttc.c | 32 +-- |
93 | hw/misc/meson.build | 2 + | 100 | MAINTAINERS | 2 +- |
94 | qemu.nsi | 8 +- | 101 | hw/misc/meson.build | 1 + |
95 | scripts/nsis.py | 17 ++- | 102 | 25 files changed, 1457 insertions(+), 600 deletions(-) |
96 | tests/tcg/aarch64/Makefile.target | 4 + | 103 | create mode 100644 include/hw/intc/exynos4210_combiner.h |
97 | tests/tcg/configure.sh | 4 + | 104 | create mode 100644 include/hw/intc/exynos4210_gic.h |
98 | 28 files changed, 1084 insertions(+), 46 deletions(-) | 105 | create mode 100644 include/hw/misc/xlnx-versal-crl.h |
99 | create mode 100644 include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 106 | create mode 100644 include/hw/timer/cadence_ttc.h |
100 | create mode 100644 include/hw/misc/xlnx-zynqmp-crf.h | 107 | create mode 100644 hw/misc/xlnx-versal-crl.c |
101 | create mode 100644 hw/misc/xlnx-zynqmp-apu-ctrl.c | ||
102 | create mode 100644 hw/misc/xlnx-zynqmp-crf.c | ||
103 | create mode 100644 tests/tcg/aarch64/test-826.c | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | It's not possible to provide the guest with the Security extensions |
---|---|---|---|
2 | (TrustZone) when using KVM or HVF, because the hardware | ||
3 | virtualization extensions don't permit running EL3 guest code. | ||
4 | However, we weren't checking for this combination, with the result | ||
5 | that QEMU would assert if you tried it: | ||
2 | 6 | ||
3 | In TCG mode, if gic-version=max we always select GICv3 even if | 7 | $ qemu-system-aarch64 -enable-kvm -machine virt,secure=on -cpu host -display none |
4 | CONFIG_ARM_GICV3_TCG is unset. We shall rather select GICv2. | 8 | Unexpected error in object_property_find_err() at ../../qom/object.c:1304: |
5 | This also brings the benefit of fixing qos tests errors for tests | 9 | qemu-system-aarch64: Property 'host-arm-cpu.secure-memory' not found |
6 | using gic-version=max with CONFIG_ARM_GICV3_TCG unset. | 10 | Aborted |
7 | 11 | ||
8 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | 12 | Check for this combination of options and report an error, in the |
9 | Reviewed-by: Andrew Jones <drjones@redhat.com> | 13 | same way we already do for attempts to give a KVM or HVF guest the |
10 | Message-id: 20220308182452.223473-3-eric.auger@redhat.com | 14 | Virtualization or MTE extensions. Now we will report: |
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 15 | |
16 | qemu-system-aarch64: mach-virt: KVM does not support providing Security extensions (TrustZone) to the guest CPU | ||
17 | |||
18 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/961 | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
20 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
21 | Message-id: 20220404155301.566542-1-peter.maydell@linaro.org | ||
13 | --- | 22 | --- |
14 | hw/arm/virt.c | 7 ++++++- | 23 | hw/arm/virt.c | 7 +++++++ |
15 | 1 file changed, 6 insertions(+), 1 deletion(-) | 24 | 1 file changed, 7 insertions(+) |
16 | 25 | ||
17 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 26 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
18 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/arm/virt.c | 28 | --- a/hw/arm/virt.c |
20 | +++ b/hw/arm/virt.c | 29 | +++ b/hw/arm/virt.c |
21 | @@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms) | 30 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) |
22 | vms->gic_version = VIRT_GIC_VERSION_2; | 31 | exit(1); |
23 | break; | 32 | } |
24 | case VIRT_GIC_VERSION_MAX: | 33 | |
25 | - vms->gic_version = VIRT_GIC_VERSION_3; | 34 | + if (vms->secure && (kvm_enabled() || hvf_enabled())) { |
26 | + if (module_object_class_by_name("arm-gicv3")) { | 35 | + error_report("mach-virt: %s does not support providing " |
27 | + /* CONFIG_ARM_GICV3_TCG was set */ | 36 | + "Security extensions (TrustZone) to the guest CPU", |
28 | + vms->gic_version = VIRT_GIC_VERSION_3; | 37 | + kvm_enabled() ? "KVM" : "HVF"); |
29 | + } else { | 38 | + exit(1); |
30 | + vms->gic_version = VIRT_GIC_VERSION_2; | 39 | + } |
31 | + } | 40 | + |
32 | break; | 41 | if (vms->virt && (kvm_enabled() || hvf_enabled())) { |
33 | case VIRT_GIC_VERSION_HOST: | 42 | error_report("mach-virt: %s does not support providing " |
34 | error_report("gic-version=host requires KVM"); | 43 | "Virtualization extensions to the guest CPU", |
35 | -- | 44 | -- |
36 | 2.25.1 | 45 | 2.25.1 | diff view generated by jsdifflib |
1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | From: "Edgar E. Iglesias" <edgar.iglesias@amd.com> |
---|---|---|---|
2 | 2 | ||
3 | Add a model of the Xilinx ZynqMP APU Control. | 3 | Break out header file to allow embedding of the the TTC. |
4 | 4 | ||
5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> | ||
6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
5 | Reviewed-by: Luc Michel <luc@lmichel.fr> | 7 | Reviewed-by: Luc Michel <luc@lmichel.fr> |
6 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 8 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> |
7 | Message-id: 20220316164645.2303510-6-edgar.iglesias@gmail.com | 9 | Message-id: 20220331222017.2914409-2-edgar.iglesias@gmail.com |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 11 | --- |
10 | include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 93 +++++++++ | 12 | include/hw/timer/cadence_ttc.h | 54 ++++++++++++++++++++++++++++++++++ |
11 | hw/misc/xlnx-zynqmp-apu-ctrl.c | 253 +++++++++++++++++++++++++ | 13 | hw/timer/cadence_ttc.c | 32 ++------------------ |
12 | hw/misc/meson.build | 1 + | 14 | 2 files changed, 56 insertions(+), 30 deletions(-) |
13 | 3 files changed, 347 insertions(+) | 15 | create mode 100644 include/hw/timer/cadence_ttc.h |
14 | create mode 100644 include/hw/misc/xlnx-zynqmp-apu-ctrl.h | ||
15 | create mode 100644 hw/misc/xlnx-zynqmp-apu-ctrl.c | ||
16 | 16 | ||
17 | diff --git a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 17 | diff --git a/include/hw/timer/cadence_ttc.h b/include/hw/timer/cadence_ttc.h |
18 | new file mode 100644 | 18 | new file mode 100644 |
19 | index XXXXXXX..XXXXXXX | 19 | index XXXXXXX..XXXXXXX |
20 | --- /dev/null | 20 | --- /dev/null |
21 | +++ b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 21 | +++ b/include/hw/timer/cadence_ttc.h |
22 | @@ -XXX,XX +XXX,XX @@ | 22 | @@ -XXX,XX +XXX,XX @@ |
23 | +/* | 23 | +/* |
24 | + * QEMU model of ZynqMP APU Control. | 24 | + * Xilinx Zynq cadence TTC model |
25 | + * | 25 | + * |
26 | + * Copyright (c) 2013-2022 Xilinx Inc | 26 | + * Copyright (c) 2011 Xilinx Inc. |
27 | + * SPDX-License-Identifier: GPL-2.0-or-later | 27 | + * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) |
28 | + * Copyright (c) 2012 PetaLogix Pty Ltd. | ||
29 | + * Written By Haibing Ma | ||
30 | + * M. Habib | ||
28 | + * | 31 | + * |
29 | + * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> and | 32 | + * This program is free software; you can redistribute it and/or |
30 | + * Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 33 | + * modify it under the terms of the GNU General Public License |
34 | + * as published by the Free Software Foundation; either version | ||
35 | + * 2 of the License, or (at your option) any later version. | ||
31 | + * | 36 | + * |
37 | + * You should have received a copy of the GNU General Public License along | ||
38 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
32 | + */ | 39 | + */ |
33 | +#ifndef HW_MISC_XLNX_ZYNQMP_APU_CTRL_H | 40 | +#ifndef HW_TIMER_CADENCE_TTC_H |
34 | +#define HW_MISC_XLNX_ZYNQMP_APU_CTRL_H | 41 | +#define HW_TIMER_CADENCE_TTC_H |
35 | + | 42 | + |
36 | +#include "hw/sysbus.h" | 43 | +#include "hw/sysbus.h" |
37 | +#include "hw/register.h" | 44 | +#include "qemu/timer.h" |
38 | +#include "target/arm/cpu.h" | ||
39 | + | 45 | + |
40 | +#define TYPE_XLNX_ZYNQMP_APU_CTRL "xlnx.apu-ctrl" | 46 | +typedef struct { |
41 | +OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPAPUCtrl, XLNX_ZYNQMP_APU_CTRL) | 47 | + QEMUTimer *timer; |
48 | + int freq; | ||
42 | + | 49 | + |
43 | +REG32(APU_ERR_CTRL, 0x0) | 50 | + uint32_t reg_clock; |
44 | + FIELD(APU_ERR_CTRL, PSLVERR, 0, 1) | 51 | + uint32_t reg_count; |
45 | +REG32(ISR, 0x10) | 52 | + uint32_t reg_value; |
46 | + FIELD(ISR, INV_APB, 0, 1) | 53 | + uint16_t reg_interval; |
47 | +REG32(IMR, 0x14) | 54 | + uint16_t reg_match[3]; |
48 | + FIELD(IMR, INV_APB, 0, 1) | 55 | + uint32_t reg_intr; |
49 | +REG32(IEN, 0x18) | 56 | + uint32_t reg_intr_en; |
50 | + FIELD(IEN, INV_APB, 0, 1) | 57 | + uint32_t reg_event_ctrl; |
51 | +REG32(IDS, 0x1c) | 58 | + uint32_t reg_event; |
52 | + FIELD(IDS, INV_APB, 0, 1) | ||
53 | +REG32(CONFIG_0, 0x20) | ||
54 | + FIELD(CONFIG_0, CFGTE, 24, 4) | ||
55 | + FIELD(CONFIG_0, CFGEND, 16, 4) | ||
56 | + FIELD(CONFIG_0, VINITHI, 8, 4) | ||
57 | + FIELD(CONFIG_0, AA64NAA32, 0, 4) | ||
58 | +REG32(CONFIG_1, 0x24) | ||
59 | + FIELD(CONFIG_1, L2RSTDISABLE, 29, 1) | ||
60 | + FIELD(CONFIG_1, L1RSTDISABLE, 28, 1) | ||
61 | + FIELD(CONFIG_1, CP15DISABLE, 0, 4) | ||
62 | +REG32(RVBARADDR0L, 0x40) | ||
63 | + FIELD(RVBARADDR0L, ADDR, 2, 30) | ||
64 | +REG32(RVBARADDR0H, 0x44) | ||
65 | + FIELD(RVBARADDR0H, ADDR, 0, 8) | ||
66 | +REG32(RVBARADDR1L, 0x48) | ||
67 | + FIELD(RVBARADDR1L, ADDR, 2, 30) | ||
68 | +REG32(RVBARADDR1H, 0x4c) | ||
69 | + FIELD(RVBARADDR1H, ADDR, 0, 8) | ||
70 | +REG32(RVBARADDR2L, 0x50) | ||
71 | + FIELD(RVBARADDR2L, ADDR, 2, 30) | ||
72 | +REG32(RVBARADDR2H, 0x54) | ||
73 | + FIELD(RVBARADDR2H, ADDR, 0, 8) | ||
74 | +REG32(RVBARADDR3L, 0x58) | ||
75 | + FIELD(RVBARADDR3L, ADDR, 2, 30) | ||
76 | +REG32(RVBARADDR3H, 0x5c) | ||
77 | + FIELD(RVBARADDR3H, ADDR, 0, 8) | ||
78 | +REG32(ACE_CTRL, 0x60) | ||
79 | + FIELD(ACE_CTRL, AWQOS, 16, 4) | ||
80 | + FIELD(ACE_CTRL, ARQOS, 0, 4) | ||
81 | +REG32(SNOOP_CTRL, 0x80) | ||
82 | + FIELD(SNOOP_CTRL, ACE_INACT, 4, 1) | ||
83 | + FIELD(SNOOP_CTRL, ACP_INACT, 0, 1) | ||
84 | +REG32(PWRCTL, 0x90) | ||
85 | + FIELD(PWRCTL, CLREXMONREQ, 17, 1) | ||
86 | + FIELD(PWRCTL, L2FLUSHREQ, 16, 1) | ||
87 | + FIELD(PWRCTL, CPUPWRDWNREQ, 0, 4) | ||
88 | +REG32(PWRSTAT, 0x94) | ||
89 | + FIELD(PWRSTAT, CLREXMONACK, 17, 1) | ||
90 | + FIELD(PWRSTAT, L2FLUSHDONE, 16, 1) | ||
91 | + FIELD(PWRSTAT, DBGNOPWRDWN, 0, 4) | ||
92 | + | 59 | + |
93 | +#define APU_R_MAX ((R_PWRSTAT) + 1) | 60 | + uint64_t cpu_time; |
61 | + unsigned int cpu_time_valid; | ||
94 | + | 62 | + |
95 | +#define APU_MAX_CPU 4 | 63 | + qemu_irq irq; |
64 | +} CadenceTimerState; | ||
96 | + | 65 | + |
97 | +struct XlnxZynqMPAPUCtrl { | 66 | +#define TYPE_CADENCE_TTC "cadence_ttc" |
98 | + SysBusDevice busdev; | 67 | +OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC) |
99 | + | 68 | + |
100 | + ARMCPU *cpus[APU_MAX_CPU]; | 69 | +struct CadenceTTCState { |
101 | + /* WFIs towards PMU. */ | 70 | + SysBusDevice parent_obj; |
102 | + qemu_irq wfi_out[4]; | ||
103 | + /* CPU Power status towards INTC Redirect. */ | ||
104 | + qemu_irq cpu_power_status[4]; | ||
105 | + qemu_irq irq_imr; | ||
106 | + | 71 | + |
107 | + uint8_t cpu_pwrdwn_req; | 72 | + MemoryRegion iomem; |
108 | + uint8_t cpu_in_wfi; | 73 | + CadenceTimerState timer[3]; |
109 | + | ||
110 | + RegisterInfoArray *reg_array; | ||
111 | + uint32_t regs[APU_R_MAX]; | ||
112 | + RegisterInfo regs_info[APU_R_MAX]; | ||
113 | +}; | 74 | +}; |
114 | + | 75 | + |
115 | +#endif | 76 | +#endif |
116 | diff --git a/hw/misc/xlnx-zynqmp-apu-ctrl.c b/hw/misc/xlnx-zynqmp-apu-ctrl.c | 77 | diff --git a/hw/timer/cadence_ttc.c b/hw/timer/cadence_ttc.c |
117 | new file mode 100644 | 78 | index XXXXXXX..XXXXXXX 100644 |
118 | index XXXXXXX..XXXXXXX | 79 | --- a/hw/timer/cadence_ttc.c |
119 | --- /dev/null | 80 | +++ b/hw/timer/cadence_ttc.c |
120 | +++ b/hw/misc/xlnx-zynqmp-apu-ctrl.c | ||
121 | @@ -XXX,XX +XXX,XX @@ | 81 | @@ -XXX,XX +XXX,XX @@ |
122 | +/* | 82 | #include "qemu/timer.h" |
123 | + * QEMU model of the ZynqMP APU Control. | 83 | #include "qom/object.h" |
124 | + * | 84 | |
125 | + * Copyright (c) 2013-2022 Xilinx Inc | 85 | +#include "hw/timer/cadence_ttc.h" |
126 | + * SPDX-License-Identifier: GPL-2.0-or-later | ||
127 | + * | ||
128 | + * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> and | ||
129 | + * Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
130 | + */ | ||
131 | + | 86 | + |
132 | +#include "qemu/osdep.h" | 87 | #ifdef CADENCE_TTC_ERR_DEBUG |
133 | +#include "qapi/error.h" | 88 | #define DB_PRINT(...) do { \ |
134 | +#include "qemu/log.h" | 89 | fprintf(stderr, ": %s: ", __func__); \ |
135 | +#include "migration/vmstate.h" | 90 | @@ -XXX,XX +XXX,XX @@ |
136 | +#include "hw/qdev-properties.h" | 91 | #define CLOCK_CTRL_PS_EN 0x00000001 |
137 | +#include "hw/sysbus.h" | 92 | #define CLOCK_CTRL_PS_V 0x0000001e |
138 | +#include "hw/irq.h" | 93 | |
139 | +#include "hw/register.h" | 94 | -typedef struct { |
140 | + | 95 | - QEMUTimer *timer; |
141 | +#include "qemu/bitops.h" | 96 | - int freq; |
142 | +#include "qapi/qmp/qerror.h" | 97 | - |
143 | + | 98 | - uint32_t reg_clock; |
144 | +#include "hw/misc/xlnx-zynqmp-apu-ctrl.h" | 99 | - uint32_t reg_count; |
145 | + | 100 | - uint32_t reg_value; |
146 | +#ifndef XILINX_ZYNQMP_APU_ERR_DEBUG | 101 | - uint16_t reg_interval; |
147 | +#define XILINX_ZYNQMP_APU_ERR_DEBUG 0 | 102 | - uint16_t reg_match[3]; |
148 | +#endif | 103 | - uint32_t reg_intr; |
149 | + | 104 | - uint32_t reg_intr_en; |
150 | +static void update_wfi_out(void *opaque) | 105 | - uint32_t reg_event_ctrl; |
151 | +{ | 106 | - uint32_t reg_event; |
152 | + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(opaque); | 107 | - |
153 | + unsigned int i, wfi_pending; | 108 | - uint64_t cpu_time; |
154 | + | 109 | - unsigned int cpu_time_valid; |
155 | + wfi_pending = s->cpu_pwrdwn_req & s->cpu_in_wfi; | 110 | - |
156 | + for (i = 0; i < APU_MAX_CPU; i++) { | 111 | - qemu_irq irq; |
157 | + qemu_set_irq(s->wfi_out[i], !!(wfi_pending & (1 << i))); | 112 | -} CadenceTimerState; |
158 | + } | 113 | - |
159 | +} | 114 | -#define TYPE_CADENCE_TTC "cadence_ttc" |
160 | + | 115 | -OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC) |
161 | +static void zynqmp_apu_rvbar_post_write(RegisterInfo *reg, uint64_t val) | 116 | - |
162 | +{ | 117 | -struct CadenceTTCState { |
163 | + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque); | 118 | - SysBusDevice parent_obj; |
164 | + int i; | 119 | - |
165 | + | 120 | - MemoryRegion iomem; |
166 | + for (i = 0; i < APU_MAX_CPU; ++i) { | 121 | - CadenceTimerState timer[3]; |
167 | + uint64_t rvbar = s->regs[R_RVBARADDR0L + 2 * i] + | 122 | -}; |
168 | + ((uint64_t)s->regs[R_RVBARADDR0H + 2 * i] << 32); | 123 | - |
169 | + if (s->cpus[i]) { | 124 | static void cadence_timer_update(CadenceTimerState *s) |
170 | + object_property_set_int(OBJECT(s->cpus[i]), "rvbar", rvbar, | 125 | { |
171 | + &error_abort); | 126 | qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en)); |
172 | + } | ||
173 | + } | ||
174 | +} | ||
175 | + | ||
176 | +static void zynqmp_apu_pwrctl_post_write(RegisterInfo *reg, uint64_t val) | ||
177 | +{ | ||
178 | + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque); | ||
179 | + unsigned int i, new; | ||
180 | + | ||
181 | + for (i = 0; i < APU_MAX_CPU; i++) { | ||
182 | + new = val & (1 << i); | ||
183 | + /* Check if CPU's CPUPWRDNREQ has changed. If yes, update GPIOs. */ | ||
184 | + if (new != (s->cpu_pwrdwn_req & (1 << i))) { | ||
185 | + qemu_set_irq(s->cpu_power_status[i], !!new); | ||
186 | + } | ||
187 | + s->cpu_pwrdwn_req &= ~(1 << i); | ||
188 | + s->cpu_pwrdwn_req |= new; | ||
189 | + } | ||
190 | + update_wfi_out(s); | ||
191 | +} | ||
192 | + | ||
193 | +static void imr_update_irq(XlnxZynqMPAPUCtrl *s) | ||
194 | +{ | ||
195 | + bool pending = s->regs[R_ISR] & ~s->regs[R_IMR]; | ||
196 | + qemu_set_irq(s->irq_imr, pending); | ||
197 | +} | ||
198 | + | ||
199 | +static void isr_postw(RegisterInfo *reg, uint64_t val64) | ||
200 | +{ | ||
201 | + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque); | ||
202 | + imr_update_irq(s); | ||
203 | +} | ||
204 | + | ||
205 | +static uint64_t ien_prew(RegisterInfo *reg, uint64_t val64) | ||
206 | +{ | ||
207 | + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque); | ||
208 | + uint32_t val = val64; | ||
209 | + | ||
210 | + s->regs[R_IMR] &= ~val; | ||
211 | + imr_update_irq(s); | ||
212 | + return 0; | ||
213 | +} | ||
214 | + | ||
215 | +static uint64_t ids_prew(RegisterInfo *reg, uint64_t val64) | ||
216 | +{ | ||
217 | + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque); | ||
218 | + uint32_t val = val64; | ||
219 | + | ||
220 | + s->regs[R_IMR] |= val; | ||
221 | + imr_update_irq(s); | ||
222 | + return 0; | ||
223 | +} | ||
224 | + | ||
225 | +static const RegisterAccessInfo zynqmp_apu_regs_info[] = { | ||
226 | +#define RVBAR_REGDEF(n) \ | ||
227 | + { .name = "RVBAR CPU " #n " Low", .addr = A_RVBARADDR ## n ## L, \ | ||
228 | + .reset = 0xffff0000ul, \ | ||
229 | + .post_write = zynqmp_apu_rvbar_post_write, \ | ||
230 | + },{ .name = "RVBAR CPU " #n " High", .addr = A_RVBARADDR ## n ## H, \ | ||
231 | + .post_write = zynqmp_apu_rvbar_post_write, \ | ||
232 | + } | ||
233 | + { .name = "ERR_CTRL", .addr = A_APU_ERR_CTRL, | ||
234 | + },{ .name = "ISR", .addr = A_ISR, | ||
235 | + .w1c = 0x1, | ||
236 | + .post_write = isr_postw, | ||
237 | + },{ .name = "IMR", .addr = A_IMR, | ||
238 | + .reset = 0x1, | ||
239 | + .ro = 0x1, | ||
240 | + },{ .name = "IEN", .addr = A_IEN, | ||
241 | + .pre_write = ien_prew, | ||
242 | + },{ .name = "IDS", .addr = A_IDS, | ||
243 | + .pre_write = ids_prew, | ||
244 | + },{ .name = "CONFIG_0", .addr = A_CONFIG_0, | ||
245 | + .reset = 0xf0f, | ||
246 | + },{ .name = "CONFIG_1", .addr = A_CONFIG_1, | ||
247 | + }, | ||
248 | + RVBAR_REGDEF(0), | ||
249 | + RVBAR_REGDEF(1), | ||
250 | + RVBAR_REGDEF(2), | ||
251 | + RVBAR_REGDEF(3), | ||
252 | + { .name = "ACE_CTRL", .addr = A_ACE_CTRL, | ||
253 | + .reset = 0xf000f, | ||
254 | + },{ .name = "SNOOP_CTRL", .addr = A_SNOOP_CTRL, | ||
255 | + },{ .name = "PWRCTL", .addr = A_PWRCTL, | ||
256 | + .post_write = zynqmp_apu_pwrctl_post_write, | ||
257 | + },{ .name = "PWRSTAT", .addr = A_PWRSTAT, | ||
258 | + .ro = 0x3000f, | ||
259 | + } | ||
260 | +}; | ||
261 | + | ||
262 | +static void zynqmp_apu_reset_enter(Object *obj, ResetType type) | ||
263 | +{ | ||
264 | + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj); | ||
265 | + int i; | ||
266 | + | ||
267 | + for (i = 0; i < APU_R_MAX; ++i) { | ||
268 | + register_reset(&s->regs_info[i]); | ||
269 | + } | ||
270 | + | ||
271 | + s->cpu_pwrdwn_req = 0; | ||
272 | + s->cpu_in_wfi = 0; | ||
273 | +} | ||
274 | + | ||
275 | +static void zynqmp_apu_reset_hold(Object *obj) | ||
276 | +{ | ||
277 | + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj); | ||
278 | + | ||
279 | + update_wfi_out(s); | ||
280 | + imr_update_irq(s); | ||
281 | +} | ||
282 | + | ||
283 | +static const MemoryRegionOps zynqmp_apu_ops = { | ||
284 | + .read = register_read_memory, | ||
285 | + .write = register_write_memory, | ||
286 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
287 | + .valid = { | ||
288 | + .min_access_size = 4, | ||
289 | + .max_access_size = 4, | ||
290 | + } | ||
291 | +}; | ||
292 | + | ||
293 | +static void zynqmp_apu_handle_wfi(void *opaque, int irq, int level) | ||
294 | +{ | ||
295 | + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(opaque); | ||
296 | + | ||
297 | + s->cpu_in_wfi = deposit32(s->cpu_in_wfi, irq, 1, level); | ||
298 | + update_wfi_out(s); | ||
299 | +} | ||
300 | + | ||
301 | +static void zynqmp_apu_init(Object *obj) | ||
302 | +{ | ||
303 | + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj); | ||
304 | + int i; | ||
305 | + | ||
306 | + s->reg_array = | ||
307 | + register_init_block32(DEVICE(obj), zynqmp_apu_regs_info, | ||
308 | + ARRAY_SIZE(zynqmp_apu_regs_info), | ||
309 | + s->regs_info, s->regs, | ||
310 | + &zynqmp_apu_ops, | ||
311 | + XILINX_ZYNQMP_APU_ERR_DEBUG, | ||
312 | + APU_R_MAX * 4); | ||
313 | + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->reg_array->mem); | ||
314 | + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq_imr); | ||
315 | + | ||
316 | + for (i = 0; i < APU_MAX_CPU; ++i) { | ||
317 | + g_autofree gchar *prop_name = g_strdup_printf("cpu%d", i); | ||
318 | + object_property_add_link(obj, prop_name, TYPE_ARM_CPU, | ||
319 | + (Object **)&s->cpus[i], | ||
320 | + qdev_prop_allow_set_link_before_realize, | ||
321 | + OBJ_PROP_LINK_STRONG); | ||
322 | + } | ||
323 | + | ||
324 | + /* wfi_out is used to connect to PMU GPIs. */ | ||
325 | + qdev_init_gpio_out_named(DEVICE(obj), s->wfi_out, "wfi_out", 4); | ||
326 | + /* CPU_POWER_STATUS is used to connect to INTC redirect. */ | ||
327 | + qdev_init_gpio_out_named(DEVICE(obj), s->cpu_power_status, | ||
328 | + "CPU_POWER_STATUS", 4); | ||
329 | + /* wfi_in is used as input from CPUs as wfi request. */ | ||
330 | + qdev_init_gpio_in_named(DEVICE(obj), zynqmp_apu_handle_wfi, "wfi_in", 4); | ||
331 | +} | ||
332 | + | ||
333 | +static void zynqmp_apu_finalize(Object *obj) | ||
334 | +{ | ||
335 | + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj); | ||
336 | + register_finalize_block(s->reg_array); | ||
337 | +} | ||
338 | + | ||
339 | +static const VMStateDescription vmstate_zynqmp_apu = { | ||
340 | + .name = TYPE_XLNX_ZYNQMP_APU_CTRL, | ||
341 | + .version_id = 1, | ||
342 | + .minimum_version_id = 1, | ||
343 | + .fields = (VMStateField[]) { | ||
344 | + VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPAPUCtrl, APU_R_MAX), | ||
345 | + VMSTATE_END_OF_LIST(), | ||
346 | + } | ||
347 | +}; | ||
348 | + | ||
349 | +static void zynqmp_apu_class_init(ObjectClass *klass, void *data) | ||
350 | +{ | ||
351 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
352 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
353 | + | ||
354 | + dc->vmsd = &vmstate_zynqmp_apu; | ||
355 | + | ||
356 | + rc->phases.enter = zynqmp_apu_reset_enter; | ||
357 | + rc->phases.hold = zynqmp_apu_reset_hold; | ||
358 | +} | ||
359 | + | ||
360 | +static const TypeInfo zynqmp_apu_info = { | ||
361 | + .name = TYPE_XLNX_ZYNQMP_APU_CTRL, | ||
362 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
363 | + .instance_size = sizeof(XlnxZynqMPAPUCtrl), | ||
364 | + .class_init = zynqmp_apu_class_init, | ||
365 | + .instance_init = zynqmp_apu_init, | ||
366 | + .instance_finalize = zynqmp_apu_finalize, | ||
367 | +}; | ||
368 | + | ||
369 | +static void zynqmp_apu_register_types(void) | ||
370 | +{ | ||
371 | + type_register_static(&zynqmp_apu_info); | ||
372 | +} | ||
373 | + | ||
374 | +type_init(zynqmp_apu_register_types) | ||
375 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
376 | index XXXXXXX..XXXXXXX 100644 | ||
377 | --- a/hw/misc/meson.build | ||
378 | +++ b/hw/misc/meson.build | ||
379 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files( | ||
380 | softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) | ||
381 | softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c')) | ||
382 | specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c')) | ||
383 | +specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c')) | ||
384 | softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files( | ||
385 | 'xlnx-versal-xramc.c', | ||
386 | 'xlnx-versal-pmc-iou-slcr.c', | ||
387 | -- | 127 | -- |
388 | 2.25.1 | 128 | 2.25.1 | diff view generated by jsdifflib |
1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | From: "Edgar E. Iglesias" <edgar.iglesias@amd.com> |
---|---|---|---|
2 | 2 | ||
3 | Connect the ZynqMP CRF - Clock Reset FPD device. | 3 | Connect the 4 TTC timers on the ZynqMP. |
4 | 4 | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> |
6 | Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com> | 6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
7 | Reviewed-by: Luc Michel <luc@lmichel.fr> | 7 | Reviewed-by: Luc Michel <luc@lmichel.fr> |
8 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 8 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> |
9 | Message-id: 20220316164645.2303510-5-edgar.iglesias@gmail.com | 9 | Message-id: 20220331222017.2914409-3-edgar.iglesias@gmail.com |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 11 | --- |
12 | include/hw/arm/xlnx-zynqmp.h | 2 ++ | 12 | include/hw/arm/xlnx-zynqmp.h | 4 ++++ |
13 | hw/arm/xlnx-zynqmp.c | 16 ++++++++++++++++ | 13 | hw/arm/xlnx-zynqmp.c | 22 ++++++++++++++++++++++ |
14 | 2 files changed, 18 insertions(+) | 14 | 2 files changed, 26 insertions(+) |
15 | 15 | ||
16 | diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h | 16 | diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h |
17 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/arm/xlnx-zynqmp.h | 18 | --- a/include/hw/arm/xlnx-zynqmp.h |
19 | +++ b/include/hw/arm/xlnx-zynqmp.h | 19 | +++ b/include/hw/arm/xlnx-zynqmp.h |
20 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ |
21 | #include "hw/nvram/xlnx-bbram.h" | ||
22 | #include "hw/nvram/xlnx-zynqmp-efuse.h" | ||
23 | #include "hw/or-irq.h" | 21 | #include "hw/or-irq.h" |
24 | +#include "hw/misc/xlnx-zynqmp-crf.h" | 22 | #include "hw/misc/xlnx-zynqmp-apu-ctrl.h" |
23 | #include "hw/misc/xlnx-zynqmp-crf.h" | ||
24 | +#include "hw/timer/cadence_ttc.h" | ||
25 | 25 | ||
26 | #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" | 26 | #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" |
27 | OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) | 27 | OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) |
28 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) | ||
29 | #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \ | ||
30 | XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE) | ||
31 | |||
32 | +#define XLNX_ZYNQMP_NUM_TTC 4 | ||
33 | + | ||
34 | /* | ||
35 | * Unimplemented mmio regions needed to boot some images. | ||
36 | */ | ||
28 | @@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState { | 37 | @@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState { |
29 | XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH]; | ||
30 | XlnxCSUDMA qspi_dma; | ||
31 | qemu_or_irq qspi_irq_orgate; | 38 | qemu_or_irq qspi_irq_orgate; |
32 | + XlnxZynqMPCRF crf; | 39 | XlnxZynqMPAPUCtrl apu_ctrl; |
40 | XlnxZynqMPCRF crf; | ||
41 | + CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC]; | ||
33 | 42 | ||
34 | char *boot_cpu; | 43 | char *boot_cpu; |
35 | ARMCPU *boot_cpu_ptr; | 44 | ARMCPU *boot_cpu_ptr; |
36 | diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c | 45 | diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c |
37 | index XXXXXXX..XXXXXXX 100644 | 46 | index XXXXXXX..XXXXXXX 100644 |
38 | --- a/hw/arm/xlnx-zynqmp.c | 47 | --- a/hw/arm/xlnx-zynqmp.c |
39 | +++ b/hw/arm/xlnx-zynqmp.c | 48 | +++ b/hw/arm/xlnx-zynqmp.c |
40 | @@ -XXX,XX +XXX,XX @@ | 49 | @@ -XXX,XX +XXX,XX @@ |
41 | #define QSPI_DMA_ADDR 0xff0f0800 | 50 | #define APU_ADDR 0xfd5c0000 |
42 | #define NUM_QSPI_IRQ_LINES 2 | 51 | #define APU_IRQ 153 |
43 | 52 | ||
44 | +#define CRF_ADDR 0xfd1a0000 | 53 | +#define TTC0_ADDR 0xFF110000 |
45 | +#define CRF_IRQ 120 | 54 | +#define TTC0_IRQ 36 |
46 | + | 55 | + |
47 | /* Serializer/Deserializer. */ | 56 | #define IPI_ADDR 0xFF300000 |
48 | #define SERDES_ADDR 0xfd400000 | 57 | #define IPI_IRQ 64 |
49 | #define SERDES_SIZE 0x20000 | 58 | |
50 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic) | 59 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic) |
51 | sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]); | 60 | sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]); |
52 | } | 61 | } |
53 | 62 | ||
54 | +static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic) | 63 | +static void xlnx_zynqmp_create_ttc(XlnxZynqMPState *s, qemu_irq *gic) |
55 | +{ | 64 | +{ |
56 | + SysBusDevice *sbd; | 65 | + SysBusDevice *sbd; |
66 | + int i, irq; | ||
57 | + | 67 | + |
58 | + object_initialize_child(OBJECT(s), "crf", &s->crf, TYPE_XLNX_ZYNQMP_CRF); | 68 | + for (i = 0; i < XLNX_ZYNQMP_NUM_TTC; i++) { |
59 | + sbd = SYS_BUS_DEVICE(&s->crf); | 69 | + object_initialize_child(OBJECT(s), "ttc[*]", &s->ttc[i], |
70 | + TYPE_CADENCE_TTC); | ||
71 | + sbd = SYS_BUS_DEVICE(&s->ttc[i]); | ||
60 | + | 72 | + |
61 | + sysbus_realize(sbd, &error_fatal); | 73 | + sysbus_realize(sbd, &error_fatal); |
62 | + sysbus_mmio_map(sbd, 0, CRF_ADDR); | 74 | + sysbus_mmio_map(sbd, 0, TTC0_ADDR + i * 0x10000); |
63 | + sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]); | 75 | + for (irq = 0; irq < 3; irq++) { |
76 | + sysbus_connect_irq(sbd, irq, gic[TTC0_IRQ + i * 3 + irq]); | ||
77 | + } | ||
78 | + } | ||
64 | +} | 79 | +} |
65 | + | 80 | + |
66 | static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) | 81 | static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) |
67 | { | 82 | { |
68 | static const struct UnimpInfo { | 83 | static const struct UnimpInfo { |
69 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) | 84 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) |
70 | |||
71 | xlnx_zynqmp_create_bbram(s, gic_spi); | ||
72 | xlnx_zynqmp_create_efuse(s, gic_spi); | 85 | xlnx_zynqmp_create_efuse(s, gic_spi); |
73 | + xlnx_zynqmp_create_crf(s, gic_spi); | 86 | xlnx_zynqmp_create_apu_ctrl(s, gic_spi); |
87 | xlnx_zynqmp_create_crf(s, gic_spi); | ||
88 | + xlnx_zynqmp_create_ttc(s, gic_spi); | ||
74 | xlnx_zynqmp_create_unimp_mmio(s); | 89 | xlnx_zynqmp_create_unimp_mmio(s); |
75 | 90 | ||
76 | for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { | 91 | for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { |
77 | -- | 92 | -- |
78 | 2.25.1 | 93 | 2.25.1 |
79 | |||
80 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: "Edgar E. Iglesias" <edgar.iglesias@amd.com> | ||
1 | 2 | ||
3 | Create an APU CPU Cluster. This is in preparation to add the RPU. | ||
4 | |||
5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> | ||
6 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | ||
7 | Message-id: 20220406174303.2022038-2-edgar.iglesias@xilinx.com | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | include/hw/arm/xlnx-versal.h | 2 ++ | ||
11 | hw/arm/xlnx-versal.c | 9 ++++++++- | ||
12 | 2 files changed, 10 insertions(+), 1 deletion(-) | ||
13 | |||
14 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/include/hw/arm/xlnx-versal.h | ||
17 | +++ b/include/hw/arm/xlnx-versal.h | ||
18 | @@ -XXX,XX +XXX,XX @@ | ||
19 | |||
20 | #include "hw/sysbus.h" | ||
21 | #include "hw/arm/boot.h" | ||
22 | +#include "hw/cpu/cluster.h" | ||
23 | #include "hw/or-irq.h" | ||
24 | #include "hw/sd/sdhci.h" | ||
25 | #include "hw/intc/arm_gicv3.h" | ||
26 | @@ -XXX,XX +XXX,XX @@ struct Versal { | ||
27 | struct { | ||
28 | struct { | ||
29 | MemoryRegion mr; | ||
30 | + CPUClusterState cluster; | ||
31 | ARMCPU cpu[XLNX_VERSAL_NR_ACPUS]; | ||
32 | GICv3State gic; | ||
33 | } apu; | ||
34 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/hw/arm/xlnx-versal.c | ||
37 | +++ b/hw/arm/xlnx-versal.c | ||
38 | @@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s) | ||
39 | { | ||
40 | int i; | ||
41 | |||
42 | + object_initialize_child(OBJECT(s), "apu-cluster", &s->fpd.apu.cluster, | ||
43 | + TYPE_CPU_CLUSTER); | ||
44 | + qdev_prop_set_uint32(DEVICE(&s->fpd.apu.cluster), "cluster-id", 0); | ||
45 | + | ||
46 | for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) { | ||
47 | Object *obj; | ||
48 | |||
49 | - object_initialize_child(OBJECT(s), "apu-cpu[*]", &s->fpd.apu.cpu[i], | ||
50 | + object_initialize_child(OBJECT(&s->fpd.apu.cluster), | ||
51 | + "apu-cpu[*]", &s->fpd.apu.cpu[i], | ||
52 | XLNX_VERSAL_ACPU_TYPE); | ||
53 | obj = OBJECT(&s->fpd.apu.cpu[i]); | ||
54 | if (i) { | ||
55 | @@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s) | ||
56 | &error_abort); | ||
57 | qdev_realize(DEVICE(obj), NULL, &error_fatal); | ||
58 | } | ||
59 | + | ||
60 | + qdev_realize(DEVICE(&s->fpd.apu.cluster), NULL, &error_fatal); | ||
61 | } | ||
62 | |||
63 | static void versal_create_apu_gic(Versal *s, qemu_irq *pic) | ||
64 | -- | ||
65 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: "Edgar E. Iglesias" <edgar.iglesias@amd.com> |
---|---|---|---|
2 | 2 | ||
3 | For both ldnt1 and stnt1, the meaning of the Rn and Rm are different | 3 | Add the Cortex-R5Fs of the Versal RPU (Real-time Processing Unit) |
4 | from ld1 and st1: the vector and integer registers are reversed, and | 4 | subsystem. |
5 | the integer register 31 refers to XZR instead of SP. | ||
6 | 5 | ||
7 | Secondly, the 64-bit version of ldnt1 was being interpreted as | 6 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> |
8 | 32-bit unpacked unscaled offset instead of 64-bit unscaled offset, | 7 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> |
9 | which discarded the upper 32 bits of the address coming from | 8 | Message-id: 20220406174303.2022038-3-edgar.iglesias@xilinx.com |
10 | the vector argument. | ||
11 | |||
12 | Thirdly, validate that the memory element size is in range for the | ||
13 | vector element size for ldnt1. For ld1, we do this via independent | ||
14 | decode patterns, but for ldnt1 we need to do it manually. | ||
15 | |||
16 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/826 | ||
17 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
18 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
19 | Message-id: 20220308031655.240710-1-richard.henderson@linaro.org | ||
20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
21 | --- | 10 | --- |
22 | target/arm/sve.decode | 5 ++- | 11 | include/hw/arm/xlnx-versal.h | 10 ++++++++++ |
23 | target/arm/translate-sve.c | 51 +++++++++++++++++++++++++++++-- | 12 | hw/arm/xlnx-versal-virt.c | 6 +++--- |
24 | tests/tcg/aarch64/test-826.c | 50 ++++++++++++++++++++++++++++++ | 13 | hw/arm/xlnx-versal.c | 36 ++++++++++++++++++++++++++++++++++++ |
25 | tests/tcg/aarch64/Makefile.target | 4 +++ | 14 | 3 files changed, 49 insertions(+), 3 deletions(-) |
26 | tests/tcg/configure.sh | 4 +++ | ||
27 | 5 files changed, 109 insertions(+), 5 deletions(-) | ||
28 | create mode 100644 tests/tcg/aarch64/test-826.c | ||
29 | 15 | ||
30 | diff --git a/target/arm/sve.decode b/target/arm/sve.decode | 16 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h |
31 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
32 | --- a/target/arm/sve.decode | 18 | --- a/include/hw/arm/xlnx-versal.h |
33 | +++ b/target/arm/sve.decode | 19 | +++ b/include/hw/arm/xlnx-versal.h |
34 | @@ -XXX,XX +XXX,XX @@ USDOT_zzzz 01000100 .. 0 ..... 011 110 ..... ..... @rda_rn_rm | 20 | @@ -XXX,XX +XXX,XX @@ |
35 | 21 | OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) | |
36 | ### SVE2 Memory Gather Load Group | 22 | |
37 | 23 | #define XLNX_VERSAL_NR_ACPUS 2 | |
38 | -# SVE2 64-bit gather non-temporal load | 24 | +#define XLNX_VERSAL_NR_RCPUS 2 |
39 | -# (scalar plus unpacked 32-bit unscaled offsets) | 25 | #define XLNX_VERSAL_NR_UARTS 2 |
40 | +# SVE2 64-bit gather non-temporal load (scalar plus 64-bit unscaled offsets) | 26 | #define XLNX_VERSAL_NR_GEMS 2 |
41 | LDNT1_zprz 1100010 msz:2 00 rm:5 1 u:1 0 pg:3 rn:5 rd:5 \ | 27 | #define XLNX_VERSAL_NR_ADMAS 8 |
42 | - &rprr_gather_load xs=0 esz=3 scale=0 ff=0 | 28 | @@ -XXX,XX +XXX,XX @@ struct Versal { |
43 | + &rprr_gather_load xs=2 esz=3 scale=0 ff=0 | 29 | VersalUsb2 usb; |
44 | 30 | } iou; | |
45 | # SVE2 32-bit gather non-temporal load (scalar plus 32-bit unscaled offsets) | 31 | |
46 | LDNT1_zprz 1000010 msz:2 00 rm:5 10 u:1 pg:3 rn:5 rd:5 \ | 32 | + /* Real-time Processing Unit. */ |
47 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | 33 | + struct { |
34 | + MemoryRegion mr; | ||
35 | + MemoryRegion mr_ps_alias; | ||
36 | + | ||
37 | + CPUClusterState cluster; | ||
38 | + ARMCPU cpu[XLNX_VERSAL_NR_RCPUS]; | ||
39 | + } rpu; | ||
40 | + | ||
41 | struct { | ||
42 | qemu_or_irq irq_orgate; | ||
43 | XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; | ||
44 | diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | 45 | index XXXXXXX..XXXXXXX 100644 |
49 | --- a/target/arm/translate-sve.c | 46 | --- a/hw/arm/xlnx-versal-virt.c |
50 | +++ b/target/arm/translate-sve.c | 47 | +++ b/hw/arm/xlnx-versal-virt.c |
51 | @@ -XXX,XX +XXX,XX @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a) | 48 | @@ -XXX,XX +XXX,XX @@ static void versal_virt_machine_class_init(ObjectClass *oc, void *data) |
52 | 49 | ||
53 | static bool trans_LDNT1_zprz(DisasContext *s, arg_LD1_zprz *a) | 50 | mc->desc = "Xilinx Versal Virtual development board"; |
54 | { | 51 | mc->init = versal_virt_init; |
55 | + gen_helper_gvec_mem_scatter *fn = NULL; | 52 | - mc->min_cpus = XLNX_VERSAL_NR_ACPUS; |
56 | + bool be = s->be_data == MO_BE; | 53 | - mc->max_cpus = XLNX_VERSAL_NR_ACPUS; |
57 | + bool mte = s->mte_active[0]; | 54 | - mc->default_cpus = XLNX_VERSAL_NR_ACPUS; |
55 | + mc->min_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS; | ||
56 | + mc->max_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS; | ||
57 | + mc->default_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS; | ||
58 | mc->no_cdrom = true; | ||
59 | mc->default_ram_id = "ddr"; | ||
60 | } | ||
61 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/hw/arm/xlnx-versal.c | ||
64 | +++ b/hw/arm/xlnx-versal.c | ||
65 | @@ -XXX,XX +XXX,XX @@ | ||
66 | #include "hw/sysbus.h" | ||
67 | |||
68 | #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") | ||
69 | +#define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") | ||
70 | #define GEM_REVISION 0x40070106 | ||
71 | |||
72 | #define VERSAL_NUM_PMC_APB_IRQS 3 | ||
73 | @@ -XXX,XX +XXX,XX @@ static void versal_create_apu_gic(Versal *s, qemu_irq *pic) | ||
74 | } | ||
75 | } | ||
76 | |||
77 | +static void versal_create_rpu_cpus(Versal *s) | ||
78 | +{ | ||
79 | + int i; | ||
58 | + | 80 | + |
59 | + if (a->esz < a->msz + !a->u) { | 81 | + object_initialize_child(OBJECT(s), "rpu-cluster", &s->lpd.rpu.cluster, |
60 | + return false; | 82 | + TYPE_CPU_CLUSTER); |
61 | + } | 83 | + qdev_prop_set_uint32(DEVICE(&s->lpd.rpu.cluster), "cluster-id", 1); |
62 | if (!dc_isar_feature(aa64_sve2, s)) { | 84 | + |
63 | return false; | 85 | + for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) { |
64 | } | 86 | + Object *obj; |
65 | - return trans_LD1_zprz(s, a); | 87 | + |
66 | + if (!sve_access_check(s)) { | 88 | + object_initialize_child(OBJECT(&s->lpd.rpu.cluster), |
67 | + return true; | 89 | + "rpu-cpu[*]", &s->lpd.rpu.cpu[i], |
90 | + XLNX_VERSAL_RCPU_TYPE); | ||
91 | + obj = OBJECT(&s->lpd.rpu.cpu[i]); | ||
92 | + object_property_set_bool(obj, "start-powered-off", true, | ||
93 | + &error_abort); | ||
94 | + | ||
95 | + object_property_set_int(obj, "mp-affinity", 0x100 | i, &error_abort); | ||
96 | + object_property_set_int(obj, "core-count", ARRAY_SIZE(s->lpd.rpu.cpu), | ||
97 | + &error_abort); | ||
98 | + object_property_set_link(obj, "memory", OBJECT(&s->lpd.rpu.mr), | ||
99 | + &error_abort); | ||
100 | + qdev_realize(DEVICE(obj), NULL, &error_fatal); | ||
68 | + } | 101 | + } |
69 | + | 102 | + |
70 | + switch (a->esz) { | 103 | + qdev_realize(DEVICE(&s->lpd.rpu.cluster), NULL, &error_fatal); |
71 | + case MO_32: | ||
72 | + fn = gather_load_fn32[mte][be][0][0][a->u][a->msz]; | ||
73 | + break; | ||
74 | + case MO_64: | ||
75 | + fn = gather_load_fn64[mte][be][0][2][a->u][a->msz]; | ||
76 | + break; | ||
77 | + } | ||
78 | + assert(fn != NULL); | ||
79 | + | ||
80 | + do_mem_zpz(s, a->rd, a->pg, a->rn, 0, | ||
81 | + cpu_reg(s, a->rm), a->msz, false, fn); | ||
82 | + return true; | ||
83 | } | ||
84 | |||
85 | /* Indexed by [mte][be][xs][msz]. */ | ||
86 | @@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a) | ||
87 | |||
88 | static bool trans_STNT1_zprz(DisasContext *s, arg_ST1_zprz *a) | ||
89 | { | ||
90 | + gen_helper_gvec_mem_scatter *fn; | ||
91 | + bool be = s->be_data == MO_BE; | ||
92 | + bool mte = s->mte_active[0]; | ||
93 | + | ||
94 | + if (a->esz < a->msz) { | ||
95 | + return false; | ||
96 | + } | ||
97 | if (!dc_isar_feature(aa64_sve2, s)) { | ||
98 | return false; | ||
99 | } | ||
100 | - return trans_ST1_zprz(s, a); | ||
101 | + if (!sve_access_check(s)) { | ||
102 | + return true; | ||
103 | + } | ||
104 | + | ||
105 | + switch (a->esz) { | ||
106 | + case MO_32: | ||
107 | + fn = scatter_store_fn32[mte][be][0][a->msz]; | ||
108 | + break; | ||
109 | + case MO_64: | ||
110 | + fn = scatter_store_fn64[mte][be][2][a->msz]; | ||
111 | + break; | ||
112 | + default: | ||
113 | + g_assert_not_reached(); | ||
114 | + } | ||
115 | + | ||
116 | + do_mem_zpz(s, a->rd, a->pg, a->rn, 0, | ||
117 | + cpu_reg(s, a->rm), a->msz, true, fn); | ||
118 | + return true; | ||
119 | } | ||
120 | |||
121 | /* | ||
122 | diff --git a/tests/tcg/aarch64/test-826.c b/tests/tcg/aarch64/test-826.c | ||
123 | new file mode 100644 | ||
124 | index XXXXXXX..XXXXXXX | ||
125 | --- /dev/null | ||
126 | +++ b/tests/tcg/aarch64/test-826.c | ||
127 | @@ -XXX,XX +XXX,XX @@ | ||
128 | +#include <sys/mman.h> | ||
129 | +#include <unistd.h> | ||
130 | +#include <signal.h> | ||
131 | +#include <stdlib.h> | ||
132 | +#include <stdio.h> | ||
133 | +#include <assert.h> | ||
134 | + | ||
135 | +static void *expected; | ||
136 | + | ||
137 | +void sigsegv(int sig, siginfo_t *info, void *vuc) | ||
138 | +{ | ||
139 | + ucontext_t *uc = vuc; | ||
140 | + | ||
141 | + assert(info->si_addr == expected); | ||
142 | + uc->uc_mcontext.pc += 4; | ||
143 | +} | 104 | +} |
144 | + | 105 | + |
145 | +int main() | 106 | static void versal_create_uarts(Versal *s, qemu_irq *pic) |
146 | +{ | 107 | { |
147 | + struct sigaction sa = { | 108 | int i; |
148 | + .sa_sigaction = sigsegv, | 109 | @@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp) |
149 | + .sa_flags = SA_SIGINFO | 110 | |
150 | + }; | 111 | versal_create_apu_cpus(s); |
151 | + | 112 | versal_create_apu_gic(s, pic); |
152 | + void *page; | 113 | + versal_create_rpu_cpus(s); |
153 | + long ofs; | 114 | versal_create_uarts(s, pic); |
154 | + | 115 | versal_create_usbs(s, pic); |
155 | + if (sigaction(SIGSEGV, &sa, NULL) < 0) { | 116 | versal_create_gems(s, pic); |
156 | + perror("sigaction"); | 117 | @@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp) |
157 | + return EXIT_FAILURE; | 118 | |
158 | + } | 119 | memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0); |
159 | + | 120 | memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0); |
160 | + page = mmap(0, getpagesize(), PROT_NONE, MAP_PRIVATE | MAP_ANON, -1, 0); | 121 | + memory_region_add_subregion_overlap(&s->lpd.rpu.mr, 0, |
161 | + if (page == MAP_FAILED) { | 122 | + &s->lpd.rpu.mr_ps_alias, 0); |
162 | + perror("mmap"); | 123 | } |
163 | + return EXIT_FAILURE; | 124 | |
164 | + } | 125 | static void versal_init(Object *obj) |
165 | + | 126 | @@ -XXX,XX +XXX,XX @@ static void versal_init(Object *obj) |
166 | + ofs = 0x124; | 127 | Versal *s = XLNX_VERSAL(obj); |
167 | + expected = page + ofs; | 128 | |
168 | + | 129 | memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX); |
169 | + asm("ptrue p0.d, vl1\n\t" | 130 | + memory_region_init(&s->lpd.rpu.mr, obj, "mr-rpu", UINT64_MAX); |
170 | + "dup z0.d, %0\n\t" | 131 | memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX); |
171 | + "ldnt1h {z1.d}, p0/z, [z0.d, %1]\n\t" | 132 | + memory_region_init_alias(&s->lpd.rpu.mr_ps_alias, OBJECT(s), |
172 | + "dup z1.d, %1\n\t" | 133 | + "mr-rpu-ps-alias", &s->mr_ps, 0, UINT64_MAX); |
173 | + "ldnt1h {z0.d}, p0/z, [z1.d, %0]" | 134 | } |
174 | + : : "r"(page), "r"(ofs) : "v0", "v1"); | 135 | |
175 | + | 136 | static Property versal_properties[] = { |
176 | + return EXIT_SUCCESS; | ||
177 | +} | ||
178 | diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target | ||
179 | index XXXXXXX..XXXXXXX 100644 | ||
180 | --- a/tests/tcg/aarch64/Makefile.target | ||
181 | +++ b/tests/tcg/aarch64/Makefile.target | ||
182 | @@ -XXX,XX +XXX,XX @@ run-gdbstub-sve-ioctls: sve-ioctls | ||
183 | |||
184 | EXTRA_RUNS += run-gdbstub-sysregs run-gdbstub-sve-ioctls | ||
185 | endif | ||
186 | +endif | ||
187 | |||
188 | +ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_SVE2),) | ||
189 | +AARCH64_TESTS += test-826 | ||
190 | +test-826: CFLAGS+=-march=armv8.1-a+sve2 | ||
191 | endif | ||
192 | |||
193 | TESTS += $(AARCH64_TESTS) | ||
194 | diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh | ||
195 | index XXXXXXX..XXXXXXX 100755 | ||
196 | --- a/tests/tcg/configure.sh | ||
197 | +++ b/tests/tcg/configure.sh | ||
198 | @@ -XXX,XX +XXX,XX @@ for target in $target_list; do | ||
199 | -march=armv8.1-a+sve -o $TMPE $TMPC; then | ||
200 | echo "CROSS_CC_HAS_SVE=y" >> $config_target_mak | ||
201 | fi | ||
202 | + if do_compiler "$target_compiler" $target_compiler_cflags \ | ||
203 | + -march=armv8.1-a+sve2 -o $TMPE $TMPC; then | ||
204 | + echo "CROSS_CC_HAS_SVE2=y" >> $config_target_mak | ||
205 | + fi | ||
206 | if do_compiler "$target_compiler" $target_compiler_cflags \ | ||
207 | -march=armv8.3-a -o $TMPE $TMPC; then | ||
208 | echo "CROSS_CC_HAS_ARMV8_3=y" >> $config_target_mak | ||
209 | -- | 137 | -- |
210 | 2.25.1 | 138 | 2.25.1 | diff view generated by jsdifflib |
1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | From: "Edgar E. Iglesias" <edgar.iglesias@amd.com> |
---|---|---|---|
2 | 2 | ||
3 | Add a model of the Xilinx ZynqMP CRF. At the moment this | 3 | Add a model of the Xilinx Versal CRL. |
4 | is mostly a stub model. | ||
5 | 4 | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Frederic Konrad <fkonrad@amd.com> |
8 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 7 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> |
9 | Message-id: 20220316164645.2303510-4-edgar.iglesias@gmail.com | 8 | Message-id: 20220406174303.2022038-4-edgar.iglesias@xilinx.com |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 10 | --- |
12 | include/hw/misc/xlnx-zynqmp-crf.h | 211 ++++++++++++++++++++++++ | 11 | include/hw/misc/xlnx-versal-crl.h | 235 +++++++++++++++++ |
13 | hw/misc/xlnx-zynqmp-crf.c | 266 ++++++++++++++++++++++++++++++ | 12 | hw/misc/xlnx-versal-crl.c | 421 ++++++++++++++++++++++++++++++ |
14 | hw/misc/meson.build | 1 + | 13 | hw/misc/meson.build | 1 + |
15 | 3 files changed, 478 insertions(+) | 14 | 3 files changed, 657 insertions(+) |
16 | create mode 100644 include/hw/misc/xlnx-zynqmp-crf.h | 15 | create mode 100644 include/hw/misc/xlnx-versal-crl.h |
17 | create mode 100644 hw/misc/xlnx-zynqmp-crf.c | 16 | create mode 100644 hw/misc/xlnx-versal-crl.c |
18 | 17 | ||
19 | diff --git a/include/hw/misc/xlnx-zynqmp-crf.h b/include/hw/misc/xlnx-zynqmp-crf.h | 18 | diff --git a/include/hw/misc/xlnx-versal-crl.h b/include/hw/misc/xlnx-versal-crl.h |
20 | new file mode 100644 | 19 | new file mode 100644 |
21 | index XXXXXXX..XXXXXXX | 20 | index XXXXXXX..XXXXXXX |
22 | --- /dev/null | 21 | --- /dev/null |
23 | +++ b/include/hw/misc/xlnx-zynqmp-crf.h | 22 | +++ b/include/hw/misc/xlnx-versal-crl.h |
24 | @@ -XXX,XX +XXX,XX @@ | 23 | @@ -XXX,XX +XXX,XX @@ |
25 | +/* | 24 | +/* |
26 | + * QEMU model of the CRF - Clock Reset FPD. | 25 | + * QEMU model of the Clock-Reset-LPD (CRL). |
27 | + * | 26 | + * |
28 | + * Copyright (c) 2022 Xilinx Inc. | 27 | + * Copyright (c) 2022 Xilinx Inc. |
29 | + * SPDX-License-Identifier: GPL-2.0-or-later | 28 | + * SPDX-License-Identifier: GPL-2.0-or-later |
29 | + * | ||
30 | + * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 30 | + * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com> |
31 | + */ | 31 | + */ |
32 | +#ifndef HW_MISC_XLNX_ZYNQMP_CRF_H | 32 | +#ifndef HW_MISC_XLNX_VERSAL_CRL_H |
33 | +#define HW_MISC_XLNX_ZYNQMP_CRF_H | 33 | +#define HW_MISC_XLNX_VERSAL_CRL_H |
34 | + | 34 | + |
35 | +#include "hw/sysbus.h" | 35 | +#include "hw/sysbus.h" |
36 | +#include "hw/register.h" | 36 | +#include "hw/register.h" |
37 | + | 37 | +#include "target/arm/cpu.h" |
38 | +#define TYPE_XLNX_ZYNQMP_CRF "xlnx.zynqmp_crf" | 38 | + |
39 | +OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPCRF, XLNX_ZYNQMP_CRF) | 39 | +#define TYPE_XLNX_VERSAL_CRL "xlnx,versal-crl" |
40 | +OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL) | ||
40 | + | 41 | + |
41 | +REG32(ERR_CTRL, 0x0) | 42 | +REG32(ERR_CTRL, 0x0) |
42 | + FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1) | 43 | + FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1) |
43 | +REG32(IR_STATUS, 0x4) | 44 | +REG32(IR_STATUS, 0x4) |
44 | + FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1) | 45 | + FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1) |
45 | +REG32(IR_MASK, 0x8) | 46 | +REG32(IR_MASK, 0x8) |
46 | + FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1) | 47 | + FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1) |
47 | +REG32(IR_ENABLE, 0xc) | 48 | +REG32(IR_ENABLE, 0xc) |
48 | + FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1) | 49 | + FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1) |
49 | +REG32(IR_DISABLE, 0x10) | 50 | +REG32(IR_DISABLE, 0x10) |
50 | + FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1) | 51 | + FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1) |
51 | +REG32(CRF_WPROT, 0x1c) | 52 | +REG32(WPROT, 0x1c) |
52 | + FIELD(CRF_WPROT, ACTIVE, 0, 1) | 53 | + FIELD(WPROT, ACTIVE, 0, 1) |
53 | +REG32(APLL_CTRL, 0x20) | 54 | +REG32(PLL_CLK_OTHER_DMN, 0x20) |
54 | + FIELD(APLL_CTRL, POST_SRC, 24, 3) | 55 | + FIELD(PLL_CLK_OTHER_DMN, APLL_BYPASS, 0, 1) |
55 | + FIELD(APLL_CTRL, PRE_SRC, 20, 3) | 56 | +REG32(RPLL_CTRL, 0x40) |
56 | + FIELD(APLL_CTRL, CLKOUTDIV, 17, 1) | 57 | + FIELD(RPLL_CTRL, POST_SRC, 24, 3) |
57 | + FIELD(APLL_CTRL, DIV2, 16, 1) | 58 | + FIELD(RPLL_CTRL, PRE_SRC, 20, 3) |
58 | + FIELD(APLL_CTRL, FBDIV, 8, 7) | 59 | + FIELD(RPLL_CTRL, CLKOUTDIV, 16, 2) |
59 | + FIELD(APLL_CTRL, BYPASS, 3, 1) | 60 | + FIELD(RPLL_CTRL, FBDIV, 8, 8) |
60 | + FIELD(APLL_CTRL, RESET, 0, 1) | 61 | + FIELD(RPLL_CTRL, BYPASS, 3, 1) |
61 | +REG32(APLL_CFG, 0x24) | 62 | + FIELD(RPLL_CTRL, RESET, 0, 1) |
62 | + FIELD(APLL_CFG, LOCK_DLY, 25, 7) | 63 | +REG32(RPLL_CFG, 0x44) |
63 | + FIELD(APLL_CFG, LOCK_CNT, 13, 10) | 64 | + FIELD(RPLL_CFG, LOCK_DLY, 25, 7) |
64 | + FIELD(APLL_CFG, LFHF, 10, 2) | 65 | + FIELD(RPLL_CFG, LOCK_CNT, 13, 10) |
65 | + FIELD(APLL_CFG, CP, 5, 4) | 66 | + FIELD(RPLL_CFG, LFHF, 10, 2) |
66 | + FIELD(APLL_CFG, RES, 0, 4) | 67 | + FIELD(RPLL_CFG, CP, 5, 4) |
67 | +REG32(APLL_FRAC_CFG, 0x28) | 68 | + FIELD(RPLL_CFG, RES, 0, 4) |
68 | + FIELD(APLL_FRAC_CFG, ENABLED, 31, 1) | 69 | +REG32(RPLL_FRAC_CFG, 0x48) |
69 | + FIELD(APLL_FRAC_CFG, SEED, 22, 3) | 70 | + FIELD(RPLL_FRAC_CFG, ENABLED, 31, 1) |
70 | + FIELD(APLL_FRAC_CFG, ALGRTHM, 19, 1) | 71 | + FIELD(RPLL_FRAC_CFG, SEED, 22, 3) |
71 | + FIELD(APLL_FRAC_CFG, ORDER, 18, 1) | 72 | + FIELD(RPLL_FRAC_CFG, ALGRTHM, 19, 1) |
72 | + FIELD(APLL_FRAC_CFG, DATA, 0, 16) | 73 | + FIELD(RPLL_FRAC_CFG, ORDER, 18, 1) |
73 | +REG32(DPLL_CTRL, 0x2c) | 74 | + FIELD(RPLL_FRAC_CFG, DATA, 0, 16) |
74 | + FIELD(DPLL_CTRL, POST_SRC, 24, 3) | 75 | +REG32(PLL_STATUS, 0x50) |
75 | + FIELD(DPLL_CTRL, PRE_SRC, 20, 3) | 76 | + FIELD(PLL_STATUS, RPLL_STABLE, 2, 1) |
76 | + FIELD(DPLL_CTRL, CLKOUTDIV, 17, 1) | 77 | + FIELD(PLL_STATUS, RPLL_LOCK, 0, 1) |
77 | + FIELD(DPLL_CTRL, DIV2, 16, 1) | 78 | +REG32(RPLL_TO_XPD_CTRL, 0x100) |
78 | + FIELD(DPLL_CTRL, FBDIV, 8, 7) | 79 | + FIELD(RPLL_TO_XPD_CTRL, CLKACT, 25, 1) |
79 | + FIELD(DPLL_CTRL, BYPASS, 3, 1) | 80 | + FIELD(RPLL_TO_XPD_CTRL, DIVISOR0, 8, 10) |
80 | + FIELD(DPLL_CTRL, RESET, 0, 1) | 81 | +REG32(LPD_TOP_SWITCH_CTRL, 0x104) |
81 | +REG32(DPLL_CFG, 0x30) | 82 | + FIELD(LPD_TOP_SWITCH_CTRL, CLKACT_ADMA, 26, 1) |
82 | + FIELD(DPLL_CFG, LOCK_DLY, 25, 7) | 83 | + FIELD(LPD_TOP_SWITCH_CTRL, CLKACT, 25, 1) |
83 | + FIELD(DPLL_CFG, LOCK_CNT, 13, 10) | 84 | + FIELD(LPD_TOP_SWITCH_CTRL, DIVISOR0, 8, 10) |
84 | + FIELD(DPLL_CFG, LFHF, 10, 2) | 85 | + FIELD(LPD_TOP_SWITCH_CTRL, SRCSEL, 0, 3) |
85 | + FIELD(DPLL_CFG, CP, 5, 4) | 86 | +REG32(LPD_LSBUS_CTRL, 0x108) |
86 | + FIELD(DPLL_CFG, RES, 0, 4) | 87 | + FIELD(LPD_LSBUS_CTRL, CLKACT, 25, 1) |
87 | +REG32(DPLL_FRAC_CFG, 0x34) | 88 | + FIELD(LPD_LSBUS_CTRL, DIVISOR0, 8, 10) |
88 | + FIELD(DPLL_FRAC_CFG, ENABLED, 31, 1) | 89 | + FIELD(LPD_LSBUS_CTRL, SRCSEL, 0, 3) |
89 | + FIELD(DPLL_FRAC_CFG, SEED, 22, 3) | 90 | +REG32(CPU_R5_CTRL, 0x10c) |
90 | + FIELD(DPLL_FRAC_CFG, ALGRTHM, 19, 1) | 91 | + FIELD(CPU_R5_CTRL, CLKACT_OCM2, 28, 1) |
91 | + FIELD(DPLL_FRAC_CFG, ORDER, 18, 1) | 92 | + FIELD(CPU_R5_CTRL, CLKACT_OCM, 27, 1) |
92 | + FIELD(DPLL_FRAC_CFG, DATA, 0, 16) | 93 | + FIELD(CPU_R5_CTRL, CLKACT_CORE, 26, 1) |
93 | +REG32(VPLL_CTRL, 0x38) | 94 | + FIELD(CPU_R5_CTRL, CLKACT, 25, 1) |
94 | + FIELD(VPLL_CTRL, POST_SRC, 24, 3) | 95 | + FIELD(CPU_R5_CTRL, DIVISOR0, 8, 10) |
95 | + FIELD(VPLL_CTRL, PRE_SRC, 20, 3) | 96 | + FIELD(CPU_R5_CTRL, SRCSEL, 0, 3) |
96 | + FIELD(VPLL_CTRL, CLKOUTDIV, 17, 1) | 97 | +REG32(IOU_SWITCH_CTRL, 0x114) |
97 | + FIELD(VPLL_CTRL, DIV2, 16, 1) | 98 | + FIELD(IOU_SWITCH_CTRL, CLKACT, 25, 1) |
98 | + FIELD(VPLL_CTRL, FBDIV, 8, 7) | 99 | + FIELD(IOU_SWITCH_CTRL, DIVISOR0, 8, 10) |
99 | + FIELD(VPLL_CTRL, BYPASS, 3, 1) | 100 | + FIELD(IOU_SWITCH_CTRL, SRCSEL, 0, 3) |
100 | + FIELD(VPLL_CTRL, RESET, 0, 1) | 101 | +REG32(GEM0_REF_CTRL, 0x118) |
101 | +REG32(VPLL_CFG, 0x3c) | 102 | + FIELD(GEM0_REF_CTRL, CLKACT_RX, 27, 1) |
102 | + FIELD(VPLL_CFG, LOCK_DLY, 25, 7) | 103 | + FIELD(GEM0_REF_CTRL, CLKACT_TX, 26, 1) |
103 | + FIELD(VPLL_CFG, LOCK_CNT, 13, 10) | 104 | + FIELD(GEM0_REF_CTRL, CLKACT, 25, 1) |
104 | + FIELD(VPLL_CFG, LFHF, 10, 2) | 105 | + FIELD(GEM0_REF_CTRL, DIVISOR0, 8, 10) |
105 | + FIELD(VPLL_CFG, CP, 5, 4) | 106 | + FIELD(GEM0_REF_CTRL, SRCSEL, 0, 3) |
106 | + FIELD(VPLL_CFG, RES, 0, 4) | 107 | +REG32(GEM1_REF_CTRL, 0x11c) |
107 | +REG32(VPLL_FRAC_CFG, 0x40) | 108 | + FIELD(GEM1_REF_CTRL, CLKACT_RX, 27, 1) |
108 | + FIELD(VPLL_FRAC_CFG, ENABLED, 31, 1) | 109 | + FIELD(GEM1_REF_CTRL, CLKACT_TX, 26, 1) |
109 | + FIELD(VPLL_FRAC_CFG, SEED, 22, 3) | 110 | + FIELD(GEM1_REF_CTRL, CLKACT, 25, 1) |
110 | + FIELD(VPLL_FRAC_CFG, ALGRTHM, 19, 1) | 111 | + FIELD(GEM1_REF_CTRL, DIVISOR0, 8, 10) |
111 | + FIELD(VPLL_FRAC_CFG, ORDER, 18, 1) | 112 | + FIELD(GEM1_REF_CTRL, SRCSEL, 0, 3) |
112 | + FIELD(VPLL_FRAC_CFG, DATA, 0, 16) | 113 | +REG32(GEM_TSU_REF_CTRL, 0x120) |
113 | +REG32(PLL_STATUS, 0x44) | 114 | + FIELD(GEM_TSU_REF_CTRL, CLKACT, 25, 1) |
114 | + FIELD(PLL_STATUS, VPLL_STABLE, 5, 1) | 115 | + FIELD(GEM_TSU_REF_CTRL, DIVISOR0, 8, 10) |
115 | + FIELD(PLL_STATUS, DPLL_STABLE, 4, 1) | 116 | + FIELD(GEM_TSU_REF_CTRL, SRCSEL, 0, 3) |
116 | + FIELD(PLL_STATUS, APLL_STABLE, 3, 1) | 117 | +REG32(USB0_BUS_REF_CTRL, 0x124) |
117 | + FIELD(PLL_STATUS, VPLL_LOCK, 2, 1) | 118 | + FIELD(USB0_BUS_REF_CTRL, CLKACT, 25, 1) |
118 | + FIELD(PLL_STATUS, DPLL_LOCK, 1, 1) | 119 | + FIELD(USB0_BUS_REF_CTRL, DIVISOR0, 8, 10) |
119 | + FIELD(PLL_STATUS, APLL_LOCK, 0, 1) | 120 | + FIELD(USB0_BUS_REF_CTRL, SRCSEL, 0, 3) |
120 | +REG32(APLL_TO_LPD_CTRL, 0x48) | 121 | +REG32(UART0_REF_CTRL, 0x128) |
121 | + FIELD(APLL_TO_LPD_CTRL, DIVISOR0, 8, 6) | 122 | + FIELD(UART0_REF_CTRL, CLKACT, 25, 1) |
122 | +REG32(DPLL_TO_LPD_CTRL, 0x4c) | 123 | + FIELD(UART0_REF_CTRL, DIVISOR0, 8, 10) |
123 | + FIELD(DPLL_TO_LPD_CTRL, DIVISOR0, 8, 6) | 124 | + FIELD(UART0_REF_CTRL, SRCSEL, 0, 3) |
124 | +REG32(VPLL_TO_LPD_CTRL, 0x50) | 125 | +REG32(UART1_REF_CTRL, 0x12c) |
125 | + FIELD(VPLL_TO_LPD_CTRL, DIVISOR0, 8, 6) | 126 | + FIELD(UART1_REF_CTRL, CLKACT, 25, 1) |
126 | +REG32(ACPU_CTRL, 0x60) | 127 | + FIELD(UART1_REF_CTRL, DIVISOR0, 8, 10) |
127 | + FIELD(ACPU_CTRL, CLKACT_HALF, 25, 1) | 128 | + FIELD(UART1_REF_CTRL, SRCSEL, 0, 3) |
128 | + FIELD(ACPU_CTRL, CLKACT_FULL, 24, 1) | 129 | +REG32(SPI0_REF_CTRL, 0x130) |
129 | + FIELD(ACPU_CTRL, DIVISOR0, 8, 6) | 130 | + FIELD(SPI0_REF_CTRL, CLKACT, 25, 1) |
130 | + FIELD(ACPU_CTRL, SRCSEL, 0, 3) | 131 | + FIELD(SPI0_REF_CTRL, DIVISOR0, 8, 10) |
131 | +REG32(DBG_TRACE_CTRL, 0x64) | 132 | + FIELD(SPI0_REF_CTRL, SRCSEL, 0, 3) |
132 | + FIELD(DBG_TRACE_CTRL, CLKACT, 24, 1) | 133 | +REG32(SPI1_REF_CTRL, 0x134) |
133 | + FIELD(DBG_TRACE_CTRL, DIVISOR0, 8, 6) | 134 | + FIELD(SPI1_REF_CTRL, CLKACT, 25, 1) |
134 | + FIELD(DBG_TRACE_CTRL, SRCSEL, 0, 3) | 135 | + FIELD(SPI1_REF_CTRL, DIVISOR0, 8, 10) |
135 | +REG32(DBG_FPD_CTRL, 0x68) | 136 | + FIELD(SPI1_REF_CTRL, SRCSEL, 0, 3) |
136 | + FIELD(DBG_FPD_CTRL, CLKACT, 24, 1) | 137 | +REG32(CAN0_REF_CTRL, 0x138) |
137 | + FIELD(DBG_FPD_CTRL, DIVISOR0, 8, 6) | 138 | + FIELD(CAN0_REF_CTRL, CLKACT, 25, 1) |
138 | + FIELD(DBG_FPD_CTRL, SRCSEL, 0, 3) | 139 | + FIELD(CAN0_REF_CTRL, DIVISOR0, 8, 10) |
139 | +REG32(DP_VIDEO_REF_CTRL, 0x70) | 140 | + FIELD(CAN0_REF_CTRL, SRCSEL, 0, 3) |
140 | + FIELD(DP_VIDEO_REF_CTRL, CLKACT, 24, 1) | 141 | +REG32(CAN1_REF_CTRL, 0x13c) |
141 | + FIELD(DP_VIDEO_REF_CTRL, DIVISOR1, 16, 6) | 142 | + FIELD(CAN1_REF_CTRL, CLKACT, 25, 1) |
142 | + FIELD(DP_VIDEO_REF_CTRL, DIVISOR0, 8, 6) | 143 | + FIELD(CAN1_REF_CTRL, DIVISOR0, 8, 10) |
143 | + FIELD(DP_VIDEO_REF_CTRL, SRCSEL, 0, 3) | 144 | + FIELD(CAN1_REF_CTRL, SRCSEL, 0, 3) |
144 | +REG32(DP_AUDIO_REF_CTRL, 0x74) | 145 | +REG32(I2C0_REF_CTRL, 0x140) |
145 | + FIELD(DP_AUDIO_REF_CTRL, CLKACT, 24, 1) | 146 | + FIELD(I2C0_REF_CTRL, CLKACT, 25, 1) |
146 | + FIELD(DP_AUDIO_REF_CTRL, DIVISOR1, 16, 6) | 147 | + FIELD(I2C0_REF_CTRL, DIVISOR0, 8, 10) |
147 | + FIELD(DP_AUDIO_REF_CTRL, DIVISOR0, 8, 6) | 148 | + FIELD(I2C0_REF_CTRL, SRCSEL, 0, 3) |
148 | + FIELD(DP_AUDIO_REF_CTRL, SRCSEL, 0, 3) | 149 | +REG32(I2C1_REF_CTRL, 0x144) |
149 | +REG32(DP_STC_REF_CTRL, 0x7c) | 150 | + FIELD(I2C1_REF_CTRL, CLKACT, 25, 1) |
150 | + FIELD(DP_STC_REF_CTRL, CLKACT, 24, 1) | 151 | + FIELD(I2C1_REF_CTRL, DIVISOR0, 8, 10) |
151 | + FIELD(DP_STC_REF_CTRL, DIVISOR1, 16, 6) | 152 | + FIELD(I2C1_REF_CTRL, SRCSEL, 0, 3) |
152 | + FIELD(DP_STC_REF_CTRL, DIVISOR0, 8, 6) | 153 | +REG32(DBG_LPD_CTRL, 0x148) |
153 | + FIELD(DP_STC_REF_CTRL, SRCSEL, 0, 3) | 154 | + FIELD(DBG_LPD_CTRL, CLKACT, 25, 1) |
154 | +REG32(DDR_CTRL, 0x80) | 155 | + FIELD(DBG_LPD_CTRL, DIVISOR0, 8, 10) |
155 | + FIELD(DDR_CTRL, CLKACT, 24, 1) | 156 | + FIELD(DBG_LPD_CTRL, SRCSEL, 0, 3) |
156 | + FIELD(DDR_CTRL, DIVISOR0, 8, 6) | 157 | +REG32(TIMESTAMP_REF_CTRL, 0x14c) |
157 | + FIELD(DDR_CTRL, SRCSEL, 0, 3) | 158 | + FIELD(TIMESTAMP_REF_CTRL, CLKACT, 25, 1) |
158 | +REG32(GPU_REF_CTRL, 0x84) | 159 | + FIELD(TIMESTAMP_REF_CTRL, DIVISOR0, 8, 10) |
159 | + FIELD(GPU_REF_CTRL, PP1_CLKACT, 26, 1) | 160 | + FIELD(TIMESTAMP_REF_CTRL, SRCSEL, 0, 3) |
160 | + FIELD(GPU_REF_CTRL, PP0_CLKACT, 25, 1) | 161 | +REG32(CRL_SAFETY_CHK, 0x150) |
161 | + FIELD(GPU_REF_CTRL, CLKACT, 24, 1) | 162 | +REG32(PSM_REF_CTRL, 0x154) |
162 | + FIELD(GPU_REF_CTRL, DIVISOR0, 8, 6) | 163 | + FIELD(PSM_REF_CTRL, DIVISOR0, 8, 10) |
163 | + FIELD(GPU_REF_CTRL, SRCSEL, 0, 3) | 164 | + FIELD(PSM_REF_CTRL, SRCSEL, 0, 3) |
164 | +REG32(SATA_REF_CTRL, 0xa0) | 165 | +REG32(DBG_TSTMP_CTRL, 0x158) |
165 | + FIELD(SATA_REF_CTRL, CLKACT, 24, 1) | 166 | + FIELD(DBG_TSTMP_CTRL, CLKACT, 25, 1) |
166 | + FIELD(SATA_REF_CTRL, DIVISOR0, 8, 6) | 167 | + FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 10) |
167 | + FIELD(SATA_REF_CTRL, SRCSEL, 0, 3) | ||
168 | +REG32(PCIE_REF_CTRL, 0xb4) | ||
169 | + FIELD(PCIE_REF_CTRL, CLKACT, 24, 1) | ||
170 | + FIELD(PCIE_REF_CTRL, DIVISOR0, 8, 6) | ||
171 | + FIELD(PCIE_REF_CTRL, SRCSEL, 0, 3) | ||
172 | +REG32(GDMA_REF_CTRL, 0xb8) | ||
173 | + FIELD(GDMA_REF_CTRL, CLKACT, 24, 1) | ||
174 | + FIELD(GDMA_REF_CTRL, DIVISOR0, 8, 6) | ||
175 | + FIELD(GDMA_REF_CTRL, SRCSEL, 0, 3) | ||
176 | +REG32(DPDMA_REF_CTRL, 0xbc) | ||
177 | + FIELD(DPDMA_REF_CTRL, CLKACT, 24, 1) | ||
178 | + FIELD(DPDMA_REF_CTRL, DIVISOR0, 8, 6) | ||
179 | + FIELD(DPDMA_REF_CTRL, SRCSEL, 0, 3) | ||
180 | +REG32(TOPSW_MAIN_CTRL, 0xc0) | ||
181 | + FIELD(TOPSW_MAIN_CTRL, CLKACT, 24, 1) | ||
182 | + FIELD(TOPSW_MAIN_CTRL, DIVISOR0, 8, 6) | ||
183 | + FIELD(TOPSW_MAIN_CTRL, SRCSEL, 0, 3) | ||
184 | +REG32(TOPSW_LSBUS_CTRL, 0xc4) | ||
185 | + FIELD(TOPSW_LSBUS_CTRL, CLKACT, 24, 1) | ||
186 | + FIELD(TOPSW_LSBUS_CTRL, DIVISOR0, 8, 6) | ||
187 | + FIELD(TOPSW_LSBUS_CTRL, SRCSEL, 0, 3) | ||
188 | +REG32(DBG_TSTMP_CTRL, 0xf8) | ||
189 | + FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 6) | ||
190 | + FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3) | 168 | + FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3) |
191 | +REG32(RST_FPD_TOP, 0x100) | 169 | +REG32(CPM_TOPSW_REF_CTRL, 0x15c) |
192 | + FIELD(RST_FPD_TOP, PCIE_CFG_RESET, 19, 1) | 170 | + FIELD(CPM_TOPSW_REF_CTRL, CLKACT, 25, 1) |
193 | + FIELD(RST_FPD_TOP, PCIE_BRIDGE_RESET, 18, 1) | 171 | + FIELD(CPM_TOPSW_REF_CTRL, DIVISOR0, 8, 10) |
194 | + FIELD(RST_FPD_TOP, PCIE_CTRL_RESET, 17, 1) | 172 | + FIELD(CPM_TOPSW_REF_CTRL, SRCSEL, 0, 3) |
195 | + FIELD(RST_FPD_TOP, DP_RESET, 16, 1) | 173 | +REG32(USB3_DUAL_REF_CTRL, 0x160) |
196 | + FIELD(RST_FPD_TOP, SWDT_RESET, 15, 1) | 174 | + FIELD(USB3_DUAL_REF_CTRL, CLKACT, 25, 1) |
197 | + FIELD(RST_FPD_TOP, AFI_FM5_RESET, 12, 1) | 175 | + FIELD(USB3_DUAL_REF_CTRL, DIVISOR0, 8, 10) |
198 | + FIELD(RST_FPD_TOP, AFI_FM4_RESET, 11, 1) | 176 | + FIELD(USB3_DUAL_REF_CTRL, SRCSEL, 0, 3) |
199 | + FIELD(RST_FPD_TOP, AFI_FM3_RESET, 10, 1) | 177 | +REG32(RST_CPU_R5, 0x300) |
200 | + FIELD(RST_FPD_TOP, AFI_FM2_RESET, 9, 1) | 178 | + FIELD(RST_CPU_R5, RESET_PGE, 4, 1) |
201 | + FIELD(RST_FPD_TOP, AFI_FM1_RESET, 8, 1) | 179 | + FIELD(RST_CPU_R5, RESET_AMBA, 2, 1) |
202 | + FIELD(RST_FPD_TOP, AFI_FM0_RESET, 7, 1) | 180 | + FIELD(RST_CPU_R5, RESET_CPU1, 1, 1) |
203 | + FIELD(RST_FPD_TOP, GDMA_RESET, 6, 1) | 181 | + FIELD(RST_CPU_R5, RESET_CPU0, 0, 1) |
204 | + FIELD(RST_FPD_TOP, GPU_PP1_RESET, 5, 1) | 182 | +REG32(RST_ADMA, 0x304) |
205 | + FIELD(RST_FPD_TOP, GPU_PP0_RESET, 4, 1) | 183 | + FIELD(RST_ADMA, RESET, 0, 1) |
206 | + FIELD(RST_FPD_TOP, GPU_RESET, 3, 1) | 184 | +REG32(RST_GEM0, 0x308) |
207 | + FIELD(RST_FPD_TOP, GT_RESET, 2, 1) | 185 | + FIELD(RST_GEM0, RESET, 0, 1) |
208 | + FIELD(RST_FPD_TOP, SATA_RESET, 1, 1) | 186 | +REG32(RST_GEM1, 0x30c) |
209 | +REG32(RST_FPD_APU, 0x104) | 187 | + FIELD(RST_GEM1, RESET, 0, 1) |
210 | + FIELD(RST_FPD_APU, ACPU3_PWRON_RESET, 13, 1) | 188 | +REG32(RST_SPARE, 0x310) |
211 | + FIELD(RST_FPD_APU, ACPU2_PWRON_RESET, 12, 1) | 189 | + FIELD(RST_SPARE, RESET, 0, 1) |
212 | + FIELD(RST_FPD_APU, ACPU1_PWRON_RESET, 11, 1) | 190 | +REG32(RST_USB0, 0x314) |
213 | + FIELD(RST_FPD_APU, ACPU0_PWRON_RESET, 10, 1) | 191 | + FIELD(RST_USB0, RESET, 0, 1) |
214 | + FIELD(RST_FPD_APU, APU_L2_RESET, 8, 1) | 192 | +REG32(RST_UART0, 0x318) |
215 | + FIELD(RST_FPD_APU, ACPU3_RESET, 3, 1) | 193 | + FIELD(RST_UART0, RESET, 0, 1) |
216 | + FIELD(RST_FPD_APU, ACPU2_RESET, 2, 1) | 194 | +REG32(RST_UART1, 0x31c) |
217 | + FIELD(RST_FPD_APU, ACPU1_RESET, 1, 1) | 195 | + FIELD(RST_UART1, RESET, 0, 1) |
218 | + FIELD(RST_FPD_APU, ACPU0_RESET, 0, 1) | 196 | +REG32(RST_SPI0, 0x320) |
219 | +REG32(RST_DDR_SS, 0x108) | 197 | + FIELD(RST_SPI0, RESET, 0, 1) |
220 | + FIELD(RST_DDR_SS, DDR_RESET, 3, 1) | 198 | +REG32(RST_SPI1, 0x324) |
221 | + FIELD(RST_DDR_SS, APM_RESET, 2, 1) | 199 | + FIELD(RST_SPI1, RESET, 0, 1) |
222 | + | 200 | +REG32(RST_CAN0, 0x328) |
223 | +#define CRF_R_MAX (R_RST_DDR_SS + 1) | 201 | + FIELD(RST_CAN0, RESET, 0, 1) |
224 | + | 202 | +REG32(RST_CAN1, 0x32c) |
225 | +struct XlnxZynqMPCRF { | 203 | + FIELD(RST_CAN1, RESET, 0, 1) |
204 | +REG32(RST_I2C0, 0x330) | ||
205 | + FIELD(RST_I2C0, RESET, 0, 1) | ||
206 | +REG32(RST_I2C1, 0x334) | ||
207 | + FIELD(RST_I2C1, RESET, 0, 1) | ||
208 | +REG32(RST_DBG_LPD, 0x338) | ||
209 | + FIELD(RST_DBG_LPD, RPU_DBG1_RESET, 5, 1) | ||
210 | + FIELD(RST_DBG_LPD, RPU_DBG0_RESET, 4, 1) | ||
211 | + FIELD(RST_DBG_LPD, RESET_HSDP, 1, 1) | ||
212 | + FIELD(RST_DBG_LPD, RESET, 0, 1) | ||
213 | +REG32(RST_GPIO, 0x33c) | ||
214 | + FIELD(RST_GPIO, RESET, 0, 1) | ||
215 | +REG32(RST_TTC, 0x344) | ||
216 | + FIELD(RST_TTC, TTC3_RESET, 3, 1) | ||
217 | + FIELD(RST_TTC, TTC2_RESET, 2, 1) | ||
218 | + FIELD(RST_TTC, TTC1_RESET, 1, 1) | ||
219 | + FIELD(RST_TTC, TTC0_RESET, 0, 1) | ||
220 | +REG32(RST_TIMESTAMP, 0x348) | ||
221 | + FIELD(RST_TIMESTAMP, RESET, 0, 1) | ||
222 | +REG32(RST_SWDT, 0x34c) | ||
223 | + FIELD(RST_SWDT, RESET, 0, 1) | ||
224 | +REG32(RST_OCM, 0x350) | ||
225 | + FIELD(RST_OCM, RESET, 0, 1) | ||
226 | +REG32(RST_IPI, 0x354) | ||
227 | + FIELD(RST_IPI, RESET, 0, 1) | ||
228 | +REG32(RST_SYSMON, 0x358) | ||
229 | + FIELD(RST_SYSMON, SEQ_RST, 1, 1) | ||
230 | + FIELD(RST_SYSMON, CFG_RST, 0, 1) | ||
231 | +REG32(RST_FPD, 0x360) | ||
232 | + FIELD(RST_FPD, SRST, 1, 1) | ||
233 | + FIELD(RST_FPD, POR, 0, 1) | ||
234 | +REG32(PSM_RST_MODE, 0x370) | ||
235 | + FIELD(PSM_RST_MODE, WAKEUP, 2, 1) | ||
236 | + FIELD(PSM_RST_MODE, RST_MODE, 0, 2) | ||
237 | + | ||
238 | +#define CRL_R_MAX (R_PSM_RST_MODE + 1) | ||
239 | + | ||
240 | +#define RPU_MAX_CPU 2 | ||
241 | + | ||
242 | +struct XlnxVersalCRL { | ||
226 | + SysBusDevice parent_obj; | 243 | + SysBusDevice parent_obj; |
227 | + MemoryRegion iomem; | 244 | + qemu_irq irq; |
228 | + qemu_irq irq_ir; | 245 | + |
246 | + struct { | ||
247 | + ARMCPU *cpu_r5[RPU_MAX_CPU]; | ||
248 | + DeviceState *adma[8]; | ||
249 | + DeviceState *uart[2]; | ||
250 | + DeviceState *gem[2]; | ||
251 | + DeviceState *usb; | ||
252 | + } cfg; | ||
229 | + | 253 | + |
230 | + RegisterInfoArray *reg_array; | 254 | + RegisterInfoArray *reg_array; |
231 | + uint32_t regs[CRF_R_MAX]; | 255 | + uint32_t regs[CRL_R_MAX]; |
232 | + RegisterInfo regs_info[CRF_R_MAX]; | 256 | + RegisterInfo regs_info[CRL_R_MAX]; |
233 | +}; | 257 | +}; |
234 | + | ||
235 | +#endif | 258 | +#endif |
236 | diff --git a/hw/misc/xlnx-zynqmp-crf.c b/hw/misc/xlnx-zynqmp-crf.c | 259 | diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c |
237 | new file mode 100644 | 260 | new file mode 100644 |
238 | index XXXXXXX..XXXXXXX | 261 | index XXXXXXX..XXXXXXX |
239 | --- /dev/null | 262 | --- /dev/null |
240 | +++ b/hw/misc/xlnx-zynqmp-crf.c | 263 | +++ b/hw/misc/xlnx-versal-crl.c |
241 | @@ -XXX,XX +XXX,XX @@ | 264 | @@ -XXX,XX +XXX,XX @@ |
242 | +/* | 265 | +/* |
243 | + * QEMU model of the CRF - Clock Reset FPD. | 266 | + * QEMU model of the Clock-Reset-LPD (CRL). |
244 | + * | 267 | + * |
245 | + * Copyright (c) 2022 Xilinx Inc. | 268 | + * Copyright (c) 2022 Advanced Micro Devices, Inc. |
246 | + * SPDX-License-Identifier: GPL-2.0-or-later | 269 | + * SPDX-License-Identifier: GPL-2.0-or-later |
247 | + * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 270 | + * |
271 | + * Written by Edgar E. Iglesias <edgar.iglesias@amd.com> | ||
248 | + */ | 272 | + */ |
249 | + | 273 | + |
250 | +#include "qemu/osdep.h" | 274 | +#include "qemu/osdep.h" |
275 | +#include "qapi/error.h" | ||
276 | +#include "qemu/log.h" | ||
277 | +#include "qemu/bitops.h" | ||
278 | +#include "migration/vmstate.h" | ||
279 | +#include "hw/qdev-properties.h" | ||
251 | +#include "hw/sysbus.h" | 280 | +#include "hw/sysbus.h" |
281 | +#include "hw/irq.h" | ||
252 | +#include "hw/register.h" | 282 | +#include "hw/register.h" |
253 | +#include "qemu/bitops.h" | 283 | +#include "hw/resettable.h" |
254 | +#include "qemu/log.h" | 284 | + |
255 | +#include "migration/vmstate.h" | ||
256 | +#include "hw/irq.h" | ||
257 | +#include "hw/misc/xlnx-zynqmp-crf.h" | ||
258 | +#include "target/arm/arm-powerctl.h" | 285 | +#include "target/arm/arm-powerctl.h" |
259 | + | 286 | +#include "hw/misc/xlnx-versal-crl.h" |
260 | +#ifndef XLNX_ZYNQMP_CRF_ERR_DEBUG | 287 | + |
261 | +#define XLNX_ZYNQMP_CRF_ERR_DEBUG 0 | 288 | +#ifndef XLNX_VERSAL_CRL_ERR_DEBUG |
289 | +#define XLNX_VERSAL_CRL_ERR_DEBUG 0 | ||
262 | +#endif | 290 | +#endif |
263 | + | 291 | + |
264 | +#define CRF_MAX_CPU 4 | 292 | +static void crl_update_irq(XlnxVersalCRL *s) |
265 | + | ||
266 | +static void ir_update_irq(XlnxZynqMPCRF *s) | ||
267 | +{ | 293 | +{ |
268 | + bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK]; | 294 | + bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK]; |
269 | + qemu_set_irq(s->irq_ir, pending); | 295 | + qemu_set_irq(s->irq, pending); |
270 | +} | 296 | +} |
271 | + | 297 | + |
272 | +static void ir_status_postw(RegisterInfo *reg, uint64_t val64) | 298 | +static void crl_status_postw(RegisterInfo *reg, uint64_t val64) |
273 | +{ | 299 | +{ |
274 | + XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque); | 300 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); |
275 | + ir_update_irq(s); | 301 | + crl_update_irq(s); |
276 | +} | 302 | +} |
277 | + | 303 | + |
278 | +static uint64_t ir_enable_prew(RegisterInfo *reg, uint64_t val64) | 304 | +static uint64_t crl_enable_prew(RegisterInfo *reg, uint64_t val64) |
279 | +{ | 305 | +{ |
280 | + XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque); | 306 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); |
281 | + uint32_t val = val64; | 307 | + uint32_t val = val64; |
282 | + | 308 | + |
283 | + s->regs[R_IR_MASK] &= ~val; | 309 | + s->regs[R_IR_MASK] &= ~val; |
284 | + ir_update_irq(s); | 310 | + crl_update_irq(s); |
285 | + return 0; | 311 | + return 0; |
286 | +} | 312 | +} |
287 | + | 313 | + |
288 | +static uint64_t ir_disable_prew(RegisterInfo *reg, uint64_t val64) | 314 | +static uint64_t crl_disable_prew(RegisterInfo *reg, uint64_t val64) |
289 | +{ | 315 | +{ |
290 | + XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque); | 316 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); |
291 | + uint32_t val = val64; | 317 | + uint32_t val = val64; |
292 | + | 318 | + |
293 | + s->regs[R_IR_MASK] |= val; | 319 | + s->regs[R_IR_MASK] |= val; |
294 | + ir_update_irq(s); | 320 | + crl_update_irq(s); |
295 | + return 0; | 321 | + return 0; |
296 | +} | 322 | +} |
297 | + | 323 | + |
298 | +static uint64_t rst_fpd_apu_prew(RegisterInfo *reg, uint64_t val64) | 324 | +static void crl_reset_dev(XlnxVersalCRL *s, DeviceState *dev, |
299 | +{ | 325 | + bool rst_old, bool rst_new) |
300 | + XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque); | 326 | +{ |
301 | + uint32_t val = val64; | 327 | + device_cold_reset(dev); |
302 | + uint32_t val_old = s->regs[R_RST_FPD_APU]; | 328 | +} |
303 | + unsigned int i; | 329 | + |
304 | + | 330 | +static void crl_reset_cpu(XlnxVersalCRL *s, ARMCPU *armcpu, |
305 | + for (i = 0; i < CRF_MAX_CPU; i++) { | 331 | + bool rst_old, bool rst_new) |
306 | + uint32_t mask = (1 << (R_RST_FPD_APU_ACPU0_RESET_SHIFT + i)); | 332 | +{ |
307 | + | 333 | + if (rst_new) { |
308 | + if ((val ^ val_old) & mask) { | 334 | + arm_set_cpu_off(armcpu->mp_affinity); |
309 | + if (val & mask) { | 335 | + } else { |
310 | + arm_set_cpu_off(i); | 336 | + arm_set_cpu_on_and_reset(armcpu->mp_affinity); |
311 | + } else { | 337 | + } |
312 | + arm_set_cpu_on_and_reset(i); | 338 | +} |
313 | + } | 339 | + |
314 | + } | 340 | +#define REGFIELD_RESET(type, s, reg, f, new_val, dev) { \ |
315 | + } | 341 | + bool old_f = ARRAY_FIELD_EX32((s)->regs, reg, f); \ |
342 | + bool new_f = FIELD_EX32(new_val, reg, f); \ | ||
343 | + \ | ||
344 | + /* Detect edges. */ \ | ||
345 | + if (dev && old_f != new_f) { \ | ||
346 | + crl_reset_ ## type(s, dev, old_f, new_f); \ | ||
347 | + } \ | ||
348 | +} | ||
349 | + | ||
350 | +static uint64_t crl_rst_r5_prew(RegisterInfo *reg, uint64_t val64) | ||
351 | +{ | ||
352 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
353 | + | ||
354 | + REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU0, val64, s->cfg.cpu_r5[0]); | ||
355 | + REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU1, val64, s->cfg.cpu_r5[1]); | ||
316 | + return val64; | 356 | + return val64; |
317 | +} | 357 | +} |
318 | + | 358 | + |
319 | +static const RegisterAccessInfo crf_regs_info[] = { | 359 | +static uint64_t crl_rst_adma_prew(RegisterInfo *reg, uint64_t val64) |
360 | +{ | ||
361 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
362 | + int i; | ||
363 | + | ||
364 | + /* A single register fans out to all ADMA reset inputs. */ | ||
365 | + for (i = 0; i < ARRAY_SIZE(s->cfg.adma); i++) { | ||
366 | + REGFIELD_RESET(dev, s, RST_ADMA, RESET, val64, s->cfg.adma[i]); | ||
367 | + } | ||
368 | + return val64; | ||
369 | +} | ||
370 | + | ||
371 | +static uint64_t crl_rst_uart0_prew(RegisterInfo *reg, uint64_t val64) | ||
372 | +{ | ||
373 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
374 | + | ||
375 | + REGFIELD_RESET(dev, s, RST_UART0, RESET, val64, s->cfg.uart[0]); | ||
376 | + return val64; | ||
377 | +} | ||
378 | + | ||
379 | +static uint64_t crl_rst_uart1_prew(RegisterInfo *reg, uint64_t val64) | ||
380 | +{ | ||
381 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
382 | + | ||
383 | + REGFIELD_RESET(dev, s, RST_UART1, RESET, val64, s->cfg.uart[1]); | ||
384 | + return val64; | ||
385 | +} | ||
386 | + | ||
387 | +static uint64_t crl_rst_gem0_prew(RegisterInfo *reg, uint64_t val64) | ||
388 | +{ | ||
389 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
390 | + | ||
391 | + REGFIELD_RESET(dev, s, RST_GEM0, RESET, val64, s->cfg.gem[0]); | ||
392 | + return val64; | ||
393 | +} | ||
394 | + | ||
395 | +static uint64_t crl_rst_gem1_prew(RegisterInfo *reg, uint64_t val64) | ||
396 | +{ | ||
397 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
398 | + | ||
399 | + REGFIELD_RESET(dev, s, RST_GEM1, RESET, val64, s->cfg.gem[1]); | ||
400 | + return val64; | ||
401 | +} | ||
402 | + | ||
403 | +static uint64_t crl_rst_usb_prew(RegisterInfo *reg, uint64_t val64) | ||
404 | +{ | ||
405 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
406 | + | ||
407 | + REGFIELD_RESET(dev, s, RST_USB0, RESET, val64, s->cfg.usb); | ||
408 | + return val64; | ||
409 | +} | ||
410 | + | ||
411 | +static const RegisterAccessInfo crl_regs_info[] = { | ||
320 | + { .name = "ERR_CTRL", .addr = A_ERR_CTRL, | 412 | + { .name = "ERR_CTRL", .addr = A_ERR_CTRL, |
321 | + },{ .name = "IR_STATUS", .addr = A_IR_STATUS, | 413 | + },{ .name = "IR_STATUS", .addr = A_IR_STATUS, |
322 | + .w1c = 0x1, | 414 | + .w1c = 0x1, |
323 | + .post_write = ir_status_postw, | 415 | + .post_write = crl_status_postw, |
324 | + },{ .name = "IR_MASK", .addr = A_IR_MASK, | 416 | + },{ .name = "IR_MASK", .addr = A_IR_MASK, |
325 | + .reset = 0x1, | 417 | + .reset = 0x1, |
326 | + .ro = 0x1, | 418 | + .ro = 0x1, |
327 | + },{ .name = "IR_ENABLE", .addr = A_IR_ENABLE, | 419 | + },{ .name = "IR_ENABLE", .addr = A_IR_ENABLE, |
328 | + .pre_write = ir_enable_prew, | 420 | + .pre_write = crl_enable_prew, |
329 | + },{ .name = "IR_DISABLE", .addr = A_IR_DISABLE, | 421 | + },{ .name = "IR_DISABLE", .addr = A_IR_DISABLE, |
330 | + .pre_write = ir_disable_prew, | 422 | + .pre_write = crl_disable_prew, |
331 | + },{ .name = "CRF_WPROT", .addr = A_CRF_WPROT, | 423 | + },{ .name = "WPROT", .addr = A_WPROT, |
332 | + },{ .name = "APLL_CTRL", .addr = A_APLL_CTRL, | 424 | + },{ .name = "PLL_CLK_OTHER_DMN", .addr = A_PLL_CLK_OTHER_DMN, |
333 | + .reset = 0x12c09, | 425 | + .reset = 0x1, |
334 | + .rsvd = 0xf88c80f6, | 426 | + .rsvd = 0xe, |
335 | + },{ .name = "APLL_CFG", .addr = A_APLL_CFG, | 427 | + },{ .name = "RPLL_CTRL", .addr = A_RPLL_CTRL, |
428 | + .reset = 0x24809, | ||
429 | + .rsvd = 0xf88c00f6, | ||
430 | + },{ .name = "RPLL_CFG", .addr = A_RPLL_CFG, | ||
431 | + .reset = 0x2000000, | ||
336 | + .rsvd = 0x1801210, | 432 | + .rsvd = 0x1801210, |
337 | + },{ .name = "APLL_FRAC_CFG", .addr = A_APLL_FRAC_CFG, | 433 | + },{ .name = "RPLL_FRAC_CFG", .addr = A_RPLL_FRAC_CFG, |
338 | + .rsvd = 0x7e330000, | ||
339 | + },{ .name = "DPLL_CTRL", .addr = A_DPLL_CTRL, | ||
340 | + .reset = 0x2c09, | ||
341 | + .rsvd = 0xf88c80f6, | ||
342 | + },{ .name = "DPLL_CFG", .addr = A_DPLL_CFG, | ||
343 | + .rsvd = 0x1801210, | ||
344 | + },{ .name = "DPLL_FRAC_CFG", .addr = A_DPLL_FRAC_CFG, | ||
345 | + .rsvd = 0x7e330000, | ||
346 | + },{ .name = "VPLL_CTRL", .addr = A_VPLL_CTRL, | ||
347 | + .reset = 0x12809, | ||
348 | + .rsvd = 0xf88c80f6, | ||
349 | + },{ .name = "VPLL_CFG", .addr = A_VPLL_CFG, | ||
350 | + .rsvd = 0x1801210, | ||
351 | + },{ .name = "VPLL_FRAC_CFG", .addr = A_VPLL_FRAC_CFG, | ||
352 | + .rsvd = 0x7e330000, | 434 | + .rsvd = 0x7e330000, |
353 | + },{ .name = "PLL_STATUS", .addr = A_PLL_STATUS, | 435 | + },{ .name = "PLL_STATUS", .addr = A_PLL_STATUS, |
354 | + .reset = 0x3f, | 436 | + .reset = R_PLL_STATUS_RPLL_STABLE_MASK | |
355 | + .rsvd = 0xc0, | 437 | + R_PLL_STATUS_RPLL_LOCK_MASK, |
356 | + .ro = 0x3f, | 438 | + .rsvd = 0xfa, |
357 | + },{ .name = "APLL_TO_LPD_CTRL", .addr = A_APLL_TO_LPD_CTRL, | 439 | + .ro = 0x5, |
358 | + .reset = 0x400, | 440 | + },{ .name = "RPLL_TO_XPD_CTRL", .addr = A_RPLL_TO_XPD_CTRL, |
359 | + .rsvd = 0xc0ff, | 441 | + .reset = 0x2000100, |
360 | + },{ .name = "DPLL_TO_LPD_CTRL", .addr = A_DPLL_TO_LPD_CTRL, | 442 | + .rsvd = 0xfdfc00ff, |
361 | + .reset = 0x400, | 443 | + },{ .name = "LPD_TOP_SWITCH_CTRL", .addr = A_LPD_TOP_SWITCH_CTRL, |
362 | + .rsvd = 0xc0ff, | 444 | + .reset = 0x6000300, |
363 | + },{ .name = "VPLL_TO_LPD_CTRL", .addr = A_VPLL_TO_LPD_CTRL, | 445 | + .rsvd = 0xf9fc00f8, |
364 | + .reset = 0x400, | 446 | + },{ .name = "LPD_LSBUS_CTRL", .addr = A_LPD_LSBUS_CTRL, |
365 | + .rsvd = 0xc0ff, | 447 | + .reset = 0x2000800, |
366 | + },{ .name = "ACPU_CTRL", .addr = A_ACPU_CTRL, | 448 | + .rsvd = 0xfdfc00f8, |
367 | + .reset = 0x3000400, | 449 | + },{ .name = "CPU_R5_CTRL", .addr = A_CPU_R5_CTRL, |
368 | + .rsvd = 0xfcffc0f8, | 450 | + .reset = 0xe000300, |
369 | + },{ .name = "DBG_TRACE_CTRL", .addr = A_DBG_TRACE_CTRL, | 451 | + .rsvd = 0xe1fc00f8, |
370 | + .reset = 0x2500, | 452 | + },{ .name = "IOU_SWITCH_CTRL", .addr = A_IOU_SWITCH_CTRL, |
371 | + .rsvd = 0xfeffc0f8, | 453 | + .reset = 0x2000500, |
372 | + },{ .name = "DBG_FPD_CTRL", .addr = A_DBG_FPD_CTRL, | 454 | + .rsvd = 0xfdfc00f8, |
373 | + .reset = 0x1002500, | 455 | + },{ .name = "GEM0_REF_CTRL", .addr = A_GEM0_REF_CTRL, |
374 | + .rsvd = 0xfeffc0f8, | 456 | + .reset = 0xe000a00, |
375 | + },{ .name = "DP_VIDEO_REF_CTRL", .addr = A_DP_VIDEO_REF_CTRL, | 457 | + .rsvd = 0xf1fc00f8, |
376 | + .reset = 0x1002300, | 458 | + },{ .name = "GEM1_REF_CTRL", .addr = A_GEM1_REF_CTRL, |
377 | + .rsvd = 0xfec0c0f8, | 459 | + .reset = 0xe000a00, |
378 | + },{ .name = "DP_AUDIO_REF_CTRL", .addr = A_DP_AUDIO_REF_CTRL, | 460 | + .rsvd = 0xf1fc00f8, |
379 | + .reset = 0x1032300, | 461 | + },{ .name = "GEM_TSU_REF_CTRL", .addr = A_GEM_TSU_REF_CTRL, |
380 | + .rsvd = 0xfec0c0f8, | 462 | + .reset = 0x300, |
381 | + },{ .name = "DP_STC_REF_CTRL", .addr = A_DP_STC_REF_CTRL, | 463 | + .rsvd = 0xfdfc00f8, |
382 | + .reset = 0x1203200, | 464 | + },{ .name = "USB0_BUS_REF_CTRL", .addr = A_USB0_BUS_REF_CTRL, |
383 | + .rsvd = 0xfec0c0f8, | 465 | + .reset = 0x2001900, |
384 | + },{ .name = "DDR_CTRL", .addr = A_DDR_CTRL, | 466 | + .rsvd = 0xfdfc00f8, |
385 | + .reset = 0x1000500, | 467 | + },{ .name = "UART0_REF_CTRL", .addr = A_UART0_REF_CTRL, |
386 | + .rsvd = 0xfeffc0f8, | 468 | + .reset = 0xc00, |
387 | + },{ .name = "GPU_REF_CTRL", .addr = A_GPU_REF_CTRL, | 469 | + .rsvd = 0xfdfc00f8, |
388 | + .reset = 0x1500, | 470 | + },{ .name = "UART1_REF_CTRL", .addr = A_UART1_REF_CTRL, |
389 | + .rsvd = 0xf8ffc0f8, | 471 | + .reset = 0xc00, |
390 | + },{ .name = "SATA_REF_CTRL", .addr = A_SATA_REF_CTRL, | 472 | + .rsvd = 0xfdfc00f8, |
391 | + .reset = 0x1001600, | 473 | + },{ .name = "SPI0_REF_CTRL", .addr = A_SPI0_REF_CTRL, |
392 | + .rsvd = 0xfeffc0f8, | 474 | + .reset = 0x600, |
393 | + },{ .name = "PCIE_REF_CTRL", .addr = A_PCIE_REF_CTRL, | 475 | + .rsvd = 0xfdfc00f8, |
394 | + .reset = 0x1500, | 476 | + },{ .name = "SPI1_REF_CTRL", .addr = A_SPI1_REF_CTRL, |
395 | + .rsvd = 0xfeffc0f8, | 477 | + .reset = 0x600, |
396 | + },{ .name = "GDMA_REF_CTRL", .addr = A_GDMA_REF_CTRL, | 478 | + .rsvd = 0xfdfc00f8, |
397 | + .reset = 0x1000500, | 479 | + },{ .name = "CAN0_REF_CTRL", .addr = A_CAN0_REF_CTRL, |
398 | + .rsvd = 0xfeffc0f8, | 480 | + .reset = 0xc00, |
399 | + },{ .name = "DPDMA_REF_CTRL", .addr = A_DPDMA_REF_CTRL, | 481 | + .rsvd = 0xfdfc00f8, |
400 | + .reset = 0x1000500, | 482 | + },{ .name = "CAN1_REF_CTRL", .addr = A_CAN1_REF_CTRL, |
401 | + .rsvd = 0xfeffc0f8, | 483 | + .reset = 0xc00, |
402 | + },{ .name = "TOPSW_MAIN_CTRL", .addr = A_TOPSW_MAIN_CTRL, | 484 | + .rsvd = 0xfdfc00f8, |
403 | + .reset = 0x1000400, | 485 | + },{ .name = "I2C0_REF_CTRL", .addr = A_I2C0_REF_CTRL, |
404 | + .rsvd = 0xfeffc0f8, | 486 | + .reset = 0xc00, |
405 | + },{ .name = "TOPSW_LSBUS_CTRL", .addr = A_TOPSW_LSBUS_CTRL, | 487 | + .rsvd = 0xfdfc00f8, |
406 | + .reset = 0x1000800, | 488 | + },{ .name = "I2C1_REF_CTRL", .addr = A_I2C1_REF_CTRL, |
407 | + .rsvd = 0xfeffc0f8, | 489 | + .reset = 0xc00, |
490 | + .rsvd = 0xfdfc00f8, | ||
491 | + },{ .name = "DBG_LPD_CTRL", .addr = A_DBG_LPD_CTRL, | ||
492 | + .reset = 0x300, | ||
493 | + .rsvd = 0xfdfc00f8, | ||
494 | + },{ .name = "TIMESTAMP_REF_CTRL", .addr = A_TIMESTAMP_REF_CTRL, | ||
495 | + .reset = 0x2000c00, | ||
496 | + .rsvd = 0xfdfc00f8, | ||
497 | + },{ .name = "CRL_SAFETY_CHK", .addr = A_CRL_SAFETY_CHK, | ||
498 | + },{ .name = "PSM_REF_CTRL", .addr = A_PSM_REF_CTRL, | ||
499 | + .reset = 0xf04, | ||
500 | + .rsvd = 0xfffc00f8, | ||
408 | + },{ .name = "DBG_TSTMP_CTRL", .addr = A_DBG_TSTMP_CTRL, | 501 | + },{ .name = "DBG_TSTMP_CTRL", .addr = A_DBG_TSTMP_CTRL, |
409 | + .reset = 0xa00, | 502 | + .reset = 0x300, |
410 | + .rsvd = 0xffffc0f8, | 503 | + .rsvd = 0xfdfc00f8, |
411 | + }, | 504 | + },{ .name = "CPM_TOPSW_REF_CTRL", .addr = A_CPM_TOPSW_REF_CTRL, |
412 | + { .name = "RST_FPD_TOP", .addr = A_RST_FPD_TOP, | 505 | + .reset = 0x300, |
413 | + .reset = 0xf9ffe, | 506 | + .rsvd = 0xfdfc00f8, |
414 | + .rsvd = 0xf06001, | 507 | + },{ .name = "USB3_DUAL_REF_CTRL", .addr = A_USB3_DUAL_REF_CTRL, |
415 | + },{ .name = "RST_FPD_APU", .addr = A_RST_FPD_APU, | 508 | + .reset = 0x3c00, |
416 | + .reset = 0x3d0f, | 509 | + .rsvd = 0xfdfc00f8, |
417 | + .rsvd = 0xc2f0, | 510 | + },{ .name = "RST_CPU_R5", .addr = A_RST_CPU_R5, |
418 | + .pre_write = rst_fpd_apu_prew, | 511 | + .reset = 0x17, |
419 | + },{ .name = "RST_DDR_SS", .addr = A_RST_DDR_SS, | 512 | + .rsvd = 0x8, |
513 | + .pre_write = crl_rst_r5_prew, | ||
514 | + },{ .name = "RST_ADMA", .addr = A_RST_ADMA, | ||
515 | + .reset = 0x1, | ||
516 | + .pre_write = crl_rst_adma_prew, | ||
517 | + },{ .name = "RST_GEM0", .addr = A_RST_GEM0, | ||
518 | + .reset = 0x1, | ||
519 | + .pre_write = crl_rst_gem0_prew, | ||
520 | + },{ .name = "RST_GEM1", .addr = A_RST_GEM1, | ||
521 | + .reset = 0x1, | ||
522 | + .pre_write = crl_rst_gem1_prew, | ||
523 | + },{ .name = "RST_SPARE", .addr = A_RST_SPARE, | ||
524 | + .reset = 0x1, | ||
525 | + },{ .name = "RST_USB0", .addr = A_RST_USB0, | ||
526 | + .reset = 0x1, | ||
527 | + .pre_write = crl_rst_usb_prew, | ||
528 | + },{ .name = "RST_UART0", .addr = A_RST_UART0, | ||
529 | + .reset = 0x1, | ||
530 | + .pre_write = crl_rst_uart0_prew, | ||
531 | + },{ .name = "RST_UART1", .addr = A_RST_UART1, | ||
532 | + .reset = 0x1, | ||
533 | + .pre_write = crl_rst_uart1_prew, | ||
534 | + },{ .name = "RST_SPI0", .addr = A_RST_SPI0, | ||
535 | + .reset = 0x1, | ||
536 | + },{ .name = "RST_SPI1", .addr = A_RST_SPI1, | ||
537 | + .reset = 0x1, | ||
538 | + },{ .name = "RST_CAN0", .addr = A_RST_CAN0, | ||
539 | + .reset = 0x1, | ||
540 | + },{ .name = "RST_CAN1", .addr = A_RST_CAN1, | ||
541 | + .reset = 0x1, | ||
542 | + },{ .name = "RST_I2C0", .addr = A_RST_I2C0, | ||
543 | + .reset = 0x1, | ||
544 | + },{ .name = "RST_I2C1", .addr = A_RST_I2C1, | ||
545 | + .reset = 0x1, | ||
546 | + },{ .name = "RST_DBG_LPD", .addr = A_RST_DBG_LPD, | ||
547 | + .reset = 0x33, | ||
548 | + .rsvd = 0xcc, | ||
549 | + },{ .name = "RST_GPIO", .addr = A_RST_GPIO, | ||
550 | + .reset = 0x1, | ||
551 | + },{ .name = "RST_TTC", .addr = A_RST_TTC, | ||
420 | + .reset = 0xf, | 552 | + .reset = 0xf, |
421 | + .rsvd = 0xf3, | 553 | + },{ .name = "RST_TIMESTAMP", .addr = A_RST_TIMESTAMP, |
554 | + .reset = 0x1, | ||
555 | + },{ .name = "RST_SWDT", .addr = A_RST_SWDT, | ||
556 | + .reset = 0x1, | ||
557 | + },{ .name = "RST_OCM", .addr = A_RST_OCM, | ||
558 | + },{ .name = "RST_IPI", .addr = A_RST_IPI, | ||
559 | + },{ .name = "RST_FPD", .addr = A_RST_FPD, | ||
560 | + .reset = 0x3, | ||
561 | + },{ .name = "PSM_RST_MODE", .addr = A_PSM_RST_MODE, | ||
562 | + .reset = 0x1, | ||
563 | + .rsvd = 0xf8, | ||
422 | + } | 564 | + } |
423 | +}; | 565 | +}; |
424 | + | 566 | + |
425 | +static void crf_reset_enter(Object *obj, ResetType type) | 567 | +static void crl_reset_enter(Object *obj, ResetType type) |
426 | +{ | 568 | +{ |
427 | + XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj); | 569 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj); |
428 | + unsigned int i; | 570 | + unsigned int i; |
429 | + | 571 | + |
430 | + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { | 572 | + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { |
431 | + register_reset(&s->regs_info[i]); | 573 | + register_reset(&s->regs_info[i]); |
432 | + } | 574 | + } |
433 | +} | 575 | +} |
434 | + | 576 | + |
435 | +static void crf_reset_hold(Object *obj) | 577 | +static void crl_reset_hold(Object *obj) |
436 | +{ | 578 | +{ |
437 | + XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj); | 579 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj); |
438 | + ir_update_irq(s); | 580 | + |
439 | +} | 581 | + crl_update_irq(s); |
440 | + | 582 | +} |
441 | +static const MemoryRegionOps crf_ops = { | 583 | + |
584 | +static const MemoryRegionOps crl_ops = { | ||
442 | + .read = register_read_memory, | 585 | + .read = register_read_memory, |
443 | + .write = register_write_memory, | 586 | + .write = register_write_memory, |
444 | + .endianness = DEVICE_LITTLE_ENDIAN, | 587 | + .endianness = DEVICE_LITTLE_ENDIAN, |
445 | + .valid = { | 588 | + .valid = { |
446 | + .min_access_size = 4, | 589 | + .min_access_size = 4, |
447 | + .max_access_size = 4, | 590 | + .max_access_size = 4, |
448 | + }, | 591 | + }, |
449 | +}; | 592 | +}; |
450 | + | 593 | + |
451 | +static void crf_init(Object *obj) | 594 | +static void crl_init(Object *obj) |
452 | +{ | 595 | +{ |
453 | + XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj); | 596 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj); |
454 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | 597 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
598 | + int i; | ||
455 | + | 599 | + |
456 | + s->reg_array = | 600 | + s->reg_array = |
457 | + register_init_block32(DEVICE(obj), crf_regs_info, | 601 | + register_init_block32(DEVICE(obj), crl_regs_info, |
458 | + ARRAY_SIZE(crf_regs_info), | 602 | + ARRAY_SIZE(crl_regs_info), |
459 | + s->regs_info, s->regs, | 603 | + s->regs_info, s->regs, |
460 | + &crf_ops, | 604 | + &crl_ops, |
461 | + XLNX_ZYNQMP_CRF_ERR_DEBUG, | 605 | + XLNX_VERSAL_CRL_ERR_DEBUG, |
462 | + CRF_R_MAX * 4); | 606 | + CRL_R_MAX * 4); |
463 | + sysbus_init_mmio(sbd, &s->reg_array->mem); | 607 | + sysbus_init_mmio(sbd, &s->reg_array->mem); |
464 | + sysbus_init_irq(sbd, &s->irq_ir); | 608 | + sysbus_init_irq(sbd, &s->irq); |
465 | +} | 609 | + |
466 | + | 610 | + for (i = 0; i < ARRAY_SIZE(s->cfg.cpu_r5); ++i) { |
467 | +static void crf_finalize(Object *obj) | 611 | + object_property_add_link(obj, "cpu_r5[*]", TYPE_ARM_CPU, |
468 | +{ | 612 | + (Object **)&s->cfg.cpu_r5[i], |
469 | + XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj); | 613 | + qdev_prop_allow_set_link_before_realize, |
614 | + OBJ_PROP_LINK_STRONG); | ||
615 | + } | ||
616 | + | ||
617 | + for (i = 0; i < ARRAY_SIZE(s->cfg.adma); ++i) { | ||
618 | + object_property_add_link(obj, "adma[*]", TYPE_DEVICE, | ||
619 | + (Object **)&s->cfg.adma[i], | ||
620 | + qdev_prop_allow_set_link_before_realize, | ||
621 | + OBJ_PROP_LINK_STRONG); | ||
622 | + } | ||
623 | + | ||
624 | + for (i = 0; i < ARRAY_SIZE(s->cfg.uart); ++i) { | ||
625 | + object_property_add_link(obj, "uart[*]", TYPE_DEVICE, | ||
626 | + (Object **)&s->cfg.uart[i], | ||
627 | + qdev_prop_allow_set_link_before_realize, | ||
628 | + OBJ_PROP_LINK_STRONG); | ||
629 | + } | ||
630 | + | ||
631 | + for (i = 0; i < ARRAY_SIZE(s->cfg.gem); ++i) { | ||
632 | + object_property_add_link(obj, "gem[*]", TYPE_DEVICE, | ||
633 | + (Object **)&s->cfg.gem[i], | ||
634 | + qdev_prop_allow_set_link_before_realize, | ||
635 | + OBJ_PROP_LINK_STRONG); | ||
636 | + } | ||
637 | + | ||
638 | + object_property_add_link(obj, "usb", TYPE_DEVICE, | ||
639 | + (Object **)&s->cfg.gem[i], | ||
640 | + qdev_prop_allow_set_link_before_realize, | ||
641 | + OBJ_PROP_LINK_STRONG); | ||
642 | +} | ||
643 | + | ||
644 | +static void crl_finalize(Object *obj) | ||
645 | +{ | ||
646 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj); | ||
470 | + register_finalize_block(s->reg_array); | 647 | + register_finalize_block(s->reg_array); |
471 | +} | 648 | +} |
472 | + | 649 | + |
473 | +static const VMStateDescription vmstate_crf = { | 650 | +static const VMStateDescription vmstate_crl = { |
474 | + .name = TYPE_XLNX_ZYNQMP_CRF, | 651 | + .name = TYPE_XLNX_VERSAL_CRL, |
475 | + .version_id = 1, | 652 | + .version_id = 1, |
476 | + .minimum_version_id = 1, | 653 | + .minimum_version_id = 1, |
477 | + .fields = (VMStateField[]) { | 654 | + .fields = (VMStateField[]) { |
478 | + VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPCRF, CRF_R_MAX), | 655 | + VMSTATE_UINT32_ARRAY(regs, XlnxVersalCRL, CRL_R_MAX), |
479 | + VMSTATE_END_OF_LIST(), | 656 | + VMSTATE_END_OF_LIST(), |
480 | + } | 657 | + } |
481 | +}; | 658 | +}; |
482 | + | 659 | + |
483 | +static void crf_class_init(ObjectClass *klass, void *data) | 660 | +static void crl_class_init(ObjectClass *klass, void *data) |
484 | +{ | 661 | +{ |
485 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | 662 | + ResettableClass *rc = RESETTABLE_CLASS(klass); |
486 | + DeviceClass *dc = DEVICE_CLASS(klass); | 663 | + DeviceClass *dc = DEVICE_CLASS(klass); |
487 | + | 664 | + |
488 | + dc->vmsd = &vmstate_crf; | 665 | + dc->vmsd = &vmstate_crl; |
489 | + rc->phases.enter = crf_reset_enter; | 666 | + |
490 | + rc->phases.hold = crf_reset_hold; | 667 | + rc->phases.enter = crl_reset_enter; |
491 | +} | 668 | + rc->phases.hold = crl_reset_hold; |
492 | + | 669 | +} |
493 | +static const TypeInfo crf_info = { | 670 | + |
494 | + .name = TYPE_XLNX_ZYNQMP_CRF, | 671 | +static const TypeInfo crl_info = { |
495 | + .parent = TYPE_SYS_BUS_DEVICE, | 672 | + .name = TYPE_XLNX_VERSAL_CRL, |
496 | + .instance_size = sizeof(XlnxZynqMPCRF), | 673 | + .parent = TYPE_SYS_BUS_DEVICE, |
497 | + .class_init = crf_class_init, | 674 | + .instance_size = sizeof(XlnxVersalCRL), |
498 | + .instance_init = crf_init, | 675 | + .class_init = crl_class_init, |
499 | + .instance_finalize = crf_finalize, | 676 | + .instance_init = crl_init, |
677 | + .instance_finalize = crl_finalize, | ||
500 | +}; | 678 | +}; |
501 | + | 679 | + |
502 | +static void crf_register_types(void) | 680 | +static void crl_register_types(void) |
503 | +{ | 681 | +{ |
504 | + type_register_static(&crf_info); | 682 | + type_register_static(&crl_info); |
505 | +} | 683 | +} |
506 | + | 684 | + |
507 | +type_init(crf_register_types) | 685 | +type_init(crl_register_types) |
508 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | 686 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build |
509 | index XXXXXXX..XXXXXXX 100644 | 687 | index XXXXXXX..XXXXXXX 100644 |
510 | --- a/hw/misc/meson.build | 688 | --- a/hw/misc/meson.build |
511 | +++ b/hw/misc/meson.build | 689 | +++ b/hw/misc/meson.build |
512 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files( | 690 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) |
513 | )) | ||
514 | softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) | ||
515 | softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c')) | 691 | softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c')) |
516 | +specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c')) | 692 | specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c')) |
693 | specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c')) | ||
694 | +specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c')) | ||
517 | softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files( | 695 | softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files( |
518 | 'xlnx-versal-xramc.c', | 696 | 'xlnx-versal-xramc.c', |
519 | 'xlnx-versal-pmc-iou-slcr.c', | 697 | 'xlnx-versal-pmc-iou-slcr.c', |
520 | -- | 698 | -- |
521 | 2.25.1 | 699 | 2.25.1 |
522 | |||
523 | diff view generated by jsdifflib |
1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | From: "Edgar E. Iglesias" <edgar.iglesias@amd.com> |
---|---|---|---|
2 | 2 | ||
3 | Connect the ZynqMP APU Control device. | 3 | Connect the CRL (Clock Reset LPD) to the Versal SoC. |
4 | 4 | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> |
6 | Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com> | 6 | Reviewed-by: Frederic Konrad <fkonrad@amd.com> |
7 | Reviewed-by: Luc Michel <luc@lmichel.fr> | 7 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> |
8 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 8 | Message-id: 20220406174303.2022038-5-edgar.iglesias@xilinx.com |
9 | Message-id: 20220316164645.2303510-7-edgar.iglesias@gmail.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 10 | --- |
12 | include/hw/arm/xlnx-zynqmp.h | 4 +++- | 11 | include/hw/arm/xlnx-versal.h | 4 +++ |
13 | hw/arm/xlnx-zynqmp.c | 25 +++++++++++++++++++++++-- | 12 | hw/arm/xlnx-versal.c | 54 ++++++++++++++++++++++++++++++++++-- |
14 | 2 files changed, 26 insertions(+), 3 deletions(-) | 13 | 2 files changed, 56 insertions(+), 2 deletions(-) |
15 | 14 | ||
16 | diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h | 15 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h |
17 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/arm/xlnx-zynqmp.h | 17 | --- a/include/hw/arm/xlnx-versal.h |
19 | +++ b/include/hw/arm/xlnx-zynqmp.h | 18 | +++ b/include/hw/arm/xlnx-versal.h |
20 | @@ -XXX,XX +XXX,XX @@ | 19 | @@ -XXX,XX +XXX,XX @@ |
21 | #include "hw/nvram/xlnx-bbram.h" | 20 | #include "hw/nvram/xlnx-versal-efuse.h" |
22 | #include "hw/nvram/xlnx-zynqmp-efuse.h" | 21 | #include "hw/ssi/xlnx-versal-ospi.h" |
23 | #include "hw/or-irq.h" | 22 | #include "hw/dma/xlnx_csu_dma.h" |
24 | +#include "hw/misc/xlnx-zynqmp-apu-ctrl.h" | 23 | +#include "hw/misc/xlnx-versal-crl.h" |
25 | #include "hw/misc/xlnx-zynqmp-crf.h" | 24 | #include "hw/misc/xlnx-versal-pmc-iou-slcr.h" |
26 | 25 | ||
27 | #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" | 26 | #define TYPE_XLNX_VERSAL "xlnx-versal" |
28 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) | 27 | @@ -XXX,XX +XXX,XX @@ struct Versal { |
29 | /* | 28 | qemu_or_irq irq_orgate; |
30 | * Unimplemented mmio regions needed to boot some images. | 29 | XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; |
31 | */ | 30 | } xram; |
32 | -#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 2 | 31 | + |
33 | +#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1 | 32 | + XlnxVersalCRL crl; |
34 | 33 | } lpd; | |
35 | struct XlnxZynqMPState { | 34 | |
36 | /*< private >*/ | 35 | /* The Platform Management Controller subsystem. */ |
37 | @@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState { | 36 | @@ -XXX,XX +XXX,XX @@ struct Versal { |
38 | XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH]; | 37 | #define VERSAL_TIMER_NS_EL1_IRQ 14 |
39 | XlnxCSUDMA qspi_dma; | 38 | #define VERSAL_TIMER_NS_EL2_IRQ 10 |
40 | qemu_or_irq qspi_irq_orgate; | 39 | |
41 | + XlnxZynqMPAPUCtrl apu_ctrl; | 40 | +#define VERSAL_CRL_IRQ 10 |
42 | XlnxZynqMPCRF crf; | 41 | #define VERSAL_UART0_IRQ_0 18 |
43 | 42 | #define VERSAL_UART1_IRQ_0 19 | |
44 | char *boot_cpu; | 43 | #define VERSAL_USB0_IRQ_0 22 |
45 | diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c | 44 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c |
46 | index XXXXXXX..XXXXXXX 100644 | 45 | index XXXXXXX..XXXXXXX 100644 |
47 | --- a/hw/arm/xlnx-zynqmp.c | 46 | --- a/hw/arm/xlnx-versal.c |
48 | +++ b/hw/arm/xlnx-zynqmp.c | 47 | +++ b/hw/arm/xlnx-versal.c |
49 | @@ -XXX,XX +XXX,XX @@ | 48 | @@ -XXX,XX +XXX,XX @@ static void versal_create_ospi(Versal *s, qemu_irq *pic) |
50 | #define DPDMA_IRQ 116 | 49 | qdev_connect_gpio_out(orgate, 0, pic[VERSAL_OSPI_IRQ]); |
51 | |||
52 | #define APU_ADDR 0xfd5c0000 | ||
53 | -#define APU_SIZE 0x100 | ||
54 | +#define APU_IRQ 153 | ||
55 | |||
56 | #define IPI_ADDR 0xFF300000 | ||
57 | #define IPI_IRQ 64 | ||
58 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic) | ||
59 | sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]); | ||
60 | } | 50 | } |
61 | 51 | ||
62 | +static void xlnx_zynqmp_create_apu_ctrl(XlnxZynqMPState *s, qemu_irq *gic) | 52 | +static void versal_create_crl(Versal *s, qemu_irq *pic) |
63 | +{ | 53 | +{ |
64 | + SysBusDevice *sbd; | 54 | + SysBusDevice *sbd; |
65 | + int i; | 55 | + int i; |
66 | + | 56 | + |
67 | + object_initialize_child(OBJECT(s), "apu-ctrl", &s->apu_ctrl, | 57 | + object_initialize_child(OBJECT(s), "crl", &s->lpd.crl, |
68 | + TYPE_XLNX_ZYNQMP_APU_CTRL); | 58 | + TYPE_XLNX_VERSAL_CRL); |
69 | + sbd = SYS_BUS_DEVICE(&s->apu_ctrl); | 59 | + sbd = SYS_BUS_DEVICE(&s->lpd.crl); |
70 | + | 60 | + |
71 | + for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { | 61 | + for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) { |
72 | + g_autofree gchar *name = g_strdup_printf("cpu%d", i); | 62 | + g_autofree gchar *name = g_strdup_printf("cpu_r5[%d]", i); |
73 | + | 63 | + |
74 | + object_property_set_link(OBJECT(&s->apu_ctrl), name, | 64 | + object_property_set_link(OBJECT(&s->lpd.crl), |
75 | + OBJECT(&s->apu_cpu[i]), &error_abort); | 65 | + name, OBJECT(&s->lpd.rpu.cpu[i]), |
66 | + &error_abort); | ||
76 | + } | 67 | + } |
77 | + | 68 | + |
69 | + for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) { | ||
70 | + g_autofree gchar *name = g_strdup_printf("gem[%d]", i); | ||
71 | + | ||
72 | + object_property_set_link(OBJECT(&s->lpd.crl), | ||
73 | + name, OBJECT(&s->lpd.iou.gem[i]), | ||
74 | + &error_abort); | ||
75 | + } | ||
76 | + | ||
77 | + for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) { | ||
78 | + g_autofree gchar *name = g_strdup_printf("adma[%d]", i); | ||
79 | + | ||
80 | + object_property_set_link(OBJECT(&s->lpd.crl), | ||
81 | + name, OBJECT(&s->lpd.iou.adma[i]), | ||
82 | + &error_abort); | ||
83 | + } | ||
84 | + | ||
85 | + for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) { | ||
86 | + g_autofree gchar *name = g_strdup_printf("uart[%d]", i); | ||
87 | + | ||
88 | + object_property_set_link(OBJECT(&s->lpd.crl), | ||
89 | + name, OBJECT(&s->lpd.iou.uart[i]), | ||
90 | + &error_abort); | ||
91 | + } | ||
92 | + | ||
93 | + object_property_set_link(OBJECT(&s->lpd.crl), | ||
94 | + "usb", OBJECT(&s->lpd.iou.usb), | ||
95 | + &error_abort); | ||
96 | + | ||
78 | + sysbus_realize(sbd, &error_fatal); | 97 | + sysbus_realize(sbd, &error_fatal); |
79 | + sysbus_mmio_map(sbd, 0, APU_ADDR); | 98 | + memory_region_add_subregion(&s->mr_ps, MM_CRL, |
80 | + sysbus_connect_irq(sbd, 0, gic[APU_IRQ]); | 99 | + sysbus_mmio_get_region(sbd, 0)); |
100 | + sysbus_connect_irq(sbd, 0, pic[VERSAL_CRL_IRQ]); | ||
81 | +} | 101 | +} |
82 | + | 102 | + |
83 | static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic) | 103 | /* This takes the board allocated linear DDR memory and creates aliases |
84 | { | 104 | * for each split DDR range/aperture on the Versal address map. |
85 | SysBusDevice *sbd; | 105 | */ |
86 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) | 106 | @@ -XXX,XX +XXX,XX @@ static void versal_unimp(Versal *s) |
87 | hwaddr base; | 107 | |
88 | hwaddr size; | 108 | versal_unimp_area(s, "psm", &s->mr_ps, |
89 | } unimp_areas[ARRAY_SIZE(s->mr_unimp)] = { | 109 | MM_PSM_START, MM_PSM_END - MM_PSM_START); |
90 | - { .name = "apu", APU_ADDR, APU_SIZE }, | 110 | - versal_unimp_area(s, "crl", &s->mr_ps, |
91 | { .name = "serdes", SERDES_ADDR, SERDES_SIZE }, | 111 | - MM_CRL, MM_CRL_SIZE); |
92 | }; | 112 | versal_unimp_area(s, "crf", &s->mr_ps, |
93 | unsigned int nr; | 113 | MM_FPD_CRF, MM_FPD_CRF_SIZE); |
94 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) | 114 | versal_unimp_area(s, "apu", &s->mr_ps, |
95 | 115 | @@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp) | |
96 | xlnx_zynqmp_create_bbram(s, gic_spi); | 116 | versal_create_efuse(s, pic); |
97 | xlnx_zynqmp_create_efuse(s, gic_spi); | 117 | versal_create_pmc_iou_slcr(s, pic); |
98 | + xlnx_zynqmp_create_apu_ctrl(s, gic_spi); | 118 | versal_create_ospi(s, pic); |
99 | xlnx_zynqmp_create_crf(s, gic_spi); | 119 | + versal_create_crl(s, pic); |
100 | xlnx_zynqmp_create_unimp_mmio(s); | 120 | versal_map_ddr(s); |
121 | versal_unimp(s); | ||
101 | 122 | ||
102 | -- | 123 | -- |
103 | 2.25.1 | 124 | 2.25.1 |
104 | |||
105 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The Exynos4210 SoC device currently uses a custom device | ||
2 | "exynos4210.irq_gate" to model the OR gate that feeds each CPU's IRQ | ||
3 | line. We have a standard TYPE_OR_IRQ device for this now, so use | ||
4 | that instead. | ||
1 | 5 | ||
6 | (This is a migration compatibility break, but that is OK for this | ||
7 | machine type.) | ||
8 | |||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20220404154658.565020-2-peter.maydell@linaro.org | ||
12 | --- | ||
13 | include/hw/arm/exynos4210.h | 1 + | ||
14 | hw/arm/exynos4210.c | 31 ++++++++++++++++--------------- | ||
15 | 2 files changed, 17 insertions(+), 15 deletions(-) | ||
16 | |||
17 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/include/hw/arm/exynos4210.h | ||
20 | +++ b/include/hw/arm/exynos4210.h | ||
21 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { | ||
22 | MemoryRegion bootreg_mem; | ||
23 | I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; | ||
24 | qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; | ||
25 | + qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; | ||
26 | }; | ||
27 | |||
28 | #define TYPE_EXYNOS4210_SOC "exynos4210" | ||
29 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/hw/arm/exynos4210.c | ||
32 | +++ b/hw/arm/exynos4210.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
34 | { | ||
35 | Exynos4210State *s = EXYNOS4210_SOC(socdev); | ||
36 | MemoryRegion *system_mem = get_system_memory(); | ||
37 | - qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; | ||
38 | SysBusDevice *busdev; | ||
39 | DeviceState *dev, *uart[4], *pl330[3]; | ||
40 | int i, n; | ||
41 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
42 | |||
43 | /* IRQ Gate */ | ||
44 | for (i = 0; i < EXYNOS4210_NCPUS; i++) { | ||
45 | - dev = qdev_new("exynos4210.irq_gate"); | ||
46 | - qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS); | ||
47 | - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | ||
48 | - /* Get IRQ Gate input in gate_irq */ | ||
49 | - for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) { | ||
50 | - gate_irq[i][n] = qdev_get_gpio_in(dev, n); | ||
51 | - } | ||
52 | - busdev = SYS_BUS_DEVICE(dev); | ||
53 | - | ||
54 | - /* Connect IRQ Gate output to CPU's IRQ line */ | ||
55 | - sysbus_connect_irq(busdev, 0, | ||
56 | - qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); | ||
57 | + DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]); | ||
58 | + object_property_set_int(OBJECT(orgate), "num-lines", | ||
59 | + EXYNOS4210_IRQ_GATE_NINPUTS, | ||
60 | + &error_abort); | ||
61 | + qdev_realize(orgate, NULL, &error_abort); | ||
62 | + qdev_connect_gpio_out(orgate, 0, | ||
63 | + qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); | ||
64 | } | ||
65 | |||
66 | /* Private memory region and Internal GIC */ | ||
67 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
68 | sysbus_realize_and_unref(busdev, &error_fatal); | ||
69 | sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); | ||
70 | for (n = 0; n < EXYNOS4210_NCPUS; n++) { | ||
71 | - sysbus_connect_irq(busdev, n, gate_irq[n][0]); | ||
72 | + sysbus_connect_irq(busdev, n, | ||
73 | + qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0)); | ||
74 | } | ||
75 | for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { | ||
76 | s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n); | ||
77 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
78 | /* Map Distributer interface */ | ||
79 | sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR); | ||
80 | for (n = 0; n < EXYNOS4210_NCPUS; n++) { | ||
81 | - sysbus_connect_irq(busdev, n, gate_irq[n][1]); | ||
82 | + sysbus_connect_irq(busdev, n, | ||
83 | + qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1)); | ||
84 | } | ||
85 | for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { | ||
86 | s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n); | ||
87 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj) | ||
88 | object_initialize_child(obj, name, orgate, TYPE_OR_IRQ); | ||
89 | g_free(name); | ||
90 | } | ||
91 | + | ||
92 | + for (i = 0; i < ARRAY_SIZE(s->cpu_irq_orgate); i++) { | ||
93 | + g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i); | ||
94 | + object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ); | ||
95 | + } | ||
96 | } | ||
97 | |||
98 | static void exynos4210_class_init(ObjectClass *klass, void *data) | ||
99 | -- | ||
100 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Now we have removed the only use of TYPE_EXYNOS4210_IRQ_GATE we can | ||
2 | delete the device entirely. | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> | ||
6 | Message-id: 20220404154658.565020-3-peter.maydell@linaro.org | ||
7 | --- | ||
8 | hw/intc/exynos4210_gic.c | 107 --------------------------------------- | ||
9 | 1 file changed, 107 deletions(-) | ||
10 | |||
11 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/hw/intc/exynos4210_gic.c | ||
14 | +++ b/hw/intc/exynos4210_gic.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_register_types(void) | ||
16 | } | ||
17 | |||
18 | type_init(exynos4210_gic_register_types) | ||
19 | - | ||
20 | -/* IRQ OR Gate struct. | ||
21 | - * | ||
22 | - * This device models an OR gate. There are n_in input qdev gpio lines and one | ||
23 | - * output sysbus IRQ line. The output IRQ level is formed as OR between all | ||
24 | - * gpio inputs. | ||
25 | - */ | ||
26 | - | ||
27 | -#define TYPE_EXYNOS4210_IRQ_GATE "exynos4210.irq_gate" | ||
28 | -OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210IRQGateState, EXYNOS4210_IRQ_GATE) | ||
29 | - | ||
30 | -struct Exynos4210IRQGateState { | ||
31 | - SysBusDevice parent_obj; | ||
32 | - | ||
33 | - uint32_t n_in; /* inputs amount */ | ||
34 | - uint32_t *level; /* input levels */ | ||
35 | - qemu_irq out; /* output IRQ */ | ||
36 | -}; | ||
37 | - | ||
38 | -static Property exynos4210_irq_gate_properties[] = { | ||
39 | - DEFINE_PROP_UINT32("n_in", Exynos4210IRQGateState, n_in, 1), | ||
40 | - DEFINE_PROP_END_OF_LIST(), | ||
41 | -}; | ||
42 | - | ||
43 | -static const VMStateDescription vmstate_exynos4210_irq_gate = { | ||
44 | - .name = "exynos4210.irq_gate", | ||
45 | - .version_id = 2, | ||
46 | - .minimum_version_id = 2, | ||
47 | - .fields = (VMStateField[]) { | ||
48 | - VMSTATE_VBUFFER_UINT32(level, Exynos4210IRQGateState, 1, NULL, n_in), | ||
49 | - VMSTATE_END_OF_LIST() | ||
50 | - } | ||
51 | -}; | ||
52 | - | ||
53 | -/* Process a change in IRQ input. */ | ||
54 | -static void exynos4210_irq_gate_handler(void *opaque, int irq, int level) | ||
55 | -{ | ||
56 | - Exynos4210IRQGateState *s = (Exynos4210IRQGateState *)opaque; | ||
57 | - uint32_t i; | ||
58 | - | ||
59 | - assert(irq < s->n_in); | ||
60 | - | ||
61 | - s->level[irq] = level; | ||
62 | - | ||
63 | - for (i = 0; i < s->n_in; i++) { | ||
64 | - if (s->level[i] >= 1) { | ||
65 | - qemu_irq_raise(s->out); | ||
66 | - return; | ||
67 | - } | ||
68 | - } | ||
69 | - | ||
70 | - qemu_irq_lower(s->out); | ||
71 | -} | ||
72 | - | ||
73 | -static void exynos4210_irq_gate_reset(DeviceState *d) | ||
74 | -{ | ||
75 | - Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(d); | ||
76 | - | ||
77 | - memset(s->level, 0, s->n_in * sizeof(*s->level)); | ||
78 | -} | ||
79 | - | ||
80 | -/* | ||
81 | - * IRQ Gate initialization. | ||
82 | - */ | ||
83 | -static void exynos4210_irq_gate_init(Object *obj) | ||
84 | -{ | ||
85 | - Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(obj); | ||
86 | - SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
87 | - | ||
88 | - sysbus_init_irq(sbd, &s->out); | ||
89 | -} | ||
90 | - | ||
91 | -static void exynos4210_irq_gate_realize(DeviceState *dev, Error **errp) | ||
92 | -{ | ||
93 | - Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(dev); | ||
94 | - | ||
95 | - /* Allocate general purpose input signals and connect a handler to each of | ||
96 | - * them */ | ||
97 | - qdev_init_gpio_in(dev, exynos4210_irq_gate_handler, s->n_in); | ||
98 | - | ||
99 | - s->level = g_malloc0(s->n_in * sizeof(*s->level)); | ||
100 | -} | ||
101 | - | ||
102 | -static void exynos4210_irq_gate_class_init(ObjectClass *klass, void *data) | ||
103 | -{ | ||
104 | - DeviceClass *dc = DEVICE_CLASS(klass); | ||
105 | - | ||
106 | - dc->reset = exynos4210_irq_gate_reset; | ||
107 | - dc->vmsd = &vmstate_exynos4210_irq_gate; | ||
108 | - device_class_set_props(dc, exynos4210_irq_gate_properties); | ||
109 | - dc->realize = exynos4210_irq_gate_realize; | ||
110 | -} | ||
111 | - | ||
112 | -static const TypeInfo exynos4210_irq_gate_info = { | ||
113 | - .name = TYPE_EXYNOS4210_IRQ_GATE, | ||
114 | - .parent = TYPE_SYS_BUS_DEVICE, | ||
115 | - .instance_size = sizeof(Exynos4210IRQGateState), | ||
116 | - .instance_init = exynos4210_irq_gate_init, | ||
117 | - .class_init = exynos4210_irq_gate_class_init, | ||
118 | -}; | ||
119 | - | ||
120 | -static void exynos4210_irq_gate_register_types(void) | ||
121 | -{ | ||
122 | - type_register_static(&exynos4210_irq_gate_info); | ||
123 | -} | ||
124 | - | ||
125 | -type_init(exynos4210_irq_gate_register_types) | ||
126 | -- | ||
127 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The exynos4210 SoC mostly creates its child devices as if it were | ||
2 | board code. This includes the a9mpcore object. Switch that to a | ||
3 | new-style "embedded in the state struct" creation, because in the | ||
4 | next commit we're going to want to refer to the object again further | ||
5 | down in the exynos4210_realize() function. | ||
1 | 6 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20220404154658.565020-4-peter.maydell@linaro.org | ||
10 | --- | ||
11 | include/hw/arm/exynos4210.h | 2 ++ | ||
12 | hw/arm/exynos4210.c | 11 ++++++----- | ||
13 | 2 files changed, 8 insertions(+), 5 deletions(-) | ||
14 | |||
15 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/include/hw/arm/exynos4210.h | ||
18 | +++ b/include/hw/arm/exynos4210.h | ||
19 | @@ -XXX,XX +XXX,XX @@ | ||
20 | |||
21 | #include "hw/or-irq.h" | ||
22 | #include "hw/sysbus.h" | ||
23 | +#include "hw/cpu/a9mpcore.h" | ||
24 | #include "target/arm/cpu-qom.h" | ||
25 | #include "qom/object.h" | ||
26 | |||
27 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { | ||
28 | I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; | ||
29 | qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; | ||
30 | qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; | ||
31 | + A9MPPrivState a9mpcore; | ||
32 | }; | ||
33 | |||
34 | #define TYPE_EXYNOS4210_SOC "exynos4210" | ||
35 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/hw/arm/exynos4210.c | ||
38 | +++ b/hw/arm/exynos4210.c | ||
39 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
40 | } | ||
41 | |||
42 | /* Private memory region and Internal GIC */ | ||
43 | - dev = qdev_new(TYPE_A9MPCORE_PRIV); | ||
44 | - qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); | ||
45 | - busdev = SYS_BUS_DEVICE(dev); | ||
46 | - sysbus_realize_and_unref(busdev, &error_fatal); | ||
47 | + qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS); | ||
48 | + busdev = SYS_BUS_DEVICE(&s->a9mpcore); | ||
49 | + sysbus_realize(busdev, &error_fatal); | ||
50 | sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); | ||
51 | for (n = 0; n < EXYNOS4210_NCPUS; n++) { | ||
52 | sysbus_connect_irq(busdev, n, | ||
53 | qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0)); | ||
54 | } | ||
55 | for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { | ||
56 | - s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n); | ||
57 | + s->irqs.int_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->a9mpcore), n); | ||
58 | } | ||
59 | |||
60 | /* Cache controller */ | ||
61 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj) | ||
62 | g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i); | ||
63 | object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ); | ||
64 | } | ||
65 | + | ||
66 | + object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); | ||
67 | } | ||
68 | |||
69 | static void exynos4210_class_init(ObjectClass *klass, void *data) | ||
70 | -- | ||
71 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The only time we use the int_gic_irq[] array in the Exynos4210Irq | ||
2 | struct is in the exynos4210_realize() function: we initialize it with | ||
3 | the GPIO inputs of the a9mpcore device, and then a bit later on we | ||
4 | connect those to the outputs of the internal combiner. Now that the | ||
5 | a9mpcore object is easily accessible as s->a9mpcore we can make the | ||
6 | connection directly from one device to the other without going via | ||
7 | this array. | ||
1 | 8 | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20220404154658.565020-5-peter.maydell@linaro.org | ||
12 | --- | ||
13 | include/hw/arm/exynos4210.h | 1 - | ||
14 | hw/arm/exynos4210.c | 6 ++---- | ||
15 | 2 files changed, 2 insertions(+), 5 deletions(-) | ||
16 | |||
17 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/include/hw/arm/exynos4210.h | ||
20 | +++ b/include/hw/arm/exynos4210.h | ||
21 | @@ -XXX,XX +XXX,XX @@ | ||
22 | typedef struct Exynos4210Irq { | ||
23 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
24 | qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; | ||
25 | - qemu_irq int_gic_irq[EXYNOS4210_INT_GIC_NIRQ]; | ||
26 | qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ]; | ||
27 | qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
28 | } Exynos4210Irq; | ||
29 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/hw/arm/exynos4210.c | ||
32 | +++ b/hw/arm/exynos4210.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
34 | sysbus_connect_irq(busdev, n, | ||
35 | qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0)); | ||
36 | } | ||
37 | - for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { | ||
38 | - s->irqs.int_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->a9mpcore), n); | ||
39 | - } | ||
40 | |||
41 | /* Cache controller */ | ||
42 | sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); | ||
43 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
44 | busdev = SYS_BUS_DEVICE(dev); | ||
45 | sysbus_realize_and_unref(busdev, &error_fatal); | ||
46 | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { | ||
47 | - sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]); | ||
48 | + sysbus_connect_irq(busdev, n, | ||
49 | + qdev_get_gpio_in(DEVICE(&s->a9mpcore), n)); | ||
50 | } | ||
51 | exynos4210_combiner_get_gpioin(&s->irqs, dev, 0); | ||
52 | sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); | ||
53 | -- | ||
54 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The exynos4210 code currently has two very similar arrays of IRQs: | ||
1 | 2 | ||
3 | * board_irqs is a field of the Exynos4210Irq struct which is filled | ||
4 | in by exynos4210_init_board_irqs() with the appropriate qemu_irqs | ||
5 | for each IRQ the board/SoC can assert | ||
6 | * irq_table is a set of qemu_irqs pointed to from the | ||
7 | Exynos4210State struct. It's allocated in exynos4210_init_irq, | ||
8 | and the only behaviour these irqs have is that they pass on the | ||
9 | level to the equivalent board_irqs[] irq | ||
10 | |||
11 | The extra indirection through irq_table is unnecessary, so coalesce | ||
12 | these into a single irq_table[] array as a direct field in | ||
13 | Exynos4210State which exynos4210_init_board_irqs() fills in. | ||
14 | |||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
17 | Message-id: 20220404154658.565020-6-peter.maydell@linaro.org | ||
18 | --- | ||
19 | include/hw/arm/exynos4210.h | 8 ++------ | ||
20 | hw/arm/exynos4210.c | 6 +----- | ||
21 | hw/intc/exynos4210_gic.c | 32 ++++++++------------------------ | ||
22 | 3 files changed, 11 insertions(+), 35 deletions(-) | ||
23 | |||
24 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/include/hw/arm/exynos4210.h | ||
27 | +++ b/include/hw/arm/exynos4210.h | ||
28 | @@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq { | ||
29 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
30 | qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; | ||
31 | qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ]; | ||
32 | - qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
33 | } Exynos4210Irq; | ||
34 | |||
35 | struct Exynos4210State { | ||
36 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { | ||
37 | /*< public >*/ | ||
38 | ARMCPU *cpu[EXYNOS4210_NCPUS]; | ||
39 | Exynos4210Irq irqs; | ||
40 | - qemu_irq *irq_table; | ||
41 | + qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
42 | |||
43 | MemoryRegion chipid_mem; | ||
44 | MemoryRegion iram_mem; | ||
45 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC) | ||
46 | void exynos4210_write_secondary(ARMCPU *cpu, | ||
47 | const struct arm_boot_info *info); | ||
48 | |||
49 | -/* Initialize exynos4210 IRQ subsystem stub */ | ||
50 | -qemu_irq *exynos4210_init_irq(Exynos4210Irq *env); | ||
51 | - | ||
52 | /* Initialize board IRQs. | ||
53 | * These IRQs contain splitted Int/External Combiner and External Gic IRQs */ | ||
54 | -void exynos4210_init_board_irqs(Exynos4210Irq *s); | ||
55 | +void exynos4210_init_board_irqs(Exynos4210State *s); | ||
56 | |||
57 | /* Get IRQ number from exynos4210 IRQ subsystem stub. | ||
58 | * To identify IRQ source use internal combiner group and bit number | ||
59 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
60 | index XXXXXXX..XXXXXXX 100644 | ||
61 | --- a/hw/arm/exynos4210.c | ||
62 | +++ b/hw/arm/exynos4210.c | ||
63 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
64 | qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); | ||
65 | } | ||
66 | |||
67 | - /*** IRQs ***/ | ||
68 | - | ||
69 | - s->irq_table = exynos4210_init_irq(&s->irqs); | ||
70 | - | ||
71 | /* IRQ Gate */ | ||
72 | for (i = 0; i < EXYNOS4210_NCPUS; i++) { | ||
73 | DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]); | ||
74 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
75 | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); | ||
76 | |||
77 | /* Initialize board IRQs. */ | ||
78 | - exynos4210_init_board_irqs(&s->irqs); | ||
79 | + exynos4210_init_board_irqs(s); | ||
80 | |||
81 | /*** Memory ***/ | ||
82 | |||
83 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | ||
84 | index XXXXXXX..XXXXXXX 100644 | ||
85 | --- a/hw/intc/exynos4210_gic.c | ||
86 | +++ b/hw/intc/exynos4210_gic.c | ||
87 | @@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
88 | #define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100 | ||
89 | #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000 | ||
90 | |||
91 | -static void exynos4210_irq_handler(void *opaque, int irq, int level) | ||
92 | -{ | ||
93 | - Exynos4210Irq *s = (Exynos4210Irq *)opaque; | ||
94 | - | ||
95 | - /* Bypass */ | ||
96 | - qemu_set_irq(s->board_irqs[irq], level); | ||
97 | -} | ||
98 | - | ||
99 | -/* | ||
100 | - * Initialize exynos4210 IRQ subsystem stub. | ||
101 | - */ | ||
102 | -qemu_irq *exynos4210_init_irq(Exynos4210Irq *s) | ||
103 | -{ | ||
104 | - return qemu_allocate_irqs(exynos4210_irq_handler, s, | ||
105 | - EXYNOS4210_MAX_INT_COMBINER_IN_IRQ); | ||
106 | -} | ||
107 | - | ||
108 | /* | ||
109 | * Initialize board IRQs. | ||
110 | * These IRQs contain splitted Int/External Combiner and External Gic IRQs. | ||
111 | */ | ||
112 | -void exynos4210_init_board_irqs(Exynos4210Irq *s) | ||
113 | +void exynos4210_init_board_irqs(Exynos4210State *s) | ||
114 | { | ||
115 | uint32_t grp, bit, irq_id, n; | ||
116 | + Exynos4210Irq *is = &s->irqs; | ||
117 | |||
118 | for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { | ||
119 | irq_id = 0; | ||
120 | @@ -XXX,XX +XXX,XX @@ void exynos4210_init_board_irqs(Exynos4210Irq *s) | ||
121 | irq_id = EXT_GIC_ID_MCT_G1; | ||
122 | } | ||
123 | if (irq_id) { | ||
124 | - s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n], | ||
125 | - s->ext_gic_irq[irq_id-32]); | ||
126 | + s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
127 | + is->ext_gic_irq[irq_id - 32]); | ||
128 | } else { | ||
129 | - s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n], | ||
130 | - s->ext_combiner_irq[n]); | ||
131 | + s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
132 | + is->ext_combiner_irq[n]); | ||
133 | } | ||
134 | } | ||
135 | for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { | ||
136 | @@ -XXX,XX +XXX,XX @@ void exynos4210_init_board_irqs(Exynos4210Irq *s) | ||
137 | EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; | ||
138 | |||
139 | if (irq_id) { | ||
140 | - s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n], | ||
141 | - s->ext_gic_irq[irq_id-32]); | ||
142 | + s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
143 | + is->ext_gic_irq[irq_id - 32]); | ||
144 | } | ||
145 | } | ||
146 | } | ||
147 | -- | ||
148 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Fix a missing set of spaces around '-' in the definition of | ||
2 | combiner_grp_to_gic_id[]. We're about to move this code, so | ||
3 | fix the style issue first to keep checkpatch happy with the | ||
4 | code-motion patch. | ||
1 | 5 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20220404154658.565020-7-peter.maydell@linaro.org | ||
9 | --- | ||
10 | hw/intc/exynos4210_gic.c | 2 +- | ||
11 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
12 | |||
13 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/hw/intc/exynos4210_gic.c | ||
16 | +++ b/hw/intc/exynos4210_gic.c | ||
17 | @@ -XXX,XX +XXX,XX @@ enum ExtInt { | ||
18 | */ | ||
19 | |||
20 | static const uint32_t | ||
21 | -combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
22 | +combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
23 | /* int combiner groups 16-19 */ | ||
24 | { }, { }, { }, { }, | ||
25 | /* int combiner group 20 */ | ||
26 | -- | ||
27 | 2.25.1 | diff view generated by jsdifflib |
1 | When we build our Windows installer, it emits the warning: | 1 | The function exynos4210_init_board_irqs() currently lives in |
---|---|---|---|
2 | 2 | exynos4210_gic.c, but it isn't really part of the exynos4210.gic | |
3 | warning 7998: ANSI targets are deprecated | 3 | device -- it is a function that implements (some of) the wiring up of |
4 | 4 | interrupts between the SoC's GIC and combiner components. This means | |
5 | Fix this by making our installer a Unicode installer instead. These | 5 | it fits better in exynos4210.c, which is the SoC-level code. Move it |
6 | won't work on Win95/98/ME, but we already do not support those. | 6 | there. Similarly, exynos4210_git_irq() is used almost only in the |
7 | 7 | SoC-level code, so move it too. | |
8 | See | ||
9 | https://nsis.sourceforge.io/Docs/Chapter4.html#aunicodetarget | ||
10 | for the documentation of the Unicode directive. | ||
11 | 8 | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
14 | Reviewed-by: Stefan Weil <sw@weilnetz.de> | 11 | Message-id: 20220404154658.565020-8-peter.maydell@linaro.org |
15 | Message-id: 20220305105743.2384766-3-peter.maydell@linaro.org | ||
16 | --- | 12 | --- |
17 | qemu.nsi | 3 +++ | 13 | include/hw/arm/exynos4210.h | 4 - |
18 | 1 file changed, 3 insertions(+) | 14 | hw/arm/exynos4210.c | 202 +++++++++++++++++++++++++++++++++++ |
15 | hw/intc/exynos4210_gic.c | 204 ------------------------------------ | ||
16 | 3 files changed, 202 insertions(+), 208 deletions(-) | ||
19 | 17 | ||
20 | diff --git a/qemu.nsi b/qemu.nsi | 18 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h |
21 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/qemu.nsi | 20 | --- a/include/hw/arm/exynos4210.h |
23 | +++ b/qemu.nsi | 21 | +++ b/include/hw/arm/exynos4210.h |
22 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC) | ||
23 | void exynos4210_write_secondary(ARMCPU *cpu, | ||
24 | const struct arm_boot_info *info); | ||
25 | |||
26 | -/* Initialize board IRQs. | ||
27 | - * These IRQs contain splitted Int/External Combiner and External Gic IRQs */ | ||
28 | -void exynos4210_init_board_irqs(Exynos4210State *s); | ||
29 | - | ||
30 | /* Get IRQ number from exynos4210 IRQ subsystem stub. | ||
31 | * To identify IRQ source use internal combiner group and bit number | ||
32 | * grp - group number | ||
33 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/hw/arm/exynos4210.c | ||
36 | +++ b/hw/arm/exynos4210.c | ||
24 | @@ -XXX,XX +XXX,XX @@ | 37 | @@ -XXX,XX +XXX,XX @@ |
25 | !define OUTFILE "qemu-setup.exe" | 38 | #define EXYNOS4210_PL330_BASE1_ADDR 0x12690000 |
26 | !endif | 39 | #define EXYNOS4210_PL330_BASE2_ADDR 0x12850000 |
27 | 40 | ||
28 | +; Build a unicode installer | 41 | +enum ExtGicId { |
29 | +Unicode true | 42 | + EXT_GIC_ID_MDMA_LCD0 = 66, |
30 | + | 43 | + EXT_GIC_ID_PDMA0, |
31 | ; Use maximum compression. | 44 | + EXT_GIC_ID_PDMA1, |
32 | SetCompressor /SOLID lzma | 45 | + EXT_GIC_ID_TIMER0, |
46 | + EXT_GIC_ID_TIMER1, | ||
47 | + EXT_GIC_ID_TIMER2, | ||
48 | + EXT_GIC_ID_TIMER3, | ||
49 | + EXT_GIC_ID_TIMER4, | ||
50 | + EXT_GIC_ID_MCT_L0, | ||
51 | + EXT_GIC_ID_WDT, | ||
52 | + EXT_GIC_ID_RTC_ALARM, | ||
53 | + EXT_GIC_ID_RTC_TIC, | ||
54 | + EXT_GIC_ID_GPIO_XB, | ||
55 | + EXT_GIC_ID_GPIO_XA, | ||
56 | + EXT_GIC_ID_MCT_L1, | ||
57 | + EXT_GIC_ID_IEM_APC, | ||
58 | + EXT_GIC_ID_IEM_IEC, | ||
59 | + EXT_GIC_ID_NFC, | ||
60 | + EXT_GIC_ID_UART0, | ||
61 | + EXT_GIC_ID_UART1, | ||
62 | + EXT_GIC_ID_UART2, | ||
63 | + EXT_GIC_ID_UART3, | ||
64 | + EXT_GIC_ID_UART4, | ||
65 | + EXT_GIC_ID_MCT_G0, | ||
66 | + EXT_GIC_ID_I2C0, | ||
67 | + EXT_GIC_ID_I2C1, | ||
68 | + EXT_GIC_ID_I2C2, | ||
69 | + EXT_GIC_ID_I2C3, | ||
70 | + EXT_GIC_ID_I2C4, | ||
71 | + EXT_GIC_ID_I2C5, | ||
72 | + EXT_GIC_ID_I2C6, | ||
73 | + EXT_GIC_ID_I2C7, | ||
74 | + EXT_GIC_ID_SPI0, | ||
75 | + EXT_GIC_ID_SPI1, | ||
76 | + EXT_GIC_ID_SPI2, | ||
77 | + EXT_GIC_ID_MCT_G1, | ||
78 | + EXT_GIC_ID_USB_HOST, | ||
79 | + EXT_GIC_ID_USB_DEVICE, | ||
80 | + EXT_GIC_ID_MODEMIF, | ||
81 | + EXT_GIC_ID_HSMMC0, | ||
82 | + EXT_GIC_ID_HSMMC1, | ||
83 | + EXT_GIC_ID_HSMMC2, | ||
84 | + EXT_GIC_ID_HSMMC3, | ||
85 | + EXT_GIC_ID_SDMMC, | ||
86 | + EXT_GIC_ID_MIPI_CSI_4LANE, | ||
87 | + EXT_GIC_ID_MIPI_DSI_4LANE, | ||
88 | + EXT_GIC_ID_MIPI_CSI_2LANE, | ||
89 | + EXT_GIC_ID_MIPI_DSI_2LANE, | ||
90 | + EXT_GIC_ID_ONENAND_AUDI, | ||
91 | + EXT_GIC_ID_ROTATOR, | ||
92 | + EXT_GIC_ID_FIMC0, | ||
93 | + EXT_GIC_ID_FIMC1, | ||
94 | + EXT_GIC_ID_FIMC2, | ||
95 | + EXT_GIC_ID_FIMC3, | ||
96 | + EXT_GIC_ID_JPEG, | ||
97 | + EXT_GIC_ID_2D, | ||
98 | + EXT_GIC_ID_PCIe, | ||
99 | + EXT_GIC_ID_MIXER, | ||
100 | + EXT_GIC_ID_HDMI, | ||
101 | + EXT_GIC_ID_HDMI_I2C, | ||
102 | + EXT_GIC_ID_MFC, | ||
103 | + EXT_GIC_ID_TVENC, | ||
104 | +}; | ||
105 | + | ||
106 | +enum ExtInt { | ||
107 | + EXT_GIC_ID_EXTINT0 = 48, | ||
108 | + EXT_GIC_ID_EXTINT1, | ||
109 | + EXT_GIC_ID_EXTINT2, | ||
110 | + EXT_GIC_ID_EXTINT3, | ||
111 | + EXT_GIC_ID_EXTINT4, | ||
112 | + EXT_GIC_ID_EXTINT5, | ||
113 | + EXT_GIC_ID_EXTINT6, | ||
114 | + EXT_GIC_ID_EXTINT7, | ||
115 | + EXT_GIC_ID_EXTINT8, | ||
116 | + EXT_GIC_ID_EXTINT9, | ||
117 | + EXT_GIC_ID_EXTINT10, | ||
118 | + EXT_GIC_ID_EXTINT11, | ||
119 | + EXT_GIC_ID_EXTINT12, | ||
120 | + EXT_GIC_ID_EXTINT13, | ||
121 | + EXT_GIC_ID_EXTINT14, | ||
122 | + EXT_GIC_ID_EXTINT15 | ||
123 | +}; | ||
124 | + | ||
125 | +/* | ||
126 | + * External GIC sources which are not from External Interrupt Combiner or | ||
127 | + * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ, | ||
128 | + * which is INTG16 in Internal Interrupt Combiner. | ||
129 | + */ | ||
130 | + | ||
131 | +static const uint32_t | ||
132 | +combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
133 | + /* int combiner groups 16-19 */ | ||
134 | + { }, { }, { }, { }, | ||
135 | + /* int combiner group 20 */ | ||
136 | + { 0, EXT_GIC_ID_MDMA_LCD0 }, | ||
137 | + /* int combiner group 21 */ | ||
138 | + { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 }, | ||
139 | + /* int combiner group 22 */ | ||
140 | + { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2, | ||
141 | + EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 }, | ||
142 | + /* int combiner group 23 */ | ||
143 | + { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC }, | ||
144 | + /* int combiner group 24 */ | ||
145 | + { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA }, | ||
146 | + /* int combiner group 25 */ | ||
147 | + { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC }, | ||
148 | + /* int combiner group 26 */ | ||
149 | + { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3, | ||
150 | + EXT_GIC_ID_UART4 }, | ||
151 | + /* int combiner group 27 */ | ||
152 | + { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3, | ||
153 | + EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6, | ||
154 | + EXT_GIC_ID_I2C7 }, | ||
155 | + /* int combiner group 28 */ | ||
156 | + { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST}, | ||
157 | + /* int combiner group 29 */ | ||
158 | + { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2, | ||
159 | + EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC }, | ||
160 | + /* int combiner group 30 */ | ||
161 | + { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE }, | ||
162 | + /* int combiner group 31 */ | ||
163 | + { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE }, | ||
164 | + /* int combiner group 32 */ | ||
165 | + { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 }, | ||
166 | + /* int combiner group 33 */ | ||
167 | + { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 }, | ||
168 | + /* int combiner group 34 */ | ||
169 | + { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, | ||
170 | + /* int combiner group 35 */ | ||
171 | + { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
172 | + /* int combiner group 36 */ | ||
173 | + { EXT_GIC_ID_MIXER }, | ||
174 | + /* int combiner group 37 */ | ||
175 | + { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6, | ||
176 | + EXT_GIC_ID_EXTINT7 }, | ||
177 | + /* groups 38-50 */ | ||
178 | + { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, | ||
179 | + /* int combiner group 51 */ | ||
180 | + { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
181 | + /* group 52 */ | ||
182 | + { }, | ||
183 | + /* int combiner group 53 */ | ||
184 | + { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
185 | + /* groups 54-63 */ | ||
186 | + { }, { }, { }, { }, { }, { }, { }, { }, { }, { } | ||
187 | +}; | ||
188 | + | ||
189 | +/* | ||
190 | + * Initialize board IRQs. | ||
191 | + * These IRQs contain splitted Int/External Combiner and External Gic IRQs. | ||
192 | + */ | ||
193 | +static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
194 | +{ | ||
195 | + uint32_t grp, bit, irq_id, n; | ||
196 | + Exynos4210Irq *is = &s->irqs; | ||
197 | + | ||
198 | + for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { | ||
199 | + irq_id = 0; | ||
200 | + if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) || | ||
201 | + n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) { | ||
202 | + /* MCT_G0 is passed to External GIC */ | ||
203 | + irq_id = EXT_GIC_ID_MCT_G0; | ||
204 | + } | ||
205 | + if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) || | ||
206 | + n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) { | ||
207 | + /* MCT_G1 is passed to External and GIC */ | ||
208 | + irq_id = EXT_GIC_ID_MCT_G1; | ||
209 | + } | ||
210 | + if (irq_id) { | ||
211 | + s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
212 | + is->ext_gic_irq[irq_id - 32]); | ||
213 | + } else { | ||
214 | + s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
215 | + is->ext_combiner_irq[n]); | ||
216 | + } | ||
217 | + } | ||
218 | + for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { | ||
219 | + /* these IDs are passed to Internal Combiner and External GIC */ | ||
220 | + grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n); | ||
221 | + bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); | ||
222 | + irq_id = combiner_grp_to_gic_id[grp - | ||
223 | + EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; | ||
224 | + | ||
225 | + if (irq_id) { | ||
226 | + s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
227 | + is->ext_gic_irq[irq_id - 32]); | ||
228 | + } | ||
229 | + } | ||
230 | +} | ||
231 | + | ||
232 | +/* | ||
233 | + * Get IRQ number from exynos4210 IRQ subsystem stub. | ||
234 | + * To identify IRQ source use internal combiner group and bit number | ||
235 | + * grp - group number | ||
236 | + * bit - bit number inside group | ||
237 | + */ | ||
238 | +uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) | ||
239 | +{ | ||
240 | + return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); | ||
241 | +} | ||
242 | + | ||
243 | static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, | ||
244 | 0x09, 0x00, 0x00, 0x00 }; | ||
245 | |||
246 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | ||
247 | index XXXXXXX..XXXXXXX 100644 | ||
248 | --- a/hw/intc/exynos4210_gic.c | ||
249 | +++ b/hw/intc/exynos4210_gic.c | ||
250 | @@ -XXX,XX +XXX,XX @@ | ||
251 | #include "hw/arm/exynos4210.h" | ||
252 | #include "qom/object.h" | ||
253 | |||
254 | -enum ExtGicId { | ||
255 | - EXT_GIC_ID_MDMA_LCD0 = 66, | ||
256 | - EXT_GIC_ID_PDMA0, | ||
257 | - EXT_GIC_ID_PDMA1, | ||
258 | - EXT_GIC_ID_TIMER0, | ||
259 | - EXT_GIC_ID_TIMER1, | ||
260 | - EXT_GIC_ID_TIMER2, | ||
261 | - EXT_GIC_ID_TIMER3, | ||
262 | - EXT_GIC_ID_TIMER4, | ||
263 | - EXT_GIC_ID_MCT_L0, | ||
264 | - EXT_GIC_ID_WDT, | ||
265 | - EXT_GIC_ID_RTC_ALARM, | ||
266 | - EXT_GIC_ID_RTC_TIC, | ||
267 | - EXT_GIC_ID_GPIO_XB, | ||
268 | - EXT_GIC_ID_GPIO_XA, | ||
269 | - EXT_GIC_ID_MCT_L1, | ||
270 | - EXT_GIC_ID_IEM_APC, | ||
271 | - EXT_GIC_ID_IEM_IEC, | ||
272 | - EXT_GIC_ID_NFC, | ||
273 | - EXT_GIC_ID_UART0, | ||
274 | - EXT_GIC_ID_UART1, | ||
275 | - EXT_GIC_ID_UART2, | ||
276 | - EXT_GIC_ID_UART3, | ||
277 | - EXT_GIC_ID_UART4, | ||
278 | - EXT_GIC_ID_MCT_G0, | ||
279 | - EXT_GIC_ID_I2C0, | ||
280 | - EXT_GIC_ID_I2C1, | ||
281 | - EXT_GIC_ID_I2C2, | ||
282 | - EXT_GIC_ID_I2C3, | ||
283 | - EXT_GIC_ID_I2C4, | ||
284 | - EXT_GIC_ID_I2C5, | ||
285 | - EXT_GIC_ID_I2C6, | ||
286 | - EXT_GIC_ID_I2C7, | ||
287 | - EXT_GIC_ID_SPI0, | ||
288 | - EXT_GIC_ID_SPI1, | ||
289 | - EXT_GIC_ID_SPI2, | ||
290 | - EXT_GIC_ID_MCT_G1, | ||
291 | - EXT_GIC_ID_USB_HOST, | ||
292 | - EXT_GIC_ID_USB_DEVICE, | ||
293 | - EXT_GIC_ID_MODEMIF, | ||
294 | - EXT_GIC_ID_HSMMC0, | ||
295 | - EXT_GIC_ID_HSMMC1, | ||
296 | - EXT_GIC_ID_HSMMC2, | ||
297 | - EXT_GIC_ID_HSMMC3, | ||
298 | - EXT_GIC_ID_SDMMC, | ||
299 | - EXT_GIC_ID_MIPI_CSI_4LANE, | ||
300 | - EXT_GIC_ID_MIPI_DSI_4LANE, | ||
301 | - EXT_GIC_ID_MIPI_CSI_2LANE, | ||
302 | - EXT_GIC_ID_MIPI_DSI_2LANE, | ||
303 | - EXT_GIC_ID_ONENAND_AUDI, | ||
304 | - EXT_GIC_ID_ROTATOR, | ||
305 | - EXT_GIC_ID_FIMC0, | ||
306 | - EXT_GIC_ID_FIMC1, | ||
307 | - EXT_GIC_ID_FIMC2, | ||
308 | - EXT_GIC_ID_FIMC3, | ||
309 | - EXT_GIC_ID_JPEG, | ||
310 | - EXT_GIC_ID_2D, | ||
311 | - EXT_GIC_ID_PCIe, | ||
312 | - EXT_GIC_ID_MIXER, | ||
313 | - EXT_GIC_ID_HDMI, | ||
314 | - EXT_GIC_ID_HDMI_I2C, | ||
315 | - EXT_GIC_ID_MFC, | ||
316 | - EXT_GIC_ID_TVENC, | ||
317 | -}; | ||
318 | - | ||
319 | -enum ExtInt { | ||
320 | - EXT_GIC_ID_EXTINT0 = 48, | ||
321 | - EXT_GIC_ID_EXTINT1, | ||
322 | - EXT_GIC_ID_EXTINT2, | ||
323 | - EXT_GIC_ID_EXTINT3, | ||
324 | - EXT_GIC_ID_EXTINT4, | ||
325 | - EXT_GIC_ID_EXTINT5, | ||
326 | - EXT_GIC_ID_EXTINT6, | ||
327 | - EXT_GIC_ID_EXTINT7, | ||
328 | - EXT_GIC_ID_EXTINT8, | ||
329 | - EXT_GIC_ID_EXTINT9, | ||
330 | - EXT_GIC_ID_EXTINT10, | ||
331 | - EXT_GIC_ID_EXTINT11, | ||
332 | - EXT_GIC_ID_EXTINT12, | ||
333 | - EXT_GIC_ID_EXTINT13, | ||
334 | - EXT_GIC_ID_EXTINT14, | ||
335 | - EXT_GIC_ID_EXTINT15 | ||
336 | -}; | ||
337 | - | ||
338 | -/* | ||
339 | - * External GIC sources which are not from External Interrupt Combiner or | ||
340 | - * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ, | ||
341 | - * which is INTG16 in Internal Interrupt Combiner. | ||
342 | - */ | ||
343 | - | ||
344 | -static const uint32_t | ||
345 | -combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
346 | - /* int combiner groups 16-19 */ | ||
347 | - { }, { }, { }, { }, | ||
348 | - /* int combiner group 20 */ | ||
349 | - { 0, EXT_GIC_ID_MDMA_LCD0 }, | ||
350 | - /* int combiner group 21 */ | ||
351 | - { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 }, | ||
352 | - /* int combiner group 22 */ | ||
353 | - { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2, | ||
354 | - EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 }, | ||
355 | - /* int combiner group 23 */ | ||
356 | - { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC }, | ||
357 | - /* int combiner group 24 */ | ||
358 | - { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA }, | ||
359 | - /* int combiner group 25 */ | ||
360 | - { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC }, | ||
361 | - /* int combiner group 26 */ | ||
362 | - { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3, | ||
363 | - EXT_GIC_ID_UART4 }, | ||
364 | - /* int combiner group 27 */ | ||
365 | - { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3, | ||
366 | - EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6, | ||
367 | - EXT_GIC_ID_I2C7 }, | ||
368 | - /* int combiner group 28 */ | ||
369 | - { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST}, | ||
370 | - /* int combiner group 29 */ | ||
371 | - { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2, | ||
372 | - EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC }, | ||
373 | - /* int combiner group 30 */ | ||
374 | - { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE }, | ||
375 | - /* int combiner group 31 */ | ||
376 | - { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE }, | ||
377 | - /* int combiner group 32 */ | ||
378 | - { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 }, | ||
379 | - /* int combiner group 33 */ | ||
380 | - { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 }, | ||
381 | - /* int combiner group 34 */ | ||
382 | - { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, | ||
383 | - /* int combiner group 35 */ | ||
384 | - { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
385 | - /* int combiner group 36 */ | ||
386 | - { EXT_GIC_ID_MIXER }, | ||
387 | - /* int combiner group 37 */ | ||
388 | - { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6, | ||
389 | - EXT_GIC_ID_EXTINT7 }, | ||
390 | - /* groups 38-50 */ | ||
391 | - { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, | ||
392 | - /* int combiner group 51 */ | ||
393 | - { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
394 | - /* group 52 */ | ||
395 | - { }, | ||
396 | - /* int combiner group 53 */ | ||
397 | - { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
398 | - /* groups 54-63 */ | ||
399 | - { }, { }, { }, { }, { }, { }, { }, { }, { }, { } | ||
400 | -}; | ||
401 | - | ||
402 | #define EXYNOS4210_GIC_NIRQ 160 | ||
403 | |||
404 | #define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE 0x10000 | ||
405 | @@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
406 | #define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100 | ||
407 | #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000 | ||
408 | |||
409 | -/* | ||
410 | - * Initialize board IRQs. | ||
411 | - * These IRQs contain splitted Int/External Combiner and External Gic IRQs. | ||
412 | - */ | ||
413 | -void exynos4210_init_board_irqs(Exynos4210State *s) | ||
414 | -{ | ||
415 | - uint32_t grp, bit, irq_id, n; | ||
416 | - Exynos4210Irq *is = &s->irqs; | ||
417 | - | ||
418 | - for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { | ||
419 | - irq_id = 0; | ||
420 | - if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) || | ||
421 | - n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) { | ||
422 | - /* MCT_G0 is passed to External GIC */ | ||
423 | - irq_id = EXT_GIC_ID_MCT_G0; | ||
424 | - } | ||
425 | - if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) || | ||
426 | - n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) { | ||
427 | - /* MCT_G1 is passed to External and GIC */ | ||
428 | - irq_id = EXT_GIC_ID_MCT_G1; | ||
429 | - } | ||
430 | - if (irq_id) { | ||
431 | - s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
432 | - is->ext_gic_irq[irq_id - 32]); | ||
433 | - } else { | ||
434 | - s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
435 | - is->ext_combiner_irq[n]); | ||
436 | - } | ||
437 | - } | ||
438 | - for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { | ||
439 | - /* these IDs are passed to Internal Combiner and External GIC */ | ||
440 | - grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n); | ||
441 | - bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); | ||
442 | - irq_id = combiner_grp_to_gic_id[grp - | ||
443 | - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; | ||
444 | - | ||
445 | - if (irq_id) { | ||
446 | - s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
447 | - is->ext_gic_irq[irq_id - 32]); | ||
448 | - } | ||
449 | - } | ||
450 | -} | ||
451 | - | ||
452 | -/* | ||
453 | - * Get IRQ number from exynos4210 IRQ subsystem stub. | ||
454 | - * To identify IRQ source use internal combiner group and bit number | ||
455 | - * grp - group number | ||
456 | - * bit - bit number inside group | ||
457 | - */ | ||
458 | -uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) | ||
459 | -{ | ||
460 | - return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); | ||
461 | -} | ||
462 | - | ||
463 | -/********* GIC part *********/ | ||
464 | - | ||
465 | #define TYPE_EXYNOS4210_GIC "exynos4210.gic" | ||
466 | OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC) | ||
33 | 467 | ||
34 | -- | 468 | -- |
35 | 2.25.1 | 469 | 2.25.1 |
36 | |||
37 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Switch the creation of the external GIC to the new-style "embedded in | ||
2 | state struct" approach, so we can easily refer to the object | ||
3 | elsewhere during realize. | ||
1 | 4 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20220404154658.565020-9-peter.maydell@linaro.org | ||
8 | --- | ||
9 | include/hw/arm/exynos4210.h | 2 ++ | ||
10 | include/hw/intc/exynos4210_gic.h | 43 ++++++++++++++++++++++++++++++++ | ||
11 | hw/arm/exynos4210.c | 10 ++++---- | ||
12 | hw/intc/exynos4210_gic.c | 17 ++----------- | ||
13 | MAINTAINERS | 2 +- | ||
14 | 5 files changed, 53 insertions(+), 21 deletions(-) | ||
15 | create mode 100644 include/hw/intc/exynos4210_gic.h | ||
16 | |||
17 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/include/hw/arm/exynos4210.h | ||
20 | +++ b/include/hw/arm/exynos4210.h | ||
21 | @@ -XXX,XX +XXX,XX @@ | ||
22 | #include "hw/or-irq.h" | ||
23 | #include "hw/sysbus.h" | ||
24 | #include "hw/cpu/a9mpcore.h" | ||
25 | +#include "hw/intc/exynos4210_gic.h" | ||
26 | #include "target/arm/cpu-qom.h" | ||
27 | #include "qom/object.h" | ||
28 | |||
29 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { | ||
30 | qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; | ||
31 | qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; | ||
32 | A9MPPrivState a9mpcore; | ||
33 | + Exynos4210GicState ext_gic; | ||
34 | }; | ||
35 | |||
36 | #define TYPE_EXYNOS4210_SOC "exynos4210" | ||
37 | diff --git a/include/hw/intc/exynos4210_gic.h b/include/hw/intc/exynos4210_gic.h | ||
38 | new file mode 100644 | ||
39 | index XXXXXXX..XXXXXXX | ||
40 | --- /dev/null | ||
41 | +++ b/include/hw/intc/exynos4210_gic.h | ||
42 | @@ -XXX,XX +XXX,XX @@ | ||
43 | +/* | ||
44 | + * Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c | ||
45 | + * | ||
46 | + * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. | ||
47 | + * All rights reserved. | ||
48 | + * | ||
49 | + * Evgeny Voevodin <e.voevodin@samsung.com> | ||
50 | + * | ||
51 | + * This program is free software; you can redistribute it and/or modify it | ||
52 | + * under the terms of the GNU General Public License as published by the | ||
53 | + * Free Software Foundation; either version 2 of the License, or (at your | ||
54 | + * option) any later version. | ||
55 | + * | ||
56 | + * This program is distributed in the hope that it will be useful, | ||
57 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
58 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | ||
59 | + * See the GNU General Public License for more details. | ||
60 | + * | ||
61 | + * You should have received a copy of the GNU General Public License along | ||
62 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
63 | + */ | ||
64 | +#ifndef HW_INTC_EXYNOS4210_GIC_H | ||
65 | +#define HW_INTC_EXYNOS4210_GIC_H | ||
66 | + | ||
67 | +#include "hw/sysbus.h" | ||
68 | + | ||
69 | +#define TYPE_EXYNOS4210_GIC "exynos4210.gic" | ||
70 | +OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC) | ||
71 | + | ||
72 | +#define EXYNOS4210_GIC_NCPUS 2 | ||
73 | + | ||
74 | +struct Exynos4210GicState { | ||
75 | + SysBusDevice parent_obj; | ||
76 | + | ||
77 | + MemoryRegion cpu_container; | ||
78 | + MemoryRegion dist_container; | ||
79 | + MemoryRegion cpu_alias[EXYNOS4210_GIC_NCPUS]; | ||
80 | + MemoryRegion dist_alias[EXYNOS4210_GIC_NCPUS]; | ||
81 | + uint32_t num_cpu; | ||
82 | + DeviceState *gic; | ||
83 | +}; | ||
84 | + | ||
85 | +#endif | ||
86 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
87 | index XXXXXXX..XXXXXXX 100644 | ||
88 | --- a/hw/arm/exynos4210.c | ||
89 | +++ b/hw/arm/exynos4210.c | ||
90 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
91 | sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); | ||
92 | |||
93 | /* External GIC */ | ||
94 | - dev = qdev_new("exynos4210.gic"); | ||
95 | - qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); | ||
96 | - busdev = SYS_BUS_DEVICE(dev); | ||
97 | - sysbus_realize_and_unref(busdev, &error_fatal); | ||
98 | + qdev_prop_set_uint32(DEVICE(&s->ext_gic), "num-cpu", EXYNOS4210_NCPUS); | ||
99 | + busdev = SYS_BUS_DEVICE(&s->ext_gic); | ||
100 | + sysbus_realize(busdev, &error_fatal); | ||
101 | /* Map CPU interface */ | ||
102 | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); | ||
103 | /* Map Distributer interface */ | ||
104 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
105 | qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1)); | ||
106 | } | ||
107 | for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { | ||
108 | - s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n); | ||
109 | + s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->ext_gic), n); | ||
110 | } | ||
111 | |||
112 | /* Internal Interrupt Combiner */ | ||
113 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj) | ||
114 | } | ||
115 | |||
116 | object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); | ||
117 | + object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC); | ||
118 | } | ||
119 | |||
120 | static void exynos4210_class_init(ObjectClass *klass, void *data) | ||
121 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | ||
122 | index XXXXXXX..XXXXXXX 100644 | ||
123 | --- a/hw/intc/exynos4210_gic.c | ||
124 | +++ b/hw/intc/exynos4210_gic.c | ||
125 | @@ -XXX,XX +XXX,XX @@ | ||
126 | #include "qemu/module.h" | ||
127 | #include "hw/irq.h" | ||
128 | #include "hw/qdev-properties.h" | ||
129 | +#include "hw/intc/exynos4210_gic.h" | ||
130 | #include "hw/arm/exynos4210.h" | ||
131 | #include "qom/object.h" | ||
132 | |||
133 | @@ -XXX,XX +XXX,XX @@ | ||
134 | #define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100 | ||
135 | #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000 | ||
136 | |||
137 | -#define TYPE_EXYNOS4210_GIC "exynos4210.gic" | ||
138 | -OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC) | ||
139 | - | ||
140 | -struct Exynos4210GicState { | ||
141 | - SysBusDevice parent_obj; | ||
142 | - | ||
143 | - MemoryRegion cpu_container; | ||
144 | - MemoryRegion dist_container; | ||
145 | - MemoryRegion cpu_alias[EXYNOS4210_NCPUS]; | ||
146 | - MemoryRegion dist_alias[EXYNOS4210_NCPUS]; | ||
147 | - uint32_t num_cpu; | ||
148 | - DeviceState *gic; | ||
149 | -}; | ||
150 | - | ||
151 | static void exynos4210_gic_set_irq(void *opaque, int irq, int level) | ||
152 | { | ||
153 | Exynos4210GicState *s = (Exynos4210GicState *)opaque; | ||
154 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_realize(DeviceState *dev, Error **errp) | ||
155 | * enough room for the cpu numbers. gcc 9.2.1 on 32-bit x86 | ||
156 | * doesn't figure this out, otherwise and gives spurious warnings. | ||
157 | */ | ||
158 | - assert(n <= EXYNOS4210_NCPUS); | ||
159 | + assert(n <= EXYNOS4210_GIC_NCPUS); | ||
160 | for (i = 0; i < n; i++) { | ||
161 | /* Map CPU interface per SMP Core */ | ||
162 | sprintf(cpu_alias_name, "%s%x", cpu_prefix, i); | ||
163 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
164 | index XXXXXXX..XXXXXXX 100644 | ||
165 | --- a/MAINTAINERS | ||
166 | +++ b/MAINTAINERS | ||
167 | @@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org> | ||
168 | L: qemu-arm@nongnu.org | ||
169 | S: Odd Fixes | ||
170 | F: hw/*/exynos* | ||
171 | -F: include/hw/arm/exynos4210.h | ||
172 | +F: include/hw/*/exynos* | ||
173 | |||
174 | Calxeda Highbank | ||
175 | M: Rob Herring <robh@kernel.org> | ||
176 | -- | ||
177 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The only time we use the ext_gic_irq[] array in the Exynos4210Irq | ||
2 | struct is during realize of the SoC -- we initialize it with the | ||
3 | input IRQs of the external GIC device, and then connect those to | ||
4 | outputs of other devices further on in realize (including in the | ||
5 | exynos4210_init_board_irqs() function). Now that the ext_gic object | ||
6 | is easily accessible as s->ext_gic we can make the connections | ||
7 | directly from one device to the other without going via this array. | ||
1 | 8 | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20220404154658.565020-10-peter.maydell@linaro.org | ||
12 | --- | ||
13 | include/hw/arm/exynos4210.h | 1 - | ||
14 | hw/arm/exynos4210.c | 12 ++++++------ | ||
15 | 2 files changed, 6 insertions(+), 7 deletions(-) | ||
16 | |||
17 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/include/hw/arm/exynos4210.h | ||
20 | +++ b/include/hw/arm/exynos4210.h | ||
21 | @@ -XXX,XX +XXX,XX @@ | ||
22 | typedef struct Exynos4210Irq { | ||
23 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
24 | qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; | ||
25 | - qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ]; | ||
26 | } Exynos4210Irq; | ||
27 | |||
28 | struct Exynos4210State { | ||
29 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/hw/arm/exynos4210.c | ||
32 | +++ b/hw/arm/exynos4210.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
34 | { | ||
35 | uint32_t grp, bit, irq_id, n; | ||
36 | Exynos4210Irq *is = &s->irqs; | ||
37 | + DeviceState *extgicdev = DEVICE(&s->ext_gic); | ||
38 | |||
39 | for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { | ||
40 | irq_id = 0; | ||
41 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
42 | } | ||
43 | if (irq_id) { | ||
44 | s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
45 | - is->ext_gic_irq[irq_id - 32]); | ||
46 | + qdev_get_gpio_in(extgicdev, | ||
47 | + irq_id - 32)); | ||
48 | } else { | ||
49 | s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
50 | is->ext_combiner_irq[n]); | ||
51 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
52 | |||
53 | if (irq_id) { | ||
54 | s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
55 | - is->ext_gic_irq[irq_id - 32]); | ||
56 | + qdev_get_gpio_in(extgicdev, | ||
57 | + irq_id - 32)); | ||
58 | } | ||
59 | } | ||
60 | } | ||
61 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
62 | sysbus_connect_irq(busdev, n, | ||
63 | qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1)); | ||
64 | } | ||
65 | - for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { | ||
66 | - s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->ext_gic), n); | ||
67 | - } | ||
68 | |||
69 | /* Internal Interrupt Combiner */ | ||
70 | dev = qdev_new("exynos4210.combiner"); | ||
71 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
72 | busdev = SYS_BUS_DEVICE(dev); | ||
73 | sysbus_realize_and_unref(busdev, &error_fatal); | ||
74 | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { | ||
75 | - sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]); | ||
76 | + sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n)); | ||
77 | } | ||
78 | exynos4210_combiner_get_gpioin(&s->irqs, dev, 1); | ||
79 | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); | ||
80 | -- | ||
81 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The function exynos4210_combiner_get_gpioin() currently lives in | ||
2 | exynos4210_combiner.c, but it isn't really part of the combiner | ||
3 | device itself -- it is a function that implements the wiring up of | ||
4 | some interrupt sources to multiple combiner inputs. Move it to live | ||
5 | with the other SoC-level code in exynos4210.c, along with a few | ||
6 | macros previously defined in exynos4210.h which are now used only | ||
7 | in exynos4210.c. | ||
1 | 8 | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20220404154658.565020-11-peter.maydell@linaro.org | ||
12 | --- | ||
13 | include/hw/arm/exynos4210.h | 11 ----- | ||
14 | hw/arm/exynos4210.c | 82 +++++++++++++++++++++++++++++++++++ | ||
15 | hw/intc/exynos4210_combiner.c | 77 -------------------------------- | ||
16 | 3 files changed, 82 insertions(+), 88 deletions(-) | ||
17 | |||
18 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/include/hw/arm/exynos4210.h | ||
21 | +++ b/include/hw/arm/exynos4210.h | ||
22 | @@ -XXX,XX +XXX,XX @@ | ||
23 | #define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \ | ||
24 | (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8) | ||
25 | |||
26 | -#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp)*8 + (bit)) | ||
27 | -#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8) | ||
28 | -#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ | ||
29 | - ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) | ||
30 | - | ||
31 | /* IRQs number for external and internal GIC */ | ||
32 | #define EXYNOS4210_EXT_GIC_NIRQ (160-32) | ||
33 | #define EXYNOS4210_INT_GIC_NIRQ 64 | ||
34 | @@ -XXX,XX +XXX,XX @@ void exynos4210_write_secondary(ARMCPU *cpu, | ||
35 | * bit - bit number inside group */ | ||
36 | uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit); | ||
37 | |||
38 | -/* | ||
39 | - * Get Combiner input GPIO into irqs structure | ||
40 | - */ | ||
41 | -void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev, | ||
42 | - int ext); | ||
43 | - | ||
44 | /* | ||
45 | * exynos4210 UART | ||
46 | */ | ||
47 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/hw/arm/exynos4210.c | ||
50 | +++ b/hw/arm/exynos4210.c | ||
51 | @@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
52 | { }, { }, { }, { }, { }, { }, { }, { }, { }, { } | ||
53 | }; | ||
54 | |||
55 | +#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp) * 8 + (bit)) | ||
56 | +#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8) | ||
57 | +#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ | ||
58 | + ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) | ||
59 | + | ||
60 | /* | ||
61 | * Initialize board IRQs. | ||
62 | * These IRQs contain splitted Int/External Combiner and External Gic IRQs. | ||
63 | @@ -XXX,XX +XXX,XX @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) | ||
64 | return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); | ||
65 | } | ||
66 | |||
67 | +/* | ||
68 | + * Get Combiner input GPIO into irqs structure | ||
69 | + */ | ||
70 | +static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, | ||
71 | + DeviceState *dev, int ext) | ||
72 | +{ | ||
73 | + int n; | ||
74 | + int bit; | ||
75 | + int max; | ||
76 | + qemu_irq *irq; | ||
77 | + | ||
78 | + max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ : | ||
79 | + EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; | ||
80 | + irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq; | ||
81 | + | ||
82 | + /* | ||
83 | + * Some IRQs of Int/External Combiner are going to two Combiners groups, | ||
84 | + * so let split them. | ||
85 | + */ | ||
86 | + for (n = 0; n < max; n++) { | ||
87 | + | ||
88 | + bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); | ||
89 | + | ||
90 | + switch (n) { | ||
91 | + /* MDNIE_LCD1 INTG1 */ | ||
92 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ... | ||
93 | + EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3): | ||
94 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
95 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]); | ||
96 | + continue; | ||
97 | + | ||
98 | + /* TMU INTG3 */ | ||
99 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4): | ||
100 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
101 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]); | ||
102 | + continue; | ||
103 | + | ||
104 | + /* LCD1 INTG12 */ | ||
105 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ... | ||
106 | + EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3): | ||
107 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
108 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]); | ||
109 | + continue; | ||
110 | + | ||
111 | + /* Multi-Core Timer INTG12 */ | ||
112 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ... | ||
113 | + EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8): | ||
114 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
115 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
116 | + continue; | ||
117 | + | ||
118 | + /* Multi-Core Timer INTG35 */ | ||
119 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ... | ||
120 | + EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8): | ||
121 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
122 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
123 | + continue; | ||
124 | + | ||
125 | + /* Multi-Core Timer INTG51 */ | ||
126 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ... | ||
127 | + EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8): | ||
128 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
129 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
130 | + continue; | ||
131 | + | ||
132 | + /* Multi-Core Timer INTG53 */ | ||
133 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ... | ||
134 | + EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8): | ||
135 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
136 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
137 | + continue; | ||
138 | + } | ||
139 | + | ||
140 | + irq[n] = qdev_get_gpio_in(dev, n); | ||
141 | + } | ||
142 | +} | ||
143 | + | ||
144 | static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, | ||
145 | 0x09, 0x00, 0x00, 0x00 }; | ||
146 | |||
147 | diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c | ||
148 | index XXXXXXX..XXXXXXX 100644 | ||
149 | --- a/hw/intc/exynos4210_combiner.c | ||
150 | +++ b/hw/intc/exynos4210_combiner.c | ||
151 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_exynos4210_combiner = { | ||
152 | } | ||
153 | }; | ||
154 | |||
155 | -/* | ||
156 | - * Get Combiner input GPIO into irqs structure | ||
157 | - */ | ||
158 | -void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev, | ||
159 | - int ext) | ||
160 | -{ | ||
161 | - int n; | ||
162 | - int bit; | ||
163 | - int max; | ||
164 | - qemu_irq *irq; | ||
165 | - | ||
166 | - max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ : | ||
167 | - EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; | ||
168 | - irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq; | ||
169 | - | ||
170 | - /* | ||
171 | - * Some IRQs of Int/External Combiner are going to two Combiners groups, | ||
172 | - * so let split them. | ||
173 | - */ | ||
174 | - for (n = 0; n < max; n++) { | ||
175 | - | ||
176 | - bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); | ||
177 | - | ||
178 | - switch (n) { | ||
179 | - /* MDNIE_LCD1 INTG1 */ | ||
180 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ... | ||
181 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3): | ||
182 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
183 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]); | ||
184 | - continue; | ||
185 | - | ||
186 | - /* TMU INTG3 */ | ||
187 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4): | ||
188 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
189 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]); | ||
190 | - continue; | ||
191 | - | ||
192 | - /* LCD1 INTG12 */ | ||
193 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ... | ||
194 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3): | ||
195 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
196 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]); | ||
197 | - continue; | ||
198 | - | ||
199 | - /* Multi-Core Timer INTG12 */ | ||
200 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ... | ||
201 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8): | ||
202 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
203 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
204 | - continue; | ||
205 | - | ||
206 | - /* Multi-Core Timer INTG35 */ | ||
207 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ... | ||
208 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8): | ||
209 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
210 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
211 | - continue; | ||
212 | - | ||
213 | - /* Multi-Core Timer INTG51 */ | ||
214 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ... | ||
215 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8): | ||
216 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
217 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
218 | - continue; | ||
219 | - | ||
220 | - /* Multi-Core Timer INTG53 */ | ||
221 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ... | ||
222 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8): | ||
223 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
224 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
225 | - continue; | ||
226 | - } | ||
227 | - | ||
228 | - irq[n] = qdev_get_gpio_in(dev, n); | ||
229 | - } | ||
230 | -} | ||
231 | - | ||
232 | static uint64_t | ||
233 | exynos4210_combiner_read(void *opaque, hwaddr offset, unsigned size) | ||
234 | { | ||
235 | -- | ||
236 | 2.25.1 | diff view generated by jsdifflib |
1 | For M-profile, the fault address is not always exposed to the guest | 1 | Delete a couple of #defines which are never used. |
---|---|---|---|
2 | in a fault register (for instance the BFAR bus fault address register | ||
3 | is only updated for bus faults on data accesses, not instruction | ||
4 | accesses). Currently we log the address only if we're putting it | ||
5 | into a particular guest-visible register. Since we always have it, | ||
6 | log it generically, to make logs of i-side faults a bit clearer. | ||
7 | 2 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
11 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 5 | Message-id: 20220404154658.565020-12-peter.maydell@linaro.org |
12 | Message-id: 20220315204306.2797684-3-peter.maydell@linaro.org | ||
13 | --- | 6 | --- |
14 | target/arm/m_helper.c | 6 ++++++ | 7 | include/hw/arm/exynos4210.h | 4 ---- |
15 | 1 file changed, 6 insertions(+) | 8 | 1 file changed, 4 deletions(-) |
16 | 9 | ||
17 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | 10 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h |
18 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/m_helper.c | 12 | --- a/include/hw/arm/exynos4210.h |
20 | +++ b/target/arm/m_helper.c | 13 | +++ b/include/hw/arm/exynos4210.h |
21 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | 14 | @@ -XXX,XX +XXX,XX @@ |
22 | * Note that for M profile we don't have a guest facing FSR, but | 15 | #define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \ |
23 | * the env->exception.fsr will be populated by the code that | 16 | (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8) |
24 | * raises the fault, in the A profile short-descriptor format. | 17 | |
25 | + * | 18 | -/* IRQs number for external and internal GIC */ |
26 | + * Log the exception.vaddress now regardless of subtype, because | 19 | -#define EXYNOS4210_EXT_GIC_NIRQ (160-32) |
27 | + * logging below only logs it when it goes into a guest visible | 20 | -#define EXYNOS4210_INT_GIC_NIRQ 64 |
28 | + * register. | 21 | - |
29 | */ | 22 | #define EXYNOS4210_I2C_NUMBER 9 |
30 | + qemu_log_mask(CPU_LOG_INT, "...at fault address 0x%x\n", | 23 | |
31 | + (uint32_t)env->exception.vaddress); | 24 | #define EXYNOS4210_NUM_DMA 3 |
32 | switch (env->exception.fsr & 0xf) { | ||
33 | case M_FAKE_FSR_NSC_EXEC: | ||
34 | /* | ||
35 | -- | 25 | -- |
36 | 2.25.1 | 26 | 2.25.1 |
37 | |||
38 | diff view generated by jsdifflib |
1 | We use the nsis.py script to write out an installer script Section | 1 | In exynos4210_init_board_irqs(), use the TYPE_SPLIT_IRQ device |
---|---|---|---|
2 | for each emulator executable, so the exact set of Sections depends on | 2 | instead of qemu_irq_split(). |
3 | which executables were built. However the part of qemu.nsi which | ||
4 | specifies mouse-over descriptions for each Section still has a | ||
5 | hard-coded and very outdated list (with just i386 and alpha). This | ||
6 | causes two problems. Firstly, if you build the installer for a | ||
7 | configuration where you didn't build the i386 binaries you get | ||
8 | warnings like this: | ||
9 | warning 6000: unknown variable/constant "{Section_i386}" detected, ignoring (macro:_==:1) | ||
10 | warning 6000: unknown variable/constant "{Section_i386w}" detected, ignoring (macro:_==:1) | ||
11 | (this happens in our gitlab CI jobs, for instance). | ||
12 | Secondly, most of the emulators in the generated installer don't have | ||
13 | any mouseover text. | ||
14 | |||
15 | Make nsis.py generate a second output file which has the necessary | ||
16 | MUI_DESCRIPTION_TEXT lines for each Section it creates, so we can | ||
17 | include that at the right point in qemu.nsi to set the mouse-over | ||
18 | text. | ||
19 | 3 | ||
20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
21 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
22 | Reviewed-by: John Snow <jsnow@redhat.com> | 6 | Message-id: 20220404154658.565020-13-peter.maydell@linaro.org |
23 | Message-id: 20220305105743.2384766-4-peter.maydell@linaro.org | ||
24 | --- | 7 | --- |
25 | qemu.nsi | 5 +---- | 8 | include/hw/arm/exynos4210.h | 9 ++++++++ |
26 | scripts/nsis.py | 13 ++++++++++++- | 9 | hw/arm/exynos4210.c | 41 +++++++++++++++++++++++++++++-------- |
27 | 2 files changed, 13 insertions(+), 5 deletions(-) | 10 | 2 files changed, 42 insertions(+), 8 deletions(-) |
28 | 11 | ||
29 | diff --git a/qemu.nsi b/qemu.nsi | 12 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h |
30 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
31 | --- a/qemu.nsi | 14 | --- a/include/hw/arm/exynos4210.h |
32 | +++ b/qemu.nsi | 15 | +++ b/include/hw/arm/exynos4210.h |
33 | @@ -XXX,XX +XXX,XX @@ SectionEnd | 16 | @@ -XXX,XX +XXX,XX @@ |
34 | ; Descriptions (mouse-over). | 17 | #include "hw/sysbus.h" |
35 | !insertmacro MUI_FUNCTION_DESCRIPTION_BEGIN | 18 | #include "hw/cpu/a9mpcore.h" |
36 | !insertmacro MUI_DESCRIPTION_TEXT ${SectionSystem} "System emulation." | 19 | #include "hw/intc/exynos4210_gic.h" |
37 | - !insertmacro MUI_DESCRIPTION_TEXT ${Section_alpha} "Alpha system emulation." | 20 | +#include "hw/core/split-irq.h" |
38 | - !insertmacro MUI_DESCRIPTION_TEXT ${Section_alphaw} "Alpha system emulation (GUI)." | 21 | #include "target/arm/cpu-qom.h" |
39 | - !insertmacro MUI_DESCRIPTION_TEXT ${Section_i386} "PC i386 system emulation." | 22 | #include "qom/object.h" |
40 | - !insertmacro MUI_DESCRIPTION_TEXT ${Section_i386w} "PC i386 system emulation (GUI)." | 23 | |
41 | +!include "${BINDIR}\system-mui-text.nsh" | 24 | @@ -XXX,XX +XXX,XX @@ |
42 | !insertmacro MUI_DESCRIPTION_TEXT ${SectionTools} "Tools." | 25 | |
43 | !ifdef DLLDIR | 26 | #define EXYNOS4210_NUM_DMA 3 |
44 | !insertmacro MUI_DESCRIPTION_TEXT ${SectionDll} "Runtime Libraries (DLL)." | 27 | |
45 | diff --git a/scripts/nsis.py b/scripts/nsis.py | 28 | +/* |
29 | + * We need one splitter for every external combiner input, plus | ||
30 | + * one for every non-zero entry in combiner_grp_to_gic_id[]. | ||
31 | + * We'll assert in exynos4210_init_board_irqs() if this is wrong. | ||
32 | + */ | ||
33 | +#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 60) | ||
34 | + | ||
35 | typedef struct Exynos4210Irq { | ||
36 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
37 | qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; | ||
38 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { | ||
39 | qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; | ||
40 | A9MPPrivState a9mpcore; | ||
41 | Exynos4210GicState ext_gic; | ||
42 | + SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS]; | ||
43 | }; | ||
44 | |||
45 | #define TYPE_EXYNOS4210_SOC "exynos4210" | ||
46 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
46 | index XXXXXXX..XXXXXXX 100644 | 47 | index XXXXXXX..XXXXXXX 100644 |
47 | --- a/scripts/nsis.py | 48 | --- a/hw/arm/exynos4210.c |
48 | +++ b/scripts/nsis.py | 49 | +++ b/hw/arm/exynos4210.c |
49 | @@ -XXX,XX +XXX,XX @@ def main(): | 50 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) |
50 | subprocess.run(["make", "install", "DESTDIR=" + destdir + os.path.sep]) | 51 | uint32_t grp, bit, irq_id, n; |
51 | with open( | 52 | Exynos4210Irq *is = &s->irqs; |
52 | os.path.join(destdir + args.prefix, "system-emulations.nsh"), "w" | 53 | DeviceState *extgicdev = DEVICE(&s->ext_gic); |
53 | - ) as nsh: | 54 | + int splitcount = 0; |
54 | + ) as nsh, open( | 55 | + DeviceState *splitter; |
55 | + os.path.join(destdir + args.prefix, "system-mui-text.nsh"), "w" | 56 | |
56 | + ) as muinsh: | 57 | for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { |
57 | for exe in sorted(glob.glob( | 58 | irq_id = 0; |
58 | os.path.join(destdir + args.prefix, "qemu-system-*.exe") | 59 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) |
59 | )): | 60 | /* MCT_G1 is passed to External and GIC */ |
60 | @@ -XXX,XX +XXX,XX @@ def main(): | 61 | irq_id = EXT_GIC_ID_MCT_G1; |
61 | arch, exe | 62 | } |
62 | ) | ||
63 | ) | ||
64 | + if arch.endswith('w'): | ||
65 | + desc = arch[:-1] + " emulation (GUI)." | ||
66 | + else: | ||
67 | + desc = arch + " emulation." | ||
68 | + | 63 | + |
69 | + muinsh.write( | 64 | + assert(splitcount < EXYNOS4210_NUM_SPLITTERS); |
70 | + """ | 65 | + splitter = DEVICE(&s->splitter[splitcount]); |
71 | + !insertmacro MUI_DESCRIPTION_TEXT ${{Section_{0}}} "{1}" | 66 | + qdev_prop_set_uint16(splitter, "num-lines", 2); |
72 | + """.format(arch, desc)) | 67 | + qdev_realize(splitter, NULL, &error_abort); |
73 | 68 | + splitcount++; | |
74 | for exe in glob.glob(os.path.join(destdir + args.prefix, "*.exe")): | 69 | + s->irq_table[n] = qdev_get_gpio_in(splitter, 0); |
75 | signcode(exe) | 70 | + qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); |
71 | if (irq_id) { | ||
72 | - s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
73 | - qdev_get_gpio_in(extgicdev, | ||
74 | - irq_id - 32)); | ||
75 | + qdev_connect_gpio_out(splitter, 1, | ||
76 | + qdev_get_gpio_in(extgicdev, irq_id - 32)); | ||
77 | } else { | ||
78 | - s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
79 | - is->ext_combiner_irq[n]); | ||
80 | + qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]); | ||
81 | } | ||
82 | } | ||
83 | for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { | ||
84 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
85 | EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; | ||
86 | |||
87 | if (irq_id) { | ||
88 | - s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
89 | - qdev_get_gpio_in(extgicdev, | ||
90 | - irq_id - 32)); | ||
91 | + assert(splitcount < EXYNOS4210_NUM_SPLITTERS); | ||
92 | + splitter = DEVICE(&s->splitter[splitcount]); | ||
93 | + qdev_prop_set_uint16(splitter, "num-lines", 2); | ||
94 | + qdev_realize(splitter, NULL, &error_abort); | ||
95 | + splitcount++; | ||
96 | + s->irq_table[n] = qdev_get_gpio_in(splitter, 0); | ||
97 | + qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); | ||
98 | + qdev_connect_gpio_out(splitter, 1, | ||
99 | + qdev_get_gpio_in(extgicdev, irq_id - 32)); | ||
100 | } | ||
101 | } | ||
102 | + /* | ||
103 | + * We check this here to avoid a more obscure assert later when | ||
104 | + * qdev_assert_realized_properly() checks that we realized every | ||
105 | + * child object we initialized. | ||
106 | + */ | ||
107 | + assert(splitcount == EXYNOS4210_NUM_SPLITTERS); | ||
108 | } | ||
109 | |||
110 | /* | ||
111 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj) | ||
112 | object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ); | ||
113 | } | ||
114 | |||
115 | + for (i = 0; i < ARRAY_SIZE(s->splitter); i++) { | ||
116 | + g_autofree char *name = g_strdup_printf("irq-splitter%d", i); | ||
117 | + object_initialize_child(obj, name, &s->splitter[i], TYPE_SPLIT_IRQ); | ||
118 | + } | ||
119 | + | ||
120 | object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); | ||
121 | object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC); | ||
122 | } | ||
76 | -- | 123 | -- |
77 | 2.25.1 | 124 | 2.25.1 |
78 | |||
79 | diff view generated by jsdifflib |
1 | We currently list the emulators in the Windows installer's dialog | 1 | In exynos4210_init_board_irqs(), the loop that handles IRQ lines that |
---|---|---|---|
2 | in an essentially random order (it's whatever glob.glob() returns | 2 | are in a range that applies to the internal combiner only creates a |
3 | them to, which is filesystem-implementation-dependent). Add a | 3 | splitter for those interrupts which go to both the internal combiner |
4 | call to sorted() so they appear in alphabetical order. | 4 | and to the external GIC, but it does nothing at all for the |
5 | interrupts which don't go to the external GIC, leaving the | ||
6 | irq_table[] array element empty for those. (This will result in | ||
7 | those interrupts simply being lost, not in a QEMU crash.) | ||
8 | |||
9 | I don't have a reliable datasheet for this SoC, but since we do wire | ||
10 | up one interrupt line in this category (the HDMI I2C device on | ||
11 | interrupt 16,1), this seems like it must be a bug in the existing | ||
12 | QEMU code. Fill in the irq_table[] entries where we're not splitting | ||
13 | the IRQ to both the internal combiner and the external GIC with the | ||
14 | IRQ line of the internal combiner. (That is, these IRQ lines go to | ||
15 | just one device, not multiple.) | ||
16 | |||
17 | This bug didn't have any visible guest effects because the only | ||
18 | implemented device that was affected was the HDMI I2C controller, | ||
19 | and we never connect any I2C devices to that bus. | ||
5 | 20 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 22 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Reviewed-by: Stefan Weil <sw@weilnetz.de> | 23 | Message-id: 20220404154658.565020-14-peter.maydell@linaro.org |
9 | Reviewed-by: John Snow <jsnow@redhat.com> | ||
10 | Message-id: 20220305105743.2384766-2-peter.maydell@linaro.org | ||
11 | --- | 24 | --- |
12 | scripts/nsis.py | 4 ++-- | 25 | hw/arm/exynos4210.c | 2 ++ |
13 | 1 file changed, 2 insertions(+), 2 deletions(-) | 26 | 1 file changed, 2 insertions(+) |
14 | 27 | ||
15 | diff --git a/scripts/nsis.py b/scripts/nsis.py | 28 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c |
16 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/scripts/nsis.py | 30 | --- a/hw/arm/exynos4210.c |
18 | +++ b/scripts/nsis.py | 31 | +++ b/hw/arm/exynos4210.c |
19 | @@ -XXX,XX +XXX,XX @@ def main(): | 32 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) |
20 | with open( | 33 | qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); |
21 | os.path.join(destdir + args.prefix, "system-emulations.nsh"), "w" | 34 | qdev_connect_gpio_out(splitter, 1, |
22 | ) as nsh: | 35 | qdev_get_gpio_in(extgicdev, irq_id - 32)); |
23 | - for exe in glob.glob( | 36 | + } else { |
24 | + for exe in sorted(glob.glob( | 37 | + s->irq_table[n] = is->int_combiner_irq[n]; |
25 | os.path.join(destdir + args.prefix, "qemu-system-*.exe") | 38 | } |
26 | - ): | 39 | } |
27 | + )): | 40 | /* |
28 | exe = os.path.basename(exe) | ||
29 | arch = exe[12:-4] | ||
30 | nsh.write( | ||
31 | -- | 41 | -- |
32 | 2.25.1 | 42 | 2.25.1 |
33 | |||
34 | diff view generated by jsdifflib |
1 | In npcm7xx_clk_sel_init() we allocate a string with g_strdup_printf(). | 1 | Currently for the interrupts MCT_G0 and MCT_G1 which are |
---|---|---|---|
2 | Use g_autofree so we free it rather than leaking it. | 2 | the only ones in the input range of the external combiner |
3 | and which are also wired to the external GIC, we connect | ||
4 | them only to the internal combiner and the external GIC. | ||
5 | This seems likely to be a bug, as all other interrupts | ||
6 | which are in the input range of both combiners are | ||
7 | connected to both combiners. (The fact that the code in | ||
8 | exynos4210_combiner_get_gpioin() is also trying to wire | ||
9 | up these inputs on both combiners also suggests this.) | ||
3 | 10 | ||
4 | (Detected with the clang leak sanitizer.) | 11 | Wire these interrupts up to both combiners, like the rest. |
5 | 12 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 15 | Message-id: 20220404154658.565020-15-peter.maydell@linaro.org |
9 | Message-id: 20220308170302.2582820-1-peter.maydell@linaro.org | ||
10 | --- | 16 | --- |
11 | hw/misc/npcm7xx_clk.c | 4 ++-- | 17 | hw/arm/exynos4210.c | 7 +++---- |
12 | 1 file changed, 2 insertions(+), 2 deletions(-) | 18 | 1 file changed, 3 insertions(+), 4 deletions(-) |
13 | 19 | ||
14 | diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c | 20 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c |
15 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/misc/npcm7xx_clk.c | 22 | --- a/hw/arm/exynos4210.c |
17 | +++ b/hw/misc/npcm7xx_clk.c | 23 | +++ b/hw/arm/exynos4210.c |
18 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_sel_init(Object *obj) | 24 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) |
19 | NPCM7xxClockSELState *sel = NPCM7XX_CLOCK_SEL(obj); | 25 | |
20 | 26 | assert(splitcount < EXYNOS4210_NUM_SPLITTERS); | |
21 | for (i = 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) { | 27 | splitter = DEVICE(&s->splitter[splitcount]); |
22 | - sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel), | 28 | - qdev_prop_set_uint16(splitter, "num-lines", 2); |
23 | - g_strdup_printf("clock-in[%d]", i), | 29 | + qdev_prop_set_uint16(splitter, "num-lines", irq_id ? 3 : 2); |
24 | + g_autofree char *s = g_strdup_printf("clock-in[%d]", i); | 30 | qdev_realize(splitter, NULL, &error_abort); |
25 | + sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel), s, | 31 | splitcount++; |
26 | npcm7xx_clk_update_sel_cb, sel, ClockUpdate); | 32 | s->irq_table[n] = qdev_get_gpio_in(splitter, 0); |
33 | qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); | ||
34 | + qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]); | ||
35 | if (irq_id) { | ||
36 | - qdev_connect_gpio_out(splitter, 1, | ||
37 | + qdev_connect_gpio_out(splitter, 2, | ||
38 | qdev_get_gpio_in(extgicdev, irq_id - 32)); | ||
39 | - } else { | ||
40 | - qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]); | ||
41 | } | ||
27 | } | 42 | } |
28 | sel->clock_out = qdev_init_clock_out(DEVICE(sel), "clock-out"); | 43 | for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { |
29 | -- | 44 | -- |
30 | 2.25.1 | 45 | 2.25.1 |
31 | |||
32 | diff view generated by jsdifflib |
1 | In commit 00f05c02f9e7342f we gave the TYPE_XLNX_CSU_DMA object its | 1 | The combiner_grp_to_gic_id[] array includes the EXT_GIC_ID_MCT_G0 |
---|---|---|---|
2 | own class struct, but forgot to update the TypeInfo::class_size | 2 | and EXT_GIC_ID_MCT_G1 multiple times. This means that we will |
3 | accordingly. This meant that not enough memory was allocated for the | 3 | connect multiple IRQs up to the same external GIC input, which |
4 | class struct, and the initialization of xcdc->read in the class init | 4 | is not permitted. We do the same thing in the code in |
5 | function wrote off the end of the memory. Add the missing line. | 5 | exynos4210_init_board_irqs() because the conditionals selecting |
6 | an irq_id in the first loop match multiple interrupt IDs. | ||
6 | 7 | ||
7 | Found by running 'check-qtest-aarch64' with a clang | 8 | Overall we do this for interrupt IDs |
8 | address-sanitizer build, which complains: | 9 | (1, 4), (12, 4), (35, 4), (51, 4), (53, 4) for EXT_GIC_ID_MCT_G0 |
10 | and | ||
11 | (1, 5), (12, 5), (35, 5), (51, 5), (53, 5) for EXT_GIC_ID_MCT_G1 | ||
9 | 12 | ||
10 | ==2542634==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x61000000ab00 at pc 0x559a20aebc29 bp 0x7fff97df74d0 sp 0x7fff97df74c8 | 13 | These correspond to the cases for the multi-core timer that we are |
11 | WRITE of size 8 at 0x61000000ab00 thread T0 | 14 | wiring up to multiple inputs on the combiner in |
12 | #0 0x559a20aebc28 in xlnx_csu_dma_class_init /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../hw/dma/xlnx_csu_dma.c:722:16 | 15 | exynos4210_combiner_get_gpioin(). That code already deals with all |
13 | #1 0x559a21bf297c in type_initialize /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:365:9 | 16 | these interrupt IDs being the same input source, so we don't need to |
14 | #2 0x559a21bf3442 in object_class_foreach_tramp /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1070:5 | 17 | connect the external GIC interrupt for any of them except the first |
15 | #3 0x7f09bcb641b7 in g_hash_table_foreach (/usr/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x401b7) | 18 | (1, 4) and (1, 5). Remove the array entries and conditionals which |
16 | #4 0x559a21bf3c27 in object_class_foreach /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1092:5 | 19 | were incorrectly causing us to wire up extra lines. |
17 | #5 0x559a21bf3c27 in object_class_get_list /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1149:5 | ||
18 | #6 0x559a2081a2fd in select_machine /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../softmmu/vl.c:1661:24 | ||
19 | #7 0x559a2081a2fd in qemu_create_machine /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../softmmu/vl.c:2146:35 | ||
20 | #8 0x559a2081a2fd in qemu_init /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../softmmu/vl.c:3706:5 | ||
21 | #9 0x559a20720ed5 in main /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../softmmu/main.c:49:5 | ||
22 | #10 0x7f09baec00b2 in __libc_start_main /build/glibc-sMfBJT/glibc-2.31/csu/../csu/libc-start.c:308:16 | ||
23 | #11 0x559a2067673d in _start (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/qemu-system-aarch64+0xf4b73d) | ||
24 | 20 | ||
25 | 0x61000000ab00 is located 0 bytes to the right of 192-byte region [0x61000000aa40,0x61000000ab00) | 21 | This bug didn't cause any visible effects, because we only connect |
26 | allocated by thread T0 here: | 22 | up a device to the "primary" ID values (1, 4) and (1, 5), so the |
27 | #0 0x559a206eeff2 in calloc (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/qemu-system-aarch64+0xfc3ff2) | 23 | extra lines would never be set to a level. |
28 | #1 0x7f09bcb7bef0 in g_malloc0 (/usr/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x57ef0) | ||
29 | #2 0x559a21bf3442 in object_class_foreach_tramp /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1070:5 | ||
30 | 24 | ||
31 | Fixes: 00f05c02f9e7342f ("hw/dma/xlnx_csu_dma: Support starting a read transfer through a class method") | ||
32 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
33 | Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com> | 26 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
34 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 27 | Message-id: 20220404154658.565020-16-peter.maydell@linaro.org |
35 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
36 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
37 | Message-id: 20220308150207.2546272-1-peter.maydell@linaro.org | ||
38 | --- | 28 | --- |
39 | hw/dma/xlnx_csu_dma.c | 1 + | 29 | include/hw/arm/exynos4210.h | 2 +- |
40 | 1 file changed, 1 insertion(+) | 30 | hw/arm/exynos4210.c | 12 +++++------- |
31 | 2 files changed, 6 insertions(+), 8 deletions(-) | ||
41 | 32 | ||
42 | diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c | 33 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h |
43 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
44 | --- a/hw/dma/xlnx_csu_dma.c | 35 | --- a/include/hw/arm/exynos4210.h |
45 | +++ b/hw/dma/xlnx_csu_dma.c | 36 | +++ b/include/hw/arm/exynos4210.h |
46 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo xlnx_csu_dma_info = { | 37 | @@ -XXX,XX +XXX,XX @@ |
47 | .parent = TYPE_SYS_BUS_DEVICE, | 38 | * one for every non-zero entry in combiner_grp_to_gic_id[]. |
48 | .instance_size = sizeof(XlnxCSUDMA), | 39 | * We'll assert in exynos4210_init_board_irqs() if this is wrong. |
49 | .class_init = xlnx_csu_dma_class_init, | 40 | */ |
50 | + .class_size = sizeof(XlnxCSUDMAClass), | 41 | -#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 60) |
51 | .instance_init = xlnx_csu_dma_init, | 42 | +#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 54) |
52 | .interfaces = (InterfaceInfo[]) { | 43 | |
53 | { TYPE_STREAM_SINK }, | 44 | typedef struct Exynos4210Irq { |
45 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
46 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/hw/arm/exynos4210.c | ||
49 | +++ b/hw/arm/exynos4210.c | ||
50 | @@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
51 | /* int combiner group 34 */ | ||
52 | { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, | ||
53 | /* int combiner group 35 */ | ||
54 | - { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
55 | + { 0, 0, 0, EXT_GIC_ID_MCT_L1 }, | ||
56 | /* int combiner group 36 */ | ||
57 | { EXT_GIC_ID_MIXER }, | ||
58 | /* int combiner group 37 */ | ||
59 | @@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
60 | /* groups 38-50 */ | ||
61 | { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, | ||
62 | /* int combiner group 51 */ | ||
63 | - { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
64 | + { EXT_GIC_ID_MCT_L0 }, | ||
65 | /* group 52 */ | ||
66 | { }, | ||
67 | /* int combiner group 53 */ | ||
68 | - { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
69 | + { EXT_GIC_ID_WDT }, | ||
70 | /* groups 54-63 */ | ||
71 | { }, { }, { }, { }, { }, { }, { }, { }, { }, { } | ||
72 | }; | ||
73 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
74 | |||
75 | for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { | ||
76 | irq_id = 0; | ||
77 | - if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) || | ||
78 | - n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) { | ||
79 | + if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4)) { | ||
80 | /* MCT_G0 is passed to External GIC */ | ||
81 | irq_id = EXT_GIC_ID_MCT_G0; | ||
82 | } | ||
83 | - if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) || | ||
84 | - n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) { | ||
85 | + if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5)) { | ||
86 | /* MCT_G1 is passed to External and GIC */ | ||
87 | irq_id = EXT_GIC_ID_MCT_G1; | ||
88 | } | ||
54 | -- | 89 | -- |
55 | 2.25.1 | 90 | 2.25.1 |
56 | |||
57 | diff view generated by jsdifflib |
1 | Currently the CPU_LOG_INT logging misses some useful information | 1 | At this point, the function exynos4210_init_board_irqs() splits input |
---|---|---|---|
2 | about loads from the vector table. Add logging where we load vector | 2 | IRQ lines to connect them to the input combiner, output combiner and |
3 | table entries. This is particularly helpful for cases where the user | 3 | external GIC. The function exynos4210_combiner_get_gpioin() splits |
4 | has accidentally not put a vector table in their image at all, which | 4 | some of the combiner input lines further to connect them to multiple |
5 | can result in confusing guest crashes at startup. | 5 | different inputs on the combiner. |
6 | 6 | ||
7 | Here's an example of the new logging for a case where | 7 | Because (unlike qemu_irq_split()) the TYPE_SPLIT_IRQ device has a |
8 | the vector table contains garbage: | 8 | configurable number of outputs, we can do all this in one place, by |
9 | 9 | making exynos4210_init_board_irqs() add extra outputs to the splitter | |
10 | Loaded reset SP 0x0 PC 0x0 from vector table | 10 | device when it must be connected to more than one input on each |
11 | Loaded reset SP 0xd008f8df PC 0xf000bf00 from vector table | 11 | combiner. |
12 | Taking exception 3 [Prefetch Abort] on CPU 0 | 12 | |
13 | ...with CFSR.IACCVIOL | 13 | We do this with a new data structure, the combinermap, which is an |
14 | ...BusFault with BFSR.STKERR | 14 | array each of whose elements is a list of the interrupt IDs on the |
15 | ...taking pending nonsecure exception 3 | 15 | combiner which must be tied together. As we loop through each |
16 | ...loading from element 3 of non-secure vector table at 0xc | 16 | interrupt ID, if we find that it is the first one in one of these |
17 | ...loaded new PC 0x20000558 | 17 | lists, we configure the splitter device with eonugh extra outputs and |
18 | ---------------- | 18 | wire them up to the other interrupt IDs in the list. |
19 | IN: | 19 | |
20 | 0x20000558: 08000079 stmdaeq r0, {r0, r3, r4, r5, r6} | 20 | Conveniently, for all the cases where this is necessary, the |
21 | 21 | lowest-numbered interrupt ID in each group is in the range of the | |
22 | (The double reset logging is the result of our long-standing | 22 | external combiner, so we only need to code for this in the first of |
23 | "CPUs all get reset twice" weirdness; it looks a bit ugly | 23 | the two loops in exynos4210_init_board_irqs(). |
24 | but it'll go away if we ever fix that :-)) | 24 | |
25 | The old code in exynos4210_combiner_get_gpioin() which is being | ||
26 | deleted here had several problems which don't exist in the new code | ||
27 | in its handling of the multi-core timer interrupts: | ||
28 | (1) the case labels specified bits 4 ... 8, but bit '8' doesn't | ||
29 | exist; these should have been 4 ... 7 | ||
30 | (2) it used the input irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)] | ||
31 | multiple times as the input of several different splitters, | ||
32 | which isn't allowed | ||
33 | (3) in an apparent cut-and-paste error, the cases for all the | ||
34 | multi-core timer inputs used "bit + 4" even though the | ||
35 | bit range for the case was (intended to be) 4 ... 7, which | ||
36 | meant it was looking at non-existent bits 8 ... 11. | ||
37 | None of these exist in the new code. | ||
25 | 38 | ||
26 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 39 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
27 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
28 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 40 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
29 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 41 | Message-id: 20220404154658.565020-17-peter.maydell@linaro.org |
30 | Message-id: 20220315204306.2797684-2-peter.maydell@linaro.org | ||
31 | --- | 42 | --- |
32 | target/arm/cpu.c | 5 +++++ | 43 | include/hw/arm/exynos4210.h | 6 +- |
33 | target/arm/m_helper.c | 5 +++++ | 44 | hw/arm/exynos4210.c | 178 +++++++++++++++++++++++------------- |
34 | 2 files changed, 10 insertions(+) | 45 | 2 files changed, 119 insertions(+), 65 deletions(-) |
35 | 46 | ||
36 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 47 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h |
37 | index XXXXXXX..XXXXXXX 100644 | 48 | index XXXXXXX..XXXXXXX 100644 |
38 | --- a/target/arm/cpu.c | 49 | --- a/include/hw/arm/exynos4210.h |
39 | +++ b/target/arm/cpu.c | 50 | +++ b/include/hw/arm/exynos4210.h |
40 | @@ -XXX,XX +XXX,XX @@ | 51 | @@ -XXX,XX +XXX,XX @@ |
41 | #include "qemu/osdep.h" | 52 | |
42 | #include "qemu/qemu-print.h" | 53 | /* |
43 | #include "qemu/timer.h" | 54 | * We need one splitter for every external combiner input, plus |
44 | +#include "qemu/log.h" | 55 | - * one for every non-zero entry in combiner_grp_to_gic_id[]. |
45 | #include "qemu-common.h" | 56 | + * one for every non-zero entry in combiner_grp_to_gic_id[], |
46 | #include "target/arm/idau.h" | 57 | + * minus one for every external combiner ID in second or later |
47 | #include "qemu/module.h" | 58 | + * places in a combinermap[] line. |
48 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev) | 59 | * We'll assert in exynos4210_init_board_irqs() if this is wrong. |
49 | initial_pc = ldl_phys(s->as, vecbase + 4); | 60 | */ |
61 | -#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 54) | ||
62 | +#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38) | ||
63 | |||
64 | typedef struct Exynos4210Irq { | ||
65 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
66 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | ||
68 | --- a/hw/arm/exynos4210.c | ||
69 | +++ b/hw/arm/exynos4210.c | ||
70 | @@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
71 | #define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ | ||
72 | ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) | ||
73 | |||
74 | +/* | ||
75 | + * Some interrupt lines go to multiple combiner inputs. | ||
76 | + * This data structure defines those: each array element is | ||
77 | + * a list of combiner inputs which are connected together; | ||
78 | + * the one with the smallest interrupt ID value must be first. | ||
79 | + * As with combiner_grp_to_gic_id[], we rely on (0, 0) not being | ||
80 | + * wired to anything so we can use 0 as a terminator. | ||
81 | + */ | ||
82 | +#define IRQNO(G, B) EXYNOS4210_COMBINER_GET_IRQ_NUM(G, B) | ||
83 | +#define IRQNONE 0 | ||
84 | + | ||
85 | +#define COMBINERMAP_SIZE 16 | ||
86 | + | ||
87 | +static const int combinermap[COMBINERMAP_SIZE][6] = { | ||
88 | + /* MDNIE_LCD1 */ | ||
89 | + { IRQNO(0, 4), IRQNO(1, 0), IRQNONE }, | ||
90 | + { IRQNO(0, 5), IRQNO(1, 1), IRQNONE }, | ||
91 | + { IRQNO(0, 6), IRQNO(1, 2), IRQNONE }, | ||
92 | + { IRQNO(0, 7), IRQNO(1, 3), IRQNONE }, | ||
93 | + /* TMU */ | ||
94 | + { IRQNO(2, 4), IRQNO(3, 4), IRQNONE }, | ||
95 | + { IRQNO(2, 5), IRQNO(3, 5), IRQNONE }, | ||
96 | + { IRQNO(2, 6), IRQNO(3, 6), IRQNONE }, | ||
97 | + { IRQNO(2, 7), IRQNO(3, 7), IRQNONE }, | ||
98 | + /* LCD1 */ | ||
99 | + { IRQNO(11, 4), IRQNO(12, 0), IRQNONE }, | ||
100 | + { IRQNO(11, 5), IRQNO(12, 1), IRQNONE }, | ||
101 | + { IRQNO(11, 6), IRQNO(12, 2), IRQNONE }, | ||
102 | + { IRQNO(11, 7), IRQNO(12, 3), IRQNONE }, | ||
103 | + /* Multi-core timer */ | ||
104 | + { IRQNO(1, 4), IRQNO(12, 4), IRQNO(35, 4), IRQNO(51, 4), IRQNO(53, 4), IRQNONE }, | ||
105 | + { IRQNO(1, 5), IRQNO(12, 5), IRQNO(35, 5), IRQNO(51, 5), IRQNO(53, 5), IRQNONE }, | ||
106 | + { IRQNO(1, 6), IRQNO(12, 6), IRQNO(35, 6), IRQNO(51, 6), IRQNO(53, 6), IRQNONE }, | ||
107 | + { IRQNO(1, 7), IRQNO(12, 7), IRQNO(35, 7), IRQNO(51, 7), IRQNO(53, 7), IRQNONE }, | ||
108 | +}; | ||
109 | + | ||
110 | +#undef IRQNO | ||
111 | + | ||
112 | +static const int *combinermap_entry(int irq) | ||
113 | +{ | ||
114 | + /* | ||
115 | + * If the interrupt number passed in is the first entry in some | ||
116 | + * line of the combinermap, return a pointer to that line; | ||
117 | + * otherwise return NULL. | ||
118 | + */ | ||
119 | + int i; | ||
120 | + for (i = 0; i < COMBINERMAP_SIZE; i++) { | ||
121 | + if (combinermap[i][0] == irq) { | ||
122 | + return combinermap[i]; | ||
123 | + } | ||
124 | + } | ||
125 | + return NULL; | ||
126 | +} | ||
127 | + | ||
128 | +static int mapline_size(const int *mapline) | ||
129 | +{ | ||
130 | + /* Return number of entries in this mapline in total */ | ||
131 | + int i = 0; | ||
132 | + | ||
133 | + if (!mapline) { | ||
134 | + /* Not in the map? IRQ goes to exactly one combiner input */ | ||
135 | + return 1; | ||
136 | + } | ||
137 | + while (*mapline != IRQNONE) { | ||
138 | + mapline++; | ||
139 | + i++; | ||
140 | + } | ||
141 | + return i; | ||
142 | +} | ||
143 | + | ||
144 | /* | ||
145 | * Initialize board IRQs. | ||
146 | * These IRQs contain splitted Int/External Combiner and External Gic IRQs. | ||
147 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
148 | DeviceState *extgicdev = DEVICE(&s->ext_gic); | ||
149 | int splitcount = 0; | ||
150 | DeviceState *splitter; | ||
151 | + const int *mapline; | ||
152 | + int numlines, splitin, in; | ||
153 | |||
154 | for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { | ||
155 | irq_id = 0; | ||
156 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
157 | irq_id = EXT_GIC_ID_MCT_G1; | ||
50 | } | 158 | } |
51 | 159 | ||
52 | + qemu_log_mask(CPU_LOG_INT, | 160 | + if (s->irq_table[n]) { |
53 | + "Loaded reset SP 0x%x PC 0x%x from vector table\n", | 161 | + /* |
54 | + initial_msp, initial_pc); | 162 | + * This must be some non-first entry in a combinermap line, |
55 | + | 163 | + * and we've already filled it in. |
56 | env->regs[13] = initial_msp & 0xFFFFFFFC; | 164 | + */ |
57 | env->regs[15] = initial_pc & ~1; | 165 | + continue; |
58 | env->thumb = initial_pc & 1; | 166 | + } |
59 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | 167 | + mapline = combinermap_entry(n); |
60 | index XXXXXXX..XXXXXXX 100644 | 168 | + /* |
61 | --- a/target/arm/m_helper.c | 169 | + * We need to connect the IRQ to multiple inputs on both combiners |
62 | +++ b/target/arm/m_helper.c | 170 | + * and possibly also to the external GIC. |
63 | @@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure, | 171 | + */ |
64 | ARMMMUIdx mmu_idx; | 172 | + numlines = 2 * mapline_size(mapline); |
65 | bool exc_secure; | 173 | + if (irq_id) { |
66 | 174 | + numlines++; | |
67 | + qemu_log_mask(CPU_LOG_INT, | 175 | + } |
68 | + "...loading from element %d of %s vector table at 0x%x\n", | 176 | assert(splitcount < EXYNOS4210_NUM_SPLITTERS); |
69 | + exc, targets_secure ? "secure" : "non-secure", addr); | 177 | splitter = DEVICE(&s->splitter[splitcount]); |
70 | + | 178 | - qdev_prop_set_uint16(splitter, "num-lines", irq_id ? 3 : 2); |
71 | mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, targets_secure, true); | 179 | + qdev_prop_set_uint16(splitter, "num-lines", numlines); |
72 | 180 | qdev_realize(splitter, NULL, &error_abort); | |
73 | /* | 181 | splitcount++; |
74 | @@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure, | 182 | - s->irq_table[n] = qdev_get_gpio_in(splitter, 0); |
75 | goto load_fail; | 183 | - qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); |
184 | - qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]); | ||
185 | + | ||
186 | + in = n; | ||
187 | + splitin = 0; | ||
188 | + for (;;) { | ||
189 | + s->irq_table[in] = qdev_get_gpio_in(splitter, 0); | ||
190 | + qdev_connect_gpio_out(splitter, splitin, is->int_combiner_irq[in]); | ||
191 | + qdev_connect_gpio_out(splitter, splitin + 1, is->ext_combiner_irq[in]); | ||
192 | + splitin += 2; | ||
193 | + if (!mapline) { | ||
194 | + break; | ||
195 | + } | ||
196 | + mapline++; | ||
197 | + in = *mapline; | ||
198 | + if (in == IRQNONE) { | ||
199 | + break; | ||
200 | + } | ||
201 | + } | ||
202 | if (irq_id) { | ||
203 | - qdev_connect_gpio_out(splitter, 2, | ||
204 | + qdev_connect_gpio_out(splitter, splitin, | ||
205 | qdev_get_gpio_in(extgicdev, irq_id - 32)); | ||
206 | } | ||
76 | } | 207 | } |
77 | *pvec = vector_entry; | 208 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) |
78 | + qemu_log_mask(CPU_LOG_INT, "...loaded new PC 0x%x\n", *pvec); | 209 | irq_id = combiner_grp_to_gic_id[grp - |
79 | return true; | 210 | EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; |
80 | 211 | ||
81 | load_fail: | 212 | + if (s->irq_table[n]) { |
213 | + /* | ||
214 | + * This must be some non-first entry in a combinermap line, | ||
215 | + * and we've already filled it in. | ||
216 | + */ | ||
217 | + continue; | ||
218 | + } | ||
219 | + | ||
220 | if (irq_id) { | ||
221 | assert(splitcount < EXYNOS4210_NUM_SPLITTERS); | ||
222 | splitter = DEVICE(&s->splitter[splitcount]); | ||
223 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, | ||
224 | DeviceState *dev, int ext) | ||
225 | { | ||
226 | int n; | ||
227 | - int bit; | ||
228 | int max; | ||
229 | qemu_irq *irq; | ||
230 | |||
231 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, | ||
232 | EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; | ||
233 | irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq; | ||
234 | |||
235 | - /* | ||
236 | - * Some IRQs of Int/External Combiner are going to two Combiners groups, | ||
237 | - * so let split them. | ||
238 | - */ | ||
239 | for (n = 0; n < max; n++) { | ||
240 | - | ||
241 | - bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); | ||
242 | - | ||
243 | - switch (n) { | ||
244 | - /* MDNIE_LCD1 INTG1 */ | ||
245 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ... | ||
246 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3): | ||
247 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
248 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]); | ||
249 | - continue; | ||
250 | - | ||
251 | - /* TMU INTG3 */ | ||
252 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4): | ||
253 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
254 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]); | ||
255 | - continue; | ||
256 | - | ||
257 | - /* LCD1 INTG12 */ | ||
258 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ... | ||
259 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3): | ||
260 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
261 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]); | ||
262 | - continue; | ||
263 | - | ||
264 | - /* Multi-Core Timer INTG12 */ | ||
265 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ... | ||
266 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8): | ||
267 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
268 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
269 | - continue; | ||
270 | - | ||
271 | - /* Multi-Core Timer INTG35 */ | ||
272 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ... | ||
273 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8): | ||
274 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
275 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
276 | - continue; | ||
277 | - | ||
278 | - /* Multi-Core Timer INTG51 */ | ||
279 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ... | ||
280 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8): | ||
281 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
282 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
283 | - continue; | ||
284 | - | ||
285 | - /* Multi-Core Timer INTG53 */ | ||
286 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ... | ||
287 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8): | ||
288 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
289 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
290 | - continue; | ||
291 | - } | ||
292 | - | ||
293 | irq[n] = qdev_get_gpio_in(dev, n); | ||
294 | } | ||
295 | } | ||
82 | -- | 296 | -- |
83 | 2.25.1 | 297 | 2.25.1 |
84 | |||
85 | diff view generated by jsdifflib |
1 | From: Andrew Deason <adeason@sinenomine.net> | 1 | Switch the creation of the combiner devices to the new-style |
---|---|---|---|
2 | "embedded in state struct" approach, so we can easily refer | ||
3 | to the object elsewhere during realize. | ||
2 | 4 | ||
3 | On older Solaris releases (before Solaris 11), we didn't get a | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | prototype for madvise, and so util/osdep.c provides its own prototype. | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Some time between the public Solaris 11.4 release and Solaris 11.4.42 | 7 | Message-id: 20220404154658.565020-18-peter.maydell@linaro.org |
6 | CBE, we started getting an madvise prototype that looks like this: | 8 | --- |
9 | include/hw/arm/exynos4210.h | 3 ++ | ||
10 | include/hw/intc/exynos4210_combiner.h | 57 +++++++++++++++++++++++++++ | ||
11 | hw/arm/exynos4210.c | 20 +++++----- | ||
12 | hw/intc/exynos4210_combiner.c | 31 +-------------- | ||
13 | 4 files changed, 72 insertions(+), 39 deletions(-) | ||
14 | create mode 100644 include/hw/intc/exynos4210_combiner.h | ||
7 | 15 | ||
8 | extern int madvise(void *, size_t, int); | 16 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h |
9 | |||
10 | which conflicts with the prototype in util/osdeps.c. Instead of always | ||
11 | declaring this prototype, check if we're missing the madvise() | ||
12 | prototype, and only declare it ourselves if the prototype is missing. | ||
13 | Move the prototype to include/qemu/osdep.h, the normal place to handle | ||
14 | platform-specific header quirks. | ||
15 | |||
16 | The 'missing_madvise_proto' meson check contains an obviously wrong | ||
17 | prototype for madvise. So if that code compiles and links, we must be | ||
18 | missing the actual prototype for madvise. | ||
19 | |||
20 | Signed-off-by: Andrew Deason <adeason@sinenomine.net> | ||
21 | Message-id: 20220316035227.3702-2-adeason@sinenomine.net | ||
22 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
24 | --- | ||
25 | meson.build | 23 +++++++++++++++++++++-- | ||
26 | include/qemu/osdep.h | 8 ++++++++ | ||
27 | util/osdep.c | 3 --- | ||
28 | 3 files changed, 29 insertions(+), 5 deletions(-) | ||
29 | |||
30 | diff --git a/meson.build b/meson.build | ||
31 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
32 | --- a/meson.build | 18 | --- a/include/hw/arm/exynos4210.h |
33 | +++ b/meson.build | 19 | +++ b/include/hw/arm/exynos4210.h |
34 | @@ -XXX,XX +XXX,XX @@ config_host_data.set('CONFIG_FDATASYNC', cc.links(gnu_source_prefix + ''' | 20 | @@ -XXX,XX +XXX,XX @@ |
35 | #error Not supported | 21 | #include "hw/sysbus.h" |
36 | #endif | 22 | #include "hw/cpu/a9mpcore.h" |
37 | }''')) | 23 | #include "hw/intc/exynos4210_gic.h" |
38 | -config_host_data.set('CONFIG_MADVISE', cc.links(gnu_source_prefix + ''' | 24 | +#include "hw/intc/exynos4210_combiner.h" |
25 | #include "hw/core/split-irq.h" | ||
26 | #include "target/arm/cpu-qom.h" | ||
27 | #include "qom/object.h" | ||
28 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { | ||
29 | qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; | ||
30 | A9MPPrivState a9mpcore; | ||
31 | Exynos4210GicState ext_gic; | ||
32 | + Exynos4210CombinerState int_combiner; | ||
33 | + Exynos4210CombinerState ext_combiner; | ||
34 | SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS]; | ||
35 | }; | ||
36 | |||
37 | diff --git a/include/hw/intc/exynos4210_combiner.h b/include/hw/intc/exynos4210_combiner.h | ||
38 | new file mode 100644 | ||
39 | index XXXXXXX..XXXXXXX | ||
40 | --- /dev/null | ||
41 | +++ b/include/hw/intc/exynos4210_combiner.h | ||
42 | @@ -XXX,XX +XXX,XX @@ | ||
43 | +/* | ||
44 | + * Samsung exynos4210 Interrupt Combiner | ||
45 | + * | ||
46 | + * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. | ||
47 | + * All rights reserved. | ||
48 | + * | ||
49 | + * Evgeny Voevodin <e.voevodin@samsung.com> | ||
50 | + * | ||
51 | + * This program is free software; you can redistribute it and/or modify it | ||
52 | + * under the terms of the GNU General Public License as published by the | ||
53 | + * Free Software Foundation; either version 2 of the License, or (at your | ||
54 | + * option) any later version. | ||
55 | + * | ||
56 | + * This program is distributed in the hope that it will be useful, | ||
57 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
58 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | ||
59 | + * See the GNU General Public License for more details. | ||
60 | + * | ||
61 | + * You should have received a copy of the GNU General Public License along | ||
62 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
63 | + */ | ||
39 | + | 64 | + |
40 | +has_madvise = cc.links(gnu_source_prefix + ''' | 65 | +#ifndef HW_INTC_EXYNOS4210_COMBINER |
41 | #include <sys/types.h> | 66 | +#define HW_INTC_EXYNOS4210_COMBINER |
42 | #include <sys/mman.h> | ||
43 | #include <stddef.h> | ||
44 | - int main(void) { return madvise(NULL, 0, MADV_DONTNEED); }''')) | ||
45 | + int main(void) { return madvise(NULL, 0, MADV_DONTNEED); }''') | ||
46 | +missing_madvise_proto = false | ||
47 | +if has_madvise | ||
48 | + # Some platforms (illumos and Solaris before Solaris 11) provide madvise() | ||
49 | + # but forget to prototype it. In this case, has_madvise will be true (the | ||
50 | + # test program links despite a compile warning). To detect the | ||
51 | + # missing-prototype case, we try again with a definitely-bogus prototype. | ||
52 | + # This will only compile if the system headers don't provide the prototype; | ||
53 | + # otherwise the conflicting prototypes will cause a compiler error. | ||
54 | + missing_madvise_proto = cc.links(gnu_source_prefix + ''' | ||
55 | + #include <sys/types.h> | ||
56 | + #include <sys/mman.h> | ||
57 | + #include <stddef.h> | ||
58 | + extern int madvise(int); | ||
59 | + int main(void) { return madvise(0); }''') | ||
60 | +endif | ||
61 | +config_host_data.set('CONFIG_MADVISE', has_madvise) | ||
62 | +config_host_data.set('HAVE_MADVISE_WITHOUT_PROTOTYPE', missing_madvise_proto) | ||
63 | + | 67 | + |
64 | config_host_data.set('CONFIG_MEMFD', cc.links(gnu_source_prefix + ''' | 68 | +#include "hw/sysbus.h" |
65 | #include <sys/mman.h> | 69 | + |
66 | int main(void) { return memfd_create("foo", MFD_ALLOW_SEALING); }''')) | 70 | +/* |
67 | diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h | 71 | + * State for each output signal of internal combiner |
72 | + */ | ||
73 | +typedef struct CombinerGroupState { | ||
74 | + uint8_t src_mask; /* 1 - source enabled, 0 - disabled */ | ||
75 | + uint8_t src_pending; /* Pending source interrupts before masking */ | ||
76 | +} CombinerGroupState; | ||
77 | + | ||
78 | +#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner" | ||
79 | +OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210CombinerState, EXYNOS4210_COMBINER) | ||
80 | + | ||
81 | +/* Number of groups and total number of interrupts for the internal combiner */ | ||
82 | +#define IIC_NGRP 64 | ||
83 | +#define IIC_NIRQ (IIC_NGRP * 8) | ||
84 | +#define IIC_REGSET_SIZE 0x41 | ||
85 | + | ||
86 | +struct Exynos4210CombinerState { | ||
87 | + SysBusDevice parent_obj; | ||
88 | + | ||
89 | + MemoryRegion iomem; | ||
90 | + | ||
91 | + struct CombinerGroupState group[IIC_NGRP]; | ||
92 | + uint32_t reg_set[IIC_REGSET_SIZE]; | ||
93 | + uint32_t icipsr[2]; | ||
94 | + uint32_t external; /* 1 means that this combiner is external */ | ||
95 | + | ||
96 | + qemu_irq output_irq[IIC_NGRP]; | ||
97 | +}; | ||
98 | + | ||
99 | +#endif | ||
100 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
68 | index XXXXXXX..XXXXXXX 100644 | 101 | index XXXXXXX..XXXXXXX 100644 |
69 | --- a/include/qemu/osdep.h | 102 | --- a/hw/arm/exynos4210.c |
70 | +++ b/include/qemu/osdep.h | 103 | +++ b/hw/arm/exynos4210.c |
71 | @@ -XXX,XX +XXX,XX @@ void qemu_anon_ram_free(void *ptr, size_t size); | 104 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) |
72 | #define SIGIO SIGPOLL | 105 | } |
106 | |||
107 | /* Internal Interrupt Combiner */ | ||
108 | - dev = qdev_new("exynos4210.combiner"); | ||
109 | - busdev = SYS_BUS_DEVICE(dev); | ||
110 | - sysbus_realize_and_unref(busdev, &error_fatal); | ||
111 | + busdev = SYS_BUS_DEVICE(&s->int_combiner); | ||
112 | + sysbus_realize(busdev, &error_fatal); | ||
113 | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { | ||
114 | sysbus_connect_irq(busdev, n, | ||
115 | qdev_get_gpio_in(DEVICE(&s->a9mpcore), n)); | ||
116 | } | ||
117 | - exynos4210_combiner_get_gpioin(&s->irqs, dev, 0); | ||
118 | + exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->int_combiner), 0); | ||
119 | sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); | ||
120 | |||
121 | /* External Interrupt Combiner */ | ||
122 | - dev = qdev_new("exynos4210.combiner"); | ||
123 | - qdev_prop_set_uint32(dev, "external", 1); | ||
124 | - busdev = SYS_BUS_DEVICE(dev); | ||
125 | - sysbus_realize_and_unref(busdev, &error_fatal); | ||
126 | + qdev_prop_set_uint32(DEVICE(&s->ext_combiner), "external", 1); | ||
127 | + busdev = SYS_BUS_DEVICE(&s->ext_combiner); | ||
128 | + sysbus_realize(busdev, &error_fatal); | ||
129 | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { | ||
130 | sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n)); | ||
131 | } | ||
132 | - exynos4210_combiner_get_gpioin(&s->irqs, dev, 1); | ||
133 | + exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->ext_combiner), 1); | ||
134 | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); | ||
135 | |||
136 | /* Initialize board IRQs. */ | ||
137 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj) | ||
138 | |||
139 | object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); | ||
140 | object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC); | ||
141 | + object_initialize_child(obj, "int-combiner", &s->int_combiner, | ||
142 | + TYPE_EXYNOS4210_COMBINER); | ||
143 | + object_initialize_child(obj, "ext-combiner", &s->ext_combiner, | ||
144 | + TYPE_EXYNOS4210_COMBINER); | ||
145 | } | ||
146 | |||
147 | static void exynos4210_class_init(ObjectClass *klass, void *data) | ||
148 | diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c | ||
149 | index XXXXXXX..XXXXXXX 100644 | ||
150 | --- a/hw/intc/exynos4210_combiner.c | ||
151 | +++ b/hw/intc/exynos4210_combiner.c | ||
152 | @@ -XXX,XX +XXX,XX @@ | ||
153 | #include "hw/sysbus.h" | ||
154 | #include "migration/vmstate.h" | ||
155 | #include "qemu/module.h" | ||
156 | - | ||
157 | +#include "hw/intc/exynos4210_combiner.h" | ||
158 | #include "hw/arm/exynos4210.h" | ||
159 | #include "hw/hw.h" | ||
160 | #include "hw/irq.h" | ||
161 | @@ -XXX,XX +XXX,XX @@ | ||
162 | #define DPRINTF(fmt, ...) do {} while (0) | ||
73 | #endif | 163 | #endif |
74 | 164 | ||
75 | +#ifdef HAVE_MADVISE_WITHOUT_PROTOTYPE | 165 | -#define IIC_NGRP 64 /* Internal Interrupt Combiner |
76 | +/* | 166 | - Groups number */ |
77 | + * See MySQL bug #7156 (http://bugs.mysql.com/bug.php?id=7156) for discussion | 167 | -#define IIC_NIRQ (IIC_NGRP * 8)/* Internal Interrupt Combiner |
78 | + * about Solaris missing the madvise() prototype. | 168 | - Interrupts number */ |
79 | + */ | 169 | #define IIC_REGION_SIZE 0x108 /* Size of memory mapped region */ |
80 | +extern int madvise(char *, size_t, int); | 170 | -#define IIC_REGSET_SIZE 0x41 |
81 | +#endif | 171 | - |
82 | + | 172 | -/* |
83 | #if defined(CONFIG_LINUX) | 173 | - * State for each output signal of internal combiner |
84 | #ifndef BUS_MCEERR_AR | 174 | - */ |
85 | #define BUS_MCEERR_AR 4 | 175 | -typedef struct CombinerGroupState { |
86 | diff --git a/util/osdep.c b/util/osdep.c | 176 | - uint8_t src_mask; /* 1 - source enabled, 0 - disabled */ |
87 | index XXXXXXX..XXXXXXX 100644 | 177 | - uint8_t src_pending; /* Pending source interrupts before masking */ |
88 | --- a/util/osdep.c | 178 | -} CombinerGroupState; |
89 | +++ b/util/osdep.c | 179 | - |
90 | @@ -XXX,XX +XXX,XX @@ | 180 | -#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner" |
91 | 181 | -OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210CombinerState, EXYNOS4210_COMBINER) | |
92 | #ifdef CONFIG_SOLARIS | 182 | - |
93 | #include <sys/statvfs.h> | 183 | -struct Exynos4210CombinerState { |
94 | -/* See MySQL bug #7156 (http://bugs.mysql.com/bug.php?id=7156) for | 184 | - SysBusDevice parent_obj; |
95 | - discussion about Solaris header problems */ | 185 | - |
96 | -extern int madvise(char *, size_t, int); | 186 | - MemoryRegion iomem; |
97 | #endif | 187 | - |
98 | 188 | - struct CombinerGroupState group[IIC_NGRP]; | |
99 | #include "qemu-common.h" | 189 | - uint32_t reg_set[IIC_REGSET_SIZE]; |
190 | - uint32_t icipsr[2]; | ||
191 | - uint32_t external; /* 1 means that this combiner is external */ | ||
192 | - | ||
193 | - qemu_irq output_irq[IIC_NGRP]; | ||
194 | -}; | ||
195 | |||
196 | static const VMStateDescription vmstate_exynos4210_combiner_group_state = { | ||
197 | .name = "exynos4210.combiner.groupstate", | ||
100 | -- | 198 | -- |
101 | 2.25.1 | 199 | 2.25.1 | diff view generated by jsdifflib |
1 | LPAE descriptors come in three forms: | 1 | The only time we use the int_combiner_irq[] and ext_combiner_irq[] |
---|---|---|---|
2 | arrays in the Exynos4210Irq struct is during realize of the SoC -- we | ||
3 | initialize them with the input IRQs of the combiner devices, and then | ||
4 | connect those to outputs of other devices in | ||
5 | exynos4210_init_board_irqs(). Now that the combiner objects are | ||
6 | easily accessible as s->int_combiner and s->ext_combiner we can make | ||
7 | the connections directly from one device to the other without going | ||
8 | via these arrays. | ||
2 | 9 | ||
3 | * table descriptors, giving the address of the next level page table | 10 | Since these are the only two remaining elements of Exynos4210Irq, |
4 | * page descriptors, which occur only at level 3 and describe the | 11 | we can remove that struct entirely. |
5 | mapping of one page (which might be 4K, 16K or 64K) | ||
6 | * block descriptors, which occur at higher page table levels, and | ||
7 | describe the mapping of huge pages | ||
8 | 12 | ||
9 | QEMU's page-table-walk code treats block and page entries | ||
10 | identically, simply ORing in a number of bits from the input virtual | ||
11 | address that depends on the level of the page table that we stopped | ||
12 | at; we depend on the previous masking of descaddr with descaddrmask | ||
13 | to have already cleared out the low bits of the descriptor word. | ||
14 | |||
15 | This is not quite right: the address field in a block descriptor is | ||
16 | smaller, and so there are bits which are valid address bits in a page | ||
17 | descriptor or a table descriptor but which are not supposed to be | ||
18 | part of the address in a block descriptor, and descaddrmask does not | ||
19 | clear them. We previously mostly got away with this because those | ||
20 | descriptor bits are RES0; however with FEAT_BBM (part of Armv8.4) | ||
21 | block descriptor bit 16 is defined to be the nT bit. No emulated | ||
22 | QEMU CPU has FEAT_BBM yet, but if the host CPU has it then we might | ||
23 | see it when using KVM or hvf. | ||
24 | |||
25 | Explicitly zero out all the descaddr bits we're about to OR vaddr | ||
26 | bits into. | ||
27 | |||
28 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/790 | ||
29 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
30 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
31 | Message-id: 20220304165628.2345765-1-peter.maydell@linaro.org | 15 | Message-id: 20220404154658.565020-19-peter.maydell@linaro.org |
32 | --- | 16 | --- |
33 | target/arm/helper.c | 10 ++++++++-- | 17 | include/hw/arm/exynos4210.h | 6 ------ |
34 | 1 file changed, 8 insertions(+), 2 deletions(-) | 18 | hw/arm/exynos4210.c | 34 ++++++++-------------------------- |
19 | 2 files changed, 8 insertions(+), 32 deletions(-) | ||
35 | 20 | ||
36 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 21 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h |
37 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
38 | --- a/target/arm/helper.c | 23 | --- a/include/hw/arm/exynos4210.h |
39 | +++ b/target/arm/helper.c | 24 | +++ b/include/hw/arm/exynos4210.h |
40 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, | 25 | @@ -XXX,XX +XXX,XX @@ |
41 | indexmask = indexmask_grainsize; | 26 | */ |
42 | continue; | 27 | #define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38) |
28 | |||
29 | -typedef struct Exynos4210Irq { | ||
30 | - qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
31 | - qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; | ||
32 | -} Exynos4210Irq; | ||
33 | - | ||
34 | struct Exynos4210State { | ||
35 | /*< private >*/ | ||
36 | SysBusDevice parent_obj; | ||
37 | /*< public >*/ | ||
38 | ARMCPU *cpu[EXYNOS4210_NCPUS]; | ||
39 | - Exynos4210Irq irqs; | ||
40 | qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
41 | |||
42 | MemoryRegion chipid_mem; | ||
43 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/hw/arm/exynos4210.c | ||
46 | +++ b/hw/arm/exynos4210.c | ||
47 | @@ -XXX,XX +XXX,XX @@ static int mapline_size(const int *mapline) | ||
48 | static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
49 | { | ||
50 | uint32_t grp, bit, irq_id, n; | ||
51 | - Exynos4210Irq *is = &s->irqs; | ||
52 | DeviceState *extgicdev = DEVICE(&s->ext_gic); | ||
53 | + DeviceState *intcdev = DEVICE(&s->int_combiner); | ||
54 | + DeviceState *extcdev = DEVICE(&s->ext_combiner); | ||
55 | int splitcount = 0; | ||
56 | DeviceState *splitter; | ||
57 | const int *mapline; | ||
58 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
59 | splitin = 0; | ||
60 | for (;;) { | ||
61 | s->irq_table[in] = qdev_get_gpio_in(splitter, 0); | ||
62 | - qdev_connect_gpio_out(splitter, splitin, is->int_combiner_irq[in]); | ||
63 | - qdev_connect_gpio_out(splitter, splitin + 1, is->ext_combiner_irq[in]); | ||
64 | + qdev_connect_gpio_out(splitter, splitin, | ||
65 | + qdev_get_gpio_in(intcdev, in)); | ||
66 | + qdev_connect_gpio_out(splitter, splitin + 1, | ||
67 | + qdev_get_gpio_in(extcdev, in)); | ||
68 | splitin += 2; | ||
69 | if (!mapline) { | ||
70 | break; | ||
71 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
72 | qdev_realize(splitter, NULL, &error_abort); | ||
73 | splitcount++; | ||
74 | s->irq_table[n] = qdev_get_gpio_in(splitter, 0); | ||
75 | - qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); | ||
76 | + qdev_connect_gpio_out(splitter, 0, qdev_get_gpio_in(intcdev, n)); | ||
77 | qdev_connect_gpio_out(splitter, 1, | ||
78 | qdev_get_gpio_in(extgicdev, irq_id - 32)); | ||
79 | } else { | ||
80 | - s->irq_table[n] = is->int_combiner_irq[n]; | ||
81 | + s->irq_table[n] = qdev_get_gpio_in(intcdev, n); | ||
43 | } | 82 | } |
44 | - /* Block entry at level 1 or 2, or page entry at level 3. | 83 | } |
45 | + /* | 84 | /* |
46 | + * Block entry at level 1 or 2, or page entry at level 3. | 85 | @@ -XXX,XX +XXX,XX @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) |
47 | * These are basically the same thing, although the number | 86 | return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); |
48 | - * of bits we pull in from the vaddr varies. | 87 | } |
49 | + * of bits we pull in from the vaddr varies. Note that although | 88 | |
50 | + * descaddrmask masks enough of the low bits of the descriptor | 89 | -/* |
51 | + * to give a correct page or table address, the address field | 90 | - * Get Combiner input GPIO into irqs structure |
52 | + * in a block descriptor is smaller; so we need to explicitly | 91 | - */ |
53 | + * clear the lower bits here before ORing in the low vaddr bits. | 92 | -static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, |
54 | */ | 93 | - DeviceState *dev, int ext) |
55 | page_size = (1ULL << ((stride * (4 - level)) + 3)); | 94 | -{ |
56 | + descaddr &= ~(page_size - 1); | 95 | - int n; |
57 | descaddr |= (address & (page_size - 1)); | 96 | - int max; |
58 | /* Extract attributes from the descriptor */ | 97 | - qemu_irq *irq; |
59 | attrs = extract64(descriptor, 2, 10) | 98 | - |
99 | - max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ : | ||
100 | - EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; | ||
101 | - irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq; | ||
102 | - | ||
103 | - for (n = 0; n < max; n++) { | ||
104 | - irq[n] = qdev_get_gpio_in(dev, n); | ||
105 | - } | ||
106 | -} | ||
107 | - | ||
108 | static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, | ||
109 | 0x09, 0x00, 0x00, 0x00 }; | ||
110 | |||
111 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
112 | sysbus_connect_irq(busdev, n, | ||
113 | qdev_get_gpio_in(DEVICE(&s->a9mpcore), n)); | ||
114 | } | ||
115 | - exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->int_combiner), 0); | ||
116 | sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); | ||
117 | |||
118 | /* External Interrupt Combiner */ | ||
119 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
120 | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { | ||
121 | sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n)); | ||
122 | } | ||
123 | - exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->ext_combiner), 1); | ||
124 | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); | ||
125 | |||
126 | /* Initialize board IRQs. */ | ||
60 | -- | 127 | -- |
61 | 2.25.1 | 128 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Andrew Deason <adeason@sinenomine.net> | 1 | From: Zongyuan Li <zongyuan.li@smartx.com> |
---|---|---|---|
2 | 2 | ||
3 | On Solaris, 'sun' is #define'd to 1, which causes errors if a variable | 3 | Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com> |
4 | is named 'sun'. Slightly change the name of the var for the Slot User | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Number so we can build on Solaris. | 5 | Message-id: 20220324181557.203805-2-zongyuan.li@smartx.com |
6 | |||
7 | Reviewed-by: Ani Sinha <ani@anisinha.ca> | ||
8 | Signed-off-by: Andrew Deason <adeason@sinenomine.net> | ||
9 | Reviewed-by: Michael S. Tsirkin <mst@redhat.com> | ||
10 | Message-id: 20220316035227.3702-3-adeason@sinenomine.net | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 7 | --- |
13 | hw/i386/acpi-build.c | 4 ++-- | 8 | hw/arm/realview.c | 33 ++++++++++++++++++++++++--------- |
14 | 1 file changed, 2 insertions(+), 2 deletions(-) | 9 | 1 file changed, 24 insertions(+), 9 deletions(-) |
15 | 10 | ||
16 | diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c | 11 | diff --git a/hw/arm/realview.c b/hw/arm/realview.c |
17 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/i386/acpi-build.c | 13 | --- a/hw/arm/realview.c |
19 | +++ b/hw/i386/acpi-build.c | 14 | +++ b/hw/arm/realview.c |
20 | @@ -XXX,XX +XXX,XX @@ Aml *aml_pci_device_dsm(void) | 15 | @@ -XXX,XX +XXX,XX @@ |
21 | Aml *bnum = aml_arg(4); | 16 | #include "hw/sysbus.h" |
22 | Aml *func = aml_arg(2); | 17 | #include "hw/arm/boot.h" |
23 | Aml *rev = aml_arg(1); | 18 | #include "hw/arm/primecell.h" |
24 | - Aml *sun = aml_arg(5); | 19 | +#include "hw/core/split-irq.h" |
25 | + Aml *sunum = aml_arg(5); | 20 | #include "hw/net/lan9118.h" |
26 | 21 | #include "hw/net/smc91c111.h" | |
27 | method = aml_method("PDSM", 6, AML_SERIALIZED); | 22 | #include "hw/pci/pci.h" |
28 | 23 | +#include "hw/qdev-core.h" | |
29 | @@ -XXX,XX +XXX,XX @@ Aml *aml_pci_device_dsm(void) | 24 | #include "net/net.h" |
30 | UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); | 25 | #include "sysemu/sysemu.h" |
31 | ifctx = aml_if(aml_equal(aml_arg(0), UUID)); | 26 | #include "hw/boards.h" |
32 | { | 27 | @@ -XXX,XX +XXX,XX @@ static const int realview_board_id[] = { |
33 | - aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sun), acpi_index)); | 28 | 0x76d |
34 | + aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); | 29 | }; |
35 | ifctx1 = aml_if(aml_equal(func, zero)); | 30 | |
36 | { | 31 | +static void split_irq_from_named(DeviceState *src, const char* outname, |
37 | uint8_t byte_list[1]; | 32 | + qemu_irq out1, qemu_irq out2) { |
33 | + DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ); | ||
34 | + | ||
35 | + qdev_prop_set_uint32(splitter, "num-lines", 2); | ||
36 | + | ||
37 | + qdev_realize_and_unref(splitter, NULL, &error_fatal); | ||
38 | + | ||
39 | + qdev_connect_gpio_out(splitter, 0, out1); | ||
40 | + qdev_connect_gpio_out(splitter, 1, out2); | ||
41 | + qdev_connect_gpio_out_named(src, outname, 0, | ||
42 | + qdev_get_gpio_in(splitter, 0)); | ||
43 | +} | ||
44 | + | ||
45 | static void realview_init(MachineState *machine, | ||
46 | enum realview_board_type board_type) | ||
47 | { | ||
48 | @@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine, | ||
49 | DeviceState *dev, *sysctl, *gpio2, *pl041; | ||
50 | SysBusDevice *busdev; | ||
51 | qemu_irq pic[64]; | ||
52 | - qemu_irq mmc_irq[2]; | ||
53 | PCIBus *pci_bus = NULL; | ||
54 | NICInfo *nd; | ||
55 | DriveInfo *dinfo; | ||
56 | @@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine, | ||
57 | * and the PL061 has them the other way about. Also the card | ||
58 | * detect line is inverted. | ||
59 | */ | ||
60 | - mmc_irq[0] = qemu_irq_split( | ||
61 | - qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), | ||
62 | - qdev_get_gpio_in(gpio2, 1)); | ||
63 | - mmc_irq[1] = qemu_irq_split( | ||
64 | - qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), | ||
65 | - qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); | ||
66 | - qdev_connect_gpio_out_named(dev, "card-read-only", 0, mmc_irq[0]); | ||
67 | - qdev_connect_gpio_out_named(dev, "card-inserted", 0, mmc_irq[1]); | ||
68 | + split_irq_from_named(dev, "card-read-only", | ||
69 | + qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), | ||
70 | + qdev_get_gpio_in(gpio2, 1)); | ||
71 | + | ||
72 | + split_irq_from_named(dev, "card-inserted", | ||
73 | + qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), | ||
74 | + qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); | ||
75 | + | ||
76 | dinfo = drive_get(IF_SD, 0, 0); | ||
77 | if (dinfo) { | ||
78 | DeviceState *card; | ||
38 | -- | 79 | -- |
39 | 2.25.1 | 80 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Andrew Deason <adeason@sinenomine.net> | 1 | From: Zongyuan Li <zongyuan.li@smartx.com> |
---|---|---|---|
2 | 2 | ||
3 | The include for statvfs.h has not been needed since all statvfs calls | 3 | Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com> |
4 | were removed in commit 4a1418e07bdc ("Unbreak large mem support by | ||
5 | removing kqemu"). | ||
6 | |||
7 | The comment mentioning CONFIG_BSD hasn't made sense since an include | ||
8 | for config-host.h was removed in commit aafd75841001 ("util: Clean up | ||
9 | includes"). | ||
10 | |||
11 | Remove this cruft. | ||
12 | |||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Signed-off-by: Andrew Deason <adeason@sinenomine.net> | 5 | Message-id: 20220324181557.203805-3-zongyuan.li@smartx.com |
15 | Message-id: 20220316035227.3702-4-adeason@sinenomine.net | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 7 | --- |
18 | util/osdep.c | 7 ------- | 8 | hw/arm/stellaris.c | 15 +++++++++++++-- |
19 | 1 file changed, 7 deletions(-) | 9 | 1 file changed, 13 insertions(+), 2 deletions(-) |
20 | 10 | ||
21 | diff --git a/util/osdep.c b/util/osdep.c | 11 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c |
22 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/util/osdep.c | 13 | --- a/hw/arm/stellaris.c |
24 | +++ b/util/osdep.c | 14 | +++ b/hw/arm/stellaris.c |
25 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ |
26 | */ | 16 | |
27 | #include "qemu/osdep.h" | 17 | #include "qemu/osdep.h" |
28 | #include "qapi/error.h" | 18 | #include "qapi/error.h" |
29 | - | 19 | +#include "hw/core/split-irq.h" |
30 | -/* Needed early for CONFIG_BSD etc. */ | 20 | #include "hw/sysbus.h" |
31 | - | 21 | #include "hw/sd/sd.h" |
32 | -#ifdef CONFIG_SOLARIS | 22 | #include "hw/ssi/ssi.h" |
33 | -#include <sys/statvfs.h> | 23 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) |
34 | -#endif | 24 | DeviceState *ssddev; |
35 | - | 25 | DriveInfo *dinfo; |
36 | #include "qemu-common.h" | 26 | DeviceState *carddev; |
37 | #include "qemu/cutils.h" | 27 | + DeviceState *gpio_d_splitter; |
38 | #include "qemu/sockets.h" | 28 | BlockBackend *blk; |
29 | |||
30 | /* | ||
31 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) | ||
32 | &error_fatal); | ||
33 | |||
34 | ssddev = ssi_create_peripheral(bus, "ssd0323"); | ||
35 | - gpio_out[GPIO_D][0] = qemu_irq_split( | ||
36 | - qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0), | ||
37 | + | ||
38 | + gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ); | ||
39 | + qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2); | ||
40 | + qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal); | ||
41 | + qdev_connect_gpio_out( | ||
42 | + gpio_d_splitter, 0, | ||
43 | + qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0)); | ||
44 | + qdev_connect_gpio_out( | ||
45 | + gpio_d_splitter, 1, | ||
46 | qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); | ||
47 | + gpio_out[GPIO_D][0] = qdev_get_gpio_in(gpio_d_splitter, 0); | ||
48 | + | ||
49 | gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); | ||
50 | |||
51 | /* Make sure the select pin is high. */ | ||
39 | -- | 52 | -- |
40 | 2.25.1 | 53 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Zongyuan Li <zongyuan.li@smartx.com> |
---|---|---|---|
2 | 2 | ||
3 | When arm_is_el2_enabled was introduced, we missed | 3 | Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com> |
4 | updating pauth_check_trap. | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
5 | 5 | Message-id: 20220324181557.203805-5-zongyuan.li@smartx.com | |
6 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/788 | 6 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/811 |
7 | Fixes: e6ef0169264b ("target/arm: use arm_is_el2_enabled() where applicable") | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
10 | Message-id: 20220315021205.342768-1-richard.henderson@linaro.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 8 | --- |
13 | target/arm/pauth_helper.c | 2 +- | 9 | include/hw/irq.h | 5 ----- |
14 | 1 file changed, 1 insertion(+), 1 deletion(-) | 10 | hw/core/irq.c | 15 --------------- |
11 | 2 files changed, 20 deletions(-) | ||
15 | 12 | ||
16 | diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c | 13 | diff --git a/include/hw/irq.h b/include/hw/irq.h |
17 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/pauth_helper.c | 15 | --- a/include/hw/irq.h |
19 | +++ b/target/arm/pauth_helper.c | 16 | +++ b/include/hw/irq.h |
20 | @@ -XXX,XX +XXX,XX @@ static void QEMU_NORETURN pauth_trap(CPUARMState *env, int target_el, | 17 | @@ -XXX,XX +XXX,XX @@ void qemu_free_irq(qemu_irq irq); |
21 | 18 | /* Returns a new IRQ with opposite polarity. */ | |
22 | static void pauth_check_trap(CPUARMState *env, int el, uintptr_t ra) | 19 | qemu_irq qemu_irq_invert(qemu_irq irq); |
20 | |||
21 | -/* Returns a new IRQ which feeds into both the passed IRQs. | ||
22 | - * It's probably better to use the TYPE_SPLIT_IRQ device instead. | ||
23 | - */ | ||
24 | -qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2); | ||
25 | - | ||
26 | /* For internal use in qtest. Similar to qemu_irq_split, but operating | ||
27 | on an existing vector of qemu_irq. */ | ||
28 | void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n); | ||
29 | diff --git a/hw/core/irq.c b/hw/core/irq.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/hw/core/irq.c | ||
32 | +++ b/hw/core/irq.c | ||
33 | @@ -XXX,XX +XXX,XX @@ qemu_irq qemu_irq_invert(qemu_irq irq) | ||
34 | return qemu_allocate_irq(qemu_notirq, irq, 0); | ||
35 | } | ||
36 | |||
37 | -static void qemu_splitirq(void *opaque, int line, int level) | ||
38 | -{ | ||
39 | - struct IRQState **irq = opaque; | ||
40 | - irq[0]->handler(irq[0]->opaque, irq[0]->n, level); | ||
41 | - irq[1]->handler(irq[1]->opaque, irq[1]->n, level); | ||
42 | -} | ||
43 | - | ||
44 | -qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2) | ||
45 | -{ | ||
46 | - qemu_irq *s = g_new0(qemu_irq, 2); | ||
47 | - s[0] = irq1; | ||
48 | - s[1] = irq2; | ||
49 | - return qemu_allocate_irq(qemu_splitirq, s, 0); | ||
50 | -} | ||
51 | - | ||
52 | void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n) | ||
23 | { | 53 | { |
24 | - if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { | 54 | int i; |
25 | + if (el < 2 && arm_is_el2_enabled(env)) { | ||
26 | uint64_t hcr = arm_hcr_el2_eff(env); | ||
27 | bool trap = !(hcr & HCR_API); | ||
28 | if (el == 0) { | ||
29 | -- | 55 | -- |
30 | 2.25.1 | 56 | 2.25.1 |
31 | |||
32 | diff view generated by jsdifflib |
1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> |
---|---|---|---|
2 | 2 | ||
3 | Make the rvbar property settable after realize. This is done | 3 | Describe that the gic-version influences the maximum number of CPUs. |
4 | in preparation to model the ZynqMP's runtime configurable rvbar. | ||
5 | 4 | ||
6 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 5 | Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> |
7 | Message-id: 20220316164645.2303510-3-edgar.iglesias@gmail.com | 6 | Message-id: 20220413231456.35811-1-heinrich.schuchardt@canonical.com |
7 | [PMM: minor punctuation tweaks] | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | target/arm/cpu.h | 3 ++- | 11 | docs/system/arm/virt.rst | 4 ++-- |
12 | target/arm/cpu.c | 12 +++++++----- | 12 | 1 file changed, 2 insertions(+), 2 deletions(-) |
13 | target/arm/helper.c | 10 +++++++--- | ||
14 | 3 files changed, 16 insertions(+), 9 deletions(-) | ||
15 | 13 | ||
16 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 14 | diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst |
17 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/cpu.h | 16 | --- a/docs/system/arm/virt.rst |
19 | +++ b/target/arm/cpu.h | 17 | +++ b/docs/system/arm/virt.rst |
20 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | 18 | @@ -XXX,XX +XXX,XX @@ gic-version |
21 | uint64_t vbar_el[4]; | 19 | Valid values are: |
22 | }; | 20 | |
23 | uint32_t mvbar; /* (monitor) vector base address register */ | 21 | ``2`` |
24 | + uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ | 22 | - GICv2 |
25 | struct { /* FCSE PID. */ | 23 | + GICv2. Note that this limits the number of CPUs to 8. |
26 | uint32_t fcseidr_ns; | 24 | ``3`` |
27 | uint32_t fcseidr_s; | 25 | - GICv3 |
28 | @@ -XXX,XX +XXX,XX @@ struct ArchCPU { | 26 | + GICv3. This allows up to 512 CPUs. |
29 | 27 | ``host`` | |
30 | /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ | 28 | Use the same GIC version the host provides, when using KVM |
31 | uint32_t dcz_blocksize; | 29 | ``max`` |
32 | - uint64_t rvbar; | ||
33 | + uint64_t rvbar_prop; /* Property/input signals. */ | ||
34 | |||
35 | /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ | ||
36 | int gic_num_lrs; /* number of list registers */ | ||
37 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/target/arm/cpu.c | ||
40 | +++ b/target/arm/cpu.c | ||
41 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev) | ||
42 | } else { | ||
43 | env->pstate = PSTATE_MODE_EL1h; | ||
44 | } | ||
45 | - env->pc = cpu->rvbar; | ||
46 | + | ||
47 | + /* Sample rvbar at reset. */ | ||
48 | + env->cp15.rvbar = cpu->rvbar_prop; | ||
49 | + env->pc = env->cp15.rvbar; | ||
50 | #endif | ||
51 | } else { | ||
52 | #if defined(CONFIG_USER_ONLY) | ||
53 | @@ -XXX,XX +XXX,XX @@ static Property arm_cpu_reset_cbar_property = | ||
54 | static Property arm_cpu_reset_hivecs_property = | ||
55 | DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); | ||
56 | |||
57 | -static Property arm_cpu_rvbar_property = | ||
58 | - DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); | ||
59 | - | ||
60 | #ifndef CONFIG_USER_ONLY | ||
61 | static Property arm_cpu_has_el2_property = | ||
62 | DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); | ||
63 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj) | ||
64 | } | ||
65 | |||
66 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | ||
67 | - qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); | ||
68 | + object_property_add_uint64_ptr(obj, "rvbar", | ||
69 | + &cpu->rvbar_prop, | ||
70 | + OBJ_PROP_FLAG_READWRITE); | ||
71 | } | ||
72 | |||
73 | #ifndef CONFIG_USER_ONLY | ||
74 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
75 | index XXXXXXX..XXXXXXX 100644 | ||
76 | --- a/target/arm/helper.c | ||
77 | +++ b/target/arm/helper.c | ||
78 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
79 | ARMCPRegInfo rvbar = { | ||
80 | .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, | ||
81 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, | ||
82 | - .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar | ||
83 | + .access = PL1_R, | ||
84 | + .fieldoffset = offsetof(CPUARMState, cp15.rvbar), | ||
85 | }; | ||
86 | define_one_arm_cp_reg(cpu, &rvbar); | ||
87 | } | ||
88 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
89 | ARMCPRegInfo rvbar = { | ||
90 | .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, | ||
91 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, | ||
92 | - .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar | ||
93 | + .access = PL2_R, | ||
94 | + .fieldoffset = offsetof(CPUARMState, cp15.rvbar), | ||
95 | }; | ||
96 | define_one_arm_cp_reg(cpu, &rvbar); | ||
97 | } | ||
98 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
99 | ARMCPRegInfo el3_regs[] = { | ||
100 | { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, | ||
101 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, | ||
102 | - .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, | ||
103 | + .access = PL3_R, | ||
104 | + .fieldoffset = offsetof(CPUARMState, cp15.rvbar), | ||
105 | + }, | ||
106 | { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, | ||
107 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, | ||
108 | .access = PL3_RW, | ||
109 | -- | 30 | -- |
110 | 2.25.1 | 31 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | From: Hao Wu <wuhaotsh@google.com> |
---|---|---|---|
2 | 2 | ||
3 | CONFIG_ARM_GIC_TCG actually guards the compilation of TCG GICv3 | 3 | Similar to the Aspeed code in include/misc/aspeed_scu.h, we define |
4 | specific files. So let's rename it into CONFIG_ARM_GICV3_TCG | 4 | the PWRON STRAP fields in their corresponding module for NPCM7XX. |
5 | 5 | ||
6 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | 6 | Signed-off-by: Hao Wu <wuhaotsh@google.com> |
7 | Reviewed-by: Andrew Jones <drjones@redhat.com> | 7 | Reviewed-by: Patrick Venture <venture@google.com> |
8 | Message-id: 20220308182452.223473-2-eric.auger@redhat.com | 8 | Message-id: 20220411165842.3912945-2-wuhaotsh@google.com |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 11 | --- |
12 | hw/intc/Kconfig | 2 +- | 12 | include/hw/misc/npcm7xx_gcr.h | 30 ++++++++++++++++++++++++++++++ |
13 | hw/intc/meson.build | 4 ++-- | 13 | 1 file changed, 30 insertions(+) |
14 | 2 files changed, 3 insertions(+), 3 deletions(-) | ||
15 | 14 | ||
16 | diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig | 15 | diff --git a/include/hw/misc/npcm7xx_gcr.h b/include/hw/misc/npcm7xx_gcr.h |
17 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/intc/Kconfig | 17 | --- a/include/hw/misc/npcm7xx_gcr.h |
19 | +++ b/hw/intc/Kconfig | 18 | +++ b/include/hw/misc/npcm7xx_gcr.h |
20 | @@ -XXX,XX +XXX,XX @@ config APIC | 19 | @@ -XXX,XX +XXX,XX @@ |
21 | select MSI_NONBROKEN | 20 | #include "exec/memory.h" |
22 | select I8259 | 21 | #include "hw/sysbus.h" |
23 | 22 | ||
24 | -config ARM_GIC_TCG | 23 | +/* |
25 | +config ARM_GICV3_TCG | 24 | + * NPCM7XX PWRON STRAP bit fields |
26 | bool | 25 | + * 12: SPI0 powered by VSBV3 at 1.8V |
27 | default y | 26 | + * 11: System flash attached to BMC |
28 | depends on ARM_GIC && TCG | 27 | + * 10: BSP alternative pins. |
29 | diff --git a/hw/intc/meson.build b/hw/intc/meson.build | 28 | + * 9:8: Flash UART command route enabled. |
30 | index XXXXXXX..XXXXXXX 100644 | 29 | + * 7: Security enabled. |
31 | --- a/hw/intc/meson.build | 30 | + * 6: HI-Z state control. |
32 | +++ b/hw/intc/meson.build | 31 | + * 5: ECC disabled. |
33 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM_GIC', if_true: files( | 32 | + * 4: Reserved |
34 | 'arm_gicv3_common.c', | 33 | + * 3: JTAG2 enabled. |
35 | 'arm_gicv3_its_common.c', | 34 | + * 2:0: CPU and DRAM clock frequency. |
36 | )) | 35 | + */ |
37 | -softmmu_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files( | 36 | +#define NPCM7XX_PWRON_STRAP_SPI0F18 BIT(12) |
38 | +softmmu_ss.add(when: 'CONFIG_ARM_GICV3_TCG', if_true: files( | 37 | +#define NPCM7XX_PWRON_STRAP_SFAB BIT(11) |
39 | 'arm_gicv3.c', | 38 | +#define NPCM7XX_PWRON_STRAP_BSPA BIT(10) |
40 | 'arm_gicv3_dist.c', | 39 | +#define NPCM7XX_PWRON_STRAP_FUP(x) ((x) << 8) |
41 | 'arm_gicv3_its.c', | 40 | +#define FUP_NORM_UART2 3 |
42 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in | 41 | +#define FUP_PROG_UART3 2 |
43 | specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c')) | 42 | +#define FUP_PROG_UART2 1 |
44 | specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c')) | 43 | +#define FUP_NORM_UART3 0 |
45 | specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c')) | 44 | +#define NPCM7XX_PWRON_STRAP_SECEN BIT(7) |
46 | -specific_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files('arm_gicv3_cpuif.c')) | 45 | +#define NPCM7XX_PWRON_STRAP_HIZ BIT(6) |
47 | +specific_ss.add(when: 'CONFIG_ARM_GICV3_TCG', if_true: files('arm_gicv3_cpuif.c')) | 46 | +#define NPCM7XX_PWRON_STRAP_ECC BIT(5) |
48 | specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c')) | 47 | +#define NPCM7XX_PWRON_STRAP_RESERVE1 BIT(4) |
49 | specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) | 48 | +#define NPCM7XX_PWRON_STRAP_J2EN BIT(3) |
50 | specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) | 49 | +#define NPCM7XX_PWRON_STRAP_CKFRQ(x) (x) |
50 | +#define CKFRQ_SKIPINIT 0x000 | ||
51 | +#define CKFRQ_DEFAULT 0x111 | ||
52 | + | ||
53 | /* | ||
54 | * Number of registers in our device state structure. Don't change this without | ||
55 | * incrementing the version_id in the vmstate. | ||
51 | -- | 56 | -- |
52 | 2.25.1 | 57 | 2.25.1 | diff view generated by jsdifflib |
1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | From: Hao Wu <wuhaotsh@google.com> |
---|---|---|---|
2 | 2 | ||
3 | Add an unimplemented SERDES (Serializer/Deserializer) area. | 3 | This patch uses the defined fields to describe PWRON STRAPs for |
4 | better readability. | ||
4 | 5 | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 6 | Signed-off-by: Hao Wu <wuhaotsh@google.com> |
6 | Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com> | 7 | Reviewed-by: Patrick Venture <venture@google.com> |
7 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 8 | Message-id: 20220411165842.3912945-3-wuhaotsh@google.com |
8 | Message-id: 20220316164645.2303510-2-edgar.iglesias@gmail.com | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 11 | --- |
11 | include/hw/arm/xlnx-zynqmp.h | 2 +- | 12 | hw/arm/npcm7xx_boards.c | 24 +++++++++++++++++++----- |
12 | hw/arm/xlnx-zynqmp.c | 5 +++++ | 13 | 1 file changed, 19 insertions(+), 5 deletions(-) |
13 | 2 files changed, 6 insertions(+), 1 deletion(-) | ||
14 | 14 | ||
15 | diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h | 15 | diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c |
16 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/include/hw/arm/xlnx-zynqmp.h | 17 | --- a/hw/arm/npcm7xx_boards.c |
18 | +++ b/include/hw/arm/xlnx-zynqmp.h | 18 | +++ b/hw/arm/npcm7xx_boards.c |
19 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) | ||
20 | /* | ||
21 | * Unimplemented mmio regions needed to boot some images. | ||
22 | */ | ||
23 | -#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1 | ||
24 | +#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 2 | ||
25 | |||
26 | struct XlnxZynqMPState { | ||
27 | /*< private >*/ | ||
28 | diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/hw/arm/xlnx-zynqmp.c | ||
31 | +++ b/hw/arm/xlnx-zynqmp.c | ||
32 | @@ -XXX,XX +XXX,XX @@ | 19 | @@ -XXX,XX +XXX,XX @@ |
33 | #define QSPI_DMA_ADDR 0xff0f0800 | 20 | #include "sysemu/sysemu.h" |
34 | #define NUM_QSPI_IRQ_LINES 2 | 21 | #include "sysemu/block-backend.h" |
35 | 22 | ||
36 | +/* Serializer/Deserializer. */ | 23 | -#define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7 |
37 | +#define SERDES_ADDR 0xfd400000 | 24 | -#define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff |
38 | +#define SERDES_SIZE 0x20000 | 25 | -#define QUANTA_GBS_POWER_ON_STRAPS 0x000017ff |
26 | -#define KUDO_BMC_POWER_ON_STRAPS 0x00001fff | ||
27 | -#define MORI_BMC_POWER_ON_STRAPS 0x00001fff | ||
28 | +#define NPCM7XX_POWER_ON_STRAPS_DEFAULT ( \ | ||
29 | + NPCM7XX_PWRON_STRAP_SPI0F18 | \ | ||
30 | + NPCM7XX_PWRON_STRAP_SFAB | \ | ||
31 | + NPCM7XX_PWRON_STRAP_BSPA | \ | ||
32 | + NPCM7XX_PWRON_STRAP_FUP(FUP_NORM_UART2) | \ | ||
33 | + NPCM7XX_PWRON_STRAP_SECEN | \ | ||
34 | + NPCM7XX_PWRON_STRAP_HIZ | \ | ||
35 | + NPCM7XX_PWRON_STRAP_ECC | \ | ||
36 | + NPCM7XX_PWRON_STRAP_RESERVE1 | \ | ||
37 | + NPCM7XX_PWRON_STRAP_J2EN | \ | ||
38 | + NPCM7XX_PWRON_STRAP_CKFRQ(CKFRQ_DEFAULT)) | ||
39 | + | 39 | + |
40 | #define DP_ADDR 0xfd4a0000 | 40 | +#define NPCM750_EVB_POWER_ON_STRAPS ( \ |
41 | #define DP_IRQ 113 | 41 | + NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_J2EN) |
42 | 42 | +#define QUANTA_GSJ_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT | |
43 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) | 43 | +#define QUANTA_GBS_POWER_ON_STRAPS ( \ |
44 | hwaddr size; | 44 | + NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_SFAB) |
45 | } unimp_areas[ARRAY_SIZE(s->mr_unimp)] = { | 45 | +#define KUDO_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT |
46 | { .name = "apu", APU_ADDR, APU_SIZE }, | 46 | +#define MORI_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT |
47 | + { .name = "serdes", SERDES_ADDR, SERDES_SIZE }, | 47 | |
48 | }; | 48 | static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin"; |
49 | unsigned int nr; | ||
50 | 49 | ||
51 | -- | 50 | -- |
52 | 2.25.1 | 51 | 2.25.1 |
53 | |||
54 | diff view generated by jsdifflib |