From: Bin Meng <bin.meng@windriver.com>
This adds debug CSR read/write support to the RISC-V CSR RW table.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
Changes in v4:
- move riscv_trigger_init() call to riscv_cpu_reset()
Changes in v3:
- add riscv_trigger_init(), moved from patch #1 to this patch
target/riscv/debug.h | 2 ++
target/riscv/cpu.c | 4 ++++
target/riscv/csr.c | 57 ++++++++++++++++++++++++++++++++++++++++++++
target/riscv/debug.c | 27 +++++++++++++++++++++
4 files changed, 90 insertions(+)
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
index fb21706e1c..27b9cac6b4 100644
--- a/target/riscv/debug.h
+++ b/target/riscv/debug.h
@@ -109,4 +109,6 @@ void riscv_cpu_debug_excp_handler(CPUState *cs);
bool riscv_cpu_debug_check_breakpoint(CPUState *cs);
bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
+void riscv_trigger_init(CPURISCVState *env);
+
#endif /* RISCV_DEBUG_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index eb2be5fa05..ba9cc3bcd6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -461,6 +461,10 @@ static void riscv_cpu_reset(DeviceState *dev)
set_default_nan_mode(1, &env->fp_status);
#ifndef CONFIG_USER_ONLY
+ if (riscv_feature(env, RISCV_FEATURE_DEBUG)) {
+ riscv_trigger_init(env);
+ }
+
if (kvm_enabled()) {
kvm_riscv_reset_vcpu(cpu);
}
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 0606cd0ea8..3b9008709d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -290,6 +290,15 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
+
+static RISCVException debug(CPURISCVState *env, int csrno)
+{
+ if (riscv_feature(env, RISCV_FEATURE_DEBUG)) {
+ return RISCV_EXCP_NONE;
+ }
+
+ return RISCV_EXCP_ILLEGAL_INST;
+}
#endif
/* User Floating-Point CSRs */
@@ -2576,6 +2585,48 @@ static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException read_tselect(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ *val = tselect_csr_read(env);
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_tselect(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ tselect_csr_write(env, val);
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_tdata(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ /* return 0 in tdata1 to end the trigger enumeration */
+ if (env->trigger_cur >= TRIGGER_NUM && csrno == CSR_TDATA1) {
+ *val = 0;
+ return RISCV_EXCP_NONE;
+ }
+
+ if (!tdata_available(env, csrno - CSR_TDATA1)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ *val = tdata_csr_read(env, csrno - CSR_TDATA1);
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_tdata(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ if (!tdata_available(env, csrno - CSR_TDATA1)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ tdata_csr_write(env, csrno - CSR_TDATA1, val);
+ return RISCV_EXCP_NONE;
+}
+
/*
* Functions to access Pointer Masking feature registers
* We have to check if current priv lvl could modify
@@ -3265,6 +3316,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
+ /* Debug CSRs */
+ [CSR_TSELECT] = { "tselect", debug, read_tselect, write_tselect },
+ [CSR_TDATA1] = { "tdata1", debug, read_tdata, write_tdata },
+ [CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata },
+ [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata },
+
/* User Pointer Masking */
[CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte },
[CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask },
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 1a9392645e..2f2a51c732 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -412,3 +412,30 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
return false;
}
+
+void riscv_trigger_init(CPURISCVState *env)
+{
+ target_ulong type2 = trigger_type(env, TRIGGER_TYPE_AD_MATCH);
+ int i;
+
+ /* type 2 triggers */
+ for (i = 0; i < TRIGGER_TYPE2_NUM; i++) {
+ /*
+ * type = TRIGGER_TYPE_AD_MATCH
+ * dmode = 0 (both debug and M-mode can write tdata)
+ * maskmax = 0 (unimplemented, always 0)
+ * sizehi = 0 (match against any size, RV64 only)
+ * hit = 0 (unimplemented, always 0)
+ * select = 0 (always 0, perform match on address)
+ * timing = 0 (always 0, trigger before instruction)
+ * sizelo = 0 (match against any size)
+ * action = 0 (always 0, raise a breakpoint exception)
+ * chain = 0 (unimplemented, always 0)
+ * match = 0 (always 0, when any compare value equals tdata2)
+ */
+ env->type2_trig[i].mcontrol = type2;
+ env->type2_trig[i].maddress = 0;
+ env->type2_trig[i].bp = NULL;
+ env->type2_trig[i].wp = NULL;
+ }
+}
--
2.25.1On Tue, Mar 15, 2022 at 5:08 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This adds debug CSR read/write support to the RISC-V CSR RW table.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> Changes in v4:
> - move riscv_trigger_init() call to riscv_cpu_reset()
>
> Changes in v3:
> - add riscv_trigger_init(), moved from patch #1 to this patch
>
> target/riscv/debug.h | 2 ++
> target/riscv/cpu.c | 4 ++++
> target/riscv/csr.c | 57 ++++++++++++++++++++++++++++++++++++++++++++
> target/riscv/debug.c | 27 +++++++++++++++++++++
> 4 files changed, 90 insertions(+)
>
> diff --git a/target/riscv/debug.h b/target/riscv/debug.h
> index fb21706e1c..27b9cac6b4 100644
> --- a/target/riscv/debug.h
> +++ b/target/riscv/debug.h
> @@ -109,4 +109,6 @@ void riscv_cpu_debug_excp_handler(CPUState *cs);
> bool riscv_cpu_debug_check_breakpoint(CPUState *cs);
> bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
>
> +void riscv_trigger_init(CPURISCVState *env);
> +
> #endif /* RISCV_DEBUG_H */
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index eb2be5fa05..ba9cc3bcd6 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -461,6 +461,10 @@ static void riscv_cpu_reset(DeviceState *dev)
> set_default_nan_mode(1, &env->fp_status);
>
> #ifndef CONFIG_USER_ONLY
> + if (riscv_feature(env, RISCV_FEATURE_DEBUG)) {
> + riscv_trigger_init(env);
> + }
> +
> if (kvm_enabled()) {
> kvm_riscv_reset_vcpu(cpu);
> }
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 0606cd0ea8..3b9008709d 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -290,6 +290,15 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
>
> return RISCV_EXCP_ILLEGAL_INST;
> }
> +
> +static RISCVException debug(CPURISCVState *env, int csrno)
> +{
> + if (riscv_feature(env, RISCV_FEATURE_DEBUG)) {
> + return RISCV_EXCP_NONE;
> + }
> +
> + return RISCV_EXCP_ILLEGAL_INST;
> +}
> #endif
>
> /* User Floating-Point CSRs */
> @@ -2576,6 +2585,48 @@ static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> +static RISCVException read_tselect(CPURISCVState *env, int csrno,
> + target_ulong *val)
> +{
> + *val = tselect_csr_read(env);
> + return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_tselect(CPURISCVState *env, int csrno,
> + target_ulong val)
> +{
> + tselect_csr_write(env, val);
> + return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException read_tdata(CPURISCVState *env, int csrno,
> + target_ulong *val)
> +{
> + /* return 0 in tdata1 to end the trigger enumeration */
> + if (env->trigger_cur >= TRIGGER_NUM && csrno == CSR_TDATA1) {
> + *val = 0;
> + return RISCV_EXCP_NONE;
> + }
> +
> + if (!tdata_available(env, csrno - CSR_TDATA1)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + *val = tdata_csr_read(env, csrno - CSR_TDATA1);
> + return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_tdata(CPURISCVState *env, int csrno,
> + target_ulong val)
> +{
> + if (!tdata_available(env, csrno - CSR_TDATA1)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + tdata_csr_write(env, csrno - CSR_TDATA1, val);
> + return RISCV_EXCP_NONE;
> +}
> +
> /*
> * Functions to access Pointer Masking feature registers
> * We have to check if current priv lvl could modify
> @@ -3265,6 +3316,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
> [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
>
> + /* Debug CSRs */
> + [CSR_TSELECT] = { "tselect", debug, read_tselect, write_tselect },
> + [CSR_TDATA1] = { "tdata1", debug, read_tdata, write_tdata },
> + [CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata },
> + [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata },
> +
> /* User Pointer Masking */
> [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte },
> [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask },
> diff --git a/target/riscv/debug.c b/target/riscv/debug.c
> index 1a9392645e..2f2a51c732 100644
> --- a/target/riscv/debug.c
> +++ b/target/riscv/debug.c
> @@ -412,3 +412,30 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
>
> return false;
> }
> +
> +void riscv_trigger_init(CPURISCVState *env)
> +{
> + target_ulong type2 = trigger_type(env, TRIGGER_TYPE_AD_MATCH);
> + int i;
> +
> + /* type 2 triggers */
> + for (i = 0; i < TRIGGER_TYPE2_NUM; i++) {
> + /*
> + * type = TRIGGER_TYPE_AD_MATCH
> + * dmode = 0 (both debug and M-mode can write tdata)
> + * maskmax = 0 (unimplemented, always 0)
> + * sizehi = 0 (match against any size, RV64 only)
> + * hit = 0 (unimplemented, always 0)
> + * select = 0 (always 0, perform match on address)
> + * timing = 0 (always 0, trigger before instruction)
> + * sizelo = 0 (match against any size)
> + * action = 0 (always 0, raise a breakpoint exception)
> + * chain = 0 (unimplemented, always 0)
> + * match = 0 (always 0, when any compare value equals tdata2)
> + */
> + env->type2_trig[i].mcontrol = type2;
> + env->type2_trig[i].maddress = 0;
> + env->type2_trig[i].bp = NULL;
> + env->type2_trig[i].wp = NULL;
> + }
> +}
> --
> 2.25.1
>
>
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