From: Alistair Francis <alistair.francis@wdc.com>
The following changes since commit ad38520bdeb2b1e0b487db317f29119e94c1c88d:
Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2022-02-15 19:30:33 +0000)
are available in the Git repository at:
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220216
for you to fetch changes up to 7035b8420fa52e8c94cf4317c0f88c1b73ced28d:
docs/system: riscv: Update description of CPU (2022-02-16 12:25:52 +1000)
----------------------------------------------------------------
Fourth RISC-V PR for QEMU 7.0
* Remove old Ibex PLIC header file
* Allow writing 8 bytes with generic loader
* Fixes for RV128
* Refactor RISC-V CPU configs
* Initial support for XVentanaCondOps custom extension
* Fix for vill field in vtype
* Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
* Support for svnapot, svinval and svpbmt extensions
----------------------------------------------------------------
Anup Patel (18):
target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
target/riscv: Implement SGEIP bit in hip and hie CSRs
target/riscv: Implement hgeie and hgeip CSRs
target/riscv: Improve delivery of guest external interrupts
target/riscv: Allow setting CPU feature from machine/device emulation
target/riscv: Add AIA cpu feature
target/riscv: Add defines for AIA CSRs
target/riscv: Allow AIA device emulation to set ireg rmw callback
target/riscv: Implement AIA local interrupt priorities
target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
target/riscv: Implement AIA hvictl and hviprioX CSRs
target/riscv: Implement AIA interrupt filtering CSRs
target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
target/riscv: Implement AIA xiselect and xireg CSRs
target/riscv: Implement AIA IMSIC interface CSRs
hw/riscv: virt: Use AIA INTC compatible string when available
target/riscv: Allow users to force enable AIA CSRs in HART
hw/intc: Add RISC-V AIA APLIC device emulation
Frédéric Pétrot (1):
target/riscv: correct "code should not be reached" for x-rv128
Guo Ren (1):
target/riscv: Ignore reserved bits in PTE for RV64
LIU Zhiwei (1):
target/riscv: Fix vill field write in vtype
Petr Tesarik (1):
Allow setting up to 8 bytes with the generic loader
Philipp Tomsich (7):
target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig'
target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr
target/riscv: access configuration through cfg_ptr in DisasContext
target/riscv: access cfg structure through DisasContext
target/riscv: iterate over a table of decoders
target/riscv: Add XVentanaCondOps custom extension
target/riscv: add a MAINTAINERS entry for XVentanaCondOps
Weiwei Li (4):
target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
target/riscv: add support for svnapot extension
target/riscv: add support for svinval extension
target/riscv: add support for svpbmt extension
Wilfred Mallawa (1):
include: hw: remove ibex_plic.h
Yu Li (1):
docs/system: riscv: Update description of CPU
docs/system/riscv/virt.rst | 6 +-
include/hw/intc/ibex_plic.h | 67 -
include/hw/intc/riscv_aplic.h | 79 ++
target/riscv/cpu.h | 169 ++-
target/riscv/cpu_bits.h | 129 ++
target/riscv/XVentanaCondOps.decode | 25 +
target/riscv/insn32.decode | 7 +
hw/core/generic-loader.c | 2 +-
hw/intc/riscv_aplic.c | 978 +++++++++++++++
hw/riscv/virt.c | 13 +-
target/riscv/cpu.c | 113 +-
target/riscv/cpu_helper.c | 377 +++++-
target/riscv/csr.c | 1282 ++++++++++++++++++--
target/riscv/gdbstub.c | 3 +
target/riscv/machine.c | 24 +-
target/riscv/translate.c | 61 +-
target/riscv/vector_helper.c | 1 +
target/riscv/insn_trans/trans_rvb.c.inc | 8 +-
target/riscv/insn_trans/trans_rvi.c.inc | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 146 ++-
target/riscv/insn_trans/trans_rvzfh.c.inc | 4 +-
target/riscv/insn_trans/trans_svinval.c.inc | 75 ++
.../riscv/insn_trans/trans_xventanacondops.c.inc | 39 +
MAINTAINERS | 7 +
hw/intc/Kconfig | 3 +
hw/intc/meson.build | 1 +
target/riscv/meson.build | 1 +
27 files changed, 3252 insertions(+), 370 deletions(-)
delete mode 100644 include/hw/intc/ibex_plic.h
create mode 100644 include/hw/intc/riscv_aplic.h
create mode 100644 target/riscv/XVentanaCondOps.decode
create mode 100644 hw/intc/riscv_aplic.c
create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc
create mode 100644 target/riscv/insn_trans/trans_xventanacondops.c.inc