From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1644996190238983.5314572234821; Tue, 15 Feb 2022 23:23:10 -0800 (PST) Received: from localhost ([::1]:56198 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKEea-00019t-3W for importer@patchew.org; Wed, 16 Feb 2022 02:23:08 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48146) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDog-0004HC-PR for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:29:31 -0500 Received: from esa5.hgst.iphmx.com ([216.71.153.144]:59472) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDoe-0006Gk-Ae for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:29:30 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:29:26 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:02:15 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:29:28 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7N721kLz1SVp0 for ; Tue, 15 Feb 2022 22:29:27 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id wvIKbQNWV7Fm for ; Tue, 15 Feb 2022 22:29:26 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7N30z1wz1Rwrw; Tue, 15 Feb 2022 22:29:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644992967; x=1676528967; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BVcJ3H0xI37hYmEcH9RcIT3zwvBrl8Sr1npO+d72CAE=; b=jqF0rF9R9OotKeyFDV4wSCmHVHHdmmaHirVHu1KPo3/evwokvvGt7dR5 JcHDAP8nORNnNO+dwiMgx0Wo1vSBZ475yK68oJ6xzMROqMfpQkW0radVH XAaLZZbTDTeUwS5UCFNghYIipDuyFcBrxZojFXBnAAFSibu48UheV0iZJ fo1DfMoZhdd8WoLtT1FgwdRuSNhd7Gi0ISVbs4IWgxeg4wsYSIbTAv73X 7dPjBZnUsPkYomS5F2b5Yu/2IXrbWPBw8rwx0oz+FUFiuLmqe9zZR6NJh 1w8j7jOEdez8C+PhhnoJXXaIeWbgHKaQdDbw/aF7srmik5D39a035thuT A==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="193072666" IronPort-SDR: m5a3lgMIiT8JWauGJohMjhuAkJ7QIF2dpRNuTg5MQCZmKAlDxIsbrg5fdd/hY2Bzkzd2iV3/hX CJI8TCoUwK2yK0a0KsG3ywra6No8KWqRv/WsYdB/9xwOEWu0ISkfQYFtH418EbgWK9tTyQfjl/ 3/btvhkTtVg0VEfikv3k4RWN1g81Fe91gdaSW6WODxuJ1griqW2KIXPhZ3jil2QHlVCx4bEJSI G4h6p8S42rP9D71bGCcx+/HLyytvQS9PfAZ8KgR0YXOacuN+BneElHNeN6mbxQVuXyE0tQf391 VxjcbnwaGKwT6wVrS4RElvvi IronPort-SDR: KBbNWQudvLwjD9AXTnvyuQbesAwzqNCRo/WU/skyDPHe1TGev/hf5mGFjsCkD7NEz9uKCUZ1wF n0Ni9BYuvzPKut3cGHqagyz3E71Bbrqv4Yoj5n4VXT8TZph9iKRBilJ+zIH5wADEj+Fz35BHgB zCryIHwhGPrzYpF9hqjyN+JbSssQERqmn8Ujk9GYU4LfFhAp53Aky7N5KHbsJ8P6InxIEgVSGg C9A29+rAcDo6Lxy9cEOtw43Ej0TWLVnauxwZF6flOsKMUez3XzZrQ7UD09tYRB93JH6HHuDtPX lgo= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:content-type :mime-version:references:in-reply-to:x-mailer:message-id:date :subject:to:from; s=dkim; t=1644992966; x=1647584967; bh=BVcJ3H0 xI37hYmEcH9RcIT3zwvBrl8Sr1npO+d72CAE=; b=Hgi0oYmtiyReLod1l75C3mS SfjhDgt1uUAf4R/1E/EODNeMcjlUp3AnSaIsqXZyf7zPsywKeGcQ1Wujwm6tVV0n Q2MaZ2ABtlMZGxolWCQX/r+klgXrEIgb5dmeaTobqsFDHF4z5Kt3f5tTXcyy6C2I gYYoX+8j0oblpvKSiG1sm9jx8RykzTmxm5670NQOy65oA2TuJ/FgsISkX4f6g0+S LAMMUfyROEjBB3HM1ucYsNEVMz3lvg/E6zXP9ylcZ48MopANl2LZ4fESZP+jWZJU k0CCYlm2Nz/zQ2oR4rDo5IU9TDNuJgDRsRPu4ZsqBc5kwWLZ2aCGM5B12T2n0BQ= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Wilfred Mallawa , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL v2 01/35] include: hw: remove ibex_plic.h Date: Wed, 16 Feb 2022 16:28:38 +1000 Message-Id: <20220216062912.319738-2-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1644996192533100001 Content-Type: text/plain; charset="utf-8" From: Wilfred Mallawa This patch removes the left-over/unused `ibex_plic.h` file. Previously used by opentitan, which now follows the RISC-V standard and uses the SiFivePlicState. Fixes: 434e7e021 ("hw/intc: Remove the Ibex PLIC") Signed-off-by: Wilfred Mallawa Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20220121055005.3159846-1-alistair.francis@opensource.wdc.com Signed-off-by: Alistair Francis --- include/hw/intc/ibex_plic.h | 67 ------------------------------------- 1 file changed, 67 deletions(-) delete mode 100644 include/hw/intc/ibex_plic.h diff --git a/include/hw/intc/ibex_plic.h b/include/hw/intc/ibex_plic.h deleted file mode 100644 index d596436e06..0000000000 --- a/include/hw/intc/ibex_plic.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * QEMU RISC-V lowRISC Ibex PLIC - * - * Copyright (c) 2020 Western Digital - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or - * more details. - * - * You should have received a copy of the GNU General Public License along= with - * this program. If not, see . - */ - -#ifndef HW_IBEX_PLIC_H -#define HW_IBEX_PLIC_H - -#include "hw/sysbus.h" -#include "qom/object.h" - -#define TYPE_IBEX_PLIC "ibex-plic" -OBJECT_DECLARE_SIMPLE_TYPE(IbexPlicState, IBEX_PLIC) - -struct IbexPlicState { - /*< private >*/ - SysBusDevice parent_obj; - - /*< public >*/ - MemoryRegion mmio; - - uint32_t *pending; - uint32_t *hidden_pending; - uint32_t *claimed; - uint32_t *source; - uint32_t *priority; - uint32_t *enable; - uint32_t threshold; - uint32_t claim; - - /* config */ - uint32_t num_cpus; - uint32_t num_sources; - - uint32_t pending_base; - uint32_t pending_num; - - uint32_t source_base; - uint32_t source_num; - - uint32_t priority_base; - uint32_t priority_num; - - uint32_t enable_base; - uint32_t enable_num; - - uint32_t threshold_base; - - uint32_t claim_base; - - qemu_irq *external_irqs; -}; - -#endif /* HW_IBEX_PLIC_H */ --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164499695122110.245962597881544; Tue, 15 Feb 2022 23:35:51 -0800 (PST) Received: from localhost ([::1]:36584 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKEqr-0007fs-Qs for importer@patchew.org; Wed, 16 Feb 2022 02:35:49 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48168) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDoj-0004Oi-PQ for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:29:34 -0500 Received: from esa5.hgst.iphmx.com ([216.71.153.144]:59472) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDoh-0006Gk-L6 for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:29:33 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:29:30 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:02:19 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:29:31 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7NB4gg7z1Rwrw for ; Tue, 15 Feb 2022 22:29:30 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id 8WE8lpkMIsTu for ; Tue, 15 Feb 2022 22:29:30 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7N72sJwz1SVp2; Tue, 15 Feb 2022 22:29:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644992970; x=1676528970; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Q6yJDJqIAw6QM8qy0fNUeXdxUdGcovlH4g3TuX9SCc4=; b=iyshMLF1RO1o0/Y94zUsZwN2zHs3YmrLO78lLbknqEkMAQn4SxF8HZMr G2hDTOIKwta5OyajR8bPqPNSX8yZdHOSrLu6PC5X4dOTMcBhRli2DSmMf oYrpIDdhQfXg/7n9H82hEmWL2WogEG5dSDNRCR9t5bN9Pf0HSKvHiiZjq lYS/dB4N7LwIvtZ5y/qjKa3EQ8uOwbNxtqYtvzZhvedOAmiyl0Q1D/o33 0tmWddPyPSVpdO+kfmI1exDUuVGnXcTt1JCkPDSQEvCQtt1wEKz9kUG99 FLmVDbya3pv4gZdgpKLwUw3elF2ECDCGduKlhEkiy8MDgz+52wERtpgxT w==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="193072670" IronPort-SDR: tiNTATvD84TMOoO/kyYzAjoYer0vu9TRmT7KZv64OJk9bVtyG0/0JcLpIKsf/WfoLL5SoXO/EN 560bJbJhw+EN7mWuwOaEUL4TCzT9eTMn1eciwdKtBYmSd6IA5Bu0erT3FpAMNx9LICbPsTN1Fn h37uGwugVjV4ddZmoECymzt1bdm5csVauIVntn8McIHqTscRb3xq2Ihdl7qTK9UZkXIjtRiyWC joWCjMmi9LNrhqbmxij11/5T3AlcWJM+NzJ/NfakUsJaylPmLfNZq7KMXhw97H/oDtsz2PSmWZ dDDSFj81dmMNN9GcUx0kB+5A IronPort-SDR: AxS1KwhuLCyB1jW4mDxGgIr1avnXMnLw8y7mFkKdsyEHrQwdr18rG1G2Fm2afQLWxv8+UUvT1K 4GS6boCp01SyvOTPjoLeoYJ8bOsJ4MPA16H5ggmRP4Qdwje2ixOqJGBbvmqzoEIa9ghhXr0oYd hhv+WFWnxl8MybNJbLvJVIzi92/cerVW0Vtwse1fpFUY4ZJPKoPsq+b97ovnzwqKJN6jFkKETL JS87Qufkfv3pnbLVCq1j3DFtGufrocPBRXOVglBPRKNtrWSp8xhLrq4EiSsRRjORqu/FZfR3c0 FXQ= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:content-type :mime-version:references:in-reply-to:x-mailer:message-id:date :subject:to:from; s=dkim; t=1644992970; x=1647584971; bh=Q6yJDJq IAw6QM8qy0fNUeXdxUdGcovlH4g3TuX9SCc4=; b=LgK4q5+Lx2ke2XSu2ud5tW2 yENQMQ08lfuwmIF/QbDaG2rTKjd7WFhNFdZqUqETfiqgEBG+T5qPFlkHmUbiueNe WNLqn65YoRBA2lbgWNKhqku5xHmk0cXFL1uQf4NqN2tVsQsY3EU3tqQ5Vjw1eXin f2SyFsdyuWZNDWVg0s496T4l2kx6Mw6cXbzpKEs84pyrLOSHXDAi64d/41uODP/E irW5Hz4IYSJ3mLZMNQ/tf9/U4GJwfF/VjFKhwHFdCXb4NfDv2I5a7RbRaMjzOA8X YFm5sm3ZdGjDhNnckhu8TMx6CnWgSsNMhjs8ihmY6ebfEnMOrXPEFE/e8Z/Cjcw= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Petr Tesarik , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL v2 02/35] Allow setting up to 8 bytes with the generic loader Date: Wed, 16 Feb 2022 16:28:39 +1000 Message-Id: <20220216062912.319738-3-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1644996952867100001 Content-Type: text/plain; charset="utf-8" From: Petr Tesarik The documentation for the generic loader says that "the maximum size of the data is 8 bytes". However, attempts to set data-len=3D8 trigger the following assertion failure: ../hw/core/generic-loader.c:59: generic_loader_reset: Assertion `s->data_le= n < sizeof(s->data)' failed. The type of s->data is uint64_t (i.e. 8 bytes long), so I believe this assert should use <=3D instead of <. Fixes: e481a1f63c93 ("generic-loader: Add a generic loader") Signed-off-by: Petr Tesarik Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-id: 20220120092715.7805-1-ptesarik@suse.com Signed-off-by: Alistair Francis --- hw/core/generic-loader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c index 9a24ffb880..504ed7ca72 100644 --- a/hw/core/generic-loader.c +++ b/hw/core/generic-loader.c @@ -56,7 +56,7 @@ static void generic_loader_reset(void *opaque) } =20 if (s->data_len) { - assert(s->data_len < sizeof(s->data)); + assert(s->data_len <=3D sizeof(s->data)); dma_memory_write(s->cpu->as, s->addr, &s->data, s->data_len, MEMTXATTRS_UNSPECIFIED); } --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1644994657931462.799442889665; Tue, 15 Feb 2022 22:57:37 -0800 (PST) Received: from localhost ([::1]:58520 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKEFu-00089C-0H for importer@patchew.org; Wed, 16 Feb 2022 01:57:38 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48250) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDow-0004cU-9S for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:29:46 -0500 Received: from esa5.hgst.iphmx.com ([216.71.153.144]:59472) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDot-0006Gk-89 for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:29:45 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:29:33 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:02:23 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:29:35 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7NH00Y4z1SVnx for ; Tue, 15 Feb 2022 22:29:34 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id ziz7E5vCTin6 for ; Tue, 15 Feb 2022 22:29:34 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7NC1CwFz1Rwrw; Tue, 15 Feb 2022 22:29:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644992981; x=1676528981; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1LlxeqPKUqxNZbvQuHDGyDTVNCxzSfXuXd+6hiz6RuQ=; b=W37aIva/RL3xwV6CPQk2NlWR+6J4yYt0JD63p5LxSpJ4cMUh7x82YDBx 5NpxdHQpX6R25tAqc2wD93oo27t7weyO8ExSrRsgr+J/8qbFcnl7bPo4D NfMNzd7+RlfSlFYPXV7Td/mrmo625BZtBXkwFqujkffUxQs/eTqXa4zon VDzWEZI3BcBemCY4hSvthWK3PlsfIf38dObIpkDTV2z1SYgATvldF9qIl F0WbGlz7FEhKy3rcY9htKOv1SopndUMIwSl3cZdnACwdGQjG8NyNFTGfR rKFeJOu2E9f3PVNdszErWyPoedxXc+wQWMIvutqLK7ZsJrWBegrlA2p9g Q==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="193072673" IronPort-SDR: LnLI+KxJJ6979i6RW75oe+m37cxbfbUrj1pP/fk0w8S5jy2Vy5klO7VbNpZnH4Dg1lJQoFlGkt j+p19uJ3/8gkKhk4XcKTJ8LEs3nqJyDH20XzaUd8aO/qnfrRIwZ4y2eJPmG6sJ4DDaOh6Y/KRQ HKHBwUwcTsu3PrMb2xrINDOW7meVUp10TravhXPpPfmhD3qNDbOy9d+B0Ll9J+yX0RultuQST9 8Jfxg8iXtujsP/6YR3DGrG+B/bf16BHVSRulFZIdlFBwoGj4Qm3wJj0yli9qKNg567L59QV9Jg V9vHYzXCqwHyuP3L84UvnmES IronPort-SDR: QKeq8i9huMn9jNkbdpzAWXLBX34su2QXNp4plIQ7mbz2qMzBQr51orxqlIKtRKTg2UR2Ivsp5d 3+Ymr55eqE7CF5JXaRTut4tpknPEVYXncjKVTvYWQlJ6PyTfPqznnntt48UkLWBq1nwWw91hKV B9dksk7dOgr/wiv6MM87RTlkOBBTgGWZ818VV8zvXhD3mug3YozhFDUl6xxHHhad5GJLZbjqW2 rZkxyTk71ZdAy8hzHbDCXhkZ7rR6wSbTMJRhlUTwXO3YJqxlpWCz+8+p4nesPvwpqd35ctIjCe kDQ= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:content-type :mime-version:references:in-reply-to:x-mailer:message-id:date :subject:to:from; s=dkim; t=1644992974; x=1647584975; bh=1LlxeqP KUqxNZbvQuHDGyDTVNCxzSfXuXd+6hiz6RuQ=; b=e4Zvz2c/W4jcd2yyAqUlGOQ eC3YGISTWdeGYV1V1zp/Qy+vjDkJsxq+1G//VAHok5Mkd5ozkXQD1RPgH16QHJMA F42JqJtUaNOXm/J5U7QudB5FFsV1PCTkms22gBeMn8nQzRIBlZ4NwH7lAngRULtY siuiUF5U7K67fGHednEBqMuxvjnp1MCpK/0AGM4SwlusnRyBMLUvjgM3I+2sNSqz nW5onmu3esr54tNrDe7HJUXWiE126HpQCSSjsdUh4EWU8oXHdvogSynBF3Fi6NVQ UKhaePFSI5yeusuwwdDceDZqoS4EoOIOg4Y8gxz/Ob1DTk4HppwVJ6tS1nNoz/w= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , LIU Zhiwei , Alistair Francis Subject: [PULL v2 03/35] target/riscv: correct "code should not be reached" for x-rv128 Date: Wed, 16 Feb 2022 16:28:40 +1000 Message-Id: <20220216062912.319738-4-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1644994660247100003 Content-Type: text/plain; charset="utf-8" From: Fr=C3=A9d=C3=A9ric P=C3=A9trot The addition of uxl support in gdbstub adds a few checks on the maximum register length, but omitted MXL_RV128, an experimental feature. This patch makes rv128 react as rv64, as previously. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-id: 20220124202456.420258-1-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 3 +-- target/riscv/gdbstub.c | 3 +++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1cb0436187..5ada71e5bf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -528,9 +528,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) switch (env->misa_mxl_max) { #ifdef TARGET_RISCV64 case MXL_RV64: - cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; - break; case MXL_RV128: + cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; break; #endif case MXL_RV32: diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index f531a74c2f..9ed049c29e 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -64,6 +64,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray = *mem_buf, int n) case MXL_RV32: return gdb_get_reg32(mem_buf, tmp); case MXL_RV64: + case MXL_RV128: return gdb_get_reg64(mem_buf, tmp); default: g_assert_not_reached(); @@ -84,6 +85,7 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *m= em_buf, int n) length =3D 4; break; case MXL_RV64: + case MXL_RV128: if (env->xl < MXL_RV64) { tmp =3D (int32_t)ldq_p(mem_buf); } else { @@ -420,6 +422,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState = *cs) 1, "riscv-32bit-virtual.xml", 0); break; case MXL_RV64: + case MXL_RV128: gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, 1, "riscv-64bit-virtual.xml", 0); --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1644997518269327.94400577399426; Tue, 15 Feb 2022 23:45:18 -0800 (PST) Received: from localhost ([::1]:45574 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKF01-0005vR-5L for importer@patchew.org; Wed, 16 Feb 2022 02:45:17 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48230) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDou-0004Za-Vr for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:29:45 -0500 Received: from esa5.hgst.iphmx.com ([216.71.153.144]:59483) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDot-0006I2-85 for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:29:44 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:29:37 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:02:27 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:29:39 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7NL6kM8z1SHwl for ; Tue, 15 Feb 2022 22:29:38 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id 0AeIG4-sBZKO for ; Tue, 15 Feb 2022 22:29:38 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7NH3b3Pz1Rwrw; Tue, 15 Feb 2022 22:29:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644992981; x=1676528981; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gQuKw+pR0sbPYb7FHP+pF/1PuBkafM513sv97qUrNQ8=; b=eoK0QDIyTR14cquTswoByGDY3emLkIHl//Wb08C2S/sTOPqNUNdZEXxJ xbpsNasYE9Ve2lau6CMy0o5Sw3WayJsVw05POjcy5SOUSpEel1pGtr9Dy ZH2hTnC140XkJj4rEodiPVIigoEwV+aSbtc/BN76ilfUZXUQD7qbWjC08 M3H+wvjCShZtLf593uu/JOwKLOSVFEKLMYCaYdjT/X3qVG4tSoH824HJN o5g5akDP/2WZ37r0MZ+mVb/m0/qt6c+fzMXw6tyyLSNdnfDE5heLV6XVK BUjDQ5EElGIcfn03yog4FQYYMM5Pz7+YSVjpL0jwsWNgk15wD0sdB7RJG A==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="193072677" IronPort-SDR: P0FlL8Cg3TyxwQX4bcCh95rQWzP6OCF1/apovTWSCt4xsuXgDia5Kzg5QaPAasQdMQJihnQDAc 5yXupcvvw9kKfxScyAz1RpXALQ7r1JAm1byKm2q9USum1AHdO/BMazO7JmrFum4tyz/Oe5ePyX u2mjCSr7eRX9c0REdhRVDhFwTgsNd9mKTm6q7NGZrMftKqOL9ER1QLV5fDX2FXMjTHRsGd/Idk NIF6OealqdwAAtr5mNO4I6mJYzsDPjWAfvddnx1mXl0vB1Au3TvnHlJ1TMF8FXZW147IhudrT7 YQj0GeLBzbvrOe8DH3CMlzY2 IronPort-SDR: Pf/7dIkV2vYmF5gaqsAkqDS8MqulvqNx+xPy0QiJyfQl6kRjOcf5x6jLqxv8fmUf9p/qqSbbHr naivmXIEzitOtPn7TyUYeXm4XCrxsFxPrBEsCZ4yb3RXJihgEh7vlyxzK717VblNZLpxa4qkZu iNgN9wPMgYpj3jrEoJZXZjWeu+qs/pi8SkD9n0PtIGsz8dPkMcZRtJrz9uV49njOnIMOkIqHkn Od0KTDo7+gmoNfErLvNTaG4Vk3pkV2fPpU56xgrv3fxJR9U37zj7JpmfeHPmllLZOcxNrRKJ95 XNQ= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644992978; x=1647584979; bh=gQuKw+pR0sbPYb7FHP +pF/1PuBkafM513sv97qUrNQ8=; b=i83ymA7ZB0ECV9/mIPKFGQiQja5eQxJIX7 7KmcJchWcLAzRCTyu7yv9YUUpvDLfzgX9dPSFK0cp89TIll3TYCiZhawddsntNJz tLeR6m+uUPL+Hq1hiaHtTGNyJuZYWjAak7lRcRZEA8TQZ2z/fVuiTZzHs3CHO3SK UOy4UqLE/CEFUEO8oikVmIYw6OJVTFzzE3Vaaia3OMfzfw/A3MAonp9piPEIGp5a B6B+VLncMsH2hMbYtLbFRed/4KehsecY+QFvlOpW0SajmmOACghL9il/W+jwYimj waNsZ0omKClSZaD00ezeZOmmOmh98T4dzTFCRxw6Ym8KAC99htCw== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Philipp Tomsich , Alistair Francis , Richard Henderson Subject: [PULL v2 04/35] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' Date: Wed, 16 Feb 2022 16:28:41 +1000 Message-Id: <20220216062912.319738-5-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1644997519461100001 Content-Type: text/plain; charset="utf-8" From: Philipp Tomsich Signed-off-by: Philipp Tomsich Reviewed-by: Alistair Francis Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Message-Id: <20220202005249.3566542-2-philipp.tomsich@vrull.eu> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 78 ++++++++++++++++++++++++---------------------- 1 file changed, 41 insertions(+), 37 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 55635d68d5..1175915c0d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -303,6 +303,46 @@ struct RISCVCPUClass { DeviceReset parent_reset; }; =20 +struct RISCVCPUConfig { + bool ext_i; + bool ext_e; + bool ext_g; + bool ext_m; + bool ext_a; + bool ext_f; + bool ext_d; + bool ext_c; + bool ext_s; + bool ext_u; + bool ext_h; + bool ext_j; + bool ext_v; + bool ext_zba; + bool ext_zbb; + bool ext_zbc; + bool ext_zbs; + bool ext_counters; + bool ext_ifencei; + bool ext_icsr; + bool ext_zfh; + bool ext_zfhmin; + bool ext_zve32f; + bool ext_zve64f; + + char *priv_spec; + char *user_spec; + char *bext_spec; + char *vext_spec; + uint16_t vlen; + uint16_t elen; + bool mmu; + bool pmp; + bool epmp; + uint64_t resetvec; +}; + +typedef struct RISCVCPUConfig RISCVCPUConfig; + /** * RISCVCPU: * @env: #CPURISCVState @@ -320,43 +360,7 @@ struct RISCVCPU { char *dyn_vreg_xml; =20 /* Configuration Settings */ - struct { - bool ext_i; - bool ext_e; - bool ext_g; - bool ext_m; - bool ext_a; - bool ext_f; - bool ext_d; - bool ext_c; - bool ext_s; - bool ext_u; - bool ext_h; - bool ext_j; - bool ext_v; - bool ext_zba; - bool ext_zbb; - bool ext_zbc; - bool ext_zbs; - bool ext_counters; - bool ext_ifencei; - bool ext_icsr; - bool ext_zfh; - bool ext_zfhmin; - bool ext_zve32f; - bool ext_zve64f; - - char *priv_spec; - char *user_spec; - char *bext_spec; - char *vext_spec; - uint16_t vlen; - uint16_t elen; - bool mmu; - bool pmp; - bool epmp; - uint64_t resetvec; - } cfg; + RISCVCPUConfig cfg; }; =20 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1644994927540277.6029224423854; Tue, 15 Feb 2022 23:02:07 -0800 (PST) Received: from localhost ([::1]:38962 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKEKF-0005Sc-7b for importer@patchew.org; Wed, 16 Feb 2022 02:02:07 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48252) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDow-0004dj-P4 for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:29:46 -0500 Received: from esa5.hgst.iphmx.com ([216.71.153.144]:59488) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDou-0006IQ-Ev for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:29:46 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:29:41 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:02:31 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:29:43 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7NQ6TDFz1SVp0 for ; Tue, 15 Feb 2022 22:29:42 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id oI3xax2UDzdf for ; Tue, 15 Feb 2022 22:29:42 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7NM2tM2z1Rwrw; Tue, 15 Feb 2022 22:29:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644992983; x=1676528983; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jJhe4C9xKTUjuHDZsArzEwaH2LLLcRIH/N5JeKNmc74=; b=NLF7GSX9L7kaKWIQ2LhBj8K7HSwKIyv39YJ9zcllh/lVVG9VqFlVFphx etvYllcet6NYOa5AVX6XaAknCRBM0+4iC6DTc29yaIpF6gnKt6inGjGBm x2X+1PImvuFrfMfIrSGmUnBK6uL4wtWTBnJNONSxWyKJdTeyJVb3+b8KN BUGLbviv2qVg82a+nGknSYQxAX10mLJ8TyA/YyscLncINiYTJIy/FRwj4 6jSDnP7OPPWJRIEqT6SH4kNVi7kfmyBxC1vJllssRX4l/Gl8uQNLiKXuY y2ntGLO8f31j9SMddrOh+xv+F0BDLThVy2K/IgY0LD7MSut2xVw6C104U g==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="193072684" IronPort-SDR: bAmkf4OUrVZtgx6fqEY/vPkWksI3HBYfO7deoIlVMkGtoFZf2gWpKEgdo/nEadIlJmZgBDKqeX 5q/MGxSUuN1vbPLedky+oLoaw6nRvkdHwhg8pcBBo2sGaxGg4krputWqRJ+qR5qPu4lK2JL4Ib 9kGvhnFu3Zumliw5T5FcKRQ9DDGzI15F54fKuzGvI4tatkeb0Zl1Dt+Ee0mSsHC+K6p7nLi9LI PE/w+W9UJAGBmcRECSLpR21qcpJne9oOWnnk6pxGszAFSqhTQxMfdYX4DshHakvk/CGeQw6JLS c9aO8jcvePt/MoNgOqagoPdF IronPort-SDR: xt5NG991uZ+VlnkklIsY7b8vkl8xF3L8EcUcinbVUAS/Zh7Nvl1iLBTEttgMuzU3T6EMe+DSSx lYehFi9Ro290/wBVzYqnDjwywSrYFigsEmOXM7Q9pbNW3qOUDtPvYYPTn9l6fLT/ldxP2mHmMP vZKsE8tnfWw5TiE0YcWqMV2Mj+wv23Mr8yOhnHhDbvwvQLRl2/XlgtmTV3dfru5SElf3mZO1Hx ZcDdRu2h5VvqANPaWGQucFvoKfOZ/o8+y+0kagK0geA6NjWmQg2cbIedTb+cnhLfrqvg2Jnmi+ 2Kk= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644992982; x=1647584983; bh=jJhe4C9xKTUjuHDZsA rzEwaH2LLLcRIH/N5JeKNmc74=; b=Ks0LSmkFuY3tWatAWlkZG4iH4wUu1kMtWl jJ89Q8oNoey/C02jYhQfZ8AI5KB76lSxvCWMTwE5Ot2lT/L8AsvjlkBpe0mxzBbE h4gn5LcuepxTQo1lUojQMd+PtbzZqMGxZFxsUvk5YGlXYGVEa1/sUeadLYI6Qqen iEh549kanjj5dldInrR55oB/MJ9VcK632HalA0UYeHhSMxJbSFeqI8re+0bYA9su xUioHyQO5MJTlzofwDO020EaCq9w7sO/R7EbWoaKCuz1Ui0OiKFXskUXCCinSdFs ItDyBBqlpW33biehEEIwwHMD0p4vptdahCR76jBRQ1/Rdao9h3Vw== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Philipp Tomsich , Alistair Francis , Richard Henderson Subject: [PULL v2 05/35] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr Date: Wed, 16 Feb 2022 16:28:42 +1000 Message-Id: <20220216062912.319738-6-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1644994944313100001 Content-Type: text/plain; charset="utf-8" From: Philipp Tomsich As the number of extensions is growing, copying them individiually into the DisasContext will scale less and less... instead we populate a pointer to the RISCVCPUConfig structure in the DisasContext. This adds an extra indirection when checking for the availability of an extension (compared to copying the fields into DisasContext). While not a performance problem today, we can always (shallow) copy the entire structure into the DisasContext (instead of putting a pointer to it) if this is ever deemed necessary. Signed-off-by: Philipp Tomsich Reviewed-by: Alistair Francis Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Message-Id: <20220202005249.3566542-3-philipp.tomsich@vrull.eu> Signed-off-by: Alistair Francis --- target/riscv/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f0bbe80875..49e40735ce 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -76,6 +76,7 @@ typedef struct DisasContext { int frm; RISCVMXL ol; bool virt_enabled; + const RISCVCPUConfig *cfg_ptr; bool ext_ifencei; bool ext_zfh; bool ext_zfhmin; @@ -908,6 +909,7 @@ static void riscv_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) #endif ctx->misa_ext =3D env->misa_ext; ctx->frm =3D -1; /* unknown rounding mode */ + ctx->cfg_ptr =3D &(cpu->cfg); ctx->ext_ifencei =3D cpu->cfg.ext_ifencei; ctx->ext_zfh =3D cpu->cfg.ext_zfh; ctx->ext_zfhmin =3D cpu->cfg.ext_zfhmin; --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1644993219233848.9722671690213; Tue, 15 Feb 2022 22:33:39 -0800 (PST) Received: from localhost ([::1]:35302 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKDsf-0008DM-R3 for importer@patchew.org; Wed, 16 Feb 2022 01:33:37 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48308) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDp5-0004xT-2j for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:29:55 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:61632) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDp1-0006JA-Fo for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:29:54 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:29:49 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:02:37 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:29:50 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7NY3GdZz1SVp0 for ; Tue, 15 Feb 2022 22:29:49 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id fxha9LIusSRg for ; Tue, 15 Feb 2022 22:29:48 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7NR2pl8z1Rwrw; Tue, 15 Feb 2022 22:29:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644992991; x=1676528991; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=o8NA4AOxHOKirwDWriBJ4AVXxL9ADb0JRoHJbqikHhE=; b=MpudgdDHWi8VTSw+/km84d6cnT6QJHLqAVdXHeBcgCOQgFl723/4jdR2 CSjI3qiQny10LrL/ip0H/qpSlihCeAT964JVras+nywNoOVwhLvH0Q/0Z x+d/ydGDpI25gyLLFFCRhA0JlfDkxQOmwuAxx4iVojjdzdwPqagQnaQoZ 78xKhjW6HT8zntl5pHsVJ8G4BMhrEmr5X1rMcC0XayalGnbB414Uf8sWp TGNTpP0kErWazwUYeH+SQam7C6jtVNYddHHb96Ldct1i+x4qZ8QY/7CoX Wxquk8KwP2ihOExpqYgzeBX7hmNW6ZJUL9gCE4ErzN7SWrjkRhyOpiqEo w==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="297181704" IronPort-SDR: afogz5QwhRIcNED7lA+4b3YTKQGnD0u31MF6b8oSsOpfD5y1ydw2EjtYhaQgE4zeXxiLNFnu8X ylMESCNofEQwkAYYoeLTHJwzTr4eANEV4jNcKrFim+nJqUellsosCE1p3Q08RxFXcFdYiYflTH wx26WY42CNgFtpOZGCPn9wr5Fwcd9KVxG4/JTZ9oc38zpNh8O2NnOUp7DHdrLbuP80hF4JbHal d0EHggN2RFgyE/vVZncB2o8JKyuJICd5f5mwk+s1RN3BF451c4M1ozdtWEf/b09RPUxl5n+ugg IzxWEM2Dla3Sz+0DW3Q8WpzT IronPort-SDR: nyE7VcD/YbBLYZVC+chXGwFf1B1y4zZyg6jWQYgLG+HFjRRTF2dP6biWWDvO7a/f9BAOKfdhjA 2sDS5J/n4wyixQoHf95w5lovvZ8jeIcgxmdv1Ra755wV8sz3gb3K08HfA5ODW/qPc25KMs/ZY7 ozW6VHxTskfMJ+1AIvSJHCZLtI4/gtmqgw3pqP2wr/x0w+owzZyE8uoa/DJbqlXg7e7sh/BNnn YK9hiYcY0Osp9sdRbNiJ1wJPe4FwTQbM0U9oBKUZwRBNVBzVrx1ASXhUGxOcnPXC0k6rNnqo6Z eJo= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644992988; x=1647584989; bh=o8NA4AOxHOKirwDWri BJ4AVXxL9ADb0JRoHJbqikHhE=; b=kuLU1WqPqODtoVwsdBPbU/va6HLp7qCoug cZjPn4zQrTIpqPU/3qfL3HklX335L/G2G6cAnrgz5Xm0cerdbMciaH5w3S5VoYq2 nHmJwfUyMis1evTdtTw1wCLYoXnCV37y37eJPlNevQhyitZKxN/xoogNp64gsTvG 5HK7pRjwLef5gTte8IDricwqOebgPCGh6A4AQ/Lhqjmeq0n1rYltZExmXGTeQgde ZWt8rlv/HMYmb8xQyzAxTIq4Hr5YdpngklfOfvxVDoCnH2+g50vo5A6Uy/S6Xrva L8dRGvhLktm0hsY8Uc3/c76Get4p8stWIPiHmWMis7u45WaSybmA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Philipp Tomsich , Alistair Francis , Richard Henderson Subject: [PULL v2 06/35] target/riscv: access configuration through cfg_ptr in DisasContext Date: Wed, 16 Feb 2022 16:28:43 +1000 Message-Id: <20220216062912.319738-7-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1644993220460100001 Content-Type: text/plain; charset="utf-8" From: Philipp Tomsich The implementation in trans_{rvi,rvv,rvzfh}.c.inc accesses the shallow copies (in DisasContext) of some of the elements available in the RISCVCPUConfig structure. This commit redirects accesses to use the cfg_ptr copied into DisasContext and removes the shallow copies. Signed-off-by: Philipp Tomsich Reviewed-by: Alistair Francis Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Message-Id: <20220202005249.3566542-4-philipp.tomsich@vrull.eu> [ Changes by AF: - Fixup checkpatch failures ] Signed-off-by: Alistair Francis --- target/riscv/translate.c | 14 --- target/riscv/insn_trans/trans_rvi.c.inc | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 146 ++++++++++++++-------- target/riscv/insn_trans/trans_rvzfh.c.inc | 4 +- 4 files changed, 97 insertions(+), 69 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 49e40735ce..f19d5cd0c0 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -77,11 +77,6 @@ typedef struct DisasContext { RISCVMXL ol; bool virt_enabled; const RISCVCPUConfig *cfg_ptr; - bool ext_ifencei; - bool ext_zfh; - bool ext_zfhmin; - bool ext_zve32f; - bool ext_zve64f; bool hlsx; /* vector extension */ bool vill; @@ -99,8 +94,6 @@ typedef struct DisasContext { */ int8_t lmul; uint8_t sew; - uint16_t vlen; - uint16_t elen; target_ulong vstart; bool vl_eq_vlmax; uint8_t ntemp; @@ -910,13 +903,6 @@ static void riscv_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) ctx->misa_ext =3D env->misa_ext; ctx->frm =3D -1; /* unknown rounding mode */ ctx->cfg_ptr =3D &(cpu->cfg); - ctx->ext_ifencei =3D cpu->cfg.ext_ifencei; - ctx->ext_zfh =3D cpu->cfg.ext_zfh; - ctx->ext_zfhmin =3D cpu->cfg.ext_zfhmin; - ctx->ext_zve32f =3D cpu->cfg.ext_zve32f; - ctx->ext_zve64f =3D cpu->cfg.ext_zve64f; - ctx->vlen =3D cpu->cfg.vlen; - ctx->elen =3D cpu->cfg.elen; ctx->mstatus_hs_fs =3D FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); ctx->mstatus_hs_vs =3D FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); ctx->hlsx =3D FIELD_EX32(tb_flags, TB_FLAGS, HLSX); diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 3cd1b3f877..f1342f30f8 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -806,7 +806,7 @@ static bool trans_fence(DisasContext *ctx, arg_fence *a) =20 static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a) { - if (!ctx->ext_ifencei) { + if (!ctx->cfg_ptr->ext_ifencei) { return false; } =20 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index f85a9e83b4..275fded6e4 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -74,7 +74,7 @@ static bool require_zve32f(DisasContext *s) } =20 /* Zve32f doesn't support FP64. (Section 18.2) */ - return s->ext_zve32f ? s->sew <=3D MO_32 : true; + return s->cfg_ptr->ext_zve32f ? s->sew <=3D MO_32 : true; } =20 static bool require_scale_zve32f(DisasContext *s) @@ -85,7 +85,7 @@ static bool require_scale_zve32f(DisasContext *s) } =20 /* Zve32f doesn't support FP64. (Section 18.2) */ - return s->ext_zve64f ? s->sew <=3D MO_16 : true; + return s->cfg_ptr->ext_zve64f ? s->sew <=3D MO_16 : true; } =20 static bool require_zve64f(DisasContext *s) @@ -96,7 +96,7 @@ static bool require_zve64f(DisasContext *s) } =20 /* Zve64f doesn't support FP64. (Section 18.2) */ - return s->ext_zve64f ? s->sew <=3D MO_32 : true; + return s->cfg_ptr->ext_zve64f ? s->sew <=3D MO_32 : true; } =20 static bool require_scale_zve64f(DisasContext *s) @@ -107,7 +107,7 @@ static bool require_scale_zve64f(DisasContext *s) } =20 /* Zve64f doesn't support FP64. (Section 18.2) */ - return s->ext_zve64f ? s->sew <=3D MO_16 : true; + return s->cfg_ptr->ext_zve64f ? s->sew <=3D MO_16 : true; } =20 /* Destination vector register group cannot overlap source mask register. = */ @@ -174,7 +174,8 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1,= TCGv s2) TCGv s1, dst; =20 if (!require_rvv(s) || - !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) { + !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f || + s->cfg_ptr->ext_zve64f)) { return false; } =20 @@ -210,7 +211,8 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s= 1, TCGv s2) TCGv dst; =20 if (!require_rvv(s) || - !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) { + !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f || + s->cfg_ptr->ext_zve64f)) { return false; } =20 @@ -248,7 +250,7 @@ static bool trans_vsetivli(DisasContext *s, arg_vsetivl= i *a) /* vector register offset from env */ static uint32_t vreg_ofs(DisasContext *s, int reg) { - return offsetof(CPURISCVState, vreg) + reg * s->vlen / 8; + return offsetof(CPURISCVState, vreg) + reg * s->cfg_ptr->vlen / 8; } =20 /* check functions */ @@ -318,7 +320,8 @@ static bool vext_check_st_index(DisasContext *s, int vd= , int vs2, int nf, * when XLEN=3D32. (Section 18.2) */ if (get_xl(s) =3D=3D MXL_RV32) { - ret &=3D (!has_ext(s, RVV) && s->ext_zve64f ? eew !=3D MO_64 : tru= e); + ret &=3D (!has_ext(s, RVV) && + s->cfg_ptr->ext_zve64f ? eew !=3D MO_64 : true); } =20 return ret; @@ -454,7 +457,7 @@ static bool vext_wide_check_common(DisasContext *s, int= vd, int vm) { return (s->lmul <=3D 2) && (s->sew < MO_64) && - ((s->sew + 1) <=3D (s->elen >> 4)) && + ((s->sew + 1) <=3D (s->cfg_ptr->elen >> 4)) && require_align(vd, s->lmul + 1) && require_vm(vm, vd); } @@ -482,7 +485,7 @@ static bool vext_narrow_check_common(DisasContext *s, i= nt vd, int vs2, { return (s->lmul <=3D 2) && (s->sew < MO_64) && - ((s->sew + 1) <=3D (s->elen >> 4)) && + ((s->sew + 1) <=3D (s->cfg_ptr->elen >> 4)) && require_align(vs2, s->lmul + 1) && require_align(vd, s->lmul) && require_vm(vm, vd); @@ -661,7 +664,8 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, ui= nt32_t data, * The first part is vlen in bytes, encoded in maxsz of simd_desc. * The second part is lmul, encoded in data of simd_desc. */ - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data)); =20 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); @@ -819,7 +823,8 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1= , uint32_t rs2, mask =3D tcg_temp_new_ptr(); base =3D get_gpr(s, rs1, EXT_NONE); stride =3D get_gpr(s, rs2, EXT_NONE); - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data)); =20 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); @@ -925,7 +930,8 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1,= uint32_t vs2, mask =3D tcg_temp_new_ptr(); index =3D tcg_temp_new_ptr(); base =3D get_gpr(s, rs1, EXT_NONE); - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data)); =20 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2)); @@ -1065,7 +1071,8 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uin= t32_t data, dest =3D tcg_temp_new_ptr(); mask =3D tcg_temp_new_ptr(); base =3D get_gpr(s, rs1, EXT_NONE); - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data)); =20 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); @@ -1120,7 +1127,8 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs= 1, uint32_t nf, =20 uint32_t data =3D FIELD_DP32(0, VDATA, NF, nf); dest =3D tcg_temp_new_ptr(); - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data)); =20 base =3D get_gpr(s, rs1, EXT_NONE); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); @@ -1185,7 +1193,7 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true) static inline uint32_t MAXSZ(DisasContext *s) { int scale =3D s->lmul - 3; - return scale < 0 ? s->vlen >> -scale : s->vlen << scale; + return scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << sc= ale; } =20 static bool opivv_check(DisasContext *s, arg_rmrr *a) @@ -1220,7 +1228,8 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3F= n *gvec_fn, data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), - cpu_env, s->vlen / 8, s->vlen / 8, data, fn); + cpu_env, s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, fn); } mark_vs_dirty(s); gen_set_label(over); @@ -1262,7 +1271,8 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, ui= nt32_t vs2, uint32_t vm, =20 data =3D FIELD_DP32(data, VDATA, VM, vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data)); =20 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); @@ -1425,7 +1435,8 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, ui= nt32_t vs2, uint32_t vm, =20 data =3D FIELD_DP32(data, VDATA, VM, vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data)); =20 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); @@ -1508,7 +1519,8 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr = *a, tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), - cpu_env, s->vlen / 8, s->vlen / 8, + cpu_env, s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, fn); mark_vs_dirty(s); gen_set_label(over); @@ -1587,7 +1599,8 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr = *a, tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), - cpu_env, s->vlen / 8, s->vlen / 8, data, fn); + cpu_env, s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, fn); mark_vs_dirty(s); gen_set_label(over); return true; @@ -1663,7 +1676,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data, \ fns[s->sew]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -1843,7 +1857,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data, \ fns[s->sew]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -1963,7 +1978,8 @@ static bool vmulh_vv_check(DisasContext *s, arg_rmrr = *a) * are not included for EEW=3D64 in Zve64*. (Section 18.2) */ return opivv_check(s, a) && - (!has_ext(s, RVV) && s->ext_zve64f ? s->sew !=3D MO_64 : true); + (!has_ext(s, RVV) && + s->cfg_ptr->ext_zve64f ? s->sew !=3D MO_64 : true); } =20 static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a) @@ -1976,7 +1992,8 @@ static bool vmulh_vx_check(DisasContext *s, arg_rmrr = *a) * are not included for EEW=3D64 in Zve64*. (Section 18.2) */ return opivx_check(s, a) && - (!has_ext(s, RVV) && s->ext_zve64f ? s->sew !=3D MO_64 : true); + (!has_ext(s, RVV) && + s->cfg_ptr->ext_zve64f ? s->sew !=3D MO_64 : true); } =20 GEN_OPIVV_GVEC_TRANS(vmul_vv, mul) @@ -2046,7 +2063,8 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_= v *a) tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); =20 tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), - cpu_env, s->vlen / 8, s->vlen / 8, data, + cpu_env, s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, fns[s->sew]); gen_set_label(over); } @@ -2083,7 +2101,8 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_= x *a) }; =20 tcg_gen_ext_tl_i64(s1_i64, s1); - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, = data)); + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); fns[s->sew](dest, s1_i64, cpu_env, desc); =20 @@ -2123,7 +2142,8 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_= i *a) =20 s1 =3D tcg_constant_i64(simm); dest =3D tcg_temp_new_ptr(); - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, = data)); + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); fns[s->sew](dest, s1, cpu_env, desc); =20 @@ -2176,7 +2196,8 @@ static bool vsmul_vv_check(DisasContext *s, arg_rmrr = *a) * for EEW=3D64 in Zve64*. (Section 18.2) */ return opivv_check(s, a) && - (!has_ext(s, RVV) && s->ext_zve64f ? s->sew !=3D MO_64 : true); + (!has_ext(s, RVV) && + s->cfg_ptr->ext_zve64f ? s->sew !=3D MO_64 : true); } =20 static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a) @@ -2187,7 +2208,8 @@ static bool vsmul_vx_check(DisasContext *s, arg_rmrr = *a) * for EEW=3D64 in Zve64*. (Section 18.2) */ return opivx_check(s, a) && - (!has_ext(s, RVV) && s->ext_zve64f ? s->sew !=3D MO_64 : true); + (!has_ext(s, RVV) && + s->cfg_ptr->ext_zve64f ? s->sew !=3D MO_64 : true); } =20 GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check) @@ -2275,7 +2297,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data, \ fns[s->sew - 1]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -2302,7 +2325,8 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, ui= nt32_t vs2, dest =3D tcg_temp_new_ptr(); mask =3D tcg_temp_new_ptr(); src2 =3D tcg_temp_new_ptr(); - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data)); =20 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); @@ -2391,7 +2415,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data, \ fns[s->sew - 1]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -2464,7 +2489,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data, \ fns[s->sew - 1]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -2583,7 +2609,8 @@ static bool do_opfv(DisasContext *s, arg_rmr *a, data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs2), cpu_env, - s->vlen / 8, s->vlen / 8, data, fn); + s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, fn); mark_vs_dirty(s); gen_set_label(over); return true; @@ -2696,7 +2723,8 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_= v_f *a) do_nanbox(s, t1, cpu_fpr[a->rs1]); =20 dest =3D tcg_temp_new_ptr(); - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, = data)); + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); =20 fns[s->sew - 1](dest, t1, cpu_env, desc); @@ -2782,7 +2810,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data, \ fns[s->sew - 1]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -2831,7 +2860,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data, \ fns[s->sew]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -2896,7 +2926,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data, \ fns[s->sew - 1]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -2947,7 +2978,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data, \ fns[s->sew]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -2986,7 +3018,7 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check) static bool reduction_widen_check(DisasContext *s, arg_rmrr *a) { return reduction_check(s, a) && (s->sew < MO_64) && - ((s->sew + 1) <=3D (s->elen >> 4)); + ((s->sew + 1) <=3D (s->cfg_ptr->elen >> 4)); } =20 GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check) @@ -3034,7 +3066,8 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) = \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, fn); \ + s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data, fn); \ mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ @@ -3067,7 +3100,8 @@ static bool trans_vcpop_m(DisasContext *s, arg_rmr *a) mask =3D tcg_temp_new_ptr(); src2 =3D tcg_temp_new_ptr(); dst =3D dest_gpr(s, a->rd); - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data= )); + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data)); =20 tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); @@ -3099,7 +3133,8 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *= a) mask =3D tcg_temp_new_ptr(); src2 =3D tcg_temp_new_ptr(); dst =3D dest_gpr(s, a->rd); - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data= )); + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data)); =20 tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); @@ -3134,7 +3169,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \ vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \ - cpu_env, s->vlen / 8, s->vlen / 8, \ + cpu_env, s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, \ data, fn); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -3174,7 +3210,8 @@ static bool trans_viota_m(DisasContext *s, arg_viota_= m *a) }; tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs2), cpu_env, - s->vlen / 8, s->vlen / 8, data, fns[s->sew]); + s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, fns[s->sew]); mark_vs_dirty(s); gen_set_label(over); return true; @@ -3200,7 +3237,8 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) gen_helper_vid_v_w, gen_helper_vid_v_d, }; tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), - cpu_env, s->vlen / 8, s->vlen / 8, + cpu_env, s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, fns[s->sew]); mark_vs_dirty(s); gen_set_label(over); @@ -3554,7 +3592,8 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rm= rr *a) =20 if (a->vm && s->vl_eq_vlmax) { int scale =3D s->lmul - (s->sew + 3); - int vlmax =3D scale < 0 ? s->vlen >> -scale : s->vlen << scale; + int vlmax =3D scale < 0 ? + s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << sc= ale; TCGv_i64 dest =3D tcg_temp_new_i64(); =20 if (a->rs1 =3D=3D 0) { @@ -3586,7 +3625,8 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rm= rr *a) =20 if (a->vm && s->vl_eq_vlmax) { int scale =3D s->lmul - (s->sew + 3); - int vlmax =3D scale < 0 ? s->vlen >> -scale : s->vlen << scale; + int vlmax =3D scale < 0 ? + s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << sc= ale; if (a->rs1 >=3D vlmax) { tcg_gen_gvec_dup_imm(MO_64, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), 0); @@ -3638,7 +3678,8 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r= *a) data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), - cpu_env, s->vlen / 8, s->vlen / 8, data, + cpu_env, s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, fns[s->sew]); mark_vs_dirty(s); gen_set_label(over); @@ -3657,7 +3698,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME = * a) \ if (require_rvv(s) && \ QEMU_IS_ALIGNED(a->rd, LEN) && \ QEMU_IS_ALIGNED(a->rs2, LEN)) { \ - uint32_t maxsz =3D (s->vlen >> 3) * LEN; \ + uint32_t maxsz =3D (s->cfg_ptr->vlen >> 3) * LEN; \ if (s->vstart =3D=3D 0) { = \ /* EEW =3D 8 */ \ tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \ @@ -3742,7 +3783,8 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, u= int8_t seq) =20 tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs2), cpu_env, - s->vlen / 8, s->vlen / 8, data, fn); + s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, fn); =20 mark_vs_dirty(s); gen_set_label(over); diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_= trans/trans_rvzfh.c.inc index 5a7cac8958..608c51da2c 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -17,13 +17,13 @@ */ =20 #define REQUIRE_ZFH(ctx) do { \ - if (!ctx->ext_zfh) { \ + if (!ctx->cfg_ptr->ext_zfh) { \ return false; \ } \ } while (0) =20 #define REQUIRE_ZFH_OR_ZFHMIN(ctx) do { \ - if (!(ctx->ext_zfh || ctx->ext_zfhmin)) { \ + if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin)) { \ return false; \ } \ } while (0) --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1644994928909419.73989357660696; Tue, 15 Feb 2022 23:02:08 -0800 (PST) Received: from localhost ([::1]:38968 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKEKH-0005Sm-18 for importer@patchew.org; Wed, 16 Feb 2022 02:02:09 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48326) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDp6-00051Z-Ms for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:29:56 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:61643) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDp4-0006JS-FV for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:29:56 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:29:53 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:02:41 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:29:53 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7Nd0CZMz1SVp0 for ; Tue, 15 Feb 2022 22:29:53 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id zMot2s3une1J for ; Tue, 15 Feb 2022 22:29:52 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7NY1JYCz1SHwl; Tue, 15 Feb 2022 22:29:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644992994; x=1676528994; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uYE/mOCtndKnFgc+9uvpYG2BClhduKs/P6ABzwgR2HE=; b=YAp83XjIphEWuJohWajiaVTk1DNjFOsyLT4/4MSu+2FC4scssa4S8loM wfBNj4gi/hpsxpOBE1GdsROc4krqbKPRUzbVBEIN1PE5M+NN0CtGbTPpj 3BOp5e6e1+1Fu6uWYamtXPzjTlv5vuu9HWyjR/RFCWa4ZRIVAGqLOnUY0 PXjCC7Pk4d7B/UiqqFzyR2PLw0Nhk1uiCx7EsGmTj/Ra0ZMj7BMZioKtE iW9R43IGeV0a1/wqTc+tpZzw0w5u0+ei49F5PvSJR7lny9BEXOkq73B1k wGo6C9JwpBLJ5gJfISoaqZGdpEkkKRGnwJojjgv2wCDZy4OCtYqhpjFC/ A==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="297181708" IronPort-SDR: zZkCU2tkhguI8AtCbb7o3ixobRdHM4bephyHX5PHjOKTA8ojE6JJ0OZN/bHyNsoonQTU0h2ogV PBaml0dM2BDp+9uTt6LWLROAg3xzYgw9ItOFZ1UoUs7F9YjuK1NgxLHRLnnphC4ab0GUd94UHy n50G8c65NIbSfC+OGOP1XMxCew/Fmu6CKWW/TsrX13aWnlr/CzQpx3AKgtnxjgBS5eB6CAFcWe +bYWO2vy2OqTZzKlqvzr2CUHCWJyqN82bkH5CKiMxkXHm4IZA5WzkjlwEh76dRfeXbfLZroFLA 7zwe9E32PiOqWVuTliov8wzx IronPort-SDR: hNS31K9QCnT6xF0fGGNp4z8W3i0cBsy9cMdG8aXOlxd+6LRWSnC7JRMHpaSaqQ/IqdXtXXklH7 z5jaYSrJmbci0UuDlBb26r1iSJeDHtgtke/vx7n1/3jk8ewZl5WcCOwstBt0KZo7n/+msuwGBt 5hbk5U5NunaIDXdsiTOXS7UUdas8iC2c2zZhb23C5g2a2BDF7REEfxLPSvJ5AIB3bQt+MxXPlP w6SW3hGWGAX+oJyGIdiG+2OIFwS1TOvZjno10KEsCMaApJmPs1wHapsFcNpBrxaqT/P86YtQFj jMg= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644992992; x=1647584993; bh=uYE/mOCtndKnFgc+9u vpYG2BClhduKs/P6ABzwgR2HE=; b=eTKpetcSvEE2WNiWuszFD7/28hUybXVxy2 MQ06YyPrwL5MTr0wfPm3XaAxRjVsP5YJfCaX2JVz7qusUONTcOx/cv/V3ChkWwng F7r2mhLEDoKNQlwN0BFelJ6YJq4CAt1BwhhB5oh+XChZg2vjxlDcP9EmpCHcUmu/ 34DQE2kEj+P0LUszTPANM6jSKoFg7S3AB45Ea6ZOH76AS550NkN8R1E3OzViu2ij QoBqi7uWniMtWkpbkzNgHXkix2WLuxl/z59yOfmYKDg6tjIW37uwU4Kl6iUq3FvW lndzL3GMtnZ5iBQge+z+hSKKPrV9Z9EEkAVEG5Res5ks9lpH+MoA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Philipp Tomsich , Alistair Francis , Richard Henderson Subject: [PULL v2 07/35] target/riscv: access cfg structure through DisasContext Date: Wed, 16 Feb 2022 16:28:44 +1000 Message-Id: <20220216062912.319738-8-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1644994931549100002 Content-Type: text/plain; charset="utf-8" From: Philipp Tomsich The Zb[abcs] support code still uses the RISCV_CPU macros to access the configuration information (i.e., check whether an extension is available/enabled). Now that we provide this information directly from DisasContext, we can access this directly via the cfg_ptr field. Signed-off-by: Philipp Tomsich Reviewed-by: Alistair Francis Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Message-Id: <20220202005249.3566542-5-philipp.tomsich@vrull.eu> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvb.c.inc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 810431a1d6..f9bd3b7ec4 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -19,25 +19,25 @@ */ =20 #define REQUIRE_ZBA(ctx) do { \ - if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) { \ + if (ctx->cfg_ptr->ext_zba) { \ return false; \ } \ } while (0) =20 #define REQUIRE_ZBB(ctx) do { \ - if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) { \ + if (ctx->cfg_ptr->ext_zbb) { \ return false; \ } \ } while (0) =20 #define REQUIRE_ZBC(ctx) do { \ - if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) { \ + if (ctx->cfg_ptr->ext_zbc) { \ return false; \ } \ } while (0) =20 #define REQUIRE_ZBS(ctx) do { \ - if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) { \ + if (ctx->cfg_ptr->ext_zbs) { \ return false; \ } \ } while (0) --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1644995474600582.3542611656828; Tue, 15 Feb 2022 23:11:14 -0800 (PST) Received: from localhost ([::1]:47674 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKET3-0003BT-6k for importer@patchew.org; Wed, 16 Feb 2022 02:11:13 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48344) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDpA-0005BG-Oi for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:00 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:61649) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDp8-0006K3-Hp for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:00 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:29:57 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:02:45 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:29:57 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7Nj1CXtz1SVp0 for ; Tue, 15 Feb 2022 22:29:57 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id uvqCYM0flvwC for ; Tue, 15 Feb 2022 22:29:56 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7Nd3NMKz1SHwl; Tue, 15 Feb 2022 22:29:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644992998; x=1676528998; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LvOnLpqh0OHiSklef1KLb+8AQDDkHx+78+oM9pbP6k4=; b=cE/H1x7SJEZ6sF3Brd0MDt7yKt/tcPWGVDiVQ7qOEuQUNl6B0UB5CR2V iLpYX0WUd6AaNLAey7aAbWbeq0TZawM5IstRnurW9DtSQZYe6EEmSaLwI 9lcJd10x9VG7VucMjJ+y4BDe4qjKJhlcX+d575U9+D6q7+jXpY0KyePG+ VJghU0jeqGfM8GWdomCf5zrg4JFN7BFW24pUe7aDNMszGqxPt1YcBIVYb KwH7F6kZJrCt+kUkYd2iKgc3nUT3sE29I1WjMoyrNWlYInl7EgPZxIP5I gKZhfuwxtmG96Mvcb+Fsn4ZkOyfCdmuCBnzJ2+f/N0K97gArWWBYqUxDw w==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="297181714" IronPort-SDR: NrJcImrAg8wx8OIbF7aRMnLd76xjIGryjNx3huOA4I8EcM0WzfhX5SL26zaebrfgknl6mWX9lg mpAYedFFvSNueYyIJ/gNdO+lWd9cLkg31YCctM1thhqeX62yiNiClW/xwvti/m9ODXOM5Y1PzO hV0xJ3Ki8Zzcic9uwdDHJkHIIl7/6NkHJwOhmii8Rtku58ouF5dPS+ucGoFQZXpEIuGwHZsK6q yO7xWhMHUwKoL0X9PVR5jzmicEGQkdiMoTPbbpKTLKXYUxkHt6/aV74KoDsiWx8gCoLfnNaizX vyWdLOvfBP8VM0JAydB3urKC IronPort-SDR: aSDglZdaRCaQisGigoh5lrP9XfufNA8vGW43rZDVQCt3VVHPcHF6Amxs3d1VmjxwfLqm6RdS3a RAPM/L8qrgd/viQMsILwbvLlj1qUx0MiyUpybGRehr4uX9tzfYwyol7E+Da9QK33TxK32Mq3IL GnTWWv4psJZot361OgOYa7PXzgBi8fxZkXomtjQcQRVTYm4jc7Ltga3z9pYYZnbSUQFTWWTc4Y NBasHou47BZjSfWv8ut/F2Xiudn+shuptkFRxGMeJvBY7b/xRpz08nt19amlsdFbZY3yzgYSP3 bH8= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644992996; x=1647584997; bh=LvOnLpqh0OHiSklef1 KLb+8AQDDkHx+78+oM9pbP6k4=; b=r0HX7tNwHaAltbnLO1IryN2mrIG+dusVo+ 1Uu7Umdi1fOuMrNCma0kwbSEj3NdpEHK12tk3j/SP1HlpmubjS7j60FbdlogPzhD SEhguHPx+Ox/ih1IlOQ5c1gbvYakT6/V6lI0juPfWndpuBJOVKjJUDM/Vb/Au+QD JARrNM6dhCHsFDNyA4gNJ62j+mrG0qtcEKS5to0Dg35QeM0iiGyOdk6tu15mtnMM UpyyTsIqxXz169eg4dUuD2op9ASiSS5vJXJ3tC+OnvMmxd505iphwBbesjX86at2 9vaP5aAybJvlf1i9X6t3gZxFwtXBDrKaJLXDck4Ik6zy+r9JjcUA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Philipp Tomsich , Richard Henderson , Alistair Francis Subject: [PULL v2 08/35] target/riscv: iterate over a table of decoders Date: Wed, 16 Feb 2022 16:28:45 +1000 Message-Id: <20220216062912.319738-9-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1644995474995100003 Content-Type: text/plain; charset="utf-8" From: Philipp Tomsich To split up the decoder into multiple functions (both to support vendor-specific opcodes in separate files and to simplify maintenance of orthogonal extensions), this changes decode_op to iterate over a table of decoders predicated on guard functions. This commit only adds the new structure and the table, allowing for the easy addition of additional decoders in the future. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20220202005249.3566542-6-philipp.tomsich@vrull.eu> Signed-off-by: Alistair Francis --- target/riscv/translate.c | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f19d5cd0c0..30b1b68341 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -111,6 +111,11 @@ static inline bool has_ext(DisasContext *ctx, uint32_t= ext) return ctx->misa_ext & ext; } =20 +static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) +{ + return true; +} + #ifdef TARGET_RISCV32 #define get_xl(ctx) MXL_RV32 #elif defined(CONFIG_USER_ONLY) @@ -855,15 +860,26 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) =20 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opc= ode) { - /* check for compressed insn */ + /* + * A table with predicate (i.e., guard) functions and decoder functions + * that are tested in-order until a decoder matches onto the opcode. + */ + static const struct { + bool (*guard_func)(DisasContext *); + bool (*decode_func)(DisasContext *, uint32_t); + } decoders[] =3D { + { always_true_p, decode_insn32 }, + }; + + /* Check for compressed insn */ if (extract16(opcode, 0, 2) !=3D 3) { if (!has_ext(ctx, RVC)) { gen_exception_illegal(ctx); } else { ctx->opcode =3D opcode; ctx->pc_succ_insn =3D ctx->base.pc_next + 2; - if (!decode_insn16(ctx, opcode)) { - gen_exception_illegal(ctx); + if (decode_insn16(ctx, opcode)) { + return; } } } else { @@ -873,10 +889,16 @@ static void decode_opc(CPURISCVState *env, DisasConte= xt *ctx, uint16_t opcode) ctx->base.pc_next + 2)); ctx->opcode =3D opcode32; ctx->pc_succ_insn =3D ctx->base.pc_next + 4; - if (!decode_insn32(ctx, opcode32)) { - gen_exception_illegal(ctx); + + for (size_t i =3D 0; i < ARRAY_SIZE(decoders); ++i) { + if (decoders[i].guard_func(ctx) && + decoders[i].decode_func(ctx, opcode32)) { + return; + } } } + + gen_exception_illegal(ctx); } =20 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cs) --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164499911409629.020418197150775; Wed, 16 Feb 2022 00:11:54 -0800 (PST) Received: from localhost ([::1]:45890 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKFPk-00018Z-S3 for importer@patchew.org; Wed, 16 Feb 2022 03:11:52 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48380) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDpF-0005Jj-6e for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:05 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:61649) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDpC-0006K3-Om for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:04 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:30:02 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:02:50 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:30:02 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7Nn5l6gz1SVny for ; Tue, 15 Feb 2022 22:30:01 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id gNTkv6q73XHf for ; Tue, 15 Feb 2022 22:30:00 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7Nj4Xgnz1Rwrw; Tue, 15 Feb 2022 22:29:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993002; x=1676529002; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BHptb7kbEv714Dh/R5SnIIpNuw/wfBKBUjAPWBpglVs=; b=gAcwrZSaZhxlnNyO+b7Smezmfs+zaIqRM69GHUL9OKTph2HOl6mV+tBa VcHm9/Lq/P0nT0sTKAEY/9vsu5OBZPbltKAfQPLKVpRV2ewK5W3VyEw3H g9ev0yl1hHbumccLRSoYO/ztzWd/zWV972AnaDFd5E4SW3Ik4dX7OEfzd fk0Y0sMAUm1oZVZBUgHaahny9kAmfutxcMzsYA4VFvuyxTy/1Mh/7IhKO izs8tzzoTl3RzaH6k+i2099G5JpHPrgvZ2n9kRLCqcOkWgcAi8w/Vig0S 57dSp4ll1OJPfCtVjPKrLNlUqHFLq9ISaidcCAJubkkTdMIIF0AbOiGPH Q==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="297181718" IronPort-SDR: 2BZUatzl82KZ342audCHh0m/qmOQGzvpcLos2MyUugg1S2rA+GBXxrWuGSkRwkyiMZbvkgE/uK nraH8DU9TT0u3JLZSEn5qM6qzDX0az7KPFfY4B5N3hjsBuXWej1KbsrwmAEPhtVmcX7EL4hLJH drWnmobcgLg/B4Nh5oSI4hJS9xz91L2KWgCySxKhVPlIlVjjEKE0EESoLzAIiDubIJABhiQHUk yAVEsdurcMulKYloKb+640tsR1kQFWArY2kagWEuUx+J8EoXDIqlB/3r58vrOhzl2UAzIm1PYL PkSVI08Rn/9RwpTL8YpSMXdX IronPort-SDR: 0QQpJ3EyjkfR/5KfmPAZOQRvJq+ALyBoi3a0YvUyjFnKm3Chpt6KXQ/ZjMDH+Lawsx9U3FE49s 5JIJ4omgdS58HptUDO8fQb2hUKksGNG+CLZDNZ9aBKuoHKIQJPdfp/a3ZNnxd6F2hI/pCfQ2bJ KxRaCrkwjJsKQFhpRyFLH/r4qo6YJ1Ln+J0v4Ke+DPZxqRif3qthN6J2UZJOJWVynKOzcyvnfo PM21p7ri94TPGMicuFdlmzti1fWlMQcybxC6dX51hofl3vH4A2gcCfW1gl2Dg0oAVyf8/l/rzI LDY= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993000; x=1647585001; bh=BHptb7kbEv714Dh/R5 SnIIpNuw/wfBKBUjAPWBpglVs=; b=eNBIVCrOsTEfdOOM2lXdWMdOPGAhvI1JGI u/q3vR4314xwNln8z6YrWcbBH3XGVlp7hq5muR9yfddFUO9WRgpr+0A8BlZNZiuT TJlY/gXj6KIMDv97ySXKZTgXxQd36DJIDOQCUZBWKEBP4ysCNxq3o41UG/YL3R5a TbyBBrqliq5PXt0A4P2kO5+ihsa64pUhT2qwzdxxjN++a/tSjbmgy7Gu5uxnAj/E 5FhtC412IS66zjE15SS2y06Its4mHWvSBvqsRsjTQdeB4W+bHPMam6JfxmUbN+pM LrzPMpwZJALtUqs6h7t1oT4NS5gGK94+rOVfIZlKRtEXzWT38WjQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Philipp Tomsich , Richard Henderson , Alistair Francis Subject: [PULL v2 09/35] target/riscv: Add XVentanaCondOps custom extension Date: Wed, 16 Feb 2022 16:28:46 +1000 Message-Id: <20220216062912.319738-10-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1644999115358100001 Content-Type: text/plain; charset="utf-8" From: Philipp Tomsich This adds the decoder and translation for the XVentanaCondOps custom extension (vendor-defined by Ventana Micro Systems), which is documented at https://github.com/ventanamicro/ventana-custom-extensions/rel= eases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf This commit then also adds a guard-function (has_XVentanaCondOps_p) and the decoder function to the table of decoders, enabling the support for the XVentanaCondOps extension. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20220202005249.3566542-7-philipp.tomsich@vrull.eu> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 ++ target/riscv/XVentanaCondOps.decode | 25 ++++++++++++ target/riscv/cpu.c | 3 ++ target/riscv/translate.c | 12 ++++++ .../insn_trans/trans_xventanacondops.c.inc | 39 +++++++++++++++++++ target/riscv/meson.build | 1 + 6 files changed, 83 insertions(+) create mode 100644 target/riscv/XVentanaCondOps.decode create mode 100644 target/riscv/insn_trans/trans_xventanacondops.c.inc diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1175915c0d..aacc997d56 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -329,6 +329,9 @@ struct RISCVCPUConfig { bool ext_zve32f; bool ext_zve64f; =20 + /* Vendor-specific custom extensions */ + bool ext_XVentanaCondOps; + char *priv_spec; char *user_spec; char *bext_spec; diff --git a/target/riscv/XVentanaCondOps.decode b/target/riscv/XVentanaCon= dOps.decode new file mode 100644 index 0000000000..5aef7c3d72 --- /dev/null +++ b/target/riscv/XVentanaCondOps.decode @@ -0,0 +1,25 @@ +# +# RISC-V translation routines for the XVentanaCondOps extension +# +# Copyright (c) 2022 Dr. Philipp Tomsich, philipp.tomsich@vrull.eu +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: VTx-family custom instructions +# Custom ISA extensions for Ventana Micro Systems RISC-V cores +# (https://github.com/ventanamicro/ventana-custom-extensions/re= leases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf) + +# Fields +%rs2 20:5 +%rs1 15:5 +%rd 7:5 + +# Argument sets +&r rd rs1 rs2 !extern + +# Formats +@r ....... ..... ..... ... ..... ....... &r %rs2 %= rs1 %rd + +# *** RV64 Custom-3 Extension *** +vt_maskc 0000000 ..... ..... 110 ..... 1111011 @r +vt_maskcn 0000000 ..... ..... 111 ..... 1111011 @r diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5ada71e5bf..1238aabe3f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -733,6 +733,9 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), =20 + /* Vendor-specific custom extensions */ + DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), + /* These are experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), /* ePMP 0.9.3 */ diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 30b1b68341..eaf5a72c81 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -116,6 +116,14 @@ static bool always_true_p(DisasContext *ctx __attribu= te__((__unused__))) return true; } =20 +#define MATERIALISE_EXT_PREDICATE(ext) \ + static bool has_ ## ext ## _p(DisasContext *ctx) \ + { \ + return ctx->cfg_ptr->ext_ ## ext ; \ + } + +MATERIALISE_EXT_PREDICATE(XVentanaCondOps); + #ifdef TARGET_RISCV32 #define get_xl(ctx) MXL_RV32 #elif defined(CONFIG_USER_ONLY) @@ -854,9 +862,12 @@ static uint32_t opcode_at(DisasContextBase *dcbase, ta= rget_ulong pc) #include "insn_trans/trans_rvb.c.inc" #include "insn_trans/trans_rvzfh.c.inc" #include "insn_trans/trans_privileged.c.inc" +#include "insn_trans/trans_xventanacondops.c.inc" =20 /* Include the auto-generated decoder for 16 bit insn */ #include "decode-insn16.c.inc" +/* Include decoders for factored-out extensions */ +#include "decode-XVentanaCondOps.c.inc" =20 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opc= ode) { @@ -869,6 +880,7 @@ static void decode_opc(CPURISCVState *env, DisasContext= *ctx, uint16_t opcode) bool (*decode_func)(DisasContext *, uint32_t); } decoders[] =3D { { always_true_p, decode_insn32 }, + { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, }; =20 /* Check for compressed insn */ diff --git a/target/riscv/insn_trans/trans_xventanacondops.c.inc b/target/r= iscv/insn_trans/trans_xventanacondops.c.inc new file mode 100644 index 0000000000..16849e6d4e --- /dev/null +++ b/target/riscv/insn_trans/trans_xventanacondops.c.inc @@ -0,0 +1,39 @@ +/* + * RISC-V translation routines for the XVentanaCondOps extension. + * + * Copyright (c) 2021-2022 VRULL GmbH. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +static bool gen_vt_condmask(DisasContext *ctx, arg_r *a, TCGCond cond) +{ + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); + + tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, ctx->zero); + + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +static bool trans_vt_maskc(DisasContext *ctx, arg_r *a) +{ + return gen_vt_condmask(ctx, a, TCG_COND_NE); +} + +static bool trans_vt_maskcn(DisasContext *ctx, arg_r *a) +{ + return gen_vt_condmask(ctx, a, TCG_COND_EQ); +} diff --git a/target/riscv/meson.build b/target/riscv/meson.build index a3997ed580..91f0ac32ff 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -4,6 +4,7 @@ dir =3D meson.current_source_dir() gen =3D [ decodetree.process('insn16.decode', extra_args: ['--static-decode=3Ddeco= de_insn16', '--insnwidth=3D16']), decodetree.process('insn32.decode', extra_args: '--static-decode=3Ddecod= e_insn32'), + decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decod= e=3Ddecode_XVentanaCodeOps'), ] =20 riscv_ss =3D ss.source_set() --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1644999516387773.9923909895248; Wed, 16 Feb 2022 00:18:36 -0800 (PST) Received: from localhost ([::1]:53534 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKFWF-0006gA-9P for importer@patchew.org; Wed, 16 Feb 2022 03:18:35 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48428) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDpI-0005RU-DQ for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:08 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:61649) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDpG-0006K3-7X for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:08 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:30:05 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:02:53 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:30:05 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7Ns1KW1z1Rwrw for ; Tue, 15 Feb 2022 22:30:05 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id rh45ubxyMtvc for ; Tue, 15 Feb 2022 22:30:04 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7Nn600bz1SVp1; Tue, 15 Feb 2022 22:30:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993006; x=1676529006; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1fU6cqKCGbr6WNItb3Jk0dOYrbRZzurPXX5iPA9BtE4=; b=bbTJJXUaSTbMwA5VuapZ//q4d5ypkLc+qwWy8R0OFSGPgfHxMhPVubtK EqWhPDRntjF0iBaI64S87rdrrCy2fAHteZ7o3gjUaLxB4Mi8AlTX3mT3x P+pWWIwjv+QWbi2QAfLB0R/bgppl90R5sDY9GiuQuLd1rAlLrlT9y9Ysn yqd3xEIZ/mj5aNgYPRQOXkJwJTuzXLEkYJTCbjKJyjBGHYsSNlyNAjh+V E5gHApdJ1TkQ9NaSWtxACEAEFVBQ5ERUGi6Ne10bWwZuZEuGm92FImKsH +IcB1Fsj6ZS8b78wWF13pvA30NzRCgpg4lziCgoZwAxL++xQ/eypSZIJv Q==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="297181721" IronPort-SDR: xyydeil+7zNmRGt0s3dXpAVwdyL+8gxQKPCRadogNQWEHPgrIDHJKLaGBqqPQq7TRULb8Y5og2 BiP34Sbhvwy8hBHdlaYySuatxV6OpeMKP0PXHnjZzU/b9fZN9x9eC3nLJzduKXv9GGAtoacVMm 7pnmN99v2lAYDGWwMCy9DXUp61XbPZUXpMEQpTkqmctALsNfMrx5YzOJeSbGXZROvGtG8eYDWt HTTc/wk34l06+d7DGxKlkTGe7OjMSCOReWI4/oSUyZ+RLG7Ctpt19fjofVzTaT0xJ6mlDMvkLS FClf8wPoup+xHGddOVHt6zhD IronPort-SDR: 2JFcIIQhj0saNiNPj9nGXRk6wO5pvzA6PjG1snp/u/8r2lxCI+REUATHLoOE/v60Ej7yMH+sGL mnfCyb+W1MOx5xt9VtBxVpOGCPJJ46jkkZ1eZcT3/tzfrbi3llNQl7g5C9zjlimnrt++gncZeG 3pi0wTlik+/U6JLA2yh0R4pFzSQ7eMibpr1GB/ptSinujugPbeKHNd2kBOFTmveSdxdsV57nGR SI1nomcBKVdj53qdx4KBdQ9cB3sCE6QAbcdLgfwjTedUAdrntuaQGqeSXSAFiw1Zx8FWbVvx1D En8= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993004; x=1647585005; bh=1fU6cqKCGbr6WNItb3 Jk0dOYrbRZzurPXX5iPA9BtE4=; b=UEEy533yoMdG/VzR0LlIRGdnqZBRi+al8R MBKOSxP2XpgzQrvPDltxGj9Rp1dkECr7nJw3Se0Hq7UgWSlOjJbtb7IsZgxM9rI2 mFNEECWH58h7igFHoCrBNKclqMVXptAh7Lv+GG00lse6uPPBlt++J1j1s/lTSRfq lo7E5Icnu/9+bsJ60nDdUvWlkkz4OojCJi1D+ce3XezM98BqJWXT6MxgJPdKLFky 0W/RtrxuHuqSefuOBEBNLu/bFN9BFV2Ho1dJnn/4oRDBMqX8h/PpOTnsETXjHZWQ Ccn9aLP1y0BxDs3GO52EnjThTbIpc/mW8JB79GQdX0K3axPOa6Hg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Philipp Tomsich , Richard Henderson , Alistair Francis Subject: [PULL v2 10/35] target/riscv: add a MAINTAINERS entry for XVentanaCondOps Date: Wed, 16 Feb 2022 16:28:47 +1000 Message-Id: <20220216062912.319738-11-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1644999518765100001 Content-Type: text/plain; charset="utf-8" From: Philipp Tomsich The XVentanaCondOps extension is supported by VRULL on behalf of the Ventana Micro. Add myself as a point-of-contact. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20220202005249.3566542-8-philipp.tomsich@vrull.eu> Signed-off-by: Alistair Francis --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4b3ae2ab08..81aa31b5e1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -286,6 +286,13 @@ F: include/hw/riscv/ F: linux-user/host/riscv32/ F: linux-user/host/riscv64/ =20 +RISC-V XVentanaCondOps extension +M: Philipp Tomsich +L: qemu-riscv@nongnu.org +S: Supported +F: target/riscv/XVentanaCondOps.decode +F: target/riscv/insn_trans/trans_xventanacondops.c.inc + RENESAS RX CPUs R: Yoshinori Sato S: Orphan --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1644996191732782.9107230215888; Tue, 15 Feb 2022 23:23:11 -0800 (PST) Received: from localhost ([::1]:56442 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKEec-0001Js-92 for importer@patchew.org; Wed, 16 Feb 2022 02:23:10 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48480) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDpM-0005bT-RF for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:12 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:61649) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDpK-0006K3-Bu for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:12 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:30:09 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:02:57 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:30:10 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7Nx37TMz1SVnx for ; Tue, 15 Feb 2022 22:30:09 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id 3OE2N-ALB6jl for ; Tue, 15 Feb 2022 22:30:09 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7Ns5pnFz1Rwrw; Tue, 15 Feb 2022 22:30:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993010; x=1676529010; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lq1YADGSCZFa18AOrj3oFEX4AW2ekGKuYY1tpRjAVEA=; b=Z5iD0fpMLr+VRXQXtkLKA+D+P0SivUuqYf+I/l5Wp3u4F0e3QbVMdvOj 8tLJXYOm74TuIhEhKf61kTFauHHxoPoXi8UXsZOkFM/4VkNrruBKUnN+R 6g5akq6tWhgyqHr8MNN40BtD/jrymS/pr0x5Eg1w9A4KxIU3wveuZ0OnQ I4jqpPR8TOi6W1QWSGnUyvInIkIDEF3lAwDJh35M1W/esZ/2TRHbvSQZN y1us/3MBHmozgYetx3eDVR8tecwRIFtxKIdlhs2tVfoeIsL21D0Nvjp8s Ia94hIwKYGNdfqEk2i/F38kP6duIDWmdisZAvwsnR6fDIoiifeHIMq5i2 A==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="297181729" IronPort-SDR: BeoGIgvlkJSAAKWVO5nrUYeR9LBlJivLAv1a2CrC9xbAlSOTcgXs1tg+l0rM5TSbgs5kq/MrvT SAFBmsmgl1qzs5H3GVlhMh6sZJrlbbnlHFx96zgH8H1I9SucJgYLVsQTF1tRgGSTmBQ1StpVy9 u7WJf8GJyV+edAvOjf7IFSP9ms5j1jqBUmmzOSfJ7+xyW5qU52adQwvE4X5AUihaa7WLhkdi9P v7CoD8SMeQIiJyplpSTeI9QrbRZ7TyWHy90d3FSCiB7R/nsxziaU/S3nYzlviRAxzElWfXFIc3 Um10Z2ncJJ1TDgSEP3GqZrdr IronPort-SDR: 5PGLwW+1mnzTrQGtFJKf/iSZBJjqakHUW+kEdXwpfF2dYxnIrZ/XNf7NxW+GuNtNE0dRgUrOw1 JVWJXsfSfgDVoiCWWE6+9hZuNHDfDj57cECftCl6iv9KhfQ3aoWzcZoLVHEBvyhOmH+k6yu04e 98Kyq1yMo3esmXESeRua/bOkoOhncS70T8jqksKMXpfxXyRJrVvaqaQvfJGfwMxCPLxXhWZsmF 1n5cL/RTuurtkgACfNu8bavBGsFNYu7Uy2RMQU74TRo/VXnPc2OOyiwEFO4ZAjLNaWSxALZKEV DLs= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993009; x=1647585010; bh=lq1YADGSCZFa18AOrj 3oFEX4AW2ekGKuYY1tpRjAVEA=; b=C5NlOlyadqc0vwWt0AUxNSAABmG2aq8/0a pclO+BmyZ5uO03A3LdlCKMYjReR5ZR7uCY7Xx3ATR80kwYCBQ75oXe/0+ttF7W8n 90klClDa8pu4BNeMWNaD6ql8yc5Vi/6JT15+f99tKZiSSFZIqApLb3K0Q6EaFaCh coZhTca9v3ZPlfbsWMyXXKnuMIG56Vb3tdodo8rB8aZvaqn9hl6Ns+PtQoMQ3/xo Dm1YlZZUzPwlRpDfeNRot5ud+fby3ewOUmhNFYkmEFXf6cind+qn+dqfvc7tgLEr bFxT3ulqNq/vDH6aH43gY4CNCWNfmfOjITmXlFlJiKWJtzd9jh9Q== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, LIU Zhiwei , Richard Henderson , Alistair Francis Subject: [PULL v2 11/35] target/riscv: Fix vill field write in vtype Date: Wed, 16 Feb 2022 16:28:48 +1000 Message-Id: <20220216062912.319738-12-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1644996192544100002 Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei The guest should be able to set the vill bit as part of vsetvl. Currently we may set env->vill to 1 in the vsetvl helper, but there is nowhere that we set it to 0, so once it transitions to 1 it's stuck there until the system is reset. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20220201064601.41143-1-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 020d2e841f..3bd4aac9c9 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -71,6 +71,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ul= ong s1, env->vl =3D vl; env->vtype =3D s2; env->vstart =3D 0; + env->vill =3D 0; return vl; } =20 --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1644998035019398.8046822538796; Tue, 15 Feb 2022 23:53:55 -0800 (PST) Received: from localhost ([::1]:54086 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKF8L-0003ZF-9u for importer@patchew.org; Wed, 16 Feb 2022 02:53:53 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48548) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDpT-0005qK-2c for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:19 -0500 Received: from esa5.hgst.iphmx.com ([216.71.153.144]:59531) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDpQ-0006Zz-V5 for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:18 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:30:14 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:03:03 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:30:15 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7P25npjz1SVp0 for ; Tue, 15 Feb 2022 22:30:14 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id Ufy3UlFnCUjE for ; Tue, 15 Feb 2022 22:30:14 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7Ny074Dz1Rwrw; Tue, 15 Feb 2022 22:30:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993016; x=1676529016; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=32il3/FXEqWt9Om01xQlWBhHPsrFjWspEJktojPne5o=; b=o5pBExL7ELmfvTzUCz5N/rNSr3dO64viTdZXZr35ap5pnoRy9/cwyMvy o4fbHJt0Z7ue2SQ3rDpOZIHK206xu6CBA0zPFhic1O/7WKJnYSNKrxbnj YbppXD7rmJihN0wmYTxVa7tGewqY7wuwQLb2wtnXhSZHxANCD2PrvC+ot JvMv7mueDMoJ2DssumUD4/hvKdTA1no7Sxrz123x40SPShQmPh+dOl5yl k2bmH4HqQfzSGUfG6syO5TiociyZV4PQOklAgGb19JnB5E21oPg1YPE1y Zs/AXHnc+XiXJa4lfcu8Qs2F6EvTHqWGXlq9iQOfkDz48jM/w71SL0/jc A==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="193072748" IronPort-SDR: Dq5k1rsAHLoBs9tNsGlcKAjLdyk9LptV2BfqDtvL0unDozq01dyFAp/a+TwkAmkryKlLfIXgnL otdORbn+FHzwOk7/uUrTazgWRfp5DUD7oLmIJsoJzhImOVb8uhQFYcn5PBvC4gCtr0qG/5q7Xd 1sJn+pt+jEV2PUE7LV+v5JBvOz61uYasL3peoEsm0p4eR9w6rJ1gd4hyEIsSw0+QqqciiMy9Hs SBLVp+hcQI25YMcufqDqnFepu2b39KkzOu4Aqfk0cDMQiFAzA1hvdUvUDb0LabBMSEmOGUgWlg 66Ipdo2LW5cw082NqcwoE55J IronPort-SDR: X44q1mY1RUpXY5o7u1icsZKKQpRNAMcr8P40j+mJvM3cM3LCLVTpkqJkOws06RWhOyS0AWx0YR JegQIZRXoJfBDYsKF5kTmsqGHJjos5kOdz8Gpm43lnsgsCjDq7EPI6CTUJuTXRyTU4Xczg1FKA mHGkuhWEakyaZO9hfeTJiDn5kvfR0P/feaZvjl6gU6IhSn8tm5OUnAK5Gck1N/POjTX8hY6K1Z nKDhIwbnc+ZVsgOk+yV/zPKi2kvdHLrF/iEUnSc9CwlTzSYOE3o2OLpC8onrsa6sR+VKaBsy2v ehk= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993014; x=1647585015; bh=32il3/FXEqWt9Om01x QlWBhHPsrFjWspEJktojPne5o=; b=IynmICDSAW0DbeOGcgGEa85aRwfwtKN+GV ITtMeIcOEIPYH1G5VmtwJkCK0Rt71Nz9aUCQYfkytcUUPvcZd9rehQMk5mumclYt wIGvM35dlgADZJJxmgdXHBq9OADIbWpygWqshNLzZQhyjrh0ip4wH29vVKcKY8Yx zk9w0jZK0w1qerFoHdfGrWmyoKEgsIBLXy5P4XdWXJIAiVRVo9jmY6okto3lUHzA 1hgI/wsLjktG77y32jAdiU5Sk89ptiTGraSi9ewybVnuPJXuoVkPH/kVz78V1p0J XDCG2RDUjJNlyEMxtodpeVgJkjTD4TQ9YkU6kZxMSDZIFXz7EXEg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anup Patel , Anup Patel , Alistair Francis , Bin Meng , Frank Chang Subject: [PULL v2 12/35] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Date: Wed, 16 Feb 2022 16:28:49 +1000 Message-Id: <20220216062912.319738-13-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1644998036500100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel We should be returning illegal instruction trap when RV64 HS-mode tries to access RV32 HS-mode CSR. Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions") Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Frank Chang Message-id: 20220204174700.534953-2-anup@brainfault.org Signed-off-by: Alistair Francis --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e5f9d4ef93..41a533a310 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -186,7 +186,7 @@ static RISCVException hmode(CPURISCVState *env, int csr= no) static RISCVException hmode32(CPURISCVState *env, int csrno) { if (riscv_cpu_mxl(env) !=3D MXL_RV32) { - if (riscv_cpu_virt_enabled(env)) { + if (!riscv_cpu_virt_enabled(env)) { return RISCV_EXCP_ILLEGAL_INST; } else { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1644996943235749.217357588424; Tue, 15 Feb 2022 23:35:43 -0800 (PST) Received: from localhost ([::1]:36128 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKEqj-0007NE-EQ for importer@patchew.org; Wed, 16 Feb 2022 02:35:41 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48572) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDpX-0005yN-4u for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:23 -0500 Received: from esa5.hgst.iphmx.com ([216.71.153.144]:59531) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDpU-0006Zz-OX for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:22 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:30:19 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:03:08 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:30:20 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7P74tFnz1SVp1 for ; Tue, 15 Feb 2022 22:30:19 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id 9P65ZJ5K4Xvy for ; Tue, 15 Feb 2022 22:30:19 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7P31ZGHz1Rwrw; Tue, 15 Feb 2022 22:30:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993020; x=1676529020; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FzZUiVDdDWtQHhwfAhtLSgxgCth6Afkp8YZ/LjldLss=; b=oeYW7IQq7WSswMg2fabbc9WgMAwVcIFB3x8tyLIVNi6uAoxDbUubIUXI nsTh1FSNagsV7YEI7QyIN1qIwpkWz06xAKfK9EbV9xwimCo01V3O5lT8O /Wu8/O4YuyEVKAUN/F9DfV2aNUXHG8c9+V9LrdK9Kaoo57bhbLB489mEK e+T5WWW7mzZ0pjWDcPzTWceAI41zEKWTcdcGC2zqmrr16+ORpCwfWjB16 Va0aM3EY7PVE+QRfM1JiPwMacCSLq2ZwkApTCLJsf55p3aZLxOay7Ob83 V83LGaWzuQyUEip+vrqpAgaAdnNZa3N3O/FrAXUFzPE/N53fvgIhm8awE Q==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="193072756" IronPort-SDR: NVKY7P9xv/ZFB3Zt0xV+94mP9pKJkI5z7PDBQUoo1BM8PMl0zY4Ea6f4tM1tZJO4BaJJIAajHc C0gRNLJKiXpd1UplpfsQ/J+892LA30gt2Zuug2nS2EgDSERKxB7cxoMHNM/MStp0nP9TQbWjL4 CRFPpaLjSB3H6TBmwqTQ0WJHjWHv7LPBvb/ebQiP70aYOJ3pdf3QDuVtkDtn0GtEB3ShJHf4aF +UM2fSUf7wtk83h0ssoQoHgOAZ9OufvmNmN81ruPMssM13SrFaxhVSr1SOX05ZfXY+QpWlu6Ci EdP6YtISYtwq8KUs0ETBCFfP IronPort-SDR: 4DcbM4BqoDAAJcm5GmkW9cUbJMqMQGYgLgw5d6YrBQVyVfvssnELcyOR2zt5WrFx6vxo+CpD4u AI75wCfmqH34scAZWkR3yQHiTA9vtCdgxLFUKyYOY/VcAi+UWZt3YNcymObY6fcYYqPZ921Gn8 +c0jLCLfG3wMpXJggJ2S1ctAfQqb9pypYWjbk6IkbzEyXl/sjao++oacXPi+Ny4TRNR6CUdbVY M76A6WJd1zFixfjm6xGTIuS+D3quB3Q7cH4AgRcopNK7rbGfFxp/hvaq0TUrSEHlFWdXlVGGTv o84= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993019; x=1647585020; bh=FzZUiVDdDWtQHhwfAh tLSgxgCth6Afkp8YZ/LjldLss=; b=ICx+bESq5Z9L5L7z0bnN7fyaCcmwjs4dW4 cuDEXaWVhWO0kLykLYEn1IM6Fgbe8MhFs8mE4AW0j5Z/uig60bqpsPtjwnnRQaZP XE1sDCO0QLA6ZKgnxw5pwXC3AiArXA80m1MT8U3Y7ipyJE3pqPOUUcQPZRXzknDM Q1yDZQoLPj2evxSoGGYXI4ozDpYqF1+24QmIRJhBZxyVxCFlwnCbibm8qpa5m/Qe Y32sGtykNjCYi8hPooL8sAjQyrekg6f1Hky0pvxFQQaeuguf2fXkCtuk4zystqQD NMbHC0pvYk3rS7wjl8kNYeKDs4hWlqHpY7BZwFt+2EVit0AJBZAQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anup Patel , Anup Patel , Alistair Francis , Frank Chang Subject: [PULL v2 13/35] target/riscv: Implement SGEIP bit in hip and hie CSRs Date: Wed, 16 Feb 2022 16:28:50 +1000 Message-Id: <20220216062912.319738-14-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1644996945048100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel A hypervisor can optionally take guest external interrupts using SGEIP bit of hip and hie CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Message-id: 20220204174700.534953-3-anup@brainfault.org Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu.c | 3 ++- target/riscv/csr.c | 18 +++++++++++------- 3 files changed, 16 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7c87433645..e1256a9982 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -540,6 +540,8 @@ typedef enum RISCVException { #define IRQ_S_EXT 9 #define IRQ_VS_EXT 10 #define IRQ_M_EXT 11 +#define IRQ_S_GEXT 12 +#define IRQ_LOCAL_MAX 16 =20 /* mip masks */ #define MIP_USIP (1 << IRQ_U_SOFT) @@ -554,6 +556,7 @@ typedef enum RISCVException { #define MIP_SEIP (1 << IRQ_S_EXT) #define MIP_VSEIP (1 << IRQ_VS_EXT) #define MIP_MEIP (1 << IRQ_M_EXT) +#define MIP_SGEIP (1 << IRQ_S_GEXT) =20 /* sip masks */ #define SIP_SSIP MIP_SSIP diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1238aabe3f..e1224d26dc 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -434,6 +434,7 @@ static void riscv_cpu_reset(DeviceState *dev) } } env->mcause =3D 0; + env->miclaim =3D MIP_SGEIP; env->pc =3D env->resetvec; env->two_stage_lookup =3D false; /* mmte is supposed to have pm.current hardwired to 1 */ @@ -695,7 +696,7 @@ static void riscv_cpu_init(Object *obj) cpu_set_cpustate_pointers(cpu); =20 #ifndef CONFIG_USER_ONLY - qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12); + qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX); #endif /* CONFIG_USER_ONLY */ } =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 41a533a310..c635ffb089 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -461,12 +461,13 @@ static RISCVException read_timeh(CPURISCVState *env, = int csrno, #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) +#define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS) =20 static const target_ulong delegable_ints =3D S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS; static const target_ulong vs_delegable_ints =3D VS_MODE_INTERRUPTS; static const target_ulong all_ints =3D M_MODE_INTERRUPTS | S_MODE_INTERRUP= TS | - VS_MODE_INTERRUPTS; + HS_MODE_INTERRUPTS; #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ @@ -748,7 +749,7 @@ static RISCVException write_mideleg(CPURISCVState *env,= int csrno, { env->mideleg =3D (env->mideleg & ~delegable_ints) | (val & delegable_i= nts); if (riscv_has_ext(env, RVH)) { - env->mideleg |=3D VS_MODE_INTERRUPTS; + env->mideleg |=3D HS_MODE_INTERRUPTS; } return RISCV_EXCP_NONE; } @@ -764,6 +765,9 @@ static RISCVException write_mie(CPURISCVState *env, int= csrno, target_ulong val) { env->mie =3D (env->mie & ~all_ints) | (val & all_ints); + if (!riscv_has_ext(env, RVH)) { + env->mie &=3D ~MIP_SGEIP; + } return RISCV_EXCP_NONE; } =20 @@ -1110,7 +1114,7 @@ static RISCVException rmw_sip(CPURISCVState *env, int= csrno, } =20 if (ret_value) { - *ret_value &=3D env->mideleg; + *ret_value &=3D env->mideleg & S_MODE_INTERRUPTS; } return ret; } @@ -1228,7 +1232,7 @@ static RISCVException rmw_hvip(CPURISCVState *env, in= t csrno, write_mask & hvip_writable_mask); =20 if (ret_value) { - *ret_value &=3D hvip_writable_mask; + *ret_value &=3D VS_MODE_INTERRUPTS; } return ret; } @@ -1241,7 +1245,7 @@ static RISCVException rmw_hip(CPURISCVState *env, int= csrno, write_mask & hip_writable_mask); =20 if (ret_value) { - *ret_value &=3D hip_writable_mask; + *ret_value &=3D HS_MODE_INTERRUPTS; } return ret; } @@ -1249,14 +1253,14 @@ static RISCVException rmw_hip(CPURISCVState *env, i= nt csrno, static RISCVException read_hie(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->mie & VS_MODE_INTERRUPTS; + *val =3D env->mie & HS_MODE_INTERRUPTS; return RISCV_EXCP_NONE; } =20 static RISCVException write_hie(CPURISCVState *env, int csrno, target_ulong val) { - target_ulong newval =3D (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_M= ODE_INTERRUPTS); + target_ulong newval =3D (env->mie & ~HS_MODE_INTERRUPTS) | (val & HS_M= ODE_INTERRUPTS); return write_mie(env, CSR_MIE, newval); } =20 --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1644998419736830.3923980169957; Wed, 16 Feb 2022 00:00:19 -0800 (PST) Received: from localhost ([::1]:34722 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKFEY-0001Eb-0c for importer@patchew.org; Wed, 16 Feb 2022 03:00:18 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48604) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDpd-0006FP-VR for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:30 -0500 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:14530) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDpa-0006fr-ND for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:29 -0500 Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:30:25 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:02:05 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:30:25 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7PD5xrzz1SVnx for ; Tue, 15 Feb 2022 22:30:24 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id TRy7ncYf23Bz for ; Tue, 15 Feb 2022 22:30:23 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7P76nQ3z1Rwrw; Tue, 15 Feb 2022 22:30:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993027; x=1676529027; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1NCQMayyILJx0qmjiORUeu5+IWQLva2eYMHLewQNNkk=; b=HJ5JMJo+BrnqggjicMUwjWojtSRelvAW6cs+6OlR8Nm4b+uHa7RZR4Ye CFagl8Wv106JOoSOHTYX+4LyanLRFXdbM2d/PqBq2xGumIEJBcYb7oHzx EQgaILALVOJ6mlkHws5Od0/xjQ22ir0YHYUMiEEZc6W2Zfv+8V+61JS0V KvEmkPD1yHGMF7LxyYaZJ/4ge8Q09TwRZGZSxcYPoGTF9mOaOq1b/tiIb 6mYUbAZDfzhgPllrHQWJqzGtjMX56uqV80gPYYBalnTqe9Hg5sRtJA/1O Pz1SjgDykQROtE2T5kF7s4iSGzYKIqwkAs0insrddvDE4K4KzrZgs11uG A==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="194046751" IronPort-SDR: jt2gTPBiaigDnfRG4jKdoPYpOw+5hvO9dBGHRIriDldDrsKPxwNrC6RxQ1rS9ny+ne48hiE6WP 45Yo0S6630pEDf2gql09pFbgyPn10I2O3ARs1MIXLsdkua9rmncc2t4n5YCkTwJfMYw+0Z6/97 y4lDus3pkPJXu3ygvrJyS0pG43LRoOLVE0u9RYcZcJwmoXzosCkSnxl5L+En0gLNg1pJIgR7uF 12to/BSqC+uJjmbAPEU0JDu0PoU+GfKZQAsNwDdtmMeI6qhnhVEfahEuNkhjHmpE0Zy2J182rG bnHfa+4NEi/Uz/loyXgVx6Dh IronPort-SDR: qfWjbffKUMyMb0b754JXk8AweBSCMYNPn93+4Srq8/wXIDaNcMV3dxw0rw5CaTQ0PrY1eVSuGO jufbTbRD+zdwZe7a7VwSy6c+qyqtVMy7ILJCFkgvvM3hDo+/mz73HO54hWcwz2LoTLRummzurg 0vygZW/IOGsHQf9P9JQgDkJK1Ci0hBTT+qrABUObqTnCEl20Pdi0EddU6k5r3b6s4f+t+tsq5C zd5D3+IHDjpj+XktGZMImWxBsbsImkdQZ0uRhQAuBFjcofJwYyCm4dbhjzKKq0meYWpMeJNuSo vZg= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993023; x=1647585024; bh=1NCQMayyILJx0qmjiO RUeu5+IWQLva2eYMHLewQNNkk=; b=nMirjD9UzHFHmpaF6UOFMOLXZxZEAtrbs9 MoIe8xIx3m1fzhZec3YXrVrRE9pSNJmxhpdnoqgWB4AzPDe0hw5JHKxrc0LboNDf oEkKCnxstAkI5L3jgyK4GP4+yQFlnAlDmHD+Y5My3iojIbibfcvuBC9jaPKvWsQD dx/kMeQ0pZeMalWNRQqSke/rApGjVt8uNJP6qF7xjTJ+GbBfTPO5WrKcC2Z5q0FN JVagcXq8c700oxtS8ZeSnYtchPwtuVd9VJGfRSOZPj4fI9hepFP4RTu6pHltaeiF bbcr2VpX3P3XOwb+n7FHIbSbdj15z611FHMtKU95DUnZvcjajxvA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anup Patel , Anup Patel , Alistair Francis , Frank Chang Subject: [PULL v2 14/35] target/riscv: Implement hgeie and hgeip CSRs Date: Wed, 16 Feb 2022 16:28:51 +1000 Message-Id: <20220216062912.319738-15-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1644998421471100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel The hgeie and hgeip CSRs are required for emulating an external interrupt controller capable of injecting virtual external interrupt to Guest/VM running at VS-level. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Message-id: 20220204174700.534953-4-anup@brainfault.org Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 5 +++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu.c | 67 +++++++++++++++++++++++++++------------ target/riscv/cpu_helper.c | 37 +++++++++++++++++++-- target/riscv/csr.c | 43 +++++++++++++++++-------- target/riscv/machine.c | 6 ++-- 6 files changed, 121 insertions(+), 38 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index aacc997d56..f030cb58b2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -161,6 +161,7 @@ struct CPURISCVState { target_ulong priv; /* This contains QEMU specific information about the virt state. */ target_ulong virt; + target_ulong geilen; target_ulong resetvec; =20 target_ulong mhartid; @@ -198,6 +199,8 @@ struct CPURISCVState { target_ulong htval; target_ulong htinst; target_ulong hgatp; + target_ulong hgeie; + target_ulong hgeip; uint64_t htimedelta; =20 /* Upper 64-bits of 128-bit CSRs */ @@ -391,6 +394,8 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f,= CPUState *cs, int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); bool riscv_cpu_fp_enabled(CPURISCVState *env); +target_ulong riscv_cpu_get_geilen(CPURISCVState *env); +void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index e1256a9982..a541705760 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -542,6 +542,7 @@ typedef enum RISCVException { #define IRQ_M_EXT 11 #define IRQ_S_GEXT 12 #define IRQ_LOCAL_MAX 16 +#define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) =20 /* mip masks */ #define MIP_USIP (1 << IRQ_U_SOFT) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e1224d26dc..f1c268415a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -663,27 +663,53 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) static void riscv_cpu_set_irq(void *opaque, int irq, int level) { RISCVCPU *cpu =3D RISCV_CPU(opaque); + CPURISCVState *env =3D &cpu->env; =20 - switch (irq) { - case IRQ_U_SOFT: - case IRQ_S_SOFT: - case IRQ_VS_SOFT: - case IRQ_M_SOFT: - case IRQ_U_TIMER: - case IRQ_S_TIMER: - case IRQ_VS_TIMER: - case IRQ_M_TIMER: - case IRQ_U_EXT: - case IRQ_S_EXT: - case IRQ_VS_EXT: - case IRQ_M_EXT: - if (kvm_enabled()) { - kvm_riscv_set_irq(cpu, irq, level); - } else { - riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); + if (irq < IRQ_LOCAL_MAX) { + switch (irq) { + case IRQ_U_SOFT: + case IRQ_S_SOFT: + case IRQ_VS_SOFT: + case IRQ_M_SOFT: + case IRQ_U_TIMER: + case IRQ_S_TIMER: + case IRQ_VS_TIMER: + case IRQ_M_TIMER: + case IRQ_U_EXT: + case IRQ_S_EXT: + case IRQ_VS_EXT: + case IRQ_M_EXT: + if (kvm_enabled()) { + kvm_riscv_set_irq(cpu, irq, level); + } else { + riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); + } + break; + default: + g_assert_not_reached(); } - break; - default: + } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { + /* Require H-extension for handling guest local interrupts */ + if (!riscv_has_ext(env, RVH)) { + g_assert_not_reached(); + } + + /* Compute bit position in HGEIP CSR */ + irq =3D irq - IRQ_LOCAL_MAX + 1; + if (env->geilen < irq) { + g_assert_not_reached(); + } + + /* Update HGEIP CSR */ + env->hgeip &=3D ~((target_ulong)1 << irq); + if (level) { + env->hgeip |=3D (target_ulong)1 << irq; + } + + /* Update mip.SGEIP bit */ + riscv_cpu_update_mip(cpu, MIP_SGEIP, + BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); + } else { g_assert_not_reached(); } } @@ -696,7 +722,8 @@ static void riscv_cpu_init(Object *obj) cpu_set_cpustate_pointers(cpu); =20 #ifndef CONFIG_USER_ONLY - qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX); + qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, + IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); #endif /* CONFIG_USER_ONLY */ } =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 327a2c4f1d..698389ba1b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -159,7 +159,11 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *= env) target_ulong mstatus_mie =3D get_field(env->mstatus, MSTATUS_MIE); target_ulong mstatus_sie =3D get_field(env->mstatus, MSTATUS_SIE); =20 - target_ulong pending =3D env->mip & env->mie; + target_ulong vsgemask =3D + (target_ulong)1 << get_field(env->hstatus, HSTATUS_VGEIN); + target_ulong vsgein =3D (env->hgeip & vsgemask) ? MIP_VSEIP : 0; + + target_ulong pending =3D (env->mip | vsgein) & env->mie; =20 target_ulong mie =3D env->priv < PRV_M || (env->priv =3D=3D PRV_M && mstatus_mie); @@ -279,6 +283,28 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) } } =20 +target_ulong riscv_cpu_get_geilen(CPURISCVState *env) +{ + if (!riscv_has_ext(env, RVH)) { + return 0; + } + + return env->geilen; +} + +void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) +{ + if (!riscv_has_ext(env, RVH)) { + return; + } + + if (geilen > (TARGET_LONG_BITS - 1)) { + return; + } + + env->geilen =3D geilen; +} + bool riscv_cpu_virt_enabled(CPURISCVState *env) { if (!riscv_has_ext(env, RVH)) { @@ -322,9 +348,14 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t = mask, uint32_t value) { CPURISCVState *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); - uint32_t old =3D env->mip; + uint32_t gein, vsgein =3D 0, old =3D env->mip; bool locked =3D false; =20 + if (riscv_cpu_virt_enabled(env)) { + gein =3D get_field(env->hstatus, HSTATUS_VGEIN); + vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; + } + if (!qemu_mutex_iothread_locked()) { locked =3D true; qemu_mutex_lock_iothread(); @@ -332,7 +363,7 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t m= ask, uint32_t value) =20 env->mip =3D (env->mip & ~mask) | (value & mask); =20 - if (env->mip) { + if (env->mip | vsgein) { cpu_interrupt(cs, CPU_INTERRUPT_HARD); } else { cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c635ffb089..b23195b479 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -883,7 +883,7 @@ static RISCVException rmw_mip(CPURISCVState *env, int c= srno, RISCVCPU *cpu =3D env_archcpu(env); /* Allow software control of delegable interrupts not claimed by hardw= are */ target_ulong mask =3D write_mask & delegable_ints & ~env->miclaim; - uint32_t old_mip; + uint32_t gin, old_mip; =20 if (mask) { old_mip =3D riscv_cpu_update_mip(cpu, mask, (new_value & mask)); @@ -891,6 +891,11 @@ static RISCVException rmw_mip(CPURISCVState *env, int = csrno, old_mip =3D env->mip; } =20 + if (csrno !=3D CSR_HVIP) { + gin =3D get_field(env->hstatus, HSTATUS_VGEIN); + old_mip |=3D (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP := 0; + } + if (ret_value) { *ret_value =3D old_mip; } @@ -1089,7 +1094,7 @@ static RISCVException rmw_vsip(CPURISCVState *env, in= t csrno, target_ulong new_value, target_ulong write_= mask) { /* Shift the S bits to their VS bit location in mip */ - int ret =3D rmw_mip(env, 0, ret_value, new_value << 1, + int ret =3D rmw_mip(env, csrno, ret_value, new_value << 1, (write_mask << 1) & vsip_writable_mask & env->hidele= g); =20 if (ret_value) { @@ -1109,7 +1114,7 @@ static RISCVException rmw_sip(CPURISCVState *env, int= csrno, if (riscv_cpu_virt_enabled(env)) { ret =3D rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); } else { - ret =3D rmw_mip(env, CSR_MSTATUS, ret_value, new_value, + ret =3D rmw_mip(env, csrno, ret_value, new_value, write_mask & env->mideleg & sip_writable_mask); } =20 @@ -1228,7 +1233,7 @@ static RISCVException rmw_hvip(CPURISCVState *env, in= t csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_= mask) { - int ret =3D rmw_mip(env, 0, ret_value, new_value, + int ret =3D rmw_mip(env, csrno, ret_value, new_value, write_mask & hvip_writable_mask); =20 if (ret_value) { @@ -1241,7 +1246,7 @@ static RISCVException rmw_hip(CPURISCVState *env, int= csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_m= ask) { - int ret =3D rmw_mip(env, 0, ret_value, new_value, + int ret =3D rmw_mip(env, csrno, ret_value, new_value, write_mask & hip_writable_mask); =20 if (ret_value) { @@ -1278,15 +1283,27 @@ static RISCVException write_hcounteren(CPURISCVStat= e *env, int csrno, return RISCV_EXCP_NONE; } =20 -static RISCVException write_hgeie(CPURISCVState *env, int csrno, - target_ulong val) +static RISCVException read_hgeie(CPURISCVState *env, int csrno, + target_ulong *val) { if (val) { - qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); + *val =3D env->hgeie; } return RISCV_EXCP_NONE; } =20 +static RISCVException write_hgeie(CPURISCVState *env, int csrno, + target_ulong val) +{ + /* Only GEILEN:1 bits implemented and BIT0 is never implemented */ + val &=3D ((((target_ulong)1) << env->geilen) - 1) << 1; + env->hgeie =3D val; + /* Update mip.SGEIP bit */ + riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP, + BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); + return RISCV_EXCP_NONE; +} + static RISCVException read_htval(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1314,11 +1331,11 @@ static RISCVException write_htinst(CPURISCVState *e= nv, int csrno, return RISCV_EXCP_NONE; } =20 -static RISCVException write_hgeip(CPURISCVState *env, int csrno, - target_ulong val) +static RISCVException read_hgeip(CPURISCVState *env, int csrno, + target_ulong *val) { if (val) { - qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); + *val =3D env->hgeip; } return RISCV_EXCP_NONE; } @@ -2148,10 +2165,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_HIP] =3D { "hip", hmode, NULL, NULL, rmw_= hip }, [CSR_HIE] =3D { "hie", hmode, read_hie, writ= e_hie }, [CSR_HCOUNTEREN] =3D { "hcounteren", hmode, read_hcounteren, writ= e_hcounteren }, - [CSR_HGEIE] =3D { "hgeie", hmode, read_zero, writ= e_hgeie }, + [CSR_HGEIE] =3D { "hgeie", hmode, read_hgeie, writ= e_hgeie }, [CSR_HTVAL] =3D { "htval", hmode, read_htval, writ= e_htval }, [CSR_HTINST] =3D { "htinst", hmode, read_htinst, writ= e_htinst }, - [CSR_HGEIP] =3D { "hgeip", hmode, read_zero, writ= e_hgeip }, + [CSR_HGEIP] =3D { "hgeip", hmode, read_hgeip, NULL= }, [CSR_HGATP] =3D { "hgatp", hmode, read_hgatp, writ= e_hgatp }, [CSR_HTIMEDELTA] =3D { "htimedelta", hmode, read_htimedelta, writ= e_htimedelta }, [CSR_HTIMEDELTAH] =3D { "htimedeltah", hmode32, read_htimedeltah, writ= e_htimedeltah }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 740e11fcff..7d72c2d8a6 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -78,8 +78,8 @@ static bool hyper_needed(void *opaque) =20 static const VMStateDescription vmstate_hyper =3D { .name =3D "cpu/hyper", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .needed =3D hyper_needed, .fields =3D (VMStateField[]) { VMSTATE_UINTTL(env.hstatus, RISCVCPU), @@ -89,6 +89,8 @@ static const VMStateDescription vmstate_hyper =3D { VMSTATE_UINTTL(env.htval, RISCVCPU), VMSTATE_UINTTL(env.htinst, RISCVCPU), VMSTATE_UINTTL(env.hgatp, RISCVCPU), + VMSTATE_UINTTL(env.hgeie, RISCVCPU), + VMSTATE_UINTTL(env.hgeip, RISCVCPU), VMSTATE_UINT64(env.htimedelta, RISCVCPU), =20 VMSTATE_UINT64(env.vsstatus, RISCVCPU), --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645000338132241.44901818213873; Wed, 16 Feb 2022 00:32:18 -0800 (PST) Received: from localhost ([::1]:43668 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKFjV-0002mg-0S for importer@patchew.org; Wed, 16 Feb 2022 03:32:17 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48628) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDpg-0006Jx-CH for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:32 -0500 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:14530) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDpe-0006fr-7F for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:32 -0500 Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:30:29 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:02:09 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:30:29 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7PJ6NRkz1SVp0 for ; Tue, 15 Feb 2022 22:30:28 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id lC5Y64sZ-VHd for ; Tue, 15 Feb 2022 22:30:28 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7PD4tpcz1SHwl; Tue, 15 Feb 2022 22:30:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993030; x=1676529030; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iLXXpXI9zgLaXQJ4bWp9YAGUXCRbcHAuyAhY5lhInqQ=; b=P5Rp9UcyM4dS0QPHM4ZI9NWt9XWLNyFqiBIiX6GcqzfivEn3oEG/RsyV IKJZLixsUPmptogSaxLvZ4LTQn57uRPd5cyBabFrt6vWG91JviMP/UN1v iIB64uitd6kvPPsqEuy1jPYcWnHYT+aqpqHlMYa3xtrMOY6X3A82hfUhr J7Pf3JpJT0LlGObx0yqEr57bgzFsNLXtrHaeN/iS13XddYGdtgeeP+ZPO mgHofhISuTBPgmnHh9qB82jCsgLJ5lZTQurgp9kMfkmHeGB1dWrdrQmlm azz88Vtly1qJ+0Ez+kwuybZyZJJRuzBhUVh/l5g6i+Xz7ty37RVedS+j0 g==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="194046754" IronPort-SDR: LnKCey/hAVNaQ8LmKCcaS2+7dFNDcmhLqkvTgf/nrh/zdtDYnGLKH/KUO35yC5/TLM7idanWsA 7fUHUUmLGZpmxkLBL/8g2Q7ryDumCMxjTKbOw15lcg2ZoQHQ25Uh4hmEbNHVCFYFCOU/We90Mc OOU3MvBRE4vbtR3crlTcTQzrAo8KF//U65OllrKrQubk6DYExnfssMlXOPSfcMpsWaLn1JTi59 grJ0EE1x1Y6lBjgpEWenr1J7PJDt/HdAS0UEL2//ZXM9hoylIIBMDW/3cHW13wFHtXBhKw88M+ /CCP0wvmD1fhYqZ1Shw8Qd/W IronPort-SDR: DJH9b4uyh0ZhIscCWHPFcTyHqhQ/cUxBaWwy8ambo5CNtAVshjHYn+Nl7+fQjPikCmXWj4iPP2 MBF+mNKt/rIGlLE63JmPX2CDaq16WhhoGpb5SQ6D3cep2G9iF58vbs8Whaxnp9Chv8GOsoSWkc 3kpxajNs4mb4dWtJokKJ9SX2ufYkDccWJt7zBUTSStQMmi7U+tPlikoZQEF3HAOQvpzbv5Ra5e DIE8gXqsYJLHkQVdt40/chXPmz/eb+xhrE8GeLMsorIecF97LT0fcVsVcgH5+odTte6eZf1wXR fH4= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993028; x=1647585029; bh=iLXXpXI9zgLaXQJ4bW p9YAGUXCRbcHAuyAhY5lhInqQ=; b=ZFqBetp8Xp1NcDnY93r8jGBAlCO9NfIGmH yXfG/ww1jRNg7IRORXFw6k2BQfNNlNKZnxveKSyWY2HzqiBb/kQYmxXScd9LKOBp KFu7liVi8JwlcAjeUJLxYQdzBwnGjmOQwmNz+NRkbOROJqq8mzZsUmGJi8aBBD85 A/GPpM+UmNyXEClqkv/xh8Lhd33hEpso/nN5e9ZbG4GEINf6/kbj0jq70eGDA3Cu AwrjoqNiHyEODuwIJXlFy0L2TcJCPx9y5VXaBhIzgB/MhgiJX+M0BC7lQYBkg/F2 eof+tna9P+1NLvskWxtg4jDM3CH8lK5MEbpXoiFkEiMzZjClWzkg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anup Patel , Anup Patel , Alistair Francis , Frank Chang Subject: [PULL v2 15/35] target/riscv: Improve delivery of guest external interrupts Date: Wed, 16 Feb 2022 16:28:52 +1000 Message-Id: <20220216062912.319738-16-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1645000340007100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel The guest external interrupts from an interrupt controller are delivered only when the Guest/VM is running (i.e. V=3D1). This means any guest external interrupt which is triggered while the Guest/VM is not running (i.e. V=3D0) will be missed on QEMU resulting in Guest with sluggish response to serial console input and other I/O events. To solve this, we check and inject interrupt after setting V=3D1. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Message-id: 20220204174700.534953-5-anup@brainfault.org Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 698389ba1b..e45ca08ea9 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -326,6 +326,19 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bo= ol enable) } =20 env->virt =3D set_field(env->virt, VIRT_ONOFF, enable); + + if (enable) { + /* + * The guest external interrupts from an interrupt controller are + * delivered only when the Guest/VM is running (i.e. V=3D1). This = means + * any guest external interrupt which is triggered while the Guest= /VM + * is not running (i.e. V=3D0) will be missed on QEMU resulting in= guest + * with sluggish response to serial console input and other I/O ev= ents. + * + * To solve this, we check and inject interrupt after setting V=3D= 1. + */ + riscv_cpu_update_mip(env_archcpu(env), 0, 0); + } } =20 bool riscv_cpu_two_stage_lookup(int mmu_idx) --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645000532965227.33139254067805; Wed, 16 Feb 2022 00:35:32 -0800 (PST) Received: from localhost ([::1]:50894 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKFmd-0007c1-Jv for importer@patchew.org; Wed, 16 Feb 2022 03:35:31 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48664) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDpm-0006Vy-Ay for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:38 -0500 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:14545) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDpj-0006h9-Dd for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:38 -0500 Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:30:35 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:02:14 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:30:34 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7PP6jwZz1SVp2 for ; Tue, 15 Feb 2022 22:30:33 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id UwdMX9y_fvLB for ; Tue, 15 Feb 2022 22:30:33 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7PK24tzz1Rwrw; Tue, 15 Feb 2022 22:30:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993036; x=1676529036; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DVUTjB2lAiVl3JnKm7Gl1e92WjdQT2bI1iA7+W7EZ4Y=; b=MN8RoYl/3DbhCtaJcFI7q4xauQ6hlZLjPTjS1sUkx9a4gTDAubdY6re2 ZjIngkwquOQ+CwKlIfIYtYf2DFmcWfICIp1ylT+ILFGy3CLeg0DeiIwy2 jrze8J7MpgYPEsZZC3gfrXlVQuVoeaI/ghZs3egZsvKeMiUiwG4y/0FJk mneJAtIaTvojH8HK512KlJ95z0mFruhKKfugQXmhtpPCjlRA5w9920Osy SgCPxuo9JqcVgB9KUBqZ5LikfgQM0j97MdwfUG06Ef8DzixRQtJFgeyuS RLtNHTC/gvS8D3S5oqfjgLCZeVbzY2W3PCzAzeCLhrgpAdO0joRXj5mw9 A==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="194046761" IronPort-SDR: h07u/iqRUt/Yz+m5pWFp6/w+MP8B2isObmjfIBP1zGBaJ9s3/SlFZXxsOaRUkTqARSyeSlp3I/ TxBT9tmgTBFygKtFEwvA9lhOd8CEpCiIM4froTFJgTvgsSbEy4CxxJtDWBNesuOdG4sRsCdv4B fz7OhId+SJSqIkH8yCId+CzfCmpj8GRh3VPwtjicZVRvuE0BeCvNYV0mhnfiVXEtkT1TO5CoMx zf9SMXoXgrQOk9FYo0Q36v1cz33t9fAy5lgFdTOu+EKJk734erl8qzo8VqzXpiWDxufPyoEVX3 L0p4GoSocTXdNznZIis5/PLv IronPort-SDR: FNVc2zM1BUkIS8WktONsJygWyZRCxnlO6KdaS1NX+Gfl9H+LWb9kYDG+CUQR4o94H+f3ZXhBFp cZYoY9eNIDCUsBvFs6bV6K3LjeK+00NK+g4zaKTN0aPuRHVTYbo/tfVSgL+Nr/iJ2wpvKdtPmj 04TSuXvShOCFYjQcdTMja3TGklTPKlzfvKKk4NtClZYMY0E1EILQluuOnj6awbisbL4oDx1Xij S0bN9soWB1vhQDFVmWHWixYHgw3OWJHGz2CWi9klbv/H2XdNDpBXiRhUXIvc9je22SQOm/EZyt yr0= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993033; x=1647585034; bh=DVUTjB2lAiVl3JnKm7 Gl1e92WjdQT2bI1iA7+W7EZ4Y=; b=Ihin+WVi9NWNsWxhHi7w4F5KCEko337ZgJ ACQZlrp4jSuN0o5jKGXCsliay4sIgBSei0MX6peGFR0FYK5kNHSBHazz70QAol6R OnKC3iTzsVHvoZRwE07Pn3U7KDDEuYspKVcbY+FIsbaTbgXGaHfNwb7V+KqfAk1v xfYRQRau12I+MhACA47ONAudvFo4uuwH0fOvIg9MH9wrIC9eBBldE0t6Yqx5Gq5P W3cocr2Uu0APhy7G+yeymdESbm36D1Tfer16zGg6G5ODoRf7/iYLryzWDZIzuQPj dM5f0uJZma7+I/e0goeFxMcH9f4aDaYsddoNJyjuIfX+aVG9ZBWw== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anup Patel , Anup Patel , Bin Meng , Alistair Francis , Frank Chang Subject: [PULL v2 16/35] target/riscv: Allow setting CPU feature from machine/device emulation Date: Wed, 16 Feb 2022 16:28:53 +1000 Message-Id: <20220216062912.319738-17-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1645000533682100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel The machine or device emulation should be able to force set certain CPU features because: 1) We can have certain CPU features which are in-general optional but implemented by RISC-V CPUs on the machine. 2) We can have devices which require a certain CPU feature. For example, AIA IMSIC devices expect AIA CSRs implemented by RISC-V CPUs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Message-id: 20220204174700.534953-6-anup@brainfault.org Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 5 +++++ target/riscv/cpu.c | 11 +++-------- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f030cb58b2..283a3cda4b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -379,6 +379,11 @@ static inline bool riscv_feature(CPURISCVState *env, i= nt feature) return env->features & (1ULL << feature); } =20 +static inline void riscv_set_feature(CPURISCVState *env, int feature) +{ + env->features |=3D (1ULL << feature); +} + #include "cpu_user.h" =20 extern const char * const riscv_int_regnames[]; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f1c268415a..ff766acc21 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -135,11 +135,6 @@ static void set_vext_version(CPURISCVState *env, int v= ext_ver) env->vext_ver =3D vext_ver; } =20 -static void set_feature(CPURISCVState *env, int feature) -{ - env->features |=3D (1ULL << feature); -} - static void set_resetvec(CPURISCVState *env, target_ulong resetvec) { #ifndef CONFIG_USER_ONLY @@ -508,18 +503,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) } =20 if (cpu->cfg.mmu) { - set_feature(env, RISCV_FEATURE_MMU); + riscv_set_feature(env, RISCV_FEATURE_MMU); } =20 if (cpu->cfg.pmp) { - set_feature(env, RISCV_FEATURE_PMP); + riscv_set_feature(env, RISCV_FEATURE_PMP); =20 /* * Enhanced PMP should only be available * on harts with PMP support */ if (cpu->cfg.epmp) { - set_feature(env, RISCV_FEATURE_EPMP); + riscv_set_feature(env, RISCV_FEATURE_EPMP); } } =20 --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1644999385747747.5788212490578; Wed, 16 Feb 2022 00:16:25 -0800 (PST) Received: from localhost ([::1]:50632 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKFU9-0004Wu-OF for importer@patchew.org; Wed, 16 Feb 2022 03:16:25 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48710) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDpr-0006gT-D1 for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:43 -0500 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:31617) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDpp-0006hk-M5 for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:43 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:30:40 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:03:28 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:30:40 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7PW4R5fz1SVp3 for ; Tue, 15 Feb 2022 22:30:39 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id YHkWqmnEiL5m for ; Tue, 15 Feb 2022 22:30:39 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7PQ74t4z1Rwrw; Tue, 15 Feb 2022 22:30:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993041; x=1676529041; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pvnxMTCRdBYWESBTahjlcU5dha2IzsUpRGE46NIzUNo=; b=CIyswWfu8I1qmVni2M3JjVcw0vFG4H4sjsw9OnnYl3qAkmucB7wr65ke X8Id0cKII5vSZBp0jaP3A7VTQtN+cLVMq0LW2kb+ddxrfSK00bQ7td+eI whZcwbe26Xqqlv7W5hrsYyN03BzmENUqhxNYf6wN/+SuRmEvnusNNnUpM X8smf0BwoUJQSpUwMXGPanjCQ542RDdHm9BjFDnz9OxWrn5prbyjlRJZw dCkFZjSd2QqSTzeWMvx3SIV4H8le12tSasp3/hBWwF8+UqJQvRlC7Fcqv 4+LArzmNQpCFeiYFrltvorOtgKsdFupzU9g5TxtF/mRwNXnwwZO1QCICW w==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="304974571" IronPort-SDR: VxErY+h6sWf4mF8iWDQqrG24ASxlm2rcQaF/SnCsOIG1WMBNbu9T1jFzSN8sYbfd2bO2n3vOIW 1xO8mv8rPwSUDaGFfIXGbLk44cGg6LvqSLJv25rhhotYUAOO1X7Dr4Q8DVQyNgEEV0isxh5Sz7 Dbp2/xi2V/gtGwcNzzNroNHDOxeEYv0M844mpfIKLs44CwDXsYa5fGOza3YQZrG9sHD0ZZOXrH TwiCwfmhOeJoIOSg/n/rtp4bdhsxfP+uFUQm4zqSZoE1AoHA5ccn7W5mpct0RWM42WEi7W14Ip p4s8sHdsw4eUFjE+EU5vAoI7 IronPort-SDR: ptUXRSNslVU2QL2VFSbYX4dvX4hUzm7Yx2ZSuvS4ZSU2luCyvzQjhrXZs6naDRHrPujj8De5Wl ewm3n0S2zJ8Irnq/VWtTTUvC+gC9xeaGc4kWYOKsxBJi6CqdXcHAfP2FrgvIk+7ugIvn68iPuG tKzdnnGQXtYx1eIbePi+YQBghOZ4N9VA7aYBMtkfYMhjK0ywsRgFLQGEXN1FNPBKLBK+dMdrFJ QfxGKCAjG7uBhMDXew2s5muxbQU5K3wxP46yS2kdQsP4murTc1+AUuXZ5vNSezhX+ZXT/f+7rU sIQ= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993039; x=1647585040; bh=pvnxMTCRdBYWESBTah jlcU5dha2IzsUpRGE46NIzUNo=; b=Dcn3+L/hkQHsVi1AQslF+njNPLyPZtQF+b HUECwvk9tMnRay1ntIej+ca/eKb+QjhEC3PAmVOkAN5dGuFggVbEWMiganY7FpTL HXQzO3N55fyLirGaKN7MB++1lbjqJKP9I5fhe2hMhjpgyzNbQOI6SE0XHVHDa2bb kJgw2MNgAUCo7jqlFkztaqb/ehcPlxB1sCGkY7Q4fZZO9LTS5R4leW3QW3mTFmww SmEWJnjxeSCoVup2lQQ3//iwxR39lEIRTSrf5SDe++gtKcEIUU0TqpmOg3dYLUwF /YpqSkUMiQSXhmbfl/2DwKJa/kVMu4TyCxuQkJkNK954MnIGENGw== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anup Patel , Anup Patel , Bin Meng , Alistair Francis , Frank Chang Subject: [PULL v2 17/35] target/riscv: Add AIA cpu feature Date: Wed, 16 Feb 2022 16:28:54 +1000 Message-Id: <20220216062912.319738-18-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1644999387844100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel We define a CPU feature for AIA CSR support in RISC-V CPUs which can be set by machine/device emulation. The RISC-V CSR emulation will also check this feature for emulating AIA CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Message-id: 20220204174700.534953-7-anup@brainfault.org Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 283a3cda4b..8838c61ae4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -78,7 +78,8 @@ enum { RISCV_FEATURE_MMU, RISCV_FEATURE_PMP, RISCV_FEATURE_EPMP, - RISCV_FEATURE_MISA + RISCV_FEATURE_MISA, + RISCV_FEATURE_AIA }; =20 #define PRIV_VERSION_1_10_0 0x00011000 --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164500105100473.04543423586767; Wed, 16 Feb 2022 00:44:11 -0800 (PST) Received: from localhost ([::1]:37450 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKFuz-0001OI-Li for importer@patchew.org; Wed, 16 Feb 2022 03:44:09 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48768) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDpw-0006pK-BH for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:49 -0500 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:31617) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDpt-0006hk-Rn for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:48 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:30:45 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:03:33 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:30:45 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7Pc5MwRz1SVp0 for ; Tue, 15 Feb 2022 22:30:44 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id dCV24kxCv8hm for ; Tue, 15 Feb 2022 22:30:44 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7PX0xyxz1Rwrw; Tue, 15 Feb 2022 22:30:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993045; x=1676529045; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qXcdzDUAYU7rsB+Pl5f84y/rN49mlJ0K3qaF87uMZyE=; b=W2+PVmXFbJKIcedysDZq3PWhKIYTP8ttfAVDs4cd/76aOwXPxk3vlkmX dXTHif/GS9XN11m0PdzILocbZhCtOJMA9oPAHvTbI23ydKjaq01YVh8+0 sROSs0mg3zJ1Jlm3qhGVdl6fc0scJ/9o46+iu5L1Yz/Kwtrbq7fWddQr7 FxP/VmMLRcAR7f8wizMPaGsEwKzNLF6J8zkhx/BO0EfdP7JRhSuVqc5vD XYk4xkzGTG8vDL22pYBhgJr1nHVQ9AHuyh/fqhcwuuj8pii2iiD7jd8ln E++sK3YV9btlnxbz2x4qMlEuXReMPV9YgCKt1jiPZXeobNXqGp0akXo61 g==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="304974589" IronPort-SDR: zaWGnTBJ70QrKYcMx9W/Uqp3oaQGQ7W1gxMSjWLGDeXpWU8TIne55VLcoU1Jpf75Uik2dJnzua zfxmBtTLx8Jkn8iAPCAwtch9V2cx7ZnfAvNVi4bWNqH80V38NciJ5jY0+5O4q/QVz9Yvo2OxQU Mrmx3zm87MwigJmA0bO4bqzO5CWs8Nk3P1FSEaiIHSIspE0dRJwWjMEBwfioe1Xv2sfTw0n4oQ KCloTgPrhlw9jq5m8XtPvYjca1+oJCIRlG3q+Fl3H0c19hjVwWGcHGtOjdItgf9ikxUbuLG4+l JRh1vjvSNg5ybHRzfEIL8Q9Z IronPort-SDR: 9H9ZnWV/tGZM/wK4Mgvxmh/A7JJCKycRCMT7jQF7TU+ritv06VEswkV56Gt43SI8/6lXHDm1uQ ZGZrrIoSEJokOtjZmROQQ48DchBYBY16RrWRmFkp96mQCe4X+RBwUW66EjU3+vT64fv/pn+FaD G6lJzPjR3mnTgdFXgXoIc9aOzAKd9Ily2GZQIOBO27HZyBSTISunojW6PJpp4S/bYu6YpSit5h BZ5aveZkdHud5EAANzIfok2xObeGtohHZnxGMCqP4XnAx5AJTNImmRVTNXD89U75c6p2UKyIrW hy8= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993044; x=1647585045; bh=qXcdzDUAYU7rsB+Pl5 f84y/rN49mlJ0K3qaF87uMZyE=; b=lRB75ZiIJMCdzgziO6saEPaOqz+YXzxGIO o3io9E/HJeeqHr951g3/9Cc6/pHI7UgSRZ+H//+8XjIdlC3kkHjV9l5I1n7sfzKz AX572CVkE78YqyP4kDLXMHQccPMbCOUNJfLxN8jxAxin3kz9dABWXg91W6yxj6m/ hTQ2vq/OiD8yxqtHFK69cy8nlsnS14pTvusLMpNS1uQB5dXLBybZT3XOAQP8tAKb R7rI2SERo3lImfNVmV0HGbHNII2O11sWKu5ZI8A0DW78qOYPqrnRJMlFXpNhPbj2 erkwwzbCV5AY5K8Zpe329++69/A764w7519ylk3GHts7P4iMajVA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anup Patel , Anup Patel , Alistair Francis , Frank Chang Subject: [PULL v2 18/35] target/riscv: Add defines for AIA CSRs Date: Wed, 16 Feb 2022 16:28:55 +1000 Message-Id: <20220216062912.319738-19-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1645001051886100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel The RISC-V AIA specification extends RISC-V local interrupts and introduces new CSRs. This patch adds defines for the new AIA CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Message-id: 20220204174700.534953-8-anup@brainfault.org Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 119 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index a541705760..068c4d8034 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -168,6 +168,31 @@ #define CSR_MTVAL 0x343 #define CSR_MIP 0x344 =20 +/* Machine-Level Window to Indirectly Accessed Registers (AIA) */ +#define CSR_MISELECT 0x350 +#define CSR_MIREG 0x351 + +/* Machine-Level Interrupts (AIA) */ +#define CSR_MTOPI 0xfb0 + +/* Machine-Level IMSIC Interface (AIA) */ +#define CSR_MSETEIPNUM 0x358 +#define CSR_MCLREIPNUM 0x359 +#define CSR_MSETEIENUM 0x35a +#define CSR_MCLREIENUM 0x35b +#define CSR_MTOPEI 0x35c + +/* Virtual Interrupts for Supervisor Level (AIA) */ +#define CSR_MVIEN 0x308 +#define CSR_MVIP 0x309 + +/* Machine-Level High-Half CSRs (AIA) */ +#define CSR_MIDELEGH 0x313 +#define CSR_MIEH 0x314 +#define CSR_MVIENH 0x318 +#define CSR_MVIPH 0x319 +#define CSR_MIPH 0x354 + /* Supervisor Trap Setup */ #define CSR_SSTATUS 0x100 #define CSR_SEDELEG 0x102 @@ -187,6 +212,24 @@ #define CSR_SPTBR 0x180 #define CSR_SATP 0x180 =20 +/* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ +#define CSR_SISELECT 0x150 +#define CSR_SIREG 0x151 + +/* Supervisor-Level Interrupts (AIA) */ +#define CSR_STOPI 0xdb0 + +/* Supervisor-Level IMSIC Interface (AIA) */ +#define CSR_SSETEIPNUM 0x158 +#define CSR_SCLREIPNUM 0x159 +#define CSR_SSETEIENUM 0x15a +#define CSR_SCLREIENUM 0x15b +#define CSR_STOPEI 0x15c + +/* Supervisor-Level High-Half CSRs (AIA) */ +#define CSR_SIEH 0x114 +#define CSR_SIPH 0x154 + /* Hpervisor CSRs */ #define CSR_HSTATUS 0x600 #define CSR_HEDELEG 0x602 @@ -217,6 +260,35 @@ #define CSR_MTINST 0x34a #define CSR_MTVAL2 0x34b =20 +/* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ +#define CSR_HVIEN 0x608 +#define CSR_HVICTL 0x609 +#define CSR_HVIPRIO1 0x646 +#define CSR_HVIPRIO2 0x647 + +/* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA)= */ +#define CSR_VSISELECT 0x250 +#define CSR_VSIREG 0x251 + +/* VS-Level Interrupts (H-extension with AIA) */ +#define CSR_VSTOPI 0xeb0 + +/* VS-Level IMSIC Interface (H-extension with AIA) */ +#define CSR_VSSETEIPNUM 0x258 +#define CSR_VSCLREIPNUM 0x259 +#define CSR_VSSETEIENUM 0x25a +#define CSR_VSCLREIENUM 0x25b +#define CSR_VSTOPEI 0x25c + +/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ +#define CSR_HIDELEGH 0x613 +#define CSR_HVIENH 0x618 +#define CSR_HVIPH 0x655 +#define CSR_HVIPRIO1H 0x656 +#define CSR_HVIPRIO2H 0x657 +#define CSR_VSIEH 0x214 +#define CSR_VSIPH 0x254 + /* Enhanced Physical Memory Protection (ePMP) */ #define CSR_MSECCFG 0x747 #define CSR_MSECCFGH 0x757 @@ -635,4 +707,51 @@ typedef enum RISCVException { #define UMTE_U_PM_INSN U_PM_INSN #define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_IN= SN) =20 +/* MISELECT, SISELECT, and VSISELECT bits (AIA) */ +#define ISELECT_IPRIO0 0x30 +#define ISELECT_IPRIO15 0x3f +#define ISELECT_IMSIC_EIDELIVERY 0x70 +#define ISELECT_IMSIC_EITHRESHOLD 0x72 +#define ISELECT_IMSIC_EIP0 0x80 +#define ISELECT_IMSIC_EIP63 0xbf +#define ISELECT_IMSIC_EIE0 0xc0 +#define ISELECT_IMSIC_EIE63 0xff +#define ISELECT_IMSIC_FIRST ISELECT_IMSIC_EIDELIVERY +#define ISELECT_IMSIC_LAST ISELECT_IMSIC_EIE63 +#define ISELECT_MASK 0x1ff + +/* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */ +#define ISELECT_IMSIC_TOPEI (ISELECT_MASK + 1) + +/* IMSIC bits (AIA) */ +#define IMSIC_TOPEI_IID_SHIFT 16 +#define IMSIC_TOPEI_IID_MASK 0x7ff +#define IMSIC_TOPEI_IPRIO_MASK 0x7ff +#define IMSIC_EIPx_BITS 32 +#define IMSIC_EIEx_BITS 32 + +/* MTOPI and STOPI bits (AIA) */ +#define TOPI_IID_SHIFT 16 +#define TOPI_IID_MASK 0xfff +#define TOPI_IPRIO_MASK 0xff + +/* Interrupt priority bits (AIA) */ +#define IPRIO_IRQ_BITS 8 +#define IPRIO_MMAXIPRIO 255 +#define IPRIO_DEFAULT_UPPER 4 +#define IPRIO_DEFAULT_MIDDLE (IPRIO_DEFAULT_UPPER + 24) +#define IPRIO_DEFAULT_M IPRIO_DEFAULT_MIDDLE +#define IPRIO_DEFAULT_S (IPRIO_DEFAULT_M + 3) +#define IPRIO_DEFAULT_SGEXT (IPRIO_DEFAULT_S + 3) +#define IPRIO_DEFAULT_VS (IPRIO_DEFAULT_SGEXT + 1) +#define IPRIO_DEFAULT_LOWER (IPRIO_DEFAULT_VS + 3) + +/* HVICTL bits (AIA) */ +#define HVICTL_VTI 0x40000000 +#define HVICTL_IID 0x0fff0000 +#define HVICTL_IPRIOM 0x00000100 +#define HVICTL_IPRIO 0x000000ff +#define HVICTL_VALID_MASK \ + (HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO) + #endif --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1644999816765420.991333570685; Wed, 16 Feb 2022 00:23:36 -0800 (PST) Received: from localhost ([::1]:58684 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKFb5-0001zY-9R for importer@patchew.org; Wed, 16 Feb 2022 03:23:35 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48808) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDq1-0006ut-QP for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:54 -0500 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:31617) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDpy-0006hk-Rf for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:53 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:30:50 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:03:38 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:30:50 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7Pj5k0Bz1SVp0 for ; Tue, 15 Feb 2022 22:30:49 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id yYlLP7wmZOe7 for ; Tue, 15 Feb 2022 22:30:49 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7Pd0ywwz1Rwrw; Tue, 15 Feb 2022 22:30:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993050; x=1676529050; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ussBVH1+4h81kyuO/1QLKONncT5n9KCiu13m38fRO1M=; b=TxWFcsg/V8J3nqwM/NwssX1kx9z6ev9k92eM3W6m7K67EjgidF8mQQ7M 6d32Z/QU3ikL/FNA15HM37YF1YJG6vGXoXxEbF5dZKbcfLho0FZEfH1Hl ZNz7ZGDR6fvuy0h1JXn7rE/CfkXRf0IwVFzYD1aLwxw0sQk5wzF1PxdaN WKPq/NNFx8OgtfCx7paQTdQR+Ngr+lGlayN6XehThTPTRKbx71IeZ5ovL r3+84XViKsIULFurYaPEMsO5exuCbu2nk5hb/1VE3d89J22nDIVH4dOE8 P8sLSOymeTDOS6lmZHVZ0kIju8sig+OiY5NPYl3baYbEt9zZLzIec0Uw+ Q==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="304974598" IronPort-SDR: oQvYfIFgj2OjerVQx1/A5UkBXTAv8ei30prY+DvOaT0//kCpSTUqV5f72MA8B+ON5v1TgC/8y/ ZvhBeLqOSXOFO7ecdnPaOnVPH9ehxRiIb7FNEVG6vjjKoFugRImmqVRdviLhj/Lgoi1Jl4L0jK VO4pgE8MlgAUUVD8OW3xnYn32a1zaaZjGMGpI09KtzuJEjBYSmUEKJlVLe1Ibt5tv3NWaBlKCj vRG6gBzH+inDDwSChb2wT8eqXSemyytz4yS0f401l98OlcAruumIrVvVM+xbakC8ShrmpKkQVP c7dASLGtiIPmV/oyue0PwbG0 IronPort-SDR: BONvIsffB7LMLf9QEVpMsgyK8V30AFDRtRc5DxTRZ/nK4Y4ofa/oT8MhV7MdjGo8z4rwb5wEdx KLY4MxyGH3Np4ZCXcyJZ8lcaar0VLIaMvUtKP50Mx/FM1JtW44ZSlbaiwIH9Mo6YLyOseCbIkA bJUZZXmnKdw7DP/5Dz1JLKCfR7Y/0SS9NGTeGDUTFXNgQGSng/CB++UjQOu/n1MbZNyDabQ+BO rDyqJGZdhXD8CXU7mvH3+pm+mHYRtuNW32MBP4H3M5zg2cHPxtg4VJTel5nmfjZVA/PVvJxj9z IBM= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993049; x=1647585050; bh=ussBVH1+4h81kyuO/1 QLKONncT5n9KCiu13m38fRO1M=; b=Cb7XAQ2szVM+cOdv60+1lC0pWctP6vdKjD aNXwyVYR2PsZyIJ8WV+N/SFiTbLKmGij6qpjU8QOdqs48nP/RxStuJnJn3CsxgsJ 55iedxlL2YXKDf9zymvIBRL5zCzRRAAoEBj9sAlxPm8fCE+ZWfFfft9A507AQ2Xf jMwqxGYHIobZTrRZ0v0346SwrD4Z7nvXacEenOHyKvUNHV0hc0z7LE8uhfifTe6d vNfVXL7TH6ya+8fWCFkJUMQg4bh/RgX0/vqvQB6EombfP8LzSo9UBvOisaEOvIRE OwxrgJwaymA/udyGcS7mou7dA1RKGPhpwM0beh40LWacEiW59tWw== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anup Patel , Anup Patel , Alistair Francis , Frank Chang Subject: [PULL v2 19/35] target/riscv: Allow AIA device emulation to set ireg rmw callback Date: Wed, 16 Feb 2022 16:28:56 +1000 Message-Id: <20220216062912.319738-20-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1644999819995100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel The AIA device emulation (such as AIA IMSIC) should be able to set (or provide) AIA ireg read-modify-write callback for each privilege level of a RISC-V HART. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Message-id: 20220204174700.534953-9-anup@brainfault.org Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 23 +++++++++++++++++++++++ target/riscv/cpu_helper.c | 14 ++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8838c61ae4..6b6df57c42 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -256,6 +256,22 @@ struct CPURISCVState { uint64_t (*rdtime_fn)(uint32_t); uint32_t rdtime_fn_arg; =20 + /* machine specific AIA ireg read-modify-write callback */ +#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ + ((((__xlen) & 0xff) << 24) | \ + (((__vgein) & 0x3f) << 20) | \ + (((__virt) & 0x1) << 18) | \ + (((__priv) & 0x3) << 16) | \ + (__isel & 0xffff)) +#define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) +#define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) +#define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) +#define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) +#define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) + int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, + target_ulong *val, target_ulong new_val, target_ulong write_mask); + void *aia_ireg_rmw_fn_arg[4]; + /* True if in debugger mode. */ bool debugger; =20 @@ -433,6 +449,13 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t = mask, uint32_t value); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value = */ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), uint32_t arg); +void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, + int (*rmw_fn)(void *arg, + target_ulong reg, + target_ulong *val, + target_ulong new_val, + target_ulong write_mask), + void *rmw_fn_arg); #endif void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e45ca08ea9..37c58a891b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -396,6 +396,20 @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint6= 4_t (*fn)(uint32_t), env->rdtime_fn_arg =3D arg; } =20 +void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, + int (*rmw_fn)(void *arg, + target_ulong reg, + target_ulong *val, + target_ulong new_val, + target_ulong write_mask), + void *rmw_fn_arg) +{ + if (priv <=3D PRV_M) { + env->aia_ireg_rmw_fn[priv] =3D rmw_fn; + env->aia_ireg_rmw_fn_arg[priv] =3D rmw_fn_arg; + } +} + void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) { if (newpriv > PRV_M) { --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645001504866268.53451879087356; Wed, 16 Feb 2022 00:51:44 -0800 (PST) Received: from localhost ([::1]:47610 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKG2J-0000MW-ID for importer@patchew.org; Wed, 16 Feb 2022 03:51:43 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48838) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDq7-000701-BJ for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:59 -0500 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:31617) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDq3-0006hk-Id for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:30:58 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:30:54 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:03:42 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:30:55 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7Pp3hX1z1SHwl for ; Tue, 15 Feb 2022 22:30:54 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id mwnov173yHKy for ; Tue, 15 Feb 2022 22:30:53 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7Pk3jD1z1Rwrw; Tue, 15 Feb 2022 22:30:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993055; x=1676529055; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XiNO+2m9meUooasqQsb3xrY672W0NC8Lav1VobbXiFM=; b=kWoQfl5DiLl2qVu4Oee7jNVc2+1uYKpVb9g80IcDDAEyIGMnPn9RxSpw umwshIdNo+69qqFnJl+iPXaiCtunpEkhsVgXE+Fuhcso0HubJK2eS0Iyc YThGq4buzR2Xx8A149hmxEudDylK3itDZX51FfAIT1w/sxV53+FfWqbLN 0MHJJ3bXzIgZKCy9oBpa8v2j8TQG9g3C+39srxke3q/oH7Rw3SRLasgus 3Ne3YV1hL3W6OgjspL4pp6UKOBHH8LavxZWbtHQzBU1GdRhlWc3HOOLAa WDJ9sbVVjCpwzVCwELMh+FTJAyi70v87I88AToBuRGeWiJ+T1ZvysII6I A==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="304974608" IronPort-SDR: YVYCDBD4DUeQUBame7s7OCp3rNLZCCtKuX6vPNHZZKuIzhUjDSLD+uURURed+4re/pLL1nOU8m +vgOdHu6MyHw9542bpRXnHJhTjv0+3vObIsV0XIhFd5sAX1FodBcN0qzE7KCn0LbafBQgdrYlZ qj7MzSYl6pDgFTlQUi09FRLetpWxqIDkVcrAwZZMLFGs7+6NDhW/A+/s0sh4n2kfS2Sf6hfKsB Kx0AVyaEnH4eyUMt2yBxXMIAeZjloMAhfcXXMI7rMdVhSoahQ6SOqyfsC4UE1rrY+lD9fk3Phg ihuQWGwi/L9Inp+P/0zibxMN IronPort-SDR: 59XyQ/+UXYI1MojKUnnjSQ7AC59rNUQsOMebYVqaad94RFfdP6ZDJ/DSKNzhxejdVe1n0uICFE wzme4cdrCVXFkUheKQdSD4xAMvqkzb1CjlHHDteN8bEpQgUQdBzJ54rXAx3Mdun8J5ttrv6FGq 6j5B5JvFuZYQNS5pqkWELXdlFCv/NlqTzhaBigegi6LGfItbeaWUykjJw62Ix9h6qJj/29bN8B VXge8NcdJpRoFNeAKvyyVtvs5REb/me/7pc2AYHHrGFm1Ke3hfhy9qscaKO3OYM7tmd6q/mVLT upg= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993053; x=1647585054; bh=XiNO+2m9meUooasqQs b3xrY672W0NC8Lav1VobbXiFM=; b=eBoWaTY+Hr20yIIPVBAOr5Y50deF/X8fLu ugQnna23UbimiMeJn0XGoE1Z1bBqHqO+Xyi/mZbuOjh59Woql1B7HapiLfnoCOnz eJCmZi9Jv+CfKHEGnh++J2DZCw+qpxrDrOJR7+LTQBXXUwSGW0jufzNV9JoxdlKz bGzOwskCHu4fSDNXwAdWKkK7t1NczmOWWnJurGJlT0jMEU8l3xXFAsRuAs4yMWWr foJRqYmviHvtvbSc+9vu0DF0YVPaMT24SK7AQMoH1p4MCR3mrREd3649/I0Aiu23 l0WSIXz/U5mJO2AhW7BgB1StCY9QT5DqUZ5hDzkiyWmPNhmqcWKA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anup Patel , Anup Patel , Alistair Francis Subject: [PULL v2 20/35] target/riscv: Implement AIA local interrupt priorities Date: Wed, 16 Feb 2022 16:28:57 +1000 Message-Id: <20220216062912.319738-21-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1645001505485100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel The AIA spec defines programmable 8-bit priority for each local interrupt at M-level, S-level and VS-level so we extend local interrupt processing to consider AIA interrupt priorities. The AIA CSRs which help software configure local interrupt priorities will be added by subsequent patches. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Message-id: 20220204174700.534953-10-anup@brainfault.org Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 12 ++ target/riscv/cpu.c | 19 +++ target/riscv/cpu_helper.c | 281 +++++++++++++++++++++++++++++++++++--- target/riscv/machine.c | 3 + 4 files changed, 294 insertions(+), 21 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6b6df57c42..89e9cc558d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -192,6 +192,10 @@ struct CPURISCVState { target_ulong mcause; target_ulong mtval; /* since: priv-1.10.0 */ =20 + /* Machine and Supervisor interrupt priorities */ + uint8_t miprio[64]; + uint8_t siprio[64]; + /* Hypervisor CSRs */ target_ulong hstatus; target_ulong hedeleg; @@ -204,6 +208,9 @@ struct CPURISCVState { target_ulong hgeip; uint64_t htimedelta; =20 + /* Hypervisor controlled virtual interrupt priorities */ + uint8_t hviprio[64]; + /* Upper 64-bits of 128-bit CSRs */ uint64_t mscratchh; uint64_t sscratchh; @@ -415,6 +422,11 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f= , CPUState *cs, int cpuid, void *opaque); int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); +uint8_t riscv_cpu_default_priority(int irq); +int riscv_cpu_mirq_pending(CPURISCVState *env); +int riscv_cpu_sirq_pending(CPURISCVState *env); +int riscv_cpu_vsirq_pending(CPURISCVState *env); bool riscv_cpu_fp_enabled(CPURISCVState *env); target_ulong riscv_cpu_get_geilen(CPURISCVState *env); void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ff766acc21..5fb0a61036 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -400,6 +400,10 @@ void restore_state_to_opc(CPURISCVState *env, Translat= ionBlock *tb, =20 static void riscv_cpu_reset(DeviceState *dev) { +#ifndef CONFIG_USER_ONLY + uint8_t iprio; + int i, irq, rdzero; +#endif CPUState *cs =3D CPU(dev); RISCVCPU *cpu =3D RISCV_CPU(cs); RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); @@ -432,6 +436,21 @@ static void riscv_cpu_reset(DeviceState *dev) env->miclaim =3D MIP_SGEIP; env->pc =3D env->resetvec; env->two_stage_lookup =3D false; + + /* Initialized default priorities of local interrupts. */ + for (i =3D 0; i < ARRAY_SIZE(env->miprio); i++) { + iprio =3D riscv_cpu_default_priority(i); + env->miprio[i] =3D (i =3D=3D IRQ_M_EXT) ? 0 : iprio; + env->siprio[i] =3D (i =3D=3D IRQ_S_EXT) ? 0 : iprio; + env->hviprio[i] =3D 0; + } + i =3D 0; + while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { + if (!rdzero) { + env->hviprio[irq] =3D env->miprio[irq]; + } + i++; + } /* mmte is supposed to have pm.current hardwired to 1 */ env->mmte |=3D (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); #endif diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 37c58a891b..1a9534d6d7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -152,36 +152,275 @@ void riscv_cpu_update_mask(CPURISCVState *env) } =20 #ifndef CONFIG_USER_ONLY -static int riscv_cpu_local_irq_pending(CPURISCVState *env) + +/* + * The HS-mode is allowed to configure priority only for the + * following VS-mode local interrupts: + * + * 0 (Reserved interrupt, reads as zero) + * 1 Supervisor software interrupt + * 4 (Reserved interrupt, reads as zero) + * 5 Supervisor timer interrupt + * 8 (Reserved interrupt, reads as zero) + * 13 (Reserved interrupt) + * 14 " + * 15 " + * 16 " + * 18 Debug/trace interrupt + * 20 (Reserved interrupt) + * 22 " + * 24 " + * 26 " + * 28 " + * 30 (Reserved for standard reporting of bus or system errors) + */ + +static const int hviprio_index2irq[] =3D { + 0, 1, 4, 5, 8, 13, 14, 15, 16, 18, 20, 22, 24, 26, 28, 30 }; +static const int hviprio_index2rdzero[] =3D { + 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; + +int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero) +{ + if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <=3D index) { + return -EINVAL; + } + + if (out_irq) { + *out_irq =3D hviprio_index2irq[index]; + } + + if (out_rdzero) { + *out_rdzero =3D hviprio_index2rdzero[index]; + } + + return 0; +} + +/* + * Default priorities of local interrupts are defined in the + * RISC-V Advanced Interrupt Architecture specification. + * + * ---------------------------------------------------------------- + * Default | + * Priority | Major Interrupt Numbers + * ---------------------------------------------------------------- + * Highest | 63 (3f), 62 (3e), 31 (1f), 30 (1e), 61 (3d), 60 (3c), + * | 59 (3b), 58 (3a), 29 (1d), 28 (1c), 57 (39), 56 (38), + * | 55 (37), 54 (36), 27 (1b), 26 (1a), 53 (35), 52 (34), + * | 51 (33), 50 (32), 25 (19), 24 (18), 49 (31), 48 (30) + * | + * | 11 (0b), 3 (03), 7 (07) + * | 9 (09), 1 (01), 5 (05) + * | 12 (0c) + * | 10 (0a), 2 (02), 6 (06) + * | + * | 47 (2f), 46 (2e), 23 (17), 22 (16), 45 (2d), 44 (2c), + * | 43 (2b), 42 (2a), 21 (15), 20 (14), 41 (29), 40 (28), + * | 39 (27), 38 (26), 19 (13), 18 (12), 37 (25), 36 (24), + * Lowest | 35 (23), 34 (22), 17 (11), 16 (10), 33 (21), 32 (20) + * ---------------------------------------------------------------- + */ +static const uint8_t default_iprio[64] =3D { + [63] =3D IPRIO_DEFAULT_UPPER, + [62] =3D IPRIO_DEFAULT_UPPER + 1, + [31] =3D IPRIO_DEFAULT_UPPER + 2, + [30] =3D IPRIO_DEFAULT_UPPER + 3, + [61] =3D IPRIO_DEFAULT_UPPER + 4, + [60] =3D IPRIO_DEFAULT_UPPER + 5, + + [59] =3D IPRIO_DEFAULT_UPPER + 6, + [58] =3D IPRIO_DEFAULT_UPPER + 7, + [29] =3D IPRIO_DEFAULT_UPPER + 8, + [28] =3D IPRIO_DEFAULT_UPPER + 9, + [57] =3D IPRIO_DEFAULT_UPPER + 10, + [56] =3D IPRIO_DEFAULT_UPPER + 11, + + [55] =3D IPRIO_DEFAULT_UPPER + 12, + [54] =3D IPRIO_DEFAULT_UPPER + 13, + [27] =3D IPRIO_DEFAULT_UPPER + 14, + [26] =3D IPRIO_DEFAULT_UPPER + 15, + [53] =3D IPRIO_DEFAULT_UPPER + 16, + [52] =3D IPRIO_DEFAULT_UPPER + 17, + + [51] =3D IPRIO_DEFAULT_UPPER + 18, + [50] =3D IPRIO_DEFAULT_UPPER + 19, + [25] =3D IPRIO_DEFAULT_UPPER + 20, + [24] =3D IPRIO_DEFAULT_UPPER + 21, + [49] =3D IPRIO_DEFAULT_UPPER + 22, + [48] =3D IPRIO_DEFAULT_UPPER + 23, + + [11] =3D IPRIO_DEFAULT_M, + [3] =3D IPRIO_DEFAULT_M + 1, + [7] =3D IPRIO_DEFAULT_M + 2, + + [9] =3D IPRIO_DEFAULT_S, + [1] =3D IPRIO_DEFAULT_S + 1, + [5] =3D IPRIO_DEFAULT_S + 2, + + [12] =3D IPRIO_DEFAULT_SGEXT, + + [10] =3D IPRIO_DEFAULT_VS, + [2] =3D IPRIO_DEFAULT_VS + 1, + [6] =3D IPRIO_DEFAULT_VS + 2, + + [47] =3D IPRIO_DEFAULT_LOWER, + [46] =3D IPRIO_DEFAULT_LOWER + 1, + [23] =3D IPRIO_DEFAULT_LOWER + 2, + [22] =3D IPRIO_DEFAULT_LOWER + 3, + [45] =3D IPRIO_DEFAULT_LOWER + 4, + [44] =3D IPRIO_DEFAULT_LOWER + 5, + + [43] =3D IPRIO_DEFAULT_LOWER + 6, + [42] =3D IPRIO_DEFAULT_LOWER + 7, + [21] =3D IPRIO_DEFAULT_LOWER + 8, + [20] =3D IPRIO_DEFAULT_LOWER + 9, + [41] =3D IPRIO_DEFAULT_LOWER + 10, + [40] =3D IPRIO_DEFAULT_LOWER + 11, + + [39] =3D IPRIO_DEFAULT_LOWER + 12, + [38] =3D IPRIO_DEFAULT_LOWER + 13, + [19] =3D IPRIO_DEFAULT_LOWER + 14, + [18] =3D IPRIO_DEFAULT_LOWER + 15, + [37] =3D IPRIO_DEFAULT_LOWER + 16, + [36] =3D IPRIO_DEFAULT_LOWER + 17, + + [35] =3D IPRIO_DEFAULT_LOWER + 18, + [34] =3D IPRIO_DEFAULT_LOWER + 19, + [17] =3D IPRIO_DEFAULT_LOWER + 20, + [16] =3D IPRIO_DEFAULT_LOWER + 21, + [33] =3D IPRIO_DEFAULT_LOWER + 22, + [32] =3D IPRIO_DEFAULT_LOWER + 23, +}; + +uint8_t riscv_cpu_default_priority(int irq) { - target_ulong virt_enabled =3D riscv_cpu_virt_enabled(env); + if (irq < 0 || irq > 63) { + return IPRIO_MMAXIPRIO; + } + + return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; +}; =20 - target_ulong mstatus_mie =3D get_field(env->mstatus, MSTATUS_MIE); - target_ulong mstatus_sie =3D get_field(env->mstatus, MSTATUS_SIE); +static int riscv_cpu_pending_to_irq(CPURISCVState *env, + int extirq, unsigned int extirq_def_pr= io, + uint64_t pending, uint8_t *iprio) +{ + int irq, best_irq =3D RISCV_EXCP_NONE; + unsigned int prio, best_prio =3D UINT_MAX; =20 - target_ulong vsgemask =3D - (target_ulong)1 << get_field(env->hstatus, HSTATUS_VGEIN); - target_ulong vsgein =3D (env->hgeip & vsgemask) ? MIP_VSEIP : 0; + if (!pending) { + return RISCV_EXCP_NONE; + } =20 - target_ulong pending =3D (env->mip | vsgein) & env->mie; + irq =3D ctz64(pending); + if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + return irq; + } =20 - target_ulong mie =3D env->priv < PRV_M || - (env->priv =3D=3D PRV_M && mstatus_mie); - target_ulong sie =3D env->priv < PRV_S || - (env->priv =3D=3D PRV_S && mstatus_sie); - target_ulong hsie =3D virt_enabled || sie; - target_ulong vsie =3D virt_enabled && sie; + pending =3D pending >> irq; + while (pending) { + prio =3D iprio[irq]; + if (!prio) { + if (irq =3D=3D extirq) { + prio =3D extirq_def_prio; + } else { + prio =3D (riscv_cpu_default_priority(irq) < extirq_def_pri= o) ? + 1 : IPRIO_MMAXIPRIO; + } + } + if ((pending & 0x1) && (prio <=3D best_prio)) { + best_irq =3D irq; + best_prio =3D prio; + } + irq++; + pending =3D pending >> 1; + } =20 - target_ulong irqs =3D - (pending & ~env->mideleg & -mie) | - (pending & env->mideleg & ~env->hideleg & -hsie) | - (pending & env->mideleg & env->hideleg & -vsie); + return best_irq; +} =20 - if (irqs) { - return ctz64(irqs); /* since non-zero */ +static uint64_t riscv_cpu_all_pending(CPURISCVState *env) +{ + uint32_t gein =3D get_field(env->hstatus, HSTATUS_VGEIN); + uint64_t vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; + + return (env->mip | vsgein) & env->mie; +} + +int riscv_cpu_mirq_pending(CPURISCVState *env) +{ + uint64_t irqs =3D riscv_cpu_all_pending(env) & ~env->mideleg & + ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); + + return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, + irqs, env->miprio); +} + +int riscv_cpu_sirq_pending(CPURISCVState *env) +{ + uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & + ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); + + return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, + irqs, env->siprio); +} + +int riscv_cpu_vsirq_pending(CPURISCVState *env) +{ + uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); + + return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, + irqs >> 1, env->hviprio); +} + +static int riscv_cpu_local_irq_pending(CPURISCVState *env) +{ + int virq; + uint64_t irqs, pending, mie, hsie, vsie; + + /* Determine interrupt enable state of all privilege modes */ + if (riscv_cpu_virt_enabled(env)) { + mie =3D 1; + hsie =3D 1; + vsie =3D (env->priv < PRV_S) || + (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_= SIE)); } else { - return RISCV_EXCP_NONE; /* indicates no pending interrupt */ + mie =3D (env->priv < PRV_M) || + (env->priv =3D=3D PRV_M && get_field(env->mstatus, MSTATUS_M= IE)); + hsie =3D (env->priv < PRV_S) || + (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_= SIE)); + vsie =3D 0; + } + + /* Determine all pending interrupts */ + pending =3D riscv_cpu_all_pending(env); + + /* Check M-mode interrupts */ + irqs =3D pending & ~env->mideleg & -mie; + if (irqs) { + return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, + irqs, env->miprio); } + + /* Check HS-mode interrupts */ + irqs =3D pending & env->mideleg & ~env->hideleg & -hsie; + if (irqs) { + return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, + irqs, env->siprio); + } + + /* Check VS-mode interrupts */ + irqs =3D pending & env->mideleg & env->hideleg & -vsie; + if (irqs) { + virq =3D riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, + irqs >> 1, env->hviprio); + return (virq <=3D 0) ? virq : virq + 1; + } + + /* Indicate no pending interrupt */ + return RISCV_EXCP_NONE; } =20 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 7d72c2d8a6..30ed77c25f 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -92,6 +92,7 @@ static const VMStateDescription vmstate_hyper =3D { VMSTATE_UINTTL(env.hgeie, RISCVCPU), VMSTATE_UINTTL(env.hgeip, RISCVCPU), VMSTATE_UINT64(env.htimedelta, RISCVCPU), + VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64), =20 VMSTATE_UINT64(env.vsstatus, RISCVCPU), VMSTATE_UINTTL(env.vstvec, RISCVCPU), @@ -235,6 +236,8 @@ const VMStateDescription vmstate_riscv_cpu =3D { .fields =3D (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), + VMSTATE_UINT8_ARRAY(env.miprio, RISCVCPU, 64), + VMSTATE_UINT8_ARRAY(env.siprio, RISCVCPU, 64), VMSTATE_UINTTL(env.pc, RISCVCPU), VMSTATE_UINTTL(env.load_res, RISCVCPU), VMSTATE_UINTTL(env.load_val, RISCVCPU), --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645001688496958.3330475493103; Wed, 16 Feb 2022 00:54:48 -0800 (PST) Received: from localhost ([::1]:52650 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKG5I-0003pS-FV for importer@patchew.org; Wed, 16 Feb 2022 03:54:48 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48878) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDqE-00072J-0F for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:31:06 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:61739) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDqA-0006jO-Mp for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:31:05 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:31:01 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:03:49 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:31:01 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7Pw4HrKz1SVp2 for ; Tue, 15 Feb 2022 22:31:00 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id szY-jaLOoBtn for ; Tue, 15 Feb 2022 22:30:58 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7Pp3zfhz1SVny; Tue, 15 Feb 2022 22:30:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993062; x=1676529062; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ILRsvaVKfvY1nUzfLjMDeXgsaNnM92qUB0iNCpDeCuE=; b=JiReDyc+qYI4gVveVD2zSxihDN3/2BnCU18Vp1Elqi8gyYlL9rZwUs31 7YmzTBr68YsRvqI4w9bOnXSxKrRyi9b6WA/yZYXSBUgHojXjSSmq8MnDD CtqAS2OmyAydXheJWvedhNz2A5pJrRX85PK3fV7Unwb2AKeXO4qxb+LYD n2+O64e4GIoH2ohoksvVHWuOeou7CvivJMXz211g6jAkq78M133pmk/ic +XvtcFQ7W79Yt+B5gKvGhw0HdvnGqXKDSfO85Vx0n8cQSB/+hjDgxFOn9 3OQ4yfmUUk+zTK97RWIqU9zN7RW3dip27P5BtDxq3gfIWkzEnyBOYRj3k A==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="297181810" IronPort-SDR: 7b1eMYY+fxsY/MCe87C/jXN6mq+SB/SeuduosQxPa5OzZG8NlUgp8CWKgka/h6LFNYPIQxtHOw NP9Yai9d1k4bYXc18C2x7c6AIEwUn+7w/6y9QRfqeMgZIPH/n7QeFNTP2WqZQ2y0Jvwtyi4mgY vZiJxYfLXcWSQspiOegAa0CqFSZZsPHuoPxtOB/8x+y4ze+/7oVcjKasbUIbzLUcp7keC9/V03 1qwZVfXS58jMLX22JGLkO33dIuKtz3t3MZ+guj2xUQDjvcfrHtvWAeZ/G7ylWU9f9A8imCV+Vu ZPB2js4nieZUKmeqXns2PvO3 IronPort-SDR: fdjoyeNrjCR0ZxuyOnrIsn/LGsVAqUt6sZTJpqCqJKzZA9IqIdbFFuklt33gFFWRdSrRyMCfL7 wjglXkp2Dt+cEaIk0OhlH7QB6dbz8QcZptpmEn87mZl2zl8w4rWUVdfv6P6k0lJ5kWyMhFnIVa 2dB3k9j/Rn4g8ihYmhOAujLcJP+IO5rbzSR9vBGNAoCDPPzGLKLnjD1kNnXjkr6FIxxsKfn7Fq KD/IRR983ywfFbB4Z7AbrMNeS3uokQcxL7D2qUHfgeTMHmuxwN4jFkUPTv6L8xDPEByQvJrgx1 KV0= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993058; x=1647585059; bh=ILRsvaVKfvY1nUzfLj MDeXgsaNnM92qUB0iNCpDeCuE=; b=YxO1KpgDvXy7Q3U1kVmrTxUkvpucETvGnh 4VHN/BZYExpY6dntYbLSsgb3kQjZmyPHQ0NzBcchNYz2g6p38e6t6GyRl9Ty1vzc ieJF/Hc/IKwYYcVx+w56Jj5iLSKpg/i1MPeb7gKP9QLEoCZH90bkjmwyyD1Qve0m Nyb9K6v8vGXYBM962tUU6TifmDOnn4zNEanBHWjTx+tx/1R6GHsRbRxwofUAefjT kiLjyabDfIgeq5ZEzp2t8PyMu10ZwPC1Uws8dxvVLRfzymTZglwO4cwLrkDZROIv ZyMu6mmCWslnl0Nus2x6scPRv8OzU0vwdYhqqdwu04rVig6W9f9A== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anup Patel , Anup Patel , Alistair Francis , Frank Chang Subject: [PULL v2 21/35] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Date: Wed, 16 Feb 2022 16:28:58 +1000 Message-Id: <20220216062912.319738-22-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1645001691937100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel The AIA specification adds new CSRs for RV32 so that RISC-V hart can support 64 local interrupts on both RV32 and RV64. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Message-id: 20220204174700.534953-11-anup@brainfault.org Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 14 +- target/riscv/cpu_helper.c | 10 +- target/riscv/csr.c | 560 +++++++++++++++++++++++++++++++------- target/riscv/machine.c | 10 +- 4 files changed, 474 insertions(+), 120 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 89e9cc558d..2dc2485bb4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -172,12 +172,12 @@ struct CPURISCVState { */ uint64_t mstatus; =20 - target_ulong mip; + uint64_t mip; =20 - uint32_t miclaim; + uint64_t miclaim; =20 - target_ulong mie; - target_ulong mideleg; + uint64_t mie; + uint64_t mideleg; =20 target_ulong satp; /* since: priv-1.10.0 */ target_ulong stval; @@ -199,7 +199,7 @@ struct CPURISCVState { /* Hypervisor CSRs */ target_ulong hstatus; target_ulong hedeleg; - target_ulong hideleg; + uint64_t hideleg; target_ulong hcounteren; target_ulong htval; target_ulong htinst; @@ -456,8 +456,8 @@ void riscv_cpu_list(void); #ifndef CONFIG_USER_ONLY bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); -int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); -uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value= ); +int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); +uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value= ); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value = */ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), uint32_t arg); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 1a9534d6d7..430060dcd8 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -585,7 +585,7 @@ bool riscv_cpu_two_stage_lookup(int mmu_idx) return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; } =20 -int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) +int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) { CPURISCVState *env =3D &cpu->env; if (env->miclaim & interrupts) { @@ -596,11 +596,11 @@ int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_= t interrupts) } } =20 -uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) +uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value) { CPURISCVState *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); - uint32_t gein, vsgein =3D 0, old =3D env->mip; + uint64_t gein, vsgein =3D 0, old =3D env->mip; bool locked =3D false; =20 if (riscv_cpu_virt_enabled(env)) { @@ -1306,7 +1306,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) */ bool async =3D !!(cs->exception_index & RISCV_EXCP_INT_FLAG); target_ulong cause =3D cs->exception_index & RISCV_EXCP_INT_MASK; - target_ulong deleg =3D async ? env->mideleg : env->medeleg; + uint64_t deleg =3D async ? env->mideleg : env->medeleg; target_ulong tval =3D 0; target_ulong htval =3D 0; target_ulong mtval2 =3D 0; @@ -1373,7 +1373,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { /* handle the trap in S-mode */ if (riscv_has_ext(env, RVH)) { - target_ulong hdeleg =3D async ? env->hideleg : env->hedeleg; + uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; =20 if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) { /* Trap to VS mode */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index b23195b479..d8283160b1 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -158,6 +158,15 @@ static RISCVException any32(CPURISCVState *env, int cs= rno) =20 } =20 +static int aia_any32(CPURISCVState *env, int csrno) +{ + if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return any32(env, csrno); +} + static RISCVException smode(CPURISCVState *env, int csrno) { if (riscv_has_ext(env, RVS)) { @@ -167,6 +176,24 @@ static RISCVException smode(CPURISCVState *env, int cs= rno) return RISCV_EXCP_ILLEGAL_INST; } =20 +static int smode32(CPURISCVState *env, int csrno) +{ + if (riscv_cpu_mxl(env) !=3D MXL_RV32) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return smode(env, csrno); +} + +static int aia_smode32(CPURISCVState *env, int csrno) +{ + if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return smode32(env, csrno); +} + static RISCVException hmode(CPURISCVState *env, int csrno) { if (riscv_has_ext(env, RVS) && @@ -207,6 +234,15 @@ static RISCVException pointer_masking(CPURISCVState *e= nv, int csrno) return RISCV_EXCP_ILLEGAL_INST; } =20 +static int aia_hmode32(CPURISCVState *env, int csrno) +{ + if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return hmode32(env, csrno); +} + static RISCVException pmp(CPURISCVState *env, int csrno) { if (riscv_feature(env, RISCV_FEATURE_PMP)) { @@ -458,15 +494,15 @@ static RISCVException read_timeh(CPURISCVState *env, = int csrno, =20 /* Machine constants */ =20 -#define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) -#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) -#define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) -#define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS) +#define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP)) +#define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP)) +#define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) +#define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS)) =20 -static const target_ulong delegable_ints =3D S_MODE_INTERRUPTS | +static const uint64_t delegable_ints =3D S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS; -static const target_ulong vs_delegable_ints =3D VS_MODE_INTERRUPTS; -static const target_ulong all_ints =3D M_MODE_INTERRUPTS | S_MODE_INTERRUP= TS | +static const uint64_t vs_delegable_ints =3D VS_MODE_INTERRUPTS; +static const uint64_t all_ints =3D M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | HS_MODE_INTERRUPTS; #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ @@ -737,40 +773,107 @@ static RISCVException write_medeleg(CPURISCVState *e= nv, int csrno, return RISCV_EXCP_NONE; } =20 -static RISCVException read_mideleg(CPURISCVState *env, int csrno, - target_ulong *val) +static RISCVException rmw_mideleg64(CPURISCVState *env, int csrno, + uint64_t *ret_val, + uint64_t new_val, uint64_t wr_mask) { - *val =3D env->mideleg; - return RISCV_EXCP_NONE; -} + uint64_t mask =3D wr_mask & delegable_ints; + + if (ret_val) { + *ret_val =3D env->mideleg; + } + + env->mideleg =3D (env->mideleg & ~mask) | (new_val & mask); =20 -static RISCVException write_mideleg(CPURISCVState *env, int csrno, - target_ulong val) -{ - env->mideleg =3D (env->mideleg & ~delegable_ints) | (val & delegable_i= nts); if (riscv_has_ext(env, RVH)) { env->mideleg |=3D HS_MODE_INTERRUPTS; } + return RISCV_EXCP_NONE; } =20 -static RISCVException read_mie(CPURISCVState *env, int csrno, - target_ulong *val) +static RISCVException rmw_mideleg(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_ma= sk) { - *val =3D env->mie; - return RISCV_EXCP_NONE; + uint64_t rval; + RISCVException ret; + + ret =3D rmw_mideleg64(env, csrno, &rval, new_val, wr_mask); + if (ret_val) { + *ret_val =3D rval; + } + + return ret; } =20 -static RISCVException write_mie(CPURISCVState *env, int csrno, - target_ulong val) +static RISCVException rmw_midelegh(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, + target_ulong wr_mask) { - env->mie =3D (env->mie & ~all_ints) | (val & all_ints); + uint64_t rval; + RISCVException ret; + + ret =3D rmw_mideleg64(env, csrno, &rval, + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); + if (ret_val) { + *ret_val =3D rval >> 32; + } + + return ret; +} + +static RISCVException rmw_mie64(CPURISCVState *env, int csrno, + uint64_t *ret_val, + uint64_t new_val, uint64_t wr_mask) +{ + uint64_t mask =3D wr_mask & all_ints; + + if (ret_val) { + *ret_val =3D env->mie; + } + + env->mie =3D (env->mie & ~mask) | (new_val & mask); + if (!riscv_has_ext(env, RVH)) { - env->mie &=3D ~MIP_SGEIP; + env->mie &=3D ~((uint64_t)MIP_SGEIP); } + return RISCV_EXCP_NONE; } =20 +static RISCVException rmw_mie(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) +{ + uint64_t rval; + RISCVException ret; + + ret =3D rmw_mie64(env, csrno, &rval, new_val, wr_mask); + if (ret_val) { + *ret_val =3D rval; + } + + return ret; +} + +static RISCVException rmw_mieh(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) +{ + uint64_t rval; + RISCVException ret; + + ret =3D rmw_mie64(env, csrno, &rval, + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); + if (ret_val) { + *ret_val =3D rval >> 32; + } + + return ret; +} + static RISCVException read_mtvec(CPURISCVState *env, int csrno, target_ulong *val) { @@ -876,17 +979,17 @@ static RISCVException write_mtval(CPURISCVState *env,= int csrno, return RISCV_EXCP_NONE; } =20 -static RISCVException rmw_mip(CPURISCVState *env, int csrno, - target_ulong *ret_value, - target_ulong new_value, target_ulong write_m= ask) +static RISCVException rmw_mip64(CPURISCVState *env, int csrno, + uint64_t *ret_val, + uint64_t new_val, uint64_t wr_mask) { RISCVCPU *cpu =3D env_archcpu(env); /* Allow software control of delegable interrupts not claimed by hardw= are */ - target_ulong mask =3D write_mask & delegable_ints & ~env->miclaim; - uint32_t gin, old_mip; + uint64_t old_mip, mask =3D wr_mask & delegable_ints & ~env->miclaim; + uint32_t gin; =20 if (mask) { - old_mip =3D riscv_cpu_update_mip(cpu, mask, (new_value & mask)); + old_mip =3D riscv_cpu_update_mip(cpu, mask, (new_val & mask)); } else { old_mip =3D env->mip; } @@ -896,13 +999,44 @@ static RISCVException rmw_mip(CPURISCVState *env, int= csrno, old_mip |=3D (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP := 0; } =20 - if (ret_value) { - *ret_value =3D old_mip; + if (ret_val) { + *ret_val =3D old_mip; } =20 return RISCV_EXCP_NONE; } =20 +static RISCVException rmw_mip(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) +{ + uint64_t rval; + RISCVException ret; + + ret =3D rmw_mip64(env, csrno, &rval, new_val, wr_mask); + if (ret_val) { + *ret_val =3D rval; + } + + return ret; +} + +static RISCVException rmw_miph(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) +{ + uint64_t rval; + RISCVException ret; + + ret =3D rmw_mip64(env, csrno, &rval, + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); + if (ret_val) { + *ret_val =3D rval >> 32; + } + + return ret; +} + /* Supervisor Trap Setup */ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno, Int128 *val) @@ -943,45 +1077,112 @@ static RISCVException write_sstatus(CPURISCVState *= env, int csrno, return write_mstatus(env, CSR_MSTATUS, newval); } =20 -static RISCVException read_vsie(CPURISCVState *env, int csrno, - target_ulong *val) +static RISCVException rmw_vsie64(CPURISCVState *env, int csrno, + uint64_t *ret_val, + uint64_t new_val, uint64_t wr_mask) { - /* Shift the VS bits to their S bit location in vsie */ - *val =3D (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1; - return RISCV_EXCP_NONE; + RISCVException ret; + uint64_t rval, vsbits, mask =3D env->hideleg & VS_MODE_INTERRUPTS; + + /* Bring VS-level bits to correct position */ + vsbits =3D new_val & (VS_MODE_INTERRUPTS >> 1); + new_val &=3D ~(VS_MODE_INTERRUPTS >> 1); + new_val |=3D vsbits << 1; + vsbits =3D wr_mask & (VS_MODE_INTERRUPTS >> 1); + wr_mask &=3D ~(VS_MODE_INTERRUPTS >> 1); + wr_mask |=3D vsbits << 1; + + ret =3D rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask); + if (ret_val) { + rval &=3D mask; + vsbits =3D rval & VS_MODE_INTERRUPTS; + rval &=3D ~VS_MODE_INTERRUPTS; + *ret_val =3D rval | (vsbits >> 1); + } + + return ret; } =20 -static RISCVException read_sie(CPURISCVState *env, int csrno, - target_ulong *val) +static RISCVException rmw_vsie(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) { - if (riscv_cpu_virt_enabled(env)) { - read_vsie(env, CSR_VSIE, val); - } else { - *val =3D env->mie & env->mideleg; + uint64_t rval; + RISCVException ret; + + ret =3D rmw_vsie64(env, csrno, &rval, new_val, wr_mask); + if (ret_val) { + *ret_val =3D rval; } - return RISCV_EXCP_NONE; + + return ret; } =20 -static RISCVException write_vsie(CPURISCVState *env, int csrno, - target_ulong val) +static RISCVException rmw_vsieh(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) { - /* Shift the S bits to their VS bit location in mie */ - target_ulong newval =3D (env->mie & ~VS_MODE_INTERRUPTS) | - ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS); - return write_mie(env, CSR_MIE, newval); + uint64_t rval; + RISCVException ret; + + ret =3D rmw_vsie64(env, csrno, &rval, + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); + if (ret_val) { + *ret_val =3D rval >> 32; + } + + return ret; } =20 -static int write_sie(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException rmw_sie64(CPURISCVState *env, int csrno, + uint64_t *ret_val, + uint64_t new_val, uint64_t wr_mask) { + RISCVException ret; + uint64_t mask =3D env->mideleg & S_MODE_INTERRUPTS; + if (riscv_cpu_virt_enabled(env)) { - write_vsie(env, CSR_VSIE, val); + ret =3D rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask); } else { - target_ulong newval =3D (env->mie & ~S_MODE_INTERRUPTS) | - (val & S_MODE_INTERRUPTS); - write_mie(env, CSR_MIE, newval); + ret =3D rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask); } =20 - return RISCV_EXCP_NONE; + if (ret_val) { + *ret_val &=3D mask; + } + + return ret; +} + +static RISCVException rmw_sie(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) +{ + uint64_t rval; + RISCVException ret; + + ret =3D rmw_sie64(env, csrno, &rval, new_val, wr_mask); + if (ret_val) { + *ret_val =3D rval; + } + + return ret; +} + +static RISCVException rmw_sieh(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) +{ + uint64_t rval; + RISCVException ret; + + ret =3D rmw_sie64(env, csrno, &rval, + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); + if (ret_val) { + *ret_val =3D rval >> 32; + } + + return ret; } =20 static RISCVException read_stvec(CPURISCVState *env, int csrno, @@ -1089,38 +1290,111 @@ static RISCVException write_stval(CPURISCVState *e= nv, int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException rmw_vsip64(CPURISCVState *env, int csrno, + uint64_t *ret_val, + uint64_t new_val, uint64_t wr_mask) +{ + RISCVException ret; + uint64_t rval, vsbits, mask =3D env->hideleg & vsip_writable_mask; + + /* Bring VS-level bits to correct position */ + vsbits =3D new_val & (VS_MODE_INTERRUPTS >> 1); + new_val &=3D ~(VS_MODE_INTERRUPTS >> 1); + new_val |=3D vsbits << 1; + vsbits =3D wr_mask & (VS_MODE_INTERRUPTS >> 1); + wr_mask &=3D ~(VS_MODE_INTERRUPTS >> 1); + wr_mask |=3D vsbits << 1; + + ret =3D rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask); + if (ret_val) { + rval &=3D mask; + vsbits =3D rval & VS_MODE_INTERRUPTS; + rval &=3D ~VS_MODE_INTERRUPTS; + *ret_val =3D rval | (vsbits >> 1); + } + + return ret; +} + static RISCVException rmw_vsip(CPURISCVState *env, int csrno, - target_ulong *ret_value, - target_ulong new_value, target_ulong write_= mask) + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) { - /* Shift the S bits to their VS bit location in mip */ - int ret =3D rmw_mip(env, csrno, ret_value, new_value << 1, - (write_mask << 1) & vsip_writable_mask & env->hidele= g); + uint64_t rval; + RISCVException ret; =20 - if (ret_value) { - *ret_value &=3D VS_MODE_INTERRUPTS; - /* Shift the VS bits to their S bit location in vsip */ - *ret_value >>=3D 1; + ret =3D rmw_vsip64(env, csrno, &rval, new_val, wr_mask); + if (ret_val) { + *ret_val =3D rval; } + return ret; } =20 -static RISCVException rmw_sip(CPURISCVState *env, int csrno, - target_ulong *ret_value, - target_ulong new_value, target_ulong write_m= ask) +static RISCVException rmw_vsiph(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) { - int ret; + uint64_t rval; + RISCVException ret; + + ret =3D rmw_vsip64(env, csrno, &rval, + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); + if (ret_val) { + *ret_val =3D rval >> 32; + } + + return ret; +} + +static RISCVException rmw_sip64(CPURISCVState *env, int csrno, + uint64_t *ret_val, + uint64_t new_val, uint64_t wr_mask) +{ + RISCVException ret; + uint64_t mask =3D env->mideleg & sip_writable_mask; =20 if (riscv_cpu_virt_enabled(env)) { - ret =3D rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); + ret =3D rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask); } else { - ret =3D rmw_mip(env, csrno, ret_value, new_value, - write_mask & env->mideleg & sip_writable_mask); + ret =3D rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask); } =20 - if (ret_value) { - *ret_value &=3D env->mideleg & S_MODE_INTERRUPTS; + if (ret_val) { + *ret_val &=3D env->mideleg & S_MODE_INTERRUPTS; + } + + return ret; +} + +static RISCVException rmw_sip(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) +{ + uint64_t rval; + RISCVException ret; + + ret =3D rmw_sip64(env, csrno, &rval, new_val, wr_mask); + if (ret_val) { + *ret_val =3D rval; } + + return ret; +} + +static RISCVException rmw_siph(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) +{ + uint64_t rval; + RISCVException ret; + + ret =3D rmw_sip64(env, csrno, &rval, + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); + if (ret_val) { + *ret_val =3D rval >> 32; + } + return ret; } =20 @@ -1215,30 +1489,94 @@ static RISCVException write_hedeleg(CPURISCVState *= env, int csrno, return RISCV_EXCP_NONE; } =20 -static RISCVException read_hideleg(CPURISCVState *env, int csrno, - target_ulong *val) +static RISCVException rmw_hideleg64(CPURISCVState *env, int csrno, + uint64_t *ret_val, + uint64_t new_val, uint64_t wr_mask) { - *val =3D env->hideleg; + uint64_t mask =3D wr_mask & vs_delegable_ints; + + if (ret_val) { + *ret_val =3D env->hideleg & vs_delegable_ints; + } + + env->hideleg =3D (env->hideleg & ~mask) | (new_val & mask); return RISCV_EXCP_NONE; } =20 -static RISCVException write_hideleg(CPURISCVState *env, int csrno, - target_ulong val) +static RISCVException rmw_hideleg(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_ma= sk) { - env->hideleg =3D val & vs_delegable_ints; - return RISCV_EXCP_NONE; + uint64_t rval; + RISCVException ret; + + ret =3D rmw_hideleg64(env, csrno, &rval, new_val, wr_mask); + if (ret_val) { + *ret_val =3D rval; + } + + return ret; +} + +static RISCVException rmw_hidelegh(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_m= ask) +{ + uint64_t rval; + RISCVException ret; + + ret =3D rmw_hideleg64(env, csrno, &rval, + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); + if (ret_val) { + *ret_val =3D rval >> 32; + } + + return ret; +} + +static RISCVException rmw_hvip64(CPURISCVState *env, int csrno, + uint64_t *ret_val, + uint64_t new_val, uint64_t wr_mask) +{ + RISCVException ret; + + ret =3D rmw_mip64(env, csrno, ret_val, new_val, + wr_mask & hvip_writable_mask); + if (ret_val) { + *ret_val &=3D VS_MODE_INTERRUPTS; + } + + return ret; } =20 static RISCVException rmw_hvip(CPURISCVState *env, int csrno, - target_ulong *ret_value, - target_ulong new_value, target_ulong write_= mask) + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) { - int ret =3D rmw_mip(env, csrno, ret_value, new_value, - write_mask & hvip_writable_mask); + uint64_t rval; + RISCVException ret; =20 - if (ret_value) { - *ret_value &=3D VS_MODE_INTERRUPTS; + ret =3D rmw_hvip64(env, csrno, &rval, new_val, wr_mask); + if (ret_val) { + *ret_val =3D rval; + } + + return ret; +} + +static RISCVException rmw_hviph(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) +{ + uint64_t rval; + RISCVException ret; + + ret =3D rmw_hvip64(env, csrno, &rval, + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); + if (ret_val) { + *ret_val =3D rval >> 32; } + return ret; } =20 @@ -1255,18 +1593,19 @@ static RISCVException rmw_hip(CPURISCVState *env, i= nt csrno, return ret; } =20 -static RISCVException read_hie(CPURISCVState *env, int csrno, - target_ulong *val) +static RISCVException rmw_hie(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) { - *val =3D env->mie & HS_MODE_INTERRUPTS; - return RISCV_EXCP_NONE; -} + uint64_t rval; + RISCVException ret; =20 -static RISCVException write_hie(CPURISCVState *env, int csrno, - target_ulong val) -{ - target_ulong newval =3D (env->mie & ~HS_MODE_INTERRUPTS) | (val & HS_M= ODE_INTERRUPTS); - return write_mie(env, CSR_MIE, newval); + ret =3D rmw_mie64(env, csrno, &rval, new_val, wr_mask & HS_MODE_INTERR= UPTS); + if (ret_val) { + *ret_val =3D rval & HS_MODE_INTERRUPTS; + } + + return ret; } =20 static RISCVException read_hcounteren(CPURISCVState *env, int csrno, @@ -2124,9 +2463,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { read_mstatus_i128 = }, [CSR_MISA] =3D { "misa", any, read_misa, write_m= isa, NULL, read_misa_i128 = }, - [CSR_MIDELEG] =3D { "mideleg", any, read_mideleg, write_m= ideleg }, + [CSR_MIDELEG] =3D { "mideleg", any, NULL, NULL, rmw_mid= eleg }, [CSR_MEDELEG] =3D { "medeleg", any, read_medeleg, write_m= edeleg }, - [CSR_MIE] =3D { "mie", any, read_mie, write_m= ie }, + [CSR_MIE] =3D { "mie", any, NULL, NULL, rmw_mie= }, [CSR_MTVEC] =3D { "mtvec", any, read_mtvec, write_m= tvec }, [CSR_MCOUNTEREN] =3D { "mcounteren", any, read_mcounteren, write_m= counteren }, =20 @@ -2140,10 +2479,15 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MTVAL] =3D { "mtval", any, read_mtval, write_mtval }, [CSR_MIP] =3D { "mip", any, NULL, NULL, rmw_mip }, =20 + /* Machine-Level High-Half CSRs (AIA) */ + [CSR_MIDELEGH] =3D { "midelegh", aia_any32, NULL, NULL, rmw_midelegh }, + [CSR_MIEH] =3D { "mieh", aia_any32, NULL, NULL, rmw_mieh }, + [CSR_MIPH] =3D { "miph", aia_any32, NULL, NULL, rmw_miph }, + /* Supervisor Trap Setup */ [CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, write_sst= atus, NULL, read_sstatus_i128 = }, - [CSR_SIE] =3D { "sie", smode, read_sie, write_sie= }, + [CSR_SIE] =3D { "sie", smode, NULL, NULL, rmw_sie = }, [CSR_STVEC] =3D { "stvec", smode, read_stvec, write_stv= ec }, [CSR_SCOUNTEREN] =3D { "scounteren", smode, read_scounteren, write_sco= unteren }, =20 @@ -2158,12 +2502,16 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* Supervisor Protection and Translation */ [CSR_SATP] =3D { "satp", smode, read_satp, write_satp = }, =20 + /* Supervisor-Level High-Half CSRs (AIA) */ + [CSR_SIEH] =3D { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, + [CSR_SIPH] =3D { "siph", aia_smode32, NULL, NULL, rmw_siph }, + [CSR_HSTATUS] =3D { "hstatus", hmode, read_hstatus, writ= e_hstatus }, [CSR_HEDELEG] =3D { "hedeleg", hmode, read_hedeleg, writ= e_hedeleg }, - [CSR_HIDELEG] =3D { "hideleg", hmode, read_hideleg, writ= e_hideleg }, + [CSR_HIDELEG] =3D { "hideleg", hmode, NULL, NULL, rmw_= hideleg }, [CSR_HVIP] =3D { "hvip", hmode, NULL, NULL, rmw_= hvip }, [CSR_HIP] =3D { "hip", hmode, NULL, NULL, rmw_= hip }, - [CSR_HIE] =3D { "hie", hmode, read_hie, writ= e_hie }, + [CSR_HIE] =3D { "hie", hmode, NULL, NULL, rmw_= hie }, [CSR_HCOUNTEREN] =3D { "hcounteren", hmode, read_hcounteren, writ= e_hcounteren }, [CSR_HGEIE] =3D { "hgeie", hmode, read_hgeie, writ= e_hgeie }, [CSR_HTVAL] =3D { "htval", hmode, read_htval, writ= e_htval }, @@ -2175,7 +2523,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { =20 [CSR_VSSTATUS] =3D { "vsstatus", hmode, read_vsstatus, writ= e_vsstatus }, [CSR_VSIP] =3D { "vsip", hmode, NULL, NULL, rmw_= vsip }, - [CSR_VSIE] =3D { "vsie", hmode, read_vsie, writ= e_vsie }, + [CSR_VSIE] =3D { "vsie", hmode, NULL, NULL, rmw_= vsie }, [CSR_VSTVEC] =3D { "vstvec", hmode, read_vstvec, writ= e_vstvec }, [CSR_VSSCRATCH] =3D { "vsscratch", hmode, read_vsscratch, writ= e_vsscratch }, [CSR_VSEPC] =3D { "vsepc", hmode, read_vsepc, writ= e_vsepc }, @@ -2186,6 +2534,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MTVAL2] =3D { "mtval2", hmode, read_mtval2, writ= e_mtval2 }, [CSR_MTINST] =3D { "mtinst", hmode, read_mtinst, writ= e_mtinst }, =20 + /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ + [CSR_HIDELEGH] =3D { "hidelegh", aia_hmode32, NULL, NULL, rmw_hi= delegh }, + [CSR_HVIPH] =3D { "hviph", aia_hmode32, NULL, NULL, rmw_hv= iph }, + [CSR_VSIEH] =3D { "vsieh", aia_hmode32, NULL, NULL, rmw_vs= ieh }, + [CSR_VSIPH] =3D { "vsiph", aia_hmode32, NULL, NULL, rmw_vs= iph }, + /* Physical Memory Protection */ [CSR_MSECCFG] =3D { "mseccfg", epmp, read_mseccfg, write_mseccfg }, [CSR_PMPCFG0] =3D { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 30ed77c25f..65e63031ba 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -84,7 +84,7 @@ static const VMStateDescription vmstate_hyper =3D { .fields =3D (VMStateField[]) { VMSTATE_UINTTL(env.hstatus, RISCVCPU), VMSTATE_UINTTL(env.hedeleg, RISCVCPU), - VMSTATE_UINTTL(env.hideleg, RISCVCPU), + VMSTATE_UINT64(env.hideleg, RISCVCPU), VMSTATE_UINTTL(env.hcounteren, RISCVCPU), VMSTATE_UINTTL(env.htval, RISCVCPU), VMSTATE_UINTTL(env.htinst, RISCVCPU), @@ -256,10 +256,10 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL(env.resetvec, RISCVCPU), VMSTATE_UINTTL(env.mhartid, RISCVCPU), VMSTATE_UINT64(env.mstatus, RISCVCPU), - VMSTATE_UINTTL(env.mip, RISCVCPU), - VMSTATE_UINT32(env.miclaim, RISCVCPU), - VMSTATE_UINTTL(env.mie, RISCVCPU), - VMSTATE_UINTTL(env.mideleg, RISCVCPU), + VMSTATE_UINT64(env.mip, RISCVCPU), + VMSTATE_UINT64(env.miclaim, RISCVCPU), + VMSTATE_UINT64(env.mie, RISCVCPU), + VMSTATE_UINT64(env.mideleg, RISCVCPU), VMSTATE_UINTTL(env.satp, RISCVCPU), VMSTATE_UINTTL(env.stval, RISCVCPU), VMSTATE_UINTTL(env.medeleg, RISCVCPU), --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1644993444186878.2879832927945; Tue, 15 Feb 2022 22:37:24 -0800 (PST) Received: from localhost ([::1]:44234 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKDwI-00060K-Rb for importer@patchew.org; Wed, 16 Feb 2022 01:37:22 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48904) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDqF-00074R-Pm for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:31:07 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:61747) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDqD-0006kp-Pq for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:31:07 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:31:04 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:03:52 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:31:05 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7Q01ZFmz1SVnx for ; Tue, 15 Feb 2022 22:31:04 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id ZLSux21vJyGU for ; Tue, 15 Feb 2022 22:31:03 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7Pv4pThz1Rwrw; Tue, 15 Feb 2022 22:30:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993065; x=1676529065; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KrOIW+U93XGr14+WEgjD9HZ1fYMLZyyxoTC7SdKW/mA=; b=nq4nIwCdP7fcNHOKOC73mxISsjHCEBnPREUO3C6x+MOodurNrgpvVkUh PWwBj8QrGcw+Xcvq6x11q25+0b5N0yV56kMz9hFox+KqbxmmJqov7Byd8 cfloInN4orJwgvdhpUKDnlc/4VHDU4qGKkpUzN4szJTwPkY770V6OSy4j Jyk1T83bM7rmI0eTtFpfaixwUlsZyqd+623/Su8s9Kd/I5ViQ29RlYwnI uSrzqmfzhbR5I2/+4bH+zBYhPcfd2A8s7ZhlvhImTJwi5MQz4M2QdenRO xg8BB7SbgFZmDh/Wm7xyxVp04mXaVJyrnJevbTJPfmJ7FSpPa3BVcJ6LR w==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="297181818" IronPort-SDR: tvIRbtbeMuckgfT/TgfwAgWWivXZ4nLhMmjNGooot1uWZamIRTqGc1aoy3PLs/rf1q5nLWjJ9B hNzngoFxuiPfB2/24Qj17k0ABNRuWLzEgCVK0iYcAg8be2f7xriK+dduMqNsOhCPPWnIIkLr3k yFEa7Z1lTYOw3XVxaFug3RIFhmxUtKlIoXsZbiTJCFCL49OknBdWJQfOdmAKmCZg0MyhPXuPPe FEsC7ww8C+sd6uWLu4CczAu24IrxaqkqiIn4tslHMfbIokhXOslvJpQVfrN3ZE5fRf3da3oGIH dYotOMEPelUoSsNlRcmfyMKw IronPort-SDR: p0UXW1bxo2h0Og0GtHvgtaemDprgmxsPmt3GIK3fju3TipVrAxwMMUI81WG272Ih66MvloLOBE J/Y2gDVitEi1D7D/OH4inZ9BUpY90xyraqaotmvZO/Uv4+LrtBws7NZjmHL1xtBrTehk126nVr 1txAjO1oIpkznuooBFxWp9eevgWRFccyaOPwvJa3n+rBRR7qdug1F1gX4DBoTI/rG6fGtXd/24 URhIlk3W8vVwik3T4gLmxXgIyWOQb6FYLYqKryT/H9BS/P+Fz5RxJIbpg2wfITNixr+8IERy9M k74= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993063; x=1647585064; bh=KrOIW+U93XGr14+WEg jD9HZ1fYMLZyyxoTC7SdKW/mA=; b=DhAaGPaj54o9aV7vS7wvWzjYQVokuuLg4W u055N2vAfYN4aFQ3ZzQB3hQdSsT5bKtFKHldRNVPBkHoACCbDP0QBu4q5ZSLpUmh AwY9l7JpKPYMR15y4eChDUwY5BoTv6k2kdeOm2rliQOMBl4pZ9H/5AxTr3Ze5Ysa al8w9Yp86PofVQxJCHLvpsP6V/kaaycXpgMTDxjUVIaPcU6R78SyOg679az7akBG rLQxCvLPMKL+bD8KbQpXPjSikZX5t0rNPWJ5yU+sPwfoN0cCquqQyxMTlEA6zX+s cyjlhNv88z+hYTeioSI3r7SR/YAsexAxAPCTVuHra5wr20ZEbROA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anup Patel , Anup Patel , Alistair Francis , Frank Chang Subject: [PULL v2 22/35] target/riscv: Implement AIA hvictl and hviprioX CSRs Date: Wed, 16 Feb 2022 16:28:59 +1000 Message-Id: <20220216062912.319738-23-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1644993445926100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel The AIA hvictl and hviprioX CSRs allow hypervisor to control interrupts visible at VS-level. This patch implements AIA hvictl and hviprioX CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Message-id: 20220204174700.534953-12-anup@brainfault.org [ Changes by AF: - Fix possible unintilised variable error in rmw_sie() ] Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 + target/riscv/csr.c | 128 ++++++++++++++++++++++++++++++++++++++++- target/riscv/machine.c | 2 + 3 files changed, 131 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2dc2485bb4..f0e69f2871 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -209,6 +209,7 @@ struct CPURISCVState { uint64_t htimedelta; =20 /* Hypervisor controlled virtual interrupt priorities */ + target_ulong hvictl; uint8_t hviprio[64]; =20 /* Upper 64-bits of 128-bit CSRs */ @@ -512,6 +513,7 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) return env->misa_mxl; } #endif +#define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) =20 #if defined(TARGET_RISCV32) #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d8283160b1..46448a2b7e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -234,6 +234,15 @@ static RISCVException pointer_masking(CPURISCVState *e= nv, int csrno) return RISCV_EXCP_ILLEGAL_INST; } =20 +static int aia_hmode(CPURISCVState *env, int csrno) +{ + if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return hmode(env, csrno); +} + static int aia_hmode32(CPURISCVState *env, int csrno) { if (!riscv_feature(env, RISCV_FEATURE_AIA)) { @@ -1142,6 +1151,9 @@ static RISCVException rmw_sie64(CPURISCVState *env, i= nt csrno, uint64_t mask =3D env->mideleg & S_MODE_INTERRUPTS; =20 if (riscv_cpu_virt_enabled(env)) { + if (env->hvictl & HVICTL_VTI) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } ret =3D rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask); } else { ret =3D rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask); @@ -1162,7 +1174,7 @@ static RISCVException rmw_sie(CPURISCVState *env, int= csrno, RISCVException ret; =20 ret =3D rmw_sie64(env, csrno, &rval, new_val, wr_mask); - if (ret_val) { + if (ret =3D=3D RISCV_EXCP_NONE && ret_val) { *ret_val =3D rval; } =20 @@ -1355,6 +1367,9 @@ static RISCVException rmw_sip64(CPURISCVState *env, i= nt csrno, uint64_t mask =3D env->mideleg & sip_writable_mask; =20 if (riscv_cpu_virt_enabled(env)) { + if (env->hvictl & HVICTL_VTI) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } ret =3D rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask); } else { ret =3D rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask); @@ -1741,6 +1756,110 @@ static RISCVException write_htimedeltah(CPURISCVSta= te *env, int csrno, return RISCV_EXCP_NONE; } =20 +static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->hvictl; + return RISCV_EXCP_NONE; +} + +static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val) +{ + env->hvictl =3D val & HVICTL_VALID_MASK; + return RISCV_EXCP_NONE; +} + +static int read_hvipriox(CPURISCVState *env, int first_index, + uint8_t *iprio, target_ulong *val) +{ + int i, irq, rdzero, num_irqs =3D 4 * (riscv_cpu_mxl_bits(env) / 32); + + /* First index has to be a multiple of number of irqs per register */ + if (first_index % num_irqs) { + return (riscv_cpu_virt_enabled(env)) ? + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; + } + + /* Fill-up return value */ + *val =3D 0; + for (i =3D 0; i < num_irqs; i++) { + if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) { + continue; + } + if (rdzero) { + continue; + } + *val |=3D ((target_ulong)iprio[irq]) << (i * 8); + } + + return RISCV_EXCP_NONE; +} + +static int write_hvipriox(CPURISCVState *env, int first_index, + uint8_t *iprio, target_ulong val) +{ + int i, irq, rdzero, num_irqs =3D 4 * (riscv_cpu_mxl_bits(env) / 32); + + /* First index has to be a multiple of number of irqs per register */ + if (first_index % num_irqs) { + return (riscv_cpu_virt_enabled(env)) ? + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; + } + + /* Fill-up priority arrary */ + for (i =3D 0; i < num_irqs; i++) { + if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) { + continue; + } + if (rdzero) { + iprio[irq] =3D 0; + } else { + iprio[irq] =3D (val >> (i * 8)) & 0xff; + } + } + + return RISCV_EXCP_NONE; +} + +static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *val) +{ + return read_hvipriox(env, 0, env->hviprio, val); +} + +static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong val) +{ + return write_hvipriox(env, 0, env->hviprio, val); +} + +static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *val) +{ + return read_hvipriox(env, 4, env->hviprio, val); +} + +static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong val) +{ + return write_hvipriox(env, 4, env->hviprio, val); +} + +static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *val) +{ + return read_hvipriox(env, 8, env->hviprio, val); +} + +static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong val) +{ + return write_hvipriox(env, 8, env->hviprio, val); +} + +static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *val) +{ + return read_hvipriox(env, 12, env->hviprio, val); +} + +static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong val) +{ + return write_hvipriox(env, 12, env->hviprio, val); +} + /* Virtual CSR Registers */ static RISCVException read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val) @@ -2534,9 +2653,16 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MTVAL2] =3D { "mtval2", hmode, read_mtval2, writ= e_mtval2 }, [CSR_MTINST] =3D { "mtinst", hmode, read_mtinst, writ= e_mtinst }, =20 + /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) = */ + [CSR_HVICTL] =3D { "hvictl", aia_hmode, read_hvictl, write_h= victl }, + [CSR_HVIPRIO1] =3D { "hviprio1", aia_hmode, read_hviprio1, wri= te_hviprio1 }, + [CSR_HVIPRIO2] =3D { "hviprio2", aia_hmode, read_hviprio2, wri= te_hviprio2 }, + /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ [CSR_HIDELEGH] =3D { "hidelegh", aia_hmode32, NULL, NULL, rmw_hi= delegh }, [CSR_HVIPH] =3D { "hviph", aia_hmode32, NULL, NULL, rmw_hv= iph }, + [CSR_HVIPRIO1H] =3D { "hviprio1h", aia_hmode32, read_hviprio1h, wr= ite_hviprio1h }, + [CSR_HVIPRIO2H] =3D { "hviprio2h", aia_hmode32, read_hviprio2h, wr= ite_hviprio2h }, [CSR_VSIEH] =3D { "vsieh", aia_hmode32, NULL, NULL, rmw_vs= ieh }, [CSR_VSIPH] =3D { "vsiph", aia_hmode32, NULL, NULL, rmw_vs= iph }, =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 65e63031ba..dbd7bd0c83 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -92,6 +92,8 @@ static const VMStateDescription vmstate_hyper =3D { VMSTATE_UINTTL(env.hgeie, RISCVCPU), VMSTATE_UINTTL(env.hgeip, RISCVCPU), VMSTATE_UINT64(env.htimedelta, RISCVCPU), + + VMSTATE_UINTTL(env.hvictl, RISCVCPU), VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64), =20 VMSTATE_UINT64(env.vsstatus, RISCVCPU), --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1644994549084906.5539485876039; Tue, 15 Feb 2022 22:55:49 -0800 (PST) Received: from localhost ([::1]:52902 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKEE9-0004Ke-8w for importer@patchew.org; Wed, 16 Feb 2022 01:55:49 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48922) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDqJ-00076h-T4 for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:31:12 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:61749) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDqI-0006ld-1E for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:31:11 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:31:08 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:03:56 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:31:09 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7Q42TYCz1SVp1 for ; Tue, 15 Feb 2022 22:31:08 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id tcx7f51JDdbF for ; Tue, 15 Feb 2022 22:31:07 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7Q02DKfz1Rwrw; Tue, 15 Feb 2022 22:31:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993070; x=1676529070; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=e6y3dsWCf1ia7rtV5ptSfzr6nuJuaFHm6pTp3m7sfs0=; b=Wz6SZkj1aFoPyA0wcJbdBwuc8lWpH9P1nGbTNnzJDbRVDK7q7yYIFJd5 hPLhO30kUi8AYqshnAQZmVOWZLVe9s9MZE5STgGOBXZXzYPaS6+Llvse6 EtNqBLw1KvXHlFWEHjAryQQGSdCpLkneK7lAqQXTnUKauxWpBSMskg2qP roonn+p53x4w1IeXELAqrm278FfBNhuP6JL2XR+MfOVgEptIfm/3Hmw3j Nazd30GT5+kbG4fghc9/L4DOAlBbRhPSswLuwgw9ZLFoGn+JZ3X9vbfQ6 gORWE/1lsYmlTG6EgKUK699Ldp1Ux7sr8Dwpbd3rW0FYzePxkQJPvUFYE g==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="297181825" IronPort-SDR: czA6wZ8WBfNFLkuzxK/Rk/vLjThMdtJpSiSWg2NFuRTTMUYCH8d2IwDnPUXow39ZSfO4Z+vhvc LCgY0YmxTnKQNO8kZnBrIKXjoLNg672jLuekytIr+URqrJ2ZhaGf+aGklvetoWvIaw8yoBYFyu bGgbNErSRut1Lk7U4ISrm8StEp4rHQRY8qH9gt22kME0z2o77Pj6ZVWZKOg830/4RQ09FBIg4W FHtmOiAZBHMf04b4BC0ILR6ehEt3cdykMc+vD+Z/qGwIua6+mpjhKrk1qqUwonIAXEn9ZZRzh3 Nk1xPZYEY10TRRW90WeXdg6p IronPort-SDR: R8OL8D68S6kQDACWpl0MSjbmArZc7Fwr/igh2ChP3lFOqxCKN7uGmKlYDvNmDIz4EoEv7lVwcI 80e9+DXQPlsqM3ysIbJO7K64ZIVL21PCj5A9xz1/8M3j7N6JQgs5k7elI1kFu3YacGic6DnGf7 37JltjotrPLlNI3N1Dt4zYQMwcceLiv37Lr+Cxb51Ft4bHea7GU2vydKD7schxXTLmjs/ndIvH aoEZ595fQyptHBhd4VX2iH6K8kqitkSQnU32iwBOzhACMZxnE/0oKYbtTZ9eR9JsdGmSznnIud X20= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993067; x=1647585068; bh=e6y3dsWCf1ia7rtV5p tSfzr6nuJuaFHm6pTp3m7sfs0=; b=bmkTBEv9IF5RcWwnJ57zWQXTOcv8CSBy+u RhjbYo5plLRTltc3ir7+kaYiAbGFf74MUOYSQGDWj4N/v/S4T48rlDVnR8c1Jo4o X3bh9HTUlq0rkaRLO/U7D3vJmQxdcpWZXk/5oTwKQeUphUFpvABAGYTRR+Z1e24/ qOKF+MSOtTf2L3FbYGylDdcniD1DCB0wRY96tsezSzJh1JpX7qBV2btGT6sRMXej rrs73Ocjs7QSONdtAzUKpS0n0S9izmfUISEvYAGsYD2bdWuIY+xPC8HNqdz7+ArI pl7xcMZJRCvBStT4GYsSD9q13ZmzO9OcBVqu087UcerwlNbjC7Gg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anup Patel , Anup Patel , Alistair Francis , Frank Chang Subject: [PULL v2 23/35] target/riscv: Implement AIA interrupt filtering CSRs Date: Wed, 16 Feb 2022 16:29:00 +1000 Message-Id: <20220216062912.319738-24-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1644994551230100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel The AIA specificaiton adds interrupt filtering support for M-mode and HS-mode. Using AIA interrupt filtering M-mode and H-mode can take local interrupt 13 or above and selectively inject same local interrupt to lower privilege modes. At the moment, we don't have any local interrupts above 12 so we add dummy implementation (i.e. read zero and ignore write) of AIA interrupt filtering CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Message-id: 20220204174700.534953-13-anup@brainfault.org Signed-off-by: Alistair Francis --- target/riscv/csr.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 46448a2b7e..89700038fb 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -158,6 +158,15 @@ static RISCVException any32(CPURISCVState *env, int cs= rno) =20 } =20 +static int aia_any(CPURISCVState *env, int csrno) +{ + if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return any(env, csrno); +} + static int aia_any32(CPURISCVState *env, int csrno) { if (!riscv_feature(env, RISCV_FEATURE_AIA)) { @@ -568,6 +577,12 @@ static RISCVException read_zero(CPURISCVState *env, in= t csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException write_ignore(CPURISCVState *env, int csrno, + target_ulong val) +{ + return RISCV_EXCP_NONE; +} + static RISCVException read_mhartid(CPURISCVState *env, int csrno, target_ulong *val) { @@ -2598,9 +2613,15 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MTVAL] =3D { "mtval", any, read_mtval, write_mtval }, [CSR_MIP] =3D { "mip", any, NULL, NULL, rmw_mip }, =20 + /* Virtual Interrupts for Supervisor Level (AIA) */ + [CSR_MVIEN] =3D { "mvien", aia_any, read_zero, write_ignore }, + [CSR_MVIP] =3D { "mvip", aia_any, read_zero, write_ignore }, + /* Machine-Level High-Half CSRs (AIA) */ [CSR_MIDELEGH] =3D { "midelegh", aia_any32, NULL, NULL, rmw_midelegh }, [CSR_MIEH] =3D { "mieh", aia_any32, NULL, NULL, rmw_mieh }, + [CSR_MVIENH] =3D { "mvienh", aia_any32, read_zero, write_ignore }, + [CSR_MVIPH] =3D { "mviph", aia_any32, read_zero, write_ignore }, [CSR_MIPH] =3D { "miph", aia_any32, NULL, NULL, rmw_miph }, =20 /* Supervisor Trap Setup */ @@ -2654,12 +2675,14 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MTINST] =3D { "mtinst", hmode, read_mtinst, writ= e_mtinst }, =20 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) = */ + [CSR_HVIEN] =3D { "hvien", aia_hmode, read_zero, write_ign= ore }, [CSR_HVICTL] =3D { "hvictl", aia_hmode, read_hvictl, write_h= victl }, [CSR_HVIPRIO1] =3D { "hviprio1", aia_hmode, read_hviprio1, wri= te_hviprio1 }, [CSR_HVIPRIO2] =3D { "hviprio2", aia_hmode, read_hviprio2, wri= te_hviprio2 }, =20 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ [CSR_HIDELEGH] =3D { "hidelegh", aia_hmode32, NULL, NULL, rmw_hi= delegh }, + [CSR_HVIENH] =3D { "hvienh", aia_hmode32, read_zero, write_i= gnore }, [CSR_HVIPH] =3D { "hviph", aia_hmode32, NULL, NULL, rmw_hv= iph }, [CSR_HVIPRIO1H] =3D { "hviprio1h", aia_hmode32, read_hviprio1h, wr= ite_hviprio1h }, [CSR_HVIPRIO2H] =3D { "hviprio2h", aia_hmode32, read_hviprio2h, wr= ite_hviprio2h }, --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1644998164756991.7030961397666; Tue, 15 Feb 2022 23:56:04 -0800 (PST) Received: from localhost ([::1]:56588 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKFAR-0005EE-Bf for importer@patchew.org; Wed, 16 Feb 2022 02:56:03 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48952) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDqO-00079x-9u for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:31:16 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:61749) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDqM-0006ld-0W for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:31:16 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:31:13 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:04:01 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:31:13 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7Q86hfyz1SVp2 for ; Tue, 15 Feb 2022 22:31:12 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id P7rHFLRoaTQT for ; Tue, 15 Feb 2022 22:31:12 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7Q44Xfgz1Rwrw; Tue, 15 Feb 2022 22:31:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993074; x=1676529074; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Qu/zkqIJUrKSYtYPhIutzeZRZv8Yrs0kM+lNXYvui9E=; b=qFVOlSBkPD3f1vto0j8otpTK3TjXU1IFtjn2TG489NdFYV7/OdpSH2kU GLTCxbdeoe179g8SVRGv85o8x6rLMkAQoB7m4cb8v7rN/qjXGU7jh/koA TSjrdOPi87yzpCDshjWUEqcuGyQe/X8QfLtHM7vWQe9RldeyPrlCA42iE RjeBTSGTNrCD6wqWoKhp5W601aWT6/ayqa/vDs030t8hR5p2UdUQcWVBU eRN6XzA+KhXGlL8h4hdPa6GSjyg9imQBPjhZV650G8IF71/4UG/L4/MVu gyy37FpFY37durIK9dwG8f+dK2S/V8oKm2TwjU6kwvnuUUO0YnfjQ2pUo g==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="297181839" IronPort-SDR: 723WWLpT3ptbmEv4FVsexb7YPGnHrIDjb0WN5Jmx3t+XFwYikdJktZRdHY1z89z2th5hoUblAK VLCJ8YU47RiW0UsH4v2T7EL0lzSibmufU57HftF0lVayvzP05ve7Ea/crYzlBjEGrwgHunP17Q mLrj1irs5bXFRlHJ0N8vgE9azwpLcr5mcmyElS3TdoeE5yPHw5oKfzBu+VUnWbMdUghHc2M/tC bKVyCB0dOJsL6l4UcIAMxPnXwBadJBw1yBi1EUMKTax+HgqZg3ojkChP8mwLkBDoLgo9d9CPfw BR7RJrQsd486p6XCoOJJ5/OQ IronPort-SDR: 2FOttgr0qSz+qqCP+RNDa2qamhPWERygs9RGCcbzHQHYus1r1CXXT4il68lfzn67qxfOvecIBO 3jOucqkzKeJ+sa95IeeNEA2+I0EAkAJDI7RTRUFKaytUUwUOocSOVJho5WOJbgJ1JGljgDuuNh GZ5DwQCQvhQFjY5Hy9Mm059sPHF9rXlwedkBxXOHjOYoVJtPlKXxfxI+fnXmkPk9pvJEjDybUj dpZEclFlwPbv3ScgunvaduJ4uod7ifejADeHxF9MV8SsfAbBWIMqGF1cp+jAp0WXO0W0pf6jN5 nsk= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993072; x=1647585073; bh=Qu/zkqIJUrKSYtYPhI utzeZRZv8Yrs0kM+lNXYvui9E=; b=IS9Qw60xQgLTDjnzOinJDNW9a9QEehfCj3 odOM7SvyzV4ZUHH8+bZtMOqCPTfsux/7Zi6Vz2f6cAdxngpSfAlD4ldCeV3RNovA cMYHQS7AIdWFq69441RHs2KTVnjZm5OKnpyQQKS4GQePjkG5MvjqJPfppspjO6O7 gpnV8bab4Wxw4oe6IH1Si5/umZsV+qNmh2IIItaT8Nc0XE0Dvz1Lxgz6Zh89oI08 VCFzx6bukrmUmfdk4OR/E77dp+syL7PCgC9b/c+SjW+A89tFDZALCcURhtCph2pa qZtLCWTqmOFeMEUKKVtxmg5lqqkDFM1zSQWMReqF0S2alYg5r77g== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anup Patel , Anup Patel , Frank Chang , Alistair Francis Subject: [PULL v2 24/35] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Date: Wed, 16 Feb 2022 16:29:01 +1000 Message-Id: <20220216062912.319738-25-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1644998167010100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel The AIA specification introduces new [m|s|vs]topi CSRs for reporting pending local IRQ number and associated IRQ priority. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Frank Chang Message-id: 20220204174700.534953-14-anup@brainfault.org [ Changed by AF: - Fixup indentation ] Signed-off-by: Alistair Francis --- target/riscv/csr.c | 156 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 156 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 89700038fb..39402a6a49 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -194,6 +194,15 @@ static int smode32(CPURISCVState *env, int csrno) return smode(env, csrno); } =20 +static int aia_smode(CPURISCVState *env, int csrno) +{ + if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return smode(env, csrno); +} + static int aia_smode32(CPURISCVState *env, int csrno) { if (!riscv_feature(env, RISCV_FEATURE_AIA)) { @@ -517,6 +526,8 @@ static RISCVException read_timeh(CPURISCVState *env, in= t csrno, #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS)) =20 +#define VSTOPI_NUM_SRCS 5 + static const uint64_t delegable_ints =3D S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS; static const uint64_t vs_delegable_ints =3D VS_MODE_INTERRUPTS; @@ -898,6 +909,28 @@ static RISCVException rmw_mieh(CPURISCVState *env, int= csrno, return ret; } =20 +static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val) +{ + int irq; + uint8_t iprio; + + irq =3D riscv_cpu_mirq_pending(env); + if (irq <=3D 0 || irq > 63) { + *val =3D 0; + } else { + iprio =3D env->miprio[irq]; + if (!iprio) { + if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_M) { + iprio =3D IPRIO_MMAXIPRIO; + } + } + *val =3D (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT; + *val |=3D iprio; + } + + return RISCV_EXCP_NONE; +} + static RISCVException read_mtvec(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1478,6 +1511,120 @@ static RISCVException write_satp(CPURISCVState *env= , int csrno, return RISCV_EXCP_NONE; } =20 +static int read_vstopi(CPURISCVState *env, int csrno, target_ulong *val) +{ + int irq, ret; + target_ulong topei; + uint64_t vseip, vsgein; + uint32_t iid, iprio, hviid, hviprio, gein; + uint32_t s, scount =3D 0, siid[VSTOPI_NUM_SRCS], siprio[VSTOPI_NUM_SRC= S]; + + gein =3D get_field(env->hstatus, HSTATUS_VGEIN); + hviid =3D get_field(env->hvictl, HVICTL_IID); + hviprio =3D get_field(env->hvictl, HVICTL_IPRIO); + + if (gein) { + vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; + vseip =3D env->mie & (env->mip | vsgein) & MIP_VSEIP; + if (gein <=3D env->geilen && vseip) { + siid[scount] =3D IRQ_S_EXT; + siprio[scount] =3D IPRIO_MMAXIPRIO + 1; + if (env->aia_ireg_rmw_fn[PRV_S]) { + /* + * Call machine specific IMSIC register emulation for + * reading TOPEI. + */ + ret =3D env->aia_ireg_rmw_fn[PRV_S]( + env->aia_ireg_rmw_fn_arg[PRV_S], + AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, PRV_S, true, ge= in, + riscv_cpu_mxl_bits(env)), + &topei, 0, 0); + if (!ret && topei) { + siprio[scount] =3D topei & IMSIC_TOPEI_IPRIO_MASK; + } + } + scount++; + } + } else { + if (hviid =3D=3D IRQ_S_EXT && hviprio) { + siid[scount] =3D IRQ_S_EXT; + siprio[scount] =3D hviprio; + scount++; + } + } + + if (env->hvictl & HVICTL_VTI) { + if (hviid !=3D IRQ_S_EXT) { + siid[scount] =3D hviid; + siprio[scount] =3D hviprio; + scount++; + } + } else { + irq =3D riscv_cpu_vsirq_pending(env); + if (irq !=3D IRQ_S_EXT && 0 < irq && irq <=3D 63) { + siid[scount] =3D irq; + siprio[scount] =3D env->hviprio[irq]; + scount++; + } + } + + iid =3D 0; + iprio =3D UINT_MAX; + for (s =3D 0; s < scount; s++) { + if (siprio[s] < iprio) { + iid =3D siid[s]; + iprio =3D siprio[s]; + } + } + + if (iid) { + if (env->hvictl & HVICTL_IPRIOM) { + if (iprio > IPRIO_MMAXIPRIO) { + iprio =3D IPRIO_MMAXIPRIO; + } + if (!iprio) { + if (riscv_cpu_default_priority(iid) > IPRIO_DEFAULT_S) { + iprio =3D IPRIO_MMAXIPRIO; + } + } + } else { + iprio =3D 1; + } + } else { + iprio =3D 0; + } + + *val =3D (iid & TOPI_IID_MASK) << TOPI_IID_SHIFT; + *val |=3D iprio; + return RISCV_EXCP_NONE; +} + +static int read_stopi(CPURISCVState *env, int csrno, target_ulong *val) +{ + int irq; + uint8_t iprio; + + if (riscv_cpu_virt_enabled(env)) { + return read_vstopi(env, CSR_VSTOPI, val); + } + + irq =3D riscv_cpu_sirq_pending(env); + if (irq <=3D 0 || irq > 63) { + *val =3D 0; + } else { + iprio =3D env->siprio[irq]; + if (!iprio) { + if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_S) { + iprio =3D IPRIO_MMAXIPRIO; + } + } + *val =3D (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT; + *val |=3D iprio; + } + + return RISCV_EXCP_NONE; +} + /* Hypervisor Extensions */ static RISCVException read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) @@ -2613,6 +2760,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MTVAL] =3D { "mtval", any, read_mtval, write_mtval }, [CSR_MIP] =3D { "mip", any, NULL, NULL, rmw_mip }, =20 + /* Machine-Level Interrupts (AIA) */ + [CSR_MTOPI] =3D { "mtopi", aia_any, read_mtopi }, + /* Virtual Interrupts for Supervisor Level (AIA) */ [CSR_MVIEN] =3D { "mvien", aia_any, read_zero, write_ignore }, [CSR_MVIP] =3D { "mvip", aia_any, read_zero, write_ignore }, @@ -2642,6 +2792,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* Supervisor Protection and Translation */ [CSR_SATP] =3D { "satp", smode, read_satp, write_satp = }, =20 + /* Supervisor-Level Interrupts (AIA) */ + [CSR_STOPI] =3D { "stopi", aia_smode, read_stopi }, + /* Supervisor-Level High-Half CSRs (AIA) */ [CSR_SIEH] =3D { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, [CSR_SIPH] =3D { "siph", aia_smode32, NULL, NULL, rmw_siph }, @@ -2680,6 +2833,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_HVIPRIO1] =3D { "hviprio1", aia_hmode, read_hviprio1, wri= te_hviprio1 }, [CSR_HVIPRIO2] =3D { "hviprio2", aia_hmode, read_hviprio2, wri= te_hviprio2 }, =20 + /* VS-Level Interrupts (H-extension with AIA) */ + [CSR_VSTOPI] =3D { "vstopi", aia_hmode, read_vstopi }, + /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ [CSR_HIDELEGH] =3D { "hidelegh", aia_hmode32, NULL, NULL, rmw_hi= delegh }, [CSR_HVIENH] =3D { "hvienh", aia_hmode32, read_zero, write_i= gnore }, --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645001874311585.1377479661652; Wed, 16 Feb 2022 00:57:54 -0800 (PST) Received: from localhost ([::1]:59498 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKG8G-00005Q-Gm for importer@patchew.org; Wed, 16 Feb 2022 03:57:52 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48978) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDqT-0007Cs-A0 for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:31:21 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:61749) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDqQ-0006ld-ME for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:31:21 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:31:18 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:04:06 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:31:18 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7QF5D45z1SVnx for ; Tue, 15 Feb 2022 22:31:17 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id Fvlcowgfru6O for ; Tue, 15 Feb 2022 22:31:16 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7Q90F4Jz1Rwrw; Tue, 15 Feb 2022 22:31:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993078; x=1676529078; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lV2H8aXYNZI3v18ib9Zl0I4yxpDpFq/u9I0xi4LQS+I=; b=a04TtfsKZgCkcxFAvfp3jzyX1zaNd9Nb1toW72BNxGhojQZvJtMi5adP yAHgq3uvTz03DLXJczIYyEpSMBE8ITGwWosTTJhE9JrgiLZ2AEJwvMKDu DqTUm0oiPncuttHZaXZR1RvE8rD545QC+lmeixja98A8/zrCGfnVeooYX XrHZCiHNoCiaIMEOrm4dfLmLBkcHK60Z03jc/3Ujq2H1wVm1cX287a/P7 bgXCwgr6ZV5ABoc9oFbZKCbSc/tzdy3CJqq7pJNN4s8LbiBr9B+QawJKN dV4PBmM0yr0CaqAs0JPfipHG8fc58xzuMI1ydNM8hMHqRRJPFKrBmJ37s Q==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="297181845" IronPort-SDR: g+EdzMTRTvUyxkPqdzJKXEeC1oDjhvPzPc6H/mQ+ChaMRG/XBXxsVCmQurMvoJttSEoyVjkS3x BqRqI1t92ZK8npiJJHcynhH9IA4uJN0moQ6aOOvEqcKiSAYK24xafkw1KimSztyIz0Qb0PSGnm cjwiZI6sDMTBKrhhY8rC+pr6tVjvvX81o7WUqWNde1aUWz4CsRJyQ1gnKGaQeBMfAnXN856r+Z 1/TYhZjTlCmRZNGkBcAckHda69Ifmw6CvtP4OVE49xE0sU/0Dq8CO6kr/Ks3jsnGUJKgDYgaLM DZOI+f/PN9EqL9iBPtihDnEO IronPort-SDR: npZMU64RymR6/f5vidMtDPoDPPeWq4temefehoi0/XOnpze5ALyaPxk4PBmSxIFbgXtFlcGNR0 2oawDN2A947N79Ln8rZZ39A/+pN+OgNRmbnxVoBmGV1sXdznjvkdo3uauLY98fQAJONJgZlN/j C0Q6qZqD/7Mts/doHhLTOEvdn4xOnkmeLsFpmNK0TOGUgvuFcqOsEhjFVbWlQPdFbdsFsbZQRc STeuRNu6oTunLznMdUn+F+/2BbvniRA+G9oZERSfKDWz4tQ1P6tUiI3ArKAF2EEGzq62wzLMxY dG8= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993076; x=1647585077; bh=lV2H8aXYNZI3v18ib9 Zl0I4yxpDpFq/u9I0xi4LQS+I=; b=fBAwM7yIE5Go9D0eob8sFG0Yu37jevGLnZ KpSxfsVNkKyqbN3o72iKQSDkq+JrQoentl1f26iN8fRz/X1HEIWhV45cPBQhtJWj 3Gd5l0i9xt18f9444jCUuRnNKG20gaA+Ugb9+CfiL/PsSJ+ehb2F3+xlxi2WxtWV Oj5d/6/oLQseW5ace6IbRrr26dJZE+Fa3eAIwJPFqkSWwZPM9SU0tx1fHkWW1zCX Vmj5YDpdKueboR98EI254o9R9dWWw8O9SQZtXeBYtmANleMlEWGz3IwQ4Gr0KJYY tWlz7BuDjBcN62H9notq2hyg6l5buZ9+U/BZnFsQZegDKFq8dEFA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anup Patel , Anup Patel , Frank Chang , Alistair Francis Subject: [PULL v2 25/35] target/riscv: Implement AIA xiselect and xireg CSRs Date: Wed, 16 Feb 2022 16:29:02 +1000 Message-Id: <20220216062912.319738-26-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1645001875679100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs which allow indirect access to interrupt priority arrays and per-HART IMSIC registers. This patch implements AIA xiselect and xireg CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Frank Chang Message-id: 20220204174700.534953-15-anup@brainfault.org Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 7 ++ target/riscv/csr.c | 177 +++++++++++++++++++++++++++++++++++++++++ target/riscv/machine.c | 3 + 3 files changed, 187 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f0e69f2871..c70de10c85 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -196,6 +196,10 @@ struct CPURISCVState { uint8_t miprio[64]; uint8_t siprio[64]; =20 + /* AIA CSRs */ + target_ulong miselect; + target_ulong siselect; + /* Hypervisor CSRs */ target_ulong hstatus; target_ulong hedeleg; @@ -229,6 +233,9 @@ struct CPURISCVState { target_ulong vstval; target_ulong vsatp; =20 + /* AIA VS-mode CSRs */ + target_ulong vsiselect; + target_ulong mtval2; target_ulong mtinst; =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 39402a6a49..a186b31fcf 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -931,6 +931,169 @@ static int read_mtopi(CPURISCVState *env, int csrno, = target_ulong *val) return RISCV_EXCP_NONE; } =20 +static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno) +{ + if (!riscv_cpu_virt_enabled(env)) { + return csrno; + } + + switch (csrno) { + case CSR_SISELECT: + return CSR_VSISELECT; + case CSR_SIREG: + return CSR_VSIREG; + default: + return csrno; + }; +} + +static int rmw_xiselect(CPURISCVState *env, int csrno, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) +{ + target_ulong *iselect; + + /* Translate CSR number for VS-mode */ + csrno =3D aia_xlate_vs_csrno(env, csrno); + + /* Find the iselect CSR based on CSR number */ + switch (csrno) { + case CSR_MISELECT: + iselect =3D &env->miselect; + break; + case CSR_SISELECT: + iselect =3D &env->siselect; + break; + case CSR_VSISELECT: + iselect =3D &env->vsiselect; + break; + default: + return RISCV_EXCP_ILLEGAL_INST; + }; + + if (val) { + *val =3D *iselect; + } + + wr_mask &=3D ISELECT_MASK; + if (wr_mask) { + *iselect =3D (*iselect & ~wr_mask) | (new_val & wr_mask); + } + + return RISCV_EXCP_NONE; +} + +static int rmw_iprio(target_ulong xlen, + target_ulong iselect, uint8_t *iprio, + target_ulong *val, target_ulong new_val, + target_ulong wr_mask, int ext_irq_no) +{ + int i, firq, nirqs; + target_ulong old_val; + + if (iselect < ISELECT_IPRIO0 || ISELECT_IPRIO15 < iselect) { + return -EINVAL; + } + if (xlen !=3D 32 && iselect & 0x1) { + return -EINVAL; + } + + nirqs =3D 4 * (xlen / 32); + firq =3D ((iselect - ISELECT_IPRIO0) / (xlen / 32)) * (nirqs); + + old_val =3D 0; + for (i =3D 0; i < nirqs; i++) { + old_val |=3D ((target_ulong)iprio[firq + i]) << (IPRIO_IRQ_BITS * = i); + } + + if (val) { + *val =3D old_val; + } + + if (wr_mask) { + new_val =3D (old_val & ~wr_mask) | (new_val & wr_mask); + for (i =3D 0; i < nirqs; i++) { + /* + * M-level and S-level external IRQ priority always read-only + * zero. This means default priority order is always preferred + * for M-level and S-level external IRQs. + */ + if ((firq + i) =3D=3D ext_irq_no) { + continue; + } + iprio[firq + i] =3D (new_val >> (IPRIO_IRQ_BITS * i)) & 0xff; + } + } + + return 0; +} + +static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) +{ + bool virt; + uint8_t *iprio; + int ret =3D -EINVAL; + target_ulong priv, isel, vgein; + + /* Translate CSR number for VS-mode */ + csrno =3D aia_xlate_vs_csrno(env, csrno); + + /* Decode register details from CSR number */ + virt =3D false; + switch (csrno) { + case CSR_MIREG: + iprio =3D env->miprio; + isel =3D env->miselect; + priv =3D PRV_M; + break; + case CSR_SIREG: + iprio =3D env->siprio; + isel =3D env->siselect; + priv =3D PRV_S; + break; + case CSR_VSIREG: + iprio =3D env->hviprio; + isel =3D env->vsiselect; + priv =3D PRV_S; + virt =3D true; + break; + default: + goto done; + }; + + /* Find the selected guest interrupt file */ + vgein =3D (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; + + if (ISELECT_IPRIO0 <=3D isel && isel <=3D ISELECT_IPRIO15) { + /* Local interrupt priority registers not available for VS-mode */ + if (!virt) { + ret =3D rmw_iprio(riscv_cpu_mxl_bits(env), + isel, iprio, val, new_val, wr_mask, + (priv =3D=3D PRV_M) ? IRQ_M_EXT : IRQ_S_EXT); + } + } else if (ISELECT_IMSIC_FIRST <=3D isel && isel <=3D ISELECT_IMSIC_LA= ST) { + /* IMSIC registers only available when machine implements it. */ + if (env->aia_ireg_rmw_fn[priv]) { + /* Selected guest interrupt file should not be zero */ + if (virt && (!vgein || env->geilen < vgein)) { + goto done; + } + /* Call machine specific IMSIC register emulation */ + ret =3D env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[pr= iv], + AIA_MAKE_IREG(isel, priv, virt, vgein, + riscv_cpu_mxl_bits(env)), + val, new_val, wr_mask); + } + } + +done: + if (ret) { + return (riscv_cpu_virt_enabled(env) && virt) ? + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; + } + return RISCV_EXCP_NONE; +} + static RISCVException read_mtvec(CPURISCVState *env, int csrno, target_ulong *val) { @@ -2760,6 +2923,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MTVAL] =3D { "mtval", any, read_mtval, write_mtval }, [CSR_MIP] =3D { "mip", any, NULL, NULL, rmw_mip }, =20 + /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ + [CSR_MISELECT] =3D { "miselect", aia_any, NULL, NULL, rmw_xiselec= t }, + [CSR_MIREG] =3D { "mireg", aia_any, NULL, NULL, rmw_xireg }, + /* Machine-Level Interrupts (AIA) */ [CSR_MTOPI] =3D { "mtopi", aia_any, read_mtopi }, =20 @@ -2792,6 +2959,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* Supervisor Protection and Translation */ [CSR_SATP] =3D { "satp", smode, read_satp, write_satp = }, =20 + /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ + [CSR_SISELECT] =3D { "siselect", aia_smode, NULL, NULL, rmw_xisele= ct }, + [CSR_SIREG] =3D { "sireg", aia_smode, NULL, NULL, rmw_xireg = }, + /* Supervisor-Level Interrupts (AIA) */ [CSR_STOPI] =3D { "stopi", aia_smode, read_stopi }, =20 @@ -2833,6 +3004,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_HVIPRIO1] =3D { "hviprio1", aia_hmode, read_hviprio1, wri= te_hviprio1 }, [CSR_HVIPRIO2] =3D { "hviprio2", aia_hmode, read_hviprio2, wri= te_hviprio2 }, =20 + /* + * VS-Level Window to Indirectly Accessed Registers (H-extension with = AIA) + */ + [CSR_VSISELECT] =3D { "vsiselect", aia_hmode, NULL, NULL, rmw= _xiselect }, + [CSR_VSIREG] =3D { "vsireg", aia_hmode, NULL, NULL, rmw= _xireg }, + /* VS-Level Interrupts (H-extension with AIA) */ [CSR_VSTOPI] =3D { "vstopi", aia_hmode, read_vstopi }, =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index dbd7bd0c83..5178b3fec9 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -103,6 +103,7 @@ static const VMStateDescription vmstate_hyper =3D { VMSTATE_UINTTL(env.vscause, RISCVCPU), VMSTATE_UINTTL(env.vstval, RISCVCPU), VMSTATE_UINTTL(env.vsatp, RISCVCPU), + VMSTATE_UINTTL(env.vsiselect, RISCVCPU), =20 VMSTATE_UINTTL(env.mtval2, RISCVCPU), VMSTATE_UINTTL(env.mtinst, RISCVCPU), @@ -272,6 +273,8 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL(env.mepc, RISCVCPU), VMSTATE_UINTTL(env.mcause, RISCVCPU), VMSTATE_UINTTL(env.mtval, RISCVCPU), + VMSTATE_UINTTL(env.miselect, RISCVCPU), + VMSTATE_UINTTL(env.siselect, RISCVCPU), VMSTATE_UINTTL(env.scounteren, RISCVCPU), VMSTATE_UINTTL(env.mcounteren, RISCVCPU), VMSTATE_UINTTL(env.sscratch, RISCVCPU), --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645000139648574.021231000868; Wed, 16 Feb 2022 00:28:59 -0800 (PST) Received: from localhost ([::1]:38780 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKFgH-0007fp-O5 for importer@patchew.org; Wed, 16 Feb 2022 03:28:58 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49008) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDqk-0007Gu-5J for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:31:38 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:61749) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDqX-0006ld-TD for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:31:28 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:31:23 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:04:11 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:31:23 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7QL573qz1SVp2 for ; Tue, 15 Feb 2022 22:31:22 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id L8Ua-mKRk3z7 for ; Tue, 15 Feb 2022 22:31:21 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7QG01hbz1Rwrw; Tue, 15 Feb 2022 22:31:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993085; x=1676529085; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FCTKbj5OTOUhTD/XG6JhsHUqPfzV/Nk7dwVazqXa3as=; b=dGuCFBlHZxS9pri9XtihxkjlIZaKCVU1K5spjBFHhblqI6ZKUNGSvgHe 1xwPynKEzOS6/mwB6KPrxwzVle8+cy7VdgVCoaB85RAsIS36EHEaz4O+m OFHpEvA2UOfZMuZL2R/LkCha4ZwQZzcx+oc5iPAn/e11DJFPeBGlnY5hw BlOU2RNwOubd3k+IUqj7EEdZQ8anEw+k+3IT/P/FdOviN5y94/zhN8vKs ykyKHzIEbBpUQXVLSmamIqje/ouQbmqXgs1SkFRhAFd1hvjaFEJRKZ4KD HPrj/xKQ+rGQf1S4/1eLrye3319J3iktOS4NdQ7ByD9jGgkkrwkxKo9Eg Q==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="297181852" IronPort-SDR: yGo2bUWn9IwPswDD71glPBFcjpCWG+65lQHkuuyDI60KACS1QzqnKbyZSvJp52p3OYae5KTbVQ zJKeAP5QL5ud2RaYslXAsUC+x687Ecw0O2hHt2S1t/uyGMkDP/W5mt62CkOmAYI7TfIdNJ7MdW cxlxO1syeJywhWaqHkJLN6ghazqM+zcwSk5NWx6VCxyD0V5hEkOaLL60b8DY+NFoFKay7uPcqi B6Vw2Y+qUDCO3S1BRepAgbHgeaeEShx/s45HiGICvTdD52+48owVQklLVMOD9q526NiU5B9+3/ e772OD8VHEOLVRI1cVvP+sEE IronPort-SDR: ty4r+mbRBWUtAmAr3M1Sb65Jc2PN33a8enoOUBKclyvyXyZu2M6ZGb44f+AGN2MWgSHtYwnoQP Ma8S5l0aGiecSyZRf2xPGA4mhjyvWAXkcCaZ+7VIXhBoXvE+lDBGZEOu+bS0kH4LzX8BUl1Sis hXY8FIIZllDbbTwtBZdpy2j0vwJa87p9Obp+NO9p3G5iknWx4RVMcI0RjtA6sm56sU/V9IwwWi 6reWQHfB01ecTY8sW2azEXuXzHvXzc24HOXAvWZHU0TpH4MyJEHHsVqETFOoJUg6DYl6qT+hhX Z7M= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993081; x=1647585082; bh=FCTKbj5OTOUhTD/XG6 JhsHUqPfzV/Nk7dwVazqXa3as=; b=FFcDt8GK3DvJNVkaZCHmUnJzWdXvkv+PnF LnqtILdSN8XFFP3ius/399HxH04tayoi3foeXrFTMoJd9PlN03YfhQnYUFXgeJaG lHVQZUd3AiIjoGgev1EP9BGMgvZmBG+x1VVyOoZTZ1Qw+KPBrqZiqCYT7tWymnSF nx5EI3t4IqxWfvm0SyVxi304FvVTmPsWpMfXyHQjlCHrjLl/03w4lLvGKpp1NaBK yZeJQikf1IdaeK9bqvx8r93WBuBhkhmcFuXWqLyQEht2CaApKAqXh5v9M94jewxI 5IXStwyEQG1Ye/hSMPkDQEsLAl+OKfKdSfkrn+oDV1ljfEUmPbpA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anup Patel , Anup Patel , Frank Chang , Alistair Francis Subject: [PULL v2 26/35] target/riscv: Implement AIA IMSIC interface CSRs Date: Wed, 16 Feb 2022 16:29:03 +1000 Message-Id: <20220216062912.319738-27-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1645000141150100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel The AIA specification defines IMSIC interface CSRs for easy access to the per-HART IMSIC registers without using indirect xiselect and xireg CSRs. This patch implements the AIA IMSIC interface CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Frank Chang Message-id: 20220204174700.534953-16-anup@brainfault.org Signed-off-by: Alistair Francis --- target/riscv/csr.c | 203 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 203 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a186b31fcf..fe2c8dd40e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -942,6 +942,16 @@ static int aia_xlate_vs_csrno(CPURISCVState *env, int = csrno) return CSR_VSISELECT; case CSR_SIREG: return CSR_VSIREG; + case CSR_SSETEIPNUM: + return CSR_VSSETEIPNUM; + case CSR_SCLREIPNUM: + return CSR_VSCLREIPNUM; + case CSR_SSETEIENUM: + return CSR_VSSETEIENUM; + case CSR_SCLREIENUM: + return CSR_VSCLREIENUM; + case CSR_STOPEI: + return CSR_VSTOPEI; default: return csrno; }; @@ -1094,6 +1104,178 @@ done: return RISCV_EXCP_NONE; } =20 +static int rmw_xsetclreinum(CPURISCVState *env, int csrno, target_ulong *v= al, + target_ulong new_val, target_ulong wr_mask) +{ + int ret =3D -EINVAL; + bool set, pend, virt; + target_ulong priv, isel, vgein, xlen, nval, wmask; + + /* Translate CSR number for VS-mode */ + csrno =3D aia_xlate_vs_csrno(env, csrno); + + /* Decode register details from CSR number */ + virt =3D set =3D pend =3D false; + switch (csrno) { + case CSR_MSETEIPNUM: + priv =3D PRV_M; + set =3D true; + pend =3D true; + break; + case CSR_MCLREIPNUM: + priv =3D PRV_M; + pend =3D true; + break; + case CSR_MSETEIENUM: + priv =3D PRV_M; + set =3D true; + break; + case CSR_MCLREIENUM: + priv =3D PRV_M; + break; + case CSR_SSETEIPNUM: + priv =3D PRV_S; + set =3D true; + pend =3D true; + break; + case CSR_SCLREIPNUM: + priv =3D PRV_S; + pend =3D true; + break; + case CSR_SSETEIENUM: + priv =3D PRV_S; + set =3D true; + break; + case CSR_SCLREIENUM: + priv =3D PRV_S; + break; + case CSR_VSSETEIPNUM: + priv =3D PRV_S; + virt =3D true; + set =3D true; + pend =3D true; + break; + case CSR_VSCLREIPNUM: + priv =3D PRV_S; + virt =3D true; + pend =3D true; + break; + case CSR_VSSETEIENUM: + priv =3D PRV_S; + virt =3D true; + set =3D true; + break; + case CSR_VSCLREIENUM: + priv =3D PRV_S; + virt =3D true; + break; + default: + goto done; + }; + + /* IMSIC CSRs only available when machine implements IMSIC. */ + if (!env->aia_ireg_rmw_fn[priv]) { + goto done; + } + + /* Find the selected guest interrupt file */ + vgein =3D (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; + + /* Selected guest interrupt file should be valid */ + if (virt && (!vgein || env->geilen < vgein)) { + goto done; + } + + /* Set/Clear CSRs always read zero */ + if (val) { + *val =3D 0; + } + + if (wr_mask) { + /* Get interrupt number */ + new_val &=3D wr_mask; + + /* Find target interrupt pending/enable register */ + xlen =3D riscv_cpu_mxl_bits(env); + isel =3D (new_val / xlen); + isel *=3D (xlen / IMSIC_EIPx_BITS); + isel +=3D (pend) ? ISELECT_IMSIC_EIP0 : ISELECT_IMSIC_EIE0; + + /* Find the interrupt bit to be set/clear */ + wmask =3D ((target_ulong)1) << (new_val % xlen); + nval =3D (set) ? wmask : 0; + + /* Call machine specific IMSIC register emulation */ + ret =3D env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], + AIA_MAKE_IREG(isel, priv, virt, + vgein, xlen), + NULL, nval, wmask); + } else { + ret =3D 0; + } + +done: + if (ret) { + return (riscv_cpu_virt_enabled(env) && virt) ? + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; + } + return RISCV_EXCP_NONE; +} + +static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) +{ + bool virt; + int ret =3D -EINVAL; + target_ulong priv, vgein; + + /* Translate CSR number for VS-mode */ + csrno =3D aia_xlate_vs_csrno(env, csrno); + + /* Decode register details from CSR number */ + virt =3D false; + switch (csrno) { + case CSR_MTOPEI: + priv =3D PRV_M; + break; + case CSR_STOPEI: + priv =3D PRV_S; + break; + case CSR_VSTOPEI: + priv =3D PRV_S; + virt =3D true; + break; + default: + goto done; + }; + + /* IMSIC CSRs only available when machine implements IMSIC. */ + if (!env->aia_ireg_rmw_fn[priv]) { + goto done; + } + + /* Find the selected guest interrupt file */ + vgein =3D (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; + + /* Selected guest interrupt file should be valid */ + if (virt && (!vgein || env->geilen < vgein)) { + goto done; + } + + /* Call machine specific IMSIC register emulation for TOPEI */ + ret =3D env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], + AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, priv, virt, vgein, + riscv_cpu_mxl_bits(env)), + val, new_val, wr_mask); + +done: + if (ret) { + return (riscv_cpu_virt_enabled(env) && virt) ? + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; + } + return RISCV_EXCP_NONE; +} + static RISCVException read_mtvec(CPURISCVState *env, int csrno, target_ulong *val) { @@ -2930,6 +3112,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* Machine-Level Interrupts (AIA) */ [CSR_MTOPI] =3D { "mtopi", aia_any, read_mtopi }, =20 + /* Machine-Level IMSIC Interface (AIA) */ + [CSR_MSETEIPNUM] =3D { "mseteipnum", aia_any, NULL, NULL, rmw_xsetclre= inum }, + [CSR_MCLREIPNUM] =3D { "mclreipnum", aia_any, NULL, NULL, rmw_xsetclre= inum }, + [CSR_MSETEIENUM] =3D { "mseteienum", aia_any, NULL, NULL, rmw_xsetclre= inum }, + [CSR_MCLREIENUM] =3D { "mclreienum", aia_any, NULL, NULL, rmw_xsetclre= inum }, + [CSR_MTOPEI] =3D { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, + /* Virtual Interrupts for Supervisor Level (AIA) */ [CSR_MVIEN] =3D { "mvien", aia_any, read_zero, write_ignore }, [CSR_MVIP] =3D { "mvip", aia_any, read_zero, write_ignore }, @@ -2966,6 +3155,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* Supervisor-Level Interrupts (AIA) */ [CSR_STOPI] =3D { "stopi", aia_smode, read_stopi }, =20 + /* Supervisor-Level IMSIC Interface (AIA) */ + [CSR_SSETEIPNUM] =3D { "sseteipnum", aia_smode, NULL, NULL, rmw_xsetcl= reinum }, + [CSR_SCLREIPNUM] =3D { "sclreipnum", aia_smode, NULL, NULL, rmw_xsetcl= reinum }, + [CSR_SSETEIENUM] =3D { "sseteienum", aia_smode, NULL, NULL, rmw_xsetcl= reinum }, + [CSR_SCLREIENUM] =3D { "sclreienum", aia_smode, NULL, NULL, rmw_xsetcl= reinum }, + [CSR_STOPEI] =3D { "stopei", aia_smode, NULL, NULL, rmw_xtopei= }, + /* Supervisor-Level High-Half CSRs (AIA) */ [CSR_SIEH] =3D { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, [CSR_SIPH] =3D { "siph", aia_smode32, NULL, NULL, rmw_siph }, @@ -3013,6 +3209,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* VS-Level Interrupts (H-extension with AIA) */ [CSR_VSTOPI] =3D { "vstopi", aia_hmode, read_vstopi }, =20 + /* VS-Level IMSIC Interface (H-extension with AIA) */ + [CSR_VSSETEIPNUM] =3D { "vsseteipnum", aia_hmode, NULL, NULL, rmw_xset= clreinum }, + [CSR_VSCLREIPNUM] =3D { "vsclreipnum", aia_hmode, NULL, NULL, rmw_xset= clreinum }, + [CSR_VSSETEIENUM] =3D { "vsseteienum", aia_hmode, NULL, NULL, rmw_xset= clreinum }, + [CSR_VSCLREIENUM] =3D { "vsclreienum", aia_hmode, NULL, NULL, rmw_xset= clreinum }, + [CSR_VSTOPEI] =3D { "vstopei", aia_hmode, NULL, NULL, rmw_xtop= ei }, + /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ [CSR_HIDELEGH] =3D { "hidelegh", aia_hmode32, NULL, NULL, rmw_hi= delegh }, [CSR_HVIENH] =3D { "hvienh", aia_hmode32, read_zero, write_i= gnore }, --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645000672575969.5153848502921; Wed, 16 Feb 2022 00:37:52 -0800 (PST) Received: from localhost ([::1]:53354 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKFot-0000vB-In for importer@patchew.org; Wed, 16 Feb 2022 03:37:51 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49044) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDqm-0007H6-4D for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:31:40 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:61794) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDqk-0006rq-Dp for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:31:39 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:31:27 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:04:15 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:31:28 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7QR3vF7z1SVp1 for ; Tue, 15 Feb 2022 22:31:27 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id bfgVOLW-5ANm for ; Tue, 15 Feb 2022 22:31:27 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7QL5S3Tz1Rwrw; Tue, 15 Feb 2022 22:31:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993098; x=1676529098; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GMz1iGz8nSi3Q+ohYXo4qXkBQTK9cKb9Tg7NTM4YfTM=; b=Mo8MwZq33WNnuS6MLZCw5FgDNGuu1LAXpjdLU0Vy6DuY4R+krFBRRbTL CWevJI955q8FJXdr+g6cLv7AxyCUSIUKTclSKgQ2GCpI2USZkCFbR6reA Fne8fE4wQv6beGbFeYV8bWkygjr9CP2ez+oIYBJ9e4E2sX+IuEqqmLPq0 n4ENEGTlZ83qul4G6J87Ov3Wa+7gWN90INg6uaavA4xIrZ0Wgilna7sMD Xf3HdZOVjxlCstLOE8JQdJen85vVv9wprv8q3WYB0JLcy7MBLWcU4P6Kc iuYpuz6sODDhE30g81PYM3/D+i51DfKQistb0Emqw1rhRvWyJlOvLKzVC g==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="297181857" IronPort-SDR: 8rO1TZm0WpFIkqnxbWktIVFUHu9aNeDs1kbihVVarr7CL50wAZpHvYg4f1CbAujLcfhTWSktu8 WqxeEOOl7l2bi05jWBF36c0UQXi6vvy7LcJ2A2g6N3jDShjZWG5LgEUI9CFthctgWRlg7Y0BgC 29E1BqY4GLVTsOSwsxMsCKMbpGEodDuOEwIKGmK82COwX2nhE5v5HvqJiqr5L0Pf9QTW1aSiM1 ZSrMKxU5NUXAZd/EJPa5EiHlAlroDGEfyWLic3UliUy11LEPmq7jKqAjrpQX2ux+qwP+kscYjh kFteDK0rPowXcAucaGzO+bFy IronPort-SDR: E6/KL2ENdCaik8CQBWC4Cw0A9UUo7FcYqILamMFUngyZL690RoY+H9/6t+E7IQ10JvVK1GwZb7 5MkmhacjaThjjuUlY6YKKt5ovWn7iF/mrMiRd0D/UWLDio1tfeXfcwIf6e/iylFldO9u+SRhpF bAq0WvI1YEDbmbds9IFoPzKH9hlEWUTWyNWLM7pNWKTBSwEqKtstzpI11kSXxH3AfXdmkQr0ht RhlKZLcIoXGHl2vvGxQpVQpV6rq++wrF2gqOU2mB9No3EneZqLnAAcIrO5CempjAqj6ZPeG4DS vtM= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993087; x=1647585088; bh=GMz1iGz8nSi3Q+ohYX o4qXkBQTK9cKb9Tg7NTM4YfTM=; b=P2WBnR6DufmLu8oCednolZAiTDQvxTZP7G nMMMMvMJf2zU2zv3m4uLronzTOwXcCyPeOxeFoYYaqWhvssONa/dCUG4Ybcfa2w0 RTmTqnJbF1JmFvF2CziL0RX2z4bHY41T6akrlnRautgUlpKZObVwSsRyhtVansQT iUSuQCKqMfwo6k2jAISmZKqJBE9TnBHsSNl24y6jj0TGtSxftg83IovpsXLT3Pgm s3J8A5iJgrjtckaY9uxqxtZKmdvdIUrynAJhzNz6ifyWCJCNs/qui8EWCRmTVKYb mM4ViRP8CqfNJ8ks3adQsRVUIUItCTk1W9Wf4C7FXZxEneeIlfLg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anup Patel , Anup Patel , Alistair Francis , Frank Chang Subject: [PULL v2 27/35] hw/riscv: virt: Use AIA INTC compatible string when available Date: Wed, 16 Feb 2022 16:29:04 +1000 Message-Id: <20220216062912.319738-28-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1645000674545100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel We should use the AIA INTC compatible string in the CPU INTC DT nodes when the CPUs support AIA feature. This will allow Linux INTC driver to use AIA local interrupt CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Message-id: 20220204174700.534953-17-anup@brainfault.org Signed-off-by: Alistair Francis --- hw/riscv/virt.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 2643c8bc37..e3068d6126 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -212,8 +212,17 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, = int socket, qemu_fdt_add_subnode(mc->fdt, intc_name); qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle", intc_phandles[cpu]); - qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", - "riscv,cpu-intc"); + if (riscv_feature(&s->soc[socket].harts[cpu].env, + RISCV_FEATURE_AIA)) { + static const char * const compat[2] =3D { + "riscv,cpu-intc-aia", "riscv,cpu-intc" + }; + qemu_fdt_setprop_string_array(mc->fdt, intc_name, "compatible", + (char **)&compat, ARRAY_SIZE(compat)= ); + } else { + qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", + "riscv,cpu-intc"); + } qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL,= 0); qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1); =20 --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645000392490742.0985245344549; Wed, 16 Feb 2022 00:33:12 -0800 (PST) Received: from localhost ([::1]:46288 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKFkN-0004Wb-5E for importer@patchew.org; Wed, 16 Feb 2022 03:33:11 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49046) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDqm-0007H7-7C for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:31:40 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:61797) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDqk-0006rz-Dp for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:31:39 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:31:32 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:04:20 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:31:33 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7QX3BX1z1SVp0 for ; Tue, 15 Feb 2022 22:31:32 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id LeHf3IYgQqxd for ; Tue, 15 Feb 2022 22:31:32 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7QR6sj1z1Rwrw; Tue, 15 Feb 2022 22:31:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993098; x=1676529098; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5vRYbIbePo4KYXoM1wvOSBCxKj+8Dktw8/euqWyCoA0=; b=Ir7itmKY4594hpzytEFtIAvrGDB/1dRMQzsq4FmKQKKgyOxg7IOAKOYI gRHlC8Msrvbc1xsd1keUaRJM4u9xhY0oVVUSh/hTIJalhZdbkGn5+E7Kj PURjZ9eL3X0zWSv8UVc7rZ99H8Mtd8svqkYN4l0HJbC7O+okcJiz/wzf+ S+ppH4P72L0M2bKkzZtsz/CpabDv9wmYndEtGyQWOpzZ+QM99B9R0bd4e lBl3xuDEALBSqMxWhg0RJdiEPPhbJtpNlQG+mCoObjCrYfpgpfBh83tQv Nxb8Aidh1kU1WloIzbbweDmuRWR6ePYIGr5Tswk5n4v1UcvflYXn7+FYG w==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="297181863" IronPort-SDR: q9d7pNnZX+E77vSmrzfNXByIjTT30J00enmlh/7H7bxUAtw0cdGtoVL8By6rjvehlNyXw6JsyO Ha/UrRoxAcBrsS7YuvadYVR1L3OQJWnXfKj+zZ0owXLSDN41a0qeOfyMVRUsJhl6mkEiZvqonI faojrIEWonnkM/oGv0MxJ8ZtbMuRYXBbL7iTixYVW7lRGYfziO1qjKuGs34bkCOAeF6Y6rJJlE Jty8y8fEm9sg0/rwMfDxvM3whi58sKEQxLm8DPfHfVGwNUUoYmyUj2bKZg2aYO8cyYfLdi51K/ N7XrubPTmQZRHgSnC4OHfLfH IronPort-SDR: uMATEU3eEHUQWx9hNNO3NGMip4HNwGImM5BcpKqUgPX/6ksDAf5HIAtyoEzFbsTCgzzl9wzIij DHqUnfgwcw53db9Lq42Q54pLxzGdc7+0iiyEq+qFwCLeQCwZBzWXIKhziIxqo7pRNb/zUGQpsS MZCtE+mpN7u94Y7Qn7SH2tT+he7ybwk5nSMcGYTqS4xXBHAdsqwph738LgEdK3lTVOsVml94WH YG2OoNd4tbf8X5yg7BqDjQSuQt4Y+NjitYUxVUgFb66xtrzSZtM8YrAfmeplrUWdVoiTHURc81 aU4= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993092; x=1647585093; bh=5vRYbIbePo4KYXoM1w vOSBCxKj+8Dktw8/euqWyCoA0=; b=XuQtDWv8tX2iOcxCuDvpdS7Tkt61KhmJc7 ttUSQAaKMIdyWC93rJdmV43jLCJjs1Zbnwz1ccyYSuhAnTyyXxCXrAd1GCgKUVDN eMfbjYue6zBdM/glk8sTfdYxm0PQ3UB8nEHK/psKM4oefxZ/yAoGFVxM7WWvGJAE xZC+w+giLIx10LWkRsLgWtjU3QjlHWsvK00JK3/25QDrVOsSdYR/NJSxzoY/6XpS 3HD5p4jVhme0kaAa0zZOPHeQeYij9OXLgKde/9U97rSqyDaO9bY8TjwUzcTaRiaF 6fV4coEn7X6j4jTD11XpyY+EcsfUt1tHCMCu4fBNLgj0VF7GvH2Q== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anup Patel , Anup Patel , Alistair Francis , Frank Chang Subject: [PULL v2 28/35] target/riscv: Allow users to force enable AIA CSRs in HART Date: Wed, 16 Feb 2022 16:29:05 +1000 Message-Id: <20220216062912.319738-29-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1645000394377100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel We add "x-aia" command-line option for RISC-V HART using which allows users to force enable CPU AIA CSRs without changing the interrupt controller available in RISC-V machine. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Message-id: 20220204174700.534953-18-anup@brainfault.org Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c70de10c85..7ecb1387dd 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -376,6 +376,7 @@ struct RISCVCPUConfig { bool mmu; bool pmp; bool epmp; + bool aia; uint64_t resetvec; }; =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5fb0a61036..9dce57a380 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -537,6 +537,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) } } =20 + if (cpu->cfg.aia) { + riscv_set_feature(env, RISCV_FEATURE_AIA); + } + set_resetvec(env, cpu->cfg.resetvec); =20 /* Validate that MISA_MXL is set properly. */ @@ -782,6 +786,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), /* ePMP 0.9.3 */ DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), + DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false), =20 DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), DEFINE_PROP_END_OF_LIST(), --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164500094196272.41396301147302; Wed, 16 Feb 2022 00:42:21 -0800 (PST) Received: from localhost ([::1]:33286 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKFtG-0006hD-13 for importer@patchew.org; Wed, 16 Feb 2022 03:42:22 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49082) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDqs-0007Ih-JC for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:31:47 -0500 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:31690) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDqo-0006sh-36 for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:31:46 -0500 Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:31:40 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:03:20 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:31:40 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7Qh0tH1z1SVp0 for ; Tue, 15 Feb 2022 22:31:40 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id BC68kJQ7DlZN for ; Tue, 15 Feb 2022 22:31:37 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7QX6QPdz1Rwrw; Tue, 15 Feb 2022 22:31:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993102; x=1676529102; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EiyvgfbagJ6HRNgqUAOH8zrdTRnY4SzBgJ0HFiL3b7o=; b=WbFGsZS+O5goUZ6kRjjC4SR/0xmo9jld4TO+Pmsv/tkgIRF00swi26lu QshFZCVOaF9yrOYzmoNFmd2FJBqn7iIHF5JHXevM5cZaUXAUmOPlxYlvD N7dDWc0pxFrzGDUWpggaY2p90rF+ZLrlSonEPuXiJZymkjFvYF6MHXflX AzP1++mviw/xenG/f1mbnFB7aTVpopl2Tx0j9Im4wD1Ee9n5JecOEdsjJ IU0xW6DJZXaeCNAyZKZLDDm861ylzd8VSw40NY9ueT1Y/ooy/w9lKSZ8U Yvk9m9sciqZZYI7WQTKoPk3CW0/+q5WD9Xe+UgprYCYrsFxILdhsDBGkH g==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="304974648" IronPort-SDR: k0FhRUukTsbYShRE9iRFYkvYjtwePLDd60Q5Mm8vBy6uBvww6bPRachJOCnjE9k+08efWHgIV8 91Wfe6umKUjPt0A5Ldpgjb8EOuixiBe+B3MrAgvGyejku3xgmcfNeLVy37VMqFiM0VAM9UHjsd m8IuTdxDwOVLaqYmqrXKNW8t6YGcV3gY6NrMUyeOgv5sEtlX0OngyNoA9cMg9ezMnM95aVleNn JBBmo3FDEDfFJVP9L+gzfHQAfQ4sRzm7FBTxs8q8IeZWsziqvtAJqIG7CHAfos3X4E4x61Q605 HpC9NMtAlbFbaE60y7pkQZHe IronPort-SDR: 76513R7Jm07WFuVmauOOQ04Ck2X4k9pzdNpYhyHUIn6YKOdXTvh+16xXdwCyDVW84aJTdtweNI WtPP51Hd6x3unxGliDTVqtLE2HxaZ0RFnNmrzFVc6afyBEh/xcQ+EZcUYhH0da6IZSxct3Kh9T 5/s2kJWf7GLs3RW4bqBYfYadjb3Na+KiZPLKGHJVq1bZBBZnJWyJlFO5jmjq2v2IiMDaD9PEyM 9qLsNesjoQVk1zsuBK0brXwpqORIllcIQYWyZF1YYjxiRt92L5B7AxaLo7LpOI8r2HKC7gl7/Z 2r0= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993097; x=1647585098; bh=EiyvgfbagJ6HRNgqUA OH8zrdTRnY4SzBgJ0HFiL3b7o=; b=esMzKMqNW2yPDY4vjhxORGSb8YAINsofGi h2Fh3yL/E6NR1H27faUY3H0UhdmJkMupdyriBOBDm47GebL5xjRoVgMZY83yDrbb 99KGZK7FI3EqIDwjXd3L5nsDp+H8ONpa2uTH3fFp7AmntDCuHb4xrzkA5tjPlqa/ Ak4fm/aBHf74FG2sv+jQuApGkKPbPO6lYU7J5FC22WAy4yWdCEl2B9eWexCb8ibn OOaY+/A4BRFFcyi/i9Ygjj9DhGLW5Sl2oAZTgJyFtvxoCz9UMfLzp4eeJloz8jR9 V790OcUK3K5yYG2RZn3gE/eopRovq60NcpWoZmaGSk8+6sVXEPMw== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anup Patel , Anup Patel , Frank Chang , Alistair Francis Subject: [PULL v2 29/35] hw/intc: Add RISC-V AIA APLIC device emulation Date: Wed, 16 Feb 2022 16:29:06 +1000 Message-Id: <20220216062912.319738-30-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1645000968931100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel The RISC-V AIA (Advanced Interrupt Architecture) defines a new interrupt controller for wired interrupts called APLIC (Advanced Platform Level Interrupt Controller). The APLIC is capabable of forwarding wired interupts to RISC-V HARTs directly or as MSIs (Message Signaled Interupts). This patch adds device emulation for RISC-V AIA APLIC. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Frank Chang Message-id: 20220204174700.534953-19-anup@brainfault.org Signed-off-by: Alistair Francis --- include/hw/intc/riscv_aplic.h | 79 +++ hw/intc/riscv_aplic.c | 978 ++++++++++++++++++++++++++++++++++ hw/intc/Kconfig | 3 + hw/intc/meson.build | 1 + 4 files changed, 1061 insertions(+) create mode 100644 include/hw/intc/riscv_aplic.h create mode 100644 hw/intc/riscv_aplic.c diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h new file mode 100644 index 0000000000..de8532fbc3 --- /dev/null +++ b/include/hw/intc/riscv_aplic.h @@ -0,0 +1,79 @@ +/* + * RISC-V APLIC (Advanced Platform Level Interrupt Controller) interface + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef HW_RISCV_APLIC_H +#define HW_RISCV_APLIC_H + +#include "hw/sysbus.h" +#include "qom/object.h" + +#define TYPE_RISCV_APLIC "riscv.aplic" + +typedef struct RISCVAPLICState RISCVAPLICState; +DECLARE_INSTANCE_CHECKER(RISCVAPLICState, RISCV_APLIC, TYPE_RISCV_APLIC) + +#define APLIC_MIN_SIZE 0x4000 +#define APLIC_SIZE_ALIGN(__x) (((__x) + (APLIC_MIN_SIZE - 1)) & \ + ~(APLIC_MIN_SIZE - 1)) +#define APLIC_SIZE(__num_harts) (APLIC_MIN_SIZE + \ + APLIC_SIZE_ALIGN(32 * (__num_harts))) + +struct RISCVAPLICState { + /*< private >*/ + SysBusDevice parent_obj; + qemu_irq *external_irqs; + + /*< public >*/ + MemoryRegion mmio; + uint32_t bitfield_words; + uint32_t domaincfg; + uint32_t mmsicfgaddr; + uint32_t mmsicfgaddrH; + uint32_t smsicfgaddr; + uint32_t smsicfgaddrH; + uint32_t genmsi; + uint32_t *sourcecfg; + uint32_t *state; + uint32_t *target; + uint32_t *idelivery; + uint32_t *iforce; + uint32_t *ithreshold; + + /* topology */ +#define QEMU_APLIC_MAX_CHILDREN 16 + struct RISCVAPLICState *parent; + struct RISCVAPLICState *children[QEMU_APLIC_MAX_CHILDREN]; + uint16_t num_children; + + /* config */ + uint32_t aperture_size; + uint32_t hartid_base; + uint32_t num_harts; + uint32_t iprio_mask; + uint32_t num_irqs; + bool msimode; + bool mmode; +}; + +void riscv_aplic_add_child(DeviceState *parent, DeviceState *child); + +DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size, + uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources, + uint32_t iprio_bits, bool msimode, bool mmode, DeviceState *parent); + +#endif diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c new file mode 100644 index 0000000000..e7809fb6b2 --- /dev/null +++ b/hw/intc/riscv_aplic.c @@ -0,0 +1,978 @@ +/* + * RISC-V APLIC (Advanced Platform Level Interrupt Controller) + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/error-report.h" +#include "qemu/bswap.h" +#include "exec/address-spaces.h" +#include "hw/sysbus.h" +#include "hw/pci/msi.h" +#include "hw/boards.h" +#include "hw/qdev-properties.h" +#include "hw/intc/riscv_aplic.h" +#include "hw/irq.h" +#include "target/riscv/cpu.h" +#include "sysemu/sysemu.h" +#include "migration/vmstate.h" + +#define APLIC_MAX_IDC (1UL << 14) +#define APLIC_MAX_SOURCE 1024 +#define APLIC_MIN_IPRIO_BITS 1 +#define APLIC_MAX_IPRIO_BITS 8 +#define APLIC_MAX_CHILDREN 1024 + +#define APLIC_DOMAINCFG 0x0000 +#define APLIC_DOMAINCFG_RDONLY 0x80000000 +#define APLIC_DOMAINCFG_IE (1 << 8) +#define APLIC_DOMAINCFG_DM (1 << 2) +#define APLIC_DOMAINCFG_BE (1 << 0) + +#define APLIC_SOURCECFG_BASE 0x0004 +#define APLIC_SOURCECFG_D (1 << 10) +#define APLIC_SOURCECFG_CHILDIDX_MASK 0x000003ff +#define APLIC_SOURCECFG_SM_MASK 0x00000007 +#define APLIC_SOURCECFG_SM_INACTIVE 0x0 +#define APLIC_SOURCECFG_SM_DETACH 0x1 +#define APLIC_SOURCECFG_SM_EDGE_RISE 0x4 +#define APLIC_SOURCECFG_SM_EDGE_FALL 0x5 +#define APLIC_SOURCECFG_SM_LEVEL_HIGH 0x6 +#define APLIC_SOURCECFG_SM_LEVEL_LOW 0x7 + +#define APLIC_MMSICFGADDR 0x1bc0 +#define APLIC_MMSICFGADDRH 0x1bc4 +#define APLIC_SMSICFGADDR 0x1bc8 +#define APLIC_SMSICFGADDRH 0x1bcc + +#define APLIC_xMSICFGADDRH_L (1UL << 31) +#define APLIC_xMSICFGADDRH_HHXS_MASK 0x1f +#define APLIC_xMSICFGADDRH_HHXS_SHIFT 24 +#define APLIC_xMSICFGADDRH_LHXS_MASK 0x7 +#define APLIC_xMSICFGADDRH_LHXS_SHIFT 20 +#define APLIC_xMSICFGADDRH_HHXW_MASK 0x7 +#define APLIC_xMSICFGADDRH_HHXW_SHIFT 16 +#define APLIC_xMSICFGADDRH_LHXW_MASK 0xf +#define APLIC_xMSICFGADDRH_LHXW_SHIFT 12 +#define APLIC_xMSICFGADDRH_BAPPN_MASK 0xfff + +#define APLIC_xMSICFGADDR_PPN_SHIFT 12 + +#define APLIC_xMSICFGADDR_PPN_HART(__lhxs) \ + ((1UL << (__lhxs)) - 1) + +#define APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) \ + ((1UL << (__lhxw)) - 1) +#define APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs) \ + ((__lhxs)) +#define APLIC_xMSICFGADDR_PPN_LHX(__lhxw, __lhxs) \ + (APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) << \ + APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs)) + +#define APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) \ + ((1UL << (__hhxw)) - 1) +#define APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs) \ + ((__hhxs) + APLIC_xMSICFGADDR_PPN_SHIFT) +#define APLIC_xMSICFGADDR_PPN_HHX(__hhxw, __hhxs) \ + (APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) << \ + APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs)) + +#define APLIC_xMSICFGADDRH_VALID_MASK \ + (APLIC_xMSICFGADDRH_L | \ + (APLIC_xMSICFGADDRH_HHXS_MASK << APLIC_xMSICFGADDRH_HHXS_SHIFT) | \ + (APLIC_xMSICFGADDRH_LHXS_MASK << APLIC_xMSICFGADDRH_LHXS_SHIFT) | \ + (APLIC_xMSICFGADDRH_HHXW_MASK << APLIC_xMSICFGADDRH_HHXW_SHIFT) | \ + (APLIC_xMSICFGADDRH_LHXW_MASK << APLIC_xMSICFGADDRH_LHXW_SHIFT) | \ + APLIC_xMSICFGADDRH_BAPPN_MASK) + +#define APLIC_SETIP_BASE 0x1c00 +#define APLIC_SETIPNUM 0x1cdc + +#define APLIC_CLRIP_BASE 0x1d00 +#define APLIC_CLRIPNUM 0x1ddc + +#define APLIC_SETIE_BASE 0x1e00 +#define APLIC_SETIENUM 0x1edc + +#define APLIC_CLRIE_BASE 0x1f00 +#define APLIC_CLRIENUM 0x1fdc + +#define APLIC_SETIPNUM_LE 0x2000 +#define APLIC_SETIPNUM_BE 0x2004 + +#define APLIC_ISTATE_PENDING (1U << 0) +#define APLIC_ISTATE_ENABLED (1U << 1) +#define APLIC_ISTATE_ENPEND (APLIC_ISTATE_ENABLED | \ + APLIC_ISTATE_PENDING) +#define APLIC_ISTATE_INPUT (1U << 8) + +#define APLIC_GENMSI 0x3000 + +#define APLIC_TARGET_BASE 0x3004 +#define APLIC_TARGET_HART_IDX_SHIFT 18 +#define APLIC_TARGET_HART_IDX_MASK 0x3fff +#define APLIC_TARGET_GUEST_IDX_SHIFT 12 +#define APLIC_TARGET_GUEST_IDX_MASK 0x3f +#define APLIC_TARGET_IPRIO_MASK 0xff +#define APLIC_TARGET_EIID_MASK 0x7ff + +#define APLIC_IDC_BASE 0x4000 +#define APLIC_IDC_SIZE 32 + +#define APLIC_IDC_IDELIVERY 0x00 + +#define APLIC_IDC_IFORCE 0x04 + +#define APLIC_IDC_ITHRESHOLD 0x08 + +#define APLIC_IDC_TOPI 0x18 +#define APLIC_IDC_TOPI_ID_SHIFT 16 +#define APLIC_IDC_TOPI_ID_MASK 0x3ff +#define APLIC_IDC_TOPI_PRIO_MASK 0xff + +#define APLIC_IDC_CLAIMI 0x1c + +static uint32_t riscv_aplic_read_input_word(RISCVAPLICState *aplic, + uint32_t word) +{ + uint32_t i, irq, ret =3D 0; + + for (i =3D 0; i < 32; i++) { + irq =3D word * 32 + i; + if (!irq || aplic->num_irqs <=3D irq) { + continue; + } + + ret |=3D ((aplic->state[irq] & APLIC_ISTATE_INPUT) ? 1 : 0) << i; + } + + return ret; +} + +static uint32_t riscv_aplic_read_pending_word(RISCVAPLICState *aplic, + uint32_t word) +{ + uint32_t i, irq, ret =3D 0; + + for (i =3D 0; i < 32; i++) { + irq =3D word * 32 + i; + if (!irq || aplic->num_irqs <=3D irq) { + continue; + } + + ret |=3D ((aplic->state[irq] & APLIC_ISTATE_PENDING) ? 1 : 0) << i; + } + + return ret; +} + +static void riscv_aplic_set_pending_raw(RISCVAPLICState *aplic, + uint32_t irq, bool pending) +{ + if (pending) { + aplic->state[irq] |=3D APLIC_ISTATE_PENDING; + } else { + aplic->state[irq] &=3D ~APLIC_ISTATE_PENDING; + } +} + +static void riscv_aplic_set_pending(RISCVAPLICState *aplic, + uint32_t irq, bool pending) +{ + uint32_t sourcecfg, sm; + + if ((irq <=3D 0) || (aplic->num_irqs <=3D irq)) { + return; + } + + sourcecfg =3D aplic->sourcecfg[irq]; + if (sourcecfg & APLIC_SOURCECFG_D) { + return; + } + + sm =3D sourcecfg & APLIC_SOURCECFG_SM_MASK; + if ((sm =3D=3D APLIC_SOURCECFG_SM_INACTIVE) || + ((!aplic->msimode || (aplic->msimode && !pending)) && + ((sm =3D=3D APLIC_SOURCECFG_SM_LEVEL_HIGH) || + (sm =3D=3D APLIC_SOURCECFG_SM_LEVEL_LOW)))) { + return; + } + + riscv_aplic_set_pending_raw(aplic, irq, pending); +} + +static void riscv_aplic_set_pending_word(RISCVAPLICState *aplic, + uint32_t word, uint32_t value, + bool pending) +{ + uint32_t i, irq; + + for (i =3D 0; i < 32; i++) { + irq =3D word * 32 + i; + if (!irq || aplic->num_irqs <=3D irq) { + continue; + } + + if (value & (1U << i)) { + riscv_aplic_set_pending(aplic, irq, pending); + } + } +} + +static uint32_t riscv_aplic_read_enabled_word(RISCVAPLICState *aplic, + int word) +{ + uint32_t i, irq, ret =3D 0; + + for (i =3D 0; i < 32; i++) { + irq =3D word * 32 + i; + if (!irq || aplic->num_irqs <=3D irq) { + continue; + } + + ret |=3D ((aplic->state[irq] & APLIC_ISTATE_ENABLED) ? 1 : 0) << i; + } + + return ret; +} + +static void riscv_aplic_set_enabled_raw(RISCVAPLICState *aplic, + uint32_t irq, bool enabled) +{ + if (enabled) { + aplic->state[irq] |=3D APLIC_ISTATE_ENABLED; + } else { + aplic->state[irq] &=3D ~APLIC_ISTATE_ENABLED; + } +} + +static void riscv_aplic_set_enabled(RISCVAPLICState *aplic, + uint32_t irq, bool enabled) +{ + uint32_t sourcecfg, sm; + + if ((irq <=3D 0) || (aplic->num_irqs <=3D irq)) { + return; + } + + sourcecfg =3D aplic->sourcecfg[irq]; + if (sourcecfg & APLIC_SOURCECFG_D) { + return; + } + + sm =3D sourcecfg & APLIC_SOURCECFG_SM_MASK; + if (sm =3D=3D APLIC_SOURCECFG_SM_INACTIVE) { + return; + } + + riscv_aplic_set_enabled_raw(aplic, irq, enabled); +} + +static void riscv_aplic_set_enabled_word(RISCVAPLICState *aplic, + uint32_t word, uint32_t value, + bool enabled) +{ + uint32_t i, irq; + + for (i =3D 0; i < 32; i++) { + irq =3D word * 32 + i; + if (!irq || aplic->num_irqs <=3D irq) { + continue; + } + + if (value & (1U << i)) { + riscv_aplic_set_enabled(aplic, irq, enabled); + } + } +} + +static void riscv_aplic_msi_send(RISCVAPLICState *aplic, + uint32_t hart_idx, uint32_t guest_idx, + uint32_t eiid) +{ + uint64_t addr; + MemTxResult result; + RISCVAPLICState *aplic_m; + uint32_t lhxs, lhxw, hhxs, hhxw, group_idx, msicfgaddr, msicfgaddrH; + + aplic_m =3D aplic; + while (aplic_m && !aplic_m->mmode) { + aplic_m =3D aplic_m->parent; + } + if (!aplic_m) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: m-level APLIC not found\n", + __func__); + return; + } + + if (aplic->mmode) { + msicfgaddr =3D aplic_m->mmsicfgaddr; + msicfgaddrH =3D aplic_m->mmsicfgaddrH; + } else { + msicfgaddr =3D aplic_m->smsicfgaddr; + msicfgaddrH =3D aplic_m->smsicfgaddrH; + } + + lhxs =3D (msicfgaddrH >> APLIC_xMSICFGADDRH_LHXS_SHIFT) & + APLIC_xMSICFGADDRH_LHXS_MASK; + lhxw =3D (msicfgaddrH >> APLIC_xMSICFGADDRH_LHXW_SHIFT) & + APLIC_xMSICFGADDRH_LHXW_MASK; + hhxs =3D (msicfgaddrH >> APLIC_xMSICFGADDRH_HHXS_SHIFT) & + APLIC_xMSICFGADDRH_HHXS_MASK; + hhxw =3D (msicfgaddrH >> APLIC_xMSICFGADDRH_HHXW_SHIFT) & + APLIC_xMSICFGADDRH_HHXW_MASK; + + group_idx =3D hart_idx >> lhxw; + hart_idx &=3D APLIC_xMSICFGADDR_PPN_LHX_MASK(lhxw); + + addr =3D msicfgaddr; + addr |=3D ((uint64_t)(msicfgaddrH & APLIC_xMSICFGADDRH_BAPPN_MASK)) <<= 32; + addr |=3D ((uint64_t)(group_idx & APLIC_xMSICFGADDR_PPN_HHX_MASK(hhxw)= )) << + APLIC_xMSICFGADDR_PPN_HHX_SHIFT(hhxs); + addr |=3D ((uint64_t)(hart_idx & APLIC_xMSICFGADDR_PPN_LHX_MASK(lhxw))= ) << + APLIC_xMSICFGADDR_PPN_LHX_SHIFT(lhxs); + addr |=3D (uint64_t)(guest_idx & APLIC_xMSICFGADDR_PPN_HART(lhxs)); + addr <<=3D APLIC_xMSICFGADDR_PPN_SHIFT; + + address_space_stl_le(&address_space_memory, addr, + eiid, MEMTXATTRS_UNSPECIFIED, &result); + if (result !=3D MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: MSI write failed for " + "hart_index=3D%d guest_index=3D%d eiid=3D%d\n", + __func__, hart_idx, guest_idx, eiid); + } +} + +static void riscv_aplic_msi_irq_update(RISCVAPLICState *aplic, uint32_t ir= q) +{ + uint32_t hart_idx, guest_idx, eiid; + + if (!aplic->msimode || (aplic->num_irqs <=3D irq) || + !(aplic->domaincfg & APLIC_DOMAINCFG_IE)) { + return; + } + + if ((aplic->state[irq] & APLIC_ISTATE_ENPEND) !=3D APLIC_ISTATE_ENPEND= ) { + return; + } + + riscv_aplic_set_pending_raw(aplic, irq, false); + + hart_idx =3D aplic->target[irq] >> APLIC_TARGET_HART_IDX_SHIFT; + hart_idx &=3D APLIC_TARGET_HART_IDX_MASK; + if (aplic->mmode) { + /* M-level APLIC ignores guest_index */ + guest_idx =3D 0; + } else { + guest_idx =3D aplic->target[irq] >> APLIC_TARGET_GUEST_IDX_SHIFT; + guest_idx &=3D APLIC_TARGET_GUEST_IDX_MASK; + } + eiid =3D aplic->target[irq] & APLIC_TARGET_EIID_MASK; + riscv_aplic_msi_send(aplic, hart_idx, guest_idx, eiid); +} + +static uint32_t riscv_aplic_idc_topi(RISCVAPLICState *aplic, uint32_t idc) +{ + uint32_t best_irq, best_iprio; + uint32_t irq, iprio, ihartidx, ithres; + + if (aplic->num_harts <=3D idc) { + return 0; + } + + ithres =3D aplic->ithreshold[idc]; + best_irq =3D best_iprio =3D UINT32_MAX; + for (irq =3D 1; irq < aplic->num_irqs; irq++) { + if ((aplic->state[irq] & APLIC_ISTATE_ENPEND) !=3D + APLIC_ISTATE_ENPEND) { + continue; + } + + ihartidx =3D aplic->target[irq] >> APLIC_TARGET_HART_IDX_SHIFT; + ihartidx &=3D APLIC_TARGET_HART_IDX_MASK; + if (ihartidx !=3D idc) { + continue; + } + + iprio =3D aplic->target[irq] & aplic->iprio_mask; + if (ithres && iprio >=3D ithres) { + continue; + } + + if (iprio < best_iprio) { + best_irq =3D irq; + best_iprio =3D iprio; + } + } + + if (best_irq < aplic->num_irqs && best_iprio <=3D aplic->iprio_mask) { + return (best_irq << APLIC_IDC_TOPI_ID_SHIFT) | best_iprio; + } + + return 0; +} + +static void riscv_aplic_idc_update(RISCVAPLICState *aplic, uint32_t idc) +{ + uint32_t topi; + + if (aplic->msimode || aplic->num_harts <=3D idc) { + return; + } + + topi =3D riscv_aplic_idc_topi(aplic, idc); + if ((aplic->domaincfg & APLIC_DOMAINCFG_IE) && + aplic->idelivery[idc] && + (aplic->iforce[idc] || topi)) { + qemu_irq_raise(aplic->external_irqs[idc]); + } else { + qemu_irq_lower(aplic->external_irqs[idc]); + } +} + +static uint32_t riscv_aplic_idc_claimi(RISCVAPLICState *aplic, uint32_t id= c) +{ + uint32_t irq, state, sm, topi =3D riscv_aplic_idc_topi(aplic, idc); + + if (!topi) { + aplic->iforce[idc] =3D 0; + return 0; + } + + irq =3D (topi >> APLIC_IDC_TOPI_ID_SHIFT) & APLIC_IDC_TOPI_ID_MASK; + sm =3D aplic->sourcecfg[irq] & APLIC_SOURCECFG_SM_MASK; + state =3D aplic->state[irq]; + riscv_aplic_set_pending_raw(aplic, irq, false); + if ((sm =3D=3D APLIC_SOURCECFG_SM_LEVEL_HIGH) && + (state & APLIC_ISTATE_INPUT)) { + riscv_aplic_set_pending_raw(aplic, irq, true); + } else if ((sm =3D=3D APLIC_SOURCECFG_SM_LEVEL_LOW) && + !(state & APLIC_ISTATE_INPUT)) { + riscv_aplic_set_pending_raw(aplic, irq, true); + } + riscv_aplic_idc_update(aplic, idc); + + return topi; +} + +static void riscv_aplic_request(void *opaque, int irq, int level) +{ + bool update =3D false; + RISCVAPLICState *aplic =3D opaque; + uint32_t sourcecfg, childidx, state, idc; + + assert((0 < irq) && (irq < aplic->num_irqs)); + + sourcecfg =3D aplic->sourcecfg[irq]; + if (sourcecfg & APLIC_SOURCECFG_D) { + childidx =3D sourcecfg & APLIC_SOURCECFG_CHILDIDX_MASK; + if (childidx < aplic->num_children) { + riscv_aplic_request(aplic->children[childidx], irq, level); + } + return; + } + + state =3D aplic->state[irq]; + switch (sourcecfg & APLIC_SOURCECFG_SM_MASK) { + case APLIC_SOURCECFG_SM_EDGE_RISE: + if ((level > 0) && !(state & APLIC_ISTATE_INPUT) && + !(state & APLIC_ISTATE_PENDING)) { + riscv_aplic_set_pending_raw(aplic, irq, true); + update =3D true; + } + break; + case APLIC_SOURCECFG_SM_EDGE_FALL: + if ((level <=3D 0) && (state & APLIC_ISTATE_INPUT) && + !(state & APLIC_ISTATE_PENDING)) { + riscv_aplic_set_pending_raw(aplic, irq, true); + update =3D true; + } + break; + case APLIC_SOURCECFG_SM_LEVEL_HIGH: + if ((level > 0) && !(state & APLIC_ISTATE_PENDING)) { + riscv_aplic_set_pending_raw(aplic, irq, true); + update =3D true; + } + break; + case APLIC_SOURCECFG_SM_LEVEL_LOW: + if ((level <=3D 0) && !(state & APLIC_ISTATE_PENDING)) { + riscv_aplic_set_pending_raw(aplic, irq, true); + update =3D true; + } + break; + default: + break; + } + + if (level <=3D 0) { + aplic->state[irq] &=3D ~APLIC_ISTATE_INPUT; + } else { + aplic->state[irq] |=3D APLIC_ISTATE_INPUT; + } + + if (update) { + if (aplic->msimode) { + riscv_aplic_msi_irq_update(aplic, irq); + } else { + idc =3D aplic->target[irq] >> APLIC_TARGET_HART_IDX_SHIFT; + idc &=3D APLIC_TARGET_HART_IDX_MASK; + riscv_aplic_idc_update(aplic, idc); + } + } +} + +static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size) +{ + uint32_t irq, word, idc; + RISCVAPLICState *aplic =3D opaque; + + /* Reads must be 4 byte words */ + if ((addr & 0x3) !=3D 0) { + goto err; + } + + if (addr =3D=3D APLIC_DOMAINCFG) { + return APLIC_DOMAINCFG_RDONLY | aplic->domaincfg | + (aplic->msimode ? APLIC_DOMAINCFG_DM : 0); + } else if ((APLIC_SOURCECFG_BASE <=3D addr) && + (addr < (APLIC_SOURCECFG_BASE + (aplic->num_irqs - 1) * 4))) { + irq =3D ((addr - APLIC_SOURCECFG_BASE) >> 2) + 1; + return aplic->sourcecfg[irq]; + } else if (aplic->mmode && aplic->msimode && + (addr =3D=3D APLIC_MMSICFGADDR)) { + return aplic->mmsicfgaddr; + } else if (aplic->mmode && aplic->msimode && + (addr =3D=3D APLIC_MMSICFGADDRH)) { + return aplic->mmsicfgaddrH; + } else if (aplic->mmode && aplic->msimode && + (addr =3D=3D APLIC_SMSICFGADDR)) { + /* + * Registers SMSICFGADDR and SMSICFGADDRH are implemented only if: + * (a) the interrupt domain is at machine level + * (b) the domain's harts implement supervisor mode + * (c) the domain has one or more child supervisor-level domains + * that support MSI delivery mode (domaincfg.DM is not read- + * only zero in at least one of the supervisor-level child + * domains). + */ + return (aplic->num_children) ? aplic->smsicfgaddr : 0; + } else if (aplic->mmode && aplic->msimode && + (addr =3D=3D APLIC_SMSICFGADDRH)) { + return (aplic->num_children) ? aplic->smsicfgaddrH : 0; + } else if ((APLIC_SETIP_BASE <=3D addr) && + (addr < (APLIC_SETIP_BASE + aplic->bitfield_words * 4))) { + word =3D (addr - APLIC_SETIP_BASE) >> 2; + return riscv_aplic_read_pending_word(aplic, word); + } else if (addr =3D=3D APLIC_SETIPNUM) { + return 0; + } else if ((APLIC_CLRIP_BASE <=3D addr) && + (addr < (APLIC_CLRIP_BASE + aplic->bitfield_words * 4))) { + word =3D (addr - APLIC_CLRIP_BASE) >> 2; + return riscv_aplic_read_input_word(aplic, word); + } else if (addr =3D=3D APLIC_CLRIPNUM) { + return 0; + } else if ((APLIC_SETIE_BASE <=3D addr) && + (addr < (APLIC_SETIE_BASE + aplic->bitfield_words * 4))) { + word =3D (addr - APLIC_SETIE_BASE) >> 2; + return riscv_aplic_read_enabled_word(aplic, word); + } else if (addr =3D=3D APLIC_SETIENUM) { + return 0; + } else if ((APLIC_CLRIE_BASE <=3D addr) && + (addr < (APLIC_CLRIE_BASE + aplic->bitfield_words * 4))) { + return 0; + } else if (addr =3D=3D APLIC_CLRIENUM) { + return 0; + } else if (addr =3D=3D APLIC_SETIPNUM_LE) { + return 0; + } else if (addr =3D=3D APLIC_SETIPNUM_BE) { + return 0; + } else if (addr =3D=3D APLIC_GENMSI) { + return (aplic->msimode) ? aplic->genmsi : 0; + } else if ((APLIC_TARGET_BASE <=3D addr) && + (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) { + irq =3D ((addr - APLIC_TARGET_BASE) >> 2) + 1; + return aplic->target[irq]; + } else if (!aplic->msimode && (APLIC_IDC_BASE <=3D addr) && + (addr < (APLIC_IDC_BASE + aplic->num_harts * APLIC_IDC_SIZE)))= { + idc =3D (addr - APLIC_IDC_BASE) / APLIC_IDC_SIZE; + switch (addr - (APLIC_IDC_BASE + idc * APLIC_IDC_SIZE)) { + case APLIC_IDC_IDELIVERY: + return aplic->idelivery[idc]; + case APLIC_IDC_IFORCE: + return aplic->iforce[idc]; + case APLIC_IDC_ITHRESHOLD: + return aplic->ithreshold[idc]; + case APLIC_IDC_TOPI: + return riscv_aplic_idc_topi(aplic, idc); + case APLIC_IDC_CLAIMI: + return riscv_aplic_idc_claimi(aplic, idc); + default: + goto err; + }; + } + +err: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid register read 0x%" HWADDR_PRIx "\n", + __func__, addr); + return 0; +} + +static void riscv_aplic_write(void *opaque, hwaddr addr, uint64_t value, + unsigned size) +{ + RISCVAPLICState *aplic =3D opaque; + uint32_t irq, word, idc =3D UINT32_MAX; + + /* Writes must be 4 byte words */ + if ((addr & 0x3) !=3D 0) { + goto err; + } + + if (addr =3D=3D APLIC_DOMAINCFG) { + /* Only IE bit writeable at the moment */ + value &=3D APLIC_DOMAINCFG_IE; + aplic->domaincfg =3D value; + } else if ((APLIC_SOURCECFG_BASE <=3D addr) && + (addr < (APLIC_SOURCECFG_BASE + (aplic->num_irqs - 1) * 4))) { + irq =3D ((addr - APLIC_SOURCECFG_BASE) >> 2) + 1; + if (!aplic->num_children && (value & APLIC_SOURCECFG_D)) { + value =3D 0; + } + if (value & APLIC_SOURCECFG_D) { + value &=3D (APLIC_SOURCECFG_D | APLIC_SOURCECFG_CHILDIDX_MASK); + } else { + value &=3D (APLIC_SOURCECFG_D | APLIC_SOURCECFG_SM_MASK); + } + aplic->sourcecfg[irq] =3D value; + if ((aplic->sourcecfg[irq] & APLIC_SOURCECFG_D) || + (aplic->sourcecfg[irq] =3D=3D 0)) { + riscv_aplic_set_pending_raw(aplic, irq, false); + riscv_aplic_set_enabled_raw(aplic, irq, false); + } + } else if (aplic->mmode && aplic->msimode && + (addr =3D=3D APLIC_MMSICFGADDR)) { + if (!(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) { + aplic->mmsicfgaddr =3D value; + } + } else if (aplic->mmode && aplic->msimode && + (addr =3D=3D APLIC_MMSICFGADDRH)) { + if (!(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) { + aplic->mmsicfgaddrH =3D value & APLIC_xMSICFGADDRH_VALID_MASK; + } + } else if (aplic->mmode && aplic->msimode && + (addr =3D=3D APLIC_SMSICFGADDR)) { + /* + * Registers SMSICFGADDR and SMSICFGADDRH are implemented only if: + * (a) the interrupt domain is at machine level + * (b) the domain's harts implement supervisor mode + * (c) the domain has one or more child supervisor-level domains + * that support MSI delivery mode (domaincfg.DM is not read- + * only zero in at least one of the supervisor-level child + * domains). + */ + if (aplic->num_children && + !(aplic->smsicfgaddrH & APLIC_xMSICFGADDRH_L)) { + aplic->smsicfgaddr =3D value; + } + } else if (aplic->mmode && aplic->msimode && + (addr =3D=3D APLIC_SMSICFGADDRH)) { + if (aplic->num_children && + !(aplic->smsicfgaddrH & APLIC_xMSICFGADDRH_L)) { + aplic->smsicfgaddrH =3D value & APLIC_xMSICFGADDRH_VALID_MASK; + } + } else if ((APLIC_SETIP_BASE <=3D addr) && + (addr < (APLIC_SETIP_BASE + aplic->bitfield_words * 4))) { + word =3D (addr - APLIC_SETIP_BASE) >> 2; + riscv_aplic_set_pending_word(aplic, word, value, true); + } else if (addr =3D=3D APLIC_SETIPNUM) { + riscv_aplic_set_pending(aplic, value, true); + } else if ((APLIC_CLRIP_BASE <=3D addr) && + (addr < (APLIC_CLRIP_BASE + aplic->bitfield_words * 4))) { + word =3D (addr - APLIC_CLRIP_BASE) >> 2; + riscv_aplic_set_pending_word(aplic, word, value, false); + } else if (addr =3D=3D APLIC_CLRIPNUM) { + riscv_aplic_set_pending(aplic, value, false); + } else if ((APLIC_SETIE_BASE <=3D addr) && + (addr < (APLIC_SETIE_BASE + aplic->bitfield_words * 4))) { + word =3D (addr - APLIC_SETIE_BASE) >> 2; + riscv_aplic_set_enabled_word(aplic, word, value, true); + } else if (addr =3D=3D APLIC_SETIENUM) { + riscv_aplic_set_enabled(aplic, value, true); + } else if ((APLIC_CLRIE_BASE <=3D addr) && + (addr < (APLIC_CLRIE_BASE + aplic->bitfield_words * 4))) { + word =3D (addr - APLIC_CLRIE_BASE) >> 2; + riscv_aplic_set_enabled_word(aplic, word, value, false); + } else if (addr =3D=3D APLIC_CLRIENUM) { + riscv_aplic_set_enabled(aplic, value, false); + } else if (addr =3D=3D APLIC_SETIPNUM_LE) { + riscv_aplic_set_pending(aplic, value, true); + } else if (addr =3D=3D APLIC_SETIPNUM_BE) { + riscv_aplic_set_pending(aplic, bswap32(value), true); + } else if (addr =3D=3D APLIC_GENMSI) { + if (aplic->msimode) { + aplic->genmsi =3D value & ~(APLIC_TARGET_GUEST_IDX_MASK << + APLIC_TARGET_GUEST_IDX_SHIFT); + riscv_aplic_msi_send(aplic, + value >> APLIC_TARGET_HART_IDX_SHIFT, + 0, + value & APLIC_TARGET_EIID_MASK); + } + } else if ((APLIC_TARGET_BASE <=3D addr) && + (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) { + irq =3D ((addr - APLIC_TARGET_BASE) >> 2) + 1; + if (aplic->msimode) { + aplic->target[irq] =3D value; + } else { + aplic->target[irq] =3D (value & ~APLIC_TARGET_IPRIO_MASK) | + ((value & aplic->iprio_mask) ? + (value & aplic->iprio_mask) : 1); + } + } else if (!aplic->msimode && (APLIC_IDC_BASE <=3D addr) && + (addr < (APLIC_IDC_BASE + aplic->num_harts * APLIC_IDC_SIZE)))= { + idc =3D (addr - APLIC_IDC_BASE) / APLIC_IDC_SIZE; + switch (addr - (APLIC_IDC_BASE + idc * APLIC_IDC_SIZE)) { + case APLIC_IDC_IDELIVERY: + aplic->idelivery[idc] =3D value & 0x1; + break; + case APLIC_IDC_IFORCE: + aplic->iforce[idc] =3D value & 0x1; + break; + case APLIC_IDC_ITHRESHOLD: + aplic->ithreshold[idc] =3D value & aplic->iprio_mask; + break; + default: + goto err; + }; + } else { + goto err; + } + + if (aplic->msimode) { + for (irq =3D 1; irq < aplic->num_irqs; irq++) { + riscv_aplic_msi_irq_update(aplic, irq); + } + } else { + if (idc =3D=3D UINT32_MAX) { + for (idc =3D 0; idc < aplic->num_harts; idc++) { + riscv_aplic_idc_update(aplic, idc); + } + } else { + riscv_aplic_idc_update(aplic, idc); + } + } + + return; + +err: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid register write 0x%" HWADDR_PRIx "\n", + __func__, addr); +} + +static const MemoryRegionOps riscv_aplic_ops =3D { + .read =3D riscv_aplic_read, + .write =3D riscv_aplic_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + } +}; + +static void riscv_aplic_realize(DeviceState *dev, Error **errp) +{ + uint32_t i; + RISCVAPLICState *aplic =3D RISCV_APLIC(dev); + + aplic->bitfield_words =3D (aplic->num_irqs + 31) >> 5; + aplic->sourcecfg =3D g_new0(uint32_t, aplic->num_irqs); + aplic->state =3D g_new(uint32_t, aplic->num_irqs); + aplic->target =3D g_new0(uint32_t, aplic->num_irqs); + if (!aplic->msimode) { + for (i =3D 0; i < aplic->num_irqs; i++) { + aplic->target[i] =3D 1; + } + } + aplic->idelivery =3D g_new0(uint32_t, aplic->num_harts); + aplic->iforce =3D g_new0(uint32_t, aplic->num_harts); + aplic->ithreshold =3D g_new0(uint32_t, aplic->num_harts); + + memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, apl= ic, + TYPE_RISCV_APLIC, aplic->aperture_size); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio); + + /* + * Only root APLICs have hardware IRQ lines. All non-root APLICs + * have IRQ lines delegated by their parent APLIC. + */ + if (!aplic->parent) { + qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs); + } + + /* Create output IRQ lines for non-MSI mode */ + if (!aplic->msimode) { + aplic->external_irqs =3D g_malloc(sizeof(qemu_irq) * aplic->num_ha= rts); + qdev_init_gpio_out(dev, aplic->external_irqs, aplic->num_harts); + + /* Claim the CPU interrupt to be triggered by this APLIC */ + for (i =3D 0; i < aplic->num_harts; i++) { + RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(aplic->hartid_base + = i)); + if (riscv_cpu_claim_interrupts(cpu, + (aplic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) { + error_report("%s already claimed", + (aplic->mmode) ? "MEIP" : "SEIP"); + exit(1); + } + } + } + + msi_nonbroken =3D true; +} + +static Property riscv_aplic_properties[] =3D { + DEFINE_PROP_UINT32("aperture-size", RISCVAPLICState, aperture_size, 0), + DEFINE_PROP_UINT32("hartid-base", RISCVAPLICState, hartid_base, 0), + DEFINE_PROP_UINT32("num-harts", RISCVAPLICState, num_harts, 0), + DEFINE_PROP_UINT32("iprio-mask", RISCVAPLICState, iprio_mask, 0), + DEFINE_PROP_UINT32("num-irqs", RISCVAPLICState, num_irqs, 0), + DEFINE_PROP_BOOL("msimode", RISCVAPLICState, msimode, 0), + DEFINE_PROP_BOOL("mmode", RISCVAPLICState, mmode, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static const VMStateDescription vmstate_riscv_aplic =3D { + .name =3D "riscv_aplic", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(domaincfg, RISCVAPLICState), + VMSTATE_UINT32(mmsicfgaddr, RISCVAPLICState), + VMSTATE_UINT32(mmsicfgaddrH, RISCVAPLICState), + VMSTATE_UINT32(smsicfgaddr, RISCVAPLICState), + VMSTATE_UINT32(smsicfgaddrH, RISCVAPLICState), + VMSTATE_UINT32(genmsi, RISCVAPLICState), + VMSTATE_VARRAY_UINT32(sourcecfg, RISCVAPLICState, + num_irqs, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(state, RISCVAPLICState, + num_irqs, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(target, RISCVAPLICState, + num_irqs, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(idelivery, RISCVAPLICState, + num_harts, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(iforce, RISCVAPLICState, + num_harts, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(ithreshold, RISCVAPLICState, + num_harts, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_END_OF_LIST() + } +}; + +static void riscv_aplic_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + device_class_set_props(dc, riscv_aplic_properties); + dc->realize =3D riscv_aplic_realize; + dc->vmsd =3D &vmstate_riscv_aplic; +} + +static const TypeInfo riscv_aplic_info =3D { + .name =3D TYPE_RISCV_APLIC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(RISCVAPLICState), + .class_init =3D riscv_aplic_class_init, +}; + +static void riscv_aplic_register_types(void) +{ + type_register_static(&riscv_aplic_info); +} + +type_init(riscv_aplic_register_types) + +/* + * Add a APLIC device to another APLIC device as child for + * interrupt delegation. + */ +void riscv_aplic_add_child(DeviceState *parent, DeviceState *child) +{ + RISCVAPLICState *caplic, *paplic; + + assert(parent && child); + caplic =3D RISCV_APLIC(child); + paplic =3D RISCV_APLIC(parent); + + assert(paplic->num_irqs =3D=3D caplic->num_irqs); + assert(paplic->num_children <=3D QEMU_APLIC_MAX_CHILDREN); + + caplic->parent =3D paplic; + paplic->children[paplic->num_children] =3D caplic; + paplic->num_children++; +} + +/* + * Create APLIC device. + */ +DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size, + uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources, + uint32_t iprio_bits, bool msimode, bool mmode, DeviceState *parent) +{ + DeviceState *dev =3D qdev_new(TYPE_RISCV_APLIC); + uint32_t i; + + assert(num_harts < APLIC_MAX_IDC); + assert((APLIC_IDC_BASE + (num_harts * APLIC_IDC_SIZE)) <=3D size); + assert(num_sources < APLIC_MAX_SOURCE); + assert(APLIC_MIN_IPRIO_BITS <=3D iprio_bits); + assert(iprio_bits <=3D APLIC_MAX_IPRIO_BITS); + + qdev_prop_set_uint32(dev, "aperture-size", size); + qdev_prop_set_uint32(dev, "hartid-base", hartid_base); + qdev_prop_set_uint32(dev, "num-harts", num_harts); + qdev_prop_set_uint32(dev, "iprio-mask", ((1U << iprio_bits) - 1)); + qdev_prop_set_uint32(dev, "num-irqs", num_sources + 1); + qdev_prop_set_bit(dev, "msimode", msimode); + qdev_prop_set_bit(dev, "mmode", mmode); + + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + + if (parent) { + riscv_aplic_add_child(parent, dev); + } + + if (!msimode) { + for (i =3D 0; i < num_harts; i++) { + CPUState *cpu =3D qemu_get_cpu(hartid_base + i); + + qdev_connect_gpio_out_named(dev, NULL, i, + qdev_get_gpio_in(DEVICE(cpu), + (mmode) ? IRQ_M_EXT : IRQ_S_EX= T)); + } + } + + return dev; +} diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 010ded7eae..528e77b4a6 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -70,6 +70,9 @@ config LOONGSON_LIOINTC config RISCV_ACLINT bool =20 +config RISCV_APLIC + bool + config SIFIVE_PLIC bool =20 diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 70080bc161..7466024402 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -50,6 +50,7 @@ specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files(= 's390_flic.c')) specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kv= m.c')) specific_ss.add(when: 'CONFIG_SH_INTC', if_true: files('sh_intc.c')) specific_ss.add(when: 'CONFIG_RISCV_ACLINT', if_true: files('riscv_aclint.= c')) +specific_ss.add(when: 'CONFIG_RISCV_APLIC', if_true: files('riscv_aplic.c'= )) specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'= )) specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c')) specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XICS'], --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645001146836257.52285761697283; Wed, 16 Feb 2022 00:45:46 -0800 (PST) Received: from localhost ([::1]:39956 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKFwX-00037Z-Hb for importer@patchew.org; Wed, 16 Feb 2022 03:45:45 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49084) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDqt-0007Ii-3Z for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:31:48 -0500 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:31692) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDqr-0006ss-49 for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:31:46 -0500 Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:31:43 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:03:24 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:31:44 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7Ql39rlz1Rwrw for ; Tue, 15 Feb 2022 22:31:43 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id ALOP6FKLMM_H for ; Tue, 15 Feb 2022 22:31:42 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7Qf57sxz1SHwl; Tue, 15 Feb 2022 22:31:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993105; x=1676529105; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xBwofrwi48pVPtDFWuxDh/a2BN1h2L8su5YfJ1V9v60=; b=SmqfrlzjlAbJLT6jxQkMVN+bDzAXaOOdZBIyl9P8joOePWgJao4vT5XP VHRrtk9nGvIsImzS4tXg1rJ1Ig9xxyGQ9albOu3iDz4Mw+LvJbpwxFE8d E4lNTGpmOC3bbx6GA0Iv9wbnMIgH41msoaXkO8mihRkBu6Ngp412a0iVR QUdfx2bIzKpBUw2qpYByz/TfawjHQ0XRvMjkDIT1RxrPRQK6SVgYLUlIr 3++kVIBcc7iMWq7mPMuMmMYkvvVXFiT07XUdoZF093Cp+I+MtEXVVHGaD 7Wly7KxYcQX7rljLIKfLyAeBOfWHXlOp15fLA8PxYS2RXLX3FkyfVnRVA w==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="304974651" IronPort-SDR: RdZWScatkGWCvNNu4XN/ISdAwI8Fd4UAK4tsXt8eCEbqj9apr/4Q3wtKn+eiJVHhtPGiYWpTww f33pDXzh1F2zRYmIoDaC8KGz1zzLykw7YC72qwDvA6lkwPkzUWCDKtoDvXavO9DmU5EiS5YV/t kauz1EfKrs5iimXQU5VdCBMYvxSaWcox6xSuhGPs9wCQCpeUMhnwc8wHfAPjOWyPoNEv3o58sk Sxg8zt8uUUCtpp3zrW2r8FR3oJfPriEYAfmxw2ygGTbTNcLNTTFmHX0Uparb4CxlE5olH+7pQJ LFCcrj/IWGV9+8IuQOKsbudG IronPort-SDR: hgbQ9lDp6ZECsMRHzfBqBmbLp8XzWX1DgWAtmnfuVuZtNsZ7ZBE9Oj1L261ldUjeHmYwPCzAUv Q5l1fkEdEO9EfZ5c7UZo31rzvSPgadhrjnMmk8bNJ5+XqAHt/coufhVYTOPydCYm448kJqwX3q owtTW+CoU0juVyDPMVmACdpgwtHcMdATSlp6AdKWkMeB768kkFJMhyDTrLFWd1j1Vto3zQuPzf yYkPMI6Q3Rfnnw4xSNdqMlGgqom6Sj39JE2UtN70Xsm9Em+HAp3LjYP8ibIGAaXJckGTWzDPWZ ZiE= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993102; x=1647585103; bh=xBwofrwi48pVPtDFWu xDh/a2BN1h2L8su5YfJ1V9v60=; b=hcRjkcZq0jT1xtpE1fIkgr2f5lzJoVNcUk WcjU2xTlSslIUjlrj7fXhRiBRj8ZlYNr9ztPpfTf4fK/P+eK+F3usVU7d13sfSE+ MT323WK3be2de3Lg/T0Q0fsMZMOVS49OuDDR4ArBFwWMkHxoQeJHWjZDNsvpd9Ij FK77SE0tjAuLYMzt2ik8gCG+cZbXD2K3OHonSl+hfiO6hwItASsrCkOskBAdwT4o xd0+YZ5dGpfUpEXg09pmlfkHerMa+r6t5lU6rM1tTSuaT7x9oRx0pPTzdRKixjmZ doukGLWaSda2qqHaPO+Ax737fZQ8dVU5u7GDVnrUCt2MZuSSDUog== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Guo Ren , Liu Zhiwei , Alistair Francis , Bin Meng Subject: [PULL v2 30/35] target/riscv: Ignore reserved bits in PTE for RV64 Date: Wed, 16 Feb 2022 16:29:07 +1000 Message-Id: <20220216062912.319738-31-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1645001149014100001 Content-Type: text/plain; charset="utf-8" From: Guo Ren Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we need to ignore them. They cannot be a part of ppn. 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture 4.4 Sv39: Page-Based 39-bit Virtual-Memory System 4.5 Sv48: Page-Based 48-bit Virtual-Memory System 2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.= pdf Signed-off-by: Guo Ren Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis Cc: Bin Meng Reviewed-by: Alistair Francis Message-Id: <20220204022658.18097-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 15 +++++++++++++++ target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_helper.c | 13 ++++++++++++- 3 files changed, 30 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7ecb1387dd..cefccb4016 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -359,6 +359,8 @@ struct RISCVCPUConfig { bool ext_counters; bool ext_ifencei; bool ext_icsr; + bool ext_svnapot; + bool ext_svpbmt; bool ext_zfh; bool ext_zfhmin; bool ext_zve32f; @@ -558,6 +560,19 @@ static inline int riscv_cpu_xlen(CPURISCVState *env) return 16 << env->xl; } =20 +#ifdef TARGET_RISCV32 +#define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) +#else +static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) +{ +#ifdef CONFIG_USER_ONLY + return env->misa_mxl; +#else + return get_field(env->mstatus, MSTATUS64_SXL); +#endif +} +#endif + /* * Encode LMUL to lmul as follows: * LMUL vlmul lmul diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 068c4d8034..b3489cbc10 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -565,6 +565,9 @@ typedef enum { /* Page table PPN shift amount */ #define PTE_PPN_SHIFT 10 =20 +/* Page table PPN mask */ +#define PTE_PPN_MASK 0x3FFFFFFFFFFC00ULL + /* Leaf page shift amount */ #define PGSHIFT 12 =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 430060dcd8..7df4569526 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -751,6 +751,8 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; int mode =3D mmu_idx & TB_FLAGS_PRIV_MMU_MASK; bool use_background =3D false; + hwaddr ppn; + RISCVCPU *cpu =3D env_archcpu(env); =20 /* * Check if we should use the background registers for the two @@ -919,7 +921,16 @@ restart: return TRANSLATE_FAIL; } =20 - hwaddr ppn =3D pte >> PTE_PPN_SHIFT; + if (riscv_cpu_sxl(env) =3D=3D MXL_RV32) { + ppn =3D pte >> PTE_PPN_SHIFT; + } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) { + ppn =3D (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; + } else { + ppn =3D pte >> PTE_PPN_SHIFT; + if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) { + return TRANSLATE_FAIL; + } + } =20 if (!(pte & PTE_V)) { /* Invalid PTE */ --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1644994712748740.7006444391894; Tue, 15 Feb 2022 22:58:32 -0800 (PST) Received: from localhost ([::1]:33354 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKEGl-0001kZ-Ol for importer@patchew.org; Wed, 16 Feb 2022 01:58:31 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49108) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDqx-0007Kh-6N for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:31:52 -0500 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:31697) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDqv-0006tE-Ho for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:31:50 -0500 Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:31:48 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:03:28 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:31:48 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7Qq71Lhz1SVp0 for ; Tue, 15 Feb 2022 22:31:47 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id GlM6hPFL4Lzb for ; Tue, 15 Feb 2022 22:31:47 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7Ql5Kydz1Rwrw; Tue, 15 Feb 2022 22:31:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993109; x=1676529109; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Op9MBksbJCLjCPcsH3y+BxEHX7yAAvSi//ZF4kTyuyI=; b=Efe1H56ZtBrc6mQ7axrNxKWiGybT0Ffi9eYPGeFQ91kr57ErmrRb62zQ sv0lLfS28RVihOYGtv5/8peDQCRRM084a1udU8cmSW/GOc3MU4dAd77L8 FARotWvxPnOaeeTGU3vwwcNWmn6HJGIN4aemFshg/m5e7XLmFDJpcjhqe vK6mnd3r9MmaH4v8jFUcgP9pW+j8LAxz+xLPrxixB4tM+ghBIDEsrwClp ondI3awI0EpvkpWKTmOKy9BrRyACoKLNWE78AOZc9TjQDYSBi1zWAE6kY kD53hoOhBVbLIJLQtoE9wQObX4znF1kX+86CAMLSszwqNHbzTG07jTpWy w==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="304974653" IronPort-SDR: VxAZfY6uAv1B0lxHwkGZvuRM9lfgKBFmSjxEsaTZW+BseOi2pPFyRQ4PraRGV4juWedt38oL6j j0ZNhRIuNc/ILRz5IeiJryxvRqzi91xgRuteL4650VbZpdc8bMwPzJ0T40M1R375jf2xH6DOKx P3Pu47T1IFUvoFlXoTDjfoOYtjZD+O4DlCfFYIKGhJQnQH9MpaAkLw1JPtV2Qo3+5bviiL0XSj z/Jd0KGLUwlPOuckw2trKnVtT7m6ixBVWtLvxXLSENdyKCHMXR6sVY+Xkc2/00E8X1RCSDsM0y SC+uhrtbtfmGxiKK+mVDVWcg IronPort-SDR: qzOCvQ2oR/7plTKxKfIhRVoJWYkbQ4sOJ8JFl7O5OujOnPwOUhv/jU5lXZfIT5XFe/NrA2NA04 vgIK5xAk89GRDG6FFWq+G9cuRRrpAbEMTNobATe/j7RQFIfvXWsVDmSslk6duIE//UjnlyKs87 TuGUotJ7WeQLAdgxDYJtGwM3xNaUQ0KX+yEoKYdAN04cnZToD0aucp6R92b2ANTI+Xy0HCiO9L Apou6PUhQY1irI6sLu2NY0Jj/j5DpG8Ds3SFTj/X0jFViNLB7Wp9zzy6JY0GvrbWdo83SmBy37 r4M= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993107; x=1647585108; bh=Op9MBksbJCLjCPcsH3 y+BxEHX7yAAvSi//ZF4kTyuyI=; b=pMAMcCtjBVraUGmu6FnV3wRUlJbfxhxRfl J0sXAdtkOPxXimSsCe9+ztFkbOEj5FAbs03p2baYnSecXU7IGzicuLA/JXoMj2D2 wry7FFP5clHOVCgodhZVnkLalXoBdKOv2RDHCSa7rn5QwfJxGO7sZwgJgPVsd1NR WhC8SoFWam+L0BOUP9rBUnzzjcZDAf6R+jyKunhHfPgzQY3dLmT59M+ndBzKC8Ie M7LBjKaBVWvHOzMIA3rPnoe/qEq6Fo8Dw19kS4bZ+oE4Hn3jDF2sabCG+HBmsH4R jublAiJAY37OH1F3YRiWfvLEzflXVzDux2/s15CAu4bQyvhaVLnQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Anup Patel , Alistair Francis Subject: [PULL v2 31/35] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE Date: Wed, 16 Feb 2022 16:29:08 +1000 Message-Id: <20220216062912.319738-32-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1644994714684100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li For non-leaf PTEs, the D, A, and U bits are reserved for future standard us= e. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel Reviewed-by: Alistair Francis Message-Id: <20220204022658.18097-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 7df4569526..25ebc76725 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -937,6 +937,9 @@ restart: return TRANSLATE_FAIL; } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { /* Inner PTE, continue walking */ + if (pte & (PTE_D | PTE_A | PTE_U)) { + return TRANSLATE_FAIL; + } base =3D ppn << PGSHIFT; } else if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D PTE_W) { /* Reserved leaf PTE flags: PTE_W */ --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645001392886638.1630093980372; Wed, 16 Feb 2022 00:49:52 -0800 (PST) Received: from localhost ([::1]:44874 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKG0U-0006gO-RB for importer@patchew.org; Wed, 16 Feb 2022 03:49:50 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49126) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDr2-0007Lr-Fr for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:31:56 -0500 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:31697) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDr0-0006tE-HH for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:31:56 -0500 Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:31:53 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:03:33 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:31:53 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7Qw6C30z1SHwl for ; Tue, 15 Feb 2022 22:31:52 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id RSicG0VIN_Hy for ; Tue, 15 Feb 2022 22:31:52 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7Qr3V7Bz1Rwrw; Tue, 15 Feb 2022 22:31:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993114; x=1676529114; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5M2juYO1XBdVp0HXJg8qxnDJ7Bn+5MPFeReNPxd/vPE=; b=KofN1ql4oHP2PTXHFwRqYTuj7MygFo45prMFL5dzHONLQWYBVO8daLKk 07/k0KJ8lWa9S9BOj8NnkqbyNWWJXD5IQTv37r0AbwqmpBBVcB2gznGX0 t0a8n8wIPCyHskM46fxIPxdYv58+OWr8Vw66XJdCFjQ7HJiEXqEi9j41M 4J8k9adyd29GZ+4S1zyLNYeTaaFTdK8TGn1KZO7TV0eTiWeRMaP7MrWr4 lQTAN52VTX5rtNqg2Wa36W6uSVu7TnwwNkkQMsuffTunrLW+LhDVNwiDJ D0aX79iyZ5VIRyo79BMaRTBD19kbOi4HdMaoxUZIFQig8sHgnsI9Gi2y4 w==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="304974664" IronPort-SDR: AdnJWqE5C3DYZpAlScivfr4Ovv40CUbu8RmoB7BiLJDmmpmbs1+ShcK080SSH2uSnKT8m1fxig E2MIbqz3rU5tXcsdzdZCdAWFVwvH6jywjD4qgWPDJ2qbMVZoUQs1an2E15ZNg3+384ArFIEvoq KCWKPRakEM+jlgRiecCwpDSqdV1X+VbwZ6KQof7gRd/tjSXQG2TrdsCM1zfwzT3wRsagmACoVx F3LHuJ9MXp4Fkag8EJjtfJ0gj/E3F5tvS4JdDuo16v6c8/tFnohK8lAWTXO0zy/tyYpsYwdGG3 zq06Ubcsu9aqu0Dp8C7XLO4J IronPort-SDR: tDd1Ju/lStGje5OUHRw3rUIDVn2J2jFM1AvI/KvrRiIykcZ/XHMnxLJLzgtOpfN2LALtyG9r+c VNBlEMvNTh3gA1Vz51URMKkx41UejiF72Ih9AB7tuSpk08E7NkvDkYs/sJyFzelLF1NZa7fo0O rpyVjMCza+ATnaTpWH3ZxgOwnWOLluDu24DU8713jFk9589sQZNSu9MO1Yre36B9oqJIHik3oK Ky2FS0gY1apPs+IFIU6FDznagmYFEbP/sLXgPVOJ40Qb1gCIODd+mmKqMnqSvYvm5KRn0sRui0 uPQ= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993112; x=1647585113; bh=5M2juYO1XBdVp0HXJg 8qxnDJ7Bn+5MPFeReNPxd/vPE=; b=W5svLGuvSihQqRu3sAn2hNlqTvrZFrMFcm kcUxl7oXxA78Lc2YiYUBREbPU5M6kV4mIeT9BfxFqR21fR2x1FAhkCsoCrVMN2W/ m+Tzg83hYQ/pGJ/8GI0MzYoMQBmfxDCC//oobiFP0VY2w3RcphURYNjHQ2Y78owz H4F4U9iZO0RPA6RV4uijgHyrRtBjl1w4S0eEekx5wjA63Wljul3Q9JXIde+k0UHu VdYmSq94uZUTisxmUTXQOxiJudoMep1TrVf3O1IFdDwDGsrfBoSdHKUCpTBsWRBY 91274Xz/Ol1S8XJnUCUNtilmk5BjU+rUUkU2GIlUKVFctK54jZ2w== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Anup Patel , Alistair Francis Subject: [PULL v2 32/35] target/riscv: add support for svnapot extension Date: Wed, 16 Feb 2022 16:29:09 +1000 Message-Id: <20220216062912.319738-33-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1645001393896100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li - add PTE_N bit - add PTE_N bit check for inner PTE - update address translation to support 64KiB continuous region (napot_bits= =3D 4) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel Reviewed-by: Alistair Francis Message-Id: <20220204022658.18097-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/cpu.c | 2 ++ target/riscv/cpu_helper.c | 18 +++++++++++++++--- 3 files changed, 18 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index b3489cbc10..37ed4da72c 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -561,6 +561,7 @@ typedef enum { #define PTE_A 0x040 /* Accessed */ #define PTE_D 0x080 /* Dirty */ #define PTE_SOFT 0x300 /* Reserved for Software */ +#define PTE_N 0x8000000000000000ULL /* NAPOT translation */ =20 /* Page table PPN shift amount */ #define PTE_PPN_SHIFT 10 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9dce57a380..fda99c2a81 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -774,6 +774,8 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), =20 + DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), + DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 25ebc76725..437c9488a6 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -753,6 +753,8 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, bool use_background =3D false; hwaddr ppn; RISCVCPU *cpu =3D env_archcpu(env); + int napot_bits =3D 0; + target_ulong napot_mask; =20 /* * Check if we should use the background registers for the two @@ -937,7 +939,7 @@ restart: return TRANSLATE_FAIL; } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { /* Inner PTE, continue walking */ - if (pte & (PTE_D | PTE_A | PTE_U)) { + if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) { return TRANSLATE_FAIL; } base =3D ppn << PGSHIFT; @@ -1013,8 +1015,18 @@ restart: /* for superpage mappings, make a fake leaf PTE for the TLB's benefit. */ target_ulong vpn =3D addr >> PGSHIFT; - *physical =3D ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIF= T) | - (addr & ~TARGET_PAGE_MASK); + + if (cpu->cfg.ext_svnapot && (pte & PTE_N)) { + napot_bits =3D ctzl(ppn) + 1; + if ((i !=3D (levels - 1)) || (napot_bits !=3D 4)) { + return TRANSLATE_FAIL; + } + } + + napot_mask =3D (1 << napot_bits) - 1; + *physical =3D (((ppn & ~napot_mask) | (vpn & napot_mask) | + (vpn & (((target_ulong)1 << ptshift) - 1)) + ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); =20 /* set permissions on the TLB entry */ if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164499503246728.023891943830222; Tue, 15 Feb 2022 23:03:52 -0800 (PST) Received: from localhost ([::1]:42104 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKELv-0007h5-AD for importer@patchew.org; Wed, 16 Feb 2022 02:03:51 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49188) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDrO-0007Ut-Re for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:32:20 -0500 Received: from esa4.hgst.iphmx.com ([216.71.154.42]:51227) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDrC-0006ts-3f for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:32:13 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:31:58 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:04:47 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:31:59 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7R24XtGz1SVp0 for ; Tue, 15 Feb 2022 22:31:58 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id HYZGYizygcnN for ; Tue, 15 Feb 2022 22:31:57 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7Qx1gBJz1Rwrw; Tue, 15 Feb 2022 22:31:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993125; x=1676529125; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZsXkcJzVuSL2NWL/cTuKMF+SnFjwZ9qctY53H23aGfc=; b=VkIUx7SizJCcX2i2q7fuBe3XfUQlWj/5ch7LuxH78l0jcIhbsVSL1KLr CRDqUyb3w0dOtukjEJ5aIx51d3rDl+RA1lL9J6QWNjoKB33NlWv3iBp4u yiSx/bqQ378TCvsbGUPiiwG1+fMU3VD1GtGRxMj/ROyRyi03lEKbmJtKX DPbV0dOcS9ldQ3hOWjqth9zEfHXeHm16VmJDrCtcjEPXXsIilo3vp+Mfp HGdkTW9xOta8naG/lVEyDOE/EuzLOaj8RjzyrYYh75zTeVINLJWq6KhRl L8WpfGm7epOgCpBvr+7RL+tYsYvofL9Nv2Ggvyz+vV+g2kw75aUugJYyL A==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="192004576" IronPort-SDR: N48hZViOVC6e69uK8vT+QFGtNJkCFOpAgEeo3sXXZ5z2MLkhBZm7BSfuePYvAn/tLfeQQY98v7 WD7cxPWPstkBg28Tb+Kvc5PSSiiblhJHbYIiqYD6p/8Ta0+erMn/TLlw7tupJsuw6d6vCokNeC rDZkzlK2Lcvsob2gJDw5tHPCRcuxc2sWE8/hkagdNjQLE9EMbLqyCQWhnZALHkzl+mPXtLmdZ1 WvSiPGGAEzSFArNOu2yh5Zwc95MhP0KzX9pz/61Z0llRQnPOWMfnBGFXpF2kp34X166riK56Nb ckVoLxDhYi9Rl9jhftDYzqJd IronPort-SDR: AYTD2s3uj8eOrB0xxxPEGmYMUQPpit1IYnZhLQOvShrj51xf+t2u6/WYVjZkrrNGTuWBkXrKuP lVLQFZLXbda2Ak7O0JdcTpUkLdqS905oV0RcUoH87kY3panA7Q/psS6YDNPwfALXGOJiT/UW7n CgYpncAphJG3rygwzfuQWUsjObi1kAvRZBwWQt1JnFJwW4/xXHK+cRHqBYMtMenBPzSSbp51Sd Y+xrOsdB7yZIMqStcb2btMzLRlR7k95tFq908bpHkfapAjg9SZqUi+t9O/GO1k4zHW/7s6XYsJ vVQ= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993117; x=1647585118; bh=ZsXkcJzVuSL2NWL/cT uKMF+SnFjwZ9qctY53H23aGfc=; b=cSDxbPzdXI3cLVtXSzPcdAfCmBqBoVBzgE 8TzxaJdUgC2brgaRfhmEGH+VSwC5j9ZYgBgKPgaVmfnuyveypZc0FTkWoJiXKtsQ RAHFXaCkw0Bhg3GaWXmqarKCXoCoe4mvggyTZUWSaGRhZqfgV862/cywdaUICGwf roupdD1yhqV5itELzKzX2NXR4sVZrEy8O+IFTpn/T3q80REEUo7opML/P71kXASx yaRanLjKrFBt6i3AvJ0raoqJZoN1VOKFiKvL4RfLakJgpIAiA6hE6mpagIg6xTqZ MeEj1Sz6yEBwsCyoxvfZsp/WD8mweyNTc25MGOKfRy6pfUxbuIVA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Anup Patel , Alistair Francis Subject: [PULL v2 33/35] target/riscv: add support for svinval extension Date: Wed, 16 Feb 2022 16:29:10 +1000 Message-Id: <20220216062912.319738-34-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1644995034579100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li - sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma, hfence= .vvma and hfence.gvma except extension check - do nothing other than extension check for sfence.w.inval and sfence.inval= .ir Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel Reviewed-by: Alistair Francis Message-Id: <20220204022658.18097-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/insn32.decode | 7 ++ target/riscv/cpu.c | 1 + target/riscv/translate.c | 1 + target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++ 5 files changed, 85 insertions(+) create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index cefccb4016..8183fb86d5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -359,6 +359,7 @@ struct RISCVCPUConfig { bool ext_counters; bool ext_ifencei; bool ext_icsr; + bool ext_svinval; bool ext_svnapot; bool ext_svpbmt; bool ext_zfh; diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 5bbedc254c..1d3ff1efe1 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -809,3 +809,10 @@ fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_= rm fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm + +# *** Svinval Standard Extension *** +sinval_vma 0001011 ..... ..... 000 00000 1110011 @sfence_vma +sfence_w_inval 0001100 00000 00000 000 00000 1110011 +sfence_inval_ir 0001100 00001 00000 000 00000 1110011 +hinval_vvma 0010011 ..... ..... 000 00000 1110011 @hfence_vvma +hinval_gvma 0110011 ..... ..... 000 00000 1110011 @hfence_gvma diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fda99c2a81..e5676b40d1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -774,6 +774,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), =20 + DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), =20 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), diff --git a/target/riscv/translate.c b/target/riscv/translate.c index eaf5a72c81..84dbfa6340 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -862,6 +862,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, tar= get_ulong pc) #include "insn_trans/trans_rvb.c.inc" #include "insn_trans/trans_rvzfh.c.inc" #include "insn_trans/trans_privileged.c.inc" +#include "insn_trans/trans_svinval.c.inc" #include "insn_trans/trans_xventanacondops.c.inc" =20 /* Include the auto-generated decoder for 16 bit insn */ diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/ins= n_trans/trans_svinval.c.inc new file mode 100644 index 0000000000..2682bd969f --- /dev/null +++ b/target/riscv/insn_trans/trans_svinval.c.inc @@ -0,0 +1,75 @@ +/* + * RISC-V translation routines for the Svinval Standard Instruction Set. + * + * Copyright (c) 2020-2022 PLCT lab + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#define REQUIRE_SVINVAL(ctx) do { \ + if (!ctx->cfg_ptr->ext_svinval) { \ + return false; \ + } \ +} while (0) + +static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a) +{ + REQUIRE_SVINVAL(ctx); + /* Do the same as sfence.vma currently */ + REQUIRE_EXT(ctx, RVS); +#ifndef CONFIG_USER_ONLY + gen_helper_tlb_flush(cpu_env); + return true; +#endif + return false; +} + +static bool trans_sfence_w_inval(DisasContext *ctx, arg_sfence_w_inval *a) +{ + REQUIRE_SVINVAL(ctx); + REQUIRE_EXT(ctx, RVS); + /* Do nothing currently */ + return true; +} + +static bool trans_sfence_inval_ir(DisasContext *ctx, arg_sfence_inval_ir *= a) +{ + REQUIRE_SVINVAL(ctx); + REQUIRE_EXT(ctx, RVS); + /* Do nothing currently */ + return true; +} + +static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a) +{ + REQUIRE_SVINVAL(ctx); + /* Do the same as hfence.vvma currently */ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + gen_helper_hyp_tlb_flush(cpu_env); + return true; +#endif + return false; +} + +static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a) +{ + REQUIRE_SVINVAL(ctx); + /* Do the same as hfence.gvma currently */ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + gen_helper_hyp_gvma_tlb_flush(cpu_env); + return true; +#endif + return false; +} --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1644998778931945.8460952855959; Wed, 16 Feb 2022 00:06:18 -0800 (PST) Received: from localhost ([::1]:40202 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKFKM-00058J-VF for importer@patchew.org; Wed, 16 Feb 2022 03:06:19 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49224) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDrW-0007WO-EW for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:32:27 -0500 Received: from esa4.hgst.iphmx.com ([216.71.154.42]:51232) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDrH-0006vE-JW for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:32:26 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:32:03 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:04:51 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:32:03 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7R66wVDz1SVnx for ; Tue, 15 Feb 2022 22:32:02 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id a1QHFbQVqnP8 for ; Tue, 15 Feb 2022 22:32:02 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7R24w39z1Rwrw; Tue, 15 Feb 2022 22:31:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993131; x=1676529131; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pGlKdfaHOFQg2MrLicewvmm13um5B719f/O0rDm4uA4=; b=Nlw34tyj7VUKdV0/TYFUjU9+rgZNIZ1zUCps/U+tg3dTSTiCKBZPpOAh hn2uWaPU4KFXy2VBBV7JtD0qxQI6ln+LvS9JKPJK/tqxuvgH5WmEQ3J5D gzG5Y68KNCVaX2UbMnGbrzNDS1bDixTCH1/KAQ2rrNJZHOpXFPVwOrqif GmHt0dXw94wQfwMgo+zPnRJTS+L8aY+JBDwI4HGisp9zvNGVDDkxUCEMg 151swfijypM4dyRLpa+MInbBD/JqgCj8QCiK9PLcJYHj66FWYuQO5Rc7D HtpGDoRdCWoOwGAzf5DB5emxl6yD+ql0gW701AATC1b9OG2VHZlbwYiSA w==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="192004585" IronPort-SDR: l2gI9AonZcmlR9u4ItUeERyjChcQb1iwav77zd+w3Q18xVYuaafinlGMRO1wjBdKoSh9Og/UAu Qp878KZRvL1yHUXpLyRHy7AkvoH7Lk15us88Wb7iQ/B63llg1lnWUCgMa3ab94YI+QmiXzbWJ6 gydAinCPnvK+xisiHktt5hSbucqUlnHlQQkxq5+tqH2+xcmXoofaq/Skg14bxhQvVDNpWtYl6i FKe+FMTwPqPI+mQVMARyZZLGz4t3WdVUtiazJdj459zoHIV3h12AAJX97qH1DKpcyKvUZqvmf7 loSkdFV8CqgN7aoJl4kaiEQ8 IronPort-SDR: YOLeXcV0NGyHdtn265To0pH3quRdcQA88ABgrCUhkDmeUwA9f9uzm/gC/9ZqBlQAX4616EoRjz HeQztT18Jyc0f0CG5RNkxHQmy3ti/WtoG3fvtu5GsrI/0iFTpW73c/S6JrGD3Z0g7mvQwiJcJD v6lGOZ7jmEA4s61qr4lHglIqiJEjICI1e+WJ1stvlOX+Iu6iFInuUSidcNTXfNzApRelFHzfIr K3x1sZlAc9ZRl7p1WsfwcKmPD9HkWXxSun9epsdn38bHGBEstuTJW+10aquUdjMV5z6ySBxXOm KQQ= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993122; x=1647585123; bh=pGlKdfaHOFQg2MrLic ewvmm13um5B719f/O0rDm4uA4=; b=rvEsbhW5JCrhsIojJyW4EehNdIkXm+dY7x 4eBo8ny4ZWtaznh5vx+C3kx+H0RTuxCVYVYw4zaZD9BhgX2d99C+lgPpLjF/+arX 17w4gfjalFU8iX3MzIehlObozzyYp76GG6qoGISwrYBUyLcmEZFiH3hrRCuvrXbE 8tMtaWRlNtIBUGLhvHC6U9VTkXZj74xuRUlMiypAPTR8C56jJ5Ft/ds72mwcjuMo eWjabhS5SGACU6ZTktvtv6eO7Fltn/CccBCYOyyPJ5XDEf2VDXy4TfGYRFC+huwe j2Vuvj9W7OAKfio6VPAjdsgl4VbGF6Ng0JwT9XyiiIadKKDO6Xtg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Anup Patel , Alistair Francis Subject: [PULL v2 34/35] target/riscv: add support for svpbmt extension Date: Wed, 16 Feb 2022 16:29:11 +1000 Message-Id: <20220216062912.319738-35-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1644998800803100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li - add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on Q= EMU, since QEMU is sequentially consistent and doesn't model PMAs currently - add PTE_PBMT bit check for inner PTE Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Anup Patel Reviewed-by: Alistair Francis Message-Id: <20220204022658.18097-6-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 2 ++ target/riscv/cpu.c | 1 + target/riscv/cpu_helper.c | 4 +++- 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 37ed4da72c..0fe01d7da5 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -561,7 +561,9 @@ typedef enum { #define PTE_A 0x040 /* Accessed */ #define PTE_D 0x080 /* Dirty */ #define PTE_SOFT 0x300 /* Reserved for Software */ +#define PTE_PBMT 0x6000000000000000ULL /* Page-based memory typ= es */ #define PTE_N 0x8000000000000000ULL /* NAPOT translation */ +#define PTE_ATTR (PTE_N | PTE_PBMT) /* All attributes bits */ =20 /* Page table PPN shift amount */ #define PTE_PPN_SHIFT 10 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e5676b40d1..b0a40b83e7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -776,6 +776,7 @@ static Property riscv_cpu_properties[] =3D { =20 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), + DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), =20 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 437c9488a6..746335bfd6 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -937,9 +937,11 @@ restart: if (!(pte & PTE_V)) { /* Invalid PTE */ return TRANSLATE_FAIL; + } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) { + return TRANSLATE_FAIL; } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { /* Inner PTE, continue walking */ - if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) { + if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { return TRANSLATE_FAIL; } base =3D ppn << PGSHIFT; --=20 2.34.1 From nobody Mon Feb 9 08:42:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=none) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645002200586250.75464761817227; Wed, 16 Feb 2022 01:03:20 -0800 (PST) Received: from localhost ([::1]:40260 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKGDY-0006Fm-6H for importer@patchew.org; Wed, 16 Feb 2022 04:03:20 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49204) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDrO-0007Uu-RZ for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:32:20 -0500 Received: from esa4.hgst.iphmx.com ([216.71.154.42]:51237) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKDrH-0006vQ-OC for qemu-devel@nongnu.org; Wed, 16 Feb 2022 01:32:14 -0500 Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 16 Feb 2022 14:32:06 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:04:55 -0800 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 22:32:07 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4Jz7RB4WgQz1SHwl for ; Tue, 15 Feb 2022 22:32:06 -0800 (PST) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id W3Psu-4sMsW3 for ; Tue, 15 Feb 2022 22:32:06 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.165.97]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Jz7R746rzz1Rwrw; Tue, 15 Feb 2022 22:32:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1644993131; x=1676529131; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lGagEk2V70JnLYrJSWPxoeD7YvAzgDmHU8MPmIJXlz8=; b=hOGhberkKorXmgcHnpNQsRh1fT8m+d4WhMKqeuu8oZCdIdvfmxSrwttW HlesCSCDwlMFMX0AYPX06mKzVjKV9T+485+zNGD8HyOnTgawPraydASiP 4OvTvmEZeWWx1K3LU4kfOfrtC52OyNsMfuCMu5iExOAAzZ/R5OmGa+rFg c7ORVVE06FSYRh+CIdAcg/bG426vB2meSzaR9++8mQssYiaG8n87IuLM9 4GNMBGaIzQWv5b9z8IYv0xn5bpMbZlGt4Q4BrzHj7Sbem9LUXf7w07QZf HuB9E9HgkskhnZwOCQ23l5urZgNd87iF3LlmUs0tqx1bM4H+RgSOE97Rd g==; X-IronPort-AV: E=Sophos;i="5.88,373,1635177600"; d="scan'208";a="192004593" IronPort-SDR: 5MDv36xQwm+sbFCexRmFoXCidG8vE0QvsxYLR/Z24wp1J1m962SIeq6rWQoCpdTRKW1yXCmpYV MqbblbkoCxDi586nsxkTKd6AHhLvcs+Q1QFABmM8UkcPmWReq7WJN/DMBYox691i6dcf8YBu6w dOmsaKSXTmgPe1TtEvRRvAS0axg5MoXb72KtuSTdm3BGzrKgoDjevzhfiBy4K/Zj8uzhJr5UDX 00Pa7mQUm9GQL4avzlV+StvBdIFLJuHczvxrIbvgJn3pW51wWp5hnFAl6nHNteGsrrp/QIW9RP WDiVna0cZ+mNZNmnBhN+dTzu IronPort-SDR: m1Wr94LMgJcTSpjDkP/PZnfFGNgM01TIAjEb7//sSZ+HKHyFyDaSHB4NWaYhJpI+nSWvGLz00t 0HHk6RIhFBrWWjacumigWxxrqovXqZ+xDhFD9IH1hIw3yiMocPVHEARE3SOik6oEXkCKqJUgug q5UdZKd3NxAWgZzAfon4VebuT+ZedOrmSMJK1TJiItJ/RnAKBTJYe+juHl5toS5H0RQ0EYyRgs /1iBD/NNCVM+xq7CF1g2+rJANrxLzh7BXRlyTmZ5AVnpj0n+HjigxjkMzqHKEbcZyzfXLK2x17 UR8= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1644993126; x=1647585127; bh=lGagEk2V70JnLYrJSW PxoeD7YvAzgDmHU8MPmIJXlz8=; b=PhHPCPjhxQavoiiNcdwqLvuisxO9aK1ck7 KxLA8wIwqXTOEmg4oxOxLpYG+Lbgaa5eHNmo+DgVKML14T9wtgFNH5jeVd50aZa4 s2a7fkZDReCrR6pUmzRVxF/+4LgY1zVZX4NUIwSz6JXXzEQveB2ncHyeCOi/5TYp gfMXrhZnKOFGVo4QQEH1137a8l0QhYOa23W/OfvPyb3i/OCVsWMCDj5EGjPE+0o1 AX1TfAbiQ2O83WiIwkGSR+GmcBFaIrZ5/R9/SoDNcAP+8zMbR0nWrdORccUjsvIk xC3ktZ8WZEQh/h2g5+9jPCG9O9sHOYV3wMCT9jUyd6Fsb+xFmGaQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Yu Li , Alistair Francis Subject: [PULL v2 35/35] docs/system: riscv: Update description of CPU Date: Wed, 16 Feb 2022 16:29:12 +1000 Message-Id: <20220216062912.319738-36-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> References: <20220216062912.319738-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1645002202413100001 Content-Type: text/plain; charset="utf-8" From: Yu Li Since the hypervisor extension been non experimental and enabled for default CPU, the previous command is no longer available and the option `x-h=3Dtrue` or `h=3Dtrue` is also no longer required. Signed-off-by: Yu Li Reviewed-by: Alistair Francis Message-Id: <9040401e-8f87-ef4a-d840-6703f08d068c@bytedance.com> Signed-off-by: Alistair Francis --- docs/system/riscv/virt.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst index fa016584bf..08ce3c4177 100644 --- a/docs/system/riscv/virt.rst +++ b/docs/system/riscv/virt.rst @@ -23,9 +23,9 @@ The ``virt`` machine supports the following devices: * 1 generic PCIe host bridge * The fw_cfg device that allows a guest to obtain data from QEMU =20 -Note that the default CPU is a generic RV32GC/RV64GC. Optional extensions -can be enabled via command line parameters, e.g.: ``-cpu rv64,x-h=3Dtrue`` -enables the hypervisor extension for RV64. +The hypervisor extension has been enabled for the default CPU, so virtual +machines with hypervisor extension can simply be used without explicitly +declaring. =20 Hardware configuration information ---------------------------------- --=20 2.34.1