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[PATCH v3 11/37] target/ppc: Implement Vector Compare Equal Quadword

matheus.ferst@eldorado.org.br posted 37 patches 3 years, 12 months ago
Maintainers: Greg Kurz <groug@kaod.org>, Richard Henderson <richard.henderson@linaro.org>, Daniel Henrique Barboza <danielhb413@gmail.com>, David Gibson <david@gibson.dropbear.id.au>, "Cédric Le Goater" <clg@kaod.org>
There is a newer version of this series
[PATCH v3 11/37] target/ppc: Implement Vector Compare Equal Quadword
Posted by matheus.ferst@eldorado.org.br 3 years, 12 months ago 
From: Matheus Ferst <matheus.ferst@eldorado.org.br>

Implement the following PowerISA v3.1 instructions:
vcmpequq Vector Compare Equal Quadword

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
 target/ppc/insn32.decode            |  1 +
 target/ppc/translate/vmx-impl.c.inc | 43 +++++++++++++++++++++++++++++
 2 files changed, 44 insertions(+)

diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index a0adf18671..39730df32d 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -382,6 +382,7 @@ VCMPEQUB        000100 ..... ..... ..... . 0000000110   @VC
 VCMPEQUH        000100 ..... ..... ..... . 0001000110   @VC
 VCMPEQUW        000100 ..... ..... ..... . 0010000110   @VC
 VCMPEQUD        000100 ..... ..... ..... . 0011000111   @VC
+VCMPEQUQ        000100 ..... ..... ..... . 0111000111   @VC
 
 VCMPGTSB        000100 ..... ..... ..... . 1100000110   @VC
 VCMPGTSH        000100 ..... ..... ..... . 1101000110   @VC
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 67059ed9b2..bdb0b4370b 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1112,6 +1112,49 @@ TRANS(VCMPNEZB, do_vcmpnez, MO_8)
 TRANS(VCMPNEZH, do_vcmpnez, MO_16)
 TRANS(VCMPNEZW, do_vcmpnez, MO_32)
 
+static bool trans_VCMPEQUQ(DisasContext *ctx, arg_VC *a)
+{
+    TCGv_i64 t0, t1;
+    TCGLabel *l1, *l2;
+
+    REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+    REQUIRE_VECTOR(ctx);
+
+    t0 = tcg_temp_new_i64();
+    t1 = tcg_temp_new_i64();
+    l1 = gen_new_label();
+    l2 = gen_new_label();
+
+    get_avr64(t0, a->vra, true);
+    get_avr64(t1, a->vrb, true);
+    tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, l1);
+
+    get_avr64(t0, a->vra, false);
+    get_avr64(t1, a->vrb, false);
+    tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, l1);
+
+    set_avr64(a->vrt, tcg_constant_i64(-1), true);
+    set_avr64(a->vrt, tcg_constant_i64(-1), false);
+    if (a->rc) {
+        tcg_gen_movi_i32(cpu_crf[6], 1 << 3);
+    }
+    tcg_gen_br(l2);
+
+    gen_set_label(l1);
+    set_avr64(a->vrt, tcg_constant_i64(0), true);
+    set_avr64(a->vrt, tcg_constant_i64(0), false);
+    if (a->rc) {
+        tcg_gen_movi_i32(cpu_crf[6], 1 << 1);
+    }
+
+    gen_set_label(l2);
+
+    tcg_temp_free_i64(t0);
+    tcg_temp_free_i64(t1);
+
+    return true;
+}
+
 GEN_VXRFORM(vcmpeqfp, 3, 3)
 GEN_VXRFORM(vcmpgefp, 3, 7)
 GEN_VXRFORM(vcmpgtfp, 3, 11)
-- 
2.31.1
Re: [PATCH v3 11/37] target/ppc: Implement Vector Compare Equal Quadword
Posted by Richard Henderson 3 years, 12 months ago 
On 2/10/22 23:34, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst <matheus.ferst@eldorado.org.br>
> 
> Implement the following PowerISA v3.1 instructions:
> vcmpequq Vector Compare Equal Quadword
> 
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
> ---
>   target/ppc/insn32.decode            |  1 +
>   target/ppc/translate/vmx-impl.c.inc | 43 +++++++++++++++++++++++++++++
>   2 files changed, 44 insertions(+)
> 
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> index a0adf18671..39730df32d 100644
> --- a/target/ppc/insn32.decode
> +++ b/target/ppc/insn32.decode
> @@ -382,6 +382,7 @@ VCMPEQUB        000100 ..... ..... ..... . 0000000110   @VC
>   VCMPEQUH        000100 ..... ..... ..... . 0001000110   @VC
>   VCMPEQUW        000100 ..... ..... ..... . 0010000110   @VC
>   VCMPEQUD        000100 ..... ..... ..... . 0011000111   @VC
> +VCMPEQUQ        000100 ..... ..... ..... . 0111000111   @VC
>   
>   VCMPGTSB        000100 ..... ..... ..... . 1100000110   @VC
>   VCMPGTSH        000100 ..... ..... ..... . 1101000110   @VC
> diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
> index 67059ed9b2..bdb0b4370b 100644
> --- a/target/ppc/translate/vmx-impl.c.inc
> +++ b/target/ppc/translate/vmx-impl.c.inc
> @@ -1112,6 +1112,49 @@ TRANS(VCMPNEZB, do_vcmpnez, MO_8)
>   TRANS(VCMPNEZH, do_vcmpnez, MO_16)
>   TRANS(VCMPNEZW, do_vcmpnez, MO_32)
>   
> +static bool trans_VCMPEQUQ(DisasContext *ctx, arg_VC *a)
> +{
> +    TCGv_i64 t0, t1;
> +    TCGLabel *l1, *l2;
> +
> +    REQUIRE_INSNS_FLAGS2(ctx, ISA310);
> +    REQUIRE_VECTOR(ctx);
> +
> +    t0 = tcg_temp_new_i64();
> +    t1 = tcg_temp_new_i64();
> +    l1 = gen_new_label();
> +    l2 = gen_new_label();
> +
> +    get_avr64(t0, a->vra, true);
> +    get_avr64(t1, a->vrb, true);
> +    tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, l1);
> +
> +    get_avr64(t0, a->vra, false);
> +    get_avr64(t1, a->vrb, false);
> +    tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, l1);

It would be much better to not use a branch.
E.g.

     get_avr64(t0, a->vra, true);
     get_avr64(t1, a->vrb, true);
     tcg_gen_xor_i64(c0, t0, t1);

     get_avr64(t0, a->vra, false);
     get_avr64(t1, a->vrb, false);
     tcg_gen_xor_i64(c1, t0, t1);

     tcg_gen_or_i64(c0, c0, c1);
     tcg_gen_setcondi_i64(TCG_COND_EQ, c0, c0, 0);
     tcg_gen_neg_i64(c0, c0);

     set_avr64(a->vrt, c0, true);
     set_avr64(a->vrt, c0, false);

     tcg_gen_extrl_i64_i32(crf, c0);
     tcg_gen_andi_i32(crf, crf, 0xa);
     tcg_gen_xori_i32(crf, crf, 0x2);


r~

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