From: Matheus Ferst <matheus.ferst@eldorado.org.br>
This patch series implements 5 missing instructions from PowerISA v3.0
and 58 new instructions from PowerISA v3.1, moving 87 other instructions
to decodetree along the way.
Patches without review: 4, 24, 26, 27, 34, 35, 38, 40, 44-46
This series can also be found at:
https://github.com/PPC64/qemu/tree/ppc-isa31-2112-v5
v5:
- 2 new instructions: vrlqnm/vrlqmi;
- DEF_HELPER_FLAGS_N with TCG_CALL_NO_RWG where possible (rth);
- Other fixes/optimizations (rth).
v4:
- Rebase on master;
- 16 new instructions: vs[lr]q, vrlq, vextsd2q, lxvr[bhwd]x/stxvr[bhwd]x,
plxssp/pstxssp and plxsd/pstxsd;
- Multiple fixes/optimizations (rth)
v3:
- Dropped patch 33, which caused a regression in xxperm[r]
v2:
- New patch (30) to remove xscmpnedp
Leandro Lupori (2):
target/ppc: implement plxsd/pstxsd
target/ppc: implement plxssp/pstxssp
Lucas Coutinho (3):
target/ppc: Move vexts[bhw]2[wd] to decodetree
target/ppc: Implement vextsd2q
target/ppc: implement lxvr[bhwd]/stxvr[bhwd]x
Lucas Mateus Castro (alqotel) (3):
target/ppc: moved vector even and odd multiplication to decodetree
target/ppc: Moved vector multiply high and low to decodetree
target/ppc: vmulh* instructions without helpers
Luis Pires (1):
target/ppc: Introduce TRANS*FLAGS macros
Matheus Ferst (29):
target/ppc: Move Vector Compare Equal/Not Equal/Greater Than to
decodetree
target/ppc: Move Vector Compare Not Equal or Zero to decodetree
target/ppc: Implement Vector Compare Equal Quadword
target/ppc: Implement Vector Compare Greater Than Quadword
target/ppc: Implement Vector Compare Quadword
target/ppc: implement vstri[bh][lr]
target/ppc: implement vclrlb
target/ppc: implement vclrrb
target/ppc: implement vcntmb[bhwd]
target/ppc: implement vgnb
target/ppc: move vs[lr][a][bhwd] to decodetree
target/ppc: implement vslq
target/ppc: implement vsrq
target/ppc: implement vsraq
target/ppc: move vrl[bhwd] to decodetree
target/ppc: move vrl[bhwd]nm/vrl[bhwd]mi to decodetree
target/ppc: implement vrlq
target/ppc: implement vrlqnm
target/ppc: implement vrlqmi
target/ppc: Move vsel and vperm/vpermr to decodetree
target/ppc: Move xxsel to decodetree
target/ppc: move xxperm/xxpermr to decodetree
target/ppc: Move xxpermdi to decodetree
target/ppc: Implement xxpermx instruction
tcg/tcg-op-gvec.c: Introduce tcg_gen_gvec_4i
target/ppc: Implement xxeval
target/ppc: Implement xxgenpcv[bhwd]m instruction
target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetree
target/ppc: implement xs[n]maddqp[o]/xs[n]msubqp[o]
Víctor Colombo (11):
target/ppc: Implement vmsumcud instruction
target/ppc: Implement vmsumudm instruction
target/ppc: Implement xvtlsbb instruction
target/ppc: Remove xscmpnedp instruction
target/ppc: Refactor VSX_SCALAR_CMP_DP
target/ppc: Implement xscmp{eq,ge,gt}qp
target/ppc: Move xscmp{eq,ge,gt}dp to decodetree
target/ppc: Move xs{max, min}[cj]dp to use do_helper_XX3
target/ppc: Refactor VSX_MAX_MINC helper
target/ppc: Implement xs{max,min}cqp
target/ppc: Implement xvcvbf16spn and xvcvspbf16 instructions
include/tcg/tcg-op-gvec.h | 22 +
target/ppc/fpu_helper.c | 221 +++--
target/ppc/helper.h | 155 ++-
target/ppc/insn32.decode | 234 ++++-
target/ppc/insn64.decode | 56 +-
target/ppc/int_helper.c | 408 ++++----
target/ppc/translate.c | 58 +-
target/ppc/translate/vmx-impl.c.inc | 1348 +++++++++++++++++++++++++--
target/ppc/translate/vmx-ops.c.inc | 59 +-
target/ppc/translate/vsx-impl.c.inc | 842 ++++++++++++++---
target/ppc/translate/vsx-ops.c.inc | 67 --
tcg/ppc/tcg-target.c.inc | 6 +
tcg/tcg-op-gvec.c | 146 +++
13 files changed, 2845 insertions(+), 777 deletions(-)
--
2.25.1