| 1 | From: Alistair Francis <alistair.francis@wdc.com> | 1 | From: Alistair Francis <alistair.francis@wdc.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The following changes since commit c5fbdd60cf1fb52f01bdfe342b6fa65d5343e1b1: | 3 | The following changes since commit 2ba341b3694cf3cff7b8a1df4cc765900d5c4f60: |
| 4 | 4 | ||
| 5 | Merge tag 'qemu-sparc-20211121' of git://github.com/mcayland/qemu into staging (2021-11-21 14:12:25 +0100) | 5 | Merge tag 'kraxel-20221013-pull-request' of https://gitlab.com/kraxel/qemu into staging (2022-10-13 13:55:53 -0400) |
| 6 | 6 | ||
| 7 | are available in the Git repository at: | 7 | are available in the Git repository at: |
| 8 | 8 | ||
| 9 | git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211122 | 9 | https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20221014 |
| 10 | 10 | ||
| 11 | for you to fetch changes up to 526e7443027c71fe7b04c29df529e1f9f425f9e3: | 11 | for you to fetch changes up to 47566421f029b0a489b63f8195b3ff944e017056: |
| 12 | 12 | ||
| 13 | hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset (2021-11-22 10:46:22 +1000) | 13 | target/riscv: pmp: Fixup TLB size calculation (2022-10-14 14:36:19 +1000) |
| 14 | 14 | ||
| 15 | ---------------------------------------------------------------- | 15 | ---------------------------------------------------------------- |
| 16 | Seventh RISC-V PR for QEMU 6.2 | 16 | Third RISC-V PR for QEMU 7.2 |
| 17 | 17 | ||
| 18 | - Deprecate IF_NONE for SiFive OTP | 18 | * Update qtest comment |
| 19 | - Don't reset SiFive OTP content | 19 | * Fix coverity issue with Ibex SPI |
| 20 | * Move load_image_to_fw_cfg() to common location | ||
| 21 | * Enable booting S-mode firmware from pflash on virt machine | ||
| 22 | * Add disas support for vector instructions | ||
| 23 | * Priority level fixes for PLIC | ||
| 24 | * Fixup TLB size calculation when using PMP | ||
| 20 | 25 | ||
| 21 | ---------------------------------------------------------------- | 26 | ---------------------------------------------------------------- |
| 22 | Philippe Mathieu-Daudé (1): | 27 | Alistair Francis (1): |
| 23 | hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset | 28 | target/riscv: pmp: Fixup TLB size calculation |
| 24 | 29 | ||
| 25 | Thomas Huth (1): | 30 | Bin Meng (1): |
| 26 | hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE | 31 | hw/riscv: Update comment for qtest check in riscv_find_firmware() |
| 27 | 32 | ||
| 28 | docs/about/deprecated.rst | 6 ++++++ | 33 | Jim Shu (2): |
| 29 | hw/misc/sifive_u_otp.c | 22 +++++++++++++--------- | 34 | hw/intc: sifive_plic: fix hard-coded max priority level |
| 30 | 2 files changed, 19 insertions(+), 9 deletions(-) | 35 | hw/intc: sifive_plic: change interrupt priority register to WARL field |
| 31 | 36 | ||
| 37 | Sunil V L (3): | ||
| 38 | hw/arm, loongarch: Move load_image_to_fw_cfg() to common location | ||
| 39 | hw/riscv: virt: Move create_fw_cfg() prior to loading kernel | ||
| 40 | hw/riscv: virt: Enable booting S-mode firmware from pflash | ||
| 41 | |||
| 42 | Wilfred Mallawa (2): | ||
| 43 | hw/ssi: ibex_spi: fixup coverity issue | ||
| 44 | hw/ssi: ibex_spi: fixup/add rw1c functionality | ||
| 45 | |||
| 46 | Yang Liu (1): | ||
| 47 | disas/riscv.c: rvv: Add disas support for vector instructions | ||
| 48 | |||
| 49 | include/hw/nvram/fw_cfg.h | 21 + | ||
| 50 | include/hw/riscv/boot.h | 1 + | ||
| 51 | include/hw/ssi/ibex_spi_host.h | 4 +- | ||
| 52 | disas/riscv.c | 1432 +++++++++++++++++++++++++++++++++++++++- | ||
| 53 | hw/arm/boot.c | 49 -- | ||
| 54 | hw/intc/sifive_plic.c | 25 +- | ||
| 55 | hw/loongarch/virt.c | 33 - | ||
| 56 | hw/nvram/fw_cfg.c | 32 + | ||
| 57 | hw/riscv/boot.c | 33 +- | ||
| 58 | hw/riscv/virt.c | 32 +- | ||
| 59 | hw/ssi/ibex_spi_host.c | 166 +++-- | ||
| 60 | target/riscv/pmp.c | 12 + | ||
| 61 | 12 files changed, 1675 insertions(+), 165 deletions(-) | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Bin Meng <bmeng.cn@gmail.com> | ||
| 1 | 2 | ||
| 3 | Since commit 4211fc553234 ("roms/opensbi: Remove ELF images"), the | ||
| 4 | comment for qtest check in riscv_find_firmware() is out of date. | ||
| 5 | Update it to reflect the latest status. | ||
| 6 | |||
| 7 | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> | ||
| 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 9 | Message-Id: <BN7PR08MB435525C92550BAC5467BE672BF219@BN7PR08MB4355.namprd08.prod.outlook.com> | ||
| 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 11 | --- | ||
| 12 | hw/riscv/boot.c | 4 ++-- | ||
| 13 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
| 14 | |||
| 15 | diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/hw/riscv/boot.c | ||
| 18 | +++ b/hw/riscv/boot.c | ||
| 19 | @@ -XXX,XX +XXX,XX @@ char *riscv_find_firmware(const char *firmware_filename) | ||
| 20 | if (filename == NULL) { | ||
| 21 | if (!qtest_enabled()) { | ||
| 22 | /* | ||
| 23 | - * We only ship plain binary bios images in the QEMU source. | ||
| 24 | - * With Spike machine that uses ELF images as the default bios, | ||
| 25 | + * We only ship OpenSBI binary bios images in the QEMU source. | ||
| 26 | + * For machines that use images other than the default bios, | ||
| 27 | * running QEMU test will complain hence let's suppress the error | ||
| 28 | * report for QEMU testing. | ||
| 29 | */ | ||
| 30 | -- | ||
| 31 | 2.37.3 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | 1 | From: Wilfred Mallawa <wilfred.mallawa@wdc.com> | |
| 2 | |||
| 3 | This patch addresses the coverity issues specified in [1], | ||
| 4 | as suggested, `FIELD_DP32()`/`FIELD_EX32()` macros have been | ||
| 5 | implemented to clean up the code. | ||
| 6 | |||
| 7 | [1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg887713.html | ||
| 8 | |||
| 9 | Fixes: Coverity CID 1488107 | ||
| 10 | |||
| 11 | Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> | ||
| 12 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 13 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
| 14 | Message-Id: <20220930033241.206581-2-wilfred.mallawa@opensource.wdc.com> | ||
| 15 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 16 | --- | ||
| 17 | hw/ssi/ibex_spi_host.c | 132 +++++++++++++++++++++-------------------- | ||
| 18 | 1 file changed, 68 insertions(+), 64 deletions(-) | ||
| 19 | |||
| 20 | diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | ||
| 22 | --- a/hw/ssi/ibex_spi_host.c | ||
| 23 | +++ b/hw/ssi/ibex_spi_host.c | ||
| 24 | @@ -XXX,XX +XXX,XX @@ static inline uint8_t div4_round_up(uint8_t dividend) | ||
| 25 | |||
| 26 | static void ibex_spi_rxfifo_reset(IbexSPIHostState *s) | ||
| 27 | { | ||
| 28 | + uint32_t data = s->regs[IBEX_SPI_HOST_STATUS]; | ||
| 29 | /* Empty the RX FIFO and assert RXEMPTY */ | ||
| 30 | fifo8_reset(&s->rx_fifo); | ||
| 31 | - s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_RXFULL_MASK; | ||
| 32 | - s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_RXEMPTY_MASK; | ||
| 33 | + data = FIELD_DP32(data, STATUS, RXFULL, 0); | ||
| 34 | + data = FIELD_DP32(data, STATUS, RXEMPTY, 1); | ||
| 35 | + s->regs[IBEX_SPI_HOST_STATUS] = data; | ||
| 36 | } | ||
| 37 | |||
| 38 | static void ibex_spi_txfifo_reset(IbexSPIHostState *s) | ||
| 39 | { | ||
| 40 | + uint32_t data = s->regs[IBEX_SPI_HOST_STATUS]; | ||
| 41 | /* Empty the TX FIFO and assert TXEMPTY */ | ||
| 42 | fifo8_reset(&s->tx_fifo); | ||
| 43 | - s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_TXFULL_MASK; | ||
| 44 | - s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_TXEMPTY_MASK; | ||
| 45 | + data = FIELD_DP32(data, STATUS, TXFULL, 0); | ||
| 46 | + data = FIELD_DP32(data, STATUS, TXEMPTY, 1); | ||
| 47 | + s->regs[IBEX_SPI_HOST_STATUS] = data; | ||
| 48 | } | ||
| 49 | |||
| 50 | static void ibex_spi_host_reset(DeviceState *dev) | ||
| 51 | @@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_reset(DeviceState *dev) | ||
| 52 | */ | ||
| 53 | static void ibex_spi_host_irq(IbexSPIHostState *s) | ||
| 54 | { | ||
| 55 | - bool error_en = s->regs[IBEX_SPI_HOST_INTR_ENABLE] | ||
| 56 | - & R_INTR_ENABLE_ERROR_MASK; | ||
| 57 | - bool event_en = s->regs[IBEX_SPI_HOST_INTR_ENABLE] | ||
| 58 | - & R_INTR_ENABLE_SPI_EVENT_MASK; | ||
| 59 | - bool err_pending = s->regs[IBEX_SPI_HOST_INTR_STATE] | ||
| 60 | - & R_INTR_STATE_ERROR_MASK; | ||
| 61 | - bool status_pending = s->regs[IBEX_SPI_HOST_INTR_STATE] | ||
| 62 | - & R_INTR_STATE_SPI_EVENT_MASK; | ||
| 63 | + uint32_t intr_test_reg = s->regs[IBEX_SPI_HOST_INTR_TEST]; | ||
| 64 | + uint32_t intr_en_reg = s->regs[IBEX_SPI_HOST_INTR_ENABLE]; | ||
| 65 | + uint32_t intr_state_reg = s->regs[IBEX_SPI_HOST_INTR_STATE]; | ||
| 66 | + | ||
| 67 | + uint32_t err_en_reg = s->regs[IBEX_SPI_HOST_ERROR_ENABLE]; | ||
| 68 | + uint32_t event_en_reg = s->regs[IBEX_SPI_HOST_EVENT_ENABLE]; | ||
| 69 | + uint32_t err_status_reg = s->regs[IBEX_SPI_HOST_ERROR_STATUS]; | ||
| 70 | + uint32_t status_reg = s->regs[IBEX_SPI_HOST_STATUS]; | ||
| 71 | + | ||
| 72 | + | ||
| 73 | + bool error_en = FIELD_EX32(intr_en_reg, INTR_ENABLE, ERROR); | ||
| 74 | + bool event_en = FIELD_EX32(intr_en_reg, INTR_ENABLE, SPI_EVENT); | ||
| 75 | + bool err_pending = FIELD_EX32(intr_state_reg, INTR_STATE, ERROR); | ||
| 76 | + bool status_pending = FIELD_EX32(intr_state_reg, INTR_STATE, SPI_EVENT); | ||
| 77 | + | ||
| 78 | int err_irq = 0, event_irq = 0; | ||
| 79 | |||
| 80 | /* Error IRQ enabled and Error IRQ Cleared */ | ||
| 81 | if (error_en && !err_pending) { | ||
| 82 | /* Event enabled, Interrupt Test Error */ | ||
| 83 | - if (s->regs[IBEX_SPI_HOST_INTR_TEST] & R_INTR_TEST_ERROR_MASK) { | ||
| 84 | + if (FIELD_EX32(intr_test_reg, INTR_TEST, ERROR)) { | ||
| 85 | err_irq = 1; | ||
| 86 | - } else if ((s->regs[IBEX_SPI_HOST_ERROR_ENABLE] | ||
| 87 | - & R_ERROR_ENABLE_CMDBUSY_MASK) && | ||
| 88 | - s->regs[IBEX_SPI_HOST_ERROR_STATUS] | ||
| 89 | - & R_ERROR_STATUS_CMDBUSY_MASK) { | ||
| 90 | + } else if (FIELD_EX32(err_en_reg, ERROR_ENABLE, CMDBUSY) && | ||
| 91 | + FIELD_EX32(err_status_reg, ERROR_STATUS, CMDBUSY)) { | ||
| 92 | /* Wrote to COMMAND when not READY */ | ||
| 93 | err_irq = 1; | ||
| 94 | - } else if ((s->regs[IBEX_SPI_HOST_ERROR_ENABLE] | ||
| 95 | - & R_ERROR_ENABLE_CMDINVAL_MASK) && | ||
| 96 | - s->regs[IBEX_SPI_HOST_ERROR_STATUS] | ||
| 97 | - & R_ERROR_STATUS_CMDINVAL_MASK) { | ||
| 98 | + } else if (FIELD_EX32(err_en_reg, ERROR_ENABLE, CMDINVAL) && | ||
| 99 | + FIELD_EX32(err_status_reg, ERROR_STATUS, CMDINVAL)) { | ||
| 100 | /* Invalid command segment */ | ||
| 101 | err_irq = 1; | ||
| 102 | - } else if ((s->regs[IBEX_SPI_HOST_ERROR_ENABLE] | ||
| 103 | - & R_ERROR_ENABLE_CSIDINVAL_MASK) && | ||
| 104 | - s->regs[IBEX_SPI_HOST_ERROR_STATUS] | ||
| 105 | - & R_ERROR_STATUS_CSIDINVAL_MASK) { | ||
| 106 | + } else if (FIELD_EX32(err_en_reg, ERROR_ENABLE, CSIDINVAL) && | ||
| 107 | + FIELD_EX32(err_status_reg, ERROR_STATUS, CSIDINVAL)) { | ||
| 108 | /* Invalid value for CSID */ | ||
| 109 | err_irq = 1; | ||
| 110 | } | ||
| 111 | @@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_irq(IbexSPIHostState *s) | ||
| 112 | |||
| 113 | /* Event IRQ Enabled and Event IRQ Cleared */ | ||
| 114 | if (event_en && !status_pending) { | ||
| 115 | - if (s->regs[IBEX_SPI_HOST_INTR_TEST] & R_INTR_TEST_SPI_EVENT_MASK) { | ||
| 116 | + if (FIELD_EX32(intr_test_reg, INTR_STATE, SPI_EVENT)) { | ||
| 117 | /* Event enabled, Interrupt Test Event */ | ||
| 118 | event_irq = 1; | ||
| 119 | - } else if ((s->regs[IBEX_SPI_HOST_EVENT_ENABLE] | ||
| 120 | - & R_EVENT_ENABLE_READY_MASK) && | ||
| 121 | - (s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_READY_MASK)) { | ||
| 122 | + } else if (FIELD_EX32(event_en_reg, EVENT_ENABLE, READY) && | ||
| 123 | + FIELD_EX32(status_reg, STATUS, READY)) { | ||
| 124 | /* SPI Host ready for next command */ | ||
| 125 | event_irq = 1; | ||
| 126 | - } else if ((s->regs[IBEX_SPI_HOST_EVENT_ENABLE] | ||
| 127 | - & R_EVENT_ENABLE_TXEMPTY_MASK) && | ||
| 128 | - (s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_TXEMPTY_MASK)) { | ||
| 129 | + } else if (FIELD_EX32(event_en_reg, EVENT_ENABLE, TXEMPTY) && | ||
| 130 | + FIELD_EX32(status_reg, STATUS, TXEMPTY)) { | ||
| 131 | /* SPI TXEMPTY, TXFIFO drained */ | ||
| 132 | event_irq = 1; | ||
| 133 | - } else if ((s->regs[IBEX_SPI_HOST_EVENT_ENABLE] | ||
| 134 | - & R_EVENT_ENABLE_RXFULL_MASK) && | ||
| 135 | - (s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_RXFULL_MASK)) { | ||
| 136 | + } else if (FIELD_EX32(event_en_reg, EVENT_ENABLE, RXFULL) && | ||
| 137 | + FIELD_EX32(status_reg, STATUS, RXFULL)) { | ||
| 138 | /* SPI RXFULL, RXFIFO full */ | ||
| 139 | event_irq = 1; | ||
| 140 | } | ||
| 141 | @@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_irq(IbexSPIHostState *s) | ||
| 142 | |||
| 143 | static void ibex_spi_host_transfer(IbexSPIHostState *s) | ||
| 144 | { | ||
| 145 | - uint32_t rx, tx; | ||
| 146 | + uint32_t rx, tx, data; | ||
| 147 | /* Get num of one byte transfers */ | ||
| 148 | - uint8_t segment_len = ((s->regs[IBEX_SPI_HOST_COMMAND] & R_COMMAND_LEN_MASK) | ||
| 149 | - >> R_COMMAND_LEN_SHIFT); | ||
| 150 | + uint8_t segment_len = FIELD_EX32(s->regs[IBEX_SPI_HOST_COMMAND], | ||
| 151 | + COMMAND, LEN); | ||
| 152 | + | ||
| 153 | while (segment_len > 0) { | ||
| 154 | if (fifo8_is_empty(&s->tx_fifo)) { | ||
| 155 | /* Assert Stall */ | ||
| 156 | @@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_transfer(IbexSPIHostState *s) | ||
| 157 | --segment_len; | ||
| 158 | } | ||
| 159 | |||
| 160 | + data = s->regs[IBEX_SPI_HOST_STATUS]; | ||
| 161 | /* Assert Ready */ | ||
| 162 | - s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_READY_MASK; | ||
| 163 | + data = FIELD_DP32(data, STATUS, READY, 1); | ||
| 164 | /* Set RXQD */ | ||
| 165 | - s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_RXQD_MASK; | ||
| 166 | - s->regs[IBEX_SPI_HOST_STATUS] |= (R_STATUS_RXQD_MASK | ||
| 167 | - & div4_round_up(segment_len)); | ||
| 168 | + data = FIELD_DP32(data, STATUS, RXQD, div4_round_up(segment_len)); | ||
| 169 | /* Set TXQD */ | ||
| 170 | - s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_TXQD_MASK; | ||
| 171 | - s->regs[IBEX_SPI_HOST_STATUS] |= (fifo8_num_used(&s->tx_fifo) / 4) | ||
| 172 | - & R_STATUS_TXQD_MASK; | ||
| 173 | + data = FIELD_DP32(data, STATUS, TXQD, fifo8_num_used(&s->tx_fifo) / 4); | ||
| 174 | /* Clear TXFULL */ | ||
| 175 | - s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_TXFULL_MASK; | ||
| 176 | - /* Assert TXEMPTY and drop remaining bytes that exceed segment_len */ | ||
| 177 | - ibex_spi_txfifo_reset(s); | ||
| 178 | + data = FIELD_DP32(data, STATUS, TXFULL, 0); | ||
| 179 | /* Reset RXEMPTY */ | ||
| 180 | - s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_RXEMPTY_MASK; | ||
| 181 | + data = FIELD_DP32(data, STATUS, RXEMPTY, 0); | ||
| 182 | + /* Update register status */ | ||
| 183 | + s->regs[IBEX_SPI_HOST_STATUS] = data; | ||
| 184 | + /* Drop remaining bytes that exceed segment_len */ | ||
| 185 | + ibex_spi_txfifo_reset(s); | ||
| 186 | |||
| 187 | ibex_spi_host_irq(s); | ||
| 188 | } | ||
| 189 | @@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr, | ||
| 190 | { | ||
| 191 | IbexSPIHostState *s = opaque; | ||
| 192 | uint32_t val32 = val64; | ||
| 193 | - uint32_t shift_mask = 0xff; | ||
| 194 | + uint32_t shift_mask = 0xff, status = 0; | ||
| 195 | uint8_t txqd_len; | ||
| 196 | |||
| 197 | trace_ibex_spi_host_write(addr, size, val64); | ||
| 198 | @@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr, | ||
| 199 | s->regs[addr] = val32; | ||
| 200 | |||
| 201 | /* STALL, IP not enabled */ | ||
| 202 | - if (!(s->regs[IBEX_SPI_HOST_CONTROL] & R_CONTROL_SPIEN_MASK)) { | ||
| 203 | + if (!(FIELD_EX32(s->regs[IBEX_SPI_HOST_CONTROL], | ||
| 204 | + CONTROL, SPIEN))) { | ||
| 205 | return; | ||
| 206 | } | ||
| 207 | |||
| 208 | /* SPI not ready, IRQ Error */ | ||
| 209 | - if (!(s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_READY_MASK)) { | ||
| 210 | + if (!(FIELD_EX32(s->regs[IBEX_SPI_HOST_STATUS], | ||
| 211 | + STATUS, READY))) { | ||
| 212 | s->regs[IBEX_SPI_HOST_ERROR_STATUS] |= R_ERROR_STATUS_CMDBUSY_MASK; | ||
| 213 | ibex_spi_host_irq(s); | ||
| 214 | return; | ||
| 215 | } | ||
| 216 | + | ||
| 217 | /* Assert Not Ready */ | ||
| 218 | s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_READY_MASK; | ||
| 219 | |||
| 220 | - if (((val32 & R_COMMAND_DIRECTION_MASK) >> R_COMMAND_DIRECTION_SHIFT) | ||
| 221 | - != BIDIRECTIONAL_TRANSFER) { | ||
| 222 | - qemu_log_mask(LOG_UNIMP, | ||
| 223 | + if (FIELD_EX32(val32, COMMAND, DIRECTION) != BIDIRECTIONAL_TRANSFER) { | ||
| 224 | + qemu_log_mask(LOG_UNIMP, | ||
| 225 | "%s: Rx Only/Tx Only are not supported\n", __func__); | ||
| 226 | } | ||
| 227 | |||
| 228 | @@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr, | ||
| 229 | return; | ||
| 230 | } | ||
| 231 | /* Byte ordering is set by the IP */ | ||
| 232 | - if ((s->regs[IBEX_SPI_HOST_STATUS] & | ||
| 233 | - R_STATUS_BYTEORDER_MASK) == 0) { | ||
| 234 | + status = s->regs[IBEX_SPI_HOST_STATUS]; | ||
| 235 | + if (FIELD_EX32(status, STATUS, BYTEORDER) == 0) { | ||
| 236 | /* LE: LSB transmitted first (default for ibex processor) */ | ||
| 237 | shift_mask = 0xff << (i * 8); | ||
| 238 | } else { | ||
| 239 | @@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr, | ||
| 240 | |||
| 241 | fifo8_push(&s->tx_fifo, (val32 & shift_mask) >> (i * 8)); | ||
| 242 | } | ||
| 243 | - | ||
| 244 | + status = s->regs[IBEX_SPI_HOST_STATUS]; | ||
| 245 | /* Reset TXEMPTY */ | ||
| 246 | - s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_TXEMPTY_MASK; | ||
| 247 | + status = FIELD_DP32(status, STATUS, TXEMPTY, 0); | ||
| 248 | /* Update TXQD */ | ||
| 249 | - txqd_len = (s->regs[IBEX_SPI_HOST_STATUS] & | ||
| 250 | - R_STATUS_TXQD_MASK) >> R_STATUS_TXQD_SHIFT; | ||
| 251 | + txqd_len = FIELD_EX32(status, STATUS, TXQD); | ||
| 252 | /* Partial bytes (size < 4) are padded, in words. */ | ||
| 253 | txqd_len += 1; | ||
| 254 | - s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_TXQD_MASK; | ||
| 255 | - s->regs[IBEX_SPI_HOST_STATUS] |= txqd_len; | ||
| 256 | + status = FIELD_DP32(status, STATUS, TXQD, txqd_len); | ||
| 257 | /* Assert Ready */ | ||
| 258 | - s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_READY_MASK; | ||
| 259 | + status = FIELD_DP32(status, STATUS, READY, 1); | ||
| 260 | + /* Update register status */ | ||
| 261 | + s->regs[IBEX_SPI_HOST_STATUS] = status; | ||
| 262 | break; | ||
| 263 | case IBEX_SPI_HOST_ERROR_ENABLE: | ||
| 264 | s->regs[addr] = val32; | ||
| 265 | -- | ||
| 266 | 2.37.3 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Wilfred Mallawa <wilfred.mallawa@wdc.com> | ||
| 1 | 2 | ||
| 3 | This patch adds the `rw1c` functionality to the respective | ||
| 4 | registers. The status fields are cleared when the respective | ||
| 5 | field is set. | ||
| 6 | |||
| 7 | Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> | ||
| 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 9 | Message-Id: <20220930033241.206581-3-wilfred.mallawa@opensource.wdc.com> | ||
| 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 11 | --- | ||
| 12 | include/hw/ssi/ibex_spi_host.h | 4 ++-- | ||
| 13 | hw/ssi/ibex_spi_host.c | 36 +++++++++++++++++++++++++++++++--- | ||
| 14 | 2 files changed, 35 insertions(+), 5 deletions(-) | ||
| 15 | |||
| 16 | diff --git a/include/hw/ssi/ibex_spi_host.h b/include/hw/ssi/ibex_spi_host.h | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/include/hw/ssi/ibex_spi_host.h | ||
| 19 | +++ b/include/hw/ssi/ibex_spi_host.h | ||
| 20 | @@ -XXX,XX +XXX,XX @@ | ||
| 21 | OBJECT_CHECK(IbexSPIHostState, (obj), TYPE_IBEX_SPI_HOST) | ||
| 22 | |||
| 23 | /* SPI Registers */ | ||
| 24 | -#define IBEX_SPI_HOST_INTR_STATE (0x00 / 4) /* rw */ | ||
| 25 | +#define IBEX_SPI_HOST_INTR_STATE (0x00 / 4) /* rw1c */ | ||
| 26 | #define IBEX_SPI_HOST_INTR_ENABLE (0x04 / 4) /* rw */ | ||
| 27 | #define IBEX_SPI_HOST_INTR_TEST (0x08 / 4) /* wo */ | ||
| 28 | #define IBEX_SPI_HOST_ALERT_TEST (0x0c / 4) /* wo */ | ||
| 29 | @@ -XXX,XX +XXX,XX @@ | ||
| 30 | #define IBEX_SPI_HOST_TXDATA (0x28 / 4) | ||
| 31 | |||
| 32 | #define IBEX_SPI_HOST_ERROR_ENABLE (0x2c / 4) /* rw */ | ||
| 33 | -#define IBEX_SPI_HOST_ERROR_STATUS (0x30 / 4) /* rw */ | ||
| 34 | +#define IBEX_SPI_HOST_ERROR_STATUS (0x30 / 4) /* rw1c */ | ||
| 35 | #define IBEX_SPI_HOST_EVENT_ENABLE (0x34 / 4) /* rw */ | ||
| 36 | |||
| 37 | /* FIFO Len in Bytes */ | ||
| 38 | diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c | ||
| 39 | index XXXXXXX..XXXXXXX 100644 | ||
| 40 | --- a/hw/ssi/ibex_spi_host.c | ||
| 41 | +++ b/hw/ssi/ibex_spi_host.c | ||
| 42 | @@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr, | ||
| 43 | { | ||
| 44 | IbexSPIHostState *s = opaque; | ||
| 45 | uint32_t val32 = val64; | ||
| 46 | - uint32_t shift_mask = 0xff, status = 0; | ||
| 47 | + uint32_t shift_mask = 0xff, status = 0, data = 0; | ||
| 48 | uint8_t txqd_len; | ||
| 49 | |||
| 50 | trace_ibex_spi_host_write(addr, size, val64); | ||
| 51 | @@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr, | ||
| 52 | |||
| 53 | switch (addr) { | ||
| 54 | /* Skipping any R/O registers */ | ||
| 55 | - case IBEX_SPI_HOST_INTR_STATE...IBEX_SPI_HOST_INTR_ENABLE: | ||
| 56 | + case IBEX_SPI_HOST_INTR_STATE: | ||
| 57 | + /* rw1c status register */ | ||
| 58 | + if (FIELD_EX32(val32, INTR_STATE, ERROR)) { | ||
| 59 | + data = FIELD_DP32(data, INTR_STATE, ERROR, 0); | ||
| 60 | + } | ||
| 61 | + if (FIELD_EX32(val32, INTR_STATE, SPI_EVENT)) { | ||
| 62 | + data = FIELD_DP32(data, INTR_STATE, SPI_EVENT, 0); | ||
| 63 | + } | ||
| 64 | + s->regs[addr] = data; | ||
| 65 | + break; | ||
| 66 | + case IBEX_SPI_HOST_INTR_ENABLE: | ||
| 67 | s->regs[addr] = val32; | ||
| 68 | break; | ||
| 69 | case IBEX_SPI_HOST_INTR_TEST: | ||
| 70 | @@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr, | ||
| 71 | * When an error occurs, the corresponding bit must be cleared | ||
| 72 | * here before issuing any further commands | ||
| 73 | */ | ||
| 74 | - s->regs[addr] = val32; | ||
| 75 | + status = s->regs[addr]; | ||
| 76 | + /* rw1c status register */ | ||
| 77 | + if (FIELD_EX32(val32, ERROR_STATUS, CMDBUSY)) { | ||
| 78 | + status = FIELD_DP32(status, ERROR_STATUS, CMDBUSY, 0); | ||
| 79 | + } | ||
| 80 | + if (FIELD_EX32(val32, ERROR_STATUS, OVERFLOW)) { | ||
| 81 | + status = FIELD_DP32(status, ERROR_STATUS, OVERFLOW, 0); | ||
| 82 | + } | ||
| 83 | + if (FIELD_EX32(val32, ERROR_STATUS, UNDERFLOW)) { | ||
| 84 | + status = FIELD_DP32(status, ERROR_STATUS, UNDERFLOW, 0); | ||
| 85 | + } | ||
| 86 | + if (FIELD_EX32(val32, ERROR_STATUS, CMDINVAL)) { | ||
| 87 | + status = FIELD_DP32(status, ERROR_STATUS, CMDINVAL, 0); | ||
| 88 | + } | ||
| 89 | + if (FIELD_EX32(val32, ERROR_STATUS, CSIDINVAL)) { | ||
| 90 | + status = FIELD_DP32(status, ERROR_STATUS, CSIDINVAL, 0); | ||
| 91 | + } | ||
| 92 | + if (FIELD_EX32(val32, ERROR_STATUS, ACCESSINVAL)) { | ||
| 93 | + status = FIELD_DP32(status, ERROR_STATUS, ACCESSINVAL, 0); | ||
| 94 | + } | ||
| 95 | + s->regs[addr] = status; | ||
| 96 | break; | ||
| 97 | case IBEX_SPI_HOST_EVENT_ENABLE: | ||
| 98 | /* Controls which classes of SPI events raise an interrupt. */ | ||
| 99 | -- | ||
| 100 | 2.37.3 | diff view generated by jsdifflib |
| 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Sunil V L <sunilvl@ventanamicro.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Once a "One Time Programmable" is programmed, it shouldn't be reset. | 3 | load_image_to_fw_cfg() is duplicated by both arm and loongarch. The same |
| 4 | function will be required by riscv too. So, it's time to refactor and | ||
| 5 | move this function to a common path. | ||
| 4 | 6 | ||
| 5 | Do not re-initialize the OTP content in the DeviceReset handler, | 7 | Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> |
| 6 | initialize it once in the DeviceRealize one. | 8 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> |
| 7 | |||
| 8 | Fixes: 9fb45c62ae8 ("riscv: sifive: Implement a model for SiFive FU540 OTP") | ||
| 9 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 11 | Message-Id: <20211119104757.331579-1-f4bug@amsat.org> | 10 | Reviewed-by: Song Gao <gaosong@loongson.cn> |
| 11 | Message-Id: <20221004092351.18209-2-sunilvl@ventanamicro.com> | ||
| 12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 13 | --- | 13 | --- |
| 14 | hw/misc/sifive_u_otp.c | 13 +++++-------- | 14 | include/hw/nvram/fw_cfg.h | 21 +++++++++++++++++ |
| 15 | 1 file changed, 5 insertions(+), 8 deletions(-) | 15 | hw/arm/boot.c | 49 --------------------------------------- |
| 16 | hw/loongarch/virt.c | 33 -------------------------- | ||
| 17 | hw/nvram/fw_cfg.c | 32 +++++++++++++++++++++++++ | ||
| 18 | 4 files changed, 53 insertions(+), 82 deletions(-) | ||
| 16 | 19 | ||
| 17 | diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c | 20 | diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h |
| 18 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
| 19 | --- a/hw/misc/sifive_u_otp.c | 22 | --- a/include/hw/nvram/fw_cfg.h |
| 20 | +++ b/hw/misc/sifive_u_otp.c | 23 | +++ b/include/hw/nvram/fw_cfg.h |
| 21 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp) | 24 | @@ -XXX,XX +XXX,XX @@ bool fw_cfg_dma_enabled(void *opaque); |
| 22 | 25 | */ | |
| 23 | if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) { | 26 | const char *fw_cfg_arch_key_name(uint16_t key); |
| 24 | error_setg(errp, "failed to read the initial flash content"); | 27 | |
| 25 | + return; | 28 | +/** |
| 26 | } | 29 | + * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified |
| 27 | } | 30 | + * by key. |
| 31 | + * @fw_cfg: The firmware config instance to store the data in. | ||
| 32 | + * @size_key: The firmware config key to store the size of the loaded | ||
| 33 | + * data under, with fw_cfg_add_i32(). | ||
| 34 | + * @data_key: The firmware config key to store the loaded data under, | ||
| 35 | + * with fw_cfg_add_bytes(). | ||
| 36 | + * @image_name: The name of the image file to load. If it is NULL, the | ||
| 37 | + * function returns without doing anything. | ||
| 38 | + * @try_decompress: Whether the image should be decompressed (gunzipped) before | ||
| 39 | + * adding it to fw_cfg. If decompression fails, the image is | ||
| 40 | + * loaded as-is. | ||
| 41 | + * | ||
| 42 | + * In case of failure, the function prints an error message to stderr and the | ||
| 43 | + * process exits with status 1. | ||
| 44 | + */ | ||
| 45 | +void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key, | ||
| 46 | + uint16_t data_key, const char *image_name, | ||
| 47 | + bool try_decompress); | ||
| 48 | + | ||
| 49 | #endif | ||
| 50 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | ||
| 51 | index XXXXXXX..XXXXXXX 100644 | ||
| 52 | --- a/hw/arm/boot.c | ||
| 53 | +++ b/hw/arm/boot.c | ||
| 54 | @@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque) | ||
| 28 | } | 55 | } |
| 56 | } | ||
| 57 | |||
| 58 | -/** | ||
| 59 | - * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified | ||
| 60 | - * by key. | ||
| 61 | - * @fw_cfg: The firmware config instance to store the data in. | ||
| 62 | - * @size_key: The firmware config key to store the size of the loaded | ||
| 63 | - * data under, with fw_cfg_add_i32(). | ||
| 64 | - * @data_key: The firmware config key to store the loaded data under, | ||
| 65 | - * with fw_cfg_add_bytes(). | ||
| 66 | - * @image_name: The name of the image file to load. If it is NULL, the | ||
| 67 | - * function returns without doing anything. | ||
| 68 | - * @try_decompress: Whether the image should be decompressed (gunzipped) before | ||
| 69 | - * adding it to fw_cfg. If decompression fails, the image is | ||
| 70 | - * loaded as-is. | ||
| 71 | - * | ||
| 72 | - * In case of failure, the function prints an error message to stderr and the | ||
| 73 | - * process exits with status 1. | ||
| 74 | - */ | ||
| 75 | -static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key, | ||
| 76 | - uint16_t data_key, const char *image_name, | ||
| 77 | - bool try_decompress) | ||
| 78 | -{ | ||
| 79 | - size_t size = -1; | ||
| 80 | - uint8_t *data; | ||
| 81 | - | ||
| 82 | - if (image_name == NULL) { | ||
| 83 | - return; | ||
| 84 | - } | ||
| 85 | - | ||
| 86 | - if (try_decompress) { | ||
| 87 | - size = load_image_gzipped_buffer(image_name, | ||
| 88 | - LOAD_IMAGE_MAX_GUNZIP_BYTES, &data); | ||
| 89 | - } | ||
| 90 | - | ||
| 91 | - if (size == (size_t)-1) { | ||
| 92 | - gchar *contents; | ||
| 93 | - gsize length; | ||
| 94 | - | ||
| 95 | - if (!g_file_get_contents(image_name, &contents, &length, NULL)) { | ||
| 96 | - error_report("failed to load \"%s\"", image_name); | ||
| 97 | - exit(1); | ||
| 98 | - } | ||
| 99 | - size = length; | ||
| 100 | - data = (uint8_t *)contents; | ||
| 101 | - } | ||
| 102 | - | ||
| 103 | - fw_cfg_add_i32(fw_cfg, size_key, size); | ||
| 104 | - fw_cfg_add_bytes(fw_cfg, data_key, data, size); | ||
| 29 | -} | 105 | -} |
| 30 | - | 106 | - |
| 31 | -static void sifive_u_otp_reset(DeviceState *dev) | 107 | static int do_arm_linux_init(Object *obj, void *opaque) |
| 108 | { | ||
| 109 | if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) { | ||
| 110 | diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c | ||
| 111 | index XXXXXXX..XXXXXXX 100644 | ||
| 112 | --- a/hw/loongarch/virt.c | ||
| 113 | +++ b/hw/loongarch/virt.c | ||
| 114 | @@ -XXX,XX +XXX,XX @@ static void reset_load_elf(void *opaque) | ||
| 115 | } | ||
| 116 | } | ||
| 117 | |||
| 118 | -/* Load an image file into an fw_cfg entry identified by key. */ | ||
| 119 | -static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key, | ||
| 120 | - uint16_t data_key, const char *image_name, | ||
| 121 | - bool try_decompress) | ||
| 32 | -{ | 122 | -{ |
| 33 | - SiFiveUOTPState *s = SIFIVE_U_OTP(dev); | 123 | - size_t size = -1; |
| 34 | 124 | - uint8_t *data; | |
| 35 | /* Initialize all fuses' initial value to 0xFFs */ | 125 | - |
| 36 | memset(s->fuse, 0xff, sizeof(s->fuse)); | 126 | - if (image_name == NULL) { |
| 37 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev) | 127 | - return; |
| 38 | serial_data = s->serial; | 128 | - } |
| 39 | if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD, | 129 | - |
| 40 | &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) { | 130 | - if (try_decompress) { |
| 41 | - error_report("write error index<%d>", index); | 131 | - size = load_image_gzipped_buffer(image_name, |
| 42 | + error_setg(errp, "failed to write index<%d>", index); | 132 | - LOAD_IMAGE_MAX_GUNZIP_BYTES, &data); |
| 43 | + return; | 133 | - } |
| 44 | } | 134 | - |
| 45 | 135 | - if (size == (size_t)-1) { | |
| 46 | serial_data = ~(s->serial); | 136 | - gchar *contents; |
| 47 | if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD, | 137 | - gsize length; |
| 48 | &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) { | 138 | - |
| 49 | - error_report("write error index<%d>", index + 1); | 139 | - if (!g_file_get_contents(image_name, &contents, &length, NULL)) { |
| 50 | + error_setg(errp, "failed to write index<%d>", index + 1); | 140 | - error_report("failed to load \"%s\"", image_name); |
| 51 | + return; | 141 | - exit(1); |
| 52 | } | 142 | - } |
| 53 | } | 143 | - size = length; |
| 54 | 144 | - data = (uint8_t *)contents; | |
| 55 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_class_init(ObjectClass *klass, void *data) | 145 | - } |
| 56 | 146 | - | |
| 57 | device_class_set_props(dc, sifive_u_otp_properties); | 147 | - fw_cfg_add_i32(fw_cfg, size_key, size); |
| 58 | dc->realize = sifive_u_otp_realize; | 148 | - fw_cfg_add_bytes(fw_cfg, data_key, data, size); |
| 59 | - dc->reset = sifive_u_otp_reset; | 149 | -} |
| 150 | - | ||
| 151 | static void fw_cfg_add_kernel_info(FWCfgState *fw_cfg) | ||
| 152 | { | ||
| 153 | /* | ||
| 154 | diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c | ||
| 155 | index XXXXXXX..XXXXXXX 100644 | ||
| 156 | --- a/hw/nvram/fw_cfg.c | ||
| 157 | +++ b/hw/nvram/fw_cfg.c | ||
| 158 | @@ -XXX,XX +XXX,XX @@ | ||
| 159 | #include "qapi/error.h" | ||
| 160 | #include "hw/acpi/aml-build.h" | ||
| 161 | #include "hw/pci/pci_bus.h" | ||
| 162 | +#include "hw/loader.h" | ||
| 163 | |||
| 164 | #define FW_CFG_FILE_SLOTS_DFLT 0x20 | ||
| 165 | |||
| 166 | @@ -XXX,XX +XXX,XX @@ FWCfgState *fw_cfg_find(void) | ||
| 167 | return FW_CFG(object_resolve_path_type("", TYPE_FW_CFG, NULL)); | ||
| 60 | } | 168 | } |
| 61 | 169 | ||
| 62 | static const TypeInfo sifive_u_otp_info = { | 170 | +void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key, |
| 171 | + uint16_t data_key, const char *image_name, | ||
| 172 | + bool try_decompress) | ||
| 173 | +{ | ||
| 174 | + size_t size = -1; | ||
| 175 | + uint8_t *data; | ||
| 176 | + | ||
| 177 | + if (image_name == NULL) { | ||
| 178 | + return; | ||
| 179 | + } | ||
| 180 | + | ||
| 181 | + if (try_decompress) { | ||
| 182 | + size = load_image_gzipped_buffer(image_name, | ||
| 183 | + LOAD_IMAGE_MAX_GUNZIP_BYTES, &data); | ||
| 184 | + } | ||
| 185 | + | ||
| 186 | + if (size == (size_t)-1) { | ||
| 187 | + gchar *contents; | ||
| 188 | + gsize length; | ||
| 189 | + | ||
| 190 | + if (!g_file_get_contents(image_name, &contents, &length, NULL)) { | ||
| 191 | + error_report("failed to load \"%s\"", image_name); | ||
| 192 | + exit(1); | ||
| 193 | + } | ||
| 194 | + size = length; | ||
| 195 | + data = (uint8_t *)contents; | ||
| 196 | + } | ||
| 197 | + | ||
| 198 | + fw_cfg_add_i32(fw_cfg, size_key, size); | ||
| 199 | + fw_cfg_add_bytes(fw_cfg, data_key, data, size); | ||
| 200 | +} | ||
| 201 | |||
| 202 | static void fw_cfg_class_init(ObjectClass *klass, void *data) | ||
| 203 | { | ||
| 63 | -- | 204 | -- |
| 64 | 2.31.1 | 205 | 2.37.3 |
| 65 | |||
| 66 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Sunil V L <sunilvl@ventanamicro.com> | ||
| 1 | 2 | ||
| 3 | To enable both -kernel and -pflash options, the fw_cfg needs to be | ||
| 4 | created prior to loading the kernel. | ||
| 5 | |||
| 6 | Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> | ||
| 7 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
| 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 9 | Message-Id: <20221004092351.18209-3-sunilvl@ventanamicro.com> | ||
| 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 11 | --- | ||
| 12 | hw/riscv/virt.c | 14 +++++++------- | ||
| 13 | 1 file changed, 7 insertions(+), 7 deletions(-) | ||
| 14 | |||
| 15 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/hw/riscv/virt.c | ||
| 18 | +++ b/hw/riscv/virt.c | ||
| 19 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data) | ||
| 20 | RISCV64_BIOS_BIN, start_addr, NULL); | ||
| 21 | } | ||
| 22 | |||
| 23 | + /* | ||
| 24 | + * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device | ||
| 25 | + * tree cannot be altered and we get FDT_ERR_NOSPACE. | ||
| 26 | + */ | ||
| 27 | + s->fw_cfg = create_fw_cfg(machine); | ||
| 28 | + rom_set_fw(s->fw_cfg); | ||
| 29 | + | ||
| 30 | if (machine->kernel_filename) { | ||
| 31 | kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], | ||
| 32 | firmware_end_addr); | ||
| 33 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data) | ||
| 34 | start_addr = virt_memmap[VIRT_FLASH].base; | ||
| 35 | } | ||
| 36 | |||
| 37 | - /* | ||
| 38 | - * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device | ||
| 39 | - * tree cannot be altered and we get FDT_ERR_NOSPACE. | ||
| 40 | - */ | ||
| 41 | - s->fw_cfg = create_fw_cfg(machine); | ||
| 42 | - rom_set_fw(s->fw_cfg); | ||
| 43 | - | ||
| 44 | /* Compute the fdt load address in dram */ | ||
| 45 | fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, | ||
| 46 | machine->ram_size, machine->fdt); | ||
| 47 | -- | ||
| 48 | 2.37.3 | diff view generated by jsdifflib |
| 1 | From: Thomas Huth <thuth@redhat.com> | 1 | From: Sunil V L <sunilvl@ventanamicro.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Configuring a drive with "if=none" is meant for creation of a backend | 3 | To boot S-mode firmware payload like EDK2 from persistent |
| 4 | only, it should not get automatically assigned to a device frontend. | 4 | flash storage, qemu needs to pass the flash address as the |
| 5 | Use "if=pflash" for the One-Time-Programmable device instead (like | 5 | next_addr in fw_dynamic_info to the opensbi. |
| 6 | it is e.g. also done for the efuse device in hw/arm/xlnx-zcu102.c). | ||
| 7 | 6 | ||
| 8 | Since the old way of configuring the device has already been published | 7 | When both -kernel and -pflash options are provided in command line, |
| 9 | with the previous QEMU versions, we cannot remove this immediately, but | 8 | the kernel (and initrd if -initrd) will be copied to fw_cfg table. |
| 10 | have to deprecate it and support it for at least two more releases. | 9 | The S-mode FW will load the kernel/initrd from fw_cfg table. |
| 11 | 10 | ||
| 12 | Signed-off-by: Thomas Huth <thuth@redhat.com> | 11 | If only pflash is given but not -kernel, then it is the job of |
| 13 | Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 12 | of the S-mode firmware to locate and load the kernel. |
| 14 | Reviewed-by: Markus Armbruster <armbru@redhat.com> | 13 | |
| 14 | In either case, update the kernel_entry with the flash address | ||
| 15 | so that the opensbi can jump to the entry point of the S-mode | ||
| 16 | firmware. | ||
| 17 | |||
| 18 | Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> | ||
| 19 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
| 15 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 20 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 16 | Message-id: 20211119102549.217755-1-thuth@redhat.com | 21 | Message-Id: <20221004092351.18209-4-sunilvl@ventanamicro.com> |
| 17 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 22 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 18 | --- | 23 | --- |
| 19 | docs/about/deprecated.rst | 6 ++++++ | 24 | include/hw/riscv/boot.h | 1 + |
| 20 | hw/misc/sifive_u_otp.c | 9 ++++++++- | 25 | hw/riscv/boot.c | 29 +++++++++++++++++++++++++++++ |
| 21 | 2 files changed, 14 insertions(+), 1 deletion(-) | 26 | hw/riscv/virt.c | 18 +++++++++++++++++- |
| 27 | 3 files changed, 47 insertions(+), 1 deletion(-) | ||
| 22 | 28 | ||
| 23 | diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst | 29 | diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h |
| 24 | index XXXXXXX..XXXXXXX 100644 | 30 | index XXXXXXX..XXXXXXX 100644 |
| 25 | --- a/docs/about/deprecated.rst | 31 | --- a/include/hw/riscv/boot.h |
| 26 | +++ b/docs/about/deprecated.rst | 32 | +++ b/include/hw/riscv/boot.h |
| 27 | @@ -XXX,XX +XXX,XX @@ as short-form boolean values, and passed to plugins as ``arg_name=on``. | 33 | @@ -XXX,XX +XXX,XX @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, |
| 28 | However, short-form booleans are deprecated and full explicit ``arg_name=on`` | 34 | uint32_t reset_vec_size, |
| 29 | form is preferred. | 35 | uint64_t kernel_entry); |
| 30 | 36 | void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr); | |
| 31 | +``-drive if=none`` for the sifive_u OTP device (since 6.2) | 37 | +void riscv_setup_firmware_boot(MachineState *machine); |
| 32 | +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''' | 38 | |
| 39 | #endif /* RISCV_BOOT_H */ | ||
| 40 | diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c | ||
| 41 | index XXXXXXX..XXXXXXX 100644 | ||
| 42 | --- a/hw/riscv/boot.c | ||
| 43 | +++ b/hw/riscv/boot.c | ||
| 44 | @@ -XXX,XX +XXX,XX @@ void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr) | ||
| 45 | riscv_cpu->env.fdt_addr = fdt_addr; | ||
| 46 | } | ||
| 47 | } | ||
| 33 | + | 48 | + |
| 34 | +Using ``-drive if=none`` to configure the OTP device of the sifive_u | 49 | +void riscv_setup_firmware_boot(MachineState *machine) |
| 35 | +RISC-V machine is deprecated. Use ``-drive if=pflash`` instead. | 50 | +{ |
| 51 | + if (machine->kernel_filename) { | ||
| 52 | + FWCfgState *fw_cfg; | ||
| 53 | + fw_cfg = fw_cfg_find(); | ||
| 36 | + | 54 | + |
| 37 | 55 | + assert(fw_cfg); | |
| 38 | QEMU Machine Protocol (QMP) commands | 56 | + /* |
| 39 | ------------------------------------ | 57 | + * Expose the kernel, the command line, and the initrd in fw_cfg. |
| 40 | diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c | 58 | + * We don't process them here at all, it's all left to the |
| 41 | index XXXXXXX..XXXXXXX 100644 | 59 | + * firmware. |
| 42 | --- a/hw/misc/sifive_u_otp.c | 60 | + */ |
| 43 | +++ b/hw/misc/sifive_u_otp.c | 61 | + load_image_to_fw_cfg(fw_cfg, |
| 44 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp) | 62 | + FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, |
| 45 | TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE); | 63 | + machine->kernel_filename, |
| 46 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); | 64 | + true); |
| 47 | 65 | + load_image_to_fw_cfg(fw_cfg, | |
| 48 | - dinfo = drive_get_next(IF_NONE); | 66 | + FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, |
| 49 | + dinfo = drive_get_next(IF_PFLASH); | 67 | + machine->initrd_filename, false); |
| 50 | + if (!dinfo) { | 68 | + |
| 51 | + dinfo = drive_get_next(IF_NONE); | 69 | + if (machine->kernel_cmdline) { |
| 52 | + if (dinfo) { | 70 | + fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
| 53 | + warn_report("using \"-drive if=none\" for the OTP is deprecated, " | 71 | + strlen(machine->kernel_cmdline) + 1); |
| 54 | + "use \"-drive if=pflash\" instead."); | 72 | + fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, |
| 73 | + machine->kernel_cmdline); | ||
| 55 | + } | 74 | + } |
| 56 | + } | 75 | + } |
| 57 | if (dinfo) { | 76 | +} |
| 58 | int ret; | 77 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c |
| 59 | uint64_t perm; | 78 | index XXXXXXX..XXXXXXX 100644 |
| 79 | --- a/hw/riscv/virt.c | ||
| 80 | +++ b/hw/riscv/virt.c | ||
| 81 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data) | ||
| 82 | s->fw_cfg = create_fw_cfg(machine); | ||
| 83 | rom_set_fw(s->fw_cfg); | ||
| 84 | |||
| 85 | - if (machine->kernel_filename) { | ||
| 86 | + if (drive_get(IF_PFLASH, 0, 1)) { | ||
| 87 | + /* | ||
| 88 | + * S-mode FW like EDK2 will be kept in second plash (unit 1). | ||
| 89 | + * When both kernel, initrd and pflash options are provided in the | ||
| 90 | + * command line, the kernel and initrd will be copied to the fw_cfg | ||
| 91 | + * table and opensbi will jump to the flash address which is the | ||
| 92 | + * entry point of S-mode FW. It is the job of the S-mode FW to load | ||
| 93 | + * the kernel and initrd using fw_cfg table. | ||
| 94 | + * | ||
| 95 | + * If only pflash is given but not -kernel, then it is the job of | ||
| 96 | + * of the S-mode firmware to locate and load the kernel. | ||
| 97 | + * In either case, the next_addr for opensbi will be the flash address. | ||
| 98 | + */ | ||
| 99 | + riscv_setup_firmware_boot(machine); | ||
| 100 | + kernel_entry = virt_memmap[VIRT_FLASH].base + | ||
| 101 | + virt_memmap[VIRT_FLASH].size / 2; | ||
| 102 | + } else if (machine->kernel_filename) { | ||
| 103 | kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], | ||
| 104 | firmware_end_addr); | ||
| 105 | |||
| 60 | -- | 106 | -- |
| 61 | 2.31.1 | 107 | 2.37.3 |
| 62 | |||
| 63 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Yang Liu <liuyang22@iscas.ac.cn> | ||
| 1 | 2 | ||
| 3 | Tested with https://github.com/ksco/rvv-decoder-tests | ||
| 4 | |||
| 5 | Expected checkpatch errors for consistency and brevity reasons: | ||
| 6 | |||
| 7 | ERROR: line over 90 characters | ||
| 8 | ERROR: trailing statements should be on next line | ||
| 9 | ERROR: braces {} are necessary for all arms of this statement | ||
| 10 | |||
| 11 | Signed-off-by: Yang Liu <liuyang22@iscas.ac.cn> | ||
| 12 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 13 | Message-Id: <20220928051842.16207-1-liuyang22@iscas.ac.cn> | ||
| 14 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 15 | --- | ||
| 16 | disas/riscv.c | 1432 ++++++++++++++++++++++++++++++++++++++++++++++++- | ||
| 17 | 1 file changed, 1430 insertions(+), 2 deletions(-) | ||
| 18 | |||
| 19 | diff --git a/disas/riscv.c b/disas/riscv.c | ||
| 20 | index XXXXXXX..XXXXXXX 100644 | ||
| 21 | --- a/disas/riscv.c | ||
| 22 | +++ b/disas/riscv.c | ||
| 23 | @@ -XXX,XX +XXX,XX @@ typedef enum { | ||
| 24 | rv_codec_css_sqsp, | ||
| 25 | rv_codec_k_bs, | ||
| 26 | rv_codec_k_rnum, | ||
| 27 | + rv_codec_v_r, | ||
| 28 | + rv_codec_v_ldst, | ||
| 29 | + rv_codec_v_i, | ||
| 30 | + rv_codec_vsetvli, | ||
| 31 | + rv_codec_vsetivli, | ||
| 32 | } rv_codec; | ||
| 33 | |||
| 34 | typedef enum { | ||
| 35 | @@ -XXX,XX +XXX,XX @@ typedef enum { | ||
| 36 | rv_op_zip = 396, | ||
| 37 | rv_op_xperm4 = 397, | ||
| 38 | rv_op_xperm8 = 398, | ||
| 39 | + rv_op_vle8_v = 399, | ||
| 40 | + rv_op_vle16_v = 400, | ||
| 41 | + rv_op_vle32_v = 401, | ||
| 42 | + rv_op_vle64_v = 402, | ||
| 43 | + rv_op_vse8_v = 403, | ||
| 44 | + rv_op_vse16_v = 404, | ||
| 45 | + rv_op_vse32_v = 405, | ||
| 46 | + rv_op_vse64_v = 406, | ||
| 47 | + rv_op_vlm_v = 407, | ||
| 48 | + rv_op_vsm_v = 408, | ||
| 49 | + rv_op_vlse8_v = 409, | ||
| 50 | + rv_op_vlse16_v = 410, | ||
| 51 | + rv_op_vlse32_v = 411, | ||
| 52 | + rv_op_vlse64_v = 412, | ||
| 53 | + rv_op_vsse8_v = 413, | ||
| 54 | + rv_op_vsse16_v = 414, | ||
| 55 | + rv_op_vsse32_v = 415, | ||
| 56 | + rv_op_vsse64_v = 416, | ||
| 57 | + rv_op_vluxei8_v = 417, | ||
| 58 | + rv_op_vluxei16_v = 418, | ||
| 59 | + rv_op_vluxei32_v = 419, | ||
| 60 | + rv_op_vluxei64_v = 420, | ||
| 61 | + rv_op_vloxei8_v = 421, | ||
| 62 | + rv_op_vloxei16_v = 422, | ||
| 63 | + rv_op_vloxei32_v = 423, | ||
| 64 | + rv_op_vloxei64_v = 424, | ||
| 65 | + rv_op_vsuxei8_v = 425, | ||
| 66 | + rv_op_vsuxei16_v = 426, | ||
| 67 | + rv_op_vsuxei32_v = 427, | ||
| 68 | + rv_op_vsuxei64_v = 428, | ||
| 69 | + rv_op_vsoxei8_v = 429, | ||
| 70 | + rv_op_vsoxei16_v = 430, | ||
| 71 | + rv_op_vsoxei32_v = 431, | ||
| 72 | + rv_op_vsoxei64_v = 432, | ||
| 73 | + rv_op_vle8ff_v = 433, | ||
| 74 | + rv_op_vle16ff_v = 434, | ||
| 75 | + rv_op_vle32ff_v = 435, | ||
| 76 | + rv_op_vle64ff_v = 436, | ||
| 77 | + rv_op_vl1re8_v = 437, | ||
| 78 | + rv_op_vl1re16_v = 438, | ||
| 79 | + rv_op_vl1re32_v = 439, | ||
| 80 | + rv_op_vl1re64_v = 440, | ||
| 81 | + rv_op_vl2re8_v = 441, | ||
| 82 | + rv_op_vl2re16_v = 442, | ||
| 83 | + rv_op_vl2re32_v = 443, | ||
| 84 | + rv_op_vl2re64_v = 444, | ||
| 85 | + rv_op_vl4re8_v = 445, | ||
| 86 | + rv_op_vl4re16_v = 446, | ||
| 87 | + rv_op_vl4re32_v = 447, | ||
| 88 | + rv_op_vl4re64_v = 448, | ||
| 89 | + rv_op_vl8re8_v = 449, | ||
| 90 | + rv_op_vl8re16_v = 450, | ||
| 91 | + rv_op_vl8re32_v = 451, | ||
| 92 | + rv_op_vl8re64_v = 452, | ||
| 93 | + rv_op_vs1r_v = 453, | ||
| 94 | + rv_op_vs2r_v = 454, | ||
| 95 | + rv_op_vs4r_v = 455, | ||
| 96 | + rv_op_vs8r_v = 456, | ||
| 97 | + rv_op_vadd_vv = 457, | ||
| 98 | + rv_op_vadd_vx = 458, | ||
| 99 | + rv_op_vadd_vi = 459, | ||
| 100 | + rv_op_vsub_vv = 460, | ||
| 101 | + rv_op_vsub_vx = 461, | ||
| 102 | + rv_op_vrsub_vx = 462, | ||
| 103 | + rv_op_vrsub_vi = 463, | ||
| 104 | + rv_op_vwaddu_vv = 464, | ||
| 105 | + rv_op_vwaddu_vx = 465, | ||
| 106 | + rv_op_vwadd_vv = 466, | ||
| 107 | + rv_op_vwadd_vx = 467, | ||
| 108 | + rv_op_vwsubu_vv = 468, | ||
| 109 | + rv_op_vwsubu_vx = 469, | ||
| 110 | + rv_op_vwsub_vv = 470, | ||
| 111 | + rv_op_vwsub_vx = 471, | ||
| 112 | + rv_op_vwaddu_wv = 472, | ||
| 113 | + rv_op_vwaddu_wx = 473, | ||
| 114 | + rv_op_vwadd_wv = 474, | ||
| 115 | + rv_op_vwadd_wx = 475, | ||
| 116 | + rv_op_vwsubu_wv = 476, | ||
| 117 | + rv_op_vwsubu_wx = 477, | ||
| 118 | + rv_op_vwsub_wv = 478, | ||
| 119 | + rv_op_vwsub_wx = 479, | ||
| 120 | + rv_op_vadc_vvm = 480, | ||
| 121 | + rv_op_vadc_vxm = 481, | ||
| 122 | + rv_op_vadc_vim = 482, | ||
| 123 | + rv_op_vmadc_vvm = 483, | ||
| 124 | + rv_op_vmadc_vxm = 484, | ||
| 125 | + rv_op_vmadc_vim = 485, | ||
| 126 | + rv_op_vsbc_vvm = 486, | ||
| 127 | + rv_op_vsbc_vxm = 487, | ||
| 128 | + rv_op_vmsbc_vvm = 488, | ||
| 129 | + rv_op_vmsbc_vxm = 489, | ||
| 130 | + rv_op_vand_vv = 490, | ||
| 131 | + rv_op_vand_vx = 491, | ||
| 132 | + rv_op_vand_vi = 492, | ||
| 133 | + rv_op_vor_vv = 493, | ||
| 134 | + rv_op_vor_vx = 494, | ||
| 135 | + rv_op_vor_vi = 495, | ||
| 136 | + rv_op_vxor_vv = 496, | ||
| 137 | + rv_op_vxor_vx = 497, | ||
| 138 | + rv_op_vxor_vi = 498, | ||
| 139 | + rv_op_vsll_vv = 499, | ||
| 140 | + rv_op_vsll_vx = 500, | ||
| 141 | + rv_op_vsll_vi = 501, | ||
| 142 | + rv_op_vsrl_vv = 502, | ||
| 143 | + rv_op_vsrl_vx = 503, | ||
| 144 | + rv_op_vsrl_vi = 504, | ||
| 145 | + rv_op_vsra_vv = 505, | ||
| 146 | + rv_op_vsra_vx = 506, | ||
| 147 | + rv_op_vsra_vi = 507, | ||
| 148 | + rv_op_vnsrl_wv = 508, | ||
| 149 | + rv_op_vnsrl_wx = 509, | ||
| 150 | + rv_op_vnsrl_wi = 510, | ||
| 151 | + rv_op_vnsra_wv = 511, | ||
| 152 | + rv_op_vnsra_wx = 512, | ||
| 153 | + rv_op_vnsra_wi = 513, | ||
| 154 | + rv_op_vmseq_vv = 514, | ||
| 155 | + rv_op_vmseq_vx = 515, | ||
| 156 | + rv_op_vmseq_vi = 516, | ||
| 157 | + rv_op_vmsne_vv = 517, | ||
| 158 | + rv_op_vmsne_vx = 518, | ||
| 159 | + rv_op_vmsne_vi = 519, | ||
| 160 | + rv_op_vmsltu_vv = 520, | ||
| 161 | + rv_op_vmsltu_vx = 521, | ||
| 162 | + rv_op_vmslt_vv = 522, | ||
| 163 | + rv_op_vmslt_vx = 523, | ||
| 164 | + rv_op_vmsleu_vv = 524, | ||
| 165 | + rv_op_vmsleu_vx = 525, | ||
| 166 | + rv_op_vmsleu_vi = 526, | ||
| 167 | + rv_op_vmsle_vv = 527, | ||
| 168 | + rv_op_vmsle_vx = 528, | ||
| 169 | + rv_op_vmsle_vi = 529, | ||
| 170 | + rv_op_vmsgtu_vx = 530, | ||
| 171 | + rv_op_vmsgtu_vi = 531, | ||
| 172 | + rv_op_vmsgt_vx = 532, | ||
| 173 | + rv_op_vmsgt_vi = 533, | ||
| 174 | + rv_op_vminu_vv = 534, | ||
| 175 | + rv_op_vminu_vx = 535, | ||
| 176 | + rv_op_vmin_vv = 536, | ||
| 177 | + rv_op_vmin_vx = 537, | ||
| 178 | + rv_op_vmaxu_vv = 538, | ||
| 179 | + rv_op_vmaxu_vx = 539, | ||
| 180 | + rv_op_vmax_vv = 540, | ||
| 181 | + rv_op_vmax_vx = 541, | ||
| 182 | + rv_op_vmul_vv = 542, | ||
| 183 | + rv_op_vmul_vx = 543, | ||
| 184 | + rv_op_vmulh_vv = 544, | ||
| 185 | + rv_op_vmulh_vx = 545, | ||
| 186 | + rv_op_vmulhu_vv = 546, | ||
| 187 | + rv_op_vmulhu_vx = 547, | ||
| 188 | + rv_op_vmulhsu_vv = 548, | ||
| 189 | + rv_op_vmulhsu_vx = 549, | ||
| 190 | + rv_op_vdivu_vv = 550, | ||
| 191 | + rv_op_vdivu_vx = 551, | ||
| 192 | + rv_op_vdiv_vv = 552, | ||
| 193 | + rv_op_vdiv_vx = 553, | ||
| 194 | + rv_op_vremu_vv = 554, | ||
| 195 | + rv_op_vremu_vx = 555, | ||
| 196 | + rv_op_vrem_vv = 556, | ||
| 197 | + rv_op_vrem_vx = 557, | ||
| 198 | + rv_op_vwmulu_vv = 558, | ||
| 199 | + rv_op_vwmulu_vx = 559, | ||
| 200 | + rv_op_vwmulsu_vv = 560, | ||
| 201 | + rv_op_vwmulsu_vx = 561, | ||
| 202 | + rv_op_vwmul_vv = 562, | ||
| 203 | + rv_op_vwmul_vx = 563, | ||
| 204 | + rv_op_vmacc_vv = 564, | ||
| 205 | + rv_op_vmacc_vx = 565, | ||
| 206 | + rv_op_vnmsac_vv = 566, | ||
| 207 | + rv_op_vnmsac_vx = 567, | ||
| 208 | + rv_op_vmadd_vv = 568, | ||
| 209 | + rv_op_vmadd_vx = 569, | ||
| 210 | + rv_op_vnmsub_vv = 570, | ||
| 211 | + rv_op_vnmsub_vx = 571, | ||
| 212 | + rv_op_vwmaccu_vv = 572, | ||
| 213 | + rv_op_vwmaccu_vx = 573, | ||
| 214 | + rv_op_vwmacc_vv = 574, | ||
| 215 | + rv_op_vwmacc_vx = 575, | ||
| 216 | + rv_op_vwmaccsu_vv = 576, | ||
| 217 | + rv_op_vwmaccsu_vx = 577, | ||
| 218 | + rv_op_vwmaccus_vx = 578, | ||
| 219 | + rv_op_vmv_v_v = 579, | ||
| 220 | + rv_op_vmv_v_x = 580, | ||
| 221 | + rv_op_vmv_v_i = 581, | ||
| 222 | + rv_op_vmerge_vvm = 582, | ||
| 223 | + rv_op_vmerge_vxm = 583, | ||
| 224 | + rv_op_vmerge_vim = 584, | ||
| 225 | + rv_op_vsaddu_vv = 585, | ||
| 226 | + rv_op_vsaddu_vx = 586, | ||
| 227 | + rv_op_vsaddu_vi = 587, | ||
| 228 | + rv_op_vsadd_vv = 588, | ||
| 229 | + rv_op_vsadd_vx = 589, | ||
| 230 | + rv_op_vsadd_vi = 590, | ||
| 231 | + rv_op_vssubu_vv = 591, | ||
| 232 | + rv_op_vssubu_vx = 592, | ||
| 233 | + rv_op_vssub_vv = 593, | ||
| 234 | + rv_op_vssub_vx = 594, | ||
| 235 | + rv_op_vaadd_vv = 595, | ||
| 236 | + rv_op_vaadd_vx = 596, | ||
| 237 | + rv_op_vaaddu_vv = 597, | ||
| 238 | + rv_op_vaaddu_vx = 598, | ||
| 239 | + rv_op_vasub_vv = 599, | ||
| 240 | + rv_op_vasub_vx = 600, | ||
| 241 | + rv_op_vasubu_vv = 601, | ||
| 242 | + rv_op_vasubu_vx = 602, | ||
| 243 | + rv_op_vsmul_vv = 603, | ||
| 244 | + rv_op_vsmul_vx = 604, | ||
| 245 | + rv_op_vssrl_vv = 605, | ||
| 246 | + rv_op_vssrl_vx = 606, | ||
| 247 | + rv_op_vssrl_vi = 607, | ||
| 248 | + rv_op_vssra_vv = 608, | ||
| 249 | + rv_op_vssra_vx = 609, | ||
| 250 | + rv_op_vssra_vi = 610, | ||
| 251 | + rv_op_vnclipu_wv = 611, | ||
| 252 | + rv_op_vnclipu_wx = 612, | ||
| 253 | + rv_op_vnclipu_wi = 613, | ||
| 254 | + rv_op_vnclip_wv = 614, | ||
| 255 | + rv_op_vnclip_wx = 615, | ||
| 256 | + rv_op_vnclip_wi = 616, | ||
| 257 | + rv_op_vfadd_vv = 617, | ||
| 258 | + rv_op_vfadd_vf = 618, | ||
| 259 | + rv_op_vfsub_vv = 619, | ||
| 260 | + rv_op_vfsub_vf = 620, | ||
| 261 | + rv_op_vfrsub_vf = 621, | ||
| 262 | + rv_op_vfwadd_vv = 622, | ||
| 263 | + rv_op_vfwadd_vf = 623, | ||
| 264 | + rv_op_vfwadd_wv = 624, | ||
| 265 | + rv_op_vfwadd_wf = 625, | ||
| 266 | + rv_op_vfwsub_vv = 626, | ||
| 267 | + rv_op_vfwsub_vf = 627, | ||
| 268 | + rv_op_vfwsub_wv = 628, | ||
| 269 | + rv_op_vfwsub_wf = 629, | ||
| 270 | + rv_op_vfmul_vv = 630, | ||
| 271 | + rv_op_vfmul_vf = 631, | ||
| 272 | + rv_op_vfdiv_vv = 632, | ||
| 273 | + rv_op_vfdiv_vf = 633, | ||
| 274 | + rv_op_vfrdiv_vf = 634, | ||
| 275 | + rv_op_vfwmul_vv = 635, | ||
| 276 | + rv_op_vfwmul_vf = 636, | ||
| 277 | + rv_op_vfmacc_vv = 637, | ||
| 278 | + rv_op_vfmacc_vf = 638, | ||
| 279 | + rv_op_vfnmacc_vv = 639, | ||
| 280 | + rv_op_vfnmacc_vf = 640, | ||
| 281 | + rv_op_vfmsac_vv = 641, | ||
| 282 | + rv_op_vfmsac_vf = 642, | ||
| 283 | + rv_op_vfnmsac_vv = 643, | ||
| 284 | + rv_op_vfnmsac_vf = 644, | ||
| 285 | + rv_op_vfmadd_vv = 645, | ||
| 286 | + rv_op_vfmadd_vf = 646, | ||
| 287 | + rv_op_vfnmadd_vv = 647, | ||
| 288 | + rv_op_vfnmadd_vf = 648, | ||
| 289 | + rv_op_vfmsub_vv = 649, | ||
| 290 | + rv_op_vfmsub_vf = 650, | ||
| 291 | + rv_op_vfnmsub_vv = 651, | ||
| 292 | + rv_op_vfnmsub_vf = 652, | ||
| 293 | + rv_op_vfwmacc_vv = 653, | ||
| 294 | + rv_op_vfwmacc_vf = 654, | ||
| 295 | + rv_op_vfwnmacc_vv = 655, | ||
| 296 | + rv_op_vfwnmacc_vf = 656, | ||
| 297 | + rv_op_vfwmsac_vv = 657, | ||
| 298 | + rv_op_vfwmsac_vf = 658, | ||
| 299 | + rv_op_vfwnmsac_vv = 659, | ||
| 300 | + rv_op_vfwnmsac_vf = 660, | ||
| 301 | + rv_op_vfsqrt_v = 661, | ||
| 302 | + rv_op_vfrsqrt7_v = 662, | ||
| 303 | + rv_op_vfrec7_v = 663, | ||
| 304 | + rv_op_vfmin_vv = 664, | ||
| 305 | + rv_op_vfmin_vf = 665, | ||
| 306 | + rv_op_vfmax_vv = 666, | ||
| 307 | + rv_op_vfmax_vf = 667, | ||
| 308 | + rv_op_vfsgnj_vv = 668, | ||
| 309 | + rv_op_vfsgnj_vf = 669, | ||
| 310 | + rv_op_vfsgnjn_vv = 670, | ||
| 311 | + rv_op_vfsgnjn_vf = 671, | ||
| 312 | + rv_op_vfsgnjx_vv = 672, | ||
| 313 | + rv_op_vfsgnjx_vf = 673, | ||
| 314 | + rv_op_vfslide1up_vf = 674, | ||
| 315 | + rv_op_vfslide1down_vf = 675, | ||
| 316 | + rv_op_vmfeq_vv = 676, | ||
| 317 | + rv_op_vmfeq_vf = 677, | ||
| 318 | + rv_op_vmfne_vv = 678, | ||
| 319 | + rv_op_vmfne_vf = 679, | ||
| 320 | + rv_op_vmflt_vv = 680, | ||
| 321 | + rv_op_vmflt_vf = 681, | ||
| 322 | + rv_op_vmfle_vv = 682, | ||
| 323 | + rv_op_vmfle_vf = 683, | ||
| 324 | + rv_op_vmfgt_vf = 684, | ||
| 325 | + rv_op_vmfge_vf = 685, | ||
| 326 | + rv_op_vfclass_v = 686, | ||
| 327 | + rv_op_vfmerge_vfm = 687, | ||
| 328 | + rv_op_vfmv_v_f = 688, | ||
| 329 | + rv_op_vfcvt_xu_f_v = 689, | ||
| 330 | + rv_op_vfcvt_x_f_v = 690, | ||
| 331 | + rv_op_vfcvt_f_xu_v = 691, | ||
| 332 | + rv_op_vfcvt_f_x_v = 692, | ||
| 333 | + rv_op_vfcvt_rtz_xu_f_v = 693, | ||
| 334 | + rv_op_vfcvt_rtz_x_f_v = 694, | ||
| 335 | + rv_op_vfwcvt_xu_f_v = 695, | ||
| 336 | + rv_op_vfwcvt_x_f_v = 696, | ||
| 337 | + rv_op_vfwcvt_f_xu_v = 697, | ||
| 338 | + rv_op_vfwcvt_f_x_v = 698, | ||
| 339 | + rv_op_vfwcvt_f_f_v = 699, | ||
| 340 | + rv_op_vfwcvt_rtz_xu_f_v = 700, | ||
| 341 | + rv_op_vfwcvt_rtz_x_f_v = 701, | ||
| 342 | + rv_op_vfncvt_xu_f_w = 702, | ||
| 343 | + rv_op_vfncvt_x_f_w = 703, | ||
| 344 | + rv_op_vfncvt_f_xu_w = 704, | ||
| 345 | + rv_op_vfncvt_f_x_w = 705, | ||
| 346 | + rv_op_vfncvt_f_f_w = 706, | ||
| 347 | + rv_op_vfncvt_rod_f_f_w = 707, | ||
| 348 | + rv_op_vfncvt_rtz_xu_f_w = 708, | ||
| 349 | + rv_op_vfncvt_rtz_x_f_w = 709, | ||
| 350 | + rv_op_vredsum_vs = 710, | ||
| 351 | + rv_op_vredand_vs = 711, | ||
| 352 | + rv_op_vredor_vs = 712, | ||
| 353 | + rv_op_vredxor_vs = 713, | ||
| 354 | + rv_op_vredminu_vs = 714, | ||
| 355 | + rv_op_vredmin_vs = 715, | ||
| 356 | + rv_op_vredmaxu_vs = 716, | ||
| 357 | + rv_op_vredmax_vs = 717, | ||
| 358 | + rv_op_vwredsumu_vs = 718, | ||
| 359 | + rv_op_vwredsum_vs = 719, | ||
| 360 | + rv_op_vfredusum_vs = 720, | ||
| 361 | + rv_op_vfredosum_vs = 721, | ||
| 362 | + rv_op_vfredmin_vs = 722, | ||
| 363 | + rv_op_vfredmax_vs = 723, | ||
| 364 | + rv_op_vfwredusum_vs = 724, | ||
| 365 | + rv_op_vfwredosum_vs = 725, | ||
| 366 | + rv_op_vmand_mm = 726, | ||
| 367 | + rv_op_vmnand_mm = 727, | ||
| 368 | + rv_op_vmandn_mm = 728, | ||
| 369 | + rv_op_vmxor_mm = 729, | ||
| 370 | + rv_op_vmor_mm = 730, | ||
| 371 | + rv_op_vmnor_mm = 731, | ||
| 372 | + rv_op_vmorn_mm = 732, | ||
| 373 | + rv_op_vmxnor_mm = 733, | ||
| 374 | + rv_op_vcpop_m = 734, | ||
| 375 | + rv_op_vfirst_m = 735, | ||
| 376 | + rv_op_vmsbf_m = 736, | ||
| 377 | + rv_op_vmsif_m = 737, | ||
| 378 | + rv_op_vmsof_m = 738, | ||
| 379 | + rv_op_viota_m = 739, | ||
| 380 | + rv_op_vid_v = 740, | ||
| 381 | + rv_op_vmv_x_s = 741, | ||
| 382 | + rv_op_vmv_s_x = 742, | ||
| 383 | + rv_op_vfmv_f_s = 743, | ||
| 384 | + rv_op_vfmv_s_f = 744, | ||
| 385 | + rv_op_vslideup_vx = 745, | ||
| 386 | + rv_op_vslideup_vi = 746, | ||
| 387 | + rv_op_vslide1up_vx = 747, | ||
| 388 | + rv_op_vslidedown_vx = 748, | ||
| 389 | + rv_op_vslidedown_vi = 749, | ||
| 390 | + rv_op_vslide1down_vx = 750, | ||
| 391 | + rv_op_vrgather_vv = 751, | ||
| 392 | + rv_op_vrgatherei16_vv = 752, | ||
| 393 | + rv_op_vrgather_vx = 753, | ||
| 394 | + rv_op_vrgather_vi = 754, | ||
| 395 | + rv_op_vcompress_vm = 755, | ||
| 396 | + rv_op_vmv1r_v = 756, | ||
| 397 | + rv_op_vmv2r_v = 757, | ||
| 398 | + rv_op_vmv4r_v = 758, | ||
| 399 | + rv_op_vmv8r_v = 759, | ||
| 400 | + rv_op_vzext_vf2 = 760, | ||
| 401 | + rv_op_vzext_vf4 = 761, | ||
| 402 | + rv_op_vzext_vf8 = 762, | ||
| 403 | + rv_op_vsext_vf2 = 763, | ||
| 404 | + rv_op_vsext_vf4 = 764, | ||
| 405 | + rv_op_vsext_vf8 = 765, | ||
| 406 | + rv_op_vsetvli = 766, | ||
| 407 | + rv_op_vsetivli = 767, | ||
| 408 | + rv_op_vsetvl = 768, | ||
| 409 | } rv_op; | ||
| 410 | |||
| 411 | /* structures */ | ||
| 412 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
| 413 | uint8_t rl; | ||
| 414 | uint8_t bs; | ||
| 415 | uint8_t rnum; | ||
| 416 | + uint8_t vm; | ||
| 417 | + uint32_t vzimm; | ||
| 418 | } rv_decode; | ||
| 419 | |||
| 420 | typedef struct { | ||
| 421 | @@ -XXX,XX +XXX,XX @@ static const char rv_freg_name_sym[32][5] = { | ||
| 422 | "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11", | ||
| 423 | }; | ||
| 424 | |||
| 425 | +static const char rv_vreg_name_sym[32][4] = { | ||
| 426 | + "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", | ||
| 427 | + "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", | ||
| 428 | + "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", | ||
| 429 | + "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" | ||
| 430 | +}; | ||
| 431 | + | ||
| 432 | /* instruction formats */ | ||
| 433 | |||
| 434 | #define rv_fmt_none "O\t" | ||
| 435 | @@ -XXX,XX +XXX,XX @@ static const char rv_freg_name_sym[32][5] = { | ||
| 436 | #define rv_fmt_rs2_offset "O\t2,o" | ||
| 437 | #define rv_fmt_rs1_rs2_bs "O\t1,2,b" | ||
| 438 | #define rv_fmt_rd_rs1_rnum "O\t0,1,n" | ||
| 439 | +#define rv_fmt_ldst_vd_rs1_vm "O\tD,(1)m" | ||
| 440 | +#define rv_fmt_ldst_vd_rs1_rs2_vm "O\tD,(1),2m" | ||
| 441 | +#define rv_fmt_ldst_vd_rs1_vs2_vm "O\tD,(1),Fm" | ||
| 442 | +#define rv_fmt_vd_vs2_vs1 "O\tD,F,E" | ||
| 443 | +#define rv_fmt_vd_vs2_vs1_vl "O\tD,F,El" | ||
| 444 | +#define rv_fmt_vd_vs2_vs1_vm "O\tD,F,Em" | ||
| 445 | +#define rv_fmt_vd_vs2_rs1_vl "O\tD,F,1l" | ||
| 446 | +#define rv_fmt_vd_vs2_fs1_vl "O\tD,F,4l" | ||
| 447 | +#define rv_fmt_vd_vs2_rs1_vm "O\tD,F,1m" | ||
| 448 | +#define rv_fmt_vd_vs2_fs1_vm "O\tD,F,4m" | ||
| 449 | +#define rv_fmt_vd_vs2_imm_vl "O\tD,F,il" | ||
| 450 | +#define rv_fmt_vd_vs2_imm_vm "O\tD,F,im" | ||
| 451 | +#define rv_fmt_vd_vs2_uimm_vm "O\tD,F,um" | ||
| 452 | +#define rv_fmt_vd_vs1_vs2_vm "O\tD,E,Fm" | ||
| 453 | +#define rv_fmt_vd_rs1_vs2_vm "O\tD,1,Fm" | ||
| 454 | +#define rv_fmt_vd_fs1_vs2_vm "O\tD,4,Fm" | ||
| 455 | +#define rv_fmt_vd_vs1 "O\tD,E" | ||
| 456 | +#define rv_fmt_vd_rs1 "O\tD,1" | ||
| 457 | +#define rv_fmt_vd_fs1 "O\tD,4" | ||
| 458 | +#define rv_fmt_vd_imm "O\tD,i" | ||
| 459 | +#define rv_fmt_vd_vs2 "O\tD,F" | ||
| 460 | +#define rv_fmt_vd_vs2_vm "O\tD,Fm" | ||
| 461 | +#define rv_fmt_rd_vs2_vm "O\t0,Fm" | ||
| 462 | +#define rv_fmt_rd_vs2 "O\t0,F" | ||
| 463 | +#define rv_fmt_fd_vs2 "O\t3,F" | ||
| 464 | +#define rv_fmt_vd_vm "O\tDm" | ||
| 465 | +#define rv_fmt_vsetvli "O\t0,1,v" | ||
| 466 | +#define rv_fmt_vsetivli "O\t0,u,v" | ||
| 467 | |||
| 468 | /* pseudo-instruction constraints */ | ||
| 469 | |||
| 470 | @@ -XXX,XX +XXX,XX @@ const rv_opcode_data opcode_data[] = { | ||
| 471 | { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, | ||
| 472 | { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, | ||
| 473 | { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, | ||
| 474 | - { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 } | ||
| 475 | + { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, | ||
| 476 | + { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle8_v, rv_op_vle8_v, 0 }, | ||
| 477 | + { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle16_v, rv_op_vle16_v, 0 }, | ||
| 478 | + { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle32_v, rv_op_vle32_v, 0 }, | ||
| 479 | + { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle64_v, rv_op_vle64_v, 0 }, | ||
| 480 | + { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse8_v, rv_op_vse8_v, 0 }, | ||
| 481 | + { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse16_v, rv_op_vse16_v, 0 }, | ||
| 482 | + { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse32_v, rv_op_vse32_v, 0 }, | ||
| 483 | + { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse64_v, rv_op_vse64_v, 0 }, | ||
| 484 | + { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vlm_v, rv_op_vlm_v, 0 }, | ||
| 485 | + { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vsm_v, rv_op_vsm_v, 0 }, | ||
| 486 | + { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse8_v, rv_op_vlse8_v, 0 }, | ||
| 487 | + { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse16_v, rv_op_vlse16_v, 0 }, | ||
| 488 | + { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse32_v, rv_op_vlse32_v, 0 }, | ||
| 489 | + { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse64_v, rv_op_vlse64_v, 0 }, | ||
| 490 | + { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse8_v, rv_op_vsse8_v, 0 }, | ||
| 491 | + { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse16_v, rv_op_vsse16_v, 0 }, | ||
| 492 | + { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse32_v, rv_op_vsse32_v, 0 }, | ||
| 493 | + { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse64_v, rv_op_vsse64_v, 0 }, | ||
| 494 | + { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei8_v, rv_op_vluxei8_v, 0 }, | ||
| 495 | + { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei16_v, rv_op_vluxei16_v, 0 }, | ||
| 496 | + { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei32_v, rv_op_vluxei32_v, 0 }, | ||
| 497 | + { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei64_v, rv_op_vluxei64_v, 0 }, | ||
| 498 | + { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei8_v, rv_op_vloxei8_v, 0 }, | ||
| 499 | + { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei16_v, rv_op_vloxei16_v, 0 }, | ||
| 500 | + { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei32_v, rv_op_vloxei32_v, 0 }, | ||
| 501 | + { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei64_v, rv_op_vloxei64_v, 0 }, | ||
| 502 | + { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei8_v, rv_op_vsuxei8_v, 0 }, | ||
| 503 | + { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei16_v, rv_op_vsuxei16_v, 0 }, | ||
| 504 | + { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei32_v, rv_op_vsuxei32_v, 0 }, | ||
| 505 | + { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei64_v, rv_op_vsuxei64_v, 0 }, | ||
| 506 | + { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei8_v, rv_op_vsoxei8_v, 0 }, | ||
| 507 | + { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei16_v, rv_op_vsoxei16_v, 0 }, | ||
| 508 | + { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei32_v, rv_op_vsoxei32_v, 0 }, | ||
| 509 | + { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei64_v, rv_op_vsoxei64_v, 0 }, | ||
| 510 | + { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle8ff_v, rv_op_vle8ff_v, 0 }, | ||
| 511 | + { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle16ff_v, rv_op_vle16ff_v, 0 }, | ||
| 512 | + { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle32ff_v, rv_op_vle32ff_v, 0 }, | ||
| 513 | + { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle64ff_v, rv_op_vle64ff_v, 0 }, | ||
| 514 | + { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re8_v, rv_op_vl1re8_v, 0 }, | ||
| 515 | + { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re16_v, rv_op_vl1re16_v, 0 }, | ||
| 516 | + { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re32_v, rv_op_vl1re32_v, 0 }, | ||
| 517 | + { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re64_v, rv_op_vl1re64_v, 0 }, | ||
| 518 | + { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re8_v, rv_op_vl2re8_v, 0 }, | ||
| 519 | + { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re16_v, rv_op_vl2re16_v, 0 }, | ||
| 520 | + { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re32_v, rv_op_vl2re32_v, 0 }, | ||
| 521 | + { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re64_v, rv_op_vl2re64_v, 0 }, | ||
| 522 | + { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re8_v, rv_op_vl4re8_v, 0 }, | ||
| 523 | + { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re16_v, rv_op_vl4re16_v, 0 }, | ||
| 524 | + { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re32_v, rv_op_vl4re32_v, 0 }, | ||
| 525 | + { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re64_v, rv_op_vl4re64_v, 0 }, | ||
| 526 | + { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re8_v, rv_op_vl8re8_v, 0 }, | ||
| 527 | + { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re16_v, rv_op_vl8re16_v, 0 }, | ||
| 528 | + { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re32_v, rv_op_vl8re32_v, 0 }, | ||
| 529 | + { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re64_v, rv_op_vl8re64_v, 0 }, | ||
| 530 | + { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs1r_v, rv_op_vs1r_v, 0 }, | ||
| 531 | + { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs2r_v, rv_op_vs2r_v, 0 }, | ||
| 532 | + { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs4r_v, rv_op_vs4r_v, 0 }, | ||
| 533 | + { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs8r_v, rv_op_vs8r_v, 0 }, | ||
| 534 | + { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vadd_vv, rv_op_vadd_vv, 0 }, | ||
| 535 | + { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vadd_vx, rv_op_vadd_vx, 0 }, | ||
| 536 | + { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vadd_vi, rv_op_vadd_vi, 0 }, | ||
| 537 | + { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsub_vv, rv_op_vsub_vv, 0 }, | ||
| 538 | + { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsub_vx, rv_op_vsub_vx, 0 }, | ||
| 539 | + { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrsub_vx, rv_op_vrsub_vx, 0 }, | ||
| 540 | + { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vrsub_vi, rv_op_vrsub_vi, 0 }, | ||
| 541 | + { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwaddu_vv, rv_op_vwaddu_vv, 0 }, | ||
| 542 | + { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwaddu_vx, rv_op_vwaddu_vx, 0 }, | ||
| 543 | + { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwadd_vv, rv_op_vwadd_vv, 0 }, | ||
| 544 | + { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwadd_vx, rv_op_vwadd_vx, 0 }, | ||
| 545 | + { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsubu_vv, rv_op_vwsubu_vv, 0 }, | ||
| 546 | + { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsubu_vx, rv_op_vwsubu_vx, 0 }, | ||
| 547 | + { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsub_vv, rv_op_vwsub_vv, 0 }, | ||
| 548 | + { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsub_vx, rv_op_vwsub_vx, 0 }, | ||
| 549 | + { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwaddu_wv, rv_op_vwaddu_wv, 0 }, | ||
| 550 | + { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwaddu_wx, rv_op_vwaddu_wx, 0 }, | ||
| 551 | + { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwadd_wv, rv_op_vwadd_wv, 0 }, | ||
| 552 | + { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwadd_wx, rv_op_vwadd_wx, 0 }, | ||
| 553 | + { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsubu_wv, rv_op_vwsubu_wv, 0 }, | ||
| 554 | + { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsubu_wx, rv_op_vwsubu_wx, 0 }, | ||
| 555 | + { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsub_wv, rv_op_vwsub_wv, 0 }, | ||
| 556 | + { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsub_wx, rv_op_vwsub_wx, 0 }, | ||
| 557 | + { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vadc_vvm, rv_op_vadc_vvm, 0 }, | ||
| 558 | + { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vadc_vxm, rv_op_vadc_vxm, 0 }, | ||
| 559 | + { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vadc_vim, rv_op_vadc_vim, 0 }, | ||
| 560 | + { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmadc_vvm, rv_op_vmadc_vvm, 0 }, | ||
| 561 | + { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmadc_vxm, rv_op_vmadc_vxm, 0 }, | ||
| 562 | + { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vmadc_vim, rv_op_vmadc_vim, 0 }, | ||
| 563 | + { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vsbc_vvm, rv_op_vsbc_vvm, 0 }, | ||
| 564 | + { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vsbc_vxm, rv_op_vsbc_vxm, 0 }, | ||
| 565 | + { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmsbc_vvm, rv_op_vmsbc_vvm, 0 }, | ||
| 566 | + { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmsbc_vxm, rv_op_vmsbc_vxm, 0 }, | ||
| 567 | + { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vand_vv, rv_op_vand_vv, 0 }, | ||
| 568 | + { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vand_vx, rv_op_vand_vx, 0 }, | ||
| 569 | + { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vand_vi, rv_op_vand_vi, 0 }, | ||
| 570 | + { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vor_vv, rv_op_vor_vv, 0 }, | ||
| 571 | + { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vor_vx, rv_op_vor_vx, 0 }, | ||
| 572 | + { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vor_vi, rv_op_vor_vi, 0 }, | ||
| 573 | + { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vxor_vv, rv_op_vxor_vv, 0 }, | ||
| 574 | + { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vxor_vx, rv_op_vxor_vx, 0 }, | ||
| 575 | + { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vxor_vi, rv_op_vxor_vi, 0 }, | ||
| 576 | + { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsll_vv, rv_op_vsll_vv, 0 }, | ||
| 577 | + { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsll_vx, rv_op_vsll_vx, 0 }, | ||
| 578 | + { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsll_vi, rv_op_vsll_vi, 0 }, | ||
| 579 | + { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsrl_vv, rv_op_vsrl_vv, 0 }, | ||
| 580 | + { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsrl_vx, rv_op_vsrl_vx, 0 }, | ||
| 581 | + { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsrl_vi, rv_op_vsrl_vi, 0 }, | ||
| 582 | + { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsra_vv, rv_op_vsra_vv, 0 }, | ||
| 583 | + { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsra_vx, rv_op_vsra_vx, 0 }, | ||
| 584 | + { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsra_vi, rv_op_vsra_vi, 0 }, | ||
| 585 | + { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnsrl_wv, rv_op_vnsrl_wv, 0 }, | ||
| 586 | + { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnsrl_wx, rv_op_vnsrl_wx, 0 }, | ||
| 587 | + { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnsrl_wi, rv_op_vnsrl_wi, 0 }, | ||
| 588 | + { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnsra_wv, rv_op_vnsra_wv, 0 }, | ||
| 589 | + { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnsra_wx, rv_op_vnsra_wx, 0 }, | ||
| 590 | + { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnsra_wi, rv_op_vnsra_wi, 0 }, | ||
| 591 | + { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmseq_vv, rv_op_vmseq_vv, 0 }, | ||
| 592 | + { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmseq_vx, rv_op_vmseq_vx, 0 }, | ||
| 593 | + { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmseq_vi, rv_op_vmseq_vi, 0 }, | ||
| 594 | + { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsne_vv, rv_op_vmsne_vv, 0 }, | ||
| 595 | + { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsne_vx, rv_op_vmsne_vx, 0 }, | ||
| 596 | + { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsne_vi, rv_op_vmsne_vi, 0 }, | ||
| 597 | + { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsltu_vv, rv_op_vmsltu_vv, 0 }, | ||
| 598 | + { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsltu_vx, rv_op_vmsltu_vx, 0 }, | ||
| 599 | + { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmslt_vv, rv_op_vmslt_vv, 0 }, | ||
| 600 | + { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmslt_vx, rv_op_vmslt_vx, 0 }, | ||
| 601 | + { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsleu_vv, rv_op_vmsleu_vv, 0 }, | ||
| 602 | + { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsleu_vx, rv_op_vmsleu_vx, 0 }, | ||
| 603 | + { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsleu_vi, rv_op_vmsleu_vi, 0 }, | ||
| 604 | + { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsle_vv, rv_op_vmsle_vv, 0 }, | ||
| 605 | + { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsle_vx, rv_op_vmsle_vx, 0 }, | ||
| 606 | + { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsle_vi, rv_op_vmsle_vi, 0 }, | ||
| 607 | + { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsgtu_vx, rv_op_vmsgtu_vx, 0 }, | ||
| 608 | + { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsgtu_vi, rv_op_vmsgtu_vi, 0 }, | ||
| 609 | + { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsgt_vx, rv_op_vmsgt_vx, 0 }, | ||
| 610 | + { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsgt_vi, rv_op_vmsgt_vi, 0 }, | ||
| 611 | + { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vminu_vv, rv_op_vminu_vv, 0 }, | ||
| 612 | + { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vminu_vx, rv_op_vminu_vx, 0 }, | ||
| 613 | + { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmin_vv, rv_op_vmin_vv, 0 }, | ||
| 614 | + { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmin_vx, rv_op_vmin_vx, 0 }, | ||
| 615 | + { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmaxu_vv, rv_op_vmaxu_vv, 0 }, | ||
| 616 | + { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmaxu_vx, rv_op_vmaxu_vx, 0 }, | ||
| 617 | + { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmax_vv, rv_op_vmax_vv, 0 }, | ||
| 618 | + { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmax_vx, rv_op_vmax_vx, 0 }, | ||
| 619 | + { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmul_vv, rv_op_vmul_vv, 0 }, | ||
| 620 | + { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmul_vx, rv_op_vmul_vx, 0 }, | ||
| 621 | + { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulh_vv, rv_op_vmulh_vv, 0 }, | ||
| 622 | + { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulh_vx, rv_op_vmulh_vx, 0 }, | ||
| 623 | + { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulhu_vv, rv_op_vmulhu_vv, 0 }, | ||
| 624 | + { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulhu_vx, rv_op_vmulhu_vx, 0 }, | ||
| 625 | + { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulhsu_vv, rv_op_vmulhsu_vv, 0 }, | ||
| 626 | + { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulhsu_vx, rv_op_vmulhsu_vx, 0 }, | ||
| 627 | + { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vdivu_vv, rv_op_vdivu_vv, 0 }, | ||
| 628 | + { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vdivu_vx, rv_op_vdivu_vx, 0 }, | ||
| 629 | + { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vdiv_vv, rv_op_vdiv_vv, 0 }, | ||
| 630 | + { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vdiv_vx, rv_op_vdiv_vx, 0 }, | ||
| 631 | + { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vremu_vv, rv_op_vremu_vv, 0 }, | ||
| 632 | + { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vremu_vx, rv_op_vremu_vx, 0 }, | ||
| 633 | + { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrem_vv, rv_op_vrem_vv, 0 }, | ||
| 634 | + { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrem_vx, rv_op_vrem_vx, 0 }, | ||
| 635 | + { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmulu_vv, rv_op_vwmulu_vv, 0 }, | ||
| 636 | + { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmulu_vx, rv_op_vwmulu_vx, 0 }, | ||
| 637 | + { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmulsu_vv, rv_op_vwmulsu_vv, 0 }, | ||
| 638 | + { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmulsu_vx, rv_op_vwmulsu_vx, 0 }, | ||
| 639 | + { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmul_vv, rv_op_vwmul_vv, 0 }, | ||
| 640 | + { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmul_vx, rv_op_vwmul_vx, 0 }, | ||
| 641 | + { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vmacc_vv, rv_op_vmacc_vv, 0 }, | ||
| 642 | + { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vmacc_vx, rv_op_vmacc_vx, 0 }, | ||
| 643 | + { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vnmsac_vv, rv_op_vnmsac_vv, 0 }, | ||
| 644 | + { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vnmsac_vx, rv_op_vnmsac_vx, 0 }, | ||
| 645 | + { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vmadd_vv, rv_op_vmadd_vv, 0 }, | ||
| 646 | + { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vmadd_vx, rv_op_vmadd_vx, 0 }, | ||
| 647 | + { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vnmsub_vv, rv_op_vnmsub_vv, 0 }, | ||
| 648 | + { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vnmsub_vx, rv_op_vnmsub_vx, 0 }, | ||
| 649 | + { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmaccu_vv, rv_op_vwmaccu_vv, 0 }, | ||
| 650 | + { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccu_vx, rv_op_vwmaccu_vx, 0 }, | ||
| 651 | + { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmacc_vv, rv_op_vwmacc_vv, 0 }, | ||
| 652 | + { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmacc_vx, rv_op_vwmacc_vx, 0 }, | ||
| 653 | + { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmaccsu_vv, rv_op_vwmaccsu_vv, 0 }, | ||
| 654 | + { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccsu_vx, rv_op_vwmaccsu_vx, 0 }, | ||
| 655 | + { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccus_vx, rv_op_vwmaccus_vx, 0 }, | ||
| 656 | + { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1, NULL, rv_op_vmv_v_v, rv_op_vmv_v_v, 0 }, | ||
| 657 | + { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, rv_op_vmv_v_x, rv_op_vmv_v_x, 0 }, | ||
| 658 | + { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm, NULL, rv_op_vmv_v_i, rv_op_vmv_v_i, 0 }, | ||
| 659 | + { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmerge_vvm, rv_op_vmerge_vvm, 0 }, | ||
| 660 | + { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmerge_vxm, rv_op_vmerge_vxm, 0 }, | ||
| 661 | + { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vmerge_vim, rv_op_vmerge_vim, 0 }, | ||
| 662 | + { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsaddu_vv, rv_op_vsaddu_vv, 0 }, | ||
| 663 | + { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsaddu_vx, rv_op_vsaddu_vx, 0 }, | ||
| 664 | + { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vsaddu_vi, rv_op_vsaddu_vi, 0 }, | ||
| 665 | + { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsadd_vv, rv_op_vsadd_vv, 0 }, | ||
| 666 | + { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsadd_vx, rv_op_vsadd_vx, 0 }, | ||
| 667 | + { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vsadd_vi, rv_op_vsadd_vi, 0 }, | ||
| 668 | + { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssubu_vv, rv_op_vssubu_vv, 0 }, | ||
| 669 | + { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssubu_vx, rv_op_vssubu_vx, 0 }, | ||
| 670 | + { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssub_vv, rv_op_vssub_vv, 0 }, | ||
| 671 | + { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssub_vx, rv_op_vssub_vx, 0 }, | ||
| 672 | + { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vaadd_vv, rv_op_vaadd_vv, 0 }, | ||
| 673 | + { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vaadd_vx, rv_op_vaadd_vx, 0 }, | ||
| 674 | + { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vaaddu_vv, rv_op_vaaddu_vv, 0 }, | ||
| 675 | + { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vaaddu_vx, rv_op_vaaddu_vx, 0 }, | ||
| 676 | + { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vasub_vv, rv_op_vasub_vv, 0 }, | ||
| 677 | + { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vasub_vx, rv_op_vasub_vx, 0 }, | ||
| 678 | + { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vasubu_vv, rv_op_vasubu_vv, 0 }, | ||
| 679 | + { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vasubu_vx, rv_op_vasubu_vx, 0 }, | ||
| 680 | + { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsmul_vv, rv_op_vsmul_vv, 0 }, | ||
| 681 | + { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsmul_vx, rv_op_vsmul_vx, 0 }, | ||
| 682 | + { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssrl_vv, rv_op_vssrl_vv, 0 }, | ||
| 683 | + { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssrl_vx, rv_op_vssrl_vx, 0 }, | ||
| 684 | + { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vssrl_vi, rv_op_vssrl_vi, 0 }, | ||
| 685 | + { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssra_vv, rv_op_vssra_vv, 0 }, | ||
| 686 | + { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssra_vx, rv_op_vssra_vx, 0 }, | ||
| 687 | + { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vssra_vi, rv_op_vssra_vi, 0 }, | ||
| 688 | + { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnclipu_wv, rv_op_vnclipu_wv, 0 }, | ||
| 689 | + { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnclipu_wx, rv_op_vnclipu_wx, 0 }, | ||
| 690 | + { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnclipu_wi, rv_op_vnclipu_wi, 0 }, | ||
| 691 | + { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnclip_wv, rv_op_vnclip_wv, 0 }, | ||
| 692 | + { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnclip_wx, rv_op_vnclip_wx, 0 }, | ||
| 693 | + { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnclip_wi, rv_op_vnclip_wi, 0 }, | ||
| 694 | + { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfadd_vv, rv_op_vfadd_vv, 0 }, | ||
| 695 | + { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfadd_vf, rv_op_vfadd_vf, 0 }, | ||
| 696 | + { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsub_vv, rv_op_vfsub_vv, 0 }, | ||
| 697 | + { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsub_vf, rv_op_vfsub_vf, 0 }, | ||
| 698 | + { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfrsub_vf, rv_op_vfrsub_vf, 0 }, | ||
| 699 | + { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwadd_vv, rv_op_vfwadd_vv, 0 }, | ||
| 700 | + { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwadd_vf, rv_op_vfwadd_vf, 0 }, | ||
| 701 | + { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwadd_wv, rv_op_vfwadd_wv, 0 }, | ||
| 702 | + { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwadd_wf, rv_op_vfwadd_wf, 0 }, | ||
| 703 | + { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwsub_vv, rv_op_vfwsub_vv, 0 }, | ||
| 704 | + { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwsub_vf, rv_op_vfwsub_vf, 0 }, | ||
| 705 | + { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwsub_wv, rv_op_vfwsub_wv, 0 }, | ||
| 706 | + { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwsub_wf, rv_op_vfwsub_wf, 0 }, | ||
| 707 | + { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmul_vv, rv_op_vfmul_vv, 0 }, | ||
| 708 | + { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmul_vf, rv_op_vfmul_vf, 0 }, | ||
| 709 | + { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfdiv_vv, rv_op_vfdiv_vv, 0 }, | ||
| 710 | + { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfdiv_vf, rv_op_vfdiv_vf, 0 }, | ||
| 711 | + { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfrdiv_vf, rv_op_vfrdiv_vf, 0 }, | ||
| 712 | + { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwmul_vv, rv_op_vfwmul_vv, 0 }, | ||
| 713 | + { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwmul_vf, rv_op_vfwmul_vf, 0 }, | ||
| 714 | + { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmacc_vv, rv_op_vfmacc_vv, 0 }, | ||
| 715 | + { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmacc_vf, rv_op_vfmacc_vf, 0 }, | ||
| 716 | + { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmacc_vv, rv_op_vfnmacc_vv, 0 }, | ||
| 717 | + { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmacc_vf, rv_op_vfnmacc_vf, 0 }, | ||
| 718 | + { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmsac_vv, rv_op_vfmsac_vv, 0 }, | ||
| 719 | + { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmsac_vf, rv_op_vfmsac_vf, 0 }, | ||
| 720 | + { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmsac_vv, rv_op_vfnmsac_vv, 0 }, | ||
| 721 | + { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmsac_vf, rv_op_vfnmsac_vf, 0 }, | ||
| 722 | + { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmadd_vv, rv_op_vfmadd_vv, 0 }, | ||
| 723 | + { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmadd_vf, rv_op_vfmadd_vf, 0 }, | ||
| 724 | + { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmadd_vv, rv_op_vfnmadd_vv, 0 }, | ||
| 725 | + { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmadd_vf, rv_op_vfnmadd_vf, 0 }, | ||
| 726 | + { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmsub_vv, rv_op_vfmsub_vv, 0 }, | ||
| 727 | + { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmsub_vf, rv_op_vfmsub_vf, 0 }, | ||
| 728 | + { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmsub_vv, rv_op_vfnmsub_vv, 0 }, | ||
| 729 | + { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmsub_vf, rv_op_vfnmsub_vf, 0 }, | ||
| 730 | + { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwmacc_vv, rv_op_vfwmacc_vv, 0 }, | ||
| 731 | + { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwmacc_vf, rv_op_vfwmacc_vf, 0 }, | ||
| 732 | + { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwnmacc_vv, rv_op_vfwnmacc_vv, 0 }, | ||
| 733 | + { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwnmacc_vf, rv_op_vfwnmacc_vf, 0 }, | ||
| 734 | + { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwmsac_vv, rv_op_vfwmsac_vv, 0 }, | ||
| 735 | + { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwmsac_vf, rv_op_vfwmsac_vf, 0 }, | ||
| 736 | + { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwnmsac_vv, rv_op_vfwnmsac_vv, 0 }, | ||
| 737 | + { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwnmsac_vf, rv_op_vfwnmsac_vf, 0 }, | ||
| 738 | + { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfsqrt_v, rv_op_vfsqrt_v, 0 }, | ||
| 739 | + { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfrsqrt7_v, rv_op_vfrsqrt7_v, 0 }, | ||
| 740 | + { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfrec7_v, rv_op_vfrec7_v, 0 }, | ||
| 741 | + { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmin_vv, rv_op_vfmin_vv, 0 }, | ||
| 742 | + { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmin_vf, rv_op_vfmin_vf, 0 }, | ||
| 743 | + { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmax_vv, rv_op_vfmax_vv, 0 }, | ||
| 744 | + { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmax_vf, rv_op_vfmax_vf, 0 }, | ||
| 745 | + { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnj_vv, rv_op_vfsgnj_vv, 0 }, | ||
| 746 | + { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnj_vf, rv_op_vfsgnj_vf, 0 }, | ||
| 747 | + { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnjn_vv, rv_op_vfsgnjn_vv, 0 }, | ||
| 748 | + { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnjn_vf, rv_op_vfsgnjn_vf, 0 }, | ||
| 749 | + { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnjx_vv, rv_op_vfsgnjx_vv, 0 }, | ||
| 750 | + { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnjx_vf, rv_op_vfsgnjx_vf, 0 }, | ||
| 751 | + { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfslide1up_vf, rv_op_vfslide1up_vf, 0 }, | ||
| 752 | + { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfslide1down_vf, rv_op_vfslide1down_vf, 0 }, | ||
| 753 | + { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfeq_vv, rv_op_vmfeq_vv, 0 }, | ||
| 754 | + { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfeq_vf, rv_op_vmfeq_vf, 0 }, | ||
| 755 | + { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfne_vv, rv_op_vmfne_vv, 0 }, | ||
| 756 | + { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfne_vf, rv_op_vmfne_vf, 0 }, | ||
| 757 | + { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmflt_vv, rv_op_vmflt_vv, 0 }, | ||
| 758 | + { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmflt_vf, rv_op_vmflt_vf, 0 }, | ||
| 759 | + { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfle_vv, rv_op_vmfle_vv, 0 }, | ||
| 760 | + { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfle_vf, rv_op_vmfle_vf, 0 }, | ||
| 761 | + { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfgt_vf, rv_op_vmfgt_vf, 0 }, | ||
| 762 | + { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfge_vf, rv_op_vmfge_vf, 0 }, | ||
| 763 | + { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfclass_v, rv_op_vfclass_v, 0 }, | ||
| 764 | + { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl, NULL, rv_op_vfmerge_vfm, rv_op_vfmerge_vfm, 0 }, | ||
| 765 | + { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, rv_op_vfmv_v_f, rv_op_vfmv_v_f, 0 }, | ||
| 766 | + { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_xu_f_v, rv_op_vfcvt_xu_f_v, 0 }, | ||
| 767 | + { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_x_f_v, rv_op_vfcvt_x_f_v, 0 }, | ||
| 768 | + { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_f_xu_v, rv_op_vfcvt_f_xu_v, 0 }, | ||
| 769 | + { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_f_x_v, rv_op_vfcvt_f_x_v, 0 }, | ||
| 770 | + { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_rtz_xu_f_v, rv_op_vfcvt_rtz_xu_f_v, 0 }, | ||
| 771 | + { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_rtz_x_f_v, rv_op_vfcvt_rtz_x_f_v, 0 }, | ||
| 772 | + { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_xu_f_v, rv_op_vfwcvt_xu_f_v, 0 }, | ||
| 773 | + { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_x_f_v, rv_op_vfwcvt_x_f_v, 0 }, | ||
| 774 | + { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_xu_v, rv_op_vfwcvt_f_xu_v, 0 }, | ||
| 775 | + { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_x_v, rv_op_vfwcvt_f_x_v, 0 }, | ||
| 776 | + { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_f_v, rv_op_vfwcvt_f_f_v, 0 }, | ||
| 777 | + { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_rtz_xu_f_v, rv_op_vfwcvt_rtz_xu_f_v, 0 }, | ||
| 778 | + { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_rtz_x_f_v, rv_op_vfwcvt_rtz_x_f_v, 0 }, | ||
| 779 | + { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_xu_f_w, rv_op_vfncvt_xu_f_w, 0 }, | ||
| 780 | + { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_x_f_w, rv_op_vfncvt_x_f_w, 0 }, | ||
| 781 | + { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_xu_w, rv_op_vfncvt_f_xu_w, 0 }, | ||
| 782 | + { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_x_w, rv_op_vfncvt_f_x_w, 0 }, | ||
| 783 | + { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_f_w, rv_op_vfncvt_f_f_w, 0 }, | ||
| 784 | + { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rod_f_f_w, rv_op_vfncvt_rod_f_f_w, 0 }, | ||
| 785 | + { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rtz_xu_f_w, rv_op_vfncvt_rtz_xu_f_w, 0 }, | ||
| 786 | + { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rtz_x_f_w, rv_op_vfncvt_rtz_x_f_w, 0 }, | ||
| 787 | + { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredsum_vs, rv_op_vredsum_vs, 0 }, | ||
| 788 | + { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredand_vs, rv_op_vredand_vs, 0 }, | ||
| 789 | + { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredor_vs, rv_op_vredor_vs, 0 }, | ||
| 790 | + { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredxor_vs, rv_op_vredxor_vs, 0 }, | ||
| 791 | + { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredminu_vs, rv_op_vredminu_vs, 0 }, | ||
| 792 | + { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmin_vs, rv_op_vredmin_vs, 0 }, | ||
| 793 | + { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmaxu_vs, rv_op_vredmaxu_vs, 0 }, | ||
| 794 | + { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmax_vs, rv_op_vredmax_vs, 0 }, | ||
| 795 | + { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwredsumu_vs, rv_op_vwredsumu_vs, 0 }, | ||
| 796 | + { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwredsum_vs, rv_op_vwredsum_vs, 0 }, | ||
| 797 | + { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredusum_vs, rv_op_vfredusum_vs, 0 }, | ||
| 798 | + { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredosum_vs, rv_op_vfredosum_vs, 0 }, | ||
| 799 | + { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredmin_vs, rv_op_vfredmin_vs, 0 }, | ||
| 800 | + { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredmax_vs, rv_op_vfredmax_vs, 0 }, | ||
| 801 | + { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwredusum_vs, rv_op_vfwredusum_vs, 0 }, | ||
| 802 | + { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwredosum_vs, rv_op_vfwredosum_vs, 0 }, | ||
| 803 | + { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmand_mm, rv_op_vmand_mm, 0 }, | ||
| 804 | + { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmnand_mm, rv_op_vmnand_mm, 0 }, | ||
| 805 | + { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmandn_mm, rv_op_vmandn_mm, 0 }, | ||
| 806 | + { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmxor_mm, rv_op_vmxor_mm, 0 }, | ||
| 807 | + { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmor_mm, rv_op_vmor_mm, 0 }, | ||
| 808 | + { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmnor_mm, rv_op_vmnor_mm, 0 }, | ||
| 809 | + { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmorn_mm, rv_op_vmorn_mm, 0 }, | ||
| 810 | + { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmxnor_mm, rv_op_vmxnor_mm, 0 }, | ||
| 811 | + { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, rv_op_vcpop_m, rv_op_vcpop_m, 0 }, | ||
| 812 | + { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, rv_op_vfirst_m, rv_op_vfirst_m, 0 }, | ||
| 813 | + { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsbf_m, rv_op_vmsbf_m, 0 }, | ||
| 814 | + { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsif_m, rv_op_vmsif_m, 0 }, | ||
| 815 | + { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsof_m, rv_op_vmsof_m, 0 }, | ||
| 816 | + { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_viota_m, rv_op_viota_m, 0 }, | ||
| 817 | + { "vid.v", rv_codec_v_r, rv_fmt_vd_vm, NULL, rv_op_vid_v, rv_op_vid_v, 0 }, | ||
| 818 | + { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2, NULL, rv_op_vmv_x_s, rv_op_vmv_x_s, 0 }, | ||
| 819 | + { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, rv_op_vmv_s_x, rv_op_vmv_s_x, 0 }, | ||
| 820 | + { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, rv_op_vfmv_f_s, rv_op_vfmv_f_s, 0 }, | ||
| 821 | + { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, rv_op_vfmv_s_f, rv_op_vfmv_s_f, 0 }, | ||
| 822 | + { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslideup_vx, rv_op_vslideup_vx, 0 }, | ||
| 823 | + { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vslideup_vi, rv_op_vslideup_vi, 0 }, | ||
| 824 | + { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslide1up_vx, rv_op_vslide1up_vx, 0 }, | ||
| 825 | + { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslidedown_vx, rv_op_vslidedown_vx, 0 }, | ||
| 826 | + { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vslidedown_vi, rv_op_vslidedown_vi, 0 }, | ||
| 827 | + { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslide1down_vx, rv_op_vslide1down_vx, 0 }, | ||
| 828 | + { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrgather_vv, rv_op_vrgather_vv, 0 }, | ||
| 829 | + { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrgatherei16_vv, rv_op_vrgatherei16_vv, 0 }, | ||
| 830 | + { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrgather_vx, rv_op_vrgather_vx, 0 }, | ||
| 831 | + { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vrgather_vi, rv_op_vrgather_vi, 0 }, | ||
| 832 | + { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, rv_op_vcompress_vm, rv_op_vcompress_vm, 0 }, | ||
| 833 | + { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv1r_v, rv_op_vmv1r_v, 0 }, | ||
| 834 | + { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv2r_v, rv_op_vmv2r_v, 0 }, | ||
| 835 | + { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv4r_v, rv_op_vmv4r_v, 0 }, | ||
| 836 | + { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv8r_v, rv_op_vmv8r_v, 0 }, | ||
| 837 | + { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf2, rv_op_vzext_vf2, 0 }, | ||
| 838 | + { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf4, rv_op_vzext_vf4, 0 }, | ||
| 839 | + { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf8, rv_op_vzext_vf8, 0 }, | ||
| 840 | + { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf2, rv_op_vsext_vf2, 0 }, | ||
| 841 | + { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf4, rv_op_vsext_vf4, 0 }, | ||
| 842 | + { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf8, rv_op_vsext_vf8, 0 }, | ||
| 843 | + { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, rv_op_vsetvli, rv_op_vsetvli, 0 }, | ||
| 844 | + { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, rv_op_vsetivli, rv_op_vsetivli, 0 }, | ||
| 845 | + { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 } | ||
| 846 | }; | ||
| 847 | |||
| 848 | /* CSR names */ | ||
| 849 | @@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno) | ||
| 850 | case 0x0003: return "fcsr"; | ||
| 851 | case 0x0004: return "uie"; | ||
| 852 | case 0x0005: return "utvec"; | ||
| 853 | + case 0x0008: return "vstart"; | ||
| 854 | + case 0x0009: return "vxsat"; | ||
| 855 | + case 0x000a: return "vxrm"; | ||
| 856 | + case 0x000f: return "vcsr"; | ||
| 857 | case 0x0015: return "seed"; | ||
| 858 | case 0x0040: return "uscratch"; | ||
| 859 | case 0x0041: return "uepc"; | ||
| 860 | @@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno) | ||
| 861 | case 0x0c00: return "cycle"; | ||
| 862 | case 0x0c01: return "time"; | ||
| 863 | case 0x0c02: return "instret"; | ||
| 864 | + case 0x0c20: return "vl"; | ||
| 865 | + case 0x0c21: return "vtype"; | ||
| 866 | + case 0x0c22: return "vlenb"; | ||
| 867 | case 0x0c80: return "cycleh"; | ||
| 868 | case 0x0c81: return "timeh"; | ||
| 869 | case 0x0c82: return "instreth"; | ||
| 870 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) | ||
| 871 | break; | ||
| 872 | case 1: | ||
| 873 | switch (((inst >> 12) & 0b111)) { | ||
| 874 | + case 0: | ||
| 875 | + switch (((inst >> 20) & 0b111111111111)) { | ||
| 876 | + case 40: op = rv_op_vl1re8_v; break; | ||
| 877 | + case 552: op = rv_op_vl2re8_v; break; | ||
| 878 | + case 1576: op = rv_op_vl4re8_v; break; | ||
| 879 | + case 3624: op = rv_op_vl8re8_v; break; | ||
| 880 | + } | ||
| 881 | + switch (((inst >> 26) & 0b111)) { | ||
| 882 | + case 0: | ||
| 883 | + switch (((inst >> 20) & 0b11111)) { | ||
| 884 | + case 0: op = rv_op_vle8_v; break; | ||
| 885 | + case 11: op = rv_op_vlm_v; break; | ||
| 886 | + case 16: op = rv_op_vle8ff_v; break; | ||
| 887 | + } | ||
| 888 | + break; | ||
| 889 | + case 1: op = rv_op_vluxei8_v; break; | ||
| 890 | + case 2: op = rv_op_vlse8_v; break; | ||
| 891 | + case 3: op = rv_op_vloxei8_v; break; | ||
| 892 | + } | ||
| 893 | + break; | ||
| 894 | case 2: op = rv_op_flw; break; | ||
| 895 | case 3: op = rv_op_fld; break; | ||
| 896 | case 4: op = rv_op_flq; break; | ||
| 897 | + case 5: | ||
| 898 | + switch (((inst >> 20) & 0b111111111111)) { | ||
| 899 | + case 40: op = rv_op_vl1re16_v; break; | ||
| 900 | + case 552: op = rv_op_vl2re16_v; break; | ||
| 901 | + case 1576: op = rv_op_vl4re16_v; break; | ||
| 902 | + case 3624: op = rv_op_vl8re16_v; break; | ||
| 903 | + } | ||
| 904 | + switch (((inst >> 26) & 0b111)) { | ||
| 905 | + case 0: | ||
| 906 | + switch (((inst >> 20) & 0b11111)) { | ||
| 907 | + case 0: op = rv_op_vle16_v; break; | ||
| 908 | + case 16: op = rv_op_vle16ff_v; break; | ||
| 909 | + } | ||
| 910 | + break; | ||
| 911 | + case 1: op = rv_op_vluxei16_v; break; | ||
| 912 | + case 2: op = rv_op_vlse16_v; break; | ||
| 913 | + case 3: op = rv_op_vloxei16_v; break; | ||
| 914 | + } | ||
| 915 | + break; | ||
| 916 | + case 6: | ||
| 917 | + switch (((inst >> 20) & 0b111111111111)) { | ||
| 918 | + case 40: op = rv_op_vl1re32_v; break; | ||
| 919 | + case 552: op = rv_op_vl2re32_v; break; | ||
| 920 | + case 1576: op = rv_op_vl4re32_v; break; | ||
| 921 | + case 3624: op = rv_op_vl8re32_v; break; | ||
| 922 | + } | ||
| 923 | + switch (((inst >> 26) & 0b111)) { | ||
| 924 | + case 0: | ||
| 925 | + switch (((inst >> 20) & 0b11111)) { | ||
| 926 | + case 0: op = rv_op_vle32_v; break; | ||
| 927 | + case 16: op = rv_op_vle32ff_v; break; | ||
| 928 | + } | ||
| 929 | + break; | ||
| 930 | + case 1: op = rv_op_vluxei32_v; break; | ||
| 931 | + case 2: op = rv_op_vlse32_v; break; | ||
| 932 | + case 3: op = rv_op_vloxei32_v; break; | ||
| 933 | + } | ||
| 934 | + break; | ||
| 935 | + case 7: | ||
| 936 | + switch (((inst >> 20) & 0b111111111111)) { | ||
| 937 | + case 40: op = rv_op_vl1re64_v; break; | ||
| 938 | + case 552: op = rv_op_vl2re64_v; break; | ||
| 939 | + case 1576: op = rv_op_vl4re64_v; break; | ||
| 940 | + case 3624: op = rv_op_vl8re64_v; break; | ||
| 941 | + } | ||
| 942 | + switch (((inst >> 26) & 0b111)) { | ||
| 943 | + case 0: | ||
| 944 | + switch (((inst >> 20) & 0b11111)) { | ||
| 945 | + case 0: op = rv_op_vle64_v; break; | ||
| 946 | + case 16: op = rv_op_vle64ff_v; break; | ||
| 947 | + } | ||
| 948 | + break; | ||
| 949 | + case 1: op = rv_op_vluxei64_v; break; | ||
| 950 | + case 2: op = rv_op_vlse64_v; break; | ||
| 951 | + case 3: op = rv_op_vloxei64_v; break; | ||
| 952 | + } | ||
| 953 | + break; | ||
| 954 | } | ||
| 955 | break; | ||
| 956 | case 3: | ||
| 957 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) | ||
| 958 | break; | ||
| 959 | case 9: | ||
| 960 | switch (((inst >> 12) & 0b111)) { | ||
| 961 | + case 0: | ||
| 962 | + switch (((inst >> 20) & 0b111111111111)) { | ||
| 963 | + case 40: op = rv_op_vs1r_v; break; | ||
| 964 | + case 552: op = rv_op_vs2r_v; break; | ||
| 965 | + case 1576: op = rv_op_vs4r_v; break; | ||
| 966 | + case 3624: op = rv_op_vs8r_v; break; | ||
| 967 | + } | ||
| 968 | + switch (((inst >> 26) & 0b111)) { | ||
| 969 | + case 0: | ||
| 970 | + switch (((inst >> 20) & 0b11111)) { | ||
| 971 | + case 0: op = rv_op_vse8_v; break; | ||
| 972 | + case 11: op = rv_op_vsm_v; break; | ||
| 973 | + } | ||
| 974 | + break; | ||
| 975 | + case 1: op = rv_op_vsuxei8_v; break; | ||
| 976 | + case 2: op = rv_op_vsse8_v; break; | ||
| 977 | + case 3: op = rv_op_vsoxei8_v; break; | ||
| 978 | + } | ||
| 979 | + break; | ||
| 980 | case 2: op = rv_op_fsw; break; | ||
| 981 | case 3: op = rv_op_fsd; break; | ||
| 982 | case 4: op = rv_op_fsq; break; | ||
| 983 | + case 5: | ||
| 984 | + switch (((inst >> 26) & 0b111)) { | ||
| 985 | + case 0: | ||
| 986 | + switch (((inst >> 20) & 0b11111)) { | ||
| 987 | + case 0: op = rv_op_vse16_v; break; | ||
| 988 | + } | ||
| 989 | + break; | ||
| 990 | + case 1: op = rv_op_vsuxei16_v; break; | ||
| 991 | + case 2: op = rv_op_vsse16_v; break; | ||
| 992 | + case 3: op = rv_op_vsoxei16_v; break; | ||
| 993 | + } | ||
| 994 | + break; | ||
| 995 | + case 6: | ||
| 996 | + switch (((inst >> 26) & 0b111)) { | ||
| 997 | + case 0: | ||
| 998 | + switch (((inst >> 20) & 0b11111)) { | ||
| 999 | + case 0: op = rv_op_vse32_v; break; | ||
| 1000 | + } | ||
| 1001 | + break; | ||
| 1002 | + case 1: op = rv_op_vsuxei32_v; break; | ||
| 1003 | + case 2: op = rv_op_vsse32_v; break; | ||
| 1004 | + case 3: op = rv_op_vsoxei32_v; break; | ||
| 1005 | + } | ||
| 1006 | + break; | ||
| 1007 | + case 7: | ||
| 1008 | + switch (((inst >> 26) & 0b111)) { | ||
| 1009 | + case 0: | ||
| 1010 | + switch (((inst >> 20) & 0b11111)) { | ||
| 1011 | + case 0: op = rv_op_vse64_v; break; | ||
| 1012 | + } | ||
| 1013 | + break; | ||
| 1014 | + case 1: op = rv_op_vsuxei64_v; break; | ||
| 1015 | + case 2: op = rv_op_vsse64_v; break; | ||
| 1016 | + case 3: op = rv_op_vsoxei64_v; break; | ||
| 1017 | + } | ||
| 1018 | + break; | ||
| 1019 | } | ||
| 1020 | break; | ||
| 1021 | case 11: | ||
| 1022 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) | ||
| 1023 | break; | ||
| 1024 | } | ||
| 1025 | break; | ||
| 1026 | + case 21: | ||
| 1027 | + switch (((inst >> 12) & 0b111)) { | ||
| 1028 | + case 0: | ||
| 1029 | + switch (((inst >> 26) & 0b111111)) { | ||
| 1030 | + case 0: op = rv_op_vadd_vv; break; | ||
| 1031 | + case 2: op = rv_op_vsub_vv; break; | ||
| 1032 | + case 4: op = rv_op_vminu_vv; break; | ||
| 1033 | + case 5: op = rv_op_vmin_vv; break; | ||
| 1034 | + case 6: op = rv_op_vmaxu_vv; break; | ||
| 1035 | + case 7: op = rv_op_vmax_vv; break; | ||
| 1036 | + case 9: op = rv_op_vand_vv; break; | ||
| 1037 | + case 10: op = rv_op_vor_vv; break; | ||
| 1038 | + case 11: op = rv_op_vxor_vv; break; | ||
| 1039 | + case 12: op = rv_op_vrgather_vv; break; | ||
| 1040 | + case 14: op = rv_op_vrgatherei16_vv; break; | ||
| 1041 | + case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vvm; break; | ||
| 1042 | + case 17: op = rv_op_vmadc_vvm; break; | ||
| 1043 | + case 18: if (((inst >> 25) & 1) == 0) op = rv_op_vsbc_vvm; break; | ||
| 1044 | + case 19: op = rv_op_vmsbc_vvm; break; | ||
| 1045 | + case 23: | ||
| 1046 | + if (((inst >> 20) & 0b111111) == 32) | ||
| 1047 | + op = rv_op_vmv_v_v; | ||
| 1048 | + else if (((inst >> 25) & 1) == 0) | ||
| 1049 | + op = rv_op_vmerge_vvm; | ||
| 1050 | + break; | ||
| 1051 | + case 24: op = rv_op_vmseq_vv; break; | ||
| 1052 | + case 25: op = rv_op_vmsne_vv; break; | ||
| 1053 | + case 26: op = rv_op_vmsltu_vv; break; | ||
| 1054 | + case 27: op = rv_op_vmslt_vv; break; | ||
| 1055 | + case 28: op = rv_op_vmsleu_vv; break; | ||
| 1056 | + case 29: op = rv_op_vmsle_vv; break; | ||
| 1057 | + case 32: op = rv_op_vsaddu_vv; break; | ||
| 1058 | + case 33: op = rv_op_vsadd_vv; break; | ||
| 1059 | + case 34: op = rv_op_vssubu_vv; break; | ||
| 1060 | + case 35: op = rv_op_vssub_vv; break; | ||
| 1061 | + case 37: op = rv_op_vsll_vv; break; | ||
| 1062 | + case 39: op = rv_op_vsmul_vv; break; | ||
| 1063 | + case 40: op = rv_op_vsrl_vv; break; | ||
| 1064 | + case 41: op = rv_op_vsra_vv; break; | ||
| 1065 | + case 42: op = rv_op_vssrl_vv; break; | ||
| 1066 | + case 43: op = rv_op_vssra_vv; break; | ||
| 1067 | + case 44: op = rv_op_vnsrl_wv; break; | ||
| 1068 | + case 45: op = rv_op_vnsra_wv; break; | ||
| 1069 | + case 46: op = rv_op_vnclipu_wv; break; | ||
| 1070 | + case 47: op = rv_op_vnclip_wv; break; | ||
| 1071 | + case 48: op = rv_op_vwredsumu_vs; break; | ||
| 1072 | + case 49: op = rv_op_vwredsum_vs; break; | ||
| 1073 | + } | ||
| 1074 | + break; | ||
| 1075 | + case 1: | ||
| 1076 | + switch (((inst >> 26) & 0b111111)) { | ||
| 1077 | + case 0: op = rv_op_vfadd_vv; break; | ||
| 1078 | + case 1: op = rv_op_vfredusum_vs; break; | ||
| 1079 | + case 2: op = rv_op_vfsub_vv; break; | ||
| 1080 | + case 3: op = rv_op_vfredosum_vs; break; | ||
| 1081 | + case 4: op = rv_op_vfmin_vv; break; | ||
| 1082 | + case 5: op = rv_op_vfredmin_vs; break; | ||
| 1083 | + case 6: op = rv_op_vfmax_vv; break; | ||
| 1084 | + case 7: op = rv_op_vfredmax_vs; break; | ||
| 1085 | + case 8: op = rv_op_vfsgnj_vv; break; | ||
| 1086 | + case 9: op = rv_op_vfsgnjn_vv; break; | ||
| 1087 | + case 10: op = rv_op_vfsgnjx_vv; break; | ||
| 1088 | + case 16: | ||
| 1089 | + switch (((inst >> 15) & 0b11111)) { | ||
| 1090 | + case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_f_s; break; | ||
| 1091 | + } | ||
| 1092 | + break; | ||
| 1093 | + case 18: | ||
| 1094 | + switch (((inst >> 15) & 0b11111)) { | ||
| 1095 | + case 0: op = rv_op_vfcvt_xu_f_v; break; | ||
| 1096 | + case 1: op = rv_op_vfcvt_x_f_v; break; | ||
| 1097 | + case 2: op = rv_op_vfcvt_f_xu_v; break; | ||
| 1098 | + case 3: op = rv_op_vfcvt_f_x_v; break; | ||
| 1099 | + case 6: op = rv_op_vfcvt_rtz_xu_f_v; break; | ||
| 1100 | + case 7: op = rv_op_vfcvt_rtz_x_f_v; break; | ||
| 1101 | + case 8: op = rv_op_vfwcvt_xu_f_v; break; | ||
| 1102 | + case 9: op = rv_op_vfwcvt_x_f_v; break; | ||
| 1103 | + case 10: op = rv_op_vfwcvt_f_xu_v; break; | ||
| 1104 | + case 11: op = rv_op_vfwcvt_f_x_v; break; | ||
| 1105 | + case 12: op = rv_op_vfwcvt_f_f_v; break; | ||
| 1106 | + case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break; | ||
| 1107 | + case 15: op = rv_op_vfwcvt_rtz_x_f_v; break; | ||
| 1108 | + case 16: op = rv_op_vfncvt_xu_f_w; break; | ||
| 1109 | + case 17: op = rv_op_vfncvt_x_f_w; break; | ||
| 1110 | + case 18: op = rv_op_vfncvt_f_xu_w; break; | ||
| 1111 | + case 19: op = rv_op_vfncvt_f_x_w; break; | ||
| 1112 | + case 20: op = rv_op_vfncvt_f_f_w; break; | ||
| 1113 | + case 21: op = rv_op_vfncvt_rod_f_f_w; break; | ||
| 1114 | + case 22: op = rv_op_vfncvt_rtz_xu_f_w; break; | ||
| 1115 | + case 23: op = rv_op_vfncvt_rtz_x_f_w; break; | ||
| 1116 | + } | ||
| 1117 | + break; | ||
| 1118 | + case 19: | ||
| 1119 | + switch (((inst >> 15) & 0b11111)) { | ||
| 1120 | + case 0: op = rv_op_vfsqrt_v; break; | ||
| 1121 | + case 4: op = rv_op_vfrsqrt7_v; break; | ||
| 1122 | + case 5: op = rv_op_vfrec7_v; break; | ||
| 1123 | + case 16: op = rv_op_vfclass_v; break; | ||
| 1124 | + } | ||
| 1125 | + break; | ||
| 1126 | + case 24: op = rv_op_vmfeq_vv; break; | ||
| 1127 | + case 25: op = rv_op_vmfle_vv; break; | ||
| 1128 | + case 27: op = rv_op_vmflt_vv; break; | ||
| 1129 | + case 28: op = rv_op_vmfne_vv; break; | ||
| 1130 | + case 32: op = rv_op_vfdiv_vv; break; | ||
| 1131 | + case 36: op = rv_op_vfmul_vv; break; | ||
| 1132 | + case 40: op = rv_op_vfmadd_vv; break; | ||
| 1133 | + case 41: op = rv_op_vfnmadd_vv; break; | ||
| 1134 | + case 42: op = rv_op_vfmsub_vv; break; | ||
| 1135 | + case 43: op = rv_op_vfnmsub_vv; break; | ||
| 1136 | + case 44: op = rv_op_vfmacc_vv; break; | ||
| 1137 | + case 45: op = rv_op_vfnmacc_vv; break; | ||
| 1138 | + case 46: op = rv_op_vfmsac_vv; break; | ||
| 1139 | + case 47: op = rv_op_vfnmsac_vv; break; | ||
| 1140 | + case 48: op = rv_op_vfwadd_vv; break; | ||
| 1141 | + case 49: op = rv_op_vfwredusum_vs; break; | ||
| 1142 | + case 50: op = rv_op_vfwsub_vv; break; | ||
| 1143 | + case 51: op = rv_op_vfwredosum_vs; break; | ||
| 1144 | + case 52: op = rv_op_vfwadd_wv; break; | ||
| 1145 | + case 54: op = rv_op_vfwsub_wv; break; | ||
| 1146 | + case 56: op = rv_op_vfwmul_vv; break; | ||
| 1147 | + case 60: op = rv_op_vfwmacc_vv; break; | ||
| 1148 | + case 61: op = rv_op_vfwnmacc_vv; break; | ||
| 1149 | + case 62: op = rv_op_vfwmsac_vv; break; | ||
| 1150 | + case 63: op = rv_op_vfwnmsac_vv; break; | ||
| 1151 | + } | ||
| 1152 | + break; | ||
| 1153 | + case 2: | ||
| 1154 | + switch (((inst >> 26) & 0b111111)) { | ||
| 1155 | + case 0: op = rv_op_vredsum_vs; break; | ||
| 1156 | + case 1: op = rv_op_vredand_vs; break; | ||
| 1157 | + case 2: op = rv_op_vredor_vs; break; | ||
| 1158 | + case 3: op = rv_op_vredxor_vs; break; | ||
| 1159 | + case 4: op = rv_op_vredminu_vs; break; | ||
| 1160 | + case 5: op = rv_op_vredmin_vs; break; | ||
| 1161 | + case 6: op = rv_op_vredmaxu_vs; break; | ||
| 1162 | + case 7: op = rv_op_vredmax_vs; break; | ||
| 1163 | + case 8: op = rv_op_vaaddu_vv; break; | ||
| 1164 | + case 9: op = rv_op_vaadd_vv; break; | ||
| 1165 | + case 10: op = rv_op_vasubu_vv; break; | ||
| 1166 | + case 11: op = rv_op_vasub_vv; break; | ||
| 1167 | + case 16: | ||
| 1168 | + switch (((inst >> 15) & 0b11111)) { | ||
| 1169 | + case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break; | ||
| 1170 | + case 16: op = rv_op_vcpop_m; break; | ||
| 1171 | + case 17: op = rv_op_vfirst_m; break; | ||
| 1172 | + } | ||
| 1173 | + break; | ||
| 1174 | + case 18: | ||
| 1175 | + switch (((inst >> 15) & 0b11111)) { | ||
| 1176 | + case 2: op = rv_op_vzext_vf8; break; | ||
| 1177 | + case 3: op = rv_op_vsext_vf8; break; | ||
| 1178 | + case 4: op = rv_op_vzext_vf4; break; | ||
| 1179 | + case 5: op = rv_op_vsext_vf4; break; | ||
| 1180 | + case 6: op = rv_op_vzext_vf2; break; | ||
| 1181 | + case 7: op = rv_op_vsext_vf2; break; | ||
| 1182 | + } | ||
| 1183 | + break; | ||
| 1184 | + case 20: | ||
| 1185 | + switch (((inst >> 15) & 0b11111)) { | ||
| 1186 | + case 1: op = rv_op_vmsbf_m; break; | ||
| 1187 | + case 2: op = rv_op_vmsof_m; break; | ||
| 1188 | + case 3: op = rv_op_vmsif_m; break; | ||
| 1189 | + case 16: op = rv_op_viota_m; break; | ||
| 1190 | + case 17: if (((inst >> 20) & 0b11111) == 0) op = rv_op_vid_v; break; | ||
| 1191 | + } | ||
| 1192 | + break; | ||
| 1193 | + case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break; | ||
| 1194 | + case 24: if ((inst >> 25) & 1) op = rv_op_vmandn_mm; break; | ||
| 1195 | + case 25: if ((inst >> 25) & 1) op = rv_op_vmand_mm; break; | ||
| 1196 | + case 26: if ((inst >> 25) & 1) op = rv_op_vmor_mm; break; | ||
| 1197 | + case 27: if ((inst >> 25) & 1) op = rv_op_vmxor_mm; break; | ||
| 1198 | + case 28: if ((inst >> 25) & 1) op = rv_op_vmorn_mm; break; | ||
| 1199 | + case 29: if ((inst >> 25) & 1) op = rv_op_vmnand_mm; break; | ||
| 1200 | + case 30: if ((inst >> 25) & 1) op = rv_op_vmnor_mm; break; | ||
| 1201 | + case 31: if ((inst >> 25) & 1) op = rv_op_vmxnor_mm; break; | ||
| 1202 | + case 32: op = rv_op_vdivu_vv; break; | ||
| 1203 | + case 33: op = rv_op_vdiv_vv; break; | ||
| 1204 | + case 34: op = rv_op_vremu_vv; break; | ||
| 1205 | + case 35: op = rv_op_vrem_vv; break; | ||
| 1206 | + case 36: op = rv_op_vmulhu_vv; break; | ||
| 1207 | + case 37: op = rv_op_vmul_vv; break; | ||
| 1208 | + case 38: op = rv_op_vmulhsu_vv; break; | ||
| 1209 | + case 39: op = rv_op_vmulh_vv; break; | ||
| 1210 | + case 41: op = rv_op_vmadd_vv; break; | ||
| 1211 | + case 43: op = rv_op_vnmsub_vv; break; | ||
| 1212 | + case 45: op = rv_op_vmacc_vv; break; | ||
| 1213 | + case 47: op = rv_op_vnmsac_vv; break; | ||
| 1214 | + case 48: op = rv_op_vwaddu_vv; break; | ||
| 1215 | + case 49: op = rv_op_vwadd_vv; break; | ||
| 1216 | + case 50: op = rv_op_vwsubu_vv; break; | ||
| 1217 | + case 51: op = rv_op_vwsub_vv; break; | ||
| 1218 | + case 52: op = rv_op_vwaddu_wv; break; | ||
| 1219 | + case 53: op = rv_op_vwadd_wv; break; | ||
| 1220 | + case 54: op = rv_op_vwsubu_wv; break; | ||
| 1221 | + case 55: op = rv_op_vwsub_wv; break; | ||
| 1222 | + case 56: op = rv_op_vwmulu_vv; break; | ||
| 1223 | + case 58: op = rv_op_vwmulsu_vv; break; | ||
| 1224 | + case 59: op = rv_op_vwmul_vv; break; | ||
| 1225 | + case 60: op = rv_op_vwmaccu_vv; break; | ||
| 1226 | + case 61: op = rv_op_vwmacc_vv; break; | ||
| 1227 | + case 63: op = rv_op_vwmaccsu_vv; break; | ||
| 1228 | + } | ||
| 1229 | + break; | ||
| 1230 | + case 3: | ||
| 1231 | + switch (((inst >> 26) & 0b111111)) { | ||
| 1232 | + case 0: op = rv_op_vadd_vi; break; | ||
| 1233 | + case 3: op = rv_op_vrsub_vi; break; | ||
| 1234 | + case 9: op = rv_op_vand_vi; break; | ||
| 1235 | + case 10: op = rv_op_vor_vi; break; | ||
| 1236 | + case 11: op = rv_op_vxor_vi; break; | ||
| 1237 | + case 12: op = rv_op_vrgather_vi; break; | ||
| 1238 | + case 14: op = rv_op_vslideup_vi; break; | ||
| 1239 | + case 15: op = rv_op_vslidedown_vi; break; | ||
| 1240 | + case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vim; break; | ||
| 1241 | + case 17: op = rv_op_vmadc_vim; break; | ||
| 1242 | + case 23: | ||
| 1243 | + if (((inst >> 20) & 0b111111) == 32) | ||
| 1244 | + op = rv_op_vmv_v_i; | ||
| 1245 | + else if (((inst >> 25) & 1) == 0) | ||
| 1246 | + op = rv_op_vmerge_vim; | ||
| 1247 | + break; | ||
| 1248 | + case 24: op = rv_op_vmseq_vi; break; | ||
| 1249 | + case 25: op = rv_op_vmsne_vi; break; | ||
| 1250 | + case 28: op = rv_op_vmsleu_vi; break; | ||
| 1251 | + case 29: op = rv_op_vmsle_vi; break; | ||
| 1252 | + case 30: op = rv_op_vmsgtu_vi; break; | ||
| 1253 | + case 31: op = rv_op_vmsgt_vi; break; | ||
| 1254 | + case 32: op = rv_op_vsaddu_vi; break; | ||
| 1255 | + case 33: op = rv_op_vsadd_vi; break; | ||
| 1256 | + case 37: op = rv_op_vsll_vi; break; | ||
| 1257 | + case 39: | ||
| 1258 | + switch (((inst >> 15) & 0b11111)) { | ||
| 1259 | + case 0: op = rv_op_vmv1r_v; break; | ||
| 1260 | + case 1: op = rv_op_vmv2r_v; break; | ||
| 1261 | + case 3: op = rv_op_vmv4r_v; break; | ||
| 1262 | + case 7: op = rv_op_vmv8r_v; break; | ||
| 1263 | + } | ||
| 1264 | + break; | ||
| 1265 | + case 40: op = rv_op_vsrl_vi; break; | ||
| 1266 | + case 41: op = rv_op_vsra_vi; break; | ||
| 1267 | + case 42: op = rv_op_vssrl_vi; break; | ||
| 1268 | + case 43: op = rv_op_vssra_vi; break; | ||
| 1269 | + case 44: op = rv_op_vnsrl_wi; break; | ||
| 1270 | + case 45: op = rv_op_vnsra_wi; break; | ||
| 1271 | + case 46: op = rv_op_vnclipu_wi; break; | ||
| 1272 | + case 47: op = rv_op_vnclip_wi; break; | ||
| 1273 | + } | ||
| 1274 | + break; | ||
| 1275 | + case 4: | ||
| 1276 | + switch (((inst >> 26) & 0b111111)) { | ||
| 1277 | + case 0: op = rv_op_vadd_vx; break; | ||
| 1278 | + case 2: op = rv_op_vsub_vx; break; | ||
| 1279 | + case 3: op = rv_op_vrsub_vx; break; | ||
| 1280 | + case 4: op = rv_op_vminu_vx; break; | ||
| 1281 | + case 5: op = rv_op_vmin_vx; break; | ||
| 1282 | + case 6: op = rv_op_vmaxu_vx; break; | ||
| 1283 | + case 7: op = rv_op_vmax_vx; break; | ||
| 1284 | + case 9: op = rv_op_vand_vx; break; | ||
| 1285 | + case 10: op = rv_op_vor_vx; break; | ||
| 1286 | + case 11: op = rv_op_vxor_vx; break; | ||
| 1287 | + case 12: op = rv_op_vrgather_vx; break; | ||
| 1288 | + case 14: op = rv_op_vslideup_vx; break; | ||
| 1289 | + case 15: op = rv_op_vslidedown_vx; break; | ||
| 1290 | + case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vxm; break; | ||
| 1291 | + case 17: op = rv_op_vmadc_vxm; break; | ||
| 1292 | + case 18: if (((inst >> 25) & 1) == 0) op = rv_op_vsbc_vxm; break; | ||
| 1293 | + case 19: op = rv_op_vmsbc_vxm; break; | ||
| 1294 | + case 23: | ||
| 1295 | + if (((inst >> 20) & 0b111111) == 32) | ||
| 1296 | + op = rv_op_vmv_v_x; | ||
| 1297 | + else if (((inst >> 25) & 1) == 0) | ||
| 1298 | + op = rv_op_vmerge_vxm; | ||
| 1299 | + break; | ||
| 1300 | + case 24: op = rv_op_vmseq_vx; break; | ||
| 1301 | + case 25: op = rv_op_vmsne_vx; break; | ||
| 1302 | + case 26: op = rv_op_vmsltu_vx; break; | ||
| 1303 | + case 27: op = rv_op_vmslt_vx; break; | ||
| 1304 | + case 28: op = rv_op_vmsleu_vx; break; | ||
| 1305 | + case 29: op = rv_op_vmsle_vx; break; | ||
| 1306 | + case 30: op = rv_op_vmsgtu_vx; break; | ||
| 1307 | + case 31: op = rv_op_vmsgt_vx; break; | ||
| 1308 | + case 32: op = rv_op_vsaddu_vx; break; | ||
| 1309 | + case 33: op = rv_op_vsadd_vx; break; | ||
| 1310 | + case 34: op = rv_op_vssubu_vx; break; | ||
| 1311 | + case 35: op = rv_op_vssub_vx; break; | ||
| 1312 | + case 37: op = rv_op_vsll_vx; break; | ||
| 1313 | + case 39: op = rv_op_vsmul_vx; break; | ||
| 1314 | + case 40: op = rv_op_vsrl_vx; break; | ||
| 1315 | + case 41: op = rv_op_vsra_vx; break; | ||
| 1316 | + case 42: op = rv_op_vssrl_vx; break; | ||
| 1317 | + case 43: op = rv_op_vssra_vx; break; | ||
| 1318 | + case 44: op = rv_op_vnsrl_wx; break; | ||
| 1319 | + case 45: op = rv_op_vnsra_wx; break; | ||
| 1320 | + case 46: op = rv_op_vnclipu_wx; break; | ||
| 1321 | + case 47: op = rv_op_vnclip_wx; break; | ||
| 1322 | + } | ||
| 1323 | + break; | ||
| 1324 | + case 5: | ||
| 1325 | + switch (((inst >> 26) & 0b111111)) { | ||
| 1326 | + case 0: op = rv_op_vfadd_vf; break; | ||
| 1327 | + case 2: op = rv_op_vfsub_vf; break; | ||
| 1328 | + case 4: op = rv_op_vfmin_vf; break; | ||
| 1329 | + case 6: op = rv_op_vfmax_vf; break; | ||
| 1330 | + case 8: op = rv_op_vfsgnj_vf; break; | ||
| 1331 | + case 9: op = rv_op_vfsgnjn_vf; break; | ||
| 1332 | + case 10: op = rv_op_vfsgnjx_vf; break; | ||
| 1333 | + case 14: op = rv_op_vfslide1up_vf; break; | ||
| 1334 | + case 15: op = rv_op_vfslide1down_vf; break; | ||
| 1335 | + case 16: | ||
| 1336 | + switch (((inst >> 20) & 0b11111)) { | ||
| 1337 | + case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_s_f; break; | ||
| 1338 | + } | ||
| 1339 | + break; | ||
| 1340 | + case 23: | ||
| 1341 | + if (((inst >> 25) & 1) == 0) | ||
| 1342 | + op = rv_op_vfmerge_vfm; | ||
| 1343 | + else if (((inst >> 20) & 0b111111) == 32) | ||
| 1344 | + op = rv_op_vfmv_v_f; | ||
| 1345 | + break; | ||
| 1346 | + case 24: op = rv_op_vmfeq_vf; break; | ||
| 1347 | + case 25: op = rv_op_vmfle_vf; break; | ||
| 1348 | + case 27: op = rv_op_vmflt_vf; break; | ||
| 1349 | + case 28: op = rv_op_vmfne_vf; break; | ||
| 1350 | + case 29: op = rv_op_vmfgt_vf; break; | ||
| 1351 | + case 31: op = rv_op_vmfge_vf; break; | ||
| 1352 | + case 32: op = rv_op_vfdiv_vf; break; | ||
| 1353 | + case 33: op = rv_op_vfrdiv_vf; break; | ||
| 1354 | + case 36: op = rv_op_vfmul_vf; break; | ||
| 1355 | + case 39: op = rv_op_vfrsub_vf; break; | ||
| 1356 | + case 40: op = rv_op_vfmadd_vf; break; | ||
| 1357 | + case 41: op = rv_op_vfnmadd_vf; break; | ||
| 1358 | + case 42: op = rv_op_vfmsub_vf; break; | ||
| 1359 | + case 43: op = rv_op_vfnmsub_vf; break; | ||
| 1360 | + case 44: op = rv_op_vfmacc_vf; break; | ||
| 1361 | + case 45: op = rv_op_vfnmacc_vf; break; | ||
| 1362 | + case 46: op = rv_op_vfmsac_vf; break; | ||
| 1363 | + case 47: op = rv_op_vfnmsac_vf; break; | ||
| 1364 | + case 48: op = rv_op_vfwadd_vf; break; | ||
| 1365 | + case 50: op = rv_op_vfwsub_vf; break; | ||
| 1366 | + case 52: op = rv_op_vfwadd_wf; break; | ||
| 1367 | + case 54: op = rv_op_vfwsub_wf; break; | ||
| 1368 | + case 56: op = rv_op_vfwmul_vf; break; | ||
| 1369 | + case 60: op = rv_op_vfwmacc_vf; break; | ||
| 1370 | + case 61: op = rv_op_vfwnmacc_vf; break; | ||
| 1371 | + case 62: op = rv_op_vfwmsac_vf; break; | ||
| 1372 | + case 63: op = rv_op_vfwnmsac_vf; break; | ||
| 1373 | + } | ||
| 1374 | + break; | ||
| 1375 | + case 6: | ||
| 1376 | + switch (((inst >> 26) & 0b111111)) { | ||
| 1377 | + case 8: op = rv_op_vaaddu_vx; break; | ||
| 1378 | + case 9: op = rv_op_vaadd_vx; break; | ||
| 1379 | + case 10: op = rv_op_vasubu_vx; break; | ||
| 1380 | + case 11: op = rv_op_vasub_vx; break; | ||
| 1381 | + case 14: op = rv_op_vslide1up_vx; break; | ||
| 1382 | + case 15: op = rv_op_vslide1down_vx; break; | ||
| 1383 | + case 16: | ||
| 1384 | + switch (((inst >> 20) & 0b11111)) { | ||
| 1385 | + case 0: if ((inst >> 25) & 1) op = rv_op_vmv_s_x; break; | ||
| 1386 | + } | ||
| 1387 | + break; | ||
| 1388 | + case 32: op = rv_op_vdivu_vx; break; | ||
| 1389 | + case 33: op = rv_op_vdiv_vx; break; | ||
| 1390 | + case 34: op = rv_op_vremu_vx; break; | ||
| 1391 | + case 35: op = rv_op_vrem_vx; break; | ||
| 1392 | + case 36: op = rv_op_vmulhu_vx; break; | ||
| 1393 | + case 37: op = rv_op_vmul_vx; break; | ||
| 1394 | + case 38: op = rv_op_vmulhsu_vx; break; | ||
| 1395 | + case 39: op = rv_op_vmulh_vx; break; | ||
| 1396 | + case 41: op = rv_op_vmadd_vx; break; | ||
| 1397 | + case 43: op = rv_op_vnmsub_vx; break; | ||
| 1398 | + case 45: op = rv_op_vmacc_vx; break; | ||
| 1399 | + case 47: op = rv_op_vnmsac_vx; break; | ||
| 1400 | + case 48: op = rv_op_vwaddu_vx; break; | ||
| 1401 | + case 49: op = rv_op_vwadd_vx; break; | ||
| 1402 | + case 50: op = rv_op_vwsubu_vx; break; | ||
| 1403 | + case 51: op = rv_op_vwsub_vx; break; | ||
| 1404 | + case 52: op = rv_op_vwaddu_wx; break; | ||
| 1405 | + case 53: op = rv_op_vwadd_wx; break; | ||
| 1406 | + case 54: op = rv_op_vwsubu_wx; break; | ||
| 1407 | + case 55: op = rv_op_vwsub_wx; break; | ||
| 1408 | + case 56: op = rv_op_vwmulu_vx; break; | ||
| 1409 | + case 58: op = rv_op_vwmulsu_vx; break; | ||
| 1410 | + case 59: op = rv_op_vwmul_vx; break; | ||
| 1411 | + case 60: op = rv_op_vwmaccu_vx; break; | ||
| 1412 | + case 61: op = rv_op_vwmacc_vx; break; | ||
| 1413 | + case 62: op = rv_op_vwmaccus_vx; break; | ||
| 1414 | + case 63: op = rv_op_vwmaccsu_vx; break; | ||
| 1415 | + } | ||
| 1416 | + break; | ||
| 1417 | + case 7: | ||
| 1418 | + if (((inst >> 31) & 1) == 0) { | ||
| 1419 | + op = rv_op_vsetvli; | ||
| 1420 | + } else if ((inst >> 30) & 1) { | ||
| 1421 | + op = rv_op_vsetivli; | ||
| 1422 | + } else if (((inst >> 25) & 0b11111) == 0) { | ||
| 1423 | + op = rv_op_vsetvl; | ||
| 1424 | + } | ||
| 1425 | + break; | ||
| 1426 | + } | ||
| 1427 | + break; | ||
| 1428 | case 22: | ||
| 1429 | switch (((inst >> 12) & 0b111)) { | ||
| 1430 | case 0: op = rv_op_addid; break; | ||
| 1431 | @@ -XXX,XX +XXX,XX @@ static uint32_t operand_cimmq(rv_inst inst) | ||
| 1432 | ((inst << 57) >> 62) << 6; | ||
| 1433 | } | ||
| 1434 | |||
| 1435 | +static uint32_t operand_vimm(rv_inst inst) | ||
| 1436 | +{ | ||
| 1437 | + return (int64_t)(inst << 44) >> 59; | ||
| 1438 | +} | ||
| 1439 | + | ||
| 1440 | +static uint32_t operand_vzimm11(rv_inst inst) | ||
| 1441 | +{ | ||
| 1442 | + return (inst << 33) >> 53; | ||
| 1443 | +} | ||
| 1444 | + | ||
| 1445 | +static uint32_t operand_vzimm10(rv_inst inst) | ||
| 1446 | +{ | ||
| 1447 | + return (inst << 34) >> 54; | ||
| 1448 | +} | ||
| 1449 | + | ||
| 1450 | static uint32_t operand_bs(rv_inst inst) | ||
| 1451 | { | ||
| 1452 | return (inst << 32) >> 62; | ||
| 1453 | @@ -XXX,XX +XXX,XX @@ static uint32_t operand_rnum(rv_inst inst) | ||
| 1454 | return (inst << 40) >> 60; | ||
| 1455 | } | ||
| 1456 | |||
| 1457 | +static uint32_t operand_vm(rv_inst inst) | ||
| 1458 | +{ | ||
| 1459 | + return (inst << 38) >> 63; | ||
| 1460 | +} | ||
| 1461 | + | ||
| 1462 | /* decode operands */ | ||
| 1463 | |||
| 1464 | static void decode_inst_operands(rv_decode *dec, rv_isa isa) | ||
| 1465 | @@ -XXX,XX +XXX,XX @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa) | ||
| 1466 | dec->rs1 = operand_rs1(inst); | ||
| 1467 | dec->rnum = operand_rnum(inst); | ||
| 1468 | break; | ||
| 1469 | + case rv_codec_v_r: | ||
| 1470 | + dec->rd = operand_rd(inst); | ||
| 1471 | + dec->rs1 = operand_rs1(inst); | ||
| 1472 | + dec->rs2 = operand_rs2(inst); | ||
| 1473 | + dec->vm = operand_vm(inst); | ||
| 1474 | + break; | ||
| 1475 | + case rv_codec_v_ldst: | ||
| 1476 | + dec->rd = operand_rd(inst); | ||
| 1477 | + dec->rs1 = operand_rs1(inst); | ||
| 1478 | + dec->vm = operand_vm(inst); | ||
| 1479 | + break; | ||
| 1480 | + case rv_codec_v_i: | ||
| 1481 | + dec->rd = operand_rd(inst); | ||
| 1482 | + dec->rs2 = operand_rs2(inst); | ||
| 1483 | + dec->imm = operand_vimm(inst); | ||
| 1484 | + dec->vm = operand_vm(inst); | ||
| 1485 | + break; | ||
| 1486 | + case rv_codec_vsetvli: | ||
| 1487 | + dec->rd = operand_rd(inst); | ||
| 1488 | + dec->rs1 = operand_rs1(inst); | ||
| 1489 | + dec->vzimm = operand_vzimm11(inst); | ||
| 1490 | + break; | ||
| 1491 | + case rv_codec_vsetivli: | ||
| 1492 | + dec->rd = operand_rd(inst); | ||
| 1493 | + dec->imm = operand_vimm(inst); | ||
| 1494 | + dec->vzimm = operand_vzimm10(inst); | ||
| 1495 | + break; | ||
| 1496 | }; | ||
| 1497 | } | ||
| 1498 | |||
| 1499 | @@ -XXX,XX +XXX,XX @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec) | ||
| 1500 | snprintf(tmp, sizeof(tmp), "%d", dec->imm); | ||
| 1501 | append(buf, tmp, buflen); | ||
| 1502 | break; | ||
| 1503 | + case 'u': | ||
| 1504 | + snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b11111)); | ||
| 1505 | + append(buf, tmp, buflen); | ||
| 1506 | + break; | ||
| 1507 | case 'o': | ||
| 1508 | snprintf(tmp, sizeof(tmp), "%d", dec->imm); | ||
| 1509 | append(buf, tmp, buflen); | ||
| 1510 | @@ -XXX,XX +XXX,XX @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec) | ||
| 1511 | append(buf, ".rl", buflen); | ||
| 1512 | } | ||
| 1513 | break; | ||
| 1514 | + case 'l': | ||
| 1515 | + append(buf, ",v0", buflen); | ||
| 1516 | + break; | ||
| 1517 | + case 'm': | ||
| 1518 | + if (dec->vm == 0) { | ||
| 1519 | + append(buf, ",v0.t", buflen); | ||
| 1520 | + } | ||
| 1521 | + break; | ||
| 1522 | + case 'D': | ||
| 1523 | + append(buf, rv_vreg_name_sym[dec->rd], buflen); | ||
| 1524 | + break; | ||
| 1525 | + case 'E': | ||
| 1526 | + append(buf, rv_vreg_name_sym[dec->rs1], buflen); | ||
| 1527 | + break; | ||
| 1528 | + case 'F': | ||
| 1529 | + append(buf, rv_vreg_name_sym[dec->rs2], buflen); | ||
| 1530 | + break; | ||
| 1531 | + case 'G': | ||
| 1532 | + append(buf, rv_vreg_name_sym[dec->rs3], buflen); | ||
| 1533 | + break; | ||
| 1534 | + case 'v': { | ||
| 1535 | + char nbuf[32] = {0}; | ||
| 1536 | + const int sew = 1 << (((dec->vzimm >> 3) & 0b111) + 3); | ||
| 1537 | + sprintf(nbuf, "%d", sew); | ||
| 1538 | + const int lmul = dec->vzimm & 0b11; | ||
| 1539 | + const int flmul = (dec->vzimm >> 2) & 1; | ||
| 1540 | + const char *vta = (dec->vzimm >> 6) & 1 ? "ta" : "tu"; | ||
| 1541 | + const char *vma = (dec->vzimm >> 7) & 1 ? "ma" : "mu"; | ||
| 1542 | + append(buf, "e", buflen); | ||
| 1543 | + append(buf, nbuf, buflen); | ||
| 1544 | + append(buf, ",m", buflen); | ||
| 1545 | + if (flmul) { | ||
| 1546 | + switch (lmul) { | ||
| 1547 | + case 3: | ||
| 1548 | + sprintf(nbuf, "f2"); | ||
| 1549 | + break; | ||
| 1550 | + case 2: | ||
| 1551 | + sprintf(nbuf, "f4"); | ||
| 1552 | + break; | ||
| 1553 | + case 1: | ||
| 1554 | + sprintf(nbuf, "f8"); | ||
| 1555 | + break; | ||
| 1556 | + } | ||
| 1557 | + append(buf, nbuf, buflen); | ||
| 1558 | + } else { | ||
| 1559 | + sprintf(nbuf, "%d", 1 << lmul); | ||
| 1560 | + append(buf, nbuf, buflen); | ||
| 1561 | + } | ||
| 1562 | + append(buf, ",", buflen); | ||
| 1563 | + append(buf, vta, buflen); | ||
| 1564 | + append(buf, ",", buflen); | ||
| 1565 | + append(buf, vma, buflen); | ||
| 1566 | + break; | ||
| 1567 | + } | ||
| 1568 | default: | ||
| 1569 | break; | ||
| 1570 | } | ||
| 1571 | @@ -XXX,XX +XXX,XX @@ disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst) | ||
| 1572 | decode_inst_operands(&dec, isa); | ||
| 1573 | decode_inst_decompress(&dec, isa); | ||
| 1574 | decode_inst_lift_pseudo(&dec); | ||
| 1575 | - format_inst(buf, buflen, 16, &dec); | ||
| 1576 | + format_inst(buf, buflen, 24, &dec); | ||
| 1577 | } | ||
| 1578 | |||
| 1579 | #define INST_FMT_2 "%04" PRIx64 " " | ||
| 1580 | -- | ||
| 1581 | 2.37.3 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Jim Shu <jim.shu@sifive.com> | ||
| 1 | 2 | ||
| 3 | The maximum priority level is hard-coded when writing to interrupt | ||
| 4 | priority register. However, when writing to priority threshold register, | ||
| 5 | the maximum priority level is from num_priorities Property which is | ||
| 6 | configured by platform. | ||
| 7 | |||
| 8 | Also change interrupt priority register to use num_priorities Property | ||
| 9 | in maximum priority level. | ||
| 10 | |||
| 11 | Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com> | ||
| 12 | Signed-off-by: Jim Shu <jim.shu@sifive.com> | ||
| 13 | Reviewed-by: Frank Chang <frank.chang@sifive.com> | ||
| 14 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 15 | Message-Id: <20221003041440.2320-2-jim.shu@sifive.com> | ||
| 16 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 17 | --- | ||
| 18 | hw/intc/sifive_plic.c | 6 ++++-- | ||
| 19 | 1 file changed, 4 insertions(+), 2 deletions(-) | ||
| 20 | |||
| 21 | diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c | ||
| 22 | index XXXXXXX..XXXXXXX 100644 | ||
| 23 | --- a/hw/intc/sifive_plic.c | ||
| 24 | +++ b/hw/intc/sifive_plic.c | ||
| 25 | @@ -XXX,XX +XXX,XX @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value, | ||
| 26 | if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) { | ||
| 27 | uint32_t irq = ((addr - plic->priority_base) >> 2) + 1; | ||
| 28 | |||
| 29 | - plic->source_priority[irq] = value & 7; | ||
| 30 | - sifive_plic_update(plic); | ||
| 31 | + if (value <= plic->num_priorities) { | ||
| 32 | + plic->source_priority[irq] = value; | ||
| 33 | + sifive_plic_update(plic); | ||
| 34 | + } | ||
| 35 | } else if (addr_between(addr, plic->pending_base, | ||
| 36 | plic->num_sources >> 3)) { | ||
| 37 | qemu_log_mask(LOG_GUEST_ERROR, | ||
| 38 | -- | ||
| 39 | 2.37.3 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Jim Shu <jim.shu@sifive.com> | ||
| 1 | 2 | ||
| 3 | PLIC spec [1] requires interrupt source priority registers are WARL | ||
| 4 | field and the number of supported priority is power-of-2 to simplify SW | ||
| 5 | discovery. | ||
| 6 | |||
| 7 | Existing QEMU RISC-V machine (e.g. shakti_c) don't strictly follow PLIC | ||
| 8 | spec, whose number of supported priority is not power-of-2. Just change | ||
| 9 | each bit of interrupt priority register to WARL field when the number of | ||
| 10 | supported priority is power-of-2. | ||
| 11 | |||
| 12 | [1] https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-priorities | ||
| 13 | |||
| 14 | Signed-off-by: Jim Shu <jim.shu@sifive.com> | ||
| 15 | Reviewed-by: Clément Chigot <chigot@adacore.com> | ||
| 16 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 17 | Message-Id: <20221003041440.2320-3-jim.shu@sifive.com> | ||
| 18 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 19 | --- | ||
| 20 | hw/intc/sifive_plic.c | 21 +++++++++++++++++++-- | ||
| 21 | 1 file changed, 19 insertions(+), 2 deletions(-) | ||
| 22 | |||
| 23 | diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c | ||
| 24 | index XXXXXXX..XXXXXXX 100644 | ||
| 25 | --- a/hw/intc/sifive_plic.c | ||
| 26 | +++ b/hw/intc/sifive_plic.c | ||
| 27 | @@ -XXX,XX +XXX,XX @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value, | ||
| 28 | if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) { | ||
| 29 | uint32_t irq = ((addr - plic->priority_base) >> 2) + 1; | ||
| 30 | |||
| 31 | - if (value <= plic->num_priorities) { | ||
| 32 | + if (((plic->num_priorities + 1) & plic->num_priorities) == 0) { | ||
| 33 | + /* | ||
| 34 | + * if "num_priorities + 1" is power-of-2, make each register bit of | ||
| 35 | + * interrupt priority WARL (Write-Any-Read-Legal). Just filter | ||
| 36 | + * out the access to unsupported priority bits. | ||
| 37 | + */ | ||
| 38 | + plic->source_priority[irq] = value % (plic->num_priorities + 1); | ||
| 39 | + sifive_plic_update(plic); | ||
| 40 | + } else if (value <= plic->num_priorities) { | ||
| 41 | plic->source_priority[irq] = value; | ||
| 42 | sifive_plic_update(plic); | ||
| 43 | } | ||
| 44 | @@ -XXX,XX +XXX,XX @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value, | ||
| 45 | uint32_t contextid = (addr & (plic->context_stride - 1)); | ||
| 46 | |||
| 47 | if (contextid == 0) { | ||
| 48 | - if (value <= plic->num_priorities) { | ||
| 49 | + if (((plic->num_priorities + 1) & plic->num_priorities) == 0) { | ||
| 50 | + /* | ||
| 51 | + * if "num_priorities + 1" is power-of-2, each register bit of | ||
| 52 | + * interrupt priority is WARL (Write-Any-Read-Legal). Just | ||
| 53 | + * filter out the access to unsupported priority bits. | ||
| 54 | + */ | ||
| 55 | + plic->target_priority[addrid] = value % | ||
| 56 | + (plic->num_priorities + 1); | ||
| 57 | + sifive_plic_update(plic); | ||
| 58 | + } else if (value <= plic->num_priorities) { | ||
| 59 | plic->target_priority[addrid] = value; | ||
| 60 | sifive_plic_update(plic); | ||
| 61 | } | ||
| 62 | -- | ||
| 63 | 2.37.3 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Alistair Francis <alistair.francis@wdc.com> | ||
| 1 | 2 | ||
| 3 | Since commit 4047368938f6 "accel/tcg: Introduce tlb_set_page_full" we | ||
| 4 | have been seeing this assert | ||
| 5 | |||
| 6 | ../accel/tcg/cputlb.c:1294: tlb_set_page_with_attrs: Assertion `is_power_of_2(size)' failed. | ||
| 7 | |||
| 8 | When running Tock on the OpenTitan machine. | ||
| 9 | |||
| 10 | The issue is that pmp_get_tlb_size() would return a TLB size that wasn't | ||
| 11 | a power of 2. The size was also smaller then TARGET_PAGE_SIZE. | ||
| 12 | |||
| 13 | This patch ensures that any TLB size less then TARGET_PAGE_SIZE is | ||
| 14 | rounded down to 1 to ensure it's a valid size. | ||
| 15 | |||
| 16 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 17 | Reviewed-by: LIU Zhiwei<zhiwei_liu@linux.alibaba.com> | ||
| 18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 19 | Message-id: 20221012011449.506928-1-alistair.francis@opensource.wdc.com | ||
| 20 | Message-Id: <20221012011449.506928-1-alistair.francis@opensource.wdc.com> | ||
| 21 | --- | ||
| 22 | target/riscv/pmp.c | 12 ++++++++++++ | ||
| 23 | 1 file changed, 12 insertions(+) | ||
| 24 | |||
| 25 | diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c | ||
| 26 | index XXXXXXX..XXXXXXX 100644 | ||
| 27 | --- a/target/riscv/pmp.c | ||
| 28 | +++ b/target/riscv/pmp.c | ||
| 29 | @@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa, | ||
| 30 | } | ||
| 31 | |||
| 32 | if (*tlb_size != 0) { | ||
| 33 | + /* | ||
| 34 | + * At this point we have a tlb_size that is the smallest possible size | ||
| 35 | + * That fits within a TARGET_PAGE_SIZE and the PMP region. | ||
| 36 | + * | ||
| 37 | + * If the size is less then TARGET_PAGE_SIZE we drop the size to 1. | ||
| 38 | + * This means the result isn't cached in the TLB and is only used for | ||
| 39 | + * a single translation. | ||
| 40 | + */ | ||
| 41 | + if (*tlb_size < TARGET_PAGE_SIZE) { | ||
| 42 | + *tlb_size = 1; | ||
| 43 | + } | ||
| 44 | + | ||
| 45 | return true; | ||
| 46 | } | ||
| 47 | |||
| 48 | -- | ||
| 49 | 2.37.3 | diff view generated by jsdifflib |