The following changes since commit 6160d8ff81fb9fba70f5dad88d43ffd0fa44984c:

Merge tag 'edgar/xilinx-next-2022-09-21.for-upstream' of https://github.com/edgarigl/qemu into staging (2022-09-22 13:24:28 -0400)

git@github.com:alistair23/qemu.git pull-riscv-to-apply-20220923-2

for you to fetch changes up to a4260684f8e2c8722d1feae0d41d956fc4109007:

hw/riscv/sifive_e: Fix inheritance of SiFiveEState (2022-09-23 09:11:34 +1000)

Second RISC-V PR for QEMU 7.2

* Fixup typos and register addresses for Ibex SPI

* Cleanup the RISC-V virt machine documentation

* Remove the sideleg and sedeleg CSR macros

* Fix the CSR check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}

* Remove fixed numbering from GDB xml feature files

* Allow setting the resetvec for the OpenTitan machine

* Check the correct exception cause in vector GDB stub

* Fix inheritance of SiFiveEState

Alex Bennée (1):

docs/system: clean up code escape for riscv virt platform

Alistair Francis (3):

target/riscv: Set the CPU resetvec directly

hw/riscv: opentitan: Fixup resetvec

hw/riscv: opentitan: Expose the resetvec as a SoC property

Andrew Burgess (2):

target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml

target/riscv: remove fixed numbering from GDB xml feature files

From: Alistair Francis <alistair.francis@wdc.com>

Instead of using our properties to set a config value which then might

be used to set the resetvec (depending on your timing), let's instead

just set the resetvec directly in the env struct.

This allows us to set the reset vec from the command line with:

-global driver=riscv.hart_array,property=resetvec,value=0x20000400

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-Id: <20220914101108.82571-2-alistair.francis@wdc.com>

target/riscv/cpu.h | 3 +--

target/riscv/cpu.c | 13 +++----------

target/riscv/machine.c | 6 +++---

3 files changed, 7 insertions(+), 15 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h

--- a/target/riscv/cpu.h

+++ b/target/riscv/cpu.h

@@ -XXX,XX +XXX,XX @@ struct CPUArchState {

/* This contains QEMU specific information about the virt state. */

target_ulong virt;

target_ulong geilen;

- target_ulong resetvec;

+ uint64_t resetvec;

target_ulong mhartid;

/*

@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {

bool pmp;

bool epmp;

bool debug;

- uint64_t resetvec;

bool short_isa_string;

};

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c

index XXXXXXX..XXXXXXX 100644

--- a/target/riscv/cpu.c

+++ b/target/riscv/cpu.c

@@ -XXX,XX +XXX,XX @@ static void set_vext_version(CPURISCVState *env, int vext_ver)

env->vext_ver = vext_ver;

}

-static void set_resetvec(CPURISCVState *env, target_ulong resetvec)

-{

-#ifndef CONFIG_USER_ONLY

- env->resetvec = resetvec;

-#endif

static void riscv_any_cpu_init(Object *obj)

{

CPURISCVState *env = &RISCV_CPU(obj)->env;

@@ -XXX,XX +XXX,XX @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)

set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);

set_priv_version(env, PRIV_VERSION_1_10_0);

- set_resetvec(env, DEFAULT_RSTVEC);

cpu->cfg.mmu = false;

}

#endif

@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)

riscv_set_feature(env, RISCV_FEATURE_DEBUG);

- set_resetvec(env, cpu->cfg.resetvec);

#ifndef CONFIG_USER_ONLY

if (cpu->cfg.ext_sstc) {

@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {

DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),

DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),

- DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),

+#ifndef CONFIG_USER_ONLY

+ DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),

+#endif

DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),

diff --git a/target/riscv/machine.c b/target/riscv/machine.c

index XXXXXXX..XXXXXXX 100644

--- a/target/riscv/machine.c

+++ b/target/riscv/machine.c

@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmu_ctr_state = {

const VMStateDescription vmstate_riscv_cpu = {

.name = "cpu",

- .version_id = 4,

- .minimum_version_id = 4,

+ .version_id = 5,

+ .minimum_version_id = 5,

.post_load = riscv_cpu_post_load,

.fields = (VMStateField[]) {

VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),

@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {

VMSTATE_UINT32(env.features, RISCVCPU),

VMSTATE_UINTTL(env.priv, RISCVCPU),

VMSTATE_UINTTL(env.virt, RISCVCPU),

- VMSTATE_UINTTL(env.resetvec, RISCVCPU),

+ VMSTATE_UINT64(env.resetvec, RISCVCPU),

VMSTATE_UINTTL(env.mhartid, RISCVCPU),

VMSTATE_UINT64(env.mstatus, RISCVCPU),

VMSTATE_UINT64(env.mip, RISCVCPU),

2.37.3

From: Bernhard Beschow <shentey@gmail.com>

SiFiveEState inherits from SysBusDevice while it's TypeInfo claims it to

inherit from TYPE_MACHINE. This is an inconsistency which can cause

undefined behavior such as memory corruption.

Change SiFiveEState to inherit from MachineState since it is registered

as a machine.

Fixes: 0869490b1c ("riscv: sifive_e: Manually define the machine")

Signed-off-by: Bernhard Beschow <shentey@gmail.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-Id: <20220922075232.33653-1-shentey@gmail.com>

include/hw/riscv/sifive_e.h | 3 ++-

1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h

--- a/include/hw/riscv/sifive_e.h

+++ b/include/hw/riscv/sifive_e.h

@@ -XXX,XX +XXX,XX @@

#include "hw/riscv/riscv_hart.h"

#include "hw/riscv/sifive_cpu.h"

#include "hw/gpio/sifive_gpio.h"

+#include "hw/boards.h"

#define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"

#define RISCV_E_SOC(obj) \

@@ -XXX,XX +XXX,XX @@ typedef struct SiFiveESoCState {

typedef struct SiFiveEState {

/*< private >*/

- SysBusDevice parent_obj;

+ MachineState parent_obj;

/*< public >*/

SiFiveESoCState soc;

2.37.3