[PULL 00/12] riscv-to-apply queue

Alistair Francis posted 12 patches 6 days ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20220923040704.428285-1-alistair.francis@opensource.wdc.com
There is a newer version of this series
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, "Alex Bennée" <alex.bennee@linaro.org>, "Philippe Mathieu-Daudé" <f4bug@amsat.org>, Bin Meng <bin.meng@windriver.com>
docs/system/riscv/virt.rst   | 13 +++++++++----
include/hw/riscv/opentitan.h |  2 ++
include/hw/riscv/sifive_e.h  |  3 ++-
target/riscv/cpu.h           |  3 +--
target/riscv/cpu_bits.h      |  2 --
disas/riscv.c                |  2 --
hw/riscv/opentitan.c         |  8 +++++++-
hw/ssi/ibex_spi_host.c       |  8 ++++----
target/riscv/cpu.c           | 13 +++----------
target/riscv/csr.c           | 13 +++++++++----
target/riscv/gdbstub.c       | 36 ++++--------------------------------
target/riscv/machine.c       |  6 +++---
gdb-xml/riscv-32bit-cpu.xml  |  6 +-----
gdb-xml/riscv-32bit-fpu.xml  | 10 +---------
gdb-xml/riscv-64bit-cpu.xml  |  6 +-----
gdb-xml/riscv-64bit-fpu.xml  | 10 +---------
16 files changed, 48 insertions(+), 93 deletions(-)
[PULL 00/12] riscv-to-apply queue
Posted by Alistair Francis 6 days ago
From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 6160d8ff81fb9fba70f5dad88d43ffd0fa44984c:

  Merge tag 'edgar/xilinx-next-2022-09-21.for-upstream' of https://github.com/edgarigl/qemu into staging (2022-09-22 13:24:28 -0400)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git pull-riscv-to-apply-20220923-2

for you to fetch changes up to a4260684f8e2c8722d1feae0d41d956fc4109007:

  hw/riscv/sifive_e: Fix inheritance of SiFiveEState (2022-09-23 09:11:34 +1000)

----------------------------------------------------------------
Second RISC-V PR for QEMU 7.2

* Fixup typos and register addresses for Ibex SPI
* Cleanup the RISC-V virt machine documentation
* Remove the sideleg and sedeleg CSR macros
* Fix the CSR check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}
* Remove fixed numbering from GDB xml feature files
* Allow setting the resetvec for the OpenTitan machine
* Check the correct exception cause in vector GDB stub
* Fix inheritance of SiFiveEState

----------------------------------------------------------------
Alex Bennée (1):
      docs/system: clean up code escape for riscv virt platform

Alistair Francis (3):
      target/riscv: Set the CPU resetvec directly
      hw/riscv: opentitan: Fixup resetvec
      hw/riscv: opentitan: Expose the resetvec as a SoC property

Andrew Burgess (2):
      target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml
      target/riscv: remove fixed numbering from GDB xml feature files

Bernhard Beschow (1):
      hw/riscv/sifive_e: Fix inheritance of SiFiveEState

Frank Chang (1):
      target/riscv: Check the correct exception cause in vector GDB stub

Rahul Pathak (1):
      target/riscv: Remove sideleg and sedeleg

Weiwei Li (1):
      target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}

Wilfred Mallawa (2):
      hw/ssi: ibex_spi: fixup typos in ibex_spi_host
      hw/ssi: ibex_spi: update reg addr

 docs/system/riscv/virt.rst   | 13 +++++++++----
 include/hw/riscv/opentitan.h |  2 ++
 include/hw/riscv/sifive_e.h  |  3 ++-
 target/riscv/cpu.h           |  3 +--
 target/riscv/cpu_bits.h      |  2 --
 disas/riscv.c                |  2 --
 hw/riscv/opentitan.c         |  8 +++++++-
 hw/ssi/ibex_spi_host.c       |  8 ++++----
 target/riscv/cpu.c           | 13 +++----------
 target/riscv/csr.c           | 13 +++++++++----
 target/riscv/gdbstub.c       | 36 ++++--------------------------------
 target/riscv/machine.c       |  6 +++---
 gdb-xml/riscv-32bit-cpu.xml  |  6 +-----
 gdb-xml/riscv-32bit-fpu.xml  | 10 +---------
 gdb-xml/riscv-64bit-cpu.xml  |  6 +-----
 gdb-xml/riscv-64bit-fpu.xml  | 10 +---------
 16 files changed, 48 insertions(+), 93 deletions(-)
Re: [PULL 00/12] riscv-to-apply queue
Posted by Stefan Hajnoczi 2 days, 9 hours ago
On Fri, 23 Sept 2022 at 00:08, Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
> are available in the Git repository at:
>
>   git@github.com:alistair23/qemu.git pull-riscv-to-apply-20220923-2

Hi Alistair,
Please use the HTTPS GitHub repo URL in pull requests. Setting
separate "url" (HTTPS) and "pushUrl" (ssh) settings for your remote in
git-config(1) should solve this problem.

Stefan
Re: [PULL 00/12] riscv-to-apply queue
Posted by Alistair Francis 2 days, 7 hours ago
On Tue, Sep 27, 2022 at 5:29 AM Stefan Hajnoczi <stefanha@gmail.com> wrote:
>
> On Fri, 23 Sept 2022 at 00:08, Alistair Francis
> <alistair.francis@opensource.wdc.com> wrote:
> > are available in the Git repository at:
> >
> >   git@github.com:alistair23/qemu.git pull-riscv-to-apply-20220923-2
>
> Hi Alistair,
> Please use the HTTPS GitHub repo URL in pull requests. Setting
> separate "url" (HTTPS) and "pushUrl" (ssh) settings for your remote in
> git-config(1) should solve this problem.

Ah! Ok, now I see. I do have a separate `pushUrl` but I didn't update
my script. I wasn't clear on what you were asking for last time. I'll
update and resend.

Alistair

>
> Stefan
Re: [PULL 00/12] riscv-to-apply queue
Posted by Stefan Hajnoczi 2 days, 7 hours ago
On Mon, 26 Sept 2022 at 17:00, Alistair Francis <alistair23@gmail.com> wrote:
>
> On Tue, Sep 27, 2022 at 5:29 AM Stefan Hajnoczi <stefanha@gmail.com> wrote:
> >
> > On Fri, 23 Sept 2022 at 00:08, Alistair Francis
> > <alistair.francis@opensource.wdc.com> wrote:
> > > are available in the Git repository at:
> > >
> > >   git@github.com:alistair23/qemu.git pull-riscv-to-apply-20220923-2
> >
> > Hi Alistair,
> > Please use the HTTPS GitHub repo URL in pull requests. Setting
> > separate "url" (HTTPS) and "pushUrl" (ssh) settings for your remote in
> > git-config(1) should solve this problem.
>
> Ah! Ok, now I see. I do have a separate `pushUrl` but I didn't update
> my script. I wasn't clear on what you were asking for last time. I'll
> update and resend.

Thanks!

Stefan