docs/system/riscv/microchip-icicle-kit.rst | 54 +++++++++--

docs/system/riscv/sifive_u.rst | 2 +-

docs/system/riscv/virt.rst | 138 +++++++++++++++++++++++++++++

docs/system/target-riscv.rst | 1 +

include/hw/riscv/opentitan.h | 3 +

hw/char/ibex_uart.c | 19 ++--

hw/riscv/boot.c | 6 +-

hw/riscv/opentitan.c | 9 ++

hw/riscv/sifive_u.c | 12 ++-

target/riscv/csr.c | 78 +++++++---------

target/riscv/pmp.c | 10 +--

11 files changed, 257 insertions(+), 75 deletions(-)

create mode 100644 docs/system/riscv/virt.rst

From: Bin Meng <bmeng.cn@gmail.com>

%s/CSP/CSR

%s/thie/the

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Message-id: 20210627115716.3552-1-bmeng.cn@gmail.com

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

---

target/riscv/pmp.c | 10 +++++-----

1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c

index XXXXXXX..XXXXXXX 100644

--- a/target/riscv/pmp.c

+++ b/target/riscv/pmp.c

@@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,

}

/*

- * Handle a write to a pmpcfg CSP

+ * Handle a write to a pmpcfg CSR

*/

void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,

target_ulong val)

@@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,

/*

- * Handle a read from a pmpcfg CSP

+ * Handle a read from a pmpcfg CSR

*/

target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)

{

@@ -XXX,XX +XXX,XX @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)

/*

- * Handle a write to a pmpaddr CSP

+ * Handle a write to a pmpaddr CSR

*/

void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,

target_ulong val)

@@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,

/*

- * Handle a read from a pmpaddr CSP

+ * Handle a read from a pmpaddr CSR

*/

target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)

{

@@ -XXX,XX +XXX,XX @@ target_ulong mseccfg_csr_read(CPURISCVState *env)

/*

* Calculate the TLB size if the start address or the end address of

- * PMP entry is presented in thie TLB page.

+ * PMP entry is presented in the TLB page.

*/

static target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,

target_ulong tlb_sa, target_ulong tlb_ea)

--

2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

The following check:

if (!env->debugger && !riscv_cpu_fp_enabled(env)) {

return -RISCV_EXCP_ILLEGAL_INST;

}

is redundant in fflags/frm/fcsr read/write routines, as the check was

already done in fs().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Message-id: 20210627120604.11116-1-bmeng.cn@gmail.com

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

---

target/riscv/csr.c | 24 ------------------------

1 file changed, 24 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c

index XXXXXXX..XXXXXXX 100644

--- a/target/riscv/csr.c

+++ b/target/riscv/csr.c

@@ -XXX,XX +XXX,XX @@ static RISCVException epmp(CPURISCVState *env, int csrno)

static RISCVException read_fflags(CPURISCVState *env, int csrno,

target_ulong *val)

{

-#if !defined(CONFIG_USER_ONLY)

- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {

- return RISCV_EXCP_ILLEGAL_INST;

- }

-#endif

*val = riscv_cpu_get_fflags(env);

return RISCV_EXCP_NONE;

}

@@ -XXX,XX +XXX,XX @@ static RISCVException write_fflags(CPURISCVState *env, int csrno,

target_ulong val)

{

#if !defined(CONFIG_USER_ONLY)

- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {

- return RISCV_EXCP_ILLEGAL_INST;

- }

env->mstatus |= MSTATUS_FS;

#endif

riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));

@@ -XXX,XX +XXX,XX @@ static RISCVException write_fflags(CPURISCVState *env, int csrno,

static RISCVException read_frm(CPURISCVState *env, int csrno,

target_ulong *val)

{

-#if !defined(CONFIG_USER_ONLY)

- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {

- return RISCV_EXCP_ILLEGAL_INST;

- }

-#endif

*val = env->frm;

return RISCV_EXCP_NONE;

}

@@ -XXX,XX +XXX,XX @@ static RISCVException write_frm(CPURISCVState *env, int csrno,

target_ulong val)

{

#if !defined(CONFIG_USER_ONLY)

- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {

- return RISCV_EXCP_ILLEGAL_INST;

- }

env->mstatus |= MSTATUS_FS;

#endif

env->frm = val & (FSR_RD >> FSR_RD_SHIFT);

@@ -XXX,XX +XXX,XX @@ static RISCVException write_frm(CPURISCVState *env, int csrno,

static RISCVException read_fcsr(CPURISCVState *env, int csrno,

target_ulong *val)

{

-#if !defined(CONFIG_USER_ONLY)

- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {

- return RISCV_EXCP_ILLEGAL_INST;

- }

-#endif

*val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)

| (env->frm << FSR_RD_SHIFT);

if (vs(env, csrno) >= 0) {

@@ -XXX,XX +XXX,XX @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno,

target_ulong val)

{

#if !defined(CONFIG_USER_ONLY)

- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {

- return RISCV_EXCP_ILLEGAL_INST;

- }

env->mstatus |= MSTATUS_FS;

#endif

env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;

--

2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

It's Core *Local* Interruptor, not 'Level'.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Message-id: 20210627142816.19789-1-bmeng.cn@gmail.com

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

---

docs/system/riscv/sifive_u.rst | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst

index XXXXXXX..XXXXXXX 100644

--- a/docs/system/riscv/sifive_u.rst

+++ b/docs/system/riscv/sifive_u.rst

@@ -XXX,XX +XXX,XX @@ The ``sifive_u`` machine supports the following devices:

* 1 E51 / E31 core

* Up to 4 U54 / U34 cores

-* Core Level Interruptor (CLINT)

+* Core Local Interruptor (CLINT)

* Platform-Level Interrupt Controller (PLIC)

* Power, Reset, Clock, Interrupt (PRCI)

* L2 Loosely Integrated Memory (L2-LIM)

--

2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

This adds detailed documentation for RISC-V `virt` machine,

including the following information:

- Supported devices

- Hardware configuration information

- Boot options

- Running Linux kernel

- Running U-Boot

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Message-id: 20210627142816.19789-2-bmeng.cn@gmail.com

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

---

docs/system/riscv/virt.rst | 138 +++++++++++++++++++++++++++++++++++

docs/system/target-riscv.rst | 1 +

2 files changed, 139 insertions(+)

create mode 100644 docs/system/riscv/virt.rst

diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/docs/system/riscv/virt.rst

@@ -XXX,XX +XXX,XX @@

+'virt' Generic Virtual Platform (``virt``)

+==========================================

+

+The `virt` board is a platform which does not correspond to any real hardware;

+it is designed for use in virtual machines. It is the recommended board type

+if you simply want to run a guest such as Linux and do not care about

+reproducing the idiosyncrasies and limitations of a particular bit of

+real-world hardware.

+

+Supported devices

+-----------------

+

+The ``virt`` machine supports the following devices:

+

+* Up to 8 generic RV32GC/RV64GC cores, with optional extensions

+* Core Local Interruptor (CLINT)

+* Platform-Level Interrupt Controller (PLIC)

+* CFI parallel NOR flash memory

+* 1 NS16550 compatible UART

+* 1 Google Goldfish RTC

+* 1 SiFive Test device

+* 8 virtio-mmio transport devices

+* 1 generic PCIe host bridge

+* The fw_cfg device that allows a guest to obtain data from QEMU

+

+Note that the default CPU is a generic RV32GC/RV64GC. Optional extensions

+can be enabled via command line parameters, e.g.: ``-cpu rv64,x-h=true``

+enables the hypervisor extension for RV64.

+

+Hardware configuration information

+----------------------------------

+

+The ``virt`` machine automatically generates a device tree blob ("dtb")

+which it passes to the guest, if there is no ``-dtb`` option. This provides

+information about the addresses, interrupt lines and other configuration of

+the various devices in the system. Guest software should discover the devices

+that are present in the generated DTB.

+

+If users want to provide their own DTB, they can use the ``-dtb`` option.

+These DTBs should have the following requirements:

+

+* The number of subnodes of the /cpus node should match QEMU's ``-smp`` option

+* The /memory reg size should match QEMU’s selected ram_size via ``-m``

+* Should contain a node for the CLINT device with a compatible string

+ "riscv,clint0" if using with OpenSBI BIOS images

+

+Boot options

+------------

+

+The ``virt`` machine can start using the standard -kernel functionality

+for loading a Linux kernel, a VxWorks kernel, an S-mode U-Boot bootloader

+with the default OpenSBI firmware image as the -bios. It also supports

+the recommended RISC-V bootflow: U-Boot SPL (M-mode) loads OpenSBI fw_dynamic

+firmware and U-Boot proper (S-mode), using the standard -bios functionality.

+

+Running Linux kernel

+--------------------

+

+Linux mainline v5.12 release is tested at the time of writing. To build a

+Linux mainline kernel that can be booted by the ``virt`` machine in

+64-bit mode, simply configure the kernel using the defconfig configuration:

+

+.. code-block:: bash

+

+ $ export ARCH=riscv

+ $ export CROSS_COMPILE=riscv64-linux-

+ $ make defconfig

+ $ make

+

+To boot the newly built Linux kernel in QEMU with the ``virt`` machine:

+

+.. code-block:: bash

+

+ $ qemu-system-riscv64 -M virt -smp 4 -m 2G \

+ -display none -serial stdio \

+ -kernel arch/riscv/boot/Image \

+ -initrd /path/to/rootfs.cpio \

+ -append "root=/dev/ram"

+

+To build a Linux mainline kernel that can be booted by the ``virt`` machine

+in 32-bit mode, use the rv32_defconfig configuration. A patch is required to

+fix the 32-bit boot issue for Linux kernel v5.12.

+

+.. code-block:: bash

+

+ $ export ARCH=riscv

+ $ export CROSS_COMPILE=riscv64-linux-

+ $ curl https://patchwork.kernel.org/project/linux-riscv/patch/20210627135117.28641-1-bmeng.cn@gmail.com/mbox/ > riscv.patch

+ $ git am riscv.patch

+ $ make rv32_defconfig

+ $ make

+

+Replace ``qemu-system-riscv64`` with ``qemu-system-riscv32`` in the command

+line above to boot the 32-bit Linux kernel. A rootfs image containing 32-bit

+applications shall be used in order for kernel to boot to user space.

+

+Running U-Boot

+--------------

+

+U-Boot mainline v2021.04 release is tested at the time of writing. To build an

+S-mode U-Boot bootloader that can be booted by the ``virt`` machine, use

+the qemu-riscv64_smode_defconfig with similar commands as described above for Linux:

+

+.. code-block:: bash

+

+ $ export CROSS_COMPILE=riscv64-linux-

+ $ make qemu-riscv64_smode_defconfig

+

+Boot the 64-bit U-Boot S-mode image directly:

+

+.. code-block:: bash

+

+ $ qemu-system-riscv64 -M virt -smp 4 -m 2G \

+ -display none -serial stdio \

+ -kernel /path/to/u-boot.bin

+

+To test booting U-Boot SPL which in M-mode, which in turn loads a FIT image

+that bundles OpenSBI fw_dynamic firmware and U-Boot proper (S-mode) together,

+build the U-Boot images using riscv64_spl_defconfig:

+

+.. code-block:: bash

+

+ $ export CROSS_COMPILE=riscv64-linux-

+ $ export OPENSBI=/path/to/opensbi-riscv64-generic-fw_dynamic.bin

+ $ make qemu-riscv64_spl_defconfig

+

+The minimal QEMU commands to run U-Boot SPL are:

+

+.. code-block:: bash

+

+ $ qemu-system-riscv64 -M virt -smp 4 -m 2G \

+ -display none -serial stdio \

+ -bios /path/to/u-boot-spl \

+ -device loader,file=/path/to/u-boot.itb,addr=0x80200000

+

+To test 32-bit U-Boot images, switch to use qemu-riscv32_smode_defconfig and

+riscv32_spl_defconfig builds, and replace ``qemu-system-riscv64`` with

+``qemu-system-riscv32`` in the command lines above to boot the 32-bit U-Boot.

diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst

index XXXXXXX..XXXXXXX 100644

--- a/docs/system/target-riscv.rst

+++ b/docs/system/target-riscv.rst

@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running

riscv/microchip-icicle-kit

riscv/shakti-c

riscv/sifive_u

+ riscv/virt

RISC-V CPU firmware

-------------------

--

2.31.1

From: Bin Meng <bin.meng@windriver.com>

This adds a new section in the documentation to demonstrate how to

use the new direct kernel boot feature for Microchip Icicle Kit,

other than the HSS bootflow, using an upstream U-Boot v2021.07 image

as an example.

It also updates the truth table to have a new '-dtb' column which is

required by direct kernel boot.

Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Message-id: 20210706095045.1917913-1-bmeng.cn@gmail.com

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

---

docs/system/riscv/microchip-icicle-kit.rst | 54 +++++++++++++++++++---

1 file changed, 47 insertions(+), 7 deletions(-)

diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst

index XXXXXXX..XXXXXXX 100644

--- a/docs/system/riscv/microchip-icicle-kit.rst

+++ b/docs/system/riscv/microchip-icicle-kit.rst

@@ -XXX,XX +XXX,XX @@ The user provided DTB should have the following requirements:

QEMU follows below truth table to select which payload to execute:

-===== ========== =======

--bios -kernel payload

-===== ========== =======

- N N HSS

- Y don't care HSS

- N Y kernel

-===== ========== =======

+===== ========== ========== =======

+-bios -kernel -dtb payload

+===== ========== ========== =======

+ N N don't care HSS

+ Y don't care don't care HSS

+ N Y Y kernel

+===== ========== ========== =======

The memory is set to 1537 MiB by default which is the minimum required high

memory size by HSS. A sanity check on ram size is performed in the machine

@@ -XXX,XX +XXX,XX @@ HSS output is on the first serial port (stdio) and U-Boot outputs on the

second serial port. U-Boot will automatically load the Linux kernel from

the SD card image.

+Direct Kernel Boot

+------------------

+

+Sometimes we just want to test booting a new kernel, and transforming the

+kernel image to the format required by the HSS bootflow is tedious. We can

+use '-kernel' for direct kernel booting just like other RISC-V machines do.

+

+In this mode, the OpenSBI fw_dynamic BIOS image for 'generic' platform is

+used to boot an S-mode payload like U-Boot or OS kernel directly.

+

+For example, the following commands show building a U-Boot image from U-Boot

+mainline v2021.07 for the Microchip Icicle Kit board:

+

+.. code-block:: bash

+

+ $ export CROSS_COMPILE=riscv64-linux-

+ $ make microchip_mpfs_icicle_defconfig

+

+Then we can boot the machine by:

+

+.. code-block:: bash

+

+ $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 -m 2G \

+ -sd path/to/sdcard.img \

+ -nic user,model=cadence_gem \

+ -nic tap,ifname=tap,model=cadence_gem,script=no \

+ -display none -serial stdio \

+ -kernel path/to/u-boot/build/dir/u-boot.bin \

+ -dtb path/to/u-boot/build/dir/u-boot.dtb

+

+CAVEATS:

+

+* Check the "stdout-path" property in the /chosen node in the DTB to determine

+ which serial port is used for the serial console, e.g.: if the console is set

+ to the second serial port, change to use "-serial null -serial stdio".

+* The default U-Boot configuration uses CONFIG_OF_SEPARATE hence the ELF image

+ ``u-boot`` cannot be passed to "-kernel" as it does not contain the DTB hence

+ ``u-boot.bin`` has to be used which does contain one. To use the ELF image,

+ we need to change to CONFIG_OF_EMBED or CONFIG_OF_PRIOR_STAGE.

+

.. _HSS: https://github.com/polarfire-soc/hart-software-services

--

2.31.1

From: Bin Meng <bin.meng@windriver.com>

At present the CLINT timebase frequency is set to 10MHz on sifive_u,

but on the real hardware the timebase frequency is 1Mhz.

Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Message-id: 20210706102616.1922469-1-bmeng.cn@gmail.com

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

---

hw/riscv/sifive_u.c | 7 +++++--

1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/riscv/sifive_u.c

+++ b/hw/riscv/sifive_u.c

@@ -XXX,XX +XXX,XX @@

#include <libfdt.h>

+/* CLINT timebase frequency */

+#define CLINT_TIMEBASE_FREQ 1000000

+

static const MemMapEntry sifive_u_memmap[] = {

[SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },

[SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },

@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,

qemu_fdt_add_subnode(fdt, "/cpus");

qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",

- SIFIVE_CLINT_TIMEBASE_FREQ);

+ CLINT_TIMEBASE_FREQ);

qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);

qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);

@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)

sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base,

memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus,

SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,

- SIFIVE_CLINT_TIMEBASE_FREQ, false);

+ CLINT_TIMEBASE_FREQ, false);

if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {

return;

--

2.31.1

Update the register layout to match the latest OpenTitan bitstream.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Message-id: 25c8377d32f3e0f0a1a862c8a5092f8a9e3f9928.1625801868.git.alistair.francis@wdc.com

---

hw/char/ibex_uart.c | 19 ++++++++++---------

1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/char/ibex_uart.c

+++ b/hw/char/ibex_uart.c

@@ -XXX,XX +XXX,XX @@ REG32(INTR_STATE, 0x00)

FIELD(INTR_STATE, RX_OVERFLOW, 3, 1)

REG32(INTR_ENABLE, 0x04)

REG32(INTR_TEST, 0x08)

-REG32(CTRL, 0x0C)

+REG32(ALERT_TEST, 0x0C)

+REG32(CTRL, 0x10)

FIELD(CTRL, TX_ENABLE, 0, 1)

FIELD(CTRL, RX_ENABLE, 1, 1)

FIELD(CTRL, NF, 2, 1)

@@ -XXX,XX +XXX,XX @@ REG32(CTRL, 0x0C)

FIELD(CTRL, PARITY_ODD, 7, 1)

FIELD(CTRL, RXBLVL, 8, 2)

FIELD(CTRL, NCO, 16, 16)

-REG32(STATUS, 0x10)

+REG32(STATUS, 0x14)

FIELD(STATUS, TXFULL, 0, 1)

FIELD(STATUS, RXFULL, 1, 1)

FIELD(STATUS, TXEMPTY, 2, 1)

FIELD(STATUS, RXIDLE, 4, 1)

FIELD(STATUS, RXEMPTY, 5, 1)

-REG32(RDATA, 0x14)

-REG32(WDATA, 0x18)

-REG32(FIFO_CTRL, 0x1c)

+REG32(RDATA, 0x18)

+REG32(WDATA, 0x1C)

+REG32(FIFO_CTRL, 0x20)

FIELD(FIFO_CTRL, RXRST, 0, 1)

FIELD(FIFO_CTRL, TXRST, 1, 1)

FIELD(FIFO_CTRL, RXILVL, 2, 3)

FIELD(FIFO_CTRL, TXILVL, 5, 2)

-REG32(FIFO_STATUS, 0x20)

+REG32(FIFO_STATUS, 0x24)

FIELD(FIFO_STATUS, TXLVL, 0, 5)

FIELD(FIFO_STATUS, RXLVL, 16, 5)

-REG32(OVRD, 0x24)

-REG32(VAL, 0x28)

-REG32(TIMEOUT_CTRL, 0x2c)

+REG32(OVRD, 0x28)

+REG32(VAL, 0x2C)

+REG32(TIMEOUT_CTRL, 0x30)

static void ibex_uart_update_irqs(IbexUartState *s)

{

--

2.31.1

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Message-id: ed707782e84118e1b06a32fd79b70fecfb54ff82.1625801868.git.alistair.francis@wdc.com

---

include/hw/riscv/opentitan.h | 1 +

hw/riscv/opentitan.c | 3 +++

2 files changed, 4 insertions(+)

diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/riscv/opentitan.h

+++ b/include/hw/riscv/opentitan.h

@@ -XXX,XX +XXX,XX @@ enum {

IBEX_DEV_ALERT_HANDLER,

IBEX_DEV_NMI_GEN,

IBEX_DEV_OTBN,

+ IBEX_DEV_PERI,

};

enum {

diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/riscv/opentitan.c

+++ b/hw/riscv/opentitan.c

@@ -XXX,XX +XXX,XX @@ static const MemMapEntry ibex_memmap[] = {

[IBEX_DEV_ALERT_HANDLER] = { 0x411b0000, 0x1000 },

[IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 },

[IBEX_DEV_OTBN] = { 0x411d0000, 0x10000 },

+ [IBEX_DEV_PERI] = { 0x411f0000, 0x10000 },

};

static void opentitan_board_init(MachineState *machine)

@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)

memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);

create_unimplemented_device("riscv.lowrisc.ibex.otbn",

memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);

+ create_unimplemented_device("riscv.lowrisc.ibex.peri",

+ memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size);

}

static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)

--

2.31.1

OpenTitan has an alias of flash avaliable which is called virtual flash.

Add support for that in the QEMU model.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Message-id: c9cfbd2dd840fd0076877b8ea4d6dcfce60db5e9.1625801868.git.alistair.francis@wdc.com

---

include/hw/riscv/opentitan.h | 2 ++

hw/riscv/opentitan.c | 6 ++++++

2 files changed, 8 insertions(+)

diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/riscv/opentitan.h

+++ b/include/hw/riscv/opentitan.h

@@ -XXX,XX +XXX,XX @@ struct LowRISCIbexSoCState {

MemoryRegion flash_mem;

MemoryRegion rom;

+ MemoryRegion flash_alias;

};

typedef struct OpenTitanState {

@@ -XXX,XX +XXX,XX @@ enum {

IBEX_DEV_ROM,

IBEX_DEV_RAM,

IBEX_DEV_FLASH,

+ IBEX_DEV_FLASH_VIRTUAL,

IBEX_DEV_UART,

IBEX_DEV_GPIO,

IBEX_DEV_SPI,

diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/riscv/opentitan.c

+++ b/hw/riscv/opentitan.c

@@ -XXX,XX +XXX,XX @@ static const MemMapEntry ibex_memmap[] = {

[IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 },

[IBEX_DEV_OTBN] = { 0x411d0000, 0x10000 },

[IBEX_DEV_PERI] = { 0x411f0000, 0x10000 },

+ [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 },

};

static void opentitan_board_init(MachineState *machine)

@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)

/* Flash memory */

memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash",

memmap[IBEX_DEV_FLASH].size, &error_fatal);

+ memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),

+ "riscv.lowrisc.ibex.flash_virtual", &s->flash_mem, 0,

+ memmap[IBEX_DEV_FLASH_VIRTUAL].size);

memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base,

&s->flash_mem);

+ memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH_VIRTUAL].base,

+ &s->flash_alias);

/* PLIC */

if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {

--

2.31.1

Coverity reports that we don't check the error result of fdt_pack(), so

let's save the result and assert that it is 0.

Fixes: Coverity CID 1458136

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Message-id: 07325315b49d5555269f76094e4bc5296e0643b9.1626303527.git.alistair.francis@wdc.com

---

hw/riscv/boot.c | 6 ++++--

1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/riscv/boot.c

+++ b/hw/riscv/boot.c

@@ -XXX,XX +XXX,XX @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)

{

uint32_t temp, fdt_addr;

hwaddr dram_end = dram_base + mem_size;

- int fdtsize = fdt_totalsize(fdt);

+ int ret, fdtsize = fdt_totalsize(fdt);

if (fdtsize <= 0) {

error_report("invalid device-tree");

@@ -XXX,XX +XXX,XX @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)

temp = MIN(dram_end, 3072 * MiB);

fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB);

- fdt_pack(fdt);

+ ret = fdt_pack(fdt);

+ /* Should only fail if we've built a corrupted tree */

+ g_assert(ret == 0);

/* copy in the device tree */

qemu_fdt_dumpdtb(fdt, fdtsize);

--

2.31.1