[v2] riscv-to-apply queue

[PULL v2 00/12] riscv-to-apply queue

Alistair Francis posted 12 patches 2 years, 9 months ago

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Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Bin Meng <bin.meng@windriver.com>, Paolo Bonzini <pbonzini@redhat.com>, Alistair Francis <Alistair.Francis@wdc.com>, Alistair Francis <alistair.francis@wdc.com>, "Marc-André Lureau" <marcandre.lureau@redhat.com>

There is a newer version of this series

docs/system/riscv/microchip-icicle-kit.rst |  54 +++++++++--
docs/system/riscv/sifive_u.rst             |   2 +-
docs/system/riscv/virt.rst                 | 138 +++++++++++++++++++++++++++++
docs/system/target-riscv.rst               |   1 +
include/hw/riscv/opentitan.h               |   3 +
hw/char/ibex_uart.c                        |  19 ++--
hw/riscv/boot.c                            |   6 +-
hw/riscv/opentitan.c                       |   9 ++
hw/riscv/sifive_u.c                        |  12 ++-
target/riscv/csr.c                         |  78 +++++++---------
target/riscv/pmp.c                         |  10 +--
11 files changed, 257 insertions(+), 75 deletions(-)
create mode 100644 docs/system/riscv/virt.rst

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[PULL v2 00/12] riscv-to-apply queue

Posted by Alistair Francis 2 years, 9 months ago

The following changes since commit a9649a719a44894b81f38dc1c5c1888ee684acef:

  Merge remote-tracking branch 'remotes/cleber-gitlab/tags/python-next-pull-request' into staging (2021-07-14 18:09:09 +0100)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210715

for you to fetch changes up to b3d8aa20692b1baed299790f4a65d6b0cfb1a0bc:

  hw/riscv/boot: Check the error of fdt_pack() (2021-07-15 09:35:46 +1000)

----------------------------------------------------------------
Fourth RISC-V PR for 6.1 release

 - Code cleanups
 - Documentation improvements
 - Hypervisor extension improvements with hideleg and hedeleg
 - sifive_u fixes
 - OpenTitan register layout updates
 - Fix coverity issue

----------------------------------------------------------------
Alistair Francis (4):
      char: ibex_uart: Update the register layout
      hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
      hw/riscv: opentitan: Add the flash alias
      hw/riscv/boot: Check the error of fdt_pack()

Bin Meng (7):
      target/riscv: pmp: Fix some typos
      target/riscv: csr: Remove redundant check in fp csr read/write routines
      docs/system: riscv: Fix CLINT name in the sifive_u doc
      docs/system: riscv: Add documentation for virt machine
      docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot
      hw/riscv: sifive_u: Correct the CLINT timebase frequency
      hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned

Jose Martins (1):
      target/riscv: hardwire bits in hideleg and hedeleg

 docs/system/riscv/microchip-icicle-kit.rst |  54 +++++++++--
 docs/system/riscv/sifive_u.rst             |   2 +-
 docs/system/riscv/virt.rst                 | 138 +++++++++++++++++++++++++++++
 docs/system/target-riscv.rst               |   1 +
 include/hw/riscv/opentitan.h               |   3 +
 hw/char/ibex_uart.c                        |  19 ++--
 hw/riscv/boot.c                            |   6 +-
 hw/riscv/opentitan.c                       |   9 ++
 hw/riscv/sifive_u.c                        |  12 ++-
 target/riscv/csr.c                         |  78 +++++++---------
 target/riscv/pmp.c                         |  10 +--
 11 files changed, 257 insertions(+), 75 deletions(-)
 create mode 100644 docs/system/riscv/virt.rst

Re: [PULL v2 00/12] riscv-to-apply queue

Posted by Peter Maydell 2 years, 9 months ago

On Thu, 15 Jul 2021 at 08:16, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit a9649a719a44894b81f38dc1c5c1888ee684acef:
>
>   Merge remote-tracking branch 'remotes/cleber-gitlab/tags/python-next-pull-request' into staging (2021-07-14 18:09:09 +0100)
>
> are available in the Git repository at:
>
>   git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210715
>
> for you to fetch changes up to b3d8aa20692b1baed299790f4a65d6b0cfb1a0bc:
>
>   hw/riscv/boot: Check the error of fdt_pack() (2021-07-15 09:35:46 +1000)
>
> ----------------------------------------------------------------
> Fourth RISC-V PR for 6.1 release
>
>  - Code cleanups
>  - Documentation improvements
>  - Hypervisor extension improvements with hideleg and hedeleg
>  - sifive_u fixes
>  - OpenTitan register layout updates
>  - Fix coverity issue
>
> ----------------------------------------------------------------


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.1
for any user-visible changes.

-- PMM