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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=8230c157d=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626333509620100001 From: Bin Meng %s/CSP/CSR %s/thie/the Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-id: 20210627115716.3552-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis --- target/riscv/pmp.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 82ed020b10..54abf42583 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -456,7 +456,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulon= g addr, } =20 /* - * Handle a write to a pmpcfg CSP + * Handle a write to a pmpcfg CSR */ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, target_ulong val) @@ -483,7 +483,7 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_= index, =20 =20 /* - * Handle a read from a pmpcfg CSP + * Handle a read from a pmpcfg CSR */ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index) { @@ -502,7 +502,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32= _t reg_index) =20 =20 /* - * Handle a write to a pmpaddr CSP + * Handle a write to a pmpaddr CSR */ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, target_ulong val) @@ -540,7 +540,7 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t add= r_index, =20 =20 /* - * Handle a read from a pmpaddr CSP + * Handle a read from a pmpaddr CSR */ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index) { @@ -593,7 +593,7 @@ target_ulong mseccfg_csr_read(CPURISCVState *env) =20 /* * Calculate the TLB size if the start address or the end address of - * PMP entry is presented in thie TLB page. + * PMP entry is presented in the TLB page. */ static target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index, target_ulong tlb_sa, target_ulong tlb= _ea) --=20 2.31.1 From nobody Fri May 10 15:17:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=8230c157d=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626333661667100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng The following check: if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -RISCV_EXCP_ILLEGAL_INST; } is redundant in fflags/frm/fcsr read/write routines, as the check was already done in fs(). Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 20210627120604.11116-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis --- target/riscv/csr.c | 24 ------------------------ 1 file changed, 24 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index fe5628fea6..62b968326c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -215,11 +215,6 @@ static RISCVException epmp(CPURISCVState *env, int csr= no) static RISCVException read_fflags(CPURISCVState *env, int csrno, target_ulong *val) { -#if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return RISCV_EXCP_ILLEGAL_INST; - } -#endif *val =3D riscv_cpu_get_fflags(env); return RISCV_EXCP_NONE; } @@ -228,9 +223,6 @@ static RISCVException write_fflags(CPURISCVState *env, = int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return RISCV_EXCP_ILLEGAL_INST; - } env->mstatus |=3D MSTATUS_FS; #endif riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); @@ -240,11 +232,6 @@ static RISCVException write_fflags(CPURISCVState *env,= int csrno, static RISCVException read_frm(CPURISCVState *env, int csrno, target_ulong *val) { -#if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return RISCV_EXCP_ILLEGAL_INST; - } -#endif *val =3D env->frm; return RISCV_EXCP_NONE; } @@ -253,9 +240,6 @@ static RISCVException write_frm(CPURISCVState *env, int= csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return RISCV_EXCP_ILLEGAL_INST; - } env->mstatus |=3D MSTATUS_FS; #endif env->frm =3D val & (FSR_RD >> FSR_RD_SHIFT); @@ -265,11 +249,6 @@ static RISCVException write_frm(CPURISCVState *env, in= t csrno, static RISCVException read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) { -#if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return RISCV_EXCP_ILLEGAL_INST; - } -#endif *val =3D (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) | (env->frm << FSR_RD_SHIFT); if (vs(env, csrno) >=3D 0) { @@ -283,9 +262,6 @@ static RISCVException write_fcsr(CPURISCVState *env, in= t csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return RISCV_EXCP_ILLEGAL_INST; - } env->mstatus |=3D MSTATUS_FS; #endif env->frm =3D (val & FSR_RD) >> FSR_RD_SHIFT; --=20 2.31.1 From nobody Fri May 10 15:17:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626333562445276.27203981717935; Thu, 15 Jul 2021 00:19:22 -0700 (PDT) Received: from localhost ([::1]:39846 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m3veT-00011n-Eu for importer@patchew.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=8230c157d=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626333564165100003 Content-Type: text/plain; charset="utf-8" From: Bin Meng It's Core *Local* Interruptor, not 'Level'. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 20210627142816.19789-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis --- docs/system/riscv/sifive_u.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst index 32d0a1b85d..01108b5ecc 100644 --- a/docs/system/riscv/sifive_u.rst +++ b/docs/system/riscv/sifive_u.rst @@ -11,7 +11,7 @@ The ``sifive_u`` machine supports the following devices: =20 * 1 E51 / E31 core * Up to 4 U54 / U34 cores -* Core Level Interruptor (CLINT) +* Core Local Interruptor (CLINT) * Platform-Level Interrupt Controller (PLIC) * Power, Reset, Clock, Interrupt (PRCI) * L2 Loosely Integrated Memory (L2-LIM) --=20 2.31.1 From nobody Fri May 10 15:17:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="175212302" IronPort-SDR: svbN7orJF4HbR39YqBZw5A+A5dNUDOJoqKf41HQxFV+WPTeXn/tZVvoUjPTzqqGrk903HoxMPU lVGtiVKIKE/5vD75SbgeUfbabhhJZoYWEy0xLs0ty6MHeA7g3EHanSPz1hbRyB3JPCRcZWeyg5 jhdqi6iaYGWzVk8G6yF+2HogNqAw7C736h3hc5FNKG98tVX8ZQiwQvRUz0AWQdEkGNwNcRIF7U TVpQBfvMYW38X7bTg73xMXPT9NjyDTrpN6VFK+wRjAod0pICWvpZGEfSflSxq8RHOx9NKxcndU t36qSKgqt03D15HLnBN6gEp2 IronPort-SDR: qIVEPipJPogY0mv0/GyFA9mKTKBuId0CFQ1sqtH3V3BrpAjGcv7o30s0pKZDiyLCm51n55Rqlj hGas9UjFNiapulRY6dkZsI5r+vD5h1V/i62uXGRWXbkNe7AopAV/+JC2Ma+lNHSnNOGkmOkeuF rL13dBhc21zcC9Deu3sqDCLDLnXs9Xeo0gfZKHhMzVd9Cya/fGxNKQs0lPNNIHvC547uCZyH5f DPjwSu6OxiFS6X02t3H5v+KrqG1q5KpgRI2NgtO4BDyAu2y1kTwzB/KN0/dvTJlAEUP033K0dd 0eU= WDCIronportException: Internal From: Alistair Francis To: peter.maydell@linaro.org, qemu-devel@nongnu.org Subject: [PULL v2 04/12] docs/system: riscv: Add documentation for virt machine Date: Thu, 15 Jul 2021 00:16:32 -0700 Message-Id: <20210715071640.232070-5-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210715071640.232070-1-alistair.francis@wdc.com> References: <20210715071640.232070-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=8230c157d=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626333659488100001 From: Bin Meng This adds detailed documentation for RISC-V `virt` machine, including the following information: - Supported devices - Hardware configuration information - Boot options - Running Linux kernel - Running U-Boot Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 20210627142816.19789-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis --- docs/system/riscv/virt.rst | 138 +++++++++++++++++++++++++++++++++++ docs/system/target-riscv.rst | 1 + 2 files changed, 139 insertions(+) create mode 100644 docs/system/riscv/virt.rst diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst new file mode 100644 index 0000000000..3709f05797 --- /dev/null +++ b/docs/system/riscv/virt.rst @@ -0,0 +1,138 @@ +'virt' Generic Virtual Platform (``virt``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The `virt` board is a platform which does not correspond to any real hardw= are; +it is designed for use in virtual machines. It is the recommended board ty= pe +if you simply want to run a guest such as Linux and do not care about +reproducing the idiosyncrasies and limitations of a particular bit of +real-world hardware. + +Supported devices +----------------- + +The ``virt`` machine supports the following devices: + +* Up to 8 generic RV32GC/RV64GC cores, with optional extensions +* Core Local Interruptor (CLINT) +* Platform-Level Interrupt Controller (PLIC) +* CFI parallel NOR flash memory +* 1 NS16550 compatible UART +* 1 Google Goldfish RTC +* 1 SiFive Test device +* 8 virtio-mmio transport devices +* 1 generic PCIe host bridge +* The fw_cfg device that allows a guest to obtain data from QEMU + +Note that the default CPU is a generic RV32GC/RV64GC. Optional extensions +can be enabled via command line parameters, e.g.: ``-cpu rv64,x-h=3Dtrue`` +enables the hypervisor extension for RV64. + +Hardware configuration information +---------------------------------- + +The ``virt`` machine automatically generates a device tree blob ("dtb") +which it passes to the guest, if there is no ``-dtb`` option. This provides +information about the addresses, interrupt lines and other configuration of +the various devices in the system. Guest software should discover the devi= ces +that are present in the generated DTB. + +If users want to provide their own DTB, they can use the ``-dtb`` option. +These DTBs should have the following requirements: + +* The number of subnodes of the /cpus node should match QEMU's ``-smp`` op= tion +* The /memory reg size should match QEMU=E2=80=99s selected ram_size via `= `-m`` +* Should contain a node for the CLINT device with a compatible string + "riscv,clint0" if using with OpenSBI BIOS images + +Boot options +------------ + +The ``virt`` machine can start using the standard -kernel functionality +for loading a Linux kernel, a VxWorks kernel, an S-mode U-Boot bootloader +with the default OpenSBI firmware image as the -bios. It also supports +the recommended RISC-V bootflow: U-Boot SPL (M-mode) loads OpenSBI fw_dyna= mic +firmware and U-Boot proper (S-mode), using the standard -bios functionalit= y. + +Running Linux kernel +-------------------- + +Linux mainline v5.12 release is tested at the time of writing. To build a +Linux mainline kernel that can be booted by the ``virt`` machine in +64-bit mode, simply configure the kernel using the defconfig configuration: + +.. code-block:: bash + + $ export ARCH=3Driscv + $ export CROSS_COMPILE=3Driscv64-linux- + $ make defconfig + $ make + +To boot the newly built Linux kernel in QEMU with the ``virt`` machine: + +.. code-block:: bash + + $ qemu-system-riscv64 -M virt -smp 4 -m 2G \ + -display none -serial stdio \ + -kernel arch/riscv/boot/Image \ + -initrd /path/to/rootfs.cpio \ + -append "root=3D/dev/ram" + +To build a Linux mainline kernel that can be booted by the ``virt`` machine +in 32-bit mode, use the rv32_defconfig configuration. A patch is required = to +fix the 32-bit boot issue for Linux kernel v5.12. + +.. code-block:: bash + + $ export ARCH=3Driscv + $ export CROSS_COMPILE=3Driscv64-linux- + $ curl https://patchwork.kernel.org/project/linux-riscv/patch/2021062713= 5117.28641-1-bmeng.cn@gmail.com/mbox/ > riscv.patch + $ git am riscv.patch + $ make rv32_defconfig + $ make + +Replace ``qemu-system-riscv64`` with ``qemu-system-riscv32`` in the command +line above to boot the 32-bit Linux kernel. A rootfs image containing 32-b= it +applications shall be used in order for kernel to boot to user space. + +Running U-Boot +-------------- + +U-Boot mainline v2021.04 release is tested at the time of writing. To buil= d an +S-mode U-Boot bootloader that can be booted by the ``virt`` machine, use +the qemu-riscv64_smode_defconfig with similar commands as described above = for Linux: + +.. code-block:: bash + + $ export CROSS_COMPILE=3Driscv64-linux- + $ make qemu-riscv64_smode_defconfig + +Boot the 64-bit U-Boot S-mode image directly: + +.. code-block:: bash + + $ qemu-system-riscv64 -M virt -smp 4 -m 2G \ + -display none -serial stdio \ + -kernel /path/to/u-boot.bin + +To test booting U-Boot SPL which in M-mode, which in turn loads a FIT image +that bundles OpenSBI fw_dynamic firmware and U-Boot proper (S-mode) togeth= er, +build the U-Boot images using riscv64_spl_defconfig: + +.. code-block:: bash + + $ export CROSS_COMPILE=3Driscv64-linux- + $ export OPENSBI=3D/path/to/opensbi-riscv64-generic-fw_dynamic.bin + $ make qemu-riscv64_spl_defconfig + +The minimal QEMU commands to run U-Boot SPL are: + +.. code-block:: bash + + $ qemu-system-riscv64 -M virt -smp 4 -m 2G \ + -display none -serial stdio \ + -bios /path/to/u-boot-spl \ + -device loader,file=3D/path/to/u-boot.itb,addr=3D0x80200000 + +To test 32-bit U-Boot images, switch to use qemu-riscv32_smode_defconfig a= nd +riscv32_spl_defconfig builds, and replace ``qemu-system-riscv64`` with +``qemu-system-riscv32`` in the command lines above to boot the 32-bit U-Bo= ot. diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst index a5cc06b726..89a866e4f4 100644 --- a/docs/system/target-riscv.rst +++ b/docs/system/target-riscv.rst @@ -69,6 +69,7 @@ undocumented; you can get a complete list by running riscv/microchip-icicle-kit riscv/shakti-c riscv/sifive_u + riscv/virt =20 RISC-V CPU firmware ------------------- --=20 2.31.1 From nobody Fri May 10 15:17:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626333699561728.539000448291; Thu, 15 Jul 2021 00:21:39 -0700 (PDT) Received: from localhost ([::1]:46178 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m3vgg-0006cn-IB for importer@patchew.org; Thu, 15 Jul 2021 03:21:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34064) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m3vc4-0005Uf-MA for qemu-devel@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=8230c157d=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jose Martins , Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626333701257100001 Content-Type: text/plain; charset="utf-8" From: Jose Martins The specification mandates for certain bits to be hardwired in the hypervisor delegation registers. This was not being enforced. Signed-off-by: Jose Martins Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-id: 20210522155902.374439-1-josemartins90@gmail.com [ Changes by AF: - Improve indentation - Convert delegable_excps to a #define to avoid failures with GCC 8 ] Signed-off-by: Alistair Francis --- target/riscv/csr.c | 54 ++++++++++++++++++++++++++-------------------- 1 file changed, 31 insertions(+), 23 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 62b968326c..9a4ed18ac5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -411,28 +411,36 @@ static RISCVException read_timeh(CPURISCVState *env, = int csrno, =20 static const target_ulong delegable_ints =3D S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS; +static const target_ulong vs_delegable_ints =3D VS_MODE_INTERRUPTS; static const target_ulong all_ints =3D M_MODE_INTERRUPTS | S_MODE_INTERRUP= TS | VS_MODE_INTERRUPTS; -static const target_ulong delegable_excps =3D - (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | - (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | - (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | - (1ULL << (RISCV_EXCP_BREAKPOINT)) | - (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | - (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | - (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | - (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | - (1ULL << (RISCV_EXCP_U_ECALL)) | - (1ULL << (RISCV_EXCP_S_ECALL)) | - (1ULL << (RISCV_EXCP_VS_ECALL)) | - (1ULL << (RISCV_EXCP_M_ECALL)) | - (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | - (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | - (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | - (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | - (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | - (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | - (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); +#define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ + (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ + (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ + (1ULL << (RISCV_EXCP_BREAKPOINT)) | \ + (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \ + (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \ + (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \ + (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \ + (1ULL << (RISCV_EXCP_U_ECALL)) | \ + (1ULL << (RISCV_EXCP_S_ECALL)) | \ + (1ULL << (RISCV_EXCP_VS_ECALL)) | \ + (1ULL << (RISCV_EXCP_M_ECALL)) | \ + (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ + (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ + (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ + (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \ + (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \ + (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \ + (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT= ))) +static const target_ulong vs_delegable_excps =3D DELEGABLE_EXCPS & + ~((1ULL << (RISCV_EXCP_S_ECALL)) | + (1ULL << (RISCV_EXCP_VS_ECALL)) | + (1ULL << (RISCV_EXCP_M_ECALL)) | + (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | + (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | + (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | + (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); static const target_ulong sstatus_v1_10_mask =3D SSTATUS_SIE | SSTATUS_SPI= E | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR; @@ -620,7 +628,7 @@ static RISCVException read_medeleg(CPURISCVState *env, = int csrno, static RISCVException write_medeleg(CPURISCVState *env, int csrno, target_ulong val) { - env->medeleg =3D (env->medeleg & ~delegable_excps) | (val & delegable_= excps); + env->medeleg =3D (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_= EXCPS); return RISCV_EXCP_NONE; } =20 @@ -1039,7 +1047,7 @@ static RISCVException read_hedeleg(CPURISCVState *env= , int csrno, static RISCVException write_hedeleg(CPURISCVState *env, int csrno, target_ulong val) { - env->hedeleg =3D val; + env->hedeleg =3D val & vs_delegable_excps; return RISCV_EXCP_NONE; } =20 @@ -1053,7 +1061,7 @@ static RISCVException read_hideleg(CPURISCVState *env= , int csrno, static RISCVException write_hideleg(CPURISCVState *env, int csrno, target_ulong val) { - env->hideleg =3D val; + env->hideleg =3D val & vs_delegable_ints; return RISCV_EXCP_NONE; } =20 --=20 2.31.1 From nobody Fri May 10 15:17:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626333762610120.19071472059318; Thu, 15 Jul 2021 00:22:42 -0700 (PDT) Received: from localhost ([::1]:50452 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m3vhh-00013u-Fn for importer@patchew.org; Thu, 15 Jul 2021 03:22:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34094) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m3vc6-0005Yg-MC for qemu-devel@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=8230c157d=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626333763264100002 Content-Type: text/plain; charset="utf-8" From: Bin Meng This adds a new section in the documentation to demonstrate how to use the new direct kernel boot feature for Microchip Icicle Kit, other than the HSS bootflow, using an upstream U-Boot v2021.07 image as an example. It also updates the truth table to have a new '-dtb' column which is required by direct kernel boot. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 20210706095045.1917913-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis --- docs/system/riscv/microchip-icicle-kit.rst | 54 +++++++++++++++++++--- 1 file changed, 47 insertions(+), 7 deletions(-) diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv= /microchip-icicle-kit.rst index 54ced661e3..817d2aec9c 100644 --- a/docs/system/riscv/microchip-icicle-kit.rst +++ b/docs/system/riscv/microchip-icicle-kit.rst @@ -47,13 +47,13 @@ The user provided DTB should have the following require= ments: =20 QEMU follows below truth table to select which payload to execute: =20 -=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D --bios -kernel payload -=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D - N N HSS - Y don't care HSS - N Y kernel -=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D =3D=3D=3D=3D=3D=3D=3D +-bios -kernel -dtb payload +=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D =3D=3D=3D=3D=3D=3D=3D + N N don't care HSS + Y don't care don't care HSS + N Y Y kernel +=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D =3D=3D=3D=3D=3D=3D=3D =20 The memory is set to 1537 MiB by default which is the minimum required high memory size by HSS. A sanity check on ram size is performed in the machine @@ -106,4 +106,44 @@ HSS output is on the first serial port (stdio) and U-B= oot outputs on the second serial port. U-Boot will automatically load the Linux kernel from the SD card image. =20 +Direct Kernel Boot +------------------ + +Sometimes we just want to test booting a new kernel, and transforming the +kernel image to the format required by the HSS bootflow is tedious. We can +use '-kernel' for direct kernel booting just like other RISC-V machines do. + +In this mode, the OpenSBI fw_dynamic BIOS image for 'generic' platform is +used to boot an S-mode payload like U-Boot or OS kernel directly. + +For example, the following commands show building a U-Boot image from U-Bo= ot +mainline v2021.07 for the Microchip Icicle Kit board: + +.. code-block:: bash + + $ export CROSS_COMPILE=3Driscv64-linux- + $ make microchip_mpfs_icicle_defconfig + +Then we can boot the machine by: + +.. code-block:: bash + + $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 -m 2G \ + -sd path/to/sdcard.img \ + -nic user,model=3Dcadence_gem \ + -nic tap,ifname=3Dtap,model=3Dcadence_gem,script=3Dno \ + -display none -serial stdio \ + -kernel path/to/u-boot/build/dir/u-boot.bin \ + -dtb path/to/u-boot/build/dir/u-boot.dtb + +CAVEATS: + +* Check the "stdout-path" property in the /chosen node in the DTB to deter= mine + which serial port is used for the serial console, e.g.: if the console i= s set + to the second serial port, change to use "-serial null -serial stdio". +* The default U-Boot configuration uses CONFIG_OF_SEPARATE hence the ELF i= mage + ``u-boot`` cannot be passed to "-kernel" as it does not contain the DTB = hence + ``u-boot.bin`` has to be used which does contain one. To use the ELF ima= ge, + we need to change to CONFIG_OF_EMBED or CONFIG_OF_PRIOR_STAGE. + .. _HSS: https://github.com/polarfire-soc/hart-software-services --=20 2.31.1 From nobody Fri May 10 15:17:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626333800460487.79526417790896; Thu, 15 Jul 2021 00:23:20 -0700 (PDT) Received: from localhost ([::1]:52620 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m3viJ-0002WG-D2 for importer@patchew.org; Thu, 15 Jul 2021 03:23:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34106) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m3vc7-0005cg-PF for qemu-devel@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=8230c157d=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626333801630100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng At present the CLINT timebase frequency is set to 10MHz on sifive_u, but on the real hardware the timebase frequency is 1Mhz. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 20210706102616.1922469-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 273c86418c..e75ca38783 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -62,6 +62,9 @@ =20 #include =20 +/* CLINT timebase frequency */ +#define CLINT_TIMEBASE_FREQ 1000000 + static const MemMapEntry sifive_u_memmap[] =3D { [SIFIVE_U_DEV_DEBUG] =3D { 0x0, 0x100 }, [SIFIVE_U_DEV_MROM] =3D { 0x1000, 0xf000 }, @@ -165,7 +168,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEnt= ry *memmap, =20 qemu_fdt_add_subnode(fdt, "/cpus"); qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", - SIFIVE_CLINT_TIMEBASE_FREQ); + CLINT_TIMEBASE_FREQ); qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); =20 @@ -847,7 +850,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Erro= r **errp) sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base, memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, - SIFIVE_CLINT_TIMEBASE_FREQ, false); + CLINT_TIMEBASE_FREQ, false); =20 if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { return; --=20 2.31.1 From nobody Fri May 10 15:17:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626333761016654.0152898486219; Thu, 15 Jul 2021 00:22:41 -0700 (PDT) Received: from localhost ([::1]:50328 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m3vhf-0000yp-Pd for importer@patchew.org; Thu, 15 Jul 2021 03:22:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34096) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m3vc6-0005Yp-RE for qemu-devel@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=8230c157d=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626333763234100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng Currently the firmware dynamic info (fw_dyn) is put right after the reset vector, which is not 8-byte aligned on RV64. OpenSBI fw_dynamic uses ld to read contents from 'struct fw_dynamic_info', which expects fw_dyn to be on the 8-byte boundary, otherwise the misaligned load exception may happen. Fortunately this does not cause any issue on QEMU, as QEMU does support misaligned load. RV32 does not have any issue as it is 4-byte aligned already. Change to make sure it is 8-byte aligned which works for both RV32 and RV64. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 20210708143319.10441-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index e75ca38783..87bbd10b21 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -602,10 +602,10 @@ static void sifive_u_machine_init(MachineState *machi= ne) } =20 /* reset vector */ - uint32_t reset_vec[11] =3D { + uint32_t reset_vec[12] =3D { s->msel, /* MSEL pin state */ 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn)= */ - 0x02828613, /* addi a2, t0, %pcrel_lo(1b)= */ + 0x02c28613, /* addi a2, t0, %pcrel_lo(1b)= */ 0xf1402573, /* csrr a0, mhartid */ 0, 0, @@ -613,6 +613,7 @@ static void sifive_u_machine_init(MachineState *machine) start_addr, /* start: .dword */ start_addr_hi32, fdt_load_addr, /* fdt_laddr: .dword */ + 0x00000000, 0x00000000, /* fw_dyn: */ }; --=20 2.31.1 From nobody Fri May 10 15:17:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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IronPort-SDR: CJTvfja9RDngXwzGAuQeE74fA1nSxYDIya/tLWU/iCwQX2gydAd0WaEyEjWT4dzuozYYwxxGPf ZUv0Km4Eh+95gKr+hqE1VAIEgwAdGXdYt8YHrNvwiHQYJNbdir8iD69FC6dfI4Z+Vw4oUyhj9Y RCZGzawqoyRFrXuycx9mSbMKiBVB1/UdEzNm18Pjapa9qq8Glr3wpQOfC5XKDDtDCsYoK7YDWP BIy4xK3+luQnNG+sXzoToWx/oyYu1KVJENtGgoMwAI8dGOZB3fs2te90BNFs7qT9IXLH4FP6Af LsM= X-IronPort-AV: E=Sophos;i="5.84,240,1620662400"; d="scan'208";a="175212308" IronPort-SDR: AAM6WS6RzclTvrP2WSxBbT8btOBxPOVDYOHav9xcnqQTjglobbsDsByDg+3RekLDP4G2ygTNPB CuXw2n67VcQ0QTVQgiEbT8KBEQ9c50v7vA03JOTl4xCR58KyPqHDJd4hNN3+mzjA94/nzothE/ EfpwKjsYcjqKH4hniuqvXsNhUZBK5+bf36Zp3XOlqsLFlObY+ErDaO6dtjjCX7m1hMkbsaTewL vmZAAcb6MkfZiqrLx+3nSrNaBg92Z3bwMJQ3xvMgOE23jW/9e2Eg+xyUgPuC8UC/7c4gKol43V G8XLl9L+WYOwxS0oF5GyD2aA IronPort-SDR: NieMzRvDLvF1DHEnLBzmtGP94icsQ9gkIPo7dicrgN7ZRrsfG9luoN1Xh4qdku2fu6nvGh+QK6 9ZG7YyATJzBPAfHiA6icwoyQl5nHHzpMrF8OBroVA0CBR0IDucsLifLKddMjvkSK1rjcVo50P9 nF0B7FW0Fmh5b8A0PBB3UZZlyPPPyuD+QQjf+aAarqUklq60snM8k16IMvaPVwW7o3JM6WJhKz ZAKbz6I65clZmTAEyPqNGkpz8vaGvt8RUlQNT6TIgtqB760AKdye0RsQKtK4IuXd+qmBBrjGGk JRg= WDCIronportException: Internal From: Alistair Francis To: peter.maydell@linaro.org, qemu-devel@nongnu.org Subject: [PULL v2 09/12] char: ibex_uart: Update the register layout Date: Thu, 15 Jul 2021 00:16:37 -0700 Message-Id: <20210715071640.232070-10-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210715071640.232070-1-alistair.francis@wdc.com> References: <20210715071640.232070-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=8230c157d=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626333913848100002 Content-Type: text/plain; charset="utf-8" Update the register layout to match the latest OpenTitan bitstream. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 25c8377d32f3e0f0a1a862c8a5092f8a9e3f9928.1625801868.git.alistai= r.francis@wdc.com --- hw/char/ibex_uart.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c index fe4b6c3c9e..6b0c9330bf 100644 --- a/hw/char/ibex_uart.c +++ b/hw/char/ibex_uart.c @@ -42,7 +42,8 @@ REG32(INTR_STATE, 0x00) FIELD(INTR_STATE, RX_OVERFLOW, 3, 1) REG32(INTR_ENABLE, 0x04) REG32(INTR_TEST, 0x08) -REG32(CTRL, 0x0C) +REG32(ALERT_TEST, 0x0C) +REG32(CTRL, 0x10) FIELD(CTRL, TX_ENABLE, 0, 1) FIELD(CTRL, RX_ENABLE, 1, 1) FIELD(CTRL, NF, 2, 1) @@ -52,25 +53,25 @@ REG32(CTRL, 0x0C) FIELD(CTRL, PARITY_ODD, 7, 1) FIELD(CTRL, RXBLVL, 8, 2) FIELD(CTRL, NCO, 16, 16) -REG32(STATUS, 0x10) +REG32(STATUS, 0x14) FIELD(STATUS, TXFULL, 0, 1) FIELD(STATUS, RXFULL, 1, 1) FIELD(STATUS, TXEMPTY, 2, 1) FIELD(STATUS, RXIDLE, 4, 1) FIELD(STATUS, RXEMPTY, 5, 1) -REG32(RDATA, 0x14) -REG32(WDATA, 0x18) -REG32(FIFO_CTRL, 0x1c) +REG32(RDATA, 0x18) +REG32(WDATA, 0x1C) +REG32(FIFO_CTRL, 0x20) FIELD(FIFO_CTRL, RXRST, 0, 1) FIELD(FIFO_CTRL, TXRST, 1, 1) FIELD(FIFO_CTRL, RXILVL, 2, 3) FIELD(FIFO_CTRL, TXILVL, 5, 2) -REG32(FIFO_STATUS, 0x20) +REG32(FIFO_STATUS, 0x24) FIELD(FIFO_STATUS, TXLVL, 0, 5) FIELD(FIFO_STATUS, RXLVL, 16, 5) -REG32(OVRD, 0x24) -REG32(VAL, 0x28) -REG32(TIMEOUT_CTRL, 0x2c) +REG32(OVRD, 0x28) +REG32(VAL, 0x2C) +REG32(TIMEOUT_CTRL, 0x30) =20 static void ibex_uart_update_irqs(IbexUartState *s) { --=20 2.31.1 From nobody Fri May 10 15:17:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=8230c157d=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626334009970100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: ed707782e84118e1b06a32fd79b70fecfb54ff82.1625801868.git.alistai= r.francis@wdc.com --- include/hw/riscv/opentitan.h | 1 + hw/riscv/opentitan.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index 86cceef698..a488f5e8ec 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -81,6 +81,7 @@ enum { IBEX_DEV_ALERT_HANDLER, IBEX_DEV_NMI_GEN, IBEX_DEV_OTBN, + IBEX_DEV_PERI, }; =20 enum { diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index c5a7e3bacb..933c211b11 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -58,6 +58,7 @@ static const MemMapEntry ibex_memmap[] =3D { [IBEX_DEV_ALERT_HANDLER] =3D { 0x411b0000, 0x1000 }, [IBEX_DEV_NMI_GEN] =3D { 0x411c0000, 0x1000 }, [IBEX_DEV_OTBN] =3D { 0x411d0000, 0x10000 }, + [IBEX_DEV_PERI] =3D { 0x411f0000, 0x10000 }, }; =20 static void opentitan_board_init(MachineState *machine) @@ -217,6 +218,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_s= oc, Error **errp) memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size); create_unimplemented_device("riscv.lowrisc.ibex.otbn", memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size); + create_unimplemented_device("riscv.lowrisc.ibex.peri", + memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size); } =20 static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data) --=20 2.31.1 From nobody Fri May 10 15:17:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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IronPort-SDR: j/1IhWNL7x5PLKIlmEXvJrbxF1LvtkTq0RQisSmDjdi5mErB3HoFHtivlCKh9I1YsCSSh76mdN JhGv3rWkwZj7+mUO2B9nEK0bKUXtUeNCfcRMfc5b5K46aYDZij6D/vJ7xr1XnEcMtER90jr5+A I9LrRQrkI6t8kTA8gZLxR4Y2rHfH7wvfJV/WXkFUvj9qLEFxjAKMUdAMwH+KTeH8OjZHt7ns6+ +ebsDv9uaGIMyAgO6KaosqDLOfBvt0rP1BMA2X9UZE6rOd3cS9rQ/930sxj49c/Ne/R6D1i4Pb uiY= X-IronPort-AV: E=Sophos;i="5.84,240,1620662400"; d="scan'208";a="175212310" IronPort-SDR: iyXw9OEgwdS+ZB4x6ltQA6eBK0idLDoN1GbsxogxB1MYRYG0KgoFU8z2CT3+tWIa/KDFaLF+4w 4Qscx4lOi0ji6gR1ci7fZCuatHjPAjVlIn86BNG1sssikSj1poVzikofaWjMeOtLwlRGjYPkIW S2o+SIgiBW5SWJDpsJLMimVuB0+NS9y6oOftAkuXudnDLJgCEEt57cNG1xkosFdlw7JVBoFJnG ypAO74BnWkqD2Y63ZBUW2p13ThlZ2WK9bkH4A6u/0Mu+d/tj3HMTe7jY9AjfyibntKmjc0hLZR 3NNC3oSq4typPerwh7l0p8at IronPort-SDR: ySomnvEeJZ4ZjTyLSzIIvMFdZing+h0DOLNFDlus0Q06GpLHiAxAzv7eSNeh/JLkY3AsmT3pVO +VKkwjdIBrd/t5GKxO5sEYRIfR2ogoAfkEB0NYOgkES4eBGq6Hmdnbe8VXAMquQOpL5BJriEbf SFIItMJYcG37F7M+6QNgh/OfI+HckbybPY5TULN6WXz41qSgkmgtZeEubejuuJGp04gTKssl+n W3ClvMRNxn8AVszR5WFzg60WhyU+DDQJrRc5Kew7xR7Xqf/upu83ojv6L7U15I9AWieT6wR+Sq 2O4= WDCIronportException: Internal From: Alistair Francis To: peter.maydell@linaro.org, qemu-devel@nongnu.org Subject: [PULL v2 11/12] hw/riscv: opentitan: Add the flash alias Date: Thu, 15 Jul 2021 00:16:39 -0700 Message-Id: <20210715071640.232070-12-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210715071640.232070-1-alistair.francis@wdc.com> References: <20210715071640.232070-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=8230c157d=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626333963148100001 Content-Type: text/plain; charset="utf-8" OpenTitan has an alias of flash avaliable which is called virtual flash. Add support for that in the QEMU model. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: c9cfbd2dd840fd0076877b8ea4d6dcfce60db5e9.1625801868.git.alistai= r.francis@wdc.com --- include/hw/riscv/opentitan.h | 2 ++ hw/riscv/opentitan.c | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index a488f5e8ec..9f93bebdac 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -40,6 +40,7 @@ struct LowRISCIbexSoCState { =20 MemoryRegion flash_mem; MemoryRegion rom; + MemoryRegion flash_alias; }; =20 typedef struct OpenTitanState { @@ -54,6 +55,7 @@ enum { IBEX_DEV_ROM, IBEX_DEV_RAM, IBEX_DEV_FLASH, + IBEX_DEV_FLASH_VIRTUAL, IBEX_DEV_UART, IBEX_DEV_GPIO, IBEX_DEV_SPI, diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 933c211b11..36a41c8b5b 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -59,6 +59,7 @@ static const MemMapEntry ibex_memmap[] =3D { [IBEX_DEV_NMI_GEN] =3D { 0x411c0000, 0x1000 }, [IBEX_DEV_OTBN] =3D { 0x411d0000, 0x10000 }, [IBEX_DEV_PERI] =3D { 0x411f0000, 0x10000 }, + [IBEX_DEV_FLASH_VIRTUAL] =3D { 0x80000000, 0x80000 }, }; =20 static void opentitan_board_init(MachineState *machine) @@ -134,8 +135,13 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_= soc, Error **errp) /* Flash memory */ memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.= ibex.flash", memmap[IBEX_DEV_FLASH].size, &error_fatal); + memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc), + "riscv.lowrisc.ibex.flash_virtual", &s->flash= _mem, 0, + memmap[IBEX_DEV_FLASH_VIRTUAL].size); memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base, &s->flash_mem); + memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH_VIRTUAL].ba= se, + &s->flash_alias); =20 /* PLIC */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) { --=20 2.31.1 From nobody Fri May 10 15:17:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="175212311" IronPort-SDR: NklwrFWerG3SjhPaW0Tdm9B+5ssc4zWD9JZ+EdDS6PdT3v+LLhe+uQofwiJx87rqKVrWjdr/U0 MvMZzEFgg3+f4eI1LTgm8aSgYJJWksU30z9LO3TiCy0eJz5RMcC6PLGvXpTpSdyN50Tt2Gu6Ay pPXyE3yA2pMvoFWAmszMUCcdGxYlwPqE+cDhYcJzHALn7a4Pw/N5iGCmLFEn66dwx+FzQGBqCO BAWT2QJYepFs8eBLERMB0YbojK9Z4fKqlLywELUbdfysNPbTGZghutvUCPeDRV/uJF2v6kGkho qwjVasshwVViLn/mBpxtoZLR IronPort-SDR: jW56WcnafIJqpSvVjxtpIUvERU9SEar+a14wre2PFr7xqlw7olta8twcZ+FVjhMXpwrHfeSGfo UPlv9Gjz4uw86cmCclGdrvfvZkzbnvHB1SE+CS3MrGcTzf4uKgMD0hO8eIxg1UfwI5VLNt/Qyq rShM6f3bLlWLEvhid9auExZaC5dLCT/wn4jwCm+XutN67OqODaOnv3J7Em4M8KUA1Dz9NyNtFx wswV9rw3+p68MzewRG5mvfW97UTphWUU7wQs83qQB9ICqwt0nF5YxQpcTMgCmHgHUa7WiIJpQy Ukg= WDCIronportException: Internal From: Alistair Francis To: peter.maydell@linaro.org, qemu-devel@nongnu.org Subject: [PULL v2 12/12] hw/riscv/boot: Check the error of fdt_pack() Date: Thu, 15 Jul 2021 00:16:40 -0700 Message-Id: <20210715071640.232070-13-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210715071640.232070-1-alistair.francis@wdc.com> References: <20210715071640.232070-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=8230c157d=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626334083139100003 Content-Type: text/plain; charset="utf-8" Coverity reports that we don't check the error result of fdt_pack(), so let's save the result and assert that it is 0. Fixes: Coverity CID 1458136 Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 07325315b49d5555269f76094e4bc5296e0643b9.1626303527.git.alistai= r.francis@wdc.com --- hw/riscv/boot.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 0d38bb7426..993bf89064 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -182,7 +182,7 @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_= size, void *fdt) { uint32_t temp, fdt_addr; hwaddr dram_end =3D dram_base + mem_size; - int fdtsize =3D fdt_totalsize(fdt); + int ret, fdtsize =3D fdt_totalsize(fdt); =20 if (fdtsize <=3D 0) { error_report("invalid device-tree"); @@ -198,7 +198,9 @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_= size, void *fdt) temp =3D MIN(dram_end, 3072 * MiB); fdt_addr =3D QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB); =20 - fdt_pack(fdt); + ret =3D fdt_pack(fdt); + /* Should only fail if we've built a corrupted tree */ + g_assert(ret =3D=3D 0); /* copy in the device tree */ qemu_fdt_dumpdtb(fdt, fdtsize); =20 --=20 2.31.1