[PULL 0/2] riscv-to-apply queue
[PULL 0/2] riscv-to-apply queue
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From: Alistair Francis <alistair.francis@wdc.com>
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From: Alistair Francis <alistair.francis@wdc.com>
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The following changes since commit 8d5fcb1990bc64b62c0bc12121fe510940be5664:
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The following changes since commit c5fbdd60cf1fb52f01bdfe342b6fa65d5343e1b1:
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Merge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into staging (2021-11-17 07:41:08 +0100)
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Merge tag 'qemu-sparc-20211121' of git://github.com/mcayland/qemu into staging (2021-11-21 14:12:25 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211117-1
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git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211122
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for you to fetch changes up to c94c239496256f1f1cb589825d052c2f3e26ebf6:
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for you to fetch changes up to 526e7443027c71fe7b04c29df529e1f9f425f9e3:
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meson.build: Merge riscv32 and riscv64 cpu family (2021-11-17 19:18:22 +1000)
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hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset (2021-11-22 10:46:22 +1000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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Sixth RISC-V PR for QEMU 6.2
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Seventh RISC-V PR for QEMU 6.2
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- Fix build for riscv hosts
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- Deprecate IF_NONE for SiFive OTP
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- Soft code alphabetically
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- Don't reset SiFive OTP content
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----------------------------------------------------------------
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----------------------------------------------------------------
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Bin Meng (1):
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Philippe Mathieu-Daudé (1):
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target/riscv: machine: Sort the .subsections
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hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
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Richard Henderson (1):
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Thomas Huth (1):
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meson.build: Merge riscv32 and riscv64 cpu family
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hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
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meson.build | 6 ++++
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docs/about/deprecated.rst | 6 ++++++
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target/riscv/machine.c | 92 +++++++++++++++++++++++++-------------------------
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hw/misc/sifive_u_otp.c | 22 +++++++++++++---------
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2 files changed, 52 insertions(+), 46 deletions(-)
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2 files changed, 19 insertions(+), 9 deletions(-)
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diff view generated by jsdifflib
[PULL 2/2] meson.build: Merge riscv32 and riscv64 cpu family
[PULL 1/2] hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
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From: Richard Henderson <richard.henderson@linaro.org>
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From: Thomas Huth <thuth@redhat.com>
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2
3
In ba0e73336200, we merged riscv32 and riscv64 in configure.
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Configuring a drive with "if=none" is meant for creation of a backend
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However, meson does not treat them the same. We need to merge
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only, it should not get automatically assigned to a device frontend.
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them here as well.
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Use "if=pflash" for the One-Time-Programmable device instead (like
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it is e.g. also done for the efuse device in hw/arm/xlnx-zcu102.c).
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7
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Fixes: ba0e73336200
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Since the old way of configuring the device has already been published
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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with the previous QEMU versions, we cannot remove this immediately, but
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Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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have to deprecate it and support it for at least two more releases.
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Signed-off-by: Thomas Huth <thuth@redhat.com>
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Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com>
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Reviewed-by: Markus Armbruster <armbru@redhat.com>
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Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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Message-id: 20211116095042.335224-1-richard.henderson@linaro.org
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Message-id: 20211119102549.217755-1-thuth@redhat.com
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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---
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---
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meson.build | 6 ++++++
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docs/about/deprecated.rst | 6 ++++++
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1 file changed, 6 insertions(+)
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hw/misc/sifive_u_otp.c | 9 ++++++++-
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2 files changed, 14 insertions(+), 1 deletion(-)
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diff --git a/meson.build b/meson.build
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diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
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index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
19
--- a/meson.build
25
--- a/docs/about/deprecated.rst
20
+++ b/meson.build
26
+++ b/docs/about/deprecated.rst
21
@@ -XXX,XX +XXX,XX @@ supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv', 'x86', 'x86_64',
27
@@ -XXX,XX +XXX,XX @@ as short-form boolean values, and passed to plugins as ``arg_name=on``.
22
'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64']
28
However, short-form booleans are deprecated and full explicit ``arg_name=on``
23
29
form is preferred.
24
cpu = host_machine.cpu_family()
30
31
+``-drive if=none`` for the sifive_u OTP device (since 6.2)
32
+''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
25
+
33
+
26
+# Unify riscv* to a single family.
34
+Using ``-drive if=none`` to configure the OTP device of the sifive_u
27
+if cpu in ['riscv32', 'riscv64']
35
+RISC-V machine is deprecated. Use ``-drive if=pflash`` instead.
28
+ cpu = 'riscv'
29
+endif
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+
36
+
31
targetos = host_machine.system()
37
32
38
QEMU Machine Protocol (QMP) commands
33
if cpu in ['x86', 'x86_64']
39
------------------------------------
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diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
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index XXXXXXX..XXXXXXX 100644
42
--- a/hw/misc/sifive_u_otp.c
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+++ b/hw/misc/sifive_u_otp.c
44
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
45
TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE);
46
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
47
48
- dinfo = drive_get_next(IF_NONE);
49
+ dinfo = drive_get_next(IF_PFLASH);
50
+ if (!dinfo) {
51
+ dinfo = drive_get_next(IF_NONE);
52
+ if (dinfo) {
53
+ warn_report("using \"-drive if=none\" for the OTP is deprecated, "
54
+ "use \"-drive if=pflash\" instead.");
55
+ }
56
+ }
57
if (dinfo) {
58
int ret;
59
uint64_t perm;
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--
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--
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2.31.1
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2.31.1
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62
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63
diff view generated by jsdifflib
[PULL 1/2] target/riscv: machine: Sort the .subsections
[PULL 2/2] hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
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From: Bin Meng <bin.meng@windriver.com>
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From: Philippe Mathieu-Daudé <f4bug@amsat.org>
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Move the codes around so that the order of .subsections matches
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Once a "One Time Programmable" is programmed, it shouldn't be reset.
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the one they are referenced in vmstate_riscv_cpu.
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Signed-off-by: Bin Meng <bin.meng@windriver.com>
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Do not re-initialize the OTP content in the DeviceReset handler,
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initialize it once in the DeviceRealize one.
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Fixes: 9fb45c62ae8 ("riscv: sifive: Implement a model for SiFive FU540 OTP")
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Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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Message-id: 20211030030606.32297-1-bmeng.cn@gmail.com
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Message-Id: <20211119104757.331579-1-f4bug@amsat.org>
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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---
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---
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target/riscv/machine.c | 92 +++++++++++++++++++++---------------------
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hw/misc/sifive_u_otp.c | 13 +++++--------
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1 file changed, 46 insertions(+), 46 deletions(-)
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1 file changed, 5 insertions(+), 8 deletions(-)
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diff --git a/target/riscv/machine.c b/target/riscv/machine.c
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diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
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index XXXXXXX..XXXXXXX 100644
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index XXXXXXX..XXXXXXX 100644
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--- a/target/riscv/machine.c
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--- a/hw/misc/sifive_u_otp.c
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+++ b/target/riscv/machine.c
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+++ b/hw/misc/sifive_u_otp.c
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@@ -XXX,XX +XXX,XX @@ static bool hyper_needed(void *opaque)
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@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
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return riscv_has_ext(env, RVH);
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if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) {
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error_setg(errp, "failed to read the initial flash content");
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+ return;
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}
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}
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}
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-}
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-
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-static void sifive_u_otp_reset(DeviceState *dev)
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-{
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- SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
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/* Initialize all fuses' initial value to 0xFFs */
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memset(s->fuse, 0xff, sizeof(s->fuse));
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@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev)
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serial_data = s->serial;
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if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
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&serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
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- error_report("write error index<%d>", index);
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+ error_setg(errp, "failed to write index<%d>", index);
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+ return;
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}
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serial_data = ~(s->serial);
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if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
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&serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
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- error_report("write error index<%d>", index + 1);
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+ error_setg(errp, "failed to write index<%d>", index + 1);
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+ return;
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}
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}
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@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_class_init(ObjectClass *klass, void *data)
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device_class_set_props(dc, sifive_u_otp_properties);
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dc->realize = sifive_u_otp_realize;
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- dc->reset = sifive_u_otp_reset;
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}
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}
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22
-static bool vector_needed(void *opaque)
62
static const TypeInfo sifive_u_otp_info = {
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-{
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- RISCVCPU *cpu = opaque;
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- CPURISCVState *env = &cpu->env;
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+static const VMStateDescription vmstate_hyper = {
27
+ .name = "cpu/hyper",
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+ .version_id = 1,
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+ .minimum_version_id = 1,
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+ .needed = hyper_needed,
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+ .fields = (VMStateField[]) {
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+ VMSTATE_UINTTL(env.hstatus, RISCVCPU),
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+ VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
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+ VMSTATE_UINTTL(env.hideleg, RISCVCPU),
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+ VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
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+ VMSTATE_UINTTL(env.htval, RISCVCPU),
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+ VMSTATE_UINTTL(env.htinst, RISCVCPU),
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+ VMSTATE_UINTTL(env.hgatp, RISCVCPU),
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+ VMSTATE_UINT64(env.htimedelta, RISCVCPU),
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- return riscv_has_ext(env, RVV);
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-}
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+ VMSTATE_UINT64(env.vsstatus, RISCVCPU),
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+ VMSTATE_UINTTL(env.vstvec, RISCVCPU),
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+ VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
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+ VMSTATE_UINTTL(env.vsepc, RISCVCPU),
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+ VMSTATE_UINTTL(env.vscause, RISCVCPU),
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+ VMSTATE_UINTTL(env.vstval, RISCVCPU),
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+ VMSTATE_UINTTL(env.vsatp, RISCVCPU),
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-static bool pointermasking_needed(void *opaque)
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+ VMSTATE_UINTTL(env.mtval2, RISCVCPU),
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+ VMSTATE_UINTTL(env.mtinst, RISCVCPU),
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+
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+ VMSTATE_UINTTL(env.stvec_hs, RISCVCPU),
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+ VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU),
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+ VMSTATE_UINTTL(env.sepc_hs, RISCVCPU),
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+ VMSTATE_UINTTL(env.scause_hs, RISCVCPU),
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+ VMSTATE_UINTTL(env.stval_hs, RISCVCPU),
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+ VMSTATE_UINTTL(env.satp_hs, RISCVCPU),
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+ VMSTATE_UINT64(env.mstatus_hs, RISCVCPU),
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+
63
+ VMSTATE_END_OF_LIST()
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+ }
65
+};
66
+
67
+static bool vector_needed(void *opaque)
68
{
69
RISCVCPU *cpu = opaque;
70
CPURISCVState *env = &cpu->env;
71
72
- return riscv_has_ext(env, RVJ);
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+ return riscv_has_ext(env, RVV);
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}
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static const VMStateDescription vmstate_vector = {
77
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_vector = {
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}
79
};
80
81
+static bool pointermasking_needed(void *opaque)
82
+{
83
+ RISCVCPU *cpu = opaque;
84
+ CPURISCVState *env = &cpu->env;
85
+
86
+ return riscv_has_ext(env, RVJ);
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+}
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+
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static const VMStateDescription vmstate_pointermasking = {
90
.name = "cpu/pointer_masking",
91
.version_id = 1,
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@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pointermasking = {
93
}
94
};
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-static const VMStateDescription vmstate_hyper = {
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- .name = "cpu/hyper",
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- .version_id = 1,
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- .minimum_version_id = 1,
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- .needed = hyper_needed,
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- .fields = (VMStateField[]) {
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- VMSTATE_UINTTL(env.hstatus, RISCVCPU),
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- VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
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- VMSTATE_UINTTL(env.hideleg, RISCVCPU),
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- VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
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- VMSTATE_UINTTL(env.htval, RISCVCPU),
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- VMSTATE_UINTTL(env.htinst, RISCVCPU),
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- VMSTATE_UINTTL(env.hgatp, RISCVCPU),
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- VMSTATE_UINT64(env.htimedelta, RISCVCPU),
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-
111
- VMSTATE_UINT64(env.vsstatus, RISCVCPU),
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- VMSTATE_UINTTL(env.vstvec, RISCVCPU),
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- VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
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- VMSTATE_UINTTL(env.vsepc, RISCVCPU),
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- VMSTATE_UINTTL(env.vscause, RISCVCPU),
116
- VMSTATE_UINTTL(env.vstval, RISCVCPU),
117
- VMSTATE_UINTTL(env.vsatp, RISCVCPU),
118
-
119
- VMSTATE_UINTTL(env.mtval2, RISCVCPU),
120
- VMSTATE_UINTTL(env.mtinst, RISCVCPU),
121
-
122
- VMSTATE_UINTTL(env.stvec_hs, RISCVCPU),
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- VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU),
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- VMSTATE_UINTTL(env.sepc_hs, RISCVCPU),
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- VMSTATE_UINTTL(env.scause_hs, RISCVCPU),
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- VMSTATE_UINTTL(env.stval_hs, RISCVCPU),
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- VMSTATE_UINTTL(env.satp_hs, RISCVCPU),
128
- VMSTATE_UINT64(env.mstatus_hs, RISCVCPU),
129
-
130
- VMSTATE_END_OF_LIST()
131
- }
132
-};
133
-
134
const VMStateDescription vmstate_riscv_cpu = {
135
.name = "cpu",
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.version_id = 3,
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--
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--
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2.31.1
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2.31.1
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140
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diff view generated by jsdifflib

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