In this patch set, we process the pc reigsters writes,
gdb reads and writes, and address calculation under
different UXLEN settings.
v2:
Split out vill from vtype
Remove context switch when xlen changes at exception
Use XL instead of OL in many places
Use pointer masking and XLEN for vector address
Define an common fuction to calculate address for ldst
LIU Zhiwei (14):
target/riscv: Sign extend pc for different XLEN
target/riscv: Ignore the pc bits above XLEN
target/riscv: Extend pc for runtime pc write
target/riscv: Use gdb xml according to max mxlen
target/riscv: Calculate address according to XLEN
target/riscv: Adjust vsetvl according to XLEN
target/riscv: Ajdust vector atomic check with XLEN
target/riscv: Fix check range for first fault only
target/riscv: Relax debug check for pm write
target/riscv: Adjust vector address with mask
target/riscv: Adjust scalar reg in vector with XLEN
target/riscv: Split out the vill from vtype
target/riscv: Don't save pc when exception return
target/riscv: Enable uxl field write
target/riscv/cpu.c | 23 +++++-
target/riscv/cpu.h | 9 +++
target/riscv/cpu_helper.c | 47 +++++++++++-
target/riscv/csr.c | 42 ++++++++++-
target/riscv/gdbstub.c | 73 ++++++++++++++-----
target/riscv/helper.h | 6 +-
.../riscv/insn_trans/trans_privileged.c.inc | 7 +-
target/riscv/insn_trans/trans_rvd.c.inc | 23 +-----
target/riscv/insn_trans/trans_rvf.c.inc | 23 +-----
target/riscv/insn_trans/trans_rvi.c.inc | 22 +-----
target/riscv/insn_trans/trans_rvv.c.inc | 12 +--
target/riscv/internals.h | 1 +
target/riscv/machine.c | 11 +++
target/riscv/op_helper.c | 7 +-
target/riscv/translate.c | 29 +++++++-
target/riscv/vector_helper.c | 54 +++++++++-----
16 files changed, 263 insertions(+), 126 deletions(-)
--
2.25.1