From nobody Tue Feb 10 02:51:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16365279952831011.0750083318082; Tue, 9 Nov 2021 23:06:35 -0800 (PST) Received: from localhost ([::1]:38850 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mkhgo-0007qj-Cs for importer@patchew.org; Wed, 10 Nov 2021 02:06:34 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37592) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhfq-0006JO-3i; Wed, 10 Nov 2021 02:05:34 -0500 Received: from out28-218.mail.aliyun.com ([115.124.28.218]:46507) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhfn-00046h-Of; Wed, 10 Nov 2021 02:05:33 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LqUBpyc_1636527926) by smtp.aliyun-inc.com(10.147.42.241); Wed, 10 Nov 2021 15:05:27 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1150252|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0320985-0.000647087-0.967254; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047211; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.LqUBpyc_1636527926; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 01/14] target/riscv: Sign extend pc for different XLEN Date: Wed, 10 Nov 2021 15:04:39 +0800 Message-Id: <20211110070452.48539-2-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211110070452.48539-1-zhiwei_liu@c-sky.com> References: <20211110070452.48539-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.218; envelope-from=zhiwei_liu@c-sky.com; helo=out28-218.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636528019271100001 Content-Type: text/plain; charset="utf-8" When pc is written, it is sign-extended to fill the widest supported XLEN. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/translate.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1d57bc97b5..a6a73ced9e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -150,16 +150,24 @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64= in) tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); } =20 +static void gen_set_pc(DisasContext *ctx, target_ulong dest) +{ + if (get_xl(ctx) =3D=3D MXL_RV32) { + dest =3D (int32_t)dest; + } + tcg_gen_movi_tl(cpu_pc, dest); +} + static void generate_exception(DisasContext *ctx, int excp) { - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); + gen_set_pc(ctx, ctx->base.pc_next); gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); ctx->base.is_jmp =3D DISAS_NORETURN; } =20 static void generate_exception_mtval(DisasContext *ctx, int excp) { - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); + gen_set_pc(ctx, ctx->base.pc_next); tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); ctx->base.is_jmp =3D DISAS_NORETURN; @@ -179,10 +187,10 @@ static void gen_goto_tb(DisasContext *ctx, int n, tar= get_ulong dest) { if (translator_use_goto_tb(&ctx->base, dest)) { tcg_gen_goto_tb(n); - tcg_gen_movi_tl(cpu_pc, dest); + gen_set_pc(ctx, dest); tcg_gen_exit_tb(ctx->base.tb, n); } else { - tcg_gen_movi_tl(cpu_pc, dest); + gen_set_pc(ctx, dest); tcg_gen_lookup_and_goto_ptr(); } } --=20 2.25.1 From nobody Tue Feb 10 02:51:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636528091452273.188559631888; Tue, 9 Nov 2021 23:08:11 -0800 (PST) Received: from localhost ([::1]:42566 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mkhiK-00020Q-26 for importer@patchew.org; Wed, 10 Nov 2021 02:08:09 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37764) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhgL-0007k8-T5; Wed, 10 Nov 2021 02:06:05 -0500 Received: from out28-76.mail.aliyun.com ([115.124.28.76]:49994) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhgK-0004Ft-CD; Wed, 10 Nov 2021 02:06:05 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LqTz0cl_1636527957) by smtp.aliyun-inc.com(10.147.41.158); Wed, 10 Nov 2021 15:05:57 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1147071|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.013589-0.000341692-0.986069; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047198; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.LqTz0cl_1636527957; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 02/14] target/riscv: Ignore the pc bits above XLEN Date: Wed, 10 Nov 2021 15:04:40 +0800 Message-Id: <20211110070452.48539-3-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211110070452.48539-1-zhiwei_liu@c-sky.com> References: <20211110070452.48539-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.76; envelope-from=zhiwei_liu@c-sky.com; helo=out28-76.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636528092396100001 Content-Type: text/plain; charset="utf-8" The read from PC for translation is in cpu_get_tb_cpu_state, before transla= tion. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/cpu_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9eeed38c7e..4c048cc266 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -70,8 +70,9 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulon= g *pc, target_ulong *cs_base, uint32_t *pflags) { uint32_t flags =3D 0; + RISCVMXL xl =3D cpu_get_xl(env); =20 - *pc =3D env->pc; + *pc =3D xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; *cs_base =3D 0; =20 if (riscv_has_ext(env, RVV)) { @@ -127,7 +128,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ul= ong *pc, } #endif =20 - flags =3D FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env)); + flags =3D FIELD_DP32(flags, TB_FLAGS, XL, xl); =20 *pflags =3D flags; } --=20 2.25.1 From nobody Tue Feb 10 02:51:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636528173333444.69028772974673; Tue, 9 Nov 2021 23:09:33 -0800 (PST) Received: from localhost ([::1]:49100 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mkhjg-0006Oc-98 for importer@patchew.org; Wed, 10 Nov 2021 02:09:32 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37838) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhgy-00006z-DN; Wed, 10 Nov 2021 02:06:44 -0500 Received: from out28-3.mail.aliyun.com ([115.124.28.3]:46614) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhgq-0004IC-DL; Wed, 10 Nov 2021 02:06:42 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LqU35ad_1636527988) by smtp.aliyun-inc.com(10.147.42.16); Wed, 10 Nov 2021 15:06:28 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07467966|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.081855-0.000518238-0.917627; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047190; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.LqU35ad_1636527988; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 03/14] target/riscv: Extend pc for runtime pc write Date: Wed, 10 Nov 2021 15:04:41 +0800 Message-Id: <20211110070452.48539-4-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211110070452.48539-1-zhiwei_liu@c-sky.com> References: <20211110070452.48539-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.3; envelope-from=zhiwei_liu@c-sky.com; helo=out28-3.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636528175351100001 Content-Type: text/plain; charset="utf-8" In some cases, we must restore the guest PC to the address of the start of the TB, such as when the instruction counter hits zero. So extend pc regist= er according to current xlen for these cases. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.c | 22 +++++++++++++++++++--- target/riscv/cpu.h | 2 ++ target/riscv/cpu_helper.c | 2 +- 3 files changed, 22 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f812998123..0d2d175fa2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -319,7 +319,12 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - env->pc =3D value; + + if (cpu_get_xl(env) =3D=3D MXL_RV32) { + env->pc =3D (int32_t)value; + } else { + env->pc =3D value; + } } =20 static void riscv_cpu_synchronize_from_tb(CPUState *cs, @@ -327,7 +332,13 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - env->pc =3D tb->pc; + RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); + + if (xl =3D=3D MXL_RV32) { + env->pc =3D (int32_t)tb->pc; + } else { + env->pc =3D tb->pc; + } } =20 static bool riscv_cpu_has_work(CPUState *cs) @@ -348,7 +359,12 @@ static bool riscv_cpu_has_work(CPUState *cs) void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, target_ulong *data) { - env->pc =3D data[0]; + RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); + if (xl =3D=3D MXL_RV32) { + env->pc =3D (int32_t)data[0]; + } else { + env->pc =3D data[0]; + } } =20 static void riscv_cpu_reset(DeviceState *dev) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0760c0af93..8befff0166 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -420,6 +420,8 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) } #endif =20 +RISCVMXL cpu_get_xl(CPURISCVState *env); + /* * A simplification for VLMAX * =3D (1 << LMUL) * VLEN / (8 * (1 << SEW)) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 4c048cc266..79aba9c880 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -35,7 +35,7 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #endif } =20 -static RISCVMXL cpu_get_xl(CPURISCVState *env) +RISCVMXL cpu_get_xl(CPURISCVState *env) { #if defined(TARGET_RISCV32) return MXL_RV32; --=20 2.25.1 From nobody Tue Feb 10 02:51:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636528101101989.9284486390493; Tue, 9 Nov 2021 23:08:21 -0800 (PST) Received: from localhost ([::1]:43408 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mkhiW-0002a2-2z for importer@patchew.org; Wed, 10 Nov 2021 02:08:20 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37982) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhhO-0000ou-3E; Wed, 10 Nov 2021 02:07:10 -0500 Received: from out28-52.mail.aliyun.com ([115.124.28.52]:50522) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhhK-0004LU-Mt; Wed, 10 Nov 2021 02:07:09 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LqTz1F1_1636528019) by smtp.aliyun-inc.com(10.147.41.158); Wed, 10 Nov 2021 15:06:59 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07459338|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0231685-0.000144035-0.976687; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047199; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.LqTz1F1_1636528019; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 04/14] target/riscv: Use gdb xml according to max mxlen Date: Wed, 10 Nov 2021 15:04:42 +0800 Message-Id: <20211110070452.48539-5-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211110070452.48539-1-zhiwei_liu@c-sky.com> References: <20211110070452.48539-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.52; envelope-from=zhiwei_liu@c-sky.com; helo=out28-52.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636528102950100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/gdbstub.c | 73 +++++++++++++++++++++++++++++++----------- 1 file changed, 54 insertions(+), 19 deletions(-) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 23429179e2..7563414ef7 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -24,11 +24,25 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArra= y *mem_buf, int n) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; + target_ulong tmp; =20 if (n < 32) { - return gdb_get_regl(mem_buf, env->gpr[n]); + tmp =3D env->gpr[n]; } else if (n =3D=3D 32) { - return gdb_get_regl(mem_buf, env->pc); + tmp =3D env->pc; + } else { + return 0; + } + + switch (env->misa_mxl_max) { + case MXL_RV32: + gdb_get_reg32(mem_buf, tmp); + break; + case MXL_RV64: + gdb_get_reg64(mem_buf, tmp); + break; + default: + g_assert_not_reached(); } return 0; } @@ -37,18 +51,32 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t = *mem_buf, int n) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - - if (n =3D=3D 0) { - /* discard writes to x0 */ - return sizeof(target_ulong); - } else if (n < 32) { - env->gpr[n] =3D ldtul_p(mem_buf); - return sizeof(target_ulong); + int length =3D 0; + target_ulong tmp; + + switch (env->misa_mxl_max) { + case MXL_RV32: + tmp =3D (int32_t)ldl_p(mem_buf); + length =3D 4; + break; + case MXL_RV64: + if (cpu_get_xl(env) < MXL_RV64) { + tmp =3D (int32_t)ldq_p(mem_buf); + } else { + tmp =3D ldq_p(mem_buf); + } + length =3D 8; + break; + default: + g_assert_not_reached(); + } + if (n > 0 && n < 32) { + env->gpr[n] =3D tmp; } else if (n =3D=3D 32) { - env->pc =3D ldtul_p(mem_buf); - return sizeof(target_ulong); + env->pc =3D tmp; } - return 0; + + return length; } =20 static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n) @@ -198,13 +226,20 @@ void riscv_cpu_register_gdb_regs_for_features(CPUStat= e *cs) gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 36, "riscv-32bit-fpu.xml", 0); } -#if defined(TARGET_RISCV32) - gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virt= ual, - 1, "riscv-32bit-virtual.xml", 0); -#elif defined(TARGET_RISCV64) - gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virt= ual, - 1, "riscv-64bit-virtual.xml", 0); -#endif + switch (env->misa_mxl_max) { + case MXL_RV32: + gdb_register_coprocessor(cs, riscv_gdb_get_virtual, + riscv_gdb_set_virtual, + 1, "riscv-32bit-virtual.xml", 0); + break; + case MXL_RV64: + gdb_register_coprocessor(cs, riscv_gdb_get_virtual, + riscv_gdb_set_virtual, + 1, "riscv-64bit-virtual.xml", 0); + break; + default: + g_assert_not_reached(); + } =20 gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_reg= s), --=20 2.25.1 From nobody Tue Feb 10 02:51:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636528114324355.0794495273951; Tue, 9 Nov 2021 23:08:34 -0800 (PST) Received: from localhost ([::1]:44712 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mkhij-0003Ra-AQ for importer@patchew.org; Wed, 10 Nov 2021 02:08:33 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38218) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhho-0001Ji-SU; Wed, 10 Nov 2021 02:07:36 -0500 Received: from out28-76.mail.aliyun.com ([115.124.28.76]:59951) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhhn-0004R0-0N; Wed, 10 Nov 2021 02:07:36 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LqUNF8n_1636528049) by smtp.aliyun-inc.com(10.147.41.137); Wed, 10 Nov 2021 15:07:29 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.00648203-6.3261e-05-0.993455; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047193; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.LqUNF8n_1636528049; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 05/14] target/riscv: Calculate address according to XLEN Date: Wed, 10 Nov 2021 15:04:43 +0800 Message-Id: <20211110070452.48539-6-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211110070452.48539-1-zhiwei_liu@c-sky.com> References: <20211110070452.48539-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.76; envelope-from=zhiwei_liu@c-sky.com; helo=out28-76.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636528116112100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvd.c.inc | 23 ++--------------------- target/riscv/insn_trans/trans_rvf.c.inc | 23 ++--------------------- target/riscv/insn_trans/trans_rvi.c.inc | 18 ++---------------- target/riscv/translate.c | 13 +++++++++++++ 4 files changed, 19 insertions(+), 58 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 64fb0046f7..29066a8ef3 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -20,19 +20,10 @@ =20 static bool trans_fld(DisasContext *ctx, arg_fld *a) { - TCGv addr; - + TCGv addr =3D get_address(ctx, a->rs1, a->imm); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - if (a->imm) { - TCGv temp =3D temp_new(ctx); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } - addr =3D gen_pm_adjust_address(ctx, addr); - tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEQ); =20 mark_fs_dirty(ctx); @@ -41,21 +32,11 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) =20 static bool trans_fsd(DisasContext *ctx, arg_fsd *a) { - TCGv addr; - + TCGv addr =3D get_address(ctx, a->rs1, a->imm); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); =20 - addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - if (a->imm) { - TCGv temp =3D temp_new(ctx); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } - addr =3D gen_pm_adjust_address(ctx, addr); - tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEQ); - return true; } =20 diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index b5459249c4..a33897db7d 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -26,19 +26,10 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) { TCGv_i64 dest; - TCGv addr; - + TCGv addr =3D get_address(ctx, a->rs1, a->imm); REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - if (a->imm) { - TCGv temp =3D temp_new(ctx); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } - addr =3D gen_pm_adjust_address(ctx, addr); - dest =3D cpu_fpr[a->rd]; tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL); gen_nanbox_s(dest, dest); @@ -49,21 +40,11 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) =20 static bool trans_fsw(DisasContext *ctx, arg_fsw *a) { - TCGv addr; - + TCGv addr =3D get_address(ctx, a->rs1, a->imm); REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - if (a->imm) { - TCGv temp =3D tcg_temp_new(); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } - addr =3D gen_pm_adjust_address(ctx, addr); - tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL); - return true; } =20 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index e51dbc41c5..7a0b037594 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -137,14 +137,7 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a) static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop) { TCGv dest =3D dest_gpr(ctx, a->rd); - TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - - if (a->imm) { - TCGv temp =3D temp_new(ctx); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } - addr =3D gen_pm_adjust_address(ctx, addr); + TCGv addr =3D get_address(ctx, a->rs1, a->imm); =20 tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop); gen_set_gpr(ctx, a->rd, dest); @@ -178,16 +171,9 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a) =20 static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) { - TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv addr =3D get_address(ctx, a->rs1, a->imm); TCGv data =3D get_gpr(ctx, a->rs2, EXT_NONE); =20 - if (a->imm) { - TCGv temp =3D temp_new(ctx); - tcg_gen_addi_tl(temp, addr, a->imm); - addr =3D temp; - } - addr =3D gen_pm_adjust_address(ctx, addr); - tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); return true; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a6a73ced9e..f52f6ef246 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -303,6 +303,19 @@ static TCGv gen_pm_adjust_address(DisasContext *s, TCG= v src) } } =20 +static TCGv get_address(DisasContext *ctx, int rs1, int imm) +{ + TCGv addr =3D temp_new(ctx); + TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); + + tcg_gen_addi_tl(addr, src1, imm); + addr =3D gen_pm_adjust_address(ctx, addr); + if (get_xl(ctx) =3D=3D MXL_RV32) { + tcg_gen_ext32u_tl(addr, addr); + } + return addr; +} + #ifndef CONFIG_USER_ONLY /* The states of mstatus_fs are: * 0 =3D disabled, 1 =3D initial, 2 =3D clean, 3 =3D dirty --=20 2.25.1 From nobody Tue Feb 10 02:51:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636528222927204.95211619965607; Tue, 9 Nov 2021 23:10:22 -0800 (PST) Received: from localhost ([::1]:51130 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mkhkT-0007jH-TD for importer@patchew.org; Wed, 10 Nov 2021 02:10:21 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38372) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhiO-00035b-7J; Wed, 10 Nov 2021 02:08:12 -0500 Received: from out28-77.mail.aliyun.com ([115.124.28.77]:36657) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhiL-0004VS-AK; Wed, 10 Nov 2021 02:08:11 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LqU1bUp_1636528080) by smtp.aliyun-inc.com(10.147.40.2); Wed, 10 Nov 2021 15:08:00 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07437406|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.332518-0.000486663-0.666995; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047194; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.LqU1bUp_1636528080; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 06/14] target/riscv: Adjust vsetvl according to XLEN Date: Wed, 10 Nov 2021 15:04:44 +0800 Message-Id: <20211110070452.48539-7-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211110070452.48539-1-zhiwei_liu@c-sky.com> References: <20211110070452.48539-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.77; envelope-from=zhiwei_liu@c-sky.com; helo=out28-77.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636528224566100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 2 ++ target/riscv/helper.h | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- target/riscv/vector_helper.c | 19 +++++++++++++++---- 4 files changed, 20 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8befff0166..11590a510e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -107,6 +107,8 @@ FIELD(VTYPE, VSEW, 2, 3) FIELD(VTYPE, VEDIV, 5, 2) FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) +FIELD(VTYPE, RESERVED_XLEN32, 7, 23) +FIELD(VTYPE, VILL_XLEN32, 31, 1) =20 struct CPURISCVState { target_ulong gpr[32]; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index c7a5376227..e198d43981 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -82,7 +82,7 @@ DEF_HELPER_2(hyp_hlvx_wu, tl, env, tl) #endif =20 /* Vector functions */ -DEF_HELPER_3(vsetvl, tl, env, tl, tl) +DEF_HELPER_4(vsetvl, tl, env, tl, tl, tl) DEF_HELPER_5(vlb_v_b, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vlb_v_b_mask, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vlb_v_h, void, ptr, ptr, tl, env, i32) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 17ee3babef..f5aabd5263 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -37,7 +37,7 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a) } else { s1 =3D get_gpr(ctx, a->rs1, EXT_ZERO); } - gen_helper_vsetvl(dst, cpu_env, s1, s2); + gen_helper_vsetvl(dst, cpu_env, s1, s2, tcg_constant_tl(get_xlen(ctx))= ); gen_set_gpr(ctx, a->rd, dst); =20 tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); @@ -64,7 +64,7 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli = *a) } else { s1 =3D get_gpr(ctx, a->rs1, EXT_ZERO); } - gen_helper_vsetvl(dst, cpu_env, s1, s2); + gen_helper_vsetvl(dst, cpu_env, s1, s2, tcg_constant_tl(get_xlen(ctx))= ); gen_set_gpr(ctx, a->rd, dst); =20 gen_goto_tb(ctx, 0, ctx->pc_succ_insn); diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 12c31aa4b4..cb6fa8718d 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -27,18 +27,29 @@ #include =20 target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, - target_ulong s2) + target_ulong s2, target_ulong xlen) { int vlmax, vl; RISCVCPU *cpu =3D env_archcpu(env); uint16_t sew =3D 8 << FIELD_EX64(s2, VTYPE, VSEW); uint8_t ediv =3D FIELD_EX64(s2, VTYPE, VEDIV); - bool vill =3D FIELD_EX64(s2, VTYPE, VILL); - target_ulong reserved =3D FIELD_EX64(s2, VTYPE, RESERVED); + bool vill; + target_ulong reserved; =20 + if (xlen < TARGET_LONG_BITS) { + vill =3D FIELD_EX64(s2, VTYPE, VILL_XLEN32); + reserved =3D FIELD_EX64(s2, VTYPE, RESERVED_XLEN32); + } else { + vill =3D FIELD_EX64(s2, VTYPE, VILL); + reserved =3D FIELD_EX64(s2, VTYPE, RESERVED); + } if ((sew > cpu->cfg.elen) || vill || (ediv !=3D 0) || (reserved !=3D 0= )) { /* only set vill bit. */ - env->vtype =3D FIELD_DP64(0, VTYPE, VILL, 1); + if (xlen < TARGET_LONG_BITS) { + env->vtype =3D FIELD_DP64(0, VTYPE, VILL_XLEN32, 1); + } else { + env->vtype =3D FIELD_DP64(0, VTYPE, VILL, 1); + } env->vl =3D 0; env->vstart =3D 0; return 0; --=20 2.25.1 From nobody Tue Feb 10 02:51:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636528185121915.0131022483417; Tue, 9 Nov 2021 23:09:45 -0800 (PST) Received: from localhost ([::1]:49898 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mkhjs-0006ut-1a for importer@patchew.org; Wed, 10 Nov 2021 02:09:44 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38426) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhip-0004kz-IA; Wed, 10 Nov 2021 02:08:39 -0500 Received: from out28-100.mail.aliyun.com ([115.124.28.100]:42066) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhin-0004Xj-Cn; Wed, 10 Nov 2021 02:08:39 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LqTz26o_1636528110) by smtp.aliyun-inc.com(10.147.41.158); Wed, 10 Nov 2021 15:08:30 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.2621412|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0184311-7.11308e-05-0.981498; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047203; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.LqTz26o_1636528110; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 07/14] target/riscv: Ajdust vector atomic check with XLEN Date: Wed, 10 Nov 2021 15:04:45 +0800 Message-Id: <20211110070452.48539-8-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211110070452.48539-1-zhiwei_liu@c-sky.com> References: <20211110070452.48539-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.100; envelope-from=zhiwei_liu@c-sky.com; helo=out28-100.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636528186342100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index f5aabd5263..41c7c88904 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -739,7 +739,8 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a) (!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) && vext_check_reg(s, a->rd, false) && vext_check_reg(s, a->rs2, false) && - ((1 << s->sew) <=3D sizeof(target_ulong)) && + /* TODO: RV128 could allow 128-bit atomics */ + ((1 << s->sew) <=3D (get_xl(s) =3D=3D MXL_RV32 ? 4 : 8)) && ((1 << s->sew) >=3D 4)); } =20 --=20 2.25.1 From nobody Tue Feb 10 02:51:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636528391188327.66354527621934; Tue, 9 Nov 2021 23:13:11 -0800 (PST) Received: from localhost ([::1]:59840 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mkhnC-0005FK-Gq for importer@patchew.org; Wed, 10 Nov 2021 02:13:10 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38630) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhjL-0006Fs-JR; Wed, 10 Nov 2021 02:09:11 -0500 Received: from out28-172.mail.aliyun.com ([115.124.28.172]:45817) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhjI-0004bz-Rr; Wed, 10 Nov 2021 02:09:10 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LqVF5oK_1636528141) by smtp.aliyun-inc.com(10.147.41.199); Wed, 10 Nov 2021 15:09:01 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1841715|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0508009-0.000453744-0.948745; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047202; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.LqVF5oK_1636528141; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 08/14] target/riscv: Fix check range for first fault only Date: Wed, 10 Nov 2021 15:04:46 +0800 Message-Id: <20211110070452.48539-9-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211110070452.48539-1-zhiwei_liu@c-sky.com> References: <20211110070452.48539-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.172; envelope-from=zhiwei_liu@c-sky.com; helo=out28-172.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636528392666000001 Content-Type: text/plain; charset="utf-8" Only check the range that has passed the address translation. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index cb6fa8718d..60006b1b1b 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -638,12 +638,12 @@ vext_ldff(void *vd, void *v0, target_ulong base, cpu_mmu_index(env, false)); if (host) { #ifdef CONFIG_USER_ONLY - if (page_check_range(addr, nf * msz, PAGE_READ) < 0) { + if (page_check_range(addr, offset, PAGE_READ) < 0) { vl =3D i; goto ProbeSuccess; } #else - probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD); + probe_pages(env, addr, offset, ra, MMU_DATA_LOAD); #endif } else { vl =3D i; --=20 2.25.1 From nobody Tue Feb 10 02:51:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163652857591848.49477303987328; Tue, 9 Nov 2021 23:16:15 -0800 (PST) Received: from localhost ([::1]:38644 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mkhqB-0001Y8-03 for importer@patchew.org; Wed, 10 Nov 2021 02:16:15 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38836) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhjs-0007rZ-Mk; Wed, 10 Nov 2021 02:09:44 -0500 Received: from out28-197.mail.aliyun.com ([115.124.28.197]:41867) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhjq-0004gu-EJ; Wed, 10 Nov 2021 02:09:44 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LqU9ybw_1636528172) by smtp.aliyun-inc.com(10.147.40.7); Wed, 10 Nov 2021 15:09:32 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.3011507|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0189165-0.00166077-0.979423; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047207; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.LqU9ybw_1636528172; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 09/14] target/riscv: Relax debug check for pm write Date: Wed, 10 Nov 2021 15:04:47 +0800 Message-Id: <20211110070452.48539-10-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211110070452.48539-1-zhiwei_liu@c-sky.com> References: <20211110070452.48539-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.197; envelope-from=zhiwei_liu@c-sky.com; helo=out28-197.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636528576953000001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/csr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9f41954894..74c0b788fd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1445,6 +1445,9 @@ static bool check_pm_current_disabled(CPURISCVState *= env, int csrno) int csr_priv =3D get_field(csrno, 0x300); int pm_current; =20 + if (env->debugger) { + return false; + } /* * If priv lvls differ that means we're accessing csr from higher priv= lvl, * so allow the access --=20 2.25.1 From nobody Tue Feb 10 02:51:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636528368769620.72902553948; Tue, 9 Nov 2021 23:12:48 -0800 (PST) Received: from localhost ([::1]:58588 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mkhmp-0004Ps-RU for importer@patchew.org; Wed, 10 Nov 2021 02:12:47 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38994) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhkL-00008y-A4; Wed, 10 Nov 2021 02:10:14 -0500 Received: from out28-217.mail.aliyun.com ([115.124.28.217]:38141) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhkI-0004lD-14; Wed, 10 Nov 2021 02:10:13 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LqV7VtX_1636528202) by smtp.aliyun-inc.com(10.147.42.135); Wed, 10 Nov 2021 15:10:03 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.00407938-0.000463374-0.995457; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047198; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.LqV7VtX_1636528202; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 10/14] target/riscv: Adjust vector address with mask Date: Wed, 10 Nov 2021 15:04:48 +0800 Message-Id: <20211110070452.48539-11-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211110070452.48539-1-zhiwei_liu@c-sky.com> References: <20211110070452.48539-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.217; envelope-from=zhiwei_liu@c-sky.com; helo=out28-217.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636528370656000001 Content-Type: text/plain; charset="utf-8" The mask comes from the pointer masking extension, or the max value corresponding to XLEN bits. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 4 ++++ target/riscv/cpu_helper.c | 40 ++++++++++++++++++++++++++++++++++++ target/riscv/csr.c | 19 +++++++++++++++++ target/riscv/machine.c | 10 +++++++++ target/riscv/vector_helper.c | 23 +++++++++++++-------- 6 files changed, 88 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0d2d175fa2..886388f066 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -378,6 +378,7 @@ static void riscv_cpu_reset(DeviceState *dev) #ifndef CONFIG_USER_ONLY env->misa_mxl =3D env->misa_mxl_max; env->priv =3D PRV_M; + riscv_cpu_update_mask(env); env->mstatus &=3D ~(MSTATUS_MIE | MSTATUS_MPRV); if (env->misa_mxl > MXL_RV32) { /* diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 11590a510e..73d7aa9ad7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -252,6 +252,8 @@ struct CPURISCVState { target_ulong upmmask; target_ulong upmbase; #endif + target_ulong mask; + target_ulong base; =20 float_status fp_status; =20 @@ -443,6 +445,8 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, ta= rget_ulong vtype) void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags); =20 +void riscv_cpu_update_mask(CPURISCVState *env); + RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask= ); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 79aba9c880..d1ecdea392 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -133,6 +133,46 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_u= long *pc, *pflags =3D flags; } =20 +void riscv_cpu_update_mask(CPURISCVState *env) +{ + target_ulong mask =3D -1, base =3D 0; +#ifndef CONFIG_USER_ONLY + if (riscv_has_ext(env, RVJ)) { + switch (env->priv) { + case PRV_M: + if (env->mmte & M_PM_ENABLE) { + mask =3D env->mpmmask; + base =3D env->mpmbase; + } + break; + case PRV_S: + if (env->mmte & S_PM_ENABLE) { + mask =3D env->spmmask; + base =3D env->spmbase; + } + break; + case PRV_U: + if (env->mmte & U_PM_ENABLE) { + mask =3D env->upmmask; + base =3D env->upmbase; + } + break; + default: + g_assert_not_reached(); + } + } +#endif + if (cpu_get_xl(env) =3D=3D MXL_RV32) { + env->mask =3D mask & UINT32_MAX; + env->base =3D base & UINT32_MAX; + } else { + env->mask =3D mask; + env->base =3D base; + } +} + + + #ifndef CONFIG_USER_ONLY static int riscv_cpu_local_irq_pending(CPURISCVState *env) { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 74c0b788fd..59e368f004 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1496,6 +1496,7 @@ static RISCVException write_mmte(CPURISCVState *env, = int csrno, /* hardwiring pm.instruction bit to 0, since it's not supported yet */ wpri_val &=3D ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); env->mmte =3D wpri_val | PM_EXT_DIRTY; + riscv_cpu_update_mask(env); =20 /* Set XS and SD bits, since PM CSRs are dirty */ mstatus =3D env->mstatus | MSTATUS_XS; @@ -1571,6 +1572,9 @@ static RISCVException write_mpmmask(CPURISCVState *en= v, int csrno, uint64_t mstatus; =20 env->mpmmask =3D val; + if ((env->priv =3D=3D PRV_M) && (env->mmte & M_PM_ENABLE)) { + env->mask =3D val; + } env->mmte |=3D PM_EXT_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ @@ -1596,6 +1600,9 @@ static RISCVException write_spmmask(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } env->spmmask =3D val; + if ((env->priv =3D=3D PRV_S) && (env->mmte & S_PM_ENABLE)) { + env->mask =3D val; + } env->mmte |=3D PM_EXT_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ @@ -1621,6 +1628,9 @@ static RISCVException write_upmmask(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } env->upmmask =3D val; + if ((env->priv =3D=3D PRV_U) && (env->mmte & U_PM_ENABLE)) { + env->mask =3D val; + } env->mmte |=3D PM_EXT_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ @@ -1642,6 +1652,9 @@ static RISCVException write_mpmbase(CPURISCVState *en= v, int csrno, uint64_t mstatus; =20 env->mpmbase =3D val; + if ((env->priv =3D=3D PRV_M) && (env->mmte & M_PM_ENABLE)) { + env->base =3D val; + } env->mmte |=3D PM_EXT_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ @@ -1667,6 +1680,9 @@ static RISCVException write_spmbase(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } env->spmbase =3D val; + if ((env->priv =3D=3D PRV_S) && (env->mmte & S_PM_ENABLE)) { + env->base =3D val; + } env->mmte |=3D PM_EXT_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ @@ -1692,6 +1708,9 @@ static RISCVException write_upmbase(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } env->upmbase =3D val; + if ((env->priv =3D=3D PRV_U) && (env->mmte & U_PM_ENABLE)) { + env->base =3D val; + } env->mmte |=3D PM_EXT_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 7b4c739564..19e982d3f0 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -164,10 +164,20 @@ static const VMStateDescription vmstate_hyper =3D { } }; =20 +static int riscv_cpu_post_load(void *opaque, int version_id) +{ + RISCVCPU *cpu =3D opaque; + CPURISCVState *env =3D &cpu->env; + + riscv_cpu_update_mask(env); + return 0; +} + const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", .version_id =3D 3, .minimum_version_id =3D 3, + .post_load =3D riscv_cpu_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 60006b1b1b..0b297f6bc8 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -123,6 +123,11 @@ static inline uint32_t vext_maxsz(uint32_t desc) return simd_maxsz(desc) << vext_lmul(desc); } =20 +static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong ad= dr) +{ + return (addr & env->mask) | env->base; +} + /* * This function checks watchpoint before real load operation. * @@ -140,12 +145,12 @@ static void probe_pages(CPURISCVState *env, target_ul= ong addr, target_ulong pagelen =3D -(addr | TARGET_PAGE_MASK); target_ulong curlen =3D MIN(pagelen, len); =20 - probe_access(env, addr, curlen, access_type, + probe_access(env, adjust_addr(env, addr), curlen, access_type, cpu_mmu_index(env, false), ra); if (len > curlen) { addr +=3D curlen; curlen =3D len - curlen; - probe_access(env, addr, curlen, access_type, + probe_access(env, adjust_addr(env, addr), curlen, access_type, cpu_mmu_index(env, false), ra); } } @@ -306,7 +311,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, } while (k < nf) { target_ulong addr =3D base + stride * i + k * msz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra); k++; } } @@ -399,7 +404,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState= *env, uint32_t desc, k =3D 0; while (k < nf) { target_ulong addr =3D base + (i * nf + k) * msz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra); k++; } } @@ -536,7 +541,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, } while (k < nf) { abi_ptr addr =3D get_index_addr(base, i, vs2) + k * msz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra); k++; } } @@ -626,7 +631,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, if (!vm && !vext_elem_mask(v0, mlen, i)) { continue; } - addr =3D base + nf * i * msz; + addr =3D adjust_addr(env, base + nf * i * msz); if (i =3D=3D 0) { probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD); } else { @@ -653,7 +658,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, break; } remain -=3D offset; - addr +=3D offset; + addr =3D adjust_addr(env, addr + offset); } } } @@ -669,7 +674,7 @@ ProbeSuccess: } while (k < nf) { target_ulong addr =3D base + (i * nf + k) * msz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra); k++; } } @@ -808,7 +813,7 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong bas= e, continue; } addr =3D get_index_addr(base, i, vs2); - noatomic_op(vs3, addr, wd, i, env, ra); + noatomic_op(vs3, adjust_addr(env, addr), wd, i, env, ra); } clear_elem(vs3, env->vl, env->vl * esz, vlmax * esz); } --=20 2.25.1 From nobody Tue Feb 10 02:51:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636528324704524.0353770824177; Tue, 9 Nov 2021 23:12:04 -0800 (PST) Received: from localhost ([::1]:57488 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mkhm7-0003gH-JX for importer@patchew.org; Wed, 10 Nov 2021 02:12:03 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39120) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhkn-0000we-Rp; Wed, 10 Nov 2021 02:10:41 -0500 Received: from out28-217.mail.aliyun.com ([115.124.28.217]:41311) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhkk-0004ot-K4; Wed, 10 Nov 2021 02:10:41 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LqVKR1A_1636528233) by smtp.aliyun-inc.com(10.147.44.118); Wed, 10 Nov 2021 15:10:33 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07905654|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.45529-0.00118736-0.543523; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047206; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.LqVKR1A_1636528233; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 11/14] target/riscv: Adjust scalar reg in vector with XLEN Date: Wed, 10 Nov 2021 15:04:49 +0800 Message-Id: <20211110070452.48539-12-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211110070452.48539-1-zhiwei_liu@c-sky.com> References: <20211110070452.48539-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.217; envelope-from=zhiwei_liu@c-sky.com; helo=out28-217.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636528327903000001 Content-Type: text/plain; charset="utf-8" When sew <=3D 32bits, not need to extend scalar reg. When sew > 32bits, if xlen is less that sew, we should sign extend the scalar register, except explicitly specified by the spec. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvv.c.inc | 5 +++-- target/riscv/internals.h | 1 + target/riscv/vector_helper.c | 11 +++++++++-- 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 41c7c88904..0a956cac5b 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -846,7 +846,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint= 32_t vs2, uint32_t vm, dest =3D tcg_temp_new_ptr(); mask =3D tcg_temp_new_ptr(); src2 =3D tcg_temp_new_ptr(); - src1 =3D get_gpr(s, rs1, EXT_NONE); + src1 =3D get_gpr(s, rs1, EXT_SIGN); =20 data =3D FIELD_DP32(data, VDATA, MLEN, s->mlen); data =3D FIELD_DP32(data, VDATA, VM, vm); @@ -2670,6 +2670,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_= x *a) /* This instruction ignores LMUL and vector register groups */ int maxsz =3D s->vlen >> 3; TCGv_i64 t1; + TCGv src1 =3D get_gpr(s, a->rs1, EXT_ZERO); TCGLabel *over =3D gen_new_label(); =20 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); @@ -2679,7 +2680,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_= x *a) } =20 t1 =3D tcg_temp_new_i64(); - tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]); + tcg_gen_extu_tl_i64(t1, src1); vec_element_storei(s, a->rd, 0, t1); tcg_temp_free_i64(t1); done: diff --git a/target/riscv/internals.h b/target/riscv/internals.h index b15ad394bb..07e882160d 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -27,6 +27,7 @@ FIELD(VDATA, VM, 8, 1) FIELD(VDATA, LMUL, 9, 2) FIELD(VDATA, NF, 11, 4) FIELD(VDATA, WD, 11, 1) +FIELD(VDATA, TRUNC, 15, 1) =20 /* float point classify helpers */ target_ulong fclass_h(uint64_t frs1); diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 0b297f6bc8..51bcf63d65 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -112,6 +112,11 @@ static uint32_t vext_wd(uint32_t desc) return (simd_data(desc) >> 11) & 0x1; } =20 +static inline bool vext_trunc(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, TRUNC); +} + /* * Get vector group length in bytes. Its range is [64, 2048]. * @@ -4748,6 +4753,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ uint32_t mlen =3D vext_mlen(desc); = \ uint32_t vlmax =3D env_archcpu(env)->cfg.vlen / mlen; = \ uint32_t vm =3D vext_vm(desc); = \ + bool trunc =3D vext_trunc(desc); = \ uint32_t vl =3D env->vl; = \ uint32_t i; \ \ @@ -4756,7 +4762,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ continue; \ } \ if (i =3D=3D 0) { = \ - *((ETYPE *)vd + H(i)) =3D s1; = \ + *((ETYPE *)vd + H(i)) =3D trunc ? (s1 & UINT32_MAX) : s1; = \ } else { \ *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i - 1)); = \ } \ @@ -4777,6 +4783,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ uint32_t mlen =3D vext_mlen(desc); = \ uint32_t vlmax =3D env_archcpu(env)->cfg.vlen / mlen; = \ uint32_t vm =3D vext_vm(desc); = \ + bool trunc =3D vext_trunc(desc); = \ uint32_t vl =3D env->vl; = \ uint32_t i; \ \ @@ -4785,7 +4792,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ continue; \ } \ if (i =3D=3D vl - 1) { = \ - *((ETYPE *)vd + H(i)) =3D s1; = \ + *((ETYPE *)vd + H(i)) =3D trunc ? (s1 & UINT32_MAX) : s1; = \ } else { \ *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i + 1)); = \ } \ --=20 2.25.1 From nobody Tue Feb 10 02:51:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636528403377581.2120326993688; Tue, 9 Nov 2021 23:13:23 -0800 (PST) Received: from localhost ([::1]:60310 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mkhnO-0005aK-JZ for importer@patchew.org; Wed, 10 Nov 2021 02:13:22 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39214) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhlI-0002Dx-1d; Wed, 10 Nov 2021 02:11:12 -0500 Received: from out28-99.mail.aliyun.com ([115.124.28.99]:34714) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhlF-0004t4-Up; Wed, 10 Nov 2021 02:11:11 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LqV1pok_1636528264) by smtp.aliyun-inc.com(10.147.40.233); Wed, 10 Nov 2021 15:11:04 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07457498|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0446471-0.000322164-0.955031; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047194; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.LqV1pok_1636528264; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 12/14] target/riscv: Split out the vill from vtype Date: Wed, 10 Nov 2021 15:04:50 +0800 Message-Id: <20211110070452.48539-13-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211110070452.48539-1-zhiwei_liu@c-sky.com> References: <20211110070452.48539-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.99; envelope-from=zhiwei_liu@c-sky.com; helo=out28-99.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636528404723000001 Content-Type: text/plain; charset="utf-8" We need not specially process vtype when XLEN changes. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 1 + target/riscv/csr.c | 15 ++++++++++++++- target/riscv/machine.c | 1 + target/riscv/vector_helper.c | 7 ++----- 4 files changed, 18 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 73d7aa9ad7..e67531deab 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -121,6 +121,7 @@ struct CPURISCVState { target_ulong vl; target_ulong vstart; target_ulong vtype; + target_ulong vill; =20 target_ulong pc; target_ulong load_res; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 59e368f004..33e342f529 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -286,7 +286,20 @@ static RISCVException write_fcsr(CPURISCVState *env, i= nt csrno, static RISCVException read_vtype(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->vtype; + target_ulong vill; + switch (cpu_get_xl(env)) { + case MXL_RV32: + vill =3D env->vill << 31; + break; +#ifdef TARGET_RISCV64 + case MXL_RV64: + vill =3D env->vill << 63; + break; +#endif + default: + g_assert_not_reached(); + } + *val =3D vill | env->vtype; return RISCV_EXCP_NONE; } =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 19e982d3f0..cc4dda4b93 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -104,6 +104,7 @@ static const VMStateDescription vmstate_vector =3D { VMSTATE_UINTTL(env.vl, RISCVCPU), VMSTATE_UINTTL(env.vstart, RISCVCPU), VMSTATE_UINTTL(env.vtype, RISCVCPU), + VMSTATE_UINTTL(env.vill, RISCVCPU), VMSTATE_END_OF_LIST() } }; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 51bcf63d65..7d7b554789 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -45,11 +45,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_u= long s1, } if ((sew > cpu->cfg.elen) || vill || (ediv !=3D 0) || (reserved !=3D 0= )) { /* only set vill bit. */ - if (xlen < TARGET_LONG_BITS) { - env->vtype =3D FIELD_DP64(0, VTYPE, VILL_XLEN32, 1); - } else { - env->vtype =3D FIELD_DP64(0, VTYPE, VILL, 1); - } + env->vill =3D 1; + env->vtype =3D 0; env->vl =3D 0; env->vstart =3D 0; return 0; --=20 2.25.1 From nobody Tue Feb 10 02:51:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1636528558849737.9066944097459; Tue, 9 Nov 2021 23:15:58 -0800 (PST) Received: from localhost ([::1]:37584 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mkhpt-0000qS-G8 for importer@patchew.org; Wed, 10 Nov 2021 02:15:57 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39298) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhlm-0003NS-8D; Wed, 10 Nov 2021 02:11:42 -0500 Received: from out28-218.mail.aliyun.com ([115.124.28.218]:44258) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhlk-00054q-D1; Wed, 10 Nov 2021 02:11:41 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LqV7Wkb_1636528294) by smtp.aliyun-inc.com(10.147.42.135); Wed, 10 Nov 2021 15:11:35 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07454327|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0106131-0.000399075-0.988988; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047204; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.LqV7Wkb_1636528294; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 13/14] target/riscv: Don't save pc when exception return Date: Wed, 10 Nov 2021 15:04:51 +0800 Message-Id: <20211110070452.48539-14-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211110070452.48539-1-zhiwei_liu@c-sky.com> References: <20211110070452.48539-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.218; envelope-from=zhiwei_liu@c-sky.com; helo=out28-218.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636528561203000001 Content-Type: text/plain; charset="utf-8" As pc will be written by the xepc in exception return, just ignore pc in translation. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 4 ++-- target/riscv/insn_trans/trans_privileged.c.inc | 7 ++----- target/riscv/op_helper.c | 4 ++-- 3 files changed, 6 insertions(+), 9 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index e198d43981..a67965efe5 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -67,8 +67,8 @@ DEF_HELPER_2(csrr, tl, env, int) DEF_HELPER_3(csrw, void, env, int, tl) DEF_HELPER_4(csrrw, tl, env, int, tl, tl) #ifndef CONFIG_USER_ONLY -DEF_HELPER_2(sret, tl, env, tl) -DEF_HELPER_2(mret, tl, env, tl) +DEF_HELPER_1(sret, tl, env) +DEF_HELPER_1(mret, tl, env) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(tlb_flush, void, env) #endif diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index 75c6ef80a6..6077bbbf11 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -74,10 +74,8 @@ static bool trans_uret(DisasContext *ctx, arg_uret *a) static bool trans_sret(DisasContext *ctx, arg_sret *a) { #ifndef CONFIG_USER_ONLY - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - if (has_ext(ctx, RVS)) { - gen_helper_sret(cpu_pc, cpu_env, cpu_pc); + gen_helper_sret(cpu_pc, cpu_env); tcg_gen_exit_tb(NULL, 0); /* no chaining */ ctx->base.is_jmp =3D DISAS_NORETURN; } else { @@ -92,8 +90,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) static bool trans_mret(DisasContext *ctx, arg_mret *a) { #ifndef CONFIG_USER_ONLY - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - gen_helper_mret(cpu_pc, cpu_env, cpu_pc); + gen_helper_mret(cpu_pc, cpu_env); tcg_gen_exit_tb(NULL, 0); /* no chaining */ ctx->base.is_jmp =3D DISAS_NORETURN; return true; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index ee7c24efe7..095d39671b 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -71,7 +71,7 @@ target_ulong helper_csrrw(CPURISCVState *env, int csr, =20 #ifndef CONFIG_USER_ONLY =20 -target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) +target_ulong helper_sret(CPURISCVState *env) { uint64_t mstatus; target_ulong prev_priv, prev_virt; @@ -132,7 +132,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulo= ng cpu_pc_deb) return retpc; } =20 -target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) +target_ulong helper_mret(CPURISCVState *env) { if (!(env->priv >=3D PRV_M)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); --=20 2.25.1 From nobody Tue Feb 10 02:51:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 163652865669436.483761823163945; Tue, 9 Nov 2021 23:17:36 -0800 (PST) Received: from localhost ([::1]:41622 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mkhrT-0003ft-Ip for importer@patchew.org; Wed, 10 Nov 2021 02:17:35 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39500) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhmJ-0005PC-Ku; Wed, 10 Nov 2021 02:12:17 -0500 Received: from out28-171.mail.aliyun.com ([115.124.28.171]:45137) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkhmD-00059W-Vl; Wed, 10 Nov 2021 02:12:11 -0500 Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.LqU1dou_1636528325) by smtp.aliyun-inc.com(10.147.40.2); Wed, 10 Nov 2021 15:12:05 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.102711|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.00206744-0.000107588-0.997825; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047187; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.LqU1dou_1636528325; From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 14/14] target/riscv: Enable uxl field write Date: Wed, 10 Nov 2021 15:04:52 +0800 Message-Id: <20211110070452.48539-15-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211110070452.48539-1-zhiwei_liu@c-sky.com> References: <20211110070452.48539-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=115.124.28.171; envelope-from=zhiwei_liu@c-sky.com; helo=out28-171.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1636528657236000001 Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei --- target/riscv/csr.c | 5 ++--- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- target/riscv/op_helper.c | 3 ++- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 33e342f529..e07cd522ef 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -555,15 +555,14 @@ static RISCVException write_mstatus(CPURISCVState *en= v, int csrno, * RV32: MPV and GVA are not in mstatus. The current plan is to * add them to mstatush. For now, we just don't support it. */ - mask |=3D MSTATUS_MPV | MSTATUS_GVA; + mask |=3D MSTATUS_MPV | MSTATUS_GVA | MSTATUS64_UXL; } =20 mstatus =3D (mstatus & ~mask) | (val & mask); =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { - /* SXL and UXL fields are for now read only */ + /* SXL fields are for now read only */ mstatus =3D set_field(mstatus, MSTATUS64_SXL, MXL_RV64); - mstatus =3D set_field(mstatus, MSTATUS64_UXL, MXL_RV64); } env->mstatus =3D mstatus; =20 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 7a0b037594..cb73a2f1ee 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -472,7 +472,7 @@ static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a) return do_csrw(ctx, a->csr, src); } =20 - TCGv mask =3D tcg_constant_tl(-1); + TCGv mask =3D tcg_constant_tl(get_xl(ctx) =3D=3D MXL_RV32 ? UINT32_MAX= : -1); return do_csrrw(ctx, a->rd, a->csr, src, mask); } =20 @@ -523,7 +523,7 @@ static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi = *a) return do_csrw(ctx, a->csr, src); } =20 - TCGv mask =3D tcg_constant_tl(-1); + TCGv mask =3D tcg_constant_tl(get_xl(ctx) =3D=3D MXL_RV32 ? UINT32_MAX= : -1); return do_csrrw(ctx, a->rd, a->csr, src, mask); } =20 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 095d39671b..561e156bec 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -50,7 +50,8 @@ target_ulong helper_csrr(CPURISCVState *env, int csr) =20 void helper_csrw(CPURISCVState *env, int csr, target_ulong src) { - RISCVException ret =3D riscv_csrrw(env, csr, NULL, src, -1); + target_ulong mask =3D cpu_get_xl(env) =3D=3D MXL_RV32 ? UINT32_MAX : -= 1; + RISCVException ret =3D riscv_csrrw(env, csr, NULL, src, mask); =20 if (ret !=3D RISCV_EXCP_NONE) { riscv_raise_exception(env, ret, GETPC()); --=20 2.25.1