target/mips: Fix Loongson-3A4000 MSAIR config register

[PATCH v2] target/mips: Fix Loongson-3A4000 MSAIR config register

Posted by Philippe Mathieu-Daudé 2 years, 6 months ago

When using the Loongson-3A4000 CPU, the MSAIR is returned with a
zero value (because unimplemented). Checking on real hardware,
this value appears incorrect:

  $ cat /proc/cpuinfo
  system type     : generic-loongson-machine
  machine         : loongson,generic
  cpu model       : Loongson-3 V0.4  FPU V0.1
  model name      : Loongson-3A R4 (Loongson-3A4000) @ 1800MHz
  isa             : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2
  ASEs implemented        : vz msa loongson-mmi loongson-cam loongson-ext loongson-ext2
  ...

Checking the CFCMSA opcode result with gdb we get 0x60140:

  Breakpoint 1, 0x00000001200037c4 in main ()
  1: x/i $pc
  => 0x1200037c4 <main+52>:  cfcmsa       v0,msa_ir
  (gdb) si
  0x00000001200037c8 in main ()
  (gdb) i r v0
  v0: 0x60140

MSAIR bits 17 and 18 are "reserved" per the spec revision 1.12,
so mask them out, and set MSAIR=0x0140 for the Loongson-3A4000
CPU model added in commit af868995e1b.

Cc: Huacai Chen <chenhuacai@kernel.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2: Mask out bits 17/18
---
 target/mips/cpu-defs.c.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index cbc45fcb0e8..ee8b322a564 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -886,6 +886,7 @@ const mips_def_t mips_defs[] =
                     (0x1 << FCR0_D) | (0x1 << FCR0_S),
         .CP1_fcr31 = 0,
         .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
+        .MSAIR = (0x01 << MSAIR_ProcID) | (0x40 << MSAIR_Rev),
         .SEGBITS = 48,
         .PABITS = 48,
         .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
-- 
2.31.1

Re: [PATCH v2] target/mips: Fix Loongson-3A4000 MSAIR config register

Posted by Philippe Mathieu-Daudé 2 years, 6 months ago

On 10/26/21 20:09, Philippe Mathieu-Daudé wrote:
> When using the Loongson-3A4000 CPU, the MSAIR is returned with a
> zero value (because unimplemented). Checking on real hardware,
> this value appears incorrect:
> 
>   $ cat /proc/cpuinfo
>   system type     : generic-loongson-machine
>   machine         : loongson,generic
>   cpu model       : Loongson-3 V0.4  FPU V0.1
>   model name      : Loongson-3A R4 (Loongson-3A4000) @ 1800MHz
>   isa             : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2
>   ASEs implemented        : vz msa loongson-mmi loongson-cam loongson-ext loongson-ext2
>   ...
> 
> Checking the CFCMSA opcode result with gdb we get 0x60140:
> 
>   Breakpoint 1, 0x00000001200037c4 in main ()
>   1: x/i $pc
>   => 0x1200037c4 <main+52>:  cfcmsa       v0,msa_ir
>   (gdb) si
>   0x00000001200037c8 in main ()
>   (gdb) i r v0
>   v0: 0x60140
> 
> MSAIR bits 17 and 18 are "reserved" per the spec revision 1.12,
> so mask them out, and set MSAIR=0x0140 for the Loongson-3A4000
> CPU model added in commit af868995e1b.
> 
> Cc: Huacai Chen <chenhuacai@kernel.org>
> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> v2: Mask out bits 17/18
> ---
>  target/mips/cpu-defs.c.inc | 1 +
>  1 file changed, 1 insertion(+)

Thanks, applied to mips-next.