Series comparison

-[PULL 00/33] riscv-to-apply queue
+[PULL 00/28] riscv-to-apply queue
-From: Alistair Francis <alistair.francis@wdc.com>
+The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:
-The following changes since commit 4c127fdbe81d66e7cafed90908d0fd1f6f2a6cd0:
+  Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)
   Merge remote-tracking branch 'remotes/rth/tags/pull-arm-20211021' into staging (2021-10-21 09:53:27 -0700)
 are available in the Git repository at:
-  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211022-2
+  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528
-for you to fetch changes up to 11ec06f9eaedc801ded34c79861367b76ab2b731:
+for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:
-  hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id (2021-10-22 23:35:47 +1000)
+  target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)
 ----------------------------------------------------------------
-Fourth RISC-V PR for QEMU 6.2
+RISC-V PR for 9.1
- - Vector extension bug fixes
+* APLICs add child earlier than realize
- - Bit manipulation extension bug fix
+* Fix exposure of Zkr
- - Support vhost-user and numa mem options on all boards
+* Raise exceptions on wrs.nto
- - Rationalise XLEN and operand lengths
+* Implement SBI debug console (DBCN) calls for KVM
- - Bump the OpenTitan FPGA support
+* Support 64-bit addresses for initrd
- - Remove the Ibex PLIC
+* Change RISCV_EXCP_SEMIHOST exception number to 63
- - General code cleanup
+* Tolerate KVM disable ext errors
 * Set tval in breakpoints
 * Add support for Zve32x extension
 * Add support for Zve64x extension
 * Relax vector register check in RISCV gdbstub
 * Fix the element agnostic Vector function problem
 * Fix Zvkb extension config
 * Implement dynamic establishment of custom decoder
 * Add th.sxstatus CSR emulation
 * Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
 * Check single width operator for vector fp widen instructions
 * Check single width operator for vfncvt.rod.f.f.w
 * Remove redudant SEW checking for vector fp narrow/widen instructions
 * Prioritize pmp errors in raise_mmu_exception()
 * Do not set mtval2 for non guest-page faults
 * Remove experimental prefix from "B" extension
 * Fixup CBO extension register calculation
 * Fix the hart bit setting of AIA
 * Fix reg_width in ricsv_gen_dynamic_vector_feature()
 * Decode all of the pmpcfg and pmpaddr CSRs
 * Raise an exception when CSRRS/CSRRC writes a read-only CSR
 ----------------------------------------------------------------
-Alistair Francis (7):
+Alexei Filippov (1):
-      target/riscv: Remove some unused macros
+      target/riscv: do not set mtval2 for non guest-page faults
       target/riscv: Organise the CPU properties
       hw/riscv: opentitan: Update to the latest build
       hw/intc: Remove the Ibex PLIC
       hw/intc: sifive_plic: Move the properties
       hw/intc: sifive_plic: Cleanup the realize function
       hw/intc: sifive_plic: Cleanup the irq_request function
-Bin Meng (6):
+Alistair Francis (2):
-      hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
+      target/riscv: rvzicbo: Fixup CBO extension register calculation
-      hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
+      disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
       hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id
       hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
       hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id
       hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id
-Frank Chang (2):
+Andrew Jones (2):
-      target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v
+      target/riscv/kvm: Fix exposure of Zkr
-      target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
+      target/riscv: Raise exceptions on wrs.nto
-Mingwang Li (1):
+Cheng Yang (1):
-      hw/riscv: virt: Use machine->ram as the system memory
+      hw/riscv/boot.c: Support 64-bit address for initrd
-Philipp Tomsich (1):
+Christoph Müllner (1):
-      target/riscv: Fix orc.b implementation
+      riscv: thead: Add th.sxstatus CSR emulation
-Richard Henderson (15):
+Clément Léger (1):
-      target/riscv: Move cpu_get_tb_cpu_state out of line
+      target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
       target/riscv: Create RISCVMXL enumeration
       target/riscv: Split misa.mxl and misa.ext
       target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
       target/riscv: Add MXL/SXL/UXL to TB_FLAGS
       target/riscv: Use REQUIRE_64BIT in amo_check64
       target/riscv: Properly check SEW in amo_op
       target/riscv: Replace is_32bit with get_xl/get_xlen
       target/riscv: Replace DisasContext.w with DisasContext.ol
       target/riscv: Use gen_arith_per_ol for RVM
       target/riscv: Adjust trans_rev8_32 for riscv64
       target/riscv: Use gen_unary_per_ol for RVB
       target/riscv: Use gen_shift*_per_ol for RVB, RVI
       target/riscv: Use riscv_csrrw_debug for cpu_dump
       target/riscv: Compute mstatus.sd on demand
-Travis Geiselbrecht (1):
+Daniel Henrique Barboza (6):
-      target/riscv: line up all of the registers in the info register dump
+      target/riscv/kvm: implement SBI debug console (DBCN) calls
       target/riscv/kvm: tolerate KVM disable ext errors
       target/riscv/debug: set tval=pc in breakpoint exceptions
       trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
       target/riscv: prioritize pmp errors in raise_mmu_exception()
       riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
- include/hw/riscv/opentitan.h            |   6 +-
+Huang Tao (2):
- target/riscv/cpu.h                      |  87 +++------
+      target/riscv: Fix the element agnostic function problem
- target/riscv/cpu_bits.h                 |  16 +-
+      target/riscv: Implement dynamic establishment of custom decoder
  hw/intc/ibex_plic.c                     | 307 --------------------------------
  hw/intc/sifive_plic.c                   |  85 ++++-----
  hw/riscv/boot.c                         |   2 +-
  hw/riscv/microchip_pfsoc.c              |  36 ++--
  hw/riscv/opentitan.c                    |  38 +++-
  hw/riscv/shakti_c.c                     |   6 +-
  hw/riscv/sifive_e.c                     |  16 +-
  hw/riscv/sifive_u.c                     |   6 +-
  hw/riscv/spike.c                        |   6 +-
  hw/riscv/virt.c                         |   6 +-
  linux-user/elfload.c                    |   2 +-
  linux-user/riscv/cpu_loop.c             |   2 +-
  semihosting/arm-compat-semi.c           |   2 +-
  target/riscv/cpu.c                      | 216 ++++++++++++----------
  target/riscv/cpu_helper.c               |  92 +++++++++-
  target/riscv/csr.c                      | 104 ++++++-----
  target/riscv/gdbstub.c                  |  10 +-
  target/riscv/machine.c                  |  10 +-
  target/riscv/monitor.c                  |   4 +-
  target/riscv/translate.c                | 174 +++++++++++++-----
  target/riscv/insn_trans/trans_rvb.c.inc | 153 +++++++++-------
  target/riscv/insn_trans/trans_rvi.c.inc |  44 ++---
  target/riscv/insn_trans/trans_rvm.c.inc |  36 +++-
  target/riscv/insn_trans/trans_rvv.c.inc |  32 ++--
  hw/intc/meson.build                     |   1 -
 files changed, 720 insertions(+), 779 deletions(-)
  delete mode 100644 hw/intc/ibex_plic.c
+Jason Chien (3):
+      target/riscv: Add support for Zve32x extension
+      target/riscv: Add support for Zve64x extension
+      target/riscv: Relax vector register check in RISCV gdbstub
+Max Chou (4):
+      target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
+      target/riscv: rvv: Check single width operator for vector fp widen instructions
+      target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
+      target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
+Rob Bradford (1):
+      target/riscv: Remove experimental prefix from "B" extension
+Yangyu Chen (1):
+      target/riscv/cpu.c: fix Zvkb extension config
+Yong-Xuan Wang (1):
+      target/riscv/kvm.c: Fix the hart bit setting of AIA
+Yu-Ming Chang (1):
+      target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
+yang.zhang (1):
+      hw/intc/riscv_aplic: APLICs should add child earlier than realize
+ MAINTAINERS                                    |   1 +
+ target/riscv/cpu.h                             |  11 ++
+ target/riscv/cpu_bits.h                        |   2 +-
+ target/riscv/cpu_cfg.h                         |   2 +
+ target/riscv/helper.h                          |   1 +
+ target/riscv/sbi_ecall_interface.h             |  17 +++
+ target/riscv/tcg/tcg-cpu.h                     |  15 +++
+ disas/riscv.c                                  |  65 +++++++++-
+ hw/intc/riscv_aplic.c                          |   8 +-
+ hw/riscv/boot.c                                |   4 +-
+ target/riscv/cpu.c                             |  10 +-
+ target/riscv/cpu_helper.c                      |  37 +++---
+ target/riscv/csr.c                             |  71 +++++++++--
+ target/riscv/debug.c                           |   3 +
+ target/riscv/gdbstub.c                         |   8 +-
+ target/riscv/kvm/kvm-cpu.c                     | 157 ++++++++++++++++++++++++-
+ target/riscv/op_helper.c                       |  17 ++-
+ target/riscv/tcg/tcg-cpu.c                     |  50 +++++---
+ target/riscv/th_csr.c                          |  79 +++++++++++++
+ target/riscv/translate.c                       |  31 +++--
+ target/riscv/vector_internals.c                |  22 ++++
+ target/riscv/insn_trans/trans_privileged.c.inc |   2 +
+ target/riscv/insn_trans/trans_rvv.c.inc        |  46 +++++---
+ target/riscv/insn_trans/trans_rvzawrs.c.inc    |  29 +++--
+ target/riscv/insn_trans/trans_rvzicbo.c.inc    |  16 ++-
+ target/riscv/meson.build                       |   1 +
+files changed, 596 insertions(+), 109 deletions(-)
+ create mode 100644 target/riscv/th_csr.c

-[PULL 33/33] hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id
+[PULL 01/28] hw/intc/riscv_aplic: APLICs should add child earlier than realize
-From: Bin Meng <bmeng.cn@gmail.com>
+From: "yang.zhang" <yang.zhang@hexintek.com>
-Using memory_region_init_ram(), which can't possibly handle vhost-user,
+Since only root APLICs can have hw IRQ lines, aplic->parent should
-and can't work as expected with '-numa node,memdev' options.
+be initialized first.
-Use MachineState::ram instead of manually initializing RAM memory
+Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
-region, as well as by providing MachineClass::default_ram_id to
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-opt in to memdev scheme.
+Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
+Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Igor Mammedov <imammedo@redhat.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20211020014112.7336-7-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/spike.c | 6 ++----
+ hw/intc/riscv_aplic.c | 8 ++++----
-file changed, 2 insertions(+), 4 deletions(-)
+file changed, 4 insertions(+), 4 deletions(-)
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
+diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/spike.c
+--- a/hw/intc/riscv_aplic.c
-+++ b/hw/riscv/spike.c
++++ b/hw/intc/riscv_aplic.c
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
-     const MemMapEntry *memmap = spike_memmap;
+     qdev_prop_set_bit(dev, "msimode", msimode);
-     SpikeState *s = SPIKE_MACHINE(machine);
+     qdev_prop_set_bit(dev, "mmode", mmode);
-     MemoryRegion *system_memory = get_system_memory();
--    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
++    if (parent) {
-     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
++        riscv_aplic_add_child(parent, dev);
-     target_ulong firmware_end_addr, kernel_start_addr;
++    }
-     uint32_t fdt_load_addr;
++
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
+     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
      if (!is_kvm_aia(msimode)) {
          sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
      }
-     /* register system main memory (actual RAM) */
+-    if (parent) {
--    memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
+-        riscv_aplic_add_child(parent, dev);
--                           machine->ram_size, &error_fatal);
+-    }
-     memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
+-
--        main_mem);
+     if (!msimode) {
-+        machine->ram);
+         for (i = 0; i < num_harts; i++) {
+             CPUState *cpu = cpu_by_arch_id(hartid_base + i);
      /* create device tree */
      create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
@@ -XXX,XX +XXX,XX @@ static void spike_machine_class_init(ObjectClass *oc, void *data)
      mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
      mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
      mc->numa_mem_supported = true;
 +    mc->default_ram_id = "riscv.spike.ram";
  }
  static const TypeInfo spike_machine_typeinfo = {
 --
-.31.1
+.45.1

-[PULL 05/33] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
+[PULL 02/28] target/riscv/kvm: Fix exposure of Zkr
-From: Frank Chang <frank.chang@sifive.com>
+From: Andrew Jones <ajones@ventanamicro.com>
-TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
+The Zkr extension may only be exposed to KVM guests if the VMM
-commit: c445593, but other TB_FLAGS bits for rvv and rvh were
+implements the SEED CSR. Use the same implementation as TCG.
 not shift as well so these bits may overlap with each other when
 rvv is enabled.
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Without this patch, running with a KVM which does not forward the
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+SEED CSR access to QEMU will result in an ILL exception being
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+injected into the guest (this results in Linux guests crashing on
-Message-Id: <20211015074627.3957162-2-frank.chang@sifive.com>
+boot). And, when running with a KVM which does forward the access,
 QEMU will crash, since QEMU doesn't know what to do with the exit.
 Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
 Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h       | 14 +++++++-------
+ target/riscv/cpu.h         |  3 +++
- target/riscv/translate.c |  2 +-
+ target/riscv/csr.c         | 18 ++++++++++++++----
-files changed, 8 insertions(+), 8 deletions(-)
+ target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
 files changed, 42 insertions(+), 4 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
+@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
- target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
- void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
+ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
--#define TB_FLAGS_MMU_MASK   7
++target_ulong riscv_new_csr_seed(target_ulong new_value,
- #define TB_FLAGS_PRIV_MMU_MASK                3
++                                target_ulong write_mask);
- #define TB_FLAGS_PRIV_HYP_ACCESS_MASK   (1 << 2)
++
- #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
+ uint8_t satp_mode_max_from_map(uint32_t map);
-@@ -XXX,XX +XXX,XX @@ typedef CPURISCVState CPUArchState;
+ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
- typedef RISCVCPU ArchCPU;
- #include "exec/cpu-all.h"
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 -FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1)
 -FIELD(TB_FLAGS, LMUL, 3, 2)
 -FIELD(TB_FLAGS, SEW, 5, 3)
 -FIELD(TB_FLAGS, VILL, 8, 1)
 +FIELD(TB_FLAGS, MEM_IDX, 0, 3)
 +FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
 +FIELD(TB_FLAGS, LMUL, 4, 2)
 +FIELD(TB_FLAGS, SEW, 6, 3)
 +FIELD(TB_FLAGS, VILL, 9, 1)
  /* Is a Hypervisor instruction load/store allowed? */
 -FIELD(TB_FLAGS, HLSX, 9, 1)
 -FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2)
 +FIELD(TB_FLAGS, HLSX, 10, 1)
 +FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2)
  bool riscv_cpu_is_32bit(CPURISCVState *env);
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/csr.c
-+++ b/target/riscv/translate.c
++++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
-     uint32_t tb_flags = ctx->base.tb->flags;
+ #endif
-     ctx->pc_succ_insn = ctx->base.pc_first;
+ /* Crypto Extension */
--    ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK;
+-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
-+    ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
+-                               target_ulong *ret_value,
-     ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
+-                               target_ulong new_value,
-     ctx->priv_ver = env->priv_ver;
+-                               target_ulong write_mask)
- #if !defined(CONFIG_USER_ONLY)
++target_ulong riscv_new_csr_seed(target_ulong new_value,
 +                                target_ulong write_mask)
  {
      uint16_t random_v;
      Error *random_e = NULL;
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
          rval = random_v | SEED_OPST_ES16;
      }
 +    return rval;
 +}
 +
 +static RISCVException rmw_seed(CPURISCVState *env, int csrno,
 +                               target_ulong *ret_value,
 +                               target_ulong new_value,
 +                               target_ulong write_mask)
 +{
 +    target_ulong rval;
 +
 +    rval = riscv_new_csr_seed(new_value, write_mask);
 +
      if (ret_value) {
          *ret_value = rval;
      }
 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm/kvm-cpu.c
 +++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
      return ret;
  }
 +static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
 +{
 +    target_ulong csr_num = run->riscv_csr.csr_num;
 +    target_ulong new_value = run->riscv_csr.new_value;
 +    target_ulong write_mask = run->riscv_csr.write_mask;
 +    int ret = 0;
 +
 +    switch (csr_num) {
 +    case CSR_SEED:
 +        run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
 +        break;
 +    default:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "%s: un-handled CSR EXIT for CSR %lx\n",
 +                      __func__, csr_num);
 +        ret = -1;
 +        break;
 +    }
 +
 +    return ret;
 +}
 +
  int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
  {
      int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
      case KVM_EXIT_RISCV_SBI:
          ret = kvm_riscv_handle_sbi(cs, run);
          break;
 +    case KVM_EXIT_RISCV_CSR:
 +        ret = kvm_riscv_handle_csr(cs, run);
 +        break;
      default:
          qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
                        __func__, run->exit_reason);
 --
-.31.1
+.45.1

-[PULL 18/33] target/riscv: Adjust trans_rev8_32 for riscv64
+[PULL 03/28] target/riscv: Raise exceptions on wrs.nto
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Andrew Jones <ajones@ventanamicro.com>
-When target_long is 64-bit, we still want a 32-bit bswap for rev8.
+Implementing wrs.nto to always just return is consistent with the
-Since this opcode is specific to RV32, we need not conditionalize.
+specification, as the instruction is permitted to terminate the
 stall for any reason, but it's not useful for virtualization, where
 we'd like the guest to trap to the hypervisor in order to allow
 scheduling of the lock holding VCPU. Change to always immediately
 raise exceptions when the appropriate conditions are present,
 otherwise continue to just return. Note, immediately raising
 exceptions is also consistent with the specification since the
 time limit that should expire prior to the exception is
 implementation-specific.
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
-Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Message-id: 20211020031709.359469-12-richard.henderson@linaro.org
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvb.c.inc | 7 ++++++-
+ target/riscv/helper.h                       |  1 +
-file changed, 6 insertions(+), 1 deletion(-)
+ target/riscv/op_helper.c                    | 11 ++++++++
  target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
 files changed, 32 insertions(+), 9 deletions(-)
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
+diff --git a/target/riscv/helper.h b/target/riscv/helper.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
+--- a/target/riscv/helper.h
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
++++ b/target/riscv/helper.h
-@@ -XXX,XX +XXX,XX @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
-     return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
+ DEF_HELPER_1(sret, tl, env)
  DEF_HELPER_1(mret, tl, env)
  DEF_HELPER_1(wfi, void, env)
 +DEF_HELPER_1(wrs_nto, void, env)
  DEF_HELPER_1(tlb_flush, void, env)
  DEF_HELPER_1(tlb_flush_all, void, env)
  /* Native Debug */
 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/op_helper.c
 +++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
      }
  }
-+static void gen_rev8_32(TCGv ret, TCGv src1)
++void helper_wrs_nto(CPURISCVState *env)
 +{
-+    tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS);
++    if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
 +        get_field(env->hstatus, HSTATUS_VTW) &&
 +        !get_field(env->mstatus, MSTATUS_TW)) {
 +        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
 +    } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
 +        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
 +    }
 +}
 +
- static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
+ void helper_tlb_flush(CPURISCVState *env)
  {
-     REQUIRE_32BIT(ctx);
+     CPUState *cs = env_cpu(env);
-     REQUIRE_ZBB(ctx);
+diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
--    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
+index XXXXXXX..XXXXXXX 100644
-+    return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
+--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
 +++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
@@ -XXX,XX +XXX,XX @@
   * this program.  If not, see <http://www.gnu.org/licenses/>.
   */
 -static bool trans_wrs(DisasContext *ctx)
 +static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
  {
      if (!ctx->cfg_ptr->ext_zawrs) {
          return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
      return true;
  }
- static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
+-#define GEN_TRANS_WRS(insn)                                     \
 -static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
 -{                                                               \
 -    (void)a;                                                    \
 -    return trans_wrs(ctx);                                      \
 -}
 +static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
 +{
 +    if (!ctx->cfg_ptr->ext_zawrs) {
 +        return false;
 +    }
 -GEN_TRANS_WRS(wrs_nto)
 -GEN_TRANS_WRS(wrs_sto)
 +    /*
 +     * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
 +     * should raise an exception when the implementation-specific bounded time
 +     * limit has expired. Our time limit is zero, so we either return
 +     * immediately, as does our implementation of wrs.sto, or raise an
 +     * exception, as handled by the wrs.nto helper.
 +     */
 +#ifndef CONFIG_USER_ONLY
 +    gen_helper_wrs_nto(tcg_env);
 +#endif
 +
 +    /* We only get here when helper_wrs_nto() doesn't raise an exception. */
 +    return trans_wrs_sto(ctx, NULL);
 +}
 --
-.31.1
+.45.1

-[PULL 19/33] target/riscv: Use gen_unary_per_ol for RVB
+[PULL 04/28] target/riscv/kvm: implement SBI debug console (DBCN) calls
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-The count zeros instructions require a separate implementation
+SBI defines a Debug Console extension "DBCN" that will, in time, replace
-for RV32 when TARGET_LONG_BITS == 64.
+the legacy console putchar and getchar SBI extensions.
-Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+The appeal of the DBCN extension is that it allows multiple bytes to be
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+read/written in the SBI console in a single SBI call.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20211020031709.359469-13-richard.henderson@linaro.org
+As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
 module to userspace. But this will only happens if the KVM module
 actually supports this SBI extension and we activate it.
 We'll check for DBCN support during init time, checking if get-reg-list
 is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
 kvm_set_one_reg() during kvm_arch_init_vcpu().
 Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
 SBI_EXT_DBCN, reading and writing as required.
 A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
 host, takes around 20 seconds to boot without using DBCN. With this
 patch we're taking around 14 seconds to boot due to the speed-up in the
 terminal output.  There's no change in boot time if the guest isn't
 using earlycon.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c                | 16 ++++++++++++
+ target/riscv/sbi_ecall_interface.h |  17 +++++
- target/riscv/insn_trans/trans_rvb.c.inc | 33 ++++++++++++-------------
+ target/riscv/kvm/kvm-cpu.c         | 111 +++++++++++++++++++++++++++++
-files changed, 32 insertions(+), 17 deletions(-)
+files changed, 128 insertions(+)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/sbi_ecall_interface.h
-+++ b/target/riscv/translate.c
++++ b/target/riscv/sbi_ecall_interface.h
-@@ -XXX,XX +XXX,XX @@ static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
+@@ -XXX,XX +XXX,XX @@
  /* clang-format off */
 +#define SBI_SUCCESS                      0
 +#define SBI_ERR_FAILED                  -1
 +#define SBI_ERR_NOT_SUPPORTED           -2
 +#define SBI_ERR_INVALID_PARAM           -3
 +#define SBI_ERR_DENIED                  -4
 +#define SBI_ERR_INVALID_ADDRESS         -5
 +#define SBI_ERR_ALREADY_AVAILABLE       -6
 +#define SBI_ERR_ALREADY_STARTED         -7
 +#define SBI_ERR_ALREADY_STOPPED         -8
 +#define SBI_ERR_NO_SHMEM                -9
 +
  /* SBI Extension IDs */
  #define SBI_EXT_0_1_SET_TIMER           0x0
  #define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
@@ -XXX,XX +XXX,XX @@
  #define SBI_EXT_IPI                     0x735049
  #define SBI_EXT_RFENCE                  0x52464E43
  #define SBI_EXT_HSM                     0x48534D
 +#define SBI_EXT_DBCN                    0x4442434E
  /* SBI function IDs for BASE extension */
  #define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
@@ -XXX,XX +XXX,XX @@
  #define SBI_EXT_HSM_HART_STOP           0x1
  #define SBI_EXT_HSM_HART_GET_STATUS     0x2
 +/* SBI function IDs for DBCN extension */
 +#define SBI_EXT_DBCN_CONSOLE_WRITE      0x0
 +#define SBI_EXT_DBCN_CONSOLE_READ       0x1
 +#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
 +
  #define SBI_HSM_HART_STATUS_STARTED     0x0
  #define SBI_HSM_HART_STATUS_STOPPED     0x1
  #define SBI_HSM_HART_STATUS_START_PENDING   0x2
 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm/kvm-cpu.c
 +++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
                     KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
  };
 +static KVMCPUConfig kvm_sbi_dbcn = {
 +    .name = "sbi_dbcn",
 +    .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
 +                  KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
 +};
 +
  static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
  {
      CPURISCVState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
      return 0;
  }
 +static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
 +                                             KVMScratchCPU *kvmcpu,
 +                                             struct kvm_reg_list *reglist)
 +{
 +    struct kvm_reg_list *reg_search;
 +
 +    reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
 +                         sizeof(uint64_t), uint64_cmp);
 +
 +    if (reg_search) {
 +        kvm_sbi_dbcn.supported = true;
 +    }
 +}
 +
  static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
                                   struct kvm_reg_list *reglist)
  {
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
      if (riscv_has_ext(&cpu->env, RVV)) {
          kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
      }
 +
 +    kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
  }
  static void riscv_init_kvm_registers(Object *cpu_obj)
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
      return ret;
  }
 +static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
 +{
 +    target_ulong reg = 1;
 +
 +    if (!kvm_sbi_dbcn.supported) {
 +        return 0;
 +    }
 +
 +    return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
 +}
 +
  int kvm_arch_init_vcpu(CPUState *cs)
  {
      int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
      kvm_riscv_update_cpu_misa_ext(cpu, cs);
      kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
 +    ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
 +
      return ret;
  }
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
      return true;
  }
-+static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
++static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
 +                             void (*f_tl)(TCGv, TCGv),
 +                             void (*f_32)(TCGv, TCGv))
 +{
-+    int olen = get_olen(ctx);
++    g_autofree uint8_t *buf = NULL;
-+
++    RISCVCPU *cpu = RISCV_CPU(cs);
-+    if (olen != TARGET_LONG_BITS) {
++    target_ulong num_bytes;
-+        if (olen == 32) {
++    uint64_t addr;
-+            f_tl = f_32;
++    unsigned char ch;
 +    int ret;
 +
 +    switch (run->riscv_sbi.function_id) {
 +    case SBI_EXT_DBCN_CONSOLE_READ:
 +    case SBI_EXT_DBCN_CONSOLE_WRITE:
 +        num_bytes = run->riscv_sbi.args[0];
 +
 +        if (num_bytes == 0) {
 +            run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +            run->riscv_sbi.ret[1] = 0;
 +            break;
 +        }
 +
 +        addr = run->riscv_sbi.args[1];
 +
 +        /*
 +         * Handle the case where a 32 bit CPU is running in a
 +         * 64 bit addressing env.
 +         */
 +        if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
 +            addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
 +        }
 +
 +        buf = g_malloc0(num_bytes);
 +
 +        if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
 +            ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
 +            if (ret < 0) {
 +                error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
 +                             "reading chardev");
 +                exit(1);
 +            }
 +
 +            cpu_physical_memory_write(addr, buf, ret);
 +        } else {
-+            g_assert_not_reached();
++            cpu_physical_memory_read(addr, buf, num_bytes);
-+        }
++
 +            ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
 +            if (ret < 0) {
 +                error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
 +                             "writing chardev");
 +                exit(1);
 +            }
 +        }
 +
 +        run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +        run->riscv_sbi.ret[1] = ret;
 +        break;
 +    case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
 +        ch = run->riscv_sbi.args[0];
 +        ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
 +
 +        if (ret < 0) {
 +            error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
 +                         "writing chardev");
 +            exit(1);
 +        }
 +
 +        run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +        run->riscv_sbi.ret[1] = 0;
 +        break;
 +    default:
 +        run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
 +    }
-+    return gen_unary(ctx, a, ext, f_tl);
 +}
 +
- static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
+ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
  {
-     DisasContext *ctx = container_of(dcbase, DisasContext, base);
+     int ret = 0;
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
+@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
-index XXXXXXX..XXXXXXX 100644
+         }
---- a/target/riscv/insn_trans/trans_rvb.c.inc
+         ret = 0;
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
+         break;
-@@ -XXX,XX +XXX,XX @@ static void gen_clz(TCGv ret, TCGv arg1)
++    case SBI_EXT_DBCN:
-     tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
++        kvm_riscv_handle_sbi_dbcn(cs, run);
- }
++        break;
+     default:
-+static void gen_clzw(TCGv ret, TCGv arg1)
+         qemu_log_mask(LOG_UNIMP,
-+{
+                       "%s: un-handled SBI EXIT, specific reasons is %lu\n",
 +    TCGv t = tcg_temp_new();
 +    tcg_gen_shli_tl(t, arg1, 32);
 +    tcg_gen_clzi_tl(ret, t, 32);
 +    tcg_temp_free(t);
 +}
 +
  static bool trans_clz(DisasContext *ctx, arg_clz *a)
  {
      REQUIRE_ZBB(ctx);
 -    return gen_unary(ctx, a, EXT_ZERO, gen_clz);
 +    return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw);
  }
  static void gen_ctz(TCGv ret, TCGv arg1)
@@ -XXX,XX +XXX,XX @@ static void gen_ctz(TCGv ret, TCGv arg1)
      tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
  }
 +static void gen_ctzw(TCGv ret, TCGv arg1)
 +{
 +    tcg_gen_ctzi_tl(ret, arg1, 32);
 +}
 +
  static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
  {
      REQUIRE_ZBB(ctx);
 -    return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
 +    return gen_unary_per_ol(ctx, a, EXT_ZERO, gen_ctz, gen_ctzw);
  }
  static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a)
      return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
  }
 -static void gen_clzw(TCGv ret, TCGv arg1)
 -{
 -    TCGv t = tcg_temp_new();
 -    tcg_gen_shli_tl(t, arg1, 32);
 -    tcg_gen_clzi_tl(ret, t, 32);
 -    tcg_temp_free(t);
 -}
 -
  static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
  {
      REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
      return gen_unary(ctx, a, EXT_NONE, gen_clzw);
  }
 -static void gen_ctzw(TCGv ret, TCGv arg1)
 -{
 -    tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
 -    tcg_gen_ctzi_tl(ret, ret, 64);
 -}
 -
  static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_ZBB(ctx);
 -    return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
 +    return gen_unary(ctx, a, EXT_ZERO, gen_ctzw);
  }
  static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
 --
-.31.1
+.45.1

-[PULL 27/33] hw/intc: sifive_plic: Cleanup the irq_request function
+[PULL 05/28] hw/riscv/boot.c: Support 64-bit address for initrd
-From: Alistair Francis <alistair.francis@wdc.com>
+From: Cheng Yang <yangcheng.work@foxmail.com>
+Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
+to set the address of initrd in FDT to support 64-bit address.
+Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Message-id: 4200da222a65c89ed1ba35f754dcca7fdd9f08d6.1634524691.git.alistair.francis@wdc.com
 ---
- hw/intc/sifive_plic.c | 10 ++++------
+ hw/riscv/boot.c | 4 ++--
-file changed, 4 insertions(+), 6 deletions(-)
+file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
+diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/sifive_plic.c
+--- a/hw/riscv/boot.c
-+++ b/hw/intc/sifive_plic.c
++++ b/hw/riscv/boot.c
-@@ -XXX,XX +XXX,XX @@ static void parse_hart_config(SiFivePLICState *plic)
+@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
+     /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
- static void sifive_plic_irq_request(void *opaque, int irq, int level)
+     if (fdt) {
- {
+         end = start + size;
--    SiFivePLICState *plic = opaque;
+-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
--    if (RISCV_DEBUG_PLIC) {
+-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
--        qemu_log("sifive_plic_irq_request: irq=%d level=%d\n", irq, level);
++        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
--    }
++        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
--    sifive_plic_set_pending(plic, irq, level > 0);
+     }
 -    sifive_plic_update(plic);
 +    SiFivePLICState *s = opaque;
 +
 +    sifive_plic_set_pending(s, irq, level > 0);
 +    sifive_plic_update(s);
  }
- static void sifive_plic_realize(DeviceState *dev, Error **errp)
 --
-.31.1
+.45.1

-[PULL 09/33] target/riscv: Create RISCVMXL enumeration
+[PULL 06/28] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Clément Léger <cleger@rivosinc.com>
-Move the MXL_RV* defines to enumerators.
+The current semihost exception number (16) is a reserved number (range
 [16-17]). The upcoming double trap specification uses that number for
 the double trap exception. Since the privileged spec (Table 22) defines
 ranges for custom uses change the semihosting exception number to 63
 which belongs to the range [48-63] in order to avoid any future
 collisions with reserved exception.
-Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Signed-off-by: Clément Léger <cleger@rivosinc.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
 Message-id: 20211020031709.359469-3-richard.henderson@linaro.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_bits.h | 8 +++++---
+ target/riscv/cpu_bits.h | 2 +-
-file changed, 5 insertions(+), 3 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_bits.h
 +++ b/target/riscv/cpu_bits.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
- #define MISA32_MXL          0xC0000000
+     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
- #define MISA64_MXL          0xC000000000000000ULL
+     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
+     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
--#define MXL_RV32            1
+-    RISCV_EXCP_SEMIHOST = 0x10,
--#define MXL_RV64            2
+     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
--#define MXL_RV128           3
+     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
-+typedef enum {
+     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
-+    MXL_RV32  = 1,
+     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
-+    MXL_RV64  = 2,
++    RISCV_EXCP_SEMIHOST = 0x3f,
-+    MXL_RV128 = 3,
+ } RISCVException;
-+} RISCVMXL;
+ #define RISCV_EXCP_INT_FLAG                0x80000000
  /* sstatus CSR bits */
  #define SSTATUS_UIE         0x00000001
 --
-.31.1
+.45.1

-[PULL 16/33] target/riscv: Replace DisasContext.w with DisasContext.ol
+[PULL 07/28] target/riscv/kvm: tolerate KVM disable ext errors
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-In preparation for RV128, consider more than just "w" for
+Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
-operand size modification.  This will be used for the "d"
+enabled, will fail with a kernel oops SIGILL right at the start. The
-insns from RV128 as well.
+reason is that we can't expose zkr without implementing the SEED CSR.
 Disabling zkr in the guest would be a workaround, but if the KVM doesn't
 allow it we'll error out and never boot.
-Rename oper_len to get_olen to better match get_xlen.
+In hindsight this is too strict. If we keep proceeding, despite not
 disabling the extension in the KVM vcpu, we'll not add the extension in
 the riscv,isa. The guest kernel will be unaware of the extension, i.e.
 it doesn't matter if the KVM vcpu has it enabled underneath or not. So
 it's ok to keep booting in this case.
-Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Change our current logic to not error out if we fail to disable an
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+extension in kvm_set_one_reg(), but show a warning and keep booting. It
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+is important to throw a warning because we must make the user aware that
-Message-id: 20211020031709.359469-10-richard.henderson@linaro.org
+the extension is still available in the vcpu, meaning that an
 ill-behaved guest can ignore the riscv,isa settings and  use the
 extension.
 The case we're handling happens with an EINVAL error code. If we fail to
 disable the extension in KVM for any other reason, error out.
 We'll also keep erroring out when we fail to enable an extension in KVM,
 since adding the extension in riscv,isa at this point will cause a guest
 malfunction because the extension isn't enabled in the vcpu.
 Suggested-by: Andrew Jones <ajones@ventanamicro.com>
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c                | 69 ++++++++++++++++---------
+ target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
- target/riscv/insn_trans/trans_rvb.c.inc |  8 +--
+file changed, 8 insertions(+), 4 deletions(-)
  target/riscv/insn_trans/trans_rvi.c.inc | 18 +++----
  target/riscv/insn_trans/trans_rvm.c.inc | 10 ++--
 files changed, 62 insertions(+), 43 deletions(-)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/kvm/kvm-cpu.c
-+++ b/target/riscv/translate.c
++++ b/target/riscv/kvm/kvm-cpu.c
-@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
+@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
-        to any system register, which includes CSR_FRM, so we do not have
+         reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
-        to reset this known value.  */
+         ret = kvm_set_one_reg(cs, id, &reg);
-     int frm;
+         if (ret != 0) {
--    bool w;
+-            error_report("Unable to %s extension %s in KVM, error %d",
-+    RISCVMXL ol;
+-                         reg ? "enable" : "disable",
-     bool virt_enabled;
+-                         multi_ext_cfg->name, ret);
-     bool ext_ifencei;
+-            exit(EXIT_FAILURE);
-     bool hlsx;
++            if (!reg && ret == -EINVAL) {
-@@ -XXX,XX +XXX,XX @@ static inline int __attribute__((unused)) get_xlen(DisasContext *ctx)
++                warn_report("KVM cannot disable extension %s",
-     return 16 << get_xl(ctx);
++                            multi_ext_cfg->name);
- }
++            } else {
++                error_report("Unable to enable extension %s in KVM, error %d",
--/* The word size for this operation. */
++                             multi_ext_cfg->name, ret);
--static inline int oper_len(DisasContext *ctx)
++                exit(EXIT_FAILURE);
-+/* The operation length, as opposed to the xlen. */
++            }
 +#ifdef TARGET_RISCV32
 +#define get_ol(ctx)    MXL_RV32
 +#else
 +#define get_ol(ctx)    ((ctx)->ol)
 +#endif
 +
 +static inline int get_olen(DisasContext *ctx)
  {
 -    return ctx->w ? 32 : TARGET_LONG_BITS;
 +    return 16 << get_ol(ctx);
  }
 -
  /*
   * RISC-V requires NaN-boxing of narrower width floating point values.
   * This applies when a 32-bit value is assigned to a 64-bit FP register.
@@ -XXX,XX +XXX,XX @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
          return ctx->zero;
      }
 -    switch (ctx->w ? ext : EXT_NONE) {
 -    case EXT_NONE:
 -        return cpu_gpr[reg_num];
 -    case EXT_SIGN:
 -        t = temp_new(ctx);
 -        tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
 -        return t;
 -    case EXT_ZERO:
 -        t = temp_new(ctx);
 -        tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
 -        return t;
 +    switch (get_ol(ctx)) {
 +    case MXL_RV32:
 +        switch (ext) {
 +        case EXT_NONE:
 +            break;
 +        case EXT_SIGN:
 +            t = temp_new(ctx);
 +            tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
 +            return t;
 +        case EXT_ZERO:
 +            t = temp_new(ctx);
 +            tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
 +            return t;
 +        default:
 +            g_assert_not_reached();
 +        }
 +        break;
 +    case MXL_RV64:
 +        break;
 +    default:
 +        g_assert_not_reached();
      }
 -    g_assert_not_reached();
 +    return cpu_gpr[reg_num];
  }
  static TCGv dest_gpr(DisasContext *ctx, int reg_num)
  {
 -    if (reg_num == 0 || ctx->w) {
 +    if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) {
          return temp_new(ctx);
      }
      return cpu_gpr[reg_num];
@@ -XXX,XX +XXX,XX @@ static TCGv dest_gpr(DisasContext *ctx, int reg_num)
  static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
  {
      if (reg_num != 0) {
 -        if (ctx->w) {
 +        switch (get_ol(ctx)) {
 +        case MXL_RV32:
              tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);
 -        } else {
 +            break;
 +        case MXL_RV64:
              tcg_gen_mov_tl(cpu_gpr[reg_num], t);
 +            break;
 +        default:
 +            g_assert_not_reached();
          }
      }
  }
-@@ -XXX,XX +XXX,XX @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
-                              void (*func)(TCGv, TCGv, target_long))
- {
-     TCGv dest, src1;
--    int max_len = oper_len(ctx);
-+    int max_len = get_olen(ctx);
-     if (a->shamt >= max_len) {
-         return false;
-@@ -XXX,XX +XXX,XX @@ static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext,
-                              void (*func)(TCGv, TCGv, TCGv))
- {
-     TCGv dest, src1, src2;
--    int max_len = oper_len(ctx);
-+    int max_len = get_olen(ctx);
-     if (a->shamt >= max_len) {
-         return false;
-@@ -XXX,XX +XXX,XX @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
-     TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
-     TCGv ext2 = tcg_temp_new();
--    tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1);
-+    tcg_gen_andi_tl(ext2, src2, get_olen(ctx) - 1);
-     func(dest, src1, ext2);
-     gen_set_gpr(ctx, a->rd, dest);
-@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
-     ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
-     ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
-     ctx->cs = cs;
--    ctx->w = false;
-     ctx->ntemp = 0;
-     memset(ctx->temp, 0, sizeof(ctx->temp));
-@@ -XXX,XX +XXX,XX @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
-     CPURISCVState *env = cpu->env_ptr;
-     uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
-+    ctx->ol = ctx->xl;
-     decode_opc(env, ctx, opcode16);
-     ctx->base.pc_next = ctx->pc_succ_insn;
--    ctx->w = false;
-     for (int i = ctx->ntemp - 1; i >= 0; --i) {
-         tcg_temp_free(ctx->temp[i]);
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
- {
-     REQUIRE_64BIT(ctx);
-     REQUIRE_ZBB(ctx);
--    ctx->w = true;
-+    ctx->ol = MXL_RV32;
-     return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
- }
-@@ -XXX,XX +XXX,XX @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
- {
-     REQUIRE_64BIT(ctx);
-     REQUIRE_ZBB(ctx);
--    ctx->w = true;
-+    ctx->ol = MXL_RV32;
-     return gen_shift(ctx, a, EXT_NONE, gen_rorw);
- }
-@@ -XXX,XX +XXX,XX @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
- {
-     REQUIRE_64BIT(ctx);
-     REQUIRE_ZBB(ctx);
--    ctx->w = true;
-+    ctx->ol = MXL_RV32;
-     return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
- }
-@@ -XXX,XX +XXX,XX @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
- {
-     REQUIRE_64BIT(ctx);
-     REQUIRE_ZBB(ctx);
--    ctx->w = true;
-+    ctx->ol = MXL_RV32;
-     return gen_shift(ctx, a, EXT_NONE, gen_rolw);
- }
-diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvi.c.inc
-+++ b/target/riscv/insn_trans/trans_rvi.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_and(DisasContext *ctx, arg_and *a)
- static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
- {
-     REQUIRE_64BIT(ctx);
--    ctx->w = true;
-+    ctx->ol = MXL_RV32;
-     return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl);
- }
- static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
- {
-     REQUIRE_64BIT(ctx);
--    ctx->w = true;
-+    ctx->ol = MXL_RV32;
-     return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
- }
-@@ -XXX,XX +XXX,XX @@ static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
- static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
- {
-     REQUIRE_64BIT(ctx);
--    ctx->w = true;
-+    ctx->ol = MXL_RV32;
-     return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw);
- }
-@@ -XXX,XX +XXX,XX @@ static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
- static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
- {
-     REQUIRE_64BIT(ctx);
--    ctx->w = true;
-+    ctx->ol = MXL_RV32;
-     return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw);
- }
- static bool trans_addw(DisasContext *ctx, arg_addw *a)
- {
-     REQUIRE_64BIT(ctx);
--    ctx->w = true;
-+    ctx->ol = MXL_RV32;
-     return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl);
- }
- static bool trans_subw(DisasContext *ctx, arg_subw *a)
- {
-     REQUIRE_64BIT(ctx);
--    ctx->w = true;
-+    ctx->ol = MXL_RV32;
-     return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
- }
- static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
- {
-     REQUIRE_64BIT(ctx);
--    ctx->w = true;
-+    ctx->ol = MXL_RV32;
-     return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl);
- }
- static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
- {
-     REQUIRE_64BIT(ctx);
--    ctx->w = true;
-+    ctx->ol = MXL_RV32;
-     return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
- }
- static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
- {
-     REQUIRE_64BIT(ctx);
--    ctx->w = true;
-+    ctx->ol = MXL_RV32;
-     return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
- }
-diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvm.c.inc
-+++ b/target/riscv/insn_trans/trans_rvm.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
- {
-     REQUIRE_64BIT(ctx);
-     REQUIRE_EXT(ctx, RVM);
--    ctx->w = true;
-+    ctx->ol = MXL_RV32;
-     return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl);
- }
-@@ -XXX,XX +XXX,XX @@ static bool trans_divw(DisasContext *ctx, arg_divw *a)
- {
-     REQUIRE_64BIT(ctx);
-     REQUIRE_EXT(ctx, RVM);
--    ctx->w = true;
-+    ctx->ol = MXL_RV32;
-     return gen_arith(ctx, a, EXT_SIGN, gen_div);
- }
-@@ -XXX,XX +XXX,XX @@ static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
- {
-     REQUIRE_64BIT(ctx);
-     REQUIRE_EXT(ctx, RVM);
--    ctx->w = true;
-+    ctx->ol = MXL_RV32;
-     return gen_arith(ctx, a, EXT_ZERO, gen_divu);
- }
-@@ -XXX,XX +XXX,XX @@ static bool trans_remw(DisasContext *ctx, arg_remw *a)
- {
-     REQUIRE_64BIT(ctx);
-     REQUIRE_EXT(ctx, RVM);
--    ctx->w = true;
-+    ctx->ol = MXL_RV32;
-     return gen_arith(ctx, a, EXT_SIGN, gen_rem);
- }
-@@ -XXX,XX +XXX,XX @@ static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
- {
-     REQUIRE_64BIT(ctx);
-     REQUIRE_EXT(ctx, RVM);
--    ctx->w = true;
-+    ctx->ol = MXL_RV32;
-     return gen_arith(ctx, a, EXT_ZERO, gen_remu);
- }
 --
-.31.1
+.45.1

-[PULL 32/33] hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id
+[PULL 08/28] target/riscv/debug: set tval=pc in breakpoint exceptions
-From: Bin Meng <bmeng.cn@gmail.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Using memory_region_init_ram(), which can't possibly handle vhost-user,
+We're not setting (s/m)tval when triggering breakpoints of type 2
-and can't work as expected with '-numa node,memdev' options.
+(mcontrol) and 6 (mcontrol6). According to the debug spec section
 .7.12, "Match Control Type 6":
-Use MachineState::ram instead of manually initializing RAM memory
+"The Privileged Spec says that breakpoint exceptions that occur on
-region, as well as by providing MachineClass::default_ram_id to
+instruction fetches, loads, or stores update the tval CSR with either
-opt in to memdev scheme.
+zero or the faulting virtual address. The faulting virtual address for
 an mcontrol6 trigger with action = 0 is the address being accessed and
 which caused that trigger to fire."
-Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
+A similar text is also found in the Debug spec section 5.7.11 w.r.t.
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+mcontrol.
-Reviewed-by: Igor Mammedov <imammedo@redhat.com>
 Note that what we're doing ATM is not violating the spec, but it's
 simple enough to set mtval/stval and it makes life easier for any
 software that relies on this info.
 Given that we always use action = 0, save the faulting address for the
 mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
 used as as scratch area for traps with address information. 'tval' is
 then set during riscv_cpu_do_interrupt().
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20211020014112.7336-6-bmeng.cn@gmail.com
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/sifive_u.c | 6 ++----
+ target/riscv/cpu_helper.c | 1 +
-file changed, 2 insertions(+), 4 deletions(-)
+ target/riscv/debug.c      | 3 +++
 files changed, 4 insertions(+)
-diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_u.c
+--- a/target/riscv/cpu_helper.c
-+++ b/hw/riscv/sifive_u.c
++++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
-     const MemMapEntry *memmap = sifive_u_memmap;
+             tval = env->bins;
-     SiFiveUState *s = RISCV_U_MACHINE(machine);
+             break;
-     MemoryRegion *system_memory = get_system_memory();
+         case RISCV_EXCP_BREAKPOINT:
--    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
++            tval = env->badaddr;
-     MemoryRegion *flash0 = g_new(MemoryRegion, 1);
+             if (cs->watchpoint_hit) {
-     target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
+                 tval = cs->watchpoint_hit->hitaddr;
-     target_ulong firmware_end_addr, kernel_start_addr;
+                 cs->watchpoint_hit = NULL;
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
+diff --git a/target/riscv/debug.c b/target/riscv/debug.c
-     qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/debug.c
-     /* register RAM */
++++ b/target/riscv/debug.c
--    memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
--                           machine->ram_size, &error_fatal);
+                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
-     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
+                     /* check U/S/M bit against current privilege level */
--                                main_mem);
+                     if ((ctrl >> 3) & BIT(env->priv)) {
-+                                machine->ram);
++                        env->badaddr = pc;
+                         return true;
-     /* register QSPI0 Flash */
+                     }
-     memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
+                 }
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
-     mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
+                     if (env->virt_enabled) {
-     mc->default_cpu_type = SIFIVE_U_CPU;
+                         /* check VU/VS bit against current privilege level */
-     mc->default_cpus = mc->min_cpus;
+                         if ((ctrl >> 23) & BIT(env->priv)) {
-+    mc->default_ram_id = "riscv.sifive.u.ram";
++                            env->badaddr = pc;
+                             return true;
-     object_class_property_add_bool(oc, "start-in-flash",
+                         }
-                                    sifive_u_machine_get_start_in_flash,
+                     } else {
                          /* check U/S/M bit against current privilege level */
                          if ((ctrl >> 3) & BIT(env->priv)) {
 +                            env->badaddr = pc;
                              return true;
                          }
                      }
 --
-.31.1
+.45.1

-[PULL 30/33] hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id
+[PULL 09/28] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
-From: Bin Meng <bmeng.cn@gmail.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Using memory_region_init_ram(), which can't possibly handle vhost-user,
+Privileged spec section 4.1.9 mentions:
 and can't work as expected with '-numa node,memdev' options.
-Use MachineState::ram instead of manually initializing RAM memory
+"When a trap is taken into S-mode, stval is written with
-region, as well as by providing MachineClass::default_ram_id to
+exception-specific information to assist software in handling the trap.
-opt in to memdev scheme.
+(...)
-Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
+If stval is written with a nonzero value when a breakpoint,
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+address-misaligned, access-fault, or page-fault exception occurs on an
-Reviewed-by: Igor Mammedov <imammedo@redhat.com>
+instruction fetch, load, or store, then stval will contain the faulting
 virtual address."
 A similar text is found for mtval in section 3.1.16.
 Setting mtval/stval in this scenario is optional, but some softwares read
 these regs when handling ebreaks.
 Write 'badaddr' in all ebreak breakpoints to write the appropriate
 'tval' during riscv_do_cpu_interrrupt().
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20211020014112.7336-4-bmeng.cn@gmail.com
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/shakti_c.c | 6 ++----
+ target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
-file changed, 2 insertions(+), 4 deletions(-)
+file changed, 2 insertions(+)
-diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
+diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/shakti_c.c
+--- a/target/riscv/insn_trans/trans_privileged.c.inc
-+++ b/hw/riscv/shakti_c.c
++++ b/target/riscv/insn_trans/trans_privileged.c.inc
-@@ -XXX,XX +XXX,XX @@ static void shakti_c_machine_state_init(MachineState *mstate)
+@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
- {
+     if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
-     ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
+         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
-     MemoryRegion *system_memory = get_system_memory();
+     } else {
--    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
++        tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
++                      offsetof(CPURISCVState, badaddr));
-     /* Allow only Shakti C CPU for this platform */
+         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
-     if (strcmp(mstate->cpu_type, TYPE_RISCV_CPU_SHAKTI_C) != 0) {
+     }
-@@ -XXX,XX +XXX,XX @@ static void shakti_c_machine_state_init(MachineState *mstate)
+     return true;
      qdev_realize(DEVICE(&sms->soc), NULL, &error_abort);
      /* register RAM */
 -    memory_region_init_ram(main_mem, NULL, "riscv.shakti.c.ram",
 -                           mstate->ram_size, &error_fatal);
      memory_region_add_subregion(system_memory,
                                  shakti_c_memmap[SHAKTI_C_RAM].base,
 -                                main_mem);
 +                                mstate->ram);
      /* ROM reset vector */
      riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus,
@@ -XXX,XX +XXX,XX @@ static void shakti_c_machine_class_init(ObjectClass *klass, void *data)
      mc->desc = "RISC-V Board compatible with Shakti SDK";
      mc->init = shakti_c_machine_state_init;
      mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C;
 +    mc->default_ram_id = "riscv.shakti.c.ram";
  }
  static const TypeInfo shakti_c_machine_type_info = {
 --
-.31.1
+.45.1

-[PULL 11/33] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
+[PULL 10/28] target/riscv: Add support for Zve32x extension
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Jason Chien <jason.chien@sifive.com>
-Shortly, the set of supported XL will not be just 32 and 64,
+Add support for Zve32x extension and replace some checks for Zve32f with
-and representing that properly using the enumeration will be
+Zve32x, since Zve32f depends on Zve32x.
 imperative.
-Two places, booting and gdb, intentionally use misa_mxl_max
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
-to emphasize the use of the reset value of misa.mxl, and not
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-the current cpu state.
+Reviewed-by: Max Chou <max.chou@sifive.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20211020031709.359469-5-richard.henderson@linaro.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h            |  9 ++++++++-
+ target/riscv/cpu_cfg.h                  |  1 +
- hw/riscv/boot.c               |  2 +-
+ target/riscv/cpu.c                      |  2 ++
- semihosting/arm-compat-semi.c |  2 +-
+ target/riscv/cpu_helper.c               |  2 +-
- target/riscv/cpu.c            | 24 ++++++++++++++----------
+ target/riscv/csr.c                      |  2 +-
- target/riscv/cpu_helper.c     | 12 ++++++------
+ target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
- target/riscv/csr.c            | 24 ++++++++++++------------
+ target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
- target/riscv/gdbstub.c        |  2 +-
+files changed, 15 insertions(+), 12 deletions(-)
  target/riscv/monitor.c        |  4 ++--
 files changed, 45 insertions(+), 34 deletions(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/target/riscv/cpu_cfg.h
-+++ b/target/riscv/cpu.h
++++ b/target/riscv/cpu_cfg.h
-@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, VILL, 9, 1)
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
- FIELD(TB_FLAGS, HLSX, 10, 1)
+     bool ext_zhinx;
- FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2)
+     bool ext_zhinxmin;
+     bool ext_zve32f;
--bool riscv_cpu_is_32bit(CPURISCVState *env);
++    bool ext_zve32x;
-+#ifdef TARGET_RISCV32
+     bool ext_zve64f;
-+#define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
+     bool ext_zve64d;
-+#else
+     bool ext_zvbb;
 +static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
 +{
 +    return env->misa_mxl;
 +}
 +#endif
  /*
   * A simplification for VLMAX
 diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/boot.c
 +++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@
  bool riscv_is_32bit(RISCVHartArrayState *harts)
  {
 -    return riscv_cpu_is_32bit(&harts->harts[0].env);
 +    return harts->harts[0].env.misa_mxl_max == MXL_RV32;
  }
  target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
 diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c
 index XXXXXXX..XXXXXXX 100644
 --- a/semihosting/arm-compat-semi.c
 +++ b/semihosting/arm-compat-semi.c
@@ -XXX,XX +XXX,XX @@ static inline bool is_64bit_semihosting(CPUArchState *env)
  #if defined(TARGET_ARM)
      return is_a64(env);
  #elif defined(TARGET_RISCV)
 -    return !riscv_cpu_is_32bit(env);
 +    return riscv_cpu_mxl(env) != MXL_RV32;
  #else
  #error un-handled architecture
  #endif
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
+@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
-     }
+     ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
- }
+     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
+     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
--bool riscv_cpu_is_32bit(CPURISCVState *env)
++    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
--{
+     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
--    return env->misa_mxl == MXL_RV32;
+     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
--}
+     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
--
+@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
- static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
+     MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
- {
+     MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
-     env->misa_mxl_max = env->misa_mxl = mxl;
+     MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
++    MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
- #ifndef CONFIG_USER_ONLY
+     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
-     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
+     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
-     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
+     MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
 -    if (riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) == MXL_RV32) {
          qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
                       (target_ulong)(env->mstatus >> 32));
      }
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
  static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
  {
      RISCVCPU *cpu = RISCV_CPU(s);
 -    if (riscv_cpu_is_32bit(&cpu->env)) {
 +
 +    switch (riscv_cpu_mxl(&cpu->env)) {
 +    case MXL_RV32:
          info->print_insn = print_insn_riscv32;
 -    } else {
 +        break;
 +    case MXL_RV64:
          info->print_insn = print_insn_riscv64;
 +        break;
 +    default:
 +        g_assert_not_reached();
      }
  }
@@ -XXX,XX +XXX,XX @@ static gchar *riscv_gdb_arch_name(CPUState *cs)
      RISCVCPU *cpu = RISCV_CPU(cs);
      CPURISCVState *env = &cpu->env;
 -    if (riscv_cpu_is_32bit(env)) {
 +    switch (riscv_cpu_mxl(env)) {
 +    case MXL_RV32:
          return g_strdup("riscv:rv32");
 -    } else {
 +    case MXL_RV64:
          return g_strdup("riscv:rv64");
 +    default:
 +        g_assert_not_reached();
      }
  }
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
+@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
+     *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
- void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
+     *cs_base = 0;
- {
--    uint64_t sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD;
+-    if (cpu->cfg.ext_zve32f) {
-+    uint64_t sd = riscv_cpu_mxl(env) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
++    if (cpu->cfg.ext_zve32x) {
-     uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
+         /*
-                             MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
+          * If env->vl equals to VLMAX, we can use generic vector operation
-                             MSTATUS64_UXL | sd;
+          * expanders (GVEC) to accerlate the vector operations.
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
      if (first_stage == true) {
          if (use_background) {
 -            if (riscv_cpu_is_32bit(env)) {
 +            if (riscv_cpu_mxl(env) == MXL_RV32) {
                  base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
                  vm = get_field(env->vsatp, SATP32_MODE);
              } else {
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
                  vm = get_field(env->vsatp, SATP64_MODE);
              }
          } else {
 -            if (riscv_cpu_is_32bit(env)) {
 +            if (riscv_cpu_mxl(env) == MXL_RV32) {
                  base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
                  vm = get_field(env->satp, SATP32_MODE);
              } else {
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
          }
          widened = 0;
      } else {
 -        if (riscv_cpu_is_32bit(env)) {
 +        if (riscv_cpu_mxl(env) == MXL_RV32) {
              base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
              vm = get_field(env->hgatp, SATP32_MODE);
          } else {
@@ -XXX,XX +XXX,XX @@ restart:
          }
          target_ulong pte;
 -        if (riscv_cpu_is_32bit(env)) {
 +        if (riscv_cpu_mxl(env) == MXL_RV32) {
              pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
          } else {
              pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
      int page_fault_exceptions, vm;
      uint64_t stap_mode;
 -    if (riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) == MXL_RV32) {
          stap_mode = SATP32_MODE;
      } else {
          stap_mode = SATP64_MODE;
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
+@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
-             }
-             break;
+ static RISCVException vs(CPURISCVState *env, int csrno)
          }
 -        if (riscv_cpu_is_32bit(env)) {
 +        if (riscv_cpu_mxl(env) == MXL_RV32) {
              switch (csrno) {
              case CSR_CYCLEH:
                  if (!get_field(env->hcounteren, COUNTEREN_CY) &&
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
  static RISCVException ctr32(CPURISCVState *env, int csrno)
  {
--    if (!riscv_cpu_is_32bit(env)) {
+-    if (riscv_cpu_cfg(env)->ext_zve32f) {
-+    if (riscv_cpu_mxl(env) != MXL_RV32) {
++    if (riscv_cpu_cfg(env)->ext_zve32x) {
-         return RISCV_EXCP_ILLEGAL_INST;
+ #if !defined(CONFIG_USER_ONLY)
-     }
+         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
@@ -XXX,XX +XXX,XX @@ static RISCVException any(CPURISCVState *env, int csrno)
  static RISCVException any32(CPURISCVState *env, int csrno)
  {
 -    if (!riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) != MXL_RV32) {
          return RISCV_EXCP_ILLEGAL_INST;
      }
@@ -XXX,XX +XXX,XX @@ static RISCVException hmode(CPURISCVState *env, int csrno)
  static RISCVException hmode32(CPURISCVState *env, int csrno)
  {
 -    if (!riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) != MXL_RV32) {
          if (riscv_cpu_virt_enabled(env)) {
              return RISCV_EXCP_ILLEGAL_INST;
-         } else {
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno,
  static int validate_vm(CPURISCVState *env, target_ulong vm)
  {
 -    if (riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) == MXL_RV32) {
          return valid_vm_1_10_32[vm & 0xf];
      } else {
          return valid_vm_1_10_64[vm & 0xf];
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
          MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
          MSTATUS_TW;
 -    if (!riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) != MXL_RV32) {
          /*
           * RV32: MPV and GVA are not in mstatus. The current plan is to
           * add them to mstatush. For now, we just don't support it.
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
      dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
              ((mstatus & MSTATUS_XS) == MSTATUS_XS);
 -    if (riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) == MXL_RV32) {
          mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
      } else {
          mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
  {
      target_ulong mask = (sstatus_v1_10_mask);
 -    if (riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) == MXL_RV32) {
          mask |= SSTATUS32_SD;
      } else {
          mask |= SSTATUS64_SD;
@@ -XXX,XX +XXX,XX @@ static RISCVException write_satp(CPURISCVState *env, int csrno,
          return RISCV_EXCP_NONE;
      }
 -    if (riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) == MXL_RV32) {
          vm = validate_vm(env, get_field(val, SATP32_MODE));
          mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
          asid = (val ^ env->satp) & SATP32_ASID;
@@ -XXX,XX +XXX,XX @@ static RISCVException read_hstatus(CPURISCVState *env, int csrno,
                                     target_ulong *val)
  {
      *val = env->hstatus;
 -    if (!riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) != MXL_RV32) {
          /* We only support 64-bit VSXL */
          *val = set_field(*val, HSTATUS_VSXL, 2);
      }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_hstatus(CPURISCVState *env, int csrno,
                                      target_ulong val)
  {
      env->hstatus = val;
 -    if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) {
 +    if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
          qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
      }
      if (get_field(val, HSTATUS_VSBE) != 0) {
@@ -XXX,XX +XXX,XX @@ static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
          return RISCV_EXCP_ILLEGAL_INST;
      }
 -    if (riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) == MXL_RV32) {
          env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
      } else {
          env->htimedelta = val;
 diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/gdbstub.c
+--- a/target/riscv/tcg/tcg-cpu.c
-+++ b/target/riscv/gdbstub.c
++++ b/target/riscv/tcg/tcg-cpu.c
-@@ -XXX,XX +XXX,XX @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
      CPURISCVState *env = &cpu->env;
      GString *s = g_string_new(NULL);
      riscv_csr_predicate_fn predicate;
 -    int bitsize = riscv_cpu_is_32bit(env) ? 32 : 64;
 +    int bitsize = 16 << env->misa_mxl_max;
      int i;
      g_string_printf(s, "<?xml version=\"1.0\"?>");
 diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/monitor.c
 +++ b/target/riscv/monitor.c
@@ -XXX,XX +XXX,XX @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env)
      target_ulong last_size;
      int last_attr;
 -    if (riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) == MXL_RV32) {
          base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
          vm = get_field(env->satp, SATP32_MODE);
      } else {
@@ -XXX,XX +XXX,XX @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
          return;
      }
--    if (riscv_cpu_is_32bit(env)) {
+-    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
-+    if (riscv_cpu_mxl(env) == MXL_RV32) {
+-        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
-         if (!(env->satp & SATP32_MODE)) {
+-        return;
-             monitor_printf(mon, "No translation or protection\n");
++    /* The Zve32f extension depends on the Zve32x extension */
-             return;
++    if (cpu->cfg.ext_zve32f) {
 +        if (!riscv_has_ext(env, RVF)) {
 +            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
 +            return;
 +        }
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
      }
      if (cpu->cfg.ext_zvfh) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
          cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
      }
 -    /*
 -     * In principle Zve*x would also suffice here, were they supported
 -     * in qemu
 -     */
      if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
           cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
 -         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
 +         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
          error_setg(errp,
                     "Vector crypto extensions require V or Zve* extensions");
          return;
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
  {
      TCGv s1, dst;
 -    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
 +    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
          return false;
      }
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
  {
      TCGv dst;
 -    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
 +    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
          return false;
      }
 --
-.31.1
+.45.1

-[PULL 07/33] target/riscv: Organise the CPU properties
+[PULL 11/28] target/riscv: Add support for Zve64x extension
-From: Alistair Francis <alistair.francis@wdc.com>
+From: Jason Chien <jason.chien@sifive.com>
-Organise the CPU properties so that standard extensions come first
+Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
-then followed by experimental extensions.
+enabling Zve64x enables Zve32x according to their dependency.
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Max Chou <max.chou@sifive.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Message-id: b6598570f60c5ee7f402be56d837bb44b289cc4d.1634531504.git.alistair.francis@wdc.com
 ---
- target/riscv/cpu.c | 17 ++++++++++-------
+ target/riscv/cpu_cfg.h     |  1 +
-file changed, 10 insertions(+), 7 deletions(-)
+ target/riscv/cpu.c         |  2 ++
  target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
 files changed, 14 insertions(+), 6 deletions(-)
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_cfg.h
++++ b/target/riscv/cpu_cfg.h
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+     bool ext_zve32x;
+     bool ext_zve64f;
+     bool ext_zve64d;
++    bool ext_zve64x;
+     bool ext_zvbb;
+     bool ext_zvbc;
+     bool ext_zvkb;
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
- }
+     ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
+     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
- static Property riscv_cpu_properties[] = {
+     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
-+    /* Defaults for standard extensions */
++    ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),
-     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
+     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
-     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
+     ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
-     DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
+     ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
+@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
-     DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
+     MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
-     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
+     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
-     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
+     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
--    /* This is experimental so mark with 'x-' */
++    MULTI_EXT_CFG_BOOL("zve64x", ext_zve64x, false),
-+    DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
+     MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
-+    DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
+     MULTI_EXT_CFG_BOOL("zvfbfwma", ext_zvfbfwma, false),
-+    DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
+     MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false),
-+    DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
-+    DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+index XXXXXXX..XXXXXXX 100644
-+
+--- a/target/riscv/tcg/tcg-cpu.c
-+    DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
++++ b/target/riscv/tcg/tcg-cpu.c
-+
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-+    /* These are experimental so mark with 'x-' */
-     DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
+     /* The Zve64d extension depends on the Zve64f extension */
-     DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
+     if (cpu->cfg.ext_zve64d) {
-     DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
++        if (!riscv_has_ext(env, RVD)) {
-     DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
++            error_setg(errp, "Zve64d/V extensions require D extension");
-     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
++            return;
-     DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
++        }
--    DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
+         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
--    DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
+     }
--    DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
--    DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
+-    /* The Zve64f extension depends on the Zve32f extension */
-     DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
++    /* The Zve64f extension depends on the Zve64x and Zve32f extensions */
-     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
+     if (cpu->cfg.ext_zve64f) {
-     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64x), true);
--    DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
+         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
--    DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+     }
-     /* ePMP 0.9.3 */
-     DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
+-    if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
 -        error_setg(errp, "Zve64d/V extensions require D extension");
 -        return;
 +    /* The Zve64x extension depends on the Zve32x extension */
 +    if (cpu->cfg.ext_zve64x) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
      }
      /* The Zve32f extension depends on the Zve32x extension */
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
          return;
      }
 -    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
 +    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) {
          error_setg(
              errp,
 -            "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
 +            "Zvbc and Zvknhb extensions require V or Zve64x extensions");
          return;
      }
 --
-.31.1
+.45.1

-[PULL 29/33] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
+[PULL 12/28] target/riscv: Relax vector register check in RISCV gdbstub
-From: Bin Meng <bmeng.cn@gmail.com>
+From: Jason Chien <jason.chien@sifive.com>
-Using memory_region_init_ram(), which can't possibly handle vhost-user,
+In current implementation, the gdbstub allows reading vector registers
-and can't work as expected with '-numa node,memdev' options.
+only if V extension is supported. However, all vector extensions and
 vector crypto extensions have the vector registers and they all depend
 on Zve32x. The gdbstub should check for Zve32x instead.
-Use MachineState::ram instead of manually initializing RAM memory
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
-region, as well as by providing MachineClass::default_ram_id to
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-opt in to memdev scheme.
+Reviewed-by: Max Chou <max.chou@sifive.com>
+Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
 While at it add check for user supplied RAM size and error out if it
 mismatches board expected value.
 Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Igor Mammedov <imammedo@redhat.com>
 Message-id: 20211020014112.7336-3-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/opentitan.c | 16 ++++++++++++----
+ target/riscv/gdbstub.c | 2 +-
-file changed, 12 insertions(+), 4 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
+diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/opentitan.c
+--- a/target/riscv/gdbstub.c
-+++ b/hw/riscv/opentitan.c
++++ b/target/riscv/gdbstub.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
-  */
+                                  gdb_find_static_feature("riscv-32bit-fpu.xml"),
+);
- #include "qemu/osdep.h"
+     }
-+#include "qemu/cutils.h"
+-    if (env->misa_ext & RVV) {
- #include "hw/riscv/opentitan.h"
++    if (cpu->cfg.ext_zve32x) {
- #include "qapi/error.h"
+         gdb_register_coprocessor(cs, riscv_gdb_get_vector,
- #include "hw/boards.h"
+                                  riscv_gdb_set_vector,
-@@ -XXX,XX +XXX,XX @@ static const MemMapEntry ibex_memmap[] = {
+                                  ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
  static void opentitan_board_init(MachineState *machine)
  {
 +    MachineClass *mc = MACHINE_GET_CLASS(machine);
      const MemMapEntry *memmap = ibex_memmap;
      OpenTitanState *s = g_new0(OpenTitanState, 1);
      MemoryRegion *sys_mem = get_system_memory();
 -    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 +
 +    if (machine->ram_size != mc->default_ram_size) {
 +        char *sz = size_to_str(mc->default_ram_size);
 +        error_report("Invalid RAM size, should be %s", sz);
 +        g_free(sz);
 +        exit(EXIT_FAILURE);
 +    }
      /* Initialize SoC */
      object_initialize_child(OBJECT(machine), "soc", &s->soc,
                              TYPE_RISCV_IBEX_SOC);
      qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
 -    memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
 -        memmap[IBEX_DEV_RAM].size, &error_fatal);
      memory_region_add_subregion(sys_mem,
 -        memmap[IBEX_DEV_RAM].base, main_mem);
 +        memmap[IBEX_DEV_RAM].base, machine->ram);
      if (machine->firmware) {
          riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL);
@@ -XXX,XX +XXX,XX @@ static void opentitan_machine_init(MachineClass *mc)
      mc->init = opentitan_board_init;
      mc->max_cpus = 1;
      mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
 +    mc->default_ram_id = "riscv.lowrisc.ibex.ram";
 +    mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
  }
  DEFINE_MACHINE("opentitan", opentitan_machine_init)
 --
-.31.1
+.45.1

-[PULL 15/33] target/riscv: Replace is_32bit with get_xl/get_xlen
+[PULL 13/28] target/riscv: Fix the element agnostic function problem
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Huang Tao <eric.huang@linux.alibaba.com>
-In preparation for RV128, replace a simple predicate
+In RVV and vcrypto instructions, the masked and tail elements are set to 1s
-with a more versatile test.
+using vext_set_elems_1s function if the vma/vta bit is set. It is the element
 agnostic policy.
-Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+However, this function can't deal the big endian situation. This patch fixes
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+the problem by adding handling of such case.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20211020031709.359469-9-richard.henderson@linaro.org
+Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
 Suggested-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c | 31 +++++++++++++++++--------------
+ target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
-file changed, 17 insertions(+), 14 deletions(-)
+file changed, 22 insertions(+)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/vector_internals.c
-+++ b/target/riscv/translate.c
++++ b/target/riscv/vector_internals.c
-@@ -XXX,XX +XXX,XX @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
+@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
      if (tot - cnt == 0) {
          return ;
      }
 +
 +    if (HOST_BIG_ENDIAN) {
 +        /*
 +         * Deal the situation when the elements are insdie
 +         * only one uint64 block including setting the
 +         * masked-off element.
 +         */
 +        if (((tot - 1) ^ cnt) < 8) {
 +            memset(base + H1(tot - 1), -1, tot - cnt);
 +            return;
 +        }
 +        /*
 +         * Otherwise, at least cross two uint64_t blocks.
 +         * Set first unaligned block.
 +         */
 +        if (cnt % 8 != 0) {
 +            uint32_t j = ROUND_UP(cnt, 8);
 +            memset(base + H1(j - 1), -1, j - cnt);
 +            cnt = j;
 +        }
 +        /* Set other 64bit aligend blocks */
 +    }
      memset(base + cnt, -1, tot - cnt);
  }
- #ifdef TARGET_RISCV32
--# define is_32bit(ctx)  true
-+#define get_xl(ctx)    MXL_RV32
- #elif defined(CONFIG_USER_ONLY)
--# define is_32bit(ctx)  false
-+#define get_xl(ctx)    MXL_RV64
- #else
--static inline bool is_32bit(DisasContext *ctx)
-+#define get_xl(ctx)    ((ctx)->xl)
-+#endif
-+
-+/* The word size for this machine mode. */
-+static inline int __attribute__((unused)) get_xlen(DisasContext *ctx)
- {
--    return ctx->xl == MXL_RV32;
-+    return 16 << get_xl(ctx);
- }
--#endif
- /* The word size for this operation. */
- static inline int oper_len(DisasContext *ctx)
-@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
- static void mark_fs_dirty(DisasContext *ctx)
- {
-     TCGv tmp;
--    target_ulong sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
-+    target_ulong sd = get_xl(ctx) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
-     if (ctx->mstatus_fs != MSTATUS_FS) {
-         /* Remember the state change for the rest of the TB. */
-@@ -XXX,XX +XXX,XX @@ EX_SH(12)
-     }                              \
- } while (0)
--#define REQUIRE_32BIT(ctx) do { \
--    if (!is_32bit(ctx)) {       \
--        return false;           \
--    }                           \
-+#define REQUIRE_32BIT(ctx) do {    \
-+    if (get_xl(ctx) != MXL_RV32) { \
-+        return false;              \
-+    }                              \
- } while (0)
--#define REQUIRE_64BIT(ctx) do { \
--    if (is_32bit(ctx)) {        \
--        return false;           \
--    }                           \
-+#define REQUIRE_64BIT(ctx) do {    \
-+    if (get_xl(ctx) < MXL_RV64) {  \
-+        return false;              \
-+    }                              \
- } while (0)
- static int ex_rvc_register(DisasContext *ctx, int reg)
 --
-.31.1
+.45.1

-[PULL 21/33] target/riscv: Use riscv_csrrw_debug for cpu_dump
+[PULL 14/28] target/riscv/cpu.c: fix Zvkb extension config
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Yangyu Chen <cyy@cyyself.name>
-Use the official debug read interface to the csrs,
+This code has a typo that writes zvkb to zvkg, causing users can't
-rather than referencing the env slots directly.
+enable zvkb through the config. This patch gets this fixed.
 Put the list of csrs to dump into a table.
+Signed-off-by: Yangyu Chen <cyy@cyyself.name>
+Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Max Chou <max.chou@sifive.com>
-Message-id: 20211020031709.359469-15-richard.henderson@linaro.org
+Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
 Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.c | 89 +++++++++++++++++++++++-----------------------
+ target/riscv/cpu.c | 2 +-
-file changed, 45 insertions(+), 44 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
+@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
- #endif
+     /* Vector cryptography extensions */
-     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
+     MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
- #ifndef CONFIG_USER_ONLY
+     MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
--    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
+-    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
--    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
++    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
--    if (riscv_cpu_mxl(env) == MXL_RV32) {
+     MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
--        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
+     MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
--                     (target_ulong)(env->mstatus >> 32));
+     MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
 -    }
 -    if (riscv_has_ext(env, RVH)) {
 -        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
 -        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus",
 -                     (target_ulong)env->vsstatus);
 -    }
 -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
 -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);
 -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
 -    if (riscv_has_ext(env, RVH)) {
 -        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
 -    }
 -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
 -    if (riscv_has_ext(env, RVH)) {
 -        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);
 -    }
 -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec   ", env->mtvec);
 -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec   ", env->stvec);
 -    if (riscv_has_ext(env, RVH)) {
 -        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec  ", env->vstvec);
 -    }
 -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc    ", env->mepc);
 -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc    ", env->sepc);
 -    if (riscv_has_ext(env, RVH)) {
 -        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc   ", env->vsepc);
 -    }
 -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause  ", env->mcause);
 -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause  ", env->scause);
 -    if (riscv_has_ext(env, RVH)) {
 -        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
 -    }
 -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval   ", env->mtval);
 -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval   ", env->stval);
 -    if (riscv_has_ext(env, RVH)) {
 -        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval   ", env->htval);
 -        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2  ", env->mtval2);
 +    {
 +        static const int dump_csrs[] = {
 +            CSR_MHARTID,
 +            CSR_MSTATUS,
 +            CSR_MSTATUSH,
 +            CSR_HSTATUS,
 +            CSR_VSSTATUS,
 +            CSR_MIP,
 +            CSR_MIE,
 +            CSR_MIDELEG,
 +            CSR_HIDELEG,
 +            CSR_MEDELEG,
 +            CSR_HEDELEG,
 +            CSR_MTVEC,
 +            CSR_STVEC,
 +            CSR_VSTVEC,
 +            CSR_MEPC,
 +            CSR_SEPC,
 +            CSR_VSEPC,
 +            CSR_MCAUSE,
 +            CSR_SCAUSE,
 +            CSR_VSCAUSE,
 +            CSR_MTVAL,
 +            CSR_STVAL,
 +            CSR_HTVAL,
 +            CSR_MTVAL2,
 +            CSR_MSCRATCH,
 +            CSR_SSCRATCH,
 +            CSR_SATP,
 +        };
 +
 +        for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
 +            int csrno = dump_csrs[i];
 +            target_ulong val = 0;
 +            RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
 +
 +            /*
 +             * Rely on the smode, hmode, etc, predicates within csr.c
 +             * to do the filtering of the registers that are present.
 +             */
 +            if (res == RISCV_EXCP_NONE) {
 +                qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
 +                             csr_ops[csrno].name, val);
 +            }
 +        }
      }
 -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch);
 -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch);
 -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp    ", env->satp);
  #endif
      for (i = 0; i < 32; i++) {
 --
-.31.1
+.45.1

-[PULL 10/33] target/riscv: Split misa.mxl and misa.ext
+[PULL 15/28] target/riscv: Implement dynamic establishment of custom decoder
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Huang Tao <eric.huang@linux.alibaba.com>
-The hw representation of misa.mxl is at the high bits of the
+In this patch, we modify the decoder to be a freely composable data
-misa csr.  Representing this in the same way inside QEMU
+structure instead of a hardcoded one. It can be dynamically builded up
-results in overly complex code trying to check that field.
+according to the extensions.
 This approach has several benefits:
 . Provides support for heterogeneous cpu architectures. As we add decoder in
    RISCVCPU, each cpu can have their own decoder, and the decoders can be
    different due to cpu's features.
 . Improve the decoding efficiency. We run the guard_func to see if the decoder
    can be added to the dynamic_decoder when building up the decoder. Therefore,
    there is no need to run the guard_func when decoding each instruction. It can
    improve the decoding efficiency
 . For vendor or dynamic cpus, it allows them to customize their own decoder
    functions to improve decoding efficiency, especially when vendor-defined
    instruction sets increase. Because of dynamic building up, it can skip the other
    decoder guard functions when decoding.
 . Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
    overhead for users that don't need this particular vendor decoder.
-Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
 Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
 Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
 Message-id: 20211020031709.359469-4-richard.henderson@linaro.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h          | 15 +++----
+ target/riscv/cpu.h         |  1 +
- linux-user/elfload.c        |  2 +-
+ target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
- linux-user/riscv/cpu_loop.c |  2 +-
+ target/riscv/cpu.c         |  1 +
- target/riscv/cpu.c          | 78 +++++++++++++++++++++----------------
+ target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
- target/riscv/csr.c          | 44 ++++++++++++++-------
+ target/riscv/translate.c   | 31 +++++++++++++++----------------
- target/riscv/gdbstub.c      |  8 ++--
+files changed, 47 insertions(+), 16 deletions(-)
  target/riscv/machine.c      | 10 +++--
  target/riscv/translate.c    | 10 +++--
 files changed, 100 insertions(+), 69 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
- #include "exec/cpu-defs.h"
+     uint32_t pmu_avail_ctrs;
- #include "fpu/softfloat-types.h"
+     /* Mapping of events to counters */
- #include "qom/object.h"
+     GHashTable *pmu_event_ctr_map;
-+#include "cpu_bits.h"
++    const GPtrArray *decoders;
+ };
- #define TCG_GUEST_DEFAULT_MO 0
+ /**
-@@ -XXX,XX +XXX,XX @@
+diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
- # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
+index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.h
 +++ b/target/riscv/tcg/tcg-cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
  void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
  bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
 +struct DisasContext;
 +struct RISCVCPUConfig;
 +typedef struct RISCVDecoder {
 +    bool (*guard_func)(const struct RISCVCPUConfig *);
 +    bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
 +} RISCVDecoder;
 +
 +typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
 +
 +extern const size_t decoder_table_size;
 +
 +extern const RISCVDecoder decoder_table[];
 +
 +void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
 +
  #endif
--#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
--#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
--
- #define RV(x) ((target_ulong)1 << (x - 'A'))
- #define RVI RV('I')
-@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
-     target_ulong priv_ver;
-     target_ulong bext_ver;
-     target_ulong vext_ver;
--    target_ulong misa;
--    target_ulong misa_mask;
-+
-+    /* RISCVMXL, but uint32_t for vmstate migration */
-+    uint32_t misa_mxl;      /* current mxl */
-+    uint32_t misa_mxl_max;  /* max mxl for this cpu */
-+    uint32_t misa_ext;      /* current extensions */
-+    uint32_t misa_ext_mask; /* max ext for this cpu */
-     uint32_t features;
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
- static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
- {
--    return (env->misa & ext) != 0;
-+    return (env->misa_ext & ext) != 0;
- }
- static inline bool riscv_feature(CPURISCVState *env, int feature)
-@@ -XXX,XX +XXX,XX @@ static inline bool riscv_feature(CPURISCVState *env, int feature)
- }
- #include "cpu_user.h"
--#include "cpu_bits.h"
- extern const char * const riscv_int_regnames[];
- extern const char * const riscv_fpr_regnames[];
-diff --git a/linux-user/elfload.c b/linux-user/elfload.c
-index XXXXXXX..XXXXXXX 100644
---- a/linux-user/elfload.c
-+++ b/linux-user/elfload.c
-@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
-     uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A')
-                     | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C');
--    return cpu->env.misa & mask;
-+    return cpu->env.misa_ext & mask;
- #undef MISA_BIT
- }
-diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
-index XXXXXXX..XXXXXXX 100644
---- a/linux-user/riscv/cpu_loop.c
-+++ b/linux-user/riscv/cpu_loop.c
-@@ -XXX,XX +XXX,XX @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
-     env->gpr[xSP] = regs->sp;
-     env->elf_flags = info->elf_flags;
--    if ((env->misa & RVE) && !(env->elf_flags & EF_RISCV_RVE)) {
-+    if ((env->misa_ext & RVE) && !(env->elf_flags & EF_RISCV_RVE)) {
-         error_report("Incompatible ELF: RVE cpu requires RVE ABI binary");
-         exit(EXIT_FAILURE);
-     }
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
+             error_propagate(errp, local_err);
- bool riscv_cpu_is_32bit(CPURISCVState *env)
+             return;
- {
+         }
--    if (env->misa & RV64) {
++        riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
--        return false;
+     } else if (kvm_enabled()) {
--    }
+         riscv_kvm_cpu_finalize_features(cpu, &local_err);
--
+         if (local_err != NULL) {
--    return true;
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
-+    return env->misa_mxl == MXL_RV32;
+index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
      }
  }
--static void set_misa(CPURISCVState *env, target_ulong misa)
++void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
-+static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
++{
- {
++    GPtrArray *dynamic_decoders;
--    env->misa_mask = env->misa = misa;
++    dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
-+    env->misa_mxl_max = env->misa_mxl = mxl;
++    for (size_t i = 0; i < decoder_table_size; ++i) {
-+    env->misa_ext_mask = env->misa_ext = ext;
++        if (decoder_table[i].guard_func &&
- }
++            decoder_table[i].guard_func(&cpu->cfg)) {
++            g_ptr_array_add(dynamic_decoders,
- static void set_priv_version(CPURISCVState *env, int priv_ver)
++                            (gpointer)decoder_table[i].riscv_cpu_decode_fn);
-@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
++        }
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
  #if defined(TARGET_RISCV32)
 -    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 +    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
  #elif defined(TARGET_RISCV64)
 -    set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 +    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
  #endif
      set_priv_version(env, PRIV_VERSION_1_11_0);
  }
@@ -XXX,XX +XXX,XX @@ static void rv64_base_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      /* We set this in the realise function */
 -    set_misa(env, RV64);
 +    set_misa(env, MXL_RV64, 0);
  }
  static void rv64_sifive_u_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
 -    set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 +    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
      set_priv_version(env, PRIV_VERSION_1_10_0);
  }
  static void rv64_sifive_e_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
 -    set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
 +    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
      set_priv_version(env, PRIV_VERSION_1_10_0);
      qdev_prop_set_bit(DEVICE(obj), "mmu", false);
  }
@@ -XXX,XX +XXX,XX @@ static void rv32_base_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      /* We set this in the realise function */
 -    set_misa(env, RV32);
 +    set_misa(env, MXL_RV32, 0);
  }
  static void rv32_sifive_u_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
 -    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 +    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
      set_priv_version(env, PRIV_VERSION_1_10_0);
  }
  static void rv32_sifive_e_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
 -    set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
 +    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
      set_priv_version(env, PRIV_VERSION_1_10_0);
      qdev_prop_set_bit(DEVICE(obj), "mmu", false);
  }
@@ -XXX,XX +XXX,XX @@ static void rv32_sifive_e_cpu_init(Object *obj)
  static void rv32_ibex_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
 -    set_misa(env, RV32 | RVI | RVM | RVC | RVU);
 +    set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
      set_priv_version(env, PRIV_VERSION_1_10_0);
      qdev_prop_set_bit(DEVICE(obj), "mmu", false);
      qdev_prop_set_bit(DEVICE(obj), "x-epmp", true);
@@ -XXX,XX +XXX,XX @@ static void rv32_ibex_cpu_init(Object *obj)
  static void rv32_imafcu_nommu_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
 -    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
 +    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
      set_priv_version(env, PRIV_VERSION_1_10_0);
      set_resetvec(env, DEFAULT_RSTVEC);
      qdev_prop_set_bit(DEVICE(obj), "mmu", false);
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
      mcc->parent_reset(dev);
  #ifndef CONFIG_USER_ONLY
 +    env->misa_mxl = env->misa_mxl_max;
      env->priv = PRV_M;
      env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
      env->mcause = 0;
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
      CPURISCVState *env = &cpu->env;
      RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
      int priv_version = 0;
 -    target_ulong target_misa = env->misa;
      Error *local_err = NULL;
      cpu_exec_realizefn(cs, &local_err);
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
      set_resetvec(env, cpu->cfg.resetvec);
 -    /* If only XLEN is set for misa, then set misa from properties */
 -    if (env->misa == RV32 || env->misa == RV64) {
 +    /* Validate that MISA_MXL is set properly. */
 +    switch (env->misa_mxl_max) {
 +#ifdef TARGET_RISCV64
 +    case MXL_RV64:
 +        break;
 +#endif
 +    case MXL_RV32:
 +        break;
 +    default:
 +        g_assert_not_reached();
 +    }
 +    assert(env->misa_mxl_max == env->misa_mxl);
 +
 +    /* If only MISA_EXT is unset for misa, then set it from properties */
 +    if (env->misa_ext == 0) {
 +        uint32_t ext = 0;
 +
          /* Do some ISA extension error checking */
          if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
              error_setg(errp,
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
          /* Set the ISA extensions, checks should have happened above */
          if (cpu->cfg.ext_i) {
 -            target_misa |= RVI;
 +            ext |= RVI;
          }
          if (cpu->cfg.ext_e) {
 -            target_misa |= RVE;
 +            ext |= RVE;
          }
          if (cpu->cfg.ext_m) {
 -            target_misa |= RVM;
 +            ext |= RVM;
          }
          if (cpu->cfg.ext_a) {
 -            target_misa |= RVA;
 +            ext |= RVA;
          }
          if (cpu->cfg.ext_f) {
 -            target_misa |= RVF;
 +            ext |= RVF;
          }
          if (cpu->cfg.ext_d) {
 -            target_misa |= RVD;
 +            ext |= RVD;
          }
          if (cpu->cfg.ext_c) {
 -            target_misa |= RVC;
 +            ext |= RVC;
          }
          if (cpu->cfg.ext_s) {
 -            target_misa |= RVS;
 +            ext |= RVS;
          }
          if (cpu->cfg.ext_u) {
 -            target_misa |= RVU;
 +            ext |= RVU;
          }
          if (cpu->cfg.ext_h) {
 -            target_misa |= RVH;
 +            ext |= RVH;
          }
          if (cpu->cfg.ext_v) {
              int vext_version = VEXT_VERSION_0_07_1;
 -            target_misa |= RVV;
 +            ext |= RVV;
              if (!is_power_of_2(cpu->cfg.vlen)) {
                  error_setg(errp,
                          "Vector extension VLEN must be power of 2");
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
              set_vext_version(env, vext_version);
          }
 -        set_misa(env, target_misa);
 +        set_misa(env, env->misa_mxl, ext);
      }
      riscv_cpu_register_gdb_regs_for_features(cs);
@@ -XXX,XX +XXX,XX @@ char *riscv_isa_string(RISCVCPU *cpu)
      char *isa_str = g_new(char, maxlen);
      char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
      for (i = 0; i < sizeof(riscv_exts); i++) {
 -        if (cpu->env.misa & RV(riscv_exts[i])) {
 +        if (cpu->env.misa_ext & RV(riscv_exts[i])) {
              *p++ = qemu_tolower(riscv_exts[i]);
          }
      }
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
  {
  #if !defined(CONFIG_USER_ONLY)
      /* loose check condition for fcsr in vector extension */
 -    if ((csrno == CSR_FCSR) && (env->misa & RVV)) {
 +    if ((csrno == CSR_FCSR) && (env->misa_ext & RVV)) {
          return RISCV_EXCP_NONE;
      }
      if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
  static RISCVException vs(CPURISCVState *env, int csrno)
  {
 -    if (env->misa & RVV) {
 +    if (env->misa_ext & RVV) {
          return RISCV_EXCP_NONE;
      }
      return RISCV_EXCP_ILLEGAL_INST;
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno,
  static RISCVException read_misa(CPURISCVState *env, int csrno,
                                  target_ulong *val)
  {
 -    *val = env->misa;
 +    target_ulong misa;
 +
 +    switch (env->misa_mxl) {
 +    case MXL_RV32:
 +        misa = (target_ulong)MXL_RV32 << 30;
 +        break;
 +#ifdef TARGET_RISCV64
 +    case MXL_RV64:
 +        misa = (target_ulong)MXL_RV64 << 62;
 +        break;
 +#endif
 +    default:
 +        g_assert_not_reached();
 +    }
 +
-+    *val = misa | env->misa_ext;
++    cpu->decoders = dynamic_decoders;
-     return RISCV_EXCP_NONE;
++}
  }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
          return RISCV_EXCP_NONE;
      }
 +    /*
 +     * misa.MXL writes are not supported by QEMU.
 +     * Drop writes to those bits.
 +     */
 +
-     /* Mask extensions that are not supported by this hart */
+ bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
 -    val &= env->misa_mask;
 +    val &= env->misa_ext_mask;
      /* Mask extensions that are not supported by QEMU */
      val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
@@ -XXX,XX +XXX,XX @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
          val &= ~RVC;
      }
 -    /* misa.MXL writes are not supported by QEMU */
 -    if (riscv_cpu_is_32bit(env)) {
 -        val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL);
 -    } else {
 -        val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL);
 +    /* If nothing changed, do nothing. */
 +    if (val == env->misa_ext) {
 +        return RISCV_EXCP_NONE;
      }
      /* flush translation cache */
 -    if (val != env->misa) {
 -        tb_flush(env_cpu(env));
 -    }
 -
 -    env->misa = val;
 -
 +    tb_flush(env_cpu(env));
 +    env->misa_ext = val;
      return RISCV_EXCP_NONE;
  }
 diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/gdbstub.c
 +++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
  static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
  {
-     if (n < 32) {
+     return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
 -        if (env->misa & RVD) {
 +        if (env->misa_ext & RVD) {
              return gdb_get_reg64(buf, env->fpr[n]);
          }
 -        if (env->misa & RVF) {
 +        if (env->misa_ext & RVF) {
              return gdb_get_reg32(buf, env->fpr[n]);
          }
      /* there is hole between ft11 and fflags in fpu.xml */
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
  {
      RISCVCPU *cpu = RISCV_CPU(cs);
      CPURISCVState *env = &cpu->env;
 -    if (env->misa & RVD) {
 +    if (env->misa_ext & RVD) {
          gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
 , "riscv-64bit-fpu.xml", 0);
 -    } else if (env->misa & RVF) {
 +    } else if (env->misa_ext & RVF) {
          gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
 , "riscv-32bit-fpu.xml", 0);
      }
 diff --git a/target/riscv/machine.c b/target/riscv/machine.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/machine.c
 +++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_hyper = {
  const VMStateDescription vmstate_riscv_cpu = {
      .name = "cpu",
 -    .version_id = 2,
 -    .minimum_version_id = 2,
 +    .version_id = 3,
 +    .minimum_version_id = 3,
      .fields = (VMStateField[]) {
          VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
          VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
          VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
          VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
          VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
 -        VMSTATE_UINTTL(env.misa, RISCVCPU),
 -        VMSTATE_UINTTL(env.misa_mask, RISCVCPU),
 +        VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
 +        VMSTATE_UINT32(env.misa_ext, RISCVCPU),
 +        VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
 +        VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
          VMSTATE_UINT32(env.features, RISCVCPU),
          VMSTATE_UINTTL(env.priv, RISCVCPU),
          VMSTATE_UINTTL(env.virt, RISCVCPU),
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
+@@ -XXX,XX +XXX,XX @@
+ #include "exec/helper-info.c.inc"
+ #undef  HELPER_H
++#include "tcg/tcg-cpu.h"
++
+ /* global register indices */
+ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
+ static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
 @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
-     /* pc_succ_insn points to the instruction following base.pc_next */
+     /* FRM is known to contain a valid value. */
-     target_ulong pc_succ_insn;
+     bool frm_valid;
-     target_ulong priv_ver;
+     bool insn_start_updated;
--    target_ulong misa;
++    const GPtrArray *decoders;
-+    RISCVMXL xl;
+ } DisasContext;
 +    uint32_t misa_ext;
      uint32_t opcode;
      uint32_t mstatus_fs;
      uint32_t mstatus_hs_fs;
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
  static inline bool has_ext(DisasContext *ctx, uint32_t ext)
+@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
+     return (first_word & 3) == 3 ? 4 : 2;
+ }
++const RISCVDecoder decoder_table[] = {
++    { always_true_p, decode_insn32 },
++    { has_xthead_p, decode_xthead},
++    { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
++};
++
++const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
++
+ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
  {
--    return ctx->misa & ext;
+-    /*
-+    return ctx->misa_ext & ext;
+-     * A table with predicate (i.e., guard) functions and decoder functions
 -     * that are tested in-order until a decoder matches onto the opcode.
 -     */
 -    static const struct {
 -        bool (*guard_func)(const RISCVCPUConfig *);
 -        bool (*decode_func)(DisasContext *, uint32_t);
 -    } decoders[] = {
 -        { always_true_p,  decode_insn32 },
 -        { has_xthead_p, decode_xthead },
 -        { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
 -    };
 -
      ctx->virt_inst_excp = false;
      ctx->cur_insn_len = insn_len(opcode);
      /* Check for compressed insn */
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
                                               ctx->base.pc_next + 2));
          ctx->opcode = opcode32;
 -        for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
 -            if (decoders[i].guard_func(ctx->cfg_ptr) &&
 -                decoders[i].decode_func(ctx, opcode32)) {
 +        for (guint i = 0; i < ctx->decoders->len; ++i) {
 +            riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
 +            if (func(ctx, opcode32)) {
                  return;
              }
          }
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
      ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
      ctx->zero = tcg_constant_tl(0);
      ctx->virt_inst_excp = false;
 +    ctx->decoders = cpu->decoders;
  }
- #ifdef TARGET_RISCV32
+ static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
@@ -XXX,XX +XXX,XX @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
  #else
  static inline bool is_32bit(DisasContext *ctx)
  {
 -    return (ctx->misa & RV32) == RV32;
 +    return ctx->xl == MXL_RV32;
  }
  #endif
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
  #else
      ctx->virt_enabled = false;
  #endif
 -    ctx->misa = env->misa;
 +    ctx->xl = env->misa_mxl;
 +    ctx->misa_ext = env->misa_ext;
      ctx->frm = -1;  /* unknown rounding mode */
      ctx->ext_ifencei = cpu->cfg.ext_ifencei;
      ctx->vlen = cpu->cfg.vlen;
 --
-.31.1
+.45.1

-[PULL 12/33] target/riscv: Add MXL/SXL/UXL to TB_FLAGS
+[PULL 16/28] riscv: thead: Add th.sxstatus CSR emulation
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Christoph Müllner <christoph.muellner@vrull.eu>
-Begin adding support for switching XLEN at runtime.  Extract the
+The th.sxstatus CSR can be used to identify available custom extension
-effective XLEN from MISA and MSTATUS and store for use during translation.
+on T-Head CPUs. The CSR is documented here:
   https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc
-Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+An important property of this patch is, that the th.sxstatus MAEE field
 is not set (indicating that XTheadMae is not available).
 XTheadMae is a memory attribute extension (similar to Svpbmt) which is
 implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
 in PTEs that are marked as reserved. QEMU maintainers prefer to not
 implement XTheadMae, so we need give kernels a mechanism to identify
 if XTheadMae is available in a system or not. And this patch introduces
 this mechanism in QEMU in a way that's compatible with real HW
 (i.e., probing the th.sxstatus.MAEE bit).
 Further context can be found on the list:
 https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html
 Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
-Message-id: 20211020031709.359469-6-richard.henderson@linaro.org
+Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h        |  2 ++
+ MAINTAINERS              |  1 +
- target/riscv/cpu.c        |  8 ++++++++
+ target/riscv/cpu.h       |  3 ++
- target/riscv/cpu_helper.c | 33 +++++++++++++++++++++++++++++++++
+ target/riscv/cpu.c       |  1 +
- target/riscv/csr.c        |  3 +++
+ target/riscv/th_csr.c    | 79 ++++++++++++++++++++++++++++++++++++++++
- target/riscv/translate.c  |  2 +-
+ target/riscv/meson.build |  1 +
-files changed, 47 insertions(+), 1 deletion(-)
+files changed, 85 insertions(+)
  create mode 100644 target/riscv/th_csr.c
+diff --git a/MAINTAINERS b/MAINTAINERS
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
+ S: Supported
+ F: target/riscv/insn_trans/trans_xthead.c.inc
+ F: target/riscv/xthead*.decode
++F: target/riscv/th_*
+ F: disas/riscv-xthead*
+ RISC-V XVentanaCondOps extension
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, VILL, 9, 1)
+@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
- /* Is a Hypervisor instruction load/store allowed? */
+ uint8_t satp_mode_max_from_map(uint32_t map);
- FIELD(TB_FLAGS, HLSX, 10, 1)
+ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
- FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2)
-+/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
++/* Implemented in th_csr.c */
-+FIELD(TB_FLAGS, XL, 13, 2)
++void th_register_custom_csrs(RISCVCPU *cpu);
++
- #ifdef TARGET_RISCV32
+ #endif /* RISCV_CPU_H */
  #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
+@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
-     env->misa_mxl = env->misa_mxl_max;
+     cpu->cfg.mvendorid = THEAD_VENDOR_ID;
-     env->priv = PRV_M;
+ #ifndef CONFIG_USER_ONLY
-     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
+     set_satp_mode_max_supported(cpu, VM_1_10_SV39);
-+    if (env->misa_mxl > MXL_RV32) {
++    th_register_custom_csrs(cpu);
-+        /*
+ #endif
-+         * The reset status of SXL/UXL is undefined, but mstatus is WARL
-+         * and we must ensure that the value after init is valid for read.
+     /* inherited from parent obj via riscv_cpu_init() */
-+         */
+diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
-+        env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
+new file mode 100644
-+        env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
+index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/target/riscv/th_csr.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * T-Head-specific CSRs.
 + *
 + * Copyright (c) 2024 VRULL GmbH
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 + * This program is distributed in the hope it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 + * more details.
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "cpu.h"
 +#include "cpu_vendorid.h"
 +
 +#define CSR_TH_SXSTATUS 0x5c0
 +
 +/* TH_SXSTATUS bits */
 +#define TH_SXSTATUS_UCME        BIT(16)
 +#define TH_SXSTATUS_MAEE        BIT(21)
 +#define TH_SXSTATUS_THEADISAEE  BIT(22)
 +
 +typedef struct {
 +    int csrno;
 +    int (*insertion_test)(RISCVCPU *cpu);
 +    riscv_csr_operations csr_ops;
 +} riscv_csr;
 +
 +static RISCVException smode(CPURISCVState *env, int csrno)
 +{
 +    if (riscv_has_ext(env, RVS)) {
 +        return RISCV_EXCP_NONE;
 +    }
-     env->mcause = 0;
++
-     env->pc = env->resetvec;
++    return RISCV_EXCP_ILLEGAL_INST;
-     env->two_stage_lookup = false;
++}
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
++
-index XXXXXXX..XXXXXXX 100644
++static int test_thead_mvendorid(RISCVCPU *cpu)
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
  #endif
  }
 +static RISCVMXL cpu_get_xl(CPURISCVState *env)
 +{
-+#if defined(TARGET_RISCV32)
++    if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
-+    return MXL_RV32;
++        return -1;
-+#elif defined(CONFIG_USER_ONLY)
++    }
 +    return MXL_RV64;
 +#else
 +    RISCVMXL xl = riscv_cpu_mxl(env);
 +
-+    /*
++    return 0;
-+     * When emulating a 32-bit-only cpu, use RV32.
++}
-+     * When emulating a 64-bit cpu, and MXL has been reduced to RV32,
++
-+     * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened
++static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
-+     * back to RV64 for lower privs.
++                                       target_ulong *val)
-+     */
++{
-+    if (xl != MXL_RV32) {
++    /* We don't set MAEE here, because QEMU does not implement MAEE. */
-+        switch (env->priv) {
++    *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
-+        case PRV_M:
++    return RISCV_EXCP_NONE;
-+            break;
++}
-+        case PRV_U:
++
-+            xl = get_field(env->mstatus, MSTATUS64_UXL);
++static riscv_csr th_csr_list[] = {
-+            break;
++    {
-+        default: /* PRV_S | PRV_H */
++        .csrno = CSR_TH_SXSTATUS,
-+            xl = get_field(env->mstatus, MSTATUS64_SXL);
++        .insertion_test = test_thead_mvendorid,
-+            break;
++        .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
 +    }
 +};
 +
 +void th_register_custom_csrs(RISCVCPU *cpu)
 +{
 +    for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
 +        int csrno = th_csr_list[i].csrno;
 +        riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
 +        if (!th_csr_list[i].insertion_test(cpu)) {
 +            riscv_set_csr_ops(csrno, csr_ops);
 +        }
 +    }
-+    return xl;
-+#endif
 +}
-+
+diff --git a/target/riscv/meson.build b/target/riscv/meson.build
  void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
                            target_ulong *cs_base, uint32_t *pflags)
  {
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
      }
  #endif
 +    flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env));
 +
      *pflags = flags;
  }
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+--- a/target/riscv/meson.build
-+++ b/target/riscv/csr.c
++++ b/target/riscv/meson.build
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
+@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
-         mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
+   'monitor.c',
-     } else {
+   'machine.c',
-         mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
+   'pmu.c',
-+        /* SXL and UXL fields are for now read only */
++  'th_csr.c',
-+        mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
+   'time_helper.c',
-+        mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
+   'riscv-qmp-cmds.c',
-     }
+ ))
      env->mstatus = mstatus;
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
  #else
      ctx->virt_enabled = false;
  #endif
 -    ctx->xl = env->misa_mxl;
      ctx->misa_ext = env->misa_ext;
      ctx->frm = -1;  /* unknown rounding mode */
      ctx->ext_ifencei = cpu->cfg.ext_ifencei;
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
      ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
      ctx->mlen = 1 << (ctx->sew  + 3 - ctx->lmul);
      ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
 +    ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
      ctx->cs = cs;
      ctx->w = false;
      ctx->ntemp = 0;
 --
-.31.1
+.45.1

-[PULL 14/33] target/riscv: Properly check SEW in amo_op
+[PULL 17/28] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Max Chou <max.chou@sifive.com>
-We're currently assuming SEW <= 3, and the "else" from
+According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
-the SEW == 3 must be less.  Use a switch and explicitly
+instructions will be affected by Zvfhmin extension.
-bound both SEW and SEQ for all cases.
+And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
 conversions of
-Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+* From 1*SEW(16/32) to 2*SEW(32/64)
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+* From 2*SEW(32/64) to 1*SEW(16/32)
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20211020031709.359469-8-richard.henderson@linaro.org
+Signed-off-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvv.c.inc | 26 +++++++++++++------------
+ target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
-file changed, 14 insertions(+), 12 deletions(-)
+file changed, 18 insertions(+), 2 deletions(-)
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
+@@ -XXX,XX +XXX,XX @@ static bool require_rvf(DisasContext *s)
-         gen_helper_exit_atomic(cpu_env);
+     }
-         s->base.is_jmp = DISAS_NORETURN;
+ }
-         return true;
--    } else {
++static bool require_rvfmin(DisasContext *s)
--        if (s->sew == 3) {
++{
--            if (!is_32bit(s)) {
++    if (s->mstatus_fs == EXT_STATUS_DISABLED) {
--                fn = fnsd[seq];
++        return false;
 -            } else {
 -                /* Check done in amo_check(). */
 -                g_assert_not_reached();
 -            }
 -        } else {
 -            assert(seq < ARRAY_SIZE(fnsw));
 -            fn = fnsw[seq];
 -        }
 +    }
 +
 +    switch (s->sew) {
-+    case 0 ... 2:
++    case MO_16:
-+        assert(seq < ARRAY_SIZE(fnsw));
++        return s->cfg_ptr->ext_zvfhmin;
-+        fn = fnsw[seq];
++    case MO_32:
-+        break;
++        return s->cfg_ptr->ext_zve32f;
 +    case 3:
 +        /* XLEN check done in amo_check(). */
 +        assert(seq < ARRAY_SIZE(fnsd));
 +        fn = fnsd[seq];
 +        break;
 +    default:
-+        g_assert_not_reached();
++        return false;
 +    }
 +}
 +
  static bool require_scale_rvf(DisasContext *s)
  {
      if (s->mstatus_fs == EXT_STATUS_DISABLED) {
@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvfmin(DisasContext *s)
      }
-     data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+     switch (s->sew) {
 -    case MO_8:
 -        return s->cfg_ptr->ext_zvfhmin;
      case MO_16:
          return s->cfg_ptr->ext_zve32f;
      case MO_32:
@@ -XXX,XX +XXX,XX @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
  static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
  {
      return opfv_widen_check(s, a) &&
 +           require_rvfmin(s) &&
             require_scale_rvfmin(s) &&
             (s->sew != MO_8);
  }
@@ -XXX,XX +XXX,XX @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
  static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
  {
      return opfv_narrow_check(s, a) &&
 +           require_rvfmin(s) &&
             require_scale_rvfmin(s) &&
             (s->sew != MO_8);
  }
 --
-.31.1
+.45.1

-[PULL 13/33] target/riscv: Use REQUIRE_64BIT in amo_check64
+[PULL 18/28] target/riscv: rvv: Check single width operator for vector fp widen instructions
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Max Chou <max.chou@sifive.com>
-Use the same REQUIRE_64BIT check that we use elsewhere,
+The require_scale_rvf function only checks the double width operator for
-rather than open-coding the use of is_32bit.
+the vector floating point widen instructions, so most of the widen
 checking functions need to add require_rvf for single width operator.
-Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+integer to double width float, so the opfxv_widen_check function doesn’t
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+need require_rvf for the single width operator(integer).
-Message-id: 20211020031709.359469-7-richard.henderson@linaro.org
 Signed-off-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
+ target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
-file changed, 2 insertions(+), 1 deletion(-)
+file changed, 5 insertions(+)
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool amo_check(DisasContext *s, arg_rwdvm* a)
+@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_TRANS(vfrsub_vf,  opfvf_check)
+ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
  static bool amo_check64(DisasContext *s, arg_rwdvm* a)
  {
--    return !is_32bit(s) && amo_check(s, a);
+     return require_rvv(s) &&
-+    REQUIRE_64BIT(s);
++           require_rvf(s) &&
-+    return amo_check(s, a);
+            require_scale_rvf(s) &&
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
  static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return require_rvv(s) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
  static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return require_rvv(s) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
@@ -XXX,XX +XXX,XX @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
  static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return require_rvv(s) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
  static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return reduction_widen_check(s, a) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8);
  }
- GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
 --
-.31.1
+.45.1

-[PULL 01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v
+[PULL 19/28] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
-From: Frank Chang <frank.chang@sifive.com>
+From: Max Chou <max.chou@sifive.com>
-oprsz and maxsz are passed with the same value in commit: eee2d61e202.
+The opfv_narrow_check needs to check the single width float operator by
-However, vmv.v.v was missed in that commit and should pass the same
+require_rvf.
 value as well in its tcg_gen_gvec_2_ptr() call.
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Signed-off-by: Max Chou <max.chou@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Message-id: 20211007081803.1705656-1-frank.chang@sifive.com
+Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240322092600.1198921-4-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
+ target/riscv/insn_trans/trans_rvv.c.inc | 1 +
-file changed, 2 insertions(+), 1 deletion(-)
+file changed, 1 insertion(+)
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
+@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
-             tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
+ {
-             tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
+     return opfv_narrow_check(s, a) &&
--                               cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
++           require_rvf(s) &&
-+                               cpu_env, s->vlen / 8, s->vlen / 8, data,
+            require_scale_rvf(s) &&
-+                               fns[s->sew]);
+            (s->sew != MO_8);
-             gen_set_label(over);
+ }
          }
          return true;
 --
-.31.1
+.45.1

-[PULL 17/33] target/riscv: Use gen_arith_per_ol for RVM
+[PULL 20/28] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Max Chou <max.chou@sifive.com>
-The multiply high-part instructions require a separate
+If the checking functions check both the single and double width
-implementation for RV32 when TARGET_LONG_BITS == 64.
+operators at the same time, then the single width operator checking
 functions (require_rvf[min]) will check whether the SEW is 8.
-Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Signed-off-by: Max Chou <max.chou@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Message-id: 20211020031709.359469-11-richard.henderson@linaro.org
+Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c                | 16 +++++++++++++++
+ target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
- target/riscv/insn_trans/trans_rvm.c.inc | 26 ++++++++++++++++++++++---
+file changed, 4 insertions(+), 12 deletions(-)
 files changed, 39 insertions(+), 3 deletions(-)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/translate.c
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
+@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
-     return true;
+     return require_rvv(s) &&
             require_rvf(s) &&
             require_scale_rvf(s) &&
 -           (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
             vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
  }
+@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
-+static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext,
+     return require_rvv(s) &&
-+                             void (*f_tl)(TCGv, TCGv, TCGv),
+            require_rvf(s) &&
-+                             void (*f_32)(TCGv, TCGv, TCGv))
+            require_scale_rvf(s) &&
-+{
+-           (s->sew != MO_8) &&
-+    int olen = get_olen(ctx);
+            vext_check_isa_ill(s) &&
-+
+            vext_check_ds(s, a->rd, a->rs2, a->vm);
-+    if (olen != TARGET_LONG_BITS) {
+ }
-+        if (olen == 32) {
+@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
-+            f_tl = f_32;
+     return require_rvv(s) &&
-+        } else {
+            require_rvf(s) &&
-+            g_assert_not_reached();
+            require_scale_rvf(s) &&
-+        }
+-           (s->sew != MO_8) &&
-+    }
+            vext_check_isa_ill(s) &&
-+    return gen_arith(ctx, a, ext, f_tl);
+            vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
-+}
+ }
-+
+@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
- static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
+     return require_rvv(s) &&
-                              void (*func)(TCGv, TCGv, target_long))
+            require_rvf(s) &&
             require_scale_rvf(s) &&
 -           (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
             vext_check_dd(s, a->rd, a->rs2, a->vm);
  }
@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
  {
-diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
+     return opfv_widen_check(s, a) &&
-index XXXXXXX..XXXXXXX 100644
+            require_rvfmin(s) &&
---- a/target/riscv/insn_trans/trans_rvm.c.inc
+-           require_scale_rvfmin(s) &&
-+++ b/target/riscv/insn_trans/trans_rvm.c.inc
+-           (s->sew != MO_8);
-@@ -XXX,XX +XXX,XX @@ static void gen_mulh(TCGv ret, TCGv s1, TCGv s2)
++           require_scale_rvfmin(s);
      tcg_temp_free(discard);
  }
-+static void gen_mulh_w(TCGv ret, TCGv s1, TCGv s2)
+ #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
-+{
+@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
 +    tcg_gen_mul_tl(ret, s1, s2);
 +    tcg_gen_sari_tl(ret, ret, 32);
 +}
 +
  static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
  {
-     REQUIRE_EXT(ctx, RVM);
+     return opfv_narrow_check(s, a) &&
--    return gen_arith(ctx, a, EXT_NONE, gen_mulh);
+            require_rvfmin(s) &&
-+    return gen_arith_per_ol(ctx, a, EXT_SIGN, gen_mulh, gen_mulh_w);
+-           require_scale_rvfmin(s) &&
 -           (s->sew != MO_8);
 +           require_scale_rvfmin(s);
  }
- static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
+ static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
-@@ -XXX,XX +XXX,XX @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
+ {
-     tcg_temp_free(rh);
+     return opfv_narrow_check(s, a) &&
             require_rvf(s) &&
 -           require_scale_rvf(s) &&
 -           (s->sew != MO_8);
 +           require_scale_rvf(s);
  }
-+static void gen_mulhsu_w(TCGv ret, TCGv arg1, TCGv arg2)
+ #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
-+{
+@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
 +    TCGv t1 = tcg_temp_new();
 +    TCGv t2 = tcg_temp_new();
 +
 +    tcg_gen_ext32s_tl(t1, arg1);
 +    tcg_gen_ext32u_tl(t2, arg2);
 +    tcg_gen_mul_tl(ret, t1, t2);
 +    tcg_temp_free(t1);
 +    tcg_temp_free(t2);
 +    tcg_gen_sari_tl(ret, ret, 32);
 +}
 +
  static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
  {
-     REQUIRE_EXT(ctx, RVM);
+     return reduction_widen_check(s, a) &&
--    return gen_arith(ctx, a, EXT_NONE, gen_mulhsu);
+            require_rvf(s) &&
-+    return gen_arith_per_ol(ctx, a, EXT_NONE, gen_mulhsu, gen_mulhsu_w);
+-           require_scale_rvf(s) &&
 -           (s->sew != MO_8);
 +           require_scale_rvf(s);
  }
- static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
+ GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
@@ -XXX,XX +XXX,XX @@ static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
  static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
  {
      REQUIRE_EXT(ctx, RVM);
 -    return gen_arith(ctx, a, EXT_NONE, gen_mulhu);
 +    /* gen_mulh_w works for either sign as input. */
 +    return gen_arith_per_ol(ctx, a, EXT_ZERO, gen_mulhu, gen_mulh_w);
  }
  static void gen_div(TCGv ret, TCGv source1, TCGv source2)
 --
-.31.1
+.45.1

-[PULL 28/33] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
+[PULL 21/28] target/riscv: prioritize pmp errors in raise_mmu_exception()
-From: Bin Meng <bmeng.cn@gmail.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Using memory_region_init_ram(), which can't possibly handle vhost-user,
+raise_mmu_exception(), as is today, is prioritizing guest page faults by
-and can't work as expected with '-numa node,memdev' options.
+checking first if virt_enabled && !first_stage, and then considering the
 regular inst/load/store faults.
-Use MachineState::ram instead of manually initializing RAM memory
+There's no mention in the spec about guest page fault being a higher
-region, as well as by providing MachineClass::default_ram_id to
+priority that PMP faults. In fact, privileged spec section 3.7.1 says:
 opt in to memdev scheme.
-Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
+"Attempting to fetch an instruction from a PMP region that does not have
 execute permissions raises an instruction access-fault exception.
 Attempting to execute a load or load-reserved instruction which accesses
 a physical address within a PMP region without read permissions raises a
 load access-fault exception. Attempting to execute a store,
 store-conditional, or AMO instruction which accesses a physical address
 within a PMP region without write permissions raises a store
 access-fault exception."
 So, in fact, we're doing it wrong - PMP faults should always be thrown,
 regardless of also being a first or second stage fault.
 The way riscv_cpu_tlb_fill() and get_physical_address() work is
 adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
 reflected in the 'pmp_violation' flag. What we need is to change
 raise_mmu_exception() to prioritize it.
 Reported-by: Joseph Chan <jchan@ventanamicro.com>
 Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Igor Mammedov <imammedo@redhat.com>
+Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
-Message-id: 20211020014112.7336-2-bmeng.cn@gmail.com
+Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/microchip_pfsoc.c | 36 ++++++++++++++++++++----------------
+ target/riscv/cpu_helper.c | 22 ++++++++++++----------
-file changed, 20 insertions(+), 16 deletions(-)
+file changed, 12 insertions(+), 10 deletions(-)
-diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/microchip_pfsoc.c
+--- a/target/riscv/cpu_helper.c
-+++ b/hw/riscv/microchip_pfsoc.c
++++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
-     MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1);
-     MemoryRegion *mem_high = g_new(MemoryRegion, 1);
+     switch (access_type) {
-     MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1);
+     case MMU_INST_FETCH:
--    uint64_t mem_high_size;
+-        if (env->virt_enabled && !first_stage) {
-+    uint64_t mem_low_size, mem_high_size;
++        if (pmp_violation) {
-     hwaddr firmware_load_addr;
++            cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
-     const char *firmware_name;
++        } else if (env->virt_enabled && !first_stage) {
-     bool kernel_as_payload = false;
+             cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
-@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
+         } else {
-                             TYPE_MICROCHIP_PFSOC);
+-            cs->exception_index = pmp_violation ?
-     qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
+-                RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
++            cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
-+    /* Split RAM into low and high regions using aliases to machine->ram */
+         }
-+    mem_low_size = memmap[MICROCHIP_PFSOC_DRAM_LO].size;
+         break;
-+    mem_high_size = machine->ram_size - mem_low_size;
+     case MMU_DATA_LOAD:
-+    memory_region_init_alias(mem_low, NULL,
+-        if (two_stage && !first_stage) {
-+                             "microchip.icicle.kit.ram_low", machine->ram,
++        if (pmp_violation) {
-+                             0, mem_low_size);
++            cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
-+    memory_region_init_alias(mem_high, NULL,
++        } else if (two_stage && !first_stage) {
-+                             "microchip.icicle.kit.ram_high", machine->ram,
+             cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
-+                             mem_low_size, mem_high_size);
+         } else {
-+
+-            cs->exception_index = pmp_violation ?
-     /* Register RAM */
+-                RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
--    memory_region_init_ram(mem_low, NULL, "microchip.icicle.kit.ram_low",
++            cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
--                           memmap[MICROCHIP_PFSOC_DRAM_LO].size,
+         }
--                           &error_fatal);
+         break;
--    memory_region_init_alias(mem_low_alias, NULL,
+     case MMU_DATA_STORE:
--                             "microchip.icicle.kit.ram_low.alias",
+-        if (two_stage && !first_stage) {
--                             mem_low, 0,
++        if (pmp_violation) {
--                             memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].size);
++            cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
-     memory_region_add_subregion(system_memory,
++        } else if (two_stage && !first_stage) {
-                                 memmap[MICROCHIP_PFSOC_DRAM_LO].base,
+             cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
-                                 mem_low);
+         } else {
-+    memory_region_add_subregion(system_memory,
+-            cs->exception_index = pmp_violation ?
-+                                memmap[MICROCHIP_PFSOC_DRAM_HI].base,
+-                RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
-+                                mem_high);
+-                RISCV_EXCP_STORE_PAGE_FAULT;
-+
++            cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
-+    /* Create aliases for the low and high RAM regions */
+         }
-+    memory_region_init_alias(mem_low_alias, NULL,
+         break;
-+                             "microchip.icicle.kit.ram_low.alias",
+     default:
 +                             mem_low, 0, mem_low_size);
      memory_region_add_subregion(system_memory,
                                  memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base,
                                  mem_low_alias);
 -
 -    mem_high_size = machine->ram_size - 1 * GiB;
 -
 -    memory_region_init_ram(mem_high, NULL, "microchip.icicle.kit.ram_high",
 -                           mem_high_size, &error_fatal);
      memory_region_init_alias(mem_high_alias, NULL,
                               "microchip.icicle.kit.ram_high.alias",
                               mem_high, 0, mem_high_size);
 -    memory_region_add_subregion(system_memory,
 -                                memmap[MICROCHIP_PFSOC_DRAM_HI].base,
 -                                mem_high);
      memory_region_add_subregion(system_memory,
                                  memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base,
                                  mem_high_alias);
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
                     MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
      mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
      mc->default_cpus = mc->min_cpus;
 +    mc->default_ram_id = "microchip.icicle.kit.ram";
      /*
       * Map 513 MiB high memory, the mimimum required high memory size, because
 --
-.31.1
+.45.1

-[PULL 22/33] target/riscv: Compute mstatus.sd on demand
+[PULL 22/28] target/riscv: do not set mtval2 for non guest-page faults
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Alexei Filippov <alexei.filippov@syntacore.com>
-The position of this read-only field is dependent on the current xlen.
+Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
-Rather than having to compute that difference in many places, compute
+setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
-it only on read.
+translation part, mtval2 will be set in case of successes 2 stage translation but
 failed pmp check.
+In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
+riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
+should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
+page-fault is taken into M-mode, mtval2 is written with either zero or guest
+physical address that faulted, shifted by 2 bits. *For other traps, mtval2
+is set to zero...*
+Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
-Message-id: 20211020031709.359469-16-richard.henderson@linaro.org
+Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c |  3 +--
+ target/riscv/cpu_helper.c | 12 ++++++------
- target/riscv/csr.c        | 37 ++++++++++++++++++++++---------------
+file changed, 6 insertions(+), 6 deletions(-)
  target/riscv/translate.c  |  5 ++---
 files changed, 25 insertions(+), 20 deletions(-)
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+                               __func__, pa, ret, prot_pmp, tlb_size);
- void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
- {
+                 prot &= prot_pmp;
--    uint64_t sd = riscv_cpu_mxl(env) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
+-            }
      uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
                              MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
 -                            MSTATUS64_UXL | sd;
 +                            MSTATUS64_UXL;
      bool current_virt = riscv_cpu_virt_enabled(env);
      g_assert(riscv_has_ext(env, RVH));
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException read_mhartid(CPURISCVState *env, int csrno,
  }
  /* Machine Trap Setup */
 +
 +/* We do not store SD explicitly, only compute it on demand. */
 +static uint64_t add_status_sd(RISCVMXL xl, uint64_t status)
 +{
 +    if ((status & MSTATUS_FS) == MSTATUS_FS ||
 +        (status & MSTATUS_XS) == MSTATUS_XS) {
 +        switch (xl) {
 +        case MXL_RV32:
 +            return status | MSTATUS32_SD;
 +        case MXL_RV64:
 +            return status | MSTATUS64_SD;
 +        default:
 +            g_assert_not_reached();
 +        }
 +    }
 +    return status;
 +}
 +
  static RISCVException read_mstatus(CPURISCVState *env, int csrno,
                                     target_ulong *val)
  {
 -    *val = env->mstatus;
 +    *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus);
      return RISCV_EXCP_NONE;
  }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
  {
      uint64_t mstatus = env->mstatus;
      uint64_t mask = 0;
 -    int dirty;
      /* flush tlb on mstatus fields that affect VM */
      if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
      mstatus = (mstatus & ~mask) | (val & mask);
 -    dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
 -            ((mstatus & MSTATUS_XS) == MSTATUS_XS);
 -    if (riscv_cpu_mxl(env) == MXL_RV32) {
 -        mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
 -    } else {
 -        mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
 +    if (riscv_cpu_mxl(env) == MXL_RV64) {
          /* SXL and UXL fields are for now read only */
          mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
          mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
  {
      target_ulong mask = (sstatus_v1_10_mask);
 -    if (riscv_cpu_mxl(env) == MXL_RV32) {
 -        mask |= SSTATUS32_SD;
 -    } else {
 -        mask |= SSTATUS64_SD;
 -    }
 -
--    *val = env->mstatus & mask;
+-            if (ret != TRANSLATE_SUCCESS) {
-+    /* TODO: Use SXL not MXL. */
++            } else {
-+    *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
+                 /*
-     return RISCV_EXCP_NONE;
+                  * Guest physical address translation failed, this is a HS
- }
+                  * level exception
+                  */
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+                 first_stage_error = false;
-index XXXXXXX..XXXXXXX 100644
+-                env->guest_phys_fault_addr = (im_address |
---- a/target/riscv/translate.c
+-                                              (address &
-+++ b/target/riscv/translate.c
+-                                               (TARGET_PAGE_SIZE - 1))) >> 2;
-@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
++                if (ret != TRANSLATE_PMP_FAIL) {
- static void mark_fs_dirty(DisasContext *ctx)
++                    env->guest_phys_fault_addr = (im_address |
- {
++                                                  (address &
-     TCGv tmp;
++                                                   (TARGET_PAGE_SIZE - 1))) >> 2;
--    target_ulong sd = get_xl(ctx) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
++                }
+             }
-     if (ctx->mstatus_fs != MSTATUS_FS) {
+         }
-         /* Remember the state change for the rest of the TB. */
+     } else {
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
          tmp = tcg_temp_new();
          tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
 -        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
 +        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
          tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
          tcg_temp_free(tmp);
      }
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
          tmp = tcg_temp_new();
          tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
 -        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
 +        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
          tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
          tcg_temp_free(tmp);
      }
 --
-.31.1
+.45.1

-[PULL 02/33] target/riscv: line up all of the registers in the info register dump
+[PULL 23/28] target/riscv: Remove experimental prefix from "B" extension
-From: Travis Geiselbrecht <travisg@gmail.com>
+From: Rob Bradford <rbradford@rivosinc.com>
-Ensure the columns for all of the register names and values line up.
+This extension has now been ratified:
-No functional change, just a minor tweak to the output.
+https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
 removed.
-Signed-off-by: Travis Geiselbrecht <travisg@gmail.com>
+Since this is now a ratified extension add it to the list of extensions
 included in the "max" CPU variant.
 Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20211009055019.545153-1-travisg@gmail.com
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.c | 10 +++++-----
+ target/riscv/cpu.c         | 2 +-
-file changed, 5 insertions(+), 5 deletions(-)
+ target/riscv/tcg/tcg-cpu.c | 2 +-
 files changed, 2 insertions(+), 2 deletions(-)
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
+@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
-     }
+     MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
-     if (riscv_has_ext(env, RVH)) {
+     MISA_EXT_INFO(RVV, "v", "Vector operations"),
-         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
+     MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
--        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ",
+-    MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
-+        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus",
++    MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
-                      (target_ulong)env->vsstatus);
+ };
-     }
-     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
+ static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
-     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval   ", env->mtval);
+index XXXXXXX..XXXXXXX 100644
-     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval   ", env->stval);
+--- a/target/riscv/tcg/tcg-cpu.c
-     if (riscv_has_ext(env, RVH)) {
++++ b/target/riscv/tcg/tcg-cpu.c
--        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
+@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
--        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
+     const RISCVCPUMultiExtConfig *prop;
-+        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval   ", env->htval);
-+        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2  ", env->mtval2);
+     /* Enable RVG, RVJ and RVV that are disabled by default */
-     }
+-    riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
-     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch);
++    riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
-     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch);
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
+     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
- #endif
+         isa_ext_update_enabled(cpu, prop->offset, true);
      for (i = 0; i < 32; i++) {
 -        qemu_fprintf(f, " %s " TARGET_FMT_lx,
 +        qemu_fprintf(f, " %-8s " TARGET_FMT_lx,
                       riscv_int_regnames[i], env->gpr[i]);
          if ((i & 3) == 3) {
              qemu_fprintf(f, "\n");
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
      }
      if (flags & CPU_DUMP_FPU) {
          for (i = 0; i < 32; i++) {
 -            qemu_fprintf(f, " %s %016" PRIx64,
 +            qemu_fprintf(f, " %-8s %016" PRIx64,
                           riscv_fpr_regnames[i], env->fpr[i]);
              if ((i & 3) == 3) {
                  qemu_fprintf(f, "\n");
 --
-.31.1
+.45.1

-[PULL 20/33] target/riscv: Use gen_shift*_per_ol for RVB, RVI
+[PULL 24/28] target/riscv: rvzicbo: Fixup CBO extension register calculation
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Alistair Francis <alistair23@gmail.com>
-Most shift instructions require a separate implementation
+When running the instruction
 for RV32 when TARGET_LONG_BITS == 64.
-Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+```
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+    cbo.flush 0(x0)
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+```
-Message-id: 20211020031709.359469-14-richard.henderson@linaro.org
 QEMU would segfault.
 The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
 allocated.
 In order to fix this let's use the existing get_address()
 helper. This also has the benefit of performing pointer mask
 calculations on the address specified in rs1.
 The pointer masking specificiation specifically states:
 """
 Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
 """
 So this is the correct behaviour and we previously have been incorrectly
 not masking the address.
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
 Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c                | 31 +++++++++
+ target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
- target/riscv/insn_trans/trans_rvb.c.inc | 92 ++++++++++++++-----------
+file changed, 12 insertions(+), 4 deletions(-)
  target/riscv/insn_trans/trans_rvi.c.inc | 26 +++----
 files changed, 97 insertions(+), 52 deletions(-)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
-+++ b/target/riscv/translate.c
++++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
+@@ -XXX,XX +XXX,XX @@
  static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
  {
      REQUIRE_ZICBOM(ctx);
 -    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
 +    TCGv src = get_address(ctx, a->rs1, 0);
 +
 +    gen_helper_cbo_clean_flush(tcg_env, src);
      return true;
  }
-+static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a,
+ static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
-+                                    DisasExtend ext,
+ {
-+                                    void (*f_tl)(TCGv, TCGv, target_long),
+     REQUIRE_ZICBOM(ctx);
-+                                    void (*f_32)(TCGv, TCGv, target_long))
+-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
-+{
++    TCGv src = get_address(ctx, a->rs1, 0);
 +    int olen = get_olen(ctx);
 +    if (olen != TARGET_LONG_BITS) {
 +        if (olen == 32) {
 +            f_tl = f_32;
 +        } else {
 +            g_assert_not_reached();
 +        }
 +    }
 +    return gen_shift_imm_fn(ctx, a, ext, f_tl);
 +}
 +
- static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext,
++    gen_helper_cbo_clean_flush(tcg_env, src);
                               void (*func)(TCGv, TCGv, TCGv))
  {
@@ -XXX,XX +XXX,XX @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
      return true;
  }
-+static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext,
+ static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
-+                             void (*f_tl)(TCGv, TCGv, TCGv),
+ {
-+                             void (*f_32)(TCGv, TCGv, TCGv))
+     REQUIRE_ZICBOM(ctx);
-+{
+-    gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
-+    int olen = get_olen(ctx);
++    TCGv src = get_address(ctx, a->rs1, 0);
 +    if (olen != TARGET_LONG_BITS) {
 +        if (olen == 32) {
 +            f_tl = f_32;
 +        } else {
 +            g_assert_not_reached();
 +        }
 +    }
 +    return gen_shift(ctx, a, ext, f_tl);
 +}
 +
- static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
++    gen_helper_cbo_inval(tcg_env, src);
-                       void (*func)(TCGv, TCGv))
+     return true;
  }
  static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
  {
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
+     REQUIRE_ZICBOZ(ctx);
-index XXXXXXX..XXXXXXX 100644
+-    gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
---- a/target/riscv/insn_trans/trans_rvb.c.inc
++    TCGv src = get_address(ctx, a->rs1, 0);
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
++
-@@ -XXX,XX +XXX,XX @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
++    gen_helper_cbo_zero(tcg_env, src);
-     return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
+     return true;
  }
-+static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
-+{
-+    TCGv_i32 t1 = tcg_temp_new_i32();
-+    TCGv_i32 t2 = tcg_temp_new_i32();
-+
-+    /* truncate to 32-bits */
-+    tcg_gen_trunc_tl_i32(t1, arg1);
-+    tcg_gen_trunc_tl_i32(t2, arg2);
-+
-+    tcg_gen_rotr_i32(t1, t1, t2);
-+
-+    /* sign-extend 64-bits */
-+    tcg_gen_ext_i32_tl(ret, t1);
-+
-+    tcg_temp_free_i32(t1);
-+    tcg_temp_free_i32(t2);
-+}
-+
- static bool trans_ror(DisasContext *ctx, arg_ror *a)
- {
-     REQUIRE_ZBB(ctx);
--    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
-+    return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw);
-+}
-+
-+static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt)
-+{
-+    TCGv_i32 t1 = tcg_temp_new_i32();
-+
-+    tcg_gen_trunc_tl_i32(t1, arg1);
-+    tcg_gen_rotri_i32(t1, t1, shamt);
-+    tcg_gen_ext_i32_tl(ret, t1);
-+
-+    tcg_temp_free_i32(t1);
- }
- static bool trans_rori(DisasContext *ctx, arg_rori *a)
- {
-     REQUIRE_ZBB(ctx);
--    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
-+    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
-+                                   tcg_gen_rotri_tl, gen_roriw);
-+}
-+
-+static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
-+{
-+    TCGv_i32 t1 = tcg_temp_new_i32();
-+    TCGv_i32 t2 = tcg_temp_new_i32();
-+
-+    /* truncate to 32-bits */
-+    tcg_gen_trunc_tl_i32(t1, arg1);
-+    tcg_gen_trunc_tl_i32(t2, arg2);
-+
-+    tcg_gen_rotl_i32(t1, t1, t2);
-+
-+    /* sign-extend 64-bits */
-+    tcg_gen_ext_i32_tl(ret, t1);
-+
-+    tcg_temp_free_i32(t1);
-+    tcg_temp_free_i32(t2);
- }
- static bool trans_rol(DisasContext *ctx, arg_rol *a)
- {
-     REQUIRE_ZBB(ctx);
--    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
-+    return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw);
- }
- static void gen_rev8_32(TCGv ret, TCGv src1)
-@@ -XXX,XX +XXX,XX @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
-     return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
- }
--static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
--{
--    TCGv_i32 t1 = tcg_temp_new_i32();
--    TCGv_i32 t2 = tcg_temp_new_i32();
--
--    /* truncate to 32-bits */
--    tcg_gen_trunc_tl_i32(t1, arg1);
--    tcg_gen_trunc_tl_i32(t2, arg2);
--
--    tcg_gen_rotr_i32(t1, t1, t2);
--
--    /* sign-extend 64-bits */
--    tcg_gen_ext_i32_tl(ret, t1);
--
--    tcg_temp_free_i32(t1);
--    tcg_temp_free_i32(t2);
--}
--
- static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
- {
-     REQUIRE_64BIT(ctx);
-@@ -XXX,XX +XXX,XX @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
-     REQUIRE_64BIT(ctx);
-     REQUIRE_ZBB(ctx);
-     ctx->ol = MXL_RV32;
--    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
--}
--
--static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
--{
--    TCGv_i32 t1 = tcg_temp_new_i32();
--    TCGv_i32 t2 = tcg_temp_new_i32();
--
--    /* truncate to 32-bits */
--    tcg_gen_trunc_tl_i32(t1, arg1);
--    tcg_gen_trunc_tl_i32(t2, arg2);
--
--    tcg_gen_rotl_i32(t1, t1, t2);
--
--    /* sign-extend 64-bits */
--    tcg_gen_ext_i32_tl(ret, t1);
--
--    tcg_temp_free_i32(t1);
--    tcg_temp_free_i32(t2);
-+    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw);
- }
- static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
-diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvi.c.inc
-+++ b/target/riscv/insn_trans/trans_rvi.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_slli(DisasContext *ctx, arg_slli *a)
-     return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
- }
-+static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
-+{
-+    tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
-+}
-+
- static bool trans_srli(DisasContext *ctx, arg_srli *a)
- {
--    return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl);
-+    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
-+                                   tcg_gen_shri_tl, gen_srliw);
-+}
-+
-+static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
-+{
-+    tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
- }
- static bool trans_srai(DisasContext *ctx, arg_srai *a)
- {
--    return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl);
-+    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
-+                                   tcg_gen_sari_tl, gen_sraiw);
- }
- static bool trans_add(DisasContext *ctx, arg_add *a)
-@@ -XXX,XX +XXX,XX @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
-     return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
- }
--static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
--{
--    tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
--}
--
- static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
- {
-     REQUIRE_64BIT(ctx);
-@@ -XXX,XX +XXX,XX @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
-     return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw);
- }
--static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
--{
--    tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
--}
--
- static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
- {
-     REQUIRE_64BIT(ctx);
 --
-.31.1
+.45.1

-[PULL 31/33] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
+[PULL 25/28] target/riscv/kvm.c: Fix the hart bit setting of AIA
-From: Bin Meng <bmeng.cn@gmail.com>
+From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
-Using memory_region_init_ram(), which can't possibly handle vhost-user,
+In AIA spec, each hart (or each hart within a group) has a unique hart
-and can't work as expected with '-numa node,memdev' options.
+number to locate the memory pages of interrupt files in the address
 space. The number of bits required to represent any hart number is equal
 to ceil(log2(hmax + 1)), where hmax is the largest hart number among
 groups.
-Use MachineState::ram instead of manually initializing RAM memory
+However, if the largest hart number among groups is a power of 2, QEMU
-region, as well as by providing MachineClass::default_ram_id to
+will pass an inaccurate hart-index-bit setting to Linux. For example, when
-opt in to memdev scheme.
+the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
 to represent 4 harts, but we passes 3 to Linux. The code needs to be
 updated to ensure accurate hart-index-bit settings.
-While at it add check for user supplied RAM size and error out if it
+Additionally, a Linux patch[1] is necessary to correctly recover the hart
-mismatches board expected value.
+index when the guest OS has only 1 hart, where the hart-index-bit is 0.
-Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
+[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
-Reviewed-by: Igor Mammedov <imammedo@redhat.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Message-id: 20211020014112.7336-5-bmeng.cn@gmail.com
+Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/sifive_e.c | 16 ++++++++++++----
+ target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
-file changed, 12 insertions(+), 4 deletions(-)
+file changed, 8 insertions(+), 1 deletion(-)
-diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
+diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_e.c
+--- a/target/riscv/kvm/kvm-cpu.c
-+++ b/hw/riscv/sifive_e.c
++++ b/target/riscv/kvm/kvm-cpu.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
-  */
+         }
+     }
- #include "qemu/osdep.h"
-+#include "qemu/cutils.h"
+-    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
- #include "qemu/error-report.h"
++
- #include "qapi/error.h"
++    if (max_hart_per_socket > 1) {
- #include "hw/boards.h"
++        max_hart_per_socket--;
-@@ -XXX,XX +XXX,XX @@ static const MemMapEntry sifive_e_memmap[] = {
++        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
++    } else {
- static void sifive_e_machine_init(MachineState *machine)
++        hart_bits = 0;
  {
 +    MachineClass *mc = MACHINE_GET_CLASS(machine);
      const MemMapEntry *memmap = sifive_e_memmap;
      SiFiveEState *s = RISCV_E_MACHINE(machine);
      MemoryRegion *sys_mem = get_system_memory();
 -    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
      int i;
 +    if (machine->ram_size != mc->default_ram_size) {
 +        char *sz = size_to_str(mc->default_ram_size);
 +        error_report("Invalid RAM size, should be %s", sz);
 +        g_free(sz);
 +        exit(EXIT_FAILURE);
 +    }
 +
-     /* Initialize SoC */
+     ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
-     object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC);
+                             KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
-     qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
+                             &hart_bits, true, NULL);
      /* Data Tightly Integrated Memory */
 -    memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
 -        memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal);
      memory_region_add_subregion(sys_mem,
 -        memmap[SIFIVE_E_DEV_DTIM].base, main_mem);
 +        memmap[SIFIVE_E_DEV_DTIM].base, machine->ram);
      /* Mask ROM reset vector */
      uint32_t reset_vec[4];
@@ -XXX,XX +XXX,XX @@ static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
      mc->init = sifive_e_machine_init;
      mc->max_cpus = 1;
      mc->default_cpu_type = SIFIVE_E_CPU;
 +    mc->default_ram_id = "riscv.sifive.e.ram";
 +    mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size;
      object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb,
                                     sifive_e_machine_set_revb);
 --
-.31.1
+.45.1

-[PULL 04/33] hw/riscv: virt: Use machine->ram as the system memory
+[PULL 26/28] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
-From: Mingwang Li <limingwang@huawei.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-If default main_mem is used to be registered as the system memory,
+Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
-other memory cannot be initialized. Therefore, the system memory
+in bytes, when in this context we want 'reg_width' as the length in
-should be initialized to the machine->ram, which consists of the
+bits.
 default main_mem and other possible memory required by applications,
 such as shared hugepage memory in DPDK.
-Also, the mc->defaul_ram_id should be set to the default main_mem,
+Fix 'reg_width' back to the value in bits like 7cb59921c05a
-such as "riscv_virt_board.ram" for the virt machine.
+("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
 beforehand.
-Signed-off-by: Mingwang Li <limingwang@huawei.com>
+While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
-Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
+clarity about what the variable represents. 'bitsize' is also used in
 riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
 gdb_feature_builder_append_reg().
 Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
 Cc: Alex Bennée <alex.bennee@linaro.org>
 Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
 Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Acked-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20211016030908.40480-1-limingwang@huawei.com
+Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/virt.c | 6 ++----
+ target/riscv/gdbstub.c | 6 +++---
-file changed, 2 insertions(+), 4 deletions(-)
+file changed, 3 insertions(+), 3 deletions(-)
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
+diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
+--- a/target/riscv/gdbstub.c
-+++ b/hw/riscv/virt.c
++++ b/target/riscv/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
-     const MemMapEntry *memmap = virt_memmap;
+ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
-     RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
+ {
-     MemoryRegion *system_memory = get_system_memory();
+     RISCVCPU *cpu = RISCV_CPU(cs);
--    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+-    int reg_width = cpu->cfg.vlenb;
-     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
++    int bitsize = cpu->cfg.vlenb << 3;
-     char *plic_hart_config, *soc_name;
+     GDBFeatureBuilder builder;
-     target_ulong start_addr = memmap[VIRT_DRAM].base;
+     int i;
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
      /* First define types and totals in a whole VL */
      for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
 -        int count = reg_width / vec_lanes[i].size;
 +        int count = bitsize / vec_lanes[i].size;
          gdb_feature_builder_append_tag(
              &builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
              vec_lanes[i].id, vec_lanes[i].gdb_type, count);
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
      /* Define vector registers */
      for (i = 0; i < 32; i++) {
          gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
 -                                       reg_width, i, "riscv_vector", "vector");
 +                                       bitsize, i, "riscv_vector", "vector");
      }
-     /* register system main memory (actual RAM) */
+     gdb_feature_builder_end(&builder);
 -    memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
 -                           machine->ram_size, &error_fatal);
      memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
 -        main_mem);
 +        machine->ram);
      /* create device tree */
      create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
      mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
      mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
      mc->numa_mem_supported = true;
 +    mc->default_ram_id = "riscv_virt_board.ram";
      machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
 --
-.31.1
+.45.1

-[PULL 03/33] target/riscv: Fix orc.b implementation
+[PULL 27/28] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: Alistair Francis <alistair23@gmail.com>
-The earlier implementation fell into a corner case for bytes that were
+Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
-x01, giving a wrong result (but not affecting our application test
+CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
-cases for strings, as an ASCII value 0x01 is rare in those...).
+CSRs are part of the disassembly.
-This changes the algorithm to:
+Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
-. Mask out the high-bit of each bytes (so that each byte is <= 127).
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-. Add 127 to each byte (i.e. if the low 7 bits are not 0, this will overflow
+Fixes: ea10325917 ("RISC-V Disassembler")
-    into the highest bit of each byte).
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-. Bitwise-or the original value back in (to cover those cases where the
+Cc: qemu-stable <qemu-stable@nongnu.org>
-    source byte was exactly 128) to saturate the high-bit.
+Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
 . Shift-and-mask (implemented as a mask-and-shift) to extract the MSB of
     each byte into its LSB.
 . Multiply with 0xff to fan out the LSB to all bits of each byte.
 Fixes: d7a4fcb034 ("target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci")
 Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
 Reported-by: Vincent Palatin <vpalatin@rivosinc.com>
 Tested-by: Vincent Palatin <vpalatin@rivosinc.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20211013184125.2010897-1-philipp.tomsich@vrull.eu
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvb.c.inc | 13 ++++++++-----
+ disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
-file changed, 8 insertions(+), 5 deletions(-)
+file changed, 64 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
+diff --git a/disas/riscv.c b/disas/riscv.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
+--- a/disas/riscv.c
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
++++ b/disas/riscv.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
+@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
- static void gen_orc_b(TCGv ret, TCGv source1)
+     case 0x0383: return "mibound";
- {
+     case 0x0384: return "mdbase";
-     TCGv  tmp = tcg_temp_new();
+     case 0x0385: return "mdbound";
--    TCGv  ones = tcg_constant_tl(dup_const_tl(MO_8, 0x01));
+-    case 0x03a0: return "pmpcfg3";
-+    TCGv  low7 = tcg_constant_tl(dup_const_tl(MO_8, 0x7f));
++    case 0x03a0: return "pmpcfg0";
++    case 0x03a1: return "pmpcfg1";
--    /* Set lsb in each byte if the byte was zero. */
++    case 0x03a2: return "pmpcfg2";
--    tcg_gen_sub_tl(tmp, source1, ones);
++    case 0x03a3: return "pmpcfg3";
--    tcg_gen_andc_tl(tmp, tmp, source1);
++    case 0x03a4: return "pmpcfg4";
-+    /* Set msb in each byte if the byte was non-zero. */
++    case 0x03a5: return "pmpcfg5";
-+    tcg_gen_and_tl(tmp, source1, low7);
++    case 0x03a6: return "pmpcfg6";
-+    tcg_gen_add_tl(tmp, tmp, low7);
++    case 0x03a7: return "pmpcfg7";
-+    tcg_gen_or_tl(tmp, tmp, source1);
++    case 0x03a8: return "pmpcfg8";
-+
++    case 0x03a9: return "pmpcfg9";
-+    /* Extract the msb to the lsb in each byte */
++    case 0x03aa: return "pmpcfg10";
-+    tcg_gen_andc_tl(tmp, tmp, low7);
++    case 0x03ab: return "pmpcfg11";
-     tcg_gen_shri_tl(tmp, tmp, 7);
++    case 0x03ac: return "pmpcfg12";
--    tcg_gen_andc_tl(tmp, ones, tmp);
++    case 0x03ad: return "pmpcfg13";
++    case 0x03ae: return "pmpcfg14";
-     /* Replicate the lsb of each byte across the byte. */
++    case 0x03af: return "pmpcfg15";
-     tcg_gen_muli_tl(ret, tmp, 0xff);
+     case 0x03b0: return "pmpaddr0";
      case 0x03b1: return "pmpaddr1";
      case 0x03b2: return "pmpaddr2";
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
      case 0x03bd: return "pmpaddr13";
      case 0x03be: return "pmpaddr14";
      case 0x03bf: return "pmpaddr15";
 +    case 0x03c0: return "pmpaddr16";
 +    case 0x03c1: return "pmpaddr17";
 +    case 0x03c2: return "pmpaddr18";
 +    case 0x03c3: return "pmpaddr19";
 +    case 0x03c4: return "pmpaddr20";
 +    case 0x03c5: return "pmpaddr21";
 +    case 0x03c6: return "pmpaddr22";
 +    case 0x03c7: return "pmpaddr23";
 +    case 0x03c8: return "pmpaddr24";
 +    case 0x03c9: return "pmpaddr25";
 +    case 0x03ca: return "pmpaddr26";
 +    case 0x03cb: return "pmpaddr27";
 +    case 0x03cc: return "pmpaddr28";
 +    case 0x03cd: return "pmpaddr29";
 +    case 0x03ce: return "pmpaddr30";
 +    case 0x03cf: return "pmpaddr31";
 +    case 0x03d0: return "pmpaddr32";
 +    case 0x03d1: return "pmpaddr33";
 +    case 0x03d2: return "pmpaddr34";
 +    case 0x03d3: return "pmpaddr35";
 +    case 0x03d4: return "pmpaddr36";
 +    case 0x03d5: return "pmpaddr37";
 +    case 0x03d6: return "pmpaddr38";
 +    case 0x03d7: return "pmpaddr39";
 +    case 0x03d8: return "pmpaddr40";
 +    case 0x03d9: return "pmpaddr41";
 +    case 0x03da: return "pmpaddr42";
 +    case 0x03db: return "pmpaddr43";
 +    case 0x03dc: return "pmpaddr44";
 +    case 0x03dd: return "pmpaddr45";
 +    case 0x03de: return "pmpaddr46";
 +    case 0x03df: return "pmpaddr47";
 +    case 0x03e0: return "pmpaddr48";
 +    case 0x03e1: return "pmpaddr49";
 +    case 0x03e2: return "pmpaddr50";
 +    case 0x03e3: return "pmpaddr51";
 +    case 0x03e4: return "pmpaddr52";
 +    case 0x03e5: return "pmpaddr53";
 +    case 0x03e6: return "pmpaddr54";
 +    case 0x03e7: return "pmpaddr55";
 +    case 0x03e8: return "pmpaddr56";
 +    case 0x03e9: return "pmpaddr57";
 +    case 0x03ea: return "pmpaddr58";
 +    case 0x03eb: return "pmpaddr59";
 +    case 0x03ec: return "pmpaddr60";
 +    case 0x03ed: return "pmpaddr61";
 +    case 0x03ee: return "pmpaddr62";
 +    case 0x03ef: return "pmpaddr63";
      case 0x0780: return "mtohost";
      case 0x0781: return "mfromhost";
      case 0x0782: return "mreset";
 --
-.31.1
+.45.1

-[PULL 06/33] target/riscv: Remove some unused macros
+Deleted patch
-From: Alistair Francis <alistair.francis@wdc.com>
-Since commit 1a9540d1f1a
-("target/riscv: Drop support for ISA spec version 1.09.1")
-these definitions are unused, remove them.
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Message-id: f4d8a7a035f39c0a35d44c1e371c5c99cc2fa15a.1634531504.git.alistair.francis@wdc.com
----
- target/riscv/cpu_bits.h | 8 --------
-file changed, 8 deletions(-)
-diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_bits.h
-+++ b/target/riscv/cpu_bits.h
-@@ -XXX,XX +XXX,XX @@
- #define SATP64_ASID         0x0FFFF00000000000ULL
- #define SATP64_PPN          0x00000FFFFFFFFFFFULL
--/* VM modes (mstatus.vm) privileged ISA 1.9.1 */
--#define VM_1_09_MBARE       0
--#define VM_1_09_MBB         1
--#define VM_1_09_MBBID       2
--#define VM_1_09_SV32        8
--#define VM_1_09_SV39        9
--#define VM_1_09_SV48        10
--
- /* VM modes (satp.mode) privileged ISA 1.10 */
- #define VM_1_10_MBARE       0
- #define VM_1_10_SV32        1
---
-.31.1

-[PULL 08/33] target/riscv: Move cpu_get_tb_cpu_state out of line
+[PULL 28/28] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Yu-Ming Chang <yumin686@andestech.com>
-Move the function to cpu_helper.c, as it is large and growing.
+Both CSRRS and CSRRC always read the addressed CSR and cause any read side
 effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
 holding a zero value other than x0, the instruction will still attempt to write
 the unmodified value back to the CSR and will cause any attendant side effects.
-Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
 a register holding a zero value, an illegal instruction exception should be
 raised.
 Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
 Message-id: 20211020031709.359469-2-richard.henderson@linaro.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h        | 47 ++-------------------------------------
+ target/riscv/cpu.h       |  4 ++++
- target/riscv/cpu_helper.c | 46 ++++++++++++++++++++++++++++++++++++++
+ target/riscv/csr.c       | 51 ++++++++++++++++++++++++++++++++++++----
-files changed, 48 insertions(+), 45 deletions(-)
+ target/riscv/op_helper.c |  6 ++---
 files changed, 53 insertions(+), 8 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
+@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
-     return cpu->cfg.vlen >> (sew + 3 - lmul);
+ void riscv_cpu_update_mask(CPURISCVState *env);
- }
+ bool riscv_cpu_is_32bit(RISCVCPU *cpu);
--static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
++RISCVException riscv_csrr(CPURISCVState *env, int csrno,
--                                        target_ulong *cs_base, uint32_t *pflags)
++                          target_ulong *ret_value);
 -{
 -    uint32_t flags = 0;
 -
 -    *pc = env->pc;
 -    *cs_base = 0;
 -
 -    if (riscv_has_ext(env, RVV)) {
 -        uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
 -        bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
 -        flags = FIELD_DP32(flags, TB_FLAGS, VILL,
 -                    FIELD_EX64(env->vtype, VTYPE, VILL));
 -        flags = FIELD_DP32(flags, TB_FLAGS, SEW,
 -                    FIELD_EX64(env->vtype, VTYPE, VSEW));
 -        flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
 -                    FIELD_EX64(env->vtype, VTYPE, VLMUL));
 -        flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
 -    } else {
 -        flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
 -    }
 -
 -#ifdef CONFIG_USER_ONLY
 -    flags |= TB_FLAGS_MSTATUS_FS;
 -#else
 -    flags |= cpu_mmu_index(env, 0);
 -    if (riscv_cpu_fp_enabled(env)) {
 -        flags |= env->mstatus & MSTATUS_FS;
 -    }
 -
 -    if (riscv_has_ext(env, RVH)) {
 -        if (env->priv == PRV_M ||
 -            (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
 -            (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
 -                get_field(env->hstatus, HSTATUS_HU))) {
 -            flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
 -        }
 -
 -        flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
 -                           get_field(env->mstatus_hs, MSTATUS_FS));
 -    }
 -#endif
 -
 -    *pflags = flags;
 -}
 +void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
 +                          target_ulong *cs_base, uint32_t *pflags);
  RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                             target_ulong *ret_value,
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+                            target_ulong new_value, target_ulong write_mask);
@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
                                            target_ulong new_value,
                                            target_ulong write_mask);
 +RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
 +                               Int128 *ret_value);
  RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                  Int128 *ret_value,
                                  Int128 new_value, Int128 write_mask);
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_helper.c
+--- a/target/riscv/csr.c
-+++ b/target/riscv/cpu_helper.c
++++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
+@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
- #endif
  static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
                                                 int csrno,
 -                                               bool write_mask)
 +                                               bool write)
  {
      /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
      bool read_only = get_field(csrno, 0xC00) == 3;
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
      }
      /* read / write check */
 -    if (write_mask && read_only) {
 +    if (write && read_only) {
          return RISCV_EXCP_ILLEGAL_INST;
      }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
      return RISCV_EXCP_NONE;
  }
-+void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
++RISCVException riscv_csrr(CPURISCVState *env, int csrno,
-+                          target_ulong *cs_base, uint32_t *pflags)
++                           target_ulong *ret_value)
 +{
-+    uint32_t flags = 0;
++    RISCVException ret = riscv_csrrw_check(env, csrno, false);
-+
++    if (ret != RISCV_EXCP_NONE) {
-+    *pc = env->pc;
++        return ret;
 +    *cs_base = 0;
 +
 +    if (riscv_has_ext(env, RVV)) {
 +        uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
 +        bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
 +        flags = FIELD_DP32(flags, TB_FLAGS, VILL,
 +                    FIELD_EX64(env->vtype, VTYPE, VILL));
 +        flags = FIELD_DP32(flags, TB_FLAGS, SEW,
 +                    FIELD_EX64(env->vtype, VTYPE, VSEW));
 +        flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
 +                    FIELD_EX64(env->vtype, VTYPE, VLMUL));
 +        flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
 +    } else {
 +        flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
 +    }
 +
-+#ifdef CONFIG_USER_ONLY
++    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
-+    flags |= TB_FLAGS_MSTATUS_FS;
++}
-+#else
++
-+    flags |= cpu_mmu_index(env, 0);
+ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
-+    if (riscv_cpu_fp_enabled(env)) {
+                            target_ulong *ret_value,
-+        flags |= env->mstatus & MSTATUS_FS;
+                            target_ulong new_value, target_ulong write_mask)
  {
 -    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
 +    RISCVException ret = riscv_csrrw_check(env, csrno, true);
      if (ret != RISCV_EXCP_NONE) {
          return ret;
      }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
      return RISCV_EXCP_NONE;
  }
 +RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
 +                               Int128 *ret_value)
 +{
 +    RISCVException ret;
 +
 +    ret = riscv_csrrw_check(env, csrno, false);
 +    if (ret != RISCV_EXCP_NONE) {
 +        return ret;
 +    }
 +
-+    if (riscv_has_ext(env, RVH)) {
++    if (csr_ops[csrno].read128) {
-+        if (env->priv == PRV_M ||
++        return riscv_csrrw_do128(env, csrno, ret_value,
-+            (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
++                                 int128_zero(), int128_zero());
-+            (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
++    }
 +                get_field(env->hstatus, HSTATUS_HU))) {
 +            flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
 +        }
 +
-+        flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
++    /*
-+                           get_field(env->mstatus_hs, MSTATUS_FS));
++     * Fall back to 64-bit version for now, if the 128-bit alternative isn't
 +     * at all defined.
 +     * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
 +     * significant), for those, this fallback is correctly handling the
 +     * accesses
 +     */
 +    target_ulong old_value;
 +    ret = riscv_csrrw_do64(env, csrno, &old_value,
 +                           (target_ulong)0,
 +                           (target_ulong)0);
 +    if (ret == RISCV_EXCP_NONE && ret_value) {
 +        *ret_value = int128_make64(old_value);
 +    }
-+#endif
++    return ret;
 +
 +    *pflags = flags;
 +}
 +
- #ifndef CONFIG_USER_ONLY
+ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
- static int riscv_cpu_local_irq_pending(CPURISCVState *env)
+                                 Int128 *ret_value,
                                  Int128 new_value, Int128 write_mask)
  {
+     RISCVException ret;
+-    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
++    ret = riscv_csrrw_check(env, csrno, true);
+     if (ret != RISCV_EXCP_NONE) {
+         return ret;
+     }
+diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/op_helper.c
++++ b/target/riscv/op_helper.c
+@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
+     }
+     target_ulong val = 0;
+-    RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
++    RISCVException ret = riscv_csrr(env, csr, &val);
+     if (ret != RISCV_EXCP_NONE) {
+         riscv_raise_exception(env, ret, GETPC());
+@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
+ target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
+ {
+     Int128 rv = int128_zero();
+-    RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
+-                                          int128_zero(),
+-                                          int128_zero());
++    RISCVException ret = riscv_csrr_i128(env, csr, &rv);
+     if (ret != RISCV_EXCP_NONE) {
+         riscv_raise_exception(env, ret, GETPC());
 --
-.31.1
+.45.1

-[PULL 23/33] hw/riscv: opentitan: Update to the latest build
+Deleted patch
-From: Alistair Francis <alistair.francis@wdc.com>
-Update the OpenTitan machine model to match the latest OpenTitan FPGA
-design.
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Message-id: 18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alistair.francis@wdc.com
----
- include/hw/riscv/opentitan.h |  6 +++---
- hw/riscv/opentitan.c         | 22 +++++++++++++++++-----
-files changed, 20 insertions(+), 8 deletions(-)
-diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/opentitan.h
-+++ b/include/hw/riscv/opentitan.h
-@@ -XXX,XX +XXX,XX @@
- #define HW_OPENTITAN_H
- #include "hw/riscv/riscv_hart.h"
--#include "hw/intc/ibex_plic.h"
-+#include "hw/intc/sifive_plic.h"
- #include "hw/char/ibex_uart.h"
- #include "hw/timer/ibex_timer.h"
- #include "qom/object.h"
-@@ -XXX,XX +XXX,XX @@ struct LowRISCIbexSoCState {
-     /*< public >*/
-     RISCVHartArrayState cpus;
--    IbexPlicState plic;
-+    SiFivePLICState plic;
-     IbexUartState uart;
-     IbexTimerState timer;
-@@ -XXX,XX +XXX,XX @@ enum {
- };
- enum {
--    IBEX_TIMER_TIMEREXPIRED0_0 = 125,
-+    IBEX_TIMER_TIMEREXPIRED0_0 = 126,
-     IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
-     IBEX_UART0_RX_TIMEOUT_IRQ = 7,
-     IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
-diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/opentitan.c
-+++ b/hw/riscv/opentitan.c
-@@ -XXX,XX +XXX,XX @@ static const MemMapEntry ibex_memmap[] = {
-     [IBEX_DEV_PINMUX] =         {  0x40460000,  0x1000  },
-     [IBEX_DEV_PADCTRL] =        {  0x40470000,  0x1000  },
-     [IBEX_DEV_FLASH_CTRL] =     {  0x41000000,  0x1000  },
--    [IBEX_DEV_PLIC] =           {  0x41010000,  0x1000  },
-     [IBEX_DEV_AES] =            {  0x41100000,  0x1000  },
-     [IBEX_DEV_HMAC] =           {  0x41110000,  0x1000  },
-     [IBEX_DEV_KMAC] =           {  0x41120000,  0x1000  },
--    [IBEX_DEV_KEYMGR] =         {  0x41130000,  0x1000  },
-+    [IBEX_DEV_OTBN] =           {  0x41130000,  0x10000 },
-+    [IBEX_DEV_KEYMGR] =         {  0x41140000,  0x1000  },
-     [IBEX_DEV_CSRNG] =          {  0x41150000,  0x1000  },
-     [IBEX_DEV_ENTROPY] =        {  0x41160000,  0x1000  },
-     [IBEX_DEV_EDNO] =           {  0x41170000,  0x1000  },
-     [IBEX_DEV_EDN1] =           {  0x41180000,  0x1000  },
-     [IBEX_DEV_ALERT_HANDLER] =  {  0x411b0000,  0x1000  },
-     [IBEX_DEV_NMI_GEN] =        {  0x411c0000,  0x1000  },
--    [IBEX_DEV_OTBN] =           {  0x411d0000,  0x10000 },
-     [IBEX_DEV_PERI] =           {  0x411f0000,  0x10000 },
-+    [IBEX_DEV_PLIC] =           {  0x48000000,  0x4005000  },
-     [IBEX_DEV_FLASH_VIRTUAL] =  {  0x80000000,  0x80000 },
- };
-@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_init(Object *obj)
-     object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
--    object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);
-+    object_initialize_child(obj, "plic", &s->plic, TYPE_SIFIVE_PLIC);
-     object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
-@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
-                                 &s->flash_alias);
-     /* PLIC */
-+    qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M");
-+    qdev_prop_set_uint32(DEVICE(&s->plic), "hartid-base", 0);
-+    qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180);
-+    qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3);
-+    qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00);
-+    qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
-+    qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
-+    qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 0x18);
-+    qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200004);
-+    qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 4);
-+    qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size);
-+
-     if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
-         return;
-     }
-@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
-     for (i = 0; i < ms->smp.cpus; i++) {
-         CPUState *cpu = qemu_get_cpu(i);
--        qdev_connect_gpio_out(DEVICE(&s->plic), i,
-+        qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i,
-                               qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
-     }
---
-.31.1

-[PULL 24/33] hw/intc: Remove the Ibex PLIC
+Deleted patch
-From: Alistair Francis <alistair.francis@wdc.com>
-The Ibex PLIC is now spec compliant. Let's remove the Ibex PLIC and
-instead use the SiFive PLIC.
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Message-id: 5557935c2660c5e6281b6d21e6514e019593662e.1634524691.git.alistair.francis@wdc.com
----
- hw/intc/ibex_plic.c | 307 --------------------------------------------
- hw/intc/meson.build |   1 -
-files changed, 308 deletions(-)
- delete mode 100644 hw/intc/ibex_plic.c
-diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
-deleted file mode 100644
-index XXXXXXX..XXXXXXX
---- a/hw/intc/ibex_plic.c
-+++ /dev/null
-@@ -XXX,XX +XXX,XX @@
--/*
-- * QEMU RISC-V lowRISC Ibex PLIC
-- *
-- * Copyright (c) 2020 Western Digital
-- *
-- * Documentation avaliable: https://docs.opentitan.org/hw/ip/rv_plic/doc/
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms and conditions of the GNU General Public License,
-- * version 2 or later, as published by the Free Software Foundation.
-- *
-- * This program is distributed in the hope it will be useful, but WITHOUT
-- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-- * more details.
-- *
-- * You should have received a copy of the GNU General Public License along with
-- * this program.  If not, see <http://www.gnu.org/licenses/>.
-- */
--
--#include "qemu/osdep.h"
--#include "qemu/log.h"
--#include "hw/qdev-properties.h"
--#include "hw/core/cpu.h"
--#include "hw/boards.h"
--#include "hw/pci/msi.h"
--#include "target/riscv/cpu_bits.h"
--#include "target/riscv/cpu.h"
--#include "hw/intc/ibex_plic.h"
--#include "hw/irq.h"
--
--static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
--{
--    uint32_t end = base + (num * 0x04);
--
--    if (addr >= base && addr < end) {
--        return true;
--    }
--
--    return false;
--}
--
--static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level)
--{
--    int pending_num = irq / 32;
--
--    if (!level) {
--        /*
--         * If the level is low make sure we clear the hidden_pending.
--         */
--        s->hidden_pending[pending_num] &= ~(1 << (irq % 32));
--    }
--
--    if (s->claimed[pending_num] & 1 << (irq % 32)) {
--        /*
--         * The interrupt has been claimed, but not completed.
--         * The pending bit can't be set.
--         * Save the pending level for after the interrupt is completed.
--         */
--        s->hidden_pending[pending_num] |= level << (irq % 32);
--    } else {
--        s->pending[pending_num] |= level << (irq % 32);
--    }
--}
--
--static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
--{
--    int i;
--    uint32_t max_irq = 0;
--    uint32_t max_prio = s->threshold;
--
--    for (i = 0; i < s->pending_num; i++) {
--        uint32_t irq_num = ctz64(s->pending[i]) + (i * 32);
--
--        if (!(s->pending[i] & s->enable[i])) {
--            /* No pending and enabled IRQ */
--            continue;
--        }
--
--        if (s->priority[irq_num] > max_prio) {
--            max_irq = irq_num;
--            max_prio = s->priority[irq_num];
--        }
--    }
--
--    if (max_irq) {
--        s->claim = max_irq;
--        return true;
--    }
--
--    return false;
--}
--
--static void ibex_plic_update(IbexPlicState *s)
--{
--    int i;
--
--    for (i = 0; i < s->num_cpus; i++) {
--        qemu_set_irq(s->external_irqs[i], ibex_plic_irqs_pending(s, 0));
--    }
--}
--
--static void ibex_plic_reset(DeviceState *dev)
--{
--    IbexPlicState *s = IBEX_PLIC(dev);
--
--    s->threshold = 0x00000000;
--    s->claim = 0x00000000;
--}
--
--static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
--                               unsigned int size)
--{
--    IbexPlicState *s = opaque;
--    int offset;
--    uint32_t ret = 0;
--
--    if (addr_between(addr, s->pending_base, s->pending_num)) {
--        offset = (addr - s->pending_base) / 4;
--        ret = s->pending[offset];
--    } else if (addr_between(addr, s->source_base, s->source_num)) {
--        qemu_log_mask(LOG_UNIMP,
--                      "%s: Interrupt source mode not supported\n", __func__);
--    } else if (addr_between(addr, s->priority_base, s->priority_num)) {
--        offset = (addr - s->priority_base) / 4;
--        ret = s->priority[offset];
--    } else if (addr_between(addr, s->enable_base, s->enable_num)) {
--        offset = (addr - s->enable_base) / 4;
--        ret = s->enable[offset];
--    } else if (addr_between(addr, s->threshold_base, 1)) {
--        ret = s->threshold;
--    } else if (addr_between(addr, s->claim_base, 1)) {
--        int pending_num = s->claim / 32;
--        s->pending[pending_num] &= ~(1 << (s->claim % 32));
--
--        /* Set the interrupt as claimed, but not completed */
--        s->claimed[pending_num] |= 1 << (s->claim % 32);
--
--        /* Return the current claimed interrupt */
--        ret = s->claim;
--
--        /* Clear the claimed interrupt */
--        s->claim = 0x00000000;
--
--        /* Update the interrupt status after the claim */
--        ibex_plic_update(s);
--    }
--
--    return ret;
--}
--
--static void ibex_plic_write(void *opaque, hwaddr addr,
--                            uint64_t value, unsigned int size)
--{
--    IbexPlicState *s = opaque;
--
--    if (addr_between(addr, s->pending_base, s->pending_num)) {
--        qemu_log_mask(LOG_GUEST_ERROR,
--                      "%s: Pending registers are read only\n", __func__);
--    } else if (addr_between(addr, s->source_base, s->source_num)) {
--        qemu_log_mask(LOG_UNIMP,
--                      "%s: Interrupt source mode not supported\n", __func__);
--    } else if (addr_between(addr, s->priority_base, s->priority_num)) {
--        uint32_t irq = ((addr - s->priority_base) >> 2) + 1;
--        s->priority[irq] = value & 7;
--        ibex_plic_update(s);
--    } else if (addr_between(addr, s->enable_base, s->enable_num)) {
--        uint32_t enable_reg = (addr - s->enable_base) / 4;
--
--        s->enable[enable_reg] = value;
--    } else if (addr_between(addr, s->threshold_base, 1)) {
--        s->threshold = value & 3;
--    } else if (addr_between(addr, s->claim_base, 1)) {
--        if (s->claim == value) {
--            /* Interrupt was completed */
--            s->claim = 0;
--        }
--        if (s->claimed[value / 32] & 1 << (value % 32)) {
--            int pending_num = value / 32;
--
--            /* This value was already claimed, clear it. */
--            s->claimed[pending_num] &= ~(1 << (value % 32));
--
--            if (s->hidden_pending[pending_num] & (1 << (value % 32))) {
--                /*
--                 * If the bit in hidden_pending is set then that means we
--                 * received an interrupt between claiming and completing
--                 * the interrupt that hasn't since been de-asserted.
--                 * On hardware this would trigger an interrupt, so let's
--                 * trigger one here as well.
--                 */
--                s->pending[pending_num] |= 1 << (value % 32);
--            }
--        }
--    }
--
--    ibex_plic_update(s);
--}
--
--static const MemoryRegionOps ibex_plic_ops = {
--    .read = ibex_plic_read,
--    .write = ibex_plic_write,
--    .endianness = DEVICE_NATIVE_ENDIAN,
--    .valid = {
--        .min_access_size = 4,
--        .max_access_size = 4
--    }
--};
--
--static void ibex_plic_irq_request(void *opaque, int irq, int level)
--{
--    IbexPlicState *s = opaque;
--
--    ibex_plic_irqs_set_pending(s, irq, level > 0);
--    ibex_plic_update(s);
--}
--
--static Property ibex_plic_properties[] = {
--    DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1),
--    DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 176),
--
--    DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0),
--    DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 6),
--
--    DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x18),
--    DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 6),
--
--    DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x30),
--    DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 177),
--
--    DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x300),
--    DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 6),
--
--    DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x318),
--
--    DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x31c),
--    DEFINE_PROP_END_OF_LIST(),
--};
--
--static void ibex_plic_init(Object *obj)
--{
--    IbexPlicState *s = IBEX_PLIC(obj);
--
--    memory_region_init_io(&s->mmio, obj, &ibex_plic_ops, s,
--                          TYPE_IBEX_PLIC, 0x400);
--    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
--}
--
--static void ibex_plic_realize(DeviceState *dev, Error **errp)
--{
--    IbexPlicState *s = IBEX_PLIC(dev);
--    int i;
--
--    s->pending = g_new0(uint32_t, s->pending_num);
--    s->hidden_pending = g_new0(uint32_t, s->pending_num);
--    s->claimed = g_new0(uint32_t, s->pending_num);
--    s->source = g_new0(uint32_t, s->source_num);
--    s->priority = g_new0(uint32_t, s->priority_num);
--    s->enable = g_new0(uint32_t, s->enable_num);
--
--    qdev_init_gpio_in(dev, ibex_plic_irq_request, s->num_sources);
--
--    s->external_irqs = g_malloc(sizeof(qemu_irq) * s->num_cpus);
--    qdev_init_gpio_out(dev, s->external_irqs, s->num_cpus);
--
--    /*
--     * We can't allow the supervisor to control SEIP as this would allow the
--     * supervisor to clear a pending external interrupt which will result in
--     * a lost interrupt in the case a PLIC is attached. The SEIP bit must be
--     * hardware controlled when a PLIC is attached.
--     */
--    MachineState *ms = MACHINE(qdev_get_machine());
--    unsigned int smp_cpus = ms->smp.cpus;
--    for (i = 0; i < smp_cpus; i++) {
--        RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i));
--        if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
--            error_report("SEIP already claimed");
--            exit(1);
--        }
--    }
--
--    msi_nonbroken = true;
--}
--
--static void ibex_plic_class_init(ObjectClass *klass, void *data)
--{
--    DeviceClass *dc = DEVICE_CLASS(klass);
--
--    dc->reset = ibex_plic_reset;
--    device_class_set_props(dc, ibex_plic_properties);
--    dc->realize = ibex_plic_realize;
--}
--
--static const TypeInfo ibex_plic_info = {
--    .name          = TYPE_IBEX_PLIC,
--    .parent        = TYPE_SYS_BUS_DEVICE,
--    .instance_size = sizeof(IbexPlicState),
--    .instance_init = ibex_plic_init,
--    .class_init    = ibex_plic_class_init,
--};
--
--static void ibex_plic_register_types(void)
--{
--    type_register_static(&ibex_plic_info);
--}
--
--type_init(ibex_plic_register_types)
-diff --git a/hw/intc/meson.build b/hw/intc/meson.build
-index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/meson.build
-+++ b/hw/intc/meson.build
-@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c'))
- specific_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_vic.c'))
- specific_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_gic.c', 'exynos4210_combiner.c'))
- specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c'))
--specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_plic.c'))
- specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c'))
- specific_ss.add(when: 'CONFIG_LOONGSON_LIOINTC', if_true: files('loongson_liointc.c'))
- specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_gic.c'))
---
-.31.1

-[PULL 25/33] hw/intc: sifive_plic: Move the properties
+Deleted patch
-From: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Message-id: 3c125e27c49a4969df82bf8b197535ccd1996939.1634524691.git.alistair.francis@wdc.com
----
- hw/intc/sifive_plic.c | 30 +++++++++++++++---------------
-file changed, 15 insertions(+), 15 deletions(-)
-diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/sifive_plic.c
-+++ b/hw/intc/sifive_plic.c
-@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps sifive_plic_ops = {
-     }
- };
--static Property sifive_plic_properties[] = {
--    DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
--    DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
--    DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
--    DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
--    DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
--    DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
--    DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
--    DEFINE_PROP_UINT32("enable-stride", SiFivePLICState, enable_stride, 0),
--    DEFINE_PROP_UINT32("context-base", SiFivePLICState, context_base, 0),
--    DEFINE_PROP_UINT32("context-stride", SiFivePLICState, context_stride, 0),
--    DEFINE_PROP_UINT32("aperture-size", SiFivePLICState, aperture_size, 0),
--    DEFINE_PROP_END_OF_LIST(),
--};
--
- /*
-  * parse PLIC hart/mode address offset config
-  *
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_sifive_plic = {
-         }
- };
-+static Property sifive_plic_properties[] = {
-+    DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
-+    DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
-+    DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
-+    DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
-+    DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
-+    DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
-+    DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
-+    DEFINE_PROP_UINT32("enable-stride", SiFivePLICState, enable_stride, 0),
-+    DEFINE_PROP_UINT32("context-base", SiFivePLICState, context_base, 0),
-+    DEFINE_PROP_UINT32("context-stride", SiFivePLICState, context_stride, 0),
-+    DEFINE_PROP_UINT32("aperture-size", SiFivePLICState, aperture_size, 0),
-+    DEFINE_PROP_END_OF_LIST(),
-+};
-+
- static void sifive_plic_class_init(ObjectClass *klass, void *data)
- {
-     DeviceClass *dc = DEVICE_CLASS(klass);
---
-.31.1

-[PULL 26/33] hw/intc: sifive_plic: Cleanup the realize function
+Deleted patch
-From: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Message-id: b94c098cb221e744683349b1ac794c23102ef471.1634524691.git.alistair.francis@wdc.com
----
- hw/intc/sifive_plic.c | 45 +++++++++++++++++++++++--------------------
-file changed, 24 insertions(+), 21 deletions(-)
-diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/sifive_plic.c
-+++ b/hw/intc/sifive_plic.c
-@@ -XXX,XX +XXX,XX @@ static void sifive_plic_irq_request(void *opaque, int irq, int level)
- static void sifive_plic_realize(DeviceState *dev, Error **errp)
- {
--    SiFivePLICState *plic = SIFIVE_PLIC(dev);
-+    SiFivePLICState *s = SIFIVE_PLIC(dev);
-     int i;
--    memory_region_init_io(&plic->mmio, OBJECT(dev), &sifive_plic_ops, plic,
--                          TYPE_SIFIVE_PLIC, plic->aperture_size);
--    parse_hart_config(plic);
--    plic->bitfield_words = (plic->num_sources + 31) >> 5;
--    plic->num_enables = plic->bitfield_words * plic->num_addrs;
--    plic->source_priority = g_new0(uint32_t, plic->num_sources);
--    plic->target_priority = g_new(uint32_t, plic->num_addrs);
--    plic->pending = g_new0(uint32_t, plic->bitfield_words);
--    plic->claimed = g_new0(uint32_t, plic->bitfield_words);
--    plic->enable = g_new0(uint32_t, plic->num_enables);
--    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
--    qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
--
--    plic->s_external_irqs = g_malloc(sizeof(qemu_irq) * plic->num_harts);
--    qdev_init_gpio_out(dev, plic->s_external_irqs, plic->num_harts);
--
--    plic->m_external_irqs = g_malloc(sizeof(qemu_irq) * plic->num_harts);
--    qdev_init_gpio_out(dev, plic->m_external_irqs, plic->num_harts);
-+    memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_plic_ops, s,
-+                          TYPE_SIFIVE_PLIC, s->aperture_size);
-+    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
-+
-+    parse_hart_config(s);
-+
-+    s->bitfield_words = (s->num_sources + 31) >> 5;
-+    s->num_enables = s->bitfield_words * s->num_addrs;
-+    s->source_priority = g_new0(uint32_t, s->num_sources);
-+    s->target_priority = g_new(uint32_t, s->num_addrs);
-+    s->pending = g_new0(uint32_t, s->bitfield_words);
-+    s->claimed = g_new0(uint32_t, s->bitfield_words);
-+    s->enable = g_new0(uint32_t, s->num_enables);
-+
-+    qdev_init_gpio_in(dev, sifive_plic_irq_request, s->num_sources);
-+
-+    s->s_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
-+    qdev_init_gpio_out(dev, s->s_external_irqs, s->num_harts);
-+
-+    s->m_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
-+    qdev_init_gpio_out(dev, s->m_external_irqs, s->num_harts);
-     /* We can't allow the supervisor to control SEIP as this would allow the
-      * supervisor to clear a pending external interrupt which will result in
-      * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
-      * hardware controlled when a PLIC is attached.
-      */
--    for (i = 0; i < plic->num_harts; i++) {
--        RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(plic->hartid_base + i));
-+    for (i = 0; i < s->num_harts; i++) {
-+        RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
-         if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
-             error_report("SEIP already claimed");
-             exit(1);
---
-.31.1

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 4c127fdbe81d66e7cafed90908d0fd1f6f2a6cd0:

Merge remote-tracking branch 'remotes/rth/tags/pull-arm-20211021' into staging (2021-10-21 09:53:27 -0700)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211022-2

for you to fetch changes up to 11ec06f9eaedc801ded34c79861367b76ab2b731:

hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id (2021-10-22 23:35:47 +1000)

----------------------------------------------------------------
Fourth RISC-V PR for QEMU 6.2

- Vector extension bug fixes
 - Bit manipulation extension bug fix
 - Support vhost-user and numa mem options on all boards
 - Rationalise XLEN and operand lengths
 - Bump the OpenTitan FPGA support
 - Remove the Ibex PLIC
 - General code cleanup

----------------------------------------------------------------
Alistair Francis (7):
      target/riscv: Remove some unused macros
      target/riscv: Organise the CPU properties
      hw/riscv: opentitan: Update to the latest build
      hw/intc: Remove the Ibex PLIC
      hw/intc: sifive_plic: Move the properties
      hw/intc: sifive_plic: Cleanup the realize function
      hw/intc: sifive_plic: Cleanup the irq_request function

Bin Meng (6):
      hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
      hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
      hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id
      hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
      hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id
      hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id

Frank Chang (2):
      target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v
      target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh

Mingwang Li (1):
      hw/riscv: virt: Use machine->ram as the system memory

Philipp Tomsich (1):
      target/riscv: Fix orc.b implementation

Richard Henderson (15):
      target/riscv: Move cpu_get_tb_cpu_state out of line
      target/riscv: Create RISCVMXL enumeration
      target/riscv: Split misa.mxl and misa.ext
      target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
      target/riscv: Add MXL/SXL/UXL to TB_FLAGS
      target/riscv: Use REQUIRE_64BIT in amo_check64
      target/riscv: Properly check SEW in amo_op
      target/riscv: Replace is_32bit with get_xl/get_xlen
      target/riscv: Replace DisasContext.w with DisasContext.ol
      target/riscv: Use gen_arith_per_ol for RVM
      target/riscv: Adjust trans_rev8_32 for riscv64
      target/riscv: Use gen_unary_per_ol for RVB
      target/riscv: Use gen_shift*_per_ol for RVB, RVI
      target/riscv: Use riscv_csrrw_debug for cpu_dump
      target/riscv: Compute mstatus.sd on demand

Travis Geiselbrecht (1):
      target/riscv: line up all of the registers in the info register dump

From: Frank Chang <frank.chang@sifive.com>

oprsz and maxsz are passed with the same value in commit: eee2d61e202.
However, vmv.v.v was missed in that commit and should pass the same
value as well in its tcg_gen_gvec_2_ptr() call.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211007081803.1705656-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

From: Travis Geiselbrecht <travisg@gmail.com>

Ensure the columns for all of the register names and values line up.
No functional change, just a minor tweak to the output.

Signed-off-by: Travis Geiselbrecht <travisg@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211009055019.545153-1-travisg@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The earlier implementation fell into a corner case for bytes that were
0x01, giving a wrong result (but not affecting our application test
cases for strings, as an ASCII value 0x01 is rare in those...).

This changes the algorithm to:
 1. Mask out the high-bit of each bytes (so that each byte is <= 127).
 2. Add 127 to each byte (i.e. if the low 7 bits are not 0, this will overflow
    into the highest bit of each byte).
 3. Bitwise-or the original value back in (to cover those cases where the
    source byte was exactly 128) to saturate the high-bit.
 4. Shift-and-mask (implemented as a mask-and-shift) to extract the MSB of
    each byte into its LSB.
 5. Multiply with 0xff to fan out the LSB to all bits of each byte.

Fixes: d7a4fcb034 ("target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci")

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reported-by: Vincent Palatin <vpalatin@rivosinc.com>
Tested-by: Vincent Palatin <vpalatin@rivosinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211013184125.2010897-1-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvb.c.inc | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
 static void gen_orc_b(TCGv ret, TCGv source1)
 {
     TCGv  tmp = tcg_temp_new();
-    TCGv  ones = tcg_constant_tl(dup_const_tl(MO_8, 0x01));
+    TCGv  low7 = tcg_constant_tl(dup_const_tl(MO_8, 0x7f));
 
-    /* Set lsb in each byte if the byte was zero. */
-    tcg_gen_sub_tl(tmp, source1, ones);
-    tcg_gen_andc_tl(tmp, tmp, source1);
+    /* Set msb in each byte if the byte was non-zero. */
+    tcg_gen_and_tl(tmp, source1, low7);
+    tcg_gen_add_tl(tmp, tmp, low7);
+    tcg_gen_or_tl(tmp, tmp, source1);
+
+    /* Extract the msb to the lsb in each byte */
+    tcg_gen_andc_tl(tmp, tmp, low7);
     tcg_gen_shri_tl(tmp, tmp, 7);
-    tcg_gen_andc_tl(tmp, ones, tmp);
 
     /* Replicate the lsb of each byte across the byte. */
     tcg_gen_muli_tl(ret, tmp, 0xff);
-- 
2.31.1

From: Mingwang Li <limingwang@huawei.com>

If default main_mem is used to be registered as the system memory,
other memory cannot be initialized. Therefore, the system memory
should be initialized to the machine->ram, which consists of the
default main_mem and other possible memory required by applications,
such as shared hugepage memory in DPDK.

Also, the mc->defaul_ram_id should be set to the default main_mem,
such as "riscv_virt_board.ram" for the virt machine.

Signed-off-by: Mingwang Li <limingwang@huawei.com>
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211016030908.40480-1-limingwang@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
     const MemMapEntry *memmap = virt_memmap;
     RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
     MemoryRegion *system_memory = get_system_memory();
-    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
     char *plic_hart_config, *soc_name;
     target_ulong start_addr = memmap[VIRT_DRAM].base;
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
     }
 
     /* register system main memory (actual RAM) */
-    memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
-                           machine->ram_size, &error_fatal);
     memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
-        main_mem);
+        machine->ram);
 
     /* create device tree */
     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
     mc->numa_mem_supported = true;
+    mc->default_ram_id = "riscv_virt_board.ram";
 
     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
 
-- 
2.31.1

From: Frank Chang <frank.chang@sifive.com>

TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
commit: c445593, but other TB_FLAGS bits for rvv and rvh were
not shift as well so these bits may overlap with each other when
rvv is enabled.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211015074627.3957162-2-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h       | 14 +++++++-------
 target/riscv/translate.c |  2 +-
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
 target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
 
-#define TB_FLAGS_MMU_MASK   7
 #define TB_FLAGS_PRIV_MMU_MASK                3
 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK   (1 << 2)
 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
@@ -XXX,XX +XXX,XX @@ typedef CPURISCVState CPUArchState;
 typedef RISCVCPU ArchCPU;
 #include "exec/cpu-all.h"
 
-FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1)
-FIELD(TB_FLAGS, LMUL, 3, 2)
-FIELD(TB_FLAGS, SEW, 5, 3)
-FIELD(TB_FLAGS, VILL, 8, 1)
+FIELD(TB_FLAGS, MEM_IDX, 0, 3)
+FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
+FIELD(TB_FLAGS, LMUL, 4, 2)
+FIELD(TB_FLAGS, SEW, 6, 3)
+FIELD(TB_FLAGS, VILL, 9, 1)
 /* Is a Hypervisor instruction load/store allowed? */
-FIELD(TB_FLAGS, HLSX, 9, 1)
-FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2)
+FIELD(TB_FLAGS, HLSX, 10, 1)
+FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2)
 
 bool riscv_cpu_is_32bit(CPURISCVState *env);
 
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     uint32_t tb_flags = ctx->base.tb->flags;
 
     ctx->pc_succ_insn = ctx->base.pc_first;
-    ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK;
+    ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
     ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
     ctx->priv_ver = env->priv_ver;
 #if !defined(CONFIG_USER_ONLY)
-- 
2.31.1

From: Alistair Francis <alistair.francis@wdc.com>

Since commit 1a9540d1f1a
("target/riscv: Drop support for ISA spec version 1.09.1")
these definitions are unused, remove them.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: f4d8a7a035f39c0a35d44c1e371c5c99cc2fa15a.1634531504.git.alistair.francis@wdc.com
---
 target/riscv/cpu_bits.h | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 #define SATP64_ASID         0x0FFFF00000000000ULL
 #define SATP64_PPN          0x00000FFFFFFFFFFFULL
 
-/* VM modes (mstatus.vm) privileged ISA 1.9.1 */
-#define VM_1_09_MBARE       0
-#define VM_1_09_MBB         1
-#define VM_1_09_MBBID       2
-#define VM_1_09_SV32        8
-#define VM_1_09_SV39        9
-#define VM_1_09_SV48        10
-
 /* VM modes (satp.mode) privileged ISA 1.10 */
 #define VM_1_10_MBARE       0
 #define VM_1_10_SV32        1
-- 
2.31.1

From: Alistair Francis <alistair.francis@wdc.com>

Organise the CPU properties so that standard extensions come first
then followed by experimental extensions.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: b6598570f60c5ee7f402be56d837bb44b289cc4d.1634531504.git.alistair.francis@wdc.com
---
 target/riscv/cpu.c | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
 }
 
 static Property riscv_cpu_properties[] = {
+    /* Defaults for standard extensions */
     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
     DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
-    /* This is experimental so mark with 'x-' */
+    DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
+    DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
+    DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
+    DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
+    DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+
+    DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
+
+    /* These are experimental so mark with 'x-' */
     DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
     DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
     DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
     DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
     DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
-    DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
-    DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
-    DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
-    DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
     DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
-    DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
-    DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
     /* ePMP 0.9.3 */
     DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
 
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Move the function to cpu_helper.c, as it is large and growing.

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
     return cpu->cfg.vlen >> (sew + 3 - lmul);
 }
 
-static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
-                                        target_ulong *cs_base, uint32_t *pflags)
-{
-    uint32_t flags = 0;
-
-    *pc = env->pc;
-    *cs_base = 0;
-
-    if (riscv_has_ext(env, RVV)) {
-        uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
-        bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
-        flags = FIELD_DP32(flags, TB_FLAGS, VILL,
-                    FIELD_EX64(env->vtype, VTYPE, VILL));
-        flags = FIELD_DP32(flags, TB_FLAGS, SEW,
-                    FIELD_EX64(env->vtype, VTYPE, VSEW));
-        flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
-                    FIELD_EX64(env->vtype, VTYPE, VLMUL));
-        flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
-    } else {
-        flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
-    }
-
-#ifdef CONFIG_USER_ONLY
-    flags |= TB_FLAGS_MSTATUS_FS;
-#else
-    flags |= cpu_mmu_index(env, 0);
-    if (riscv_cpu_fp_enabled(env)) {
-        flags |= env->mstatus & MSTATUS_FS;
-    }
-
-    if (riscv_has_ext(env, RVH)) {
-        if (env->priv == PRV_M ||
-            (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
-            (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
-                get_field(env->hstatus, HSTATUS_HU))) {
-            flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
-        }
-
-        flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
-                           get_field(env->mstatus_hs, MSTATUS_FS));
-    }
-#endif
-
-    *pflags = flags;
-}
+void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
+                          target_ulong *cs_base, uint32_t *pflags);
 
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
 #endif
 }
 
+void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
+                          target_ulong *cs_base, uint32_t *pflags)
+{
+    uint32_t flags = 0;
+
+    *pc = env->pc;
+    *cs_base = 0;
+
+    if (riscv_has_ext(env, RVV)) {
+        uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
+        bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
+        flags = FIELD_DP32(flags, TB_FLAGS, VILL,
+                    FIELD_EX64(env->vtype, VTYPE, VILL));
+        flags = FIELD_DP32(flags, TB_FLAGS, SEW,
+                    FIELD_EX64(env->vtype, VTYPE, VSEW));
+        flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
+                    FIELD_EX64(env->vtype, VTYPE, VLMUL));
+        flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
+    } else {
+        flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
+    }
+
+#ifdef CONFIG_USER_ONLY
+    flags |= TB_FLAGS_MSTATUS_FS;
+#else
+    flags |= cpu_mmu_index(env, 0);
+    if (riscv_cpu_fp_enabled(env)) {
+        flags |= env->mstatus & MSTATUS_FS;
+    }
+
+    if (riscv_has_ext(env, RVH)) {
+        if (env->priv == PRV_M ||
+            (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
+            (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
+                get_field(env->hstatus, HSTATUS_HU))) {
+            flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
+        }
+
+        flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
+                           get_field(env->mstatus_hs, MSTATUS_FS));
+    }
+#endif
+
+    *pflags = flags;
+}
+
 #ifndef CONFIG_USER_ONLY
 static int riscv_cpu_local_irq_pending(CPURISCVState *env)
 {
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Move the MXL_RV* defines to enumerators.

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 #define MISA32_MXL          0xC0000000
 #define MISA64_MXL          0xC000000000000000ULL
 
-#define MXL_RV32            1
-#define MXL_RV64            2
-#define MXL_RV128           3
+typedef enum {
+    MXL_RV32  = 1,
+    MXL_RV64  = 2,
+    MXL_RV128 = 3,
+} RISCVMXL;
 
 /* sstatus CSR bits */
 #define SSTATUS_UIE         0x00000001
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

The hw representation of misa.mxl is at the high bits of the
misa csr.  Representing this in the same way inside QEMU
results in overly complex code trying to check that field.

Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-4-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h          | 15 +++----
 linux-user/elfload.c        |  2 +-
 linux-user/riscv/cpu_loop.c |  2 +-
 target/riscv/cpu.c          | 78 +++++++++++++++++++++----------------
 target/riscv/csr.c          | 44 ++++++++++++++-------
 target/riscv/gdbstub.c      |  8 ++--
 target/riscv/machine.c      | 10 +++--
 target/riscv/translate.c    | 10 +++--
 8 files changed, 100 insertions(+), 69 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@
 #include "exec/cpu-defs.h"
 #include "fpu/softfloat-types.h"
 #include "qom/object.h"
+#include "cpu_bits.h"
 
 #define TCG_GUEST_DEFAULT_MO 0
 
@@ -XXX,XX +XXX,XX @@
 # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
 #endif
 
-#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
-#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
-
 #define RV(x) ((target_ulong)1 << (x - 'A'))
 
 #define RVI RV('I')
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     target_ulong priv_ver;
     target_ulong bext_ver;
     target_ulong vext_ver;
-    target_ulong misa;
-    target_ulong misa_mask;
+
+    /* RISCVMXL, but uint32_t for vmstate migration */
+    uint32_t misa_mxl;      /* current mxl */
+    uint32_t misa_mxl_max;  /* max mxl for this cpu */
+    uint32_t misa_ext;      /* current extensions */
+    uint32_t misa_ext_mask; /* max ext for this cpu */
 
     uint32_t features;
 
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
 
 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
 {
-    return (env->misa & ext) != 0;
+    return (env->misa_ext & ext) != 0;
 }
 
 static inline bool riscv_feature(CPURISCVState *env, int feature)
@@ -XXX,XX +XXX,XX @@ static inline bool riscv_feature(CPURISCVState *env, int feature)
 }
 
 #include "cpu_user.h"
-#include "cpu_bits.h"
 
 extern const char * const riscv_int_regnames[];
 extern const char * const riscv_fpr_regnames[];
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
     uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A')
                     | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C');
 
-    return cpu->env.misa & mask;
+    return cpu->env.misa_ext & mask;
 #undef MISA_BIT
 }
 
diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/riscv/cpu_loop.c
+++ b/linux-user/riscv/cpu_loop.c
@@ -XXX,XX +XXX,XX @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
     env->gpr[xSP] = regs->sp;
     env->elf_flags = info->elf_flags;
 
-    if ((env->misa & RVE) && !(env->elf_flags & EF_RISCV_RVE)) {
+    if ((env->misa_ext & RVE) && !(env->elf_flags & EF_RISCV_RVE)) {
         error_report("Incompatible ELF: RVE cpu requires RVE ABI binary");
         exit(EXIT_FAILURE);
     }
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
 
 bool riscv_cpu_is_32bit(CPURISCVState *env)
 {
-    if (env->misa & RV64) {
-        return false;
-    }
-
-    return true;
+    return env->misa_mxl == MXL_RV32;
 }
 
-static void set_misa(CPURISCVState *env, target_ulong misa)
+static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
 {
-    env->misa_mask = env->misa = misa;
+    env->misa_mxl_max = env->misa_mxl = mxl;
+    env->misa_ext_mask = env->misa_ext = ext;
 }
 
 static void set_priv_version(CPURISCVState *env, int priv_ver)
@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
 #if defined(TARGET_RISCV32)
-    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 #elif defined(TARGET_RISCV64)
-    set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 #endif
     set_priv_version(env, PRIV_VERSION_1_11_0);
 }
@@ -XXX,XX +XXX,XX @@ static void rv64_base_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     /* We set this in the realise function */
-    set_misa(env, RV64);
+    set_misa(env, MXL_RV64, 0);
 }
 
 static void rv64_sifive_u_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
-    set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
 }
 
 static void rv64_sifive_e_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
-    set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
+    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 }
@@ -XXX,XX +XXX,XX @@ static void rv32_base_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     /* We set this in the realise function */
-    set_misa(env, RV32);
+    set_misa(env, MXL_RV32, 0);
 }
 
 static void rv32_sifive_u_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
-    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
 }
 
 static void rv32_sifive_e_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
-    set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
+    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 }
@@ -XXX,XX +XXX,XX @@ static void rv32_sifive_e_cpu_init(Object *obj)
 static void rv32_ibex_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
-    set_misa(env, RV32 | RVI | RVM | RVC | RVU);
+    set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
     qdev_prop_set_bit(DEVICE(obj), "x-epmp", true);
@@ -XXX,XX +XXX,XX @@ static void rv32_ibex_cpu_init(Object *obj)
 static void rv32_imafcu_nommu_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
-    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
+    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
     set_resetvec(env, DEFAULT_RSTVEC);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
 
     mcc->parent_reset(dev);
 #ifndef CONFIG_USER_ONLY
+    env->misa_mxl = env->misa_mxl_max;
     env->priv = PRV_M;
     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
     env->mcause = 0;
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     CPURISCVState *env = &cpu->env;
     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
     int priv_version = 0;
-    target_ulong target_misa = env->misa;
     Error *local_err = NULL;
 
     cpu_exec_realizefn(cs, &local_err);
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 
     set_resetvec(env, cpu->cfg.resetvec);
 
-    /* If only XLEN is set for misa, then set misa from properties */
-    if (env->misa == RV32 || env->misa == RV64) {
+    /* Validate that MISA_MXL is set properly. */
+    switch (env->misa_mxl_max) {
+#ifdef TARGET_RISCV64
+    case MXL_RV64:
+        break;
+#endif
+    case MXL_RV32:
+        break;
+    default:
+        g_assert_not_reached();
+    }
+    assert(env->misa_mxl_max == env->misa_mxl);
+
+    /* If only MISA_EXT is unset for misa, then set it from properties */
+    if (env->misa_ext == 0) {
+        uint32_t ext = 0;
+
         /* Do some ISA extension error checking */
         if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
             error_setg(errp,
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 
         /* Set the ISA extensions, checks should have happened above */
         if (cpu->cfg.ext_i) {
-            target_misa |= RVI;
+            ext |= RVI;
         }
         if (cpu->cfg.ext_e) {
-            target_misa |= RVE;
+            ext |= RVE;
         }
         if (cpu->cfg.ext_m) {
-            target_misa |= RVM;
+            ext |= RVM;
         }
         if (cpu->cfg.ext_a) {
-            target_misa |= RVA;
+            ext |= RVA;
         }
         if (cpu->cfg.ext_f) {
-            target_misa |= RVF;
+            ext |= RVF;
         }
         if (cpu->cfg.ext_d) {
-            target_misa |= RVD;
+            ext |= RVD;
         }
         if (cpu->cfg.ext_c) {
-            target_misa |= RVC;
+            ext |= RVC;
         }
         if (cpu->cfg.ext_s) {
-            target_misa |= RVS;
+            ext |= RVS;
         }
         if (cpu->cfg.ext_u) {
-            target_misa |= RVU;
+            ext |= RVU;
         }
         if (cpu->cfg.ext_h) {
-            target_misa |= RVH;
+            ext |= RVH;
         }
         if (cpu->cfg.ext_v) {
             int vext_version = VEXT_VERSION_0_07_1;
-            target_misa |= RVV;
+            ext |= RVV;
             if (!is_power_of_2(cpu->cfg.vlen)) {
                 error_setg(errp,
                         "Vector extension VLEN must be power of 2");
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             set_vext_version(env, vext_version);
         }
 
-        set_misa(env, target_misa);
+        set_misa(env, env->misa_mxl, ext);
     }
 
     riscv_cpu_register_gdb_regs_for_features(cs);
@@ -XXX,XX +XXX,XX @@ char *riscv_isa_string(RISCVCPU *cpu)
     char *isa_str = g_new(char, maxlen);
     char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
     for (i = 0; i < sizeof(riscv_exts); i++) {
-        if (cpu->env.misa & RV(riscv_exts[i])) {
+        if (cpu->env.misa_ext & RV(riscv_exts[i])) {
             *p++ = qemu_tolower(riscv_exts[i]);
         }
     }
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
 {
 #if !defined(CONFIG_USER_ONLY)
     /* loose check condition for fcsr in vector extension */
-    if ((csrno == CSR_FCSR) && (env->misa & RVV)) {
+    if ((csrno == CSR_FCSR) && (env->misa_ext & RVV)) {
         return RISCV_EXCP_NONE;
     }
     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
 
 static RISCVException vs(CPURISCVState *env, int csrno)
 {
-    if (env->misa & RVV) {
+    if (env->misa_ext & RVV) {
         return RISCV_EXCP_NONE;
     }
     return RISCV_EXCP_ILLEGAL_INST;
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno,
 static RISCVException read_misa(CPURISCVState *env, int csrno,
                                 target_ulong *val)
 {
-    *val = env->misa;
+    target_ulong misa;
+
+    switch (env->misa_mxl) {
+    case MXL_RV32:
+        misa = (target_ulong)MXL_RV32 << 30;
+        break;
+#ifdef TARGET_RISCV64
+    case MXL_RV64:
+        misa = (target_ulong)MXL_RV64 << 62;
+        break;
+#endif
+    default:
+        g_assert_not_reached();
+    }
+
+    *val = misa | env->misa_ext;
     return RISCV_EXCP_NONE;
 }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
         return RISCV_EXCP_NONE;
     }
 
+    /*
+     * misa.MXL writes are not supported by QEMU.
+     * Drop writes to those bits.
+     */
+
     /* Mask extensions that are not supported by this hart */
-    val &= env->misa_mask;
+    val &= env->misa_ext_mask;
 
     /* Mask extensions that are not supported by QEMU */
     val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
@@ -XXX,XX +XXX,XX @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
         val &= ~RVC;
     }
 
-    /* misa.MXL writes are not supported by QEMU */
-    if (riscv_cpu_is_32bit(env)) {
-        val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL);
-    } else {
-        val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL);
+    /* If nothing changed, do nothing. */
+    if (val == env->misa_ext) {
+        return RISCV_EXCP_NONE;
     }
 
     /* flush translation cache */
-    if (val != env->misa) {
-        tb_flush(env_cpu(env));
-    }
-
-    env->misa = val;
-
+    tb_flush(env_cpu(env));
+    env->misa_ext = val;
     return RISCV_EXCP_NONE;
 }
 
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
 static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
 {
     if (n < 32) {
-        if (env->misa & RVD) {
+        if (env->misa_ext & RVD) {
             return gdb_get_reg64(buf, env->fpr[n]);
         }
-        if (env->misa & RVF) {
+        if (env->misa_ext & RVF) {
             return gdb_get_reg32(buf, env->fpr[n]);
         }
     /* there is hole between ft11 and fflags in fpu.xml */
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
-    if (env->misa & RVD) {
+    if (env->misa_ext & RVD) {
         gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
                                  36, "riscv-64bit-fpu.xml", 0);
-    } else if (env->misa & RVF) {
+    } else if (env->misa_ext & RVF) {
         gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
                                  36, "riscv-32bit-fpu.xml", 0);
     }
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_hyper = {
 
 const VMStateDescription vmstate_riscv_cpu = {
     .name = "cpu",
-    .version_id = 2,
-    .minimum_version_id = 2,
+    .version_id = 3,
+    .minimum_version_id = 3,
     .fields = (VMStateField[]) {
         VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
         VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
         VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
         VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
         VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
-        VMSTATE_UINTTL(env.misa, RISCVCPU),
-        VMSTATE_UINTTL(env.misa_mask, RISCVCPU),
+        VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
+        VMSTATE_UINT32(env.misa_ext, RISCVCPU),
+        VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
+        VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
         VMSTATE_UINT32(env.features, RISCVCPU),
         VMSTATE_UINTTL(env.priv, RISCVCPU),
         VMSTATE_UINTTL(env.virt, RISCVCPU),
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     /* pc_succ_insn points to the instruction following base.pc_next */
     target_ulong pc_succ_insn;
     target_ulong priv_ver;
-    target_ulong misa;
+    RISCVMXL xl;
+    uint32_t misa_ext;
     uint32_t opcode;
     uint32_t mstatus_fs;
     uint32_t mstatus_hs_fs;
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
 
 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
 {
-    return ctx->misa & ext;
+    return ctx->misa_ext & ext;
 }
 
 #ifdef TARGET_RISCV32
@@ -XXX,XX +XXX,XX @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
 #else
 static inline bool is_32bit(DisasContext *ctx)
 {
-    return (ctx->misa & RV32) == RV32;
+    return ctx->xl == MXL_RV32;
 }
 #endif
 
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
 #else
     ctx->virt_enabled = false;
 #endif
-    ctx->misa = env->misa;
+    ctx->xl = env->misa_mxl;
+    ctx->misa_ext = env->misa_ext;
     ctx->frm = -1;  /* unknown rounding mode */
     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
     ctx->vlen = cpu->cfg.vlen;
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Shortly, the set of supported XL will not be just 32 and 64,
and representing that properly using the enumeration will be
imperative.

Two places, booting and gdb, intentionally use misa_mxl_max
to emphasize the use of the reset value of misa.mxl, and not
the current cpu state.

Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-5-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h            |  9 ++++++++-
 hw/riscv/boot.c               |  2 +-
 semihosting/arm-compat-semi.c |  2 +-
 target/riscv/cpu.c            | 24 ++++++++++++++----------
 target/riscv/cpu_helper.c     | 12 ++++++------
 target/riscv/csr.c            | 24 ++++++++++++------------
 target/riscv/gdbstub.c        |  2 +-
 target/riscv/monitor.c        |  4 ++--
 8 files changed, 45 insertions(+), 34 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, VILL, 9, 1)
 FIELD(TB_FLAGS, HLSX, 10, 1)
 FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2)
 
-bool riscv_cpu_is_32bit(CPURISCVState *env);
+#ifdef TARGET_RISCV32
+#define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
+#else
+static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
+{
+    return env->misa_mxl;
+}
+#endif
 
 /*
  * A simplification for VLMAX
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@
 
 bool riscv_is_32bit(RISCVHartArrayState *harts)
 {
-    return riscv_cpu_is_32bit(&harts->harts[0].env);
+    return harts->harts[0].env.misa_mxl_max == MXL_RV32;
 }
 
 target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c
index XXXXXXX..XXXXXXX 100644
--- a/semihosting/arm-compat-semi.c
+++ b/semihosting/arm-compat-semi.c
@@ -XXX,XX +XXX,XX @@ static inline bool is_64bit_semihosting(CPUArchState *env)
 #if defined(TARGET_ARM)
     return is_a64(env);
 #elif defined(TARGET_RISCV)
-    return !riscv_cpu_is_32bit(env);
+    return riscv_cpu_mxl(env) != MXL_RV32;
 #else
 #error un-handled architecture
 #endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
     }
 }
 
-bool riscv_cpu_is_32bit(CPURISCVState *env)
-{
-    return env->misa_mxl == MXL_RV32;
-}
-
 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
 {
     env->misa_mxl_max = env->misa_mxl = mxl;
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 #ifndef CONFIG_USER_ONLY
     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
-    if (riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) == MXL_RV32) {
         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
                      (target_ulong)(env->mstatus >> 32));
     }
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 {
     RISCVCPU *cpu = RISCV_CPU(s);
-    if (riscv_cpu_is_32bit(&cpu->env)) {
+
+    switch (riscv_cpu_mxl(&cpu->env)) {
+    case MXL_RV32:
         info->print_insn = print_insn_riscv32;
-    } else {
+        break;
+    case MXL_RV64:
         info->print_insn = print_insn_riscv64;
+        break;
+    default:
+        g_assert_not_reached();
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static gchar *riscv_gdb_arch_name(CPUState *cs)
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
 
-    if (riscv_cpu_is_32bit(env)) {
+    switch (riscv_cpu_mxl(env)) {
+    case MXL_RV32:
         return g_strdup("riscv:rv32");
-    } else {
+    case MXL_RV64:
         return g_strdup("riscv:rv64");
+    default:
+        g_assert_not_reached();
     }
 }
 
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
 
 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
 {
-    uint64_t sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD;
+    uint64_t sd = riscv_cpu_mxl(env) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
     uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
                             MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
                             MSTATUS64_UXL | sd;
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
 
     if (first_stage == true) {
         if (use_background) {
-            if (riscv_cpu_is_32bit(env)) {
+            if (riscv_cpu_mxl(env) == MXL_RV32) {
                 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
                 vm = get_field(env->vsatp, SATP32_MODE);
             } else {
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
                 vm = get_field(env->vsatp, SATP64_MODE);
             }
         } else {
-            if (riscv_cpu_is_32bit(env)) {
+            if (riscv_cpu_mxl(env) == MXL_RV32) {
                 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
                 vm = get_field(env->satp, SATP32_MODE);
             } else {
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
         }
         widened = 0;
     } else {
-        if (riscv_cpu_is_32bit(env)) {
+        if (riscv_cpu_mxl(env) == MXL_RV32) {
             base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
             vm = get_field(env->hgatp, SATP32_MODE);
         } else {
@@ -XXX,XX +XXX,XX @@ restart:
         }
 
         target_ulong pte;
-        if (riscv_cpu_is_32bit(env)) {
+        if (riscv_cpu_mxl(env) == MXL_RV32) {
             pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
         } else {
             pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
     int page_fault_exceptions, vm;
     uint64_t stap_mode;
 
-    if (riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) == MXL_RV32) {
         stap_mode = SATP32_MODE;
     } else {
         stap_mode = SATP64_MODE;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
             }
             break;
         }
-        if (riscv_cpu_is_32bit(env)) {
+        if (riscv_cpu_mxl(env) == MXL_RV32) {
             switch (csrno) {
             case CSR_CYCLEH:
                 if (!get_field(env->hcounteren, COUNTEREN_CY) &&
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
 
 static RISCVException ctr32(CPURISCVState *env, int csrno)
 {
-    if (!riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) != MXL_RV32) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException any(CPURISCVState *env, int csrno)
 
 static RISCVException any32(CPURISCVState *env, int csrno)
 {
-    if (!riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) != MXL_RV32) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException hmode(CPURISCVState *env, int csrno)
 
 static RISCVException hmode32(CPURISCVState *env, int csrno)
 {
-    if (!riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) != MXL_RV32) {
         if (riscv_cpu_virt_enabled(env)) {
             return RISCV_EXCP_ILLEGAL_INST;
         } else {
@@ -XXX,XX +XXX,XX @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno,
 
 static int validate_vm(CPURISCVState *env, target_ulong vm)
 {
-    if (riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) == MXL_RV32) {
         return valid_vm_1_10_32[vm & 0xf];
     } else {
         return valid_vm_1_10_64[vm & 0xf];
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
         MSTATUS_TW;
 
-    if (!riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) != MXL_RV32) {
         /*
          * RV32: MPV and GVA are not in mstatus. The current plan is to
          * add them to mstatush. For now, we just don't support it.
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
 
     dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
             ((mstatus & MSTATUS_XS) == MSTATUS_XS);
-    if (riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) == MXL_RV32) {
         mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
     } else {
         mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
 {
     target_ulong mask = (sstatus_v1_10_mask);
 
-    if (riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) == MXL_RV32) {
         mask |= SSTATUS32_SD;
     } else {
         mask |= SSTATUS64_SD;
@@ -XXX,XX +XXX,XX @@ static RISCVException write_satp(CPURISCVState *env, int csrno,
         return RISCV_EXCP_NONE;
     }
 
-    if (riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) == MXL_RV32) {
         vm = validate_vm(env, get_field(val, SATP32_MODE));
         mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
         asid = (val ^ env->satp) & SATP32_ASID;
@@ -XXX,XX +XXX,XX @@ static RISCVException read_hstatus(CPURISCVState *env, int csrno,
                                    target_ulong *val)
 {
     *val = env->hstatus;
-    if (!riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) != MXL_RV32) {
         /* We only support 64-bit VSXL */
         *val = set_field(*val, HSTATUS_VSXL, 2);
     }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_hstatus(CPURISCVState *env, int csrno,
                                     target_ulong val)
 {
     env->hstatus = val;
-    if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) {
+    if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
         qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
     }
     if (get_field(val, HSTATUS_VSBE) != 0) {
@@ -XXX,XX +XXX,XX @@ static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
-    if (riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) == MXL_RV32) {
         env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
     } else {
         env->htimedelta = val;
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
     CPURISCVState *env = &cpu->env;
     GString *s = g_string_new(NULL);
     riscv_csr_predicate_fn predicate;
-    int bitsize = riscv_cpu_is_32bit(env) ? 32 : 64;
+    int bitsize = 16 << env->misa_mxl_max;
     int i;
 
     g_string_printf(s, "<?xml version=\"1.0\"?>");
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -XXX,XX +XXX,XX @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env)
     target_ulong last_size;
     int last_attr;
 
-    if (riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) == MXL_RV32) {
         base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
         vm = get_field(env->satp, SATP32_MODE);
     } else {
@@ -XXX,XX +XXX,XX @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
         return;
     }
 
-    if (riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) == MXL_RV32) {
         if (!(env->satp & SATP32_MODE)) {
             monitor_printf(mon, "No translation or protection\n");
             return;
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Begin adding support for switching XLEN at runtime.  Extract the
effective XLEN from MISA and MSTATUS and store for use during translation.

Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-6-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  2 ++
 target/riscv/cpu.c        |  8 ++++++++
 target/riscv/cpu_helper.c | 33 +++++++++++++++++++++++++++++++++
 target/riscv/csr.c        |  3 +++
 target/riscv/translate.c  |  2 +-
 5 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, VILL, 9, 1)
 /* Is a Hypervisor instruction load/store allowed? */
 FIELD(TB_FLAGS, HLSX, 10, 1)
 FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2)
+/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
+FIELD(TB_FLAGS, XL, 13, 2)
 
 #ifdef TARGET_RISCV32
 #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
     env->misa_mxl = env->misa_mxl_max;
     env->priv = PRV_M;
     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
+    if (env->misa_mxl > MXL_RV32) {
+        /*
+         * The reset status of SXL/UXL is undefined, but mstatus is WARL
+         * and we must ensure that the value after init is valid for read.
+         */
+        env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
+        env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
+    }
     env->mcause = 0;
     env->pc = env->resetvec;
     env->two_stage_lookup = false;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
 #endif
 }
 
+static RISCVMXL cpu_get_xl(CPURISCVState *env)
+{
+#if defined(TARGET_RISCV32)
+    return MXL_RV32;
+#elif defined(CONFIG_USER_ONLY)
+    return MXL_RV64;
+#else
+    RISCVMXL xl = riscv_cpu_mxl(env);
+
+    /*
+     * When emulating a 32-bit-only cpu, use RV32.
+     * When emulating a 64-bit cpu, and MXL has been reduced to RV32,
+     * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened
+     * back to RV64 for lower privs.
+     */
+    if (xl != MXL_RV32) {
+        switch (env->priv) {
+        case PRV_M:
+            break;
+        case PRV_U:
+            xl = get_field(env->mstatus, MSTATUS64_UXL);
+            break;
+        default: /* PRV_S | PRV_H */
+            xl = get_field(env->mstatus, MSTATUS64_SXL);
+            break;
+        }
+    }
+    return xl;
+#endif
+}
+
 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
                           target_ulong *cs_base, uint32_t *pflags)
 {
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
     }
 #endif
 
+    flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env));
+
     *pflags = flags;
 }
 
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
         mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
     } else {
         mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
+        /* SXL and UXL fields are for now read only */
+        mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
+        mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
     }
     env->mstatus = mstatus;
 
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
 #else
     ctx->virt_enabled = false;
 #endif
-    ctx->xl = env->misa_mxl;
     ctx->misa_ext = env->misa_ext;
     ctx->frm = -1;  /* unknown rounding mode */
     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
     ctx->mlen = 1 << (ctx->sew  + 3 - ctx->lmul);
     ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
+    ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
     ctx->cs = cs;
     ctx->w = false;
     ctx->ntemp = 0;
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Use the same REQUIRE_64BIT check that we use elsewhere,
rather than open-coding the use of is_32bit.

From: Richard Henderson <richard.henderson@linaro.org>

We're currently assuming SEW <= 3, and the "else" from
the SEW == 3 must be less.  Use a switch and explicitly
bound both SEW and SEQ for all cases.

From: Richard Henderson <richard.henderson@linaro.org>

In preparation for RV128, replace a simple predicate
with a more versatile test.

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
 }
 
 #ifdef TARGET_RISCV32
-# define is_32bit(ctx)  true
+#define get_xl(ctx)    MXL_RV32
 #elif defined(CONFIG_USER_ONLY)
-# define is_32bit(ctx)  false
+#define get_xl(ctx)    MXL_RV64
 #else
-static inline bool is_32bit(DisasContext *ctx)
+#define get_xl(ctx)    ((ctx)->xl)
+#endif
+
+/* The word size for this machine mode. */
+static inline int __attribute__((unused)) get_xlen(DisasContext *ctx)
 {
-    return ctx->xl == MXL_RV32;
+    return 16 << get_xl(ctx);
 }
-#endif
 
 /* The word size for this operation. */
 static inline int oper_len(DisasContext *ctx)
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
 static void mark_fs_dirty(DisasContext *ctx)
 {
     TCGv tmp;
-    target_ulong sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
+    target_ulong sd = get_xl(ctx) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
 
     if (ctx->mstatus_fs != MSTATUS_FS) {
         /* Remember the state change for the rest of the TB. */
@@ -XXX,XX +XXX,XX @@ EX_SH(12)
     }                              \
 } while (0)
 
-#define REQUIRE_32BIT(ctx) do { \
-    if (!is_32bit(ctx)) {       \
-        return false;           \
-    }                           \
+#define REQUIRE_32BIT(ctx) do {    \
+    if (get_xl(ctx) != MXL_RV32) { \
+        return false;              \
+    }                              \
 } while (0)
 
-#define REQUIRE_64BIT(ctx) do { \
-    if (is_32bit(ctx)) {        \
-        return false;           \
-    }                           \
+#define REQUIRE_64BIT(ctx) do {    \
+    if (get_xl(ctx) < MXL_RV64) {  \
+        return false;              \
+    }                              \
 } while (0)
 
 static int ex_rvc_register(DisasContext *ctx, int reg)
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

In preparation for RV128, consider more than just "w" for
operand size modification.  This will be used for the "d"
insns from RV128 as well.

Rename oper_len to get_olen to better match get_xlen.

Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-10-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                | 69 ++++++++++++++++---------
 target/riscv/insn_trans/trans_rvb.c.inc |  8 +--
 target/riscv/insn_trans/trans_rvi.c.inc | 18 +++----
 target/riscv/insn_trans/trans_rvm.c.inc | 10 ++--
 4 files changed, 62 insertions(+), 43 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
        to any system register, which includes CSR_FRM, so we do not have
        to reset this known value.  */
     int frm;
-    bool w;
+    RISCVMXL ol;
     bool virt_enabled;
     bool ext_ifencei;
     bool hlsx;
@@ -XXX,XX +XXX,XX @@ static inline int __attribute__((unused)) get_xlen(DisasContext *ctx)
     return 16 << get_xl(ctx);
 }
 
-/* The word size for this operation. */
-static inline int oper_len(DisasContext *ctx)
+/* The operation length, as opposed to the xlen. */
+#ifdef TARGET_RISCV32
+#define get_ol(ctx)    MXL_RV32
+#else
+#define get_ol(ctx)    ((ctx)->ol)
+#endif
+
+static inline int get_olen(DisasContext *ctx)
 {
-    return ctx->w ? 32 : TARGET_LONG_BITS;
+    return 16 << get_ol(ctx);
 }
 
-
 /*
  * RISC-V requires NaN-boxing of narrower width floating point values.
  * This applies when a 32-bit value is assigned to a 64-bit FP register.
@@ -XXX,XX +XXX,XX @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
         return ctx->zero;
     }
 
-    switch (ctx->w ? ext : EXT_NONE) {
-    case EXT_NONE:
-        return cpu_gpr[reg_num];
-    case EXT_SIGN:
-        t = temp_new(ctx);
-        tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
-        return t;
-    case EXT_ZERO:
-        t = temp_new(ctx);
-        tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
-        return t;
+    switch (get_ol(ctx)) {
+    case MXL_RV32:
+        switch (ext) {
+        case EXT_NONE:
+            break;
+        case EXT_SIGN:
+            t = temp_new(ctx);
+            tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
+            return t;
+        case EXT_ZERO:
+            t = temp_new(ctx);
+            tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
+            return t;
+        default:
+            g_assert_not_reached();
+        }
+        break;
+    case MXL_RV64:
+        break;
+    default:
+        g_assert_not_reached();
     }
-    g_assert_not_reached();
+    return cpu_gpr[reg_num];
 }
 
 static TCGv dest_gpr(DisasContext *ctx, int reg_num)
 {
-    if (reg_num == 0 || ctx->w) {
+    if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) {
         return temp_new(ctx);
     }
     return cpu_gpr[reg_num];
@@ -XXX,XX +XXX,XX @@ static TCGv dest_gpr(DisasContext *ctx, int reg_num)
 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
 {
     if (reg_num != 0) {
-        if (ctx->w) {
+        switch (get_ol(ctx)) {
+        case MXL_RV32:
             tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);
-        } else {
+            break;
+        case MXL_RV64:
             tcg_gen_mov_tl(cpu_gpr[reg_num], t);
+            break;
+        default:
+            g_assert_not_reached();
         }
     }
 }
@@ -XXX,XX +XXX,XX @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
                              void (*func)(TCGv, TCGv, target_long))
 {
     TCGv dest, src1;
-    int max_len = oper_len(ctx);
+    int max_len = get_olen(ctx);
 
     if (a->shamt >= max_len) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext,
                              void (*func)(TCGv, TCGv, TCGv))
 {
     TCGv dest, src1, src2;
-    int max_len = oper_len(ctx);
+    int max_len = get_olen(ctx);
 
     if (a->shamt >= max_len) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
     TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
     TCGv ext2 = tcg_temp_new();
 
-    tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1);
+    tcg_gen_andi_tl(ext2, src2, get_olen(ctx) - 1);
     func(dest, src1, ext2);
 
     gen_set_gpr(ctx, a->rd, dest);
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
     ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
     ctx->cs = cs;
-    ctx->w = false;
     ctx->ntemp = 0;
     memset(ctx->temp, 0, sizeof(ctx->temp));
 
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     CPURISCVState *env = cpu->env_ptr;
     uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
 
+    ctx->ol = ctx->xl;
     decode_opc(env, ctx, opcode16);
     ctx->base.pc_next = ctx->pc_succ_insn;
-    ctx->w = false;
 
     for (int i = ctx->ntemp - 1; i >= 0; --i) {
         tcg_temp_free(ctx->temp[i]);
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_ZBB(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_ZBB(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_shift(ctx, a, EXT_NONE, gen_rorw);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_ZBB(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_ZBB(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_shift(ctx, a, EXT_NONE, gen_rolw);
 }
 
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_and(DisasContext *ctx, arg_and *a)
 static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
 {
     REQUIRE_64BIT(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl);
 }
 
 static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
 {
     REQUIRE_64BIT(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
 }
 
@@ -XXX,XX +XXX,XX @@ static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
 static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
 {
     REQUIRE_64BIT(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw);
 }
 
@@ -XXX,XX +XXX,XX @@ static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
 static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
 {
     REQUIRE_64BIT(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw);
 }
 
 static bool trans_addw(DisasContext *ctx, arg_addw *a)
 {
     REQUIRE_64BIT(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl);
 }
 
 static bool trans_subw(DisasContext *ctx, arg_subw *a)
 {
     REQUIRE_64BIT(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
 }
 
 static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
 {
     REQUIRE_64BIT(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl);
 }
 
 static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
 {
     REQUIRE_64BIT(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
 }
 
 static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
 {
     REQUIRE_64BIT(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
 }
 
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_divw(DisasContext *ctx, arg_divw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_arith(ctx, a, EXT_SIGN, gen_div);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_arith(ctx, a, EXT_ZERO, gen_divu);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_remw(DisasContext *ctx, arg_remw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_arith(ctx, a, EXT_SIGN, gen_rem);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_arith(ctx, a, EXT_ZERO, gen_remu);
 }
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

The multiply high-part instructions require a separate
implementation for RV32 when TARGET_LONG_BITS == 64.

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
     return true;
 }
 
+static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext,
+                             void (*f_tl)(TCGv, TCGv, TCGv),
+                             void (*f_32)(TCGv, TCGv, TCGv))
+{
+    int olen = get_olen(ctx);
+
+    if (olen != TARGET_LONG_BITS) {
+        if (olen == 32) {
+            f_tl = f_32;
+        } else {
+            g_assert_not_reached();
+        }
+    }
+    return gen_arith(ctx, a, ext, f_tl);
+}
+
 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
                              void (*func)(TCGv, TCGv, target_long))
 {
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -XXX,XX +XXX,XX @@ static void gen_mulh(TCGv ret, TCGv s1, TCGv s2)
     tcg_temp_free(discard);
 }
 
+static void gen_mulh_w(TCGv ret, TCGv s1, TCGv s2)
+{
+    tcg_gen_mul_tl(ret, s1, s2);
+    tcg_gen_sari_tl(ret, ret, 32);
+}
+
 static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
 {
     REQUIRE_EXT(ctx, RVM);
-    return gen_arith(ctx, a, EXT_NONE, gen_mulh);
+    return gen_arith_per_ol(ctx, a, EXT_SIGN, gen_mulh, gen_mulh_w);
 }
 
 static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
@@ -XXX,XX +XXX,XX @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free(rh);
 }
 
+static void gen_mulhsu_w(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv t1 = tcg_temp_new();
+    TCGv t2 = tcg_temp_new();
+
+    tcg_gen_ext32s_tl(t1, arg1);
+    tcg_gen_ext32u_tl(t2, arg2);
+    tcg_gen_mul_tl(ret, t1, t2);
+    tcg_temp_free(t1);
+    tcg_temp_free(t2);
+    tcg_gen_sari_tl(ret, ret, 32);
+}
+
 static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
 {
     REQUIRE_EXT(ctx, RVM);
-    return gen_arith(ctx, a, EXT_NONE, gen_mulhsu);
+    return gen_arith_per_ol(ctx, a, EXT_NONE, gen_mulhsu, gen_mulhsu_w);
 }
 
 static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
@@ -XXX,XX +XXX,XX @@ static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
 static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
 {
     REQUIRE_EXT(ctx, RVM);
-    return gen_arith(ctx, a, EXT_NONE, gen_mulhu);
+    /* gen_mulh_w works for either sign as input. */
+    return gen_arith_per_ol(ctx, a, EXT_ZERO, gen_mulhu, gen_mulh_w);
 }
 
 static void gen_div(TCGv ret, TCGv source1, TCGv source2)
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

When target_long is 64-bit, we still want a 32-bit bswap for rev8.
Since this opcode is specific to RV32, we need not conditionalize.

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-12-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvb.c.inc | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

From: Richard Henderson <richard.henderson@linaro.org>

The count zeros instructions require a separate implementation
for RV32 when TARGET_LONG_BITS == 64.

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
     return true;
 }
 
+static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
+                             void (*f_tl)(TCGv, TCGv),
+                             void (*f_32)(TCGv, TCGv))
+{
+    int olen = get_olen(ctx);
+
+    if (olen != TARGET_LONG_BITS) {
+        if (olen == 32) {
+            f_tl = f_32;
+        } else {
+            g_assert_not_reached();
+        }
+    }
+    return gen_unary(ctx, a, ext, f_tl);
+}
+
 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
 {
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static void gen_clz(TCGv ret, TCGv arg1)
     tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
 }
 
+static void gen_clzw(TCGv ret, TCGv arg1)
+{
+    TCGv t = tcg_temp_new();
+    tcg_gen_shli_tl(t, arg1, 32);
+    tcg_gen_clzi_tl(ret, t, 32);
+    tcg_temp_free(t);
+}
+
 static bool trans_clz(DisasContext *ctx, arg_clz *a)
 {
     REQUIRE_ZBB(ctx);
-    return gen_unary(ctx, a, EXT_ZERO, gen_clz);
+    return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw);
 }
 
 static void gen_ctz(TCGv ret, TCGv arg1)
@@ -XXX,XX +XXX,XX @@ static void gen_ctz(TCGv ret, TCGv arg1)
     tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
 }
 
+static void gen_ctzw(TCGv ret, TCGv arg1)
+{
+    tcg_gen_ctzi_tl(ret, arg1, 32);
+}
+
 static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
 {
     REQUIRE_ZBB(ctx);
-    return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
+    return gen_unary_per_ol(ctx, a, EXT_ZERO, gen_ctz, gen_ctzw);
 }
 
 static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a)
     return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
 }
 
-static void gen_clzw(TCGv ret, TCGv arg1)
-{
-    TCGv t = tcg_temp_new();
-    tcg_gen_shli_tl(t, arg1, 32);
-    tcg_gen_clzi_tl(ret, t, 32);
-    tcg_temp_free(t);
-}
-
 static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
 {
     REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
     return gen_unary(ctx, a, EXT_NONE, gen_clzw);
 }
 
-static void gen_ctzw(TCGv ret, TCGv arg1)
-{
-    tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
-    tcg_gen_ctzi_tl(ret, ret, 64);
-}
-
 static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_ZBB(ctx);
-    return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
+    return gen_unary(ctx, a, EXT_ZERO, gen_ctzw);
 }
 
 static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Most shift instructions require a separate implementation
for RV32 when TARGET_LONG_BITS == 64.

Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-14-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                | 31 +++++++++
 target/riscv/insn_trans/trans_rvb.c.inc | 92 ++++++++++++++-----------
 target/riscv/insn_trans/trans_rvi.c.inc | 26 +++----
 3 files changed, 97 insertions(+), 52 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
     return true;
 }
 
+static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a,
+                                    DisasExtend ext,
+                                    void (*f_tl)(TCGv, TCGv, target_long),
+                                    void (*f_32)(TCGv, TCGv, target_long))
+{
+    int olen = get_olen(ctx);
+    if (olen != TARGET_LONG_BITS) {
+        if (olen == 32) {
+            f_tl = f_32;
+        } else {
+            g_assert_not_reached();
+        }
+    }
+    return gen_shift_imm_fn(ctx, a, ext, f_tl);
+}
+
 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext,
                              void (*func)(TCGv, TCGv, TCGv))
 {
@@ -XXX,XX +XXX,XX @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
     return true;
 }
 
+static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext,
+                             void (*f_tl)(TCGv, TCGv, TCGv),
+                             void (*f_32)(TCGv, TCGv, TCGv))
+{
+    int olen = get_olen(ctx);
+    if (olen != TARGET_LONG_BITS) {
+        if (olen == 32) {
+            f_tl = f_32;
+        } else {
+            g_assert_not_reached();
+        }
+    }
+    return gen_shift(ctx, a, ext, f_tl);
+}
+
 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
                       void (*func)(TCGv, TCGv))
 {
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
     return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
 }
 
+static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv_i32 t1 = tcg_temp_new_i32();
+    TCGv_i32 t2 = tcg_temp_new_i32();
+
+    /* truncate to 32-bits */
+    tcg_gen_trunc_tl_i32(t1, arg1);
+    tcg_gen_trunc_tl_i32(t2, arg2);
+
+    tcg_gen_rotr_i32(t1, t1, t2);
+
+    /* sign-extend 64-bits */
+    tcg_gen_ext_i32_tl(ret, t1);
+
+    tcg_temp_free_i32(t1);
+    tcg_temp_free_i32(t2);
+}
+
 static bool trans_ror(DisasContext *ctx, arg_ror *a)
 {
     REQUIRE_ZBB(ctx);
-    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
+    return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw);
+}
+
+static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt)
+{
+    TCGv_i32 t1 = tcg_temp_new_i32();
+
+    tcg_gen_trunc_tl_i32(t1, arg1);
+    tcg_gen_rotri_i32(t1, t1, shamt);
+    tcg_gen_ext_i32_tl(ret, t1);
+
+    tcg_temp_free_i32(t1);
 }
 
 static bool trans_rori(DisasContext *ctx, arg_rori *a)
 {
     REQUIRE_ZBB(ctx);
-    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
+    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
+                                   tcg_gen_rotri_tl, gen_roriw);
+}
+
+static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv_i32 t1 = tcg_temp_new_i32();
+    TCGv_i32 t2 = tcg_temp_new_i32();
+
+    /* truncate to 32-bits */
+    tcg_gen_trunc_tl_i32(t1, arg1);
+    tcg_gen_trunc_tl_i32(t2, arg2);
+
+    tcg_gen_rotl_i32(t1, t1, t2);
+
+    /* sign-extend 64-bits */
+    tcg_gen_ext_i32_tl(ret, t1);
+
+    tcg_temp_free_i32(t1);
+    tcg_temp_free_i32(t2);
 }
 
 static bool trans_rol(DisasContext *ctx, arg_rol *a)
 {
     REQUIRE_ZBB(ctx);
-    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
+    return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw);
 }
 
 static void gen_rev8_32(TCGv ret, TCGv src1)
@@ -XXX,XX +XXX,XX @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
     return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
 }
 
-static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
-{
-    TCGv_i32 t1 = tcg_temp_new_i32();
-    TCGv_i32 t2 = tcg_temp_new_i32();
-
-    /* truncate to 32-bits */
-    tcg_gen_trunc_tl_i32(t1, arg1);
-    tcg_gen_trunc_tl_i32(t2, arg2);
-
-    tcg_gen_rotr_i32(t1, t1, t2);
-
-    /* sign-extend 64-bits */
-    tcg_gen_ext_i32_tl(ret, t1);
-
-    tcg_temp_free_i32(t1);
-    tcg_temp_free_i32(t2);
-}
-
 static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
 {
     REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
     REQUIRE_64BIT(ctx);
     REQUIRE_ZBB(ctx);
     ctx->ol = MXL_RV32;
-    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
-}
-
-static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
-{
-    TCGv_i32 t1 = tcg_temp_new_i32();
-    TCGv_i32 t2 = tcg_temp_new_i32();
-
-    /* truncate to 32-bits */
-    tcg_gen_trunc_tl_i32(t1, arg1);
-    tcg_gen_trunc_tl_i32(t2, arg2);
-
-    tcg_gen_rotl_i32(t1, t1, t2);
-
-    /* sign-extend 64-bits */
-    tcg_gen_ext_i32_tl(ret, t1);
-
-    tcg_temp_free_i32(t1);
-    tcg_temp_free_i32(t2);
+    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw);
 }
 
 static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_slli(DisasContext *ctx, arg_slli *a)
     return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
 }
 
+static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
+{
+    tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
+}
+
 static bool trans_srli(DisasContext *ctx, arg_srli *a)
 {
-    return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl);
+    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
+                                   tcg_gen_shri_tl, gen_srliw);
+}
+
+static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
+{
+    tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
 }
 
 static bool trans_srai(DisasContext *ctx, arg_srai *a)
 {
-    return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl);
+    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
+                                   tcg_gen_sari_tl, gen_sraiw);
 }
 
 static bool trans_add(DisasContext *ctx, arg_add *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
     return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
 }
 
-static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
-{
-    tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
-}
-
 static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
 {
     REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
     return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw);
 }
 
-static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
-{
-    tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
-}
-
 static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
 {
     REQUIRE_64BIT(ctx);
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Use the official debug read interface to the csrs,
rather than referencing the env slots directly.
Put the list of csrs to dump into a table.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-15-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 89 +++++++++++++++++++++++-----------------------
 1 file changed, 45 insertions(+), 44 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 #endif
     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
 #ifndef CONFIG_USER_ONLY
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
-    if (riscv_cpu_mxl(env) == MXL_RV32) {
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
-                     (target_ulong)(env->mstatus >> 32));
-    }
-    if (riscv_has_ext(env, RVH)) {
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus",
-                     (target_ulong)env->vsstatus);
-    }
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
-    if (riscv_has_ext(env, RVH)) {
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
-    }
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
-    if (riscv_has_ext(env, RVH)) {
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);
-    }
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec   ", env->mtvec);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec   ", env->stvec);
-    if (riscv_has_ext(env, RVH)) {
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec  ", env->vstvec);
-    }
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc    ", env->mepc);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc    ", env->sepc);
-    if (riscv_has_ext(env, RVH)) {
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc   ", env->vsepc);
-    }
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause  ", env->mcause);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause  ", env->scause);
-    if (riscv_has_ext(env, RVH)) {
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
-    }
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval   ", env->mtval);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval   ", env->stval);
-    if (riscv_has_ext(env, RVH)) {
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval   ", env->htval);
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2  ", env->mtval2);
+    {
+        static const int dump_csrs[] = {
+            CSR_MHARTID,
+            CSR_MSTATUS,
+            CSR_MSTATUSH,
+            CSR_HSTATUS,
+            CSR_VSSTATUS,
+            CSR_MIP,
+            CSR_MIE,
+            CSR_MIDELEG,
+            CSR_HIDELEG,
+            CSR_MEDELEG,
+            CSR_HEDELEG,
+            CSR_MTVEC,
+            CSR_STVEC,
+            CSR_VSTVEC,
+            CSR_MEPC,
+            CSR_SEPC,
+            CSR_VSEPC,
+            CSR_MCAUSE,
+            CSR_SCAUSE,
+            CSR_VSCAUSE,
+            CSR_MTVAL,
+            CSR_STVAL,
+            CSR_HTVAL,
+            CSR_MTVAL2,
+            CSR_MSCRATCH,
+            CSR_SSCRATCH,
+            CSR_SATP,
+        };
+
+        for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
+            int csrno = dump_csrs[i];
+            target_ulong val = 0;
+            RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
+
+            /*
+             * Rely on the smode, hmode, etc, predicates within csr.c
+             * to do the filtering of the registers that are present.
+             */
+            if (res == RISCV_EXCP_NONE) {
+                qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
+                             csr_ops[csrno].name, val);
+            }
+        }
     }
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp    ", env->satp);
 #endif
 
     for (i = 0; i < 32; i++) {
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

The position of this read-only field is dependent on the current xlen.
Rather than having to compute that difference in many places, compute
it only on read.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-16-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c |  3 +--
 target/riscv/csr.c        | 37 ++++++++++++++++++++++---------------
 target/riscv/translate.c  |  5 ++---
 3 files changed, 25 insertions(+), 20 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
 
 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
 {
-    uint64_t sd = riscv_cpu_mxl(env) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
     uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
                             MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
-                            MSTATUS64_UXL | sd;
+                            MSTATUS64_UXL;
     bool current_virt = riscv_cpu_virt_enabled(env);
 
     g_assert(riscv_has_ext(env, RVH));
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException read_mhartid(CPURISCVState *env, int csrno,
 }
 
 /* Machine Trap Setup */
+
+/* We do not store SD explicitly, only compute it on demand. */
+static uint64_t add_status_sd(RISCVMXL xl, uint64_t status)
+{
+    if ((status & MSTATUS_FS) == MSTATUS_FS ||
+        (status & MSTATUS_XS) == MSTATUS_XS) {
+        switch (xl) {
+        case MXL_RV32:
+            return status | MSTATUS32_SD;
+        case MXL_RV64:
+            return status | MSTATUS64_SD;
+        default:
+            g_assert_not_reached();
+        }
+    }
+    return status;
+}
+
 static RISCVException read_mstatus(CPURISCVState *env, int csrno,
                                    target_ulong *val)
 {
-    *val = env->mstatus;
+    *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus);
     return RISCV_EXCP_NONE;
 }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
 {
     uint64_t mstatus = env->mstatus;
     uint64_t mask = 0;
-    int dirty;
 
     /* flush tlb on mstatus fields that affect VM */
     if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
 
     mstatus = (mstatus & ~mask) | (val & mask);
 
-    dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
-            ((mstatus & MSTATUS_XS) == MSTATUS_XS);
-    if (riscv_cpu_mxl(env) == MXL_RV32) {
-        mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
-    } else {
-        mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
+    if (riscv_cpu_mxl(env) == MXL_RV64) {
         /* SXL and UXL fields are for now read only */
         mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
         mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
 {
     target_ulong mask = (sstatus_v1_10_mask);
 
-    if (riscv_cpu_mxl(env) == MXL_RV32) {
-        mask |= SSTATUS32_SD;
-    } else {
-        mask |= SSTATUS64_SD;
-    }
-
-    *val = env->mstatus & mask;
+    /* TODO: Use SXL not MXL. */
+    *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
     return RISCV_EXCP_NONE;
 }
 
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
 static void mark_fs_dirty(DisasContext *ctx)
 {
     TCGv tmp;
-    target_ulong sd = get_xl(ctx) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
 
     if (ctx->mstatus_fs != MSTATUS_FS) {
         /* Remember the state change for the rest of the TB. */
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
 
         tmp = tcg_temp_new();
         tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
-        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
+        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
         tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
         tcg_temp_free(tmp);
     }
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
 
         tmp = tcg_temp_new();
         tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
-        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
+        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
         tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
         tcg_temp_free(tmp);
     }
-- 
2.31.1

From: Alistair Francis <alistair.francis@wdc.com>

Update the OpenTitan machine model to match the latest OpenTitan FPGA
design.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alistair.francis@wdc.com
---
 include/hw/riscv/opentitan.h |  6 +++---
 hw/riscv/opentitan.c         | 22 +++++++++++++++++-----
 2 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -XXX,XX +XXX,XX @@
 #define HW_OPENTITAN_H
 
 #include "hw/riscv/riscv_hart.h"
-#include "hw/intc/ibex_plic.h"
+#include "hw/intc/sifive_plic.h"
 #include "hw/char/ibex_uart.h"
 #include "hw/timer/ibex_timer.h"
 #include "qom/object.h"
@@ -XXX,XX +XXX,XX @@ struct LowRISCIbexSoCState {
 
     /*< public >*/
     RISCVHartArrayState cpus;
-    IbexPlicState plic;
+    SiFivePLICState plic;
     IbexUartState uart;
     IbexTimerState timer;
 
@@ -XXX,XX +XXX,XX @@ enum {
 };
 
 enum {
-    IBEX_TIMER_TIMEREXPIRED0_0 = 125,
+    IBEX_TIMER_TIMEREXPIRED0_0 = 126,
     IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
     IBEX_UART0_RX_TIMEOUT_IRQ = 7,
     IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry ibex_memmap[] = {
     [IBEX_DEV_PINMUX] =         {  0x40460000,  0x1000  },
     [IBEX_DEV_PADCTRL] =        {  0x40470000,  0x1000  },
     [IBEX_DEV_FLASH_CTRL] =     {  0x41000000,  0x1000  },
-    [IBEX_DEV_PLIC] =           {  0x41010000,  0x1000  },
     [IBEX_DEV_AES] =            {  0x41100000,  0x1000  },
     [IBEX_DEV_HMAC] =           {  0x41110000,  0x1000  },
     [IBEX_DEV_KMAC] =           {  0x41120000,  0x1000  },
-    [IBEX_DEV_KEYMGR] =         {  0x41130000,  0x1000  },
+    [IBEX_DEV_OTBN] =           {  0x41130000,  0x10000 },
+    [IBEX_DEV_KEYMGR] =         {  0x41140000,  0x1000  },
     [IBEX_DEV_CSRNG] =          {  0x41150000,  0x1000  },
     [IBEX_DEV_ENTROPY] =        {  0x41160000,  0x1000  },
     [IBEX_DEV_EDNO] =           {  0x41170000,  0x1000  },
     [IBEX_DEV_EDN1] =           {  0x41180000,  0x1000  },
     [IBEX_DEV_ALERT_HANDLER] =  {  0x411b0000,  0x1000  },
     [IBEX_DEV_NMI_GEN] =        {  0x411c0000,  0x1000  },
-    [IBEX_DEV_OTBN] =           {  0x411d0000,  0x10000 },
     [IBEX_DEV_PERI] =           {  0x411f0000,  0x10000 },
+    [IBEX_DEV_PLIC] =           {  0x48000000,  0x4005000  },
     [IBEX_DEV_FLASH_VIRTUAL] =  {  0x80000000,  0x80000 },
 };
 
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_init(Object *obj)
 
     object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
 
-    object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);
+    object_initialize_child(obj, "plic", &s->plic, TYPE_SIFIVE_PLIC);
 
     object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
 
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
                                 &s->flash_alias);
 
     /* PLIC */
+    qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M");
+    qdev_prop_set_uint32(DEVICE(&s->plic), "hartid-base", 0);
+    qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180);
+    qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3);
+    qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00);
+    qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
+    qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
+    qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 0x18);
+    qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200004);
+    qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 4);
+    qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size);
+
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
         return;
     }
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
     for (i = 0; i < ms->smp.cpus; i++) {
         CPUState *cpu = qemu_get_cpu(i);
 
-        qdev_connect_gpio_out(DEVICE(&s->plic), i,
+        qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i,
                               qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
     }
 
-- 
2.31.1

From: Alistair Francis <alistair.francis@wdc.com>

The Ibex PLIC is now spec compliant. Let's remove the Ibex PLIC and
instead use the SiFive PLIC.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 5557935c2660c5e6281b6d21e6514e019593662e.1634524691.git.alistair.francis@wdc.com
---
 hw/intc/ibex_plic.c | 307 --------------------------------------------
 hw/intc/meson.build |   1 -
 2 files changed, 308 deletions(-)
 delete mode 100644 hw/intc/ibex_plic.c

diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/hw/intc/ibex_plic.c
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-/*
- * QEMU RISC-V lowRISC Ibex PLIC
- *
- * Copyright (c) 2020 Western Digital
- *
- * Documentation avaliable: https://docs.opentitan.org/hw/ip/rv_plic/doc/
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "qemu/osdep.h"
-#include "qemu/log.h"
-#include "hw/qdev-properties.h"
-#include "hw/core/cpu.h"
-#include "hw/boards.h"
-#include "hw/pci/msi.h"
-#include "target/riscv/cpu_bits.h"
-#include "target/riscv/cpu.h"
-#include "hw/intc/ibex_plic.h"
-#include "hw/irq.h"
-
-static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
-{
-    uint32_t end = base + (num * 0x04);
-
-    if (addr >= base && addr < end) {
-        return true;
-    }
-
-    return false;
-}
-
-static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level)
-{
-    int pending_num = irq / 32;
-
-    if (!level) {
-        /*
-         * If the level is low make sure we clear the hidden_pending.
-         */
-        s->hidden_pending[pending_num] &= ~(1 << (irq % 32));
-    }
-
-    if (s->claimed[pending_num] & 1 << (irq % 32)) {
-        /*
-         * The interrupt has been claimed, but not completed.
-         * The pending bit can't be set.
-         * Save the pending level for after the interrupt is completed.
-         */
-        s->hidden_pending[pending_num] |= level << (irq % 32);
-    } else {
-        s->pending[pending_num] |= level << (irq % 32);
-    }
-}
-
-static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
-{
-    int i;
-    uint32_t max_irq = 0;
-    uint32_t max_prio = s->threshold;
-
-    for (i = 0; i < s->pending_num; i++) {
-        uint32_t irq_num = ctz64(s->pending[i]) + (i * 32);
-
-        if (!(s->pending[i] & s->enable[i])) {
-            /* No pending and enabled IRQ */
-            continue;
-        }
-
-        if (s->priority[irq_num] > max_prio) {
-            max_irq = irq_num;
-            max_prio = s->priority[irq_num];
-        }
-    }
-
-    if (max_irq) {
-        s->claim = max_irq;
-        return true;
-    }
-
-    return false;
-}
-
-static void ibex_plic_update(IbexPlicState *s)
-{
-    int i;
-
-    for (i = 0; i < s->num_cpus; i++) {
-        qemu_set_irq(s->external_irqs[i], ibex_plic_irqs_pending(s, 0));
-    }
-}
-
-static void ibex_plic_reset(DeviceState *dev)
-{
-    IbexPlicState *s = IBEX_PLIC(dev);
-
-    s->threshold = 0x00000000;
-    s->claim = 0x00000000;
-}
-
-static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
-                               unsigned int size)
-{
-    IbexPlicState *s = opaque;
-    int offset;
-    uint32_t ret = 0;
-
-    if (addr_between(addr, s->pending_base, s->pending_num)) {
-        offset = (addr - s->pending_base) / 4;
-        ret = s->pending[offset];
-    } else if (addr_between(addr, s->source_base, s->source_num)) {
-        qemu_log_mask(LOG_UNIMP,
-                      "%s: Interrupt source mode not supported\n", __func__);
-    } else if (addr_between(addr, s->priority_base, s->priority_num)) {
-        offset = (addr - s->priority_base) / 4;
-        ret = s->priority[offset];
-    } else if (addr_between(addr, s->enable_base, s->enable_num)) {
-        offset = (addr - s->enable_base) / 4;
-        ret = s->enable[offset];
-    } else if (addr_between(addr, s->threshold_base, 1)) {
-        ret = s->threshold;
-    } else if (addr_between(addr, s->claim_base, 1)) {
-        int pending_num = s->claim / 32;
-        s->pending[pending_num] &= ~(1 << (s->claim % 32));
-
-        /* Set the interrupt as claimed, but not completed */
-        s->claimed[pending_num] |= 1 << (s->claim % 32);
-
-        /* Return the current claimed interrupt */
-        ret = s->claim;
-
-        /* Clear the claimed interrupt */
-        s->claim = 0x00000000;
-
-        /* Update the interrupt status after the claim */
-        ibex_plic_update(s);
-    }
-
-    return ret;
-}
-
-static void ibex_plic_write(void *opaque, hwaddr addr,
-                            uint64_t value, unsigned int size)
-{
-    IbexPlicState *s = opaque;
-
-    if (addr_between(addr, s->pending_base, s->pending_num)) {
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: Pending registers are read only\n", __func__);
-    } else if (addr_between(addr, s->source_base, s->source_num)) {
-        qemu_log_mask(LOG_UNIMP,
-                      "%s: Interrupt source mode not supported\n", __func__);
-    } else if (addr_between(addr, s->priority_base, s->priority_num)) {
-        uint32_t irq = ((addr - s->priority_base) >> 2) + 1;
-        s->priority[irq] = value & 7;
-        ibex_plic_update(s);
-    } else if (addr_between(addr, s->enable_base, s->enable_num)) {
-        uint32_t enable_reg = (addr - s->enable_base) / 4;
-
-        s->enable[enable_reg] = value;
-    } else if (addr_between(addr, s->threshold_base, 1)) {
-        s->threshold = value & 3;
-    } else if (addr_between(addr, s->claim_base, 1)) {
-        if (s->claim == value) {
-            /* Interrupt was completed */
-            s->claim = 0;
-        }
-        if (s->claimed[value / 32] & 1 << (value % 32)) {
-            int pending_num = value / 32;
-
-            /* This value was already claimed, clear it. */
-            s->claimed[pending_num] &= ~(1 << (value % 32));
-
-            if (s->hidden_pending[pending_num] & (1 << (value % 32))) {
-                /*
-                 * If the bit in hidden_pending is set then that means we
-                 * received an interrupt between claiming and completing
-                 * the interrupt that hasn't since been de-asserted.
-                 * On hardware this would trigger an interrupt, so let's
-                 * trigger one here as well.
-                 */
-                s->pending[pending_num] |= 1 << (value % 32);
-            }
-        }
-    }
-
-    ibex_plic_update(s);
-}
-
-static const MemoryRegionOps ibex_plic_ops = {
-    .read = ibex_plic_read,
-    .write = ibex_plic_write,
-    .endianness = DEVICE_NATIVE_ENDIAN,
-    .valid = {
-        .min_access_size = 4,
-        .max_access_size = 4
-    }
-};
-
-static void ibex_plic_irq_request(void *opaque, int irq, int level)
-{
-    IbexPlicState *s = opaque;
-
-    ibex_plic_irqs_set_pending(s, irq, level > 0);
-    ibex_plic_update(s);
-}
-
-static Property ibex_plic_properties[] = {
-    DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1),
-    DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 176),
-
-    DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0),
-    DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 6),
-
-    DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x18),
-    DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 6),
-
-    DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x30),
-    DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 177),
-
-    DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x300),
-    DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 6),
-
-    DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x318),
-
-    DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x31c),
-    DEFINE_PROP_END_OF_LIST(),
-};
-
-static void ibex_plic_init(Object *obj)
-{
-    IbexPlicState *s = IBEX_PLIC(obj);
-
-    memory_region_init_io(&s->mmio, obj, &ibex_plic_ops, s,
-                          TYPE_IBEX_PLIC, 0x400);
-    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
-}
-
-static void ibex_plic_realize(DeviceState *dev, Error **errp)
-{
-    IbexPlicState *s = IBEX_PLIC(dev);
-    int i;
-
-    s->pending = g_new0(uint32_t, s->pending_num);
-    s->hidden_pending = g_new0(uint32_t, s->pending_num);
-    s->claimed = g_new0(uint32_t, s->pending_num);
-    s->source = g_new0(uint32_t, s->source_num);
-    s->priority = g_new0(uint32_t, s->priority_num);
-    s->enable = g_new0(uint32_t, s->enable_num);
-
-    qdev_init_gpio_in(dev, ibex_plic_irq_request, s->num_sources);
-
-    s->external_irqs = g_malloc(sizeof(qemu_irq) * s->num_cpus);
-    qdev_init_gpio_out(dev, s->external_irqs, s->num_cpus);
-
-    /*
-     * We can't allow the supervisor to control SEIP as this would allow the
-     * supervisor to clear a pending external interrupt which will result in
-     * a lost interrupt in the case a PLIC is attached. The SEIP bit must be
-     * hardware controlled when a PLIC is attached.
-     */
-    MachineState *ms = MACHINE(qdev_get_machine());
-    unsigned int smp_cpus = ms->smp.cpus;
-    for (i = 0; i < smp_cpus; i++) {
-        RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i));
-        if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
-            error_report("SEIP already claimed");
-            exit(1);
-        }
-    }
-
-    msi_nonbroken = true;
-}
-
-static void ibex_plic_class_init(ObjectClass *klass, void *data)
-{
-    DeviceClass *dc = DEVICE_CLASS(klass);
-
-    dc->reset = ibex_plic_reset;
-    device_class_set_props(dc, ibex_plic_properties);
-    dc->realize = ibex_plic_realize;
-}
-
-static const TypeInfo ibex_plic_info = {
-    .name          = TYPE_IBEX_PLIC,
-    .parent        = TYPE_SYS_BUS_DEVICE,
-    .instance_size = sizeof(IbexPlicState),
-    .instance_init = ibex_plic_init,
-    .class_init    = ibex_plic_class_init,
-};
-
-static void ibex_plic_register_types(void)
-{
-    type_register_static(&ibex_plic_info);
-}
-
-type_init(ibex_plic_register_types)
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c'))
 specific_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_vic.c'))
 specific_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_gic.c', 'exynos4210_combiner.c'))
 specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c'))
-specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_plic.c'))
 specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c'))
 specific_ss.add(when: 'CONFIG_LOONGSON_LIOINTC', if_true: files('loongson_liointc.c'))
 specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_gic.c'))
-- 
2.31.1

From: Alistair Francis <alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 3c125e27c49a4969df82bf8b197535ccd1996939.1634524691.git.alistair.francis@wdc.com
---
 hw/intc/sifive_plic.c | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps sifive_plic_ops = {
     }
 };
 
-static Property sifive_plic_properties[] = {
-    DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
-    DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
-    DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
-    DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
-    DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
-    DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
-    DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
-    DEFINE_PROP_UINT32("enable-stride", SiFivePLICState, enable_stride, 0),
-    DEFINE_PROP_UINT32("context-base", SiFivePLICState, context_base, 0),
-    DEFINE_PROP_UINT32("context-stride", SiFivePLICState, context_stride, 0),
-    DEFINE_PROP_UINT32("aperture-size", SiFivePLICState, aperture_size, 0),
-    DEFINE_PROP_END_OF_LIST(),
-};
-
 /*
  * parse PLIC hart/mode address offset config
  *
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_sifive_plic = {
         }
 };
 
+static Property sifive_plic_properties[] = {
+    DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
+    DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
+    DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
+    DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
+    DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
+    DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
+    DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
+    DEFINE_PROP_UINT32("enable-stride", SiFivePLICState, enable_stride, 0),
+    DEFINE_PROP_UINT32("context-base", SiFivePLICState, context_base, 0),
+    DEFINE_PROP_UINT32("context-stride", SiFivePLICState, context_stride, 0),
+    DEFINE_PROP_UINT32("aperture-size", SiFivePLICState, aperture_size, 0),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
 static void sifive_plic_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
-- 
2.31.1

From: Alistair Francis <alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: b94c098cb221e744683349b1ac794c23102ef471.1634524691.git.alistair.francis@wdc.com
---
 hw/intc/sifive_plic.c | 45 +++++++++++++++++++++++--------------------
 1 file changed, 24 insertions(+), 21 deletions(-)

diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -XXX,XX +XXX,XX @@ static void sifive_plic_irq_request(void *opaque, int irq, int level)
 
 static void sifive_plic_realize(DeviceState *dev, Error **errp)
 {
-    SiFivePLICState *plic = SIFIVE_PLIC(dev);
+    SiFivePLICState *s = SIFIVE_PLIC(dev);
     int i;
 
-    memory_region_init_io(&plic->mmio, OBJECT(dev), &sifive_plic_ops, plic,
-                          TYPE_SIFIVE_PLIC, plic->aperture_size);
-    parse_hart_config(plic);
-    plic->bitfield_words = (plic->num_sources + 31) >> 5;
-    plic->num_enables = plic->bitfield_words * plic->num_addrs;
-    plic->source_priority = g_new0(uint32_t, plic->num_sources);
-    plic->target_priority = g_new(uint32_t, plic->num_addrs);
-    plic->pending = g_new0(uint32_t, plic->bitfield_words);
-    plic->claimed = g_new0(uint32_t, plic->bitfield_words);
-    plic->enable = g_new0(uint32_t, plic->num_enables);
-    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
-    qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
-
-    plic->s_external_irqs = g_malloc(sizeof(qemu_irq) * plic->num_harts);
-    qdev_init_gpio_out(dev, plic->s_external_irqs, plic->num_harts);
-
-    plic->m_external_irqs = g_malloc(sizeof(qemu_irq) * plic->num_harts);
-    qdev_init_gpio_out(dev, plic->m_external_irqs, plic->num_harts);
+    memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_plic_ops, s,
+                          TYPE_SIFIVE_PLIC, s->aperture_size);
+    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
+
+    parse_hart_config(s);
+
+    s->bitfield_words = (s->num_sources + 31) >> 5;
+    s->num_enables = s->bitfield_words * s->num_addrs;
+    s->source_priority = g_new0(uint32_t, s->num_sources);
+    s->target_priority = g_new(uint32_t, s->num_addrs);
+    s->pending = g_new0(uint32_t, s->bitfield_words);
+    s->claimed = g_new0(uint32_t, s->bitfield_words);
+    s->enable = g_new0(uint32_t, s->num_enables);
+
+    qdev_init_gpio_in(dev, sifive_plic_irq_request, s->num_sources);
+
+    s->s_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
+    qdev_init_gpio_out(dev, s->s_external_irqs, s->num_harts);
+
+    s->m_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
+    qdev_init_gpio_out(dev, s->m_external_irqs, s->num_harts);
 
     /* We can't allow the supervisor to control SEIP as this would allow the
      * supervisor to clear a pending external interrupt which will result in
      * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
      * hardware controlled when a PLIC is attached.
      */
-    for (i = 0; i < plic->num_harts; i++) {
-        RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(plic->hartid_base + i));
+    for (i = 0; i < s->num_harts; i++) {
+        RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
         if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
             error_report("SEIP already claimed");
             exit(1);
-- 
2.31.1

From: Alistair Francis <alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 4200da222a65c89ed1ba35f754dcca7fdd9f08d6.1634524691.git.alistair.francis@wdc.com
---
 hw/intc/sifive_plic.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -XXX,XX +XXX,XX @@ static void parse_hart_config(SiFivePLICState *plic)
 
 static void sifive_plic_irq_request(void *opaque, int irq, int level)
 {
-    SiFivePLICState *plic = opaque;
-    if (RISCV_DEBUG_PLIC) {
-        qemu_log("sifive_plic_irq_request: irq=%d level=%d\n", irq, level);
-    }
-    sifive_plic_set_pending(plic, irq, level > 0);
-    sifive_plic_update(plic);
+    SiFivePLICState *s = opaque;
+
+    sifive_plic_set_pending(s, irq, level > 0);
+    sifive_plic_update(s);
 }
 
 static void sifive_plic_realize(DeviceState *dev, Error **errp)
-- 
2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.

Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20211020014112.7336-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/microchip_pfsoc.c | 36 ++++++++++++++++++++----------------
 1 file changed, 20 insertions(+), 16 deletions(-)

diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
     MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1);
     MemoryRegion *mem_high = g_new(MemoryRegion, 1);
     MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1);
-    uint64_t mem_high_size;
+    uint64_t mem_low_size, mem_high_size;
     hwaddr firmware_load_addr;
     const char *firmware_name;
     bool kernel_as_payload = false;
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
                             TYPE_MICROCHIP_PFSOC);
     qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
 
+    /* Split RAM into low and high regions using aliases to machine->ram */
+    mem_low_size = memmap[MICROCHIP_PFSOC_DRAM_LO].size;
+    mem_high_size = machine->ram_size - mem_low_size;
+    memory_region_init_alias(mem_low, NULL,
+                             "microchip.icicle.kit.ram_low", machine->ram,
+                             0, mem_low_size);
+    memory_region_init_alias(mem_high, NULL,
+                             "microchip.icicle.kit.ram_high", machine->ram,
+                             mem_low_size, mem_high_size);
+
     /* Register RAM */
-    memory_region_init_ram(mem_low, NULL, "microchip.icicle.kit.ram_low",
-                           memmap[MICROCHIP_PFSOC_DRAM_LO].size,
-                           &error_fatal);
-    memory_region_init_alias(mem_low_alias, NULL,
-                             "microchip.icicle.kit.ram_low.alias",
-                             mem_low, 0,
-                             memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].size);
     memory_region_add_subregion(system_memory,
                                 memmap[MICROCHIP_PFSOC_DRAM_LO].base,
                                 mem_low);
+    memory_region_add_subregion(system_memory,
+                                memmap[MICROCHIP_PFSOC_DRAM_HI].base,
+                                mem_high);
+
+    /* Create aliases for the low and high RAM regions */
+    memory_region_init_alias(mem_low_alias, NULL,
+                             "microchip.icicle.kit.ram_low.alias",
+                             mem_low, 0, mem_low_size);
     memory_region_add_subregion(system_memory,
                                 memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base,
                                 mem_low_alias);
-
-    mem_high_size = machine->ram_size - 1 * GiB;
-
-    memory_region_init_ram(mem_high, NULL, "microchip.icicle.kit.ram_high",
-                           mem_high_size, &error_fatal);
     memory_region_init_alias(mem_high_alias, NULL,
                              "microchip.icicle.kit.ram_high.alias",
                              mem_high, 0, mem_high_size);
-    memory_region_add_subregion(system_memory,
-                                memmap[MICROCHIP_PFSOC_DRAM_HI].base,
-                                mem_high);
     memory_region_add_subregion(system_memory,
                                 memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base,
                                 mem_high_alias);
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
                    MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
     mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
     mc->default_cpus = mc->min_cpus;
+    mc->default_ram_id = "microchip.icicle.kit.ram";
 
     /*
      * Map 513 MiB high memory, the mimimum required high memory size, because
-- 
2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.

Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.

While at it add check for user supplied RAM size and error out if it
mismatches board expected value.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20211020014112.7336-3-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/opentitan.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/cutils.h"
 #include "hw/riscv/opentitan.h"
 #include "qapi/error.h"
 #include "hw/boards.h"
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry ibex_memmap[] = {
 
 static void opentitan_board_init(MachineState *machine)
 {
+    MachineClass *mc = MACHINE_GET_CLASS(machine);
     const MemMapEntry *memmap = ibex_memmap;
     OpenTitanState *s = g_new0(OpenTitanState, 1);
     MemoryRegion *sys_mem = get_system_memory();
-    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+
+    if (machine->ram_size != mc->default_ram_size) {
+        char *sz = size_to_str(mc->default_ram_size);
+        error_report("Invalid RAM size, should be %s", sz);
+        g_free(sz);
+        exit(EXIT_FAILURE);
+    }
 
     /* Initialize SoC */
     object_initialize_child(OBJECT(machine), "soc", &s->soc,
                             TYPE_RISCV_IBEX_SOC);
     qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
 
-    memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
-        memmap[IBEX_DEV_RAM].size, &error_fatal);
     memory_region_add_subregion(sys_mem,
-        memmap[IBEX_DEV_RAM].base, main_mem);
+        memmap[IBEX_DEV_RAM].base, machine->ram);
 
     if (machine->firmware) {
         riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL);
@@ -XXX,XX +XXX,XX @@ static void opentitan_machine_init(MachineClass *mc)
     mc->init = opentitan_board_init;
     mc->max_cpus = 1;
     mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
+    mc->default_ram_id = "riscv.lowrisc.ibex.ram";
+    mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
 }
 
 DEFINE_MACHINE("opentitan", opentitan_machine_init)
-- 
2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.

Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211020014112.7336-4-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/shakti_c.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -XXX,XX +XXX,XX @@ static void shakti_c_machine_state_init(MachineState *mstate)
 {
     ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
     MemoryRegion *system_memory = get_system_memory();
-    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 
     /* Allow only Shakti C CPU for this platform */
     if (strcmp(mstate->cpu_type, TYPE_RISCV_CPU_SHAKTI_C) != 0) {
@@ -XXX,XX +XXX,XX @@ static void shakti_c_machine_state_init(MachineState *mstate)
     qdev_realize(DEVICE(&sms->soc), NULL, &error_abort);
 
     /* register RAM */
-    memory_region_init_ram(main_mem, NULL, "riscv.shakti.c.ram",
-                           mstate->ram_size, &error_fatal);
     memory_region_add_subregion(system_memory,
                                 shakti_c_memmap[SHAKTI_C_RAM].base,
-                                main_mem);
+                                mstate->ram);
 
     /* ROM reset vector */
     riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus,
@@ -XXX,XX +XXX,XX @@ static void shakti_c_machine_class_init(ObjectClass *klass, void *data)
     mc->desc = "RISC-V Board compatible with Shakti SDK";
     mc->init = shakti_c_machine_state_init;
     mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C;
+    mc->default_ram_id = "riscv.shakti.c.ram";
 }
 
 static const TypeInfo shakti_c_machine_type_info = {
-- 
2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.

Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.

While at it add check for user supplied RAM size and error out if it
mismatches board expected value.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20211020014112.7336-5-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_e.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/cutils.h"
 #include "qemu/error-report.h"
 #include "qapi/error.h"
 #include "hw/boards.h"
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry sifive_e_memmap[] = {
 
 static void sifive_e_machine_init(MachineState *machine)
 {
+    MachineClass *mc = MACHINE_GET_CLASS(machine);
     const MemMapEntry *memmap = sifive_e_memmap;
 
     SiFiveEState *s = RISCV_E_MACHINE(machine);
     MemoryRegion *sys_mem = get_system_memory();
-    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
     int i;
 
+    if (machine->ram_size != mc->default_ram_size) {
+        char *sz = size_to_str(mc->default_ram_size);
+        error_report("Invalid RAM size, should be %s", sz);
+        g_free(sz);
+        exit(EXIT_FAILURE);
+    }
+
     /* Initialize SoC */
     object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC);
     qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
 
     /* Data Tightly Integrated Memory */
-    memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
-        memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal);
     memory_region_add_subregion(sys_mem,
-        memmap[SIFIVE_E_DEV_DTIM].base, main_mem);
+        memmap[SIFIVE_E_DEV_DTIM].base, machine->ram);
 
     /* Mask ROM reset vector */
     uint32_t reset_vec[4];
@@ -XXX,XX +XXX,XX @@ static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
     mc->init = sifive_e_machine_init;
     mc->max_cpus = 1;
     mc->default_cpu_type = SIFIVE_E_CPU;
+    mc->default_ram_id = "riscv.sifive.e.ram";
+    mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size;
 
     object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb,
                                    sifive_e_machine_set_revb);
-- 
2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.

Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211020014112.7336-6-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_u.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
     const MemMapEntry *memmap = sifive_u_memmap;
     SiFiveUState *s = RISCV_U_MACHINE(machine);
     MemoryRegion *system_memory = get_system_memory();
-    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
     MemoryRegion *flash0 = g_new(MemoryRegion, 1);
     target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
     target_ulong firmware_end_addr, kernel_start_addr;
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
     qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
 
     /* register RAM */
-    memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
-                           machine->ram_size, &error_fatal);
     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
-                                main_mem);
+                                machine->ram);
 
     /* register QSPI0 Flash */
     memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
     mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
     mc->default_cpu_type = SIFIVE_U_CPU;
     mc->default_cpus = mc->min_cpus;
+    mc->default_ram_id = "riscv.sifive.u.ram";
 
     object_class_property_add_bool(oc, "start-in-flash",
                                    sifive_u_machine_get_start_in_flash,
-- 
2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.

Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211020014112.7336-7-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/spike.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
     const MemMapEntry *memmap = spike_memmap;
     SpikeState *s = SPIKE_MACHINE(machine);
     MemoryRegion *system_memory = get_system_memory();
-    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
     target_ulong firmware_end_addr, kernel_start_addr;
     uint32_t fdt_load_addr;
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
     }
 
     /* register system main memory (actual RAM) */
-    memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
-                           machine->ram_size, &error_fatal);
     memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
-        main_mem);
+        machine->ram);
 
     /* create device tree */
     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
@@ -XXX,XX +XXX,XX @@ static void spike_machine_class_init(ObjectClass *oc, void *data)
     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
     mc->numa_mem_supported = true;
+    mc->default_ram_id = "riscv.spike.ram";
 }
 
 static const TypeInfo spike_machine_typeinfo = {
-- 
2.31.1

The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:

Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)

are available in the Git repository at:

https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528

for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:

target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)

----------------------------------------------------------------
RISC-V PR for 9.1

* APLICs add child earlier than realize
* Fix exposure of Zkr
* Raise exceptions on wrs.nto
* Implement SBI debug console (DBCN) calls for KVM
* Support 64-bit addresses for initrd
* Change RISCV_EXCP_SEMIHOST exception number to 63
* Tolerate KVM disable ext errors
* Set tval in breakpoints
* Add support for Zve32x extension
* Add support for Zve64x extension
* Relax vector register check in RISCV gdbstub
* Fix the element agnostic Vector function problem
* Fix Zvkb extension config
* Implement dynamic establishment of custom decoder
* Add th.sxstatus CSR emulation
* Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
* Check single width operator for vector fp widen instructions
* Check single width operator for vfncvt.rod.f.f.w
* Remove redudant SEW checking for vector fp narrow/widen instructions
* Prioritize pmp errors in raise_mmu_exception()
* Do not set mtval2 for non guest-page faults
* Remove experimental prefix from "B" extension
* Fixup CBO extension register calculation
* Fix the hart bit setting of AIA
* Fix reg_width in ricsv_gen_dynamic_vector_feature()
* Decode all of the pmpcfg and pmpaddr CSRs
* Raise an exception when CSRRS/CSRRC writes a read-only CSR

----------------------------------------------------------------
Alexei Filippov (1):
      target/riscv: do not set mtval2 for non guest-page faults

Alistair Francis (2):
      target/riscv: rvzicbo: Fixup CBO extension register calculation
      disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs

Andrew Jones (2):
      target/riscv/kvm: Fix exposure of Zkr
      target/riscv: Raise exceptions on wrs.nto

Cheng Yang (1):
      hw/riscv/boot.c: Support 64-bit address for initrd

Christoph Müllner (1):
      riscv: thead: Add th.sxstatus CSR emulation

Clément Léger (1):
      target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

Daniel Henrique Barboza (6):
      target/riscv/kvm: implement SBI debug console (DBCN) calls
      target/riscv/kvm: tolerate KVM disable ext errors
      target/riscv/debug: set tval=pc in breakpoint exceptions
      trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
      target/riscv: prioritize pmp errors in raise_mmu_exception()
      riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()

Huang Tao (2):
      target/riscv: Fix the element agnostic function problem
      target/riscv: Implement dynamic establishment of custom decoder

Jason Chien (3):
      target/riscv: Add support for Zve32x extension
      target/riscv: Add support for Zve64x extension
      target/riscv: Relax vector register check in RISCV gdbstub

Max Chou (4):
      target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
      target/riscv: rvv: Check single width operator for vector fp widen instructions
      target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
      target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions

Rob Bradford (1):
      target/riscv: Remove experimental prefix from "B" extension

Yangyu Chen (1):
      target/riscv/cpu.c: fix Zvkb extension config

Yong-Xuan Wang (1):
      target/riscv/kvm.c: Fix the hart bit setting of AIA

Yu-Ming Chang (1):
      target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

yang.zhang (1):
      hw/intc/riscv_aplic: APLICs should add child earlier than realize

From: "yang.zhang" <yang.zhang@hexintek.com>

Since only root APLICs can have hw IRQ lines, aplic->parent should
be initialized first.

Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/riscv_aplic.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
     qdev_prop_set_bit(dev, "msimode", msimode);
     qdev_prop_set_bit(dev, "mmode", mmode);
 
+    if (parent) {
+        riscv_aplic_add_child(parent, dev);
+    }
+
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 
     if (!is_kvm_aia(msimode)) {
         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
     }
 
-    if (parent) {
-        riscv_aplic_add_child(parent, dev);
-    }
-
     if (!msimode) {
         for (i = 0; i < num_harts; i++) {
             CPUState *cpu = cpu_by_arch_id(hartid_base + i);
-- 
2.45.1

From: Andrew Jones <ajones@ventanamicro.com>

The Zkr extension may only be exposed to KVM guests if the VMM
implements the SEED CSR. Use the same implementation as TCG.

Without this patch, running with a KVM which does not forward the
SEED CSR access to QEMU will result in an ILL exception being
injected into the guest (this results in Linux guests crashing on
boot). And, when running with a KVM which does forward the access,
QEMU will crash, since QEMU doesn't know what to do with the exit.

Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  3 +++
 target/riscv/csr.c         | 18 ++++++++++++++----
 target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
 3 files changed, 42 insertions(+), 4 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 
 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
 
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+                                target_ulong write_mask);
+
 uint8_t satp_mode_max_from_map(uint32_t map);
 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
 #endif
 
 /* Crypto Extension */
-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
-                               target_ulong *ret_value,
-                               target_ulong new_value,
-                               target_ulong write_mask)
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+                                target_ulong write_mask)
 {
     uint16_t random_v;
     Error *random_e = NULL;
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
         rval = random_v | SEED_OPST_ES16;
     }
 
+    return rval;
+}
+
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+                               target_ulong *ret_value,
+                               target_ulong new_value,
+                               target_ulong write_mask)
+{
+    target_ulong rval;
+
+    rval = riscv_new_csr_seed(new_value, write_mask);
+
     if (ret_value) {
         *ret_value = rval;
     }
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
     return ret;
 }
 
+static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
+{
+    target_ulong csr_num = run->riscv_csr.csr_num;
+    target_ulong new_value = run->riscv_csr.new_value;
+    target_ulong write_mask = run->riscv_csr.write_mask;
+    int ret = 0;
+
+    switch (csr_num) {
+    case CSR_SEED:
+        run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: un-handled CSR EXIT for CSR %lx\n",
+                      __func__, csr_num);
+        ret = -1;
+        break;
+    }
+
+    return ret;
+}
+
 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
     case KVM_EXIT_RISCV_SBI:
         ret = kvm_riscv_handle_sbi(cs, run);
         break;
+    case KVM_EXIT_RISCV_CSR:
+        ret = kvm_riscv_handle_csr(cs, run);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
                       __func__, run->exit_reason);
-- 
2.45.1

From: Andrew Jones <ajones@ventanamicro.com>

Implementing wrs.nto to always just return is consistent with the
specification, as the instruction is permitted to terminate the
stall for any reason, but it's not useful for virtualization, where
we'd like the guest to trap to the hypervisor in order to allow
scheduling of the lock holding VCPU. Change to always immediately
raise exceptions when the appropriate conditions are present,
otherwise continue to just return. Note, immediately raising
exceptions is also consistent with the specification since the
time limit that should expire prior to the exception is
implementation-specific.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                       |  1 +
 target/riscv/op_helper.c                    | 11 ++++++++
 target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
 3 files changed, 32 insertions(+), 9 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
 DEF_HELPER_1(sret, tl, env)
 DEF_HELPER_1(mret, tl, env)
 DEF_HELPER_1(wfi, void, env)
+DEF_HELPER_1(wrs_nto, void, env)
 DEF_HELPER_1(tlb_flush, void, env)
 DEF_HELPER_1(tlb_flush_all, void, env)
 /* Native Debug */
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
     }
 }
 
+void helper_wrs_nto(CPURISCVState *env)
+{
+    if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
+        get_field(env->hstatus, HSTATUS_VTW) &&
+        !get_field(env->mstatus, MSTATUS_TW)) {
+        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+    } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    }
+}
+
 void helper_tlb_flush(CPURISCVState *env)
 {
     CPUState *cs = env_cpu(env);
diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
+++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
@@ -XXX,XX +XXX,XX @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-static bool trans_wrs(DisasContext *ctx)
+static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
 {
     if (!ctx->cfg_ptr->ext_zawrs) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
     return true;
 }
 
-#define GEN_TRANS_WRS(insn)                                     \
-static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
-{                                                               \
-    (void)a;                                                    \
-    return trans_wrs(ctx);                                      \
-}
+static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
+{
+    if (!ctx->cfg_ptr->ext_zawrs) {
+        return false;
+    }
 
-GEN_TRANS_WRS(wrs_nto)
-GEN_TRANS_WRS(wrs_sto)
+    /*
+     * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
+     * should raise an exception when the implementation-specific bounded time
+     * limit has expired. Our time limit is zero, so we either return
+     * immediately, as does our implementation of wrs.sto, or raise an
+     * exception, as handled by the wrs.nto helper.
+     */
+#ifndef CONFIG_USER_ONLY
+    gen_helper_wrs_nto(tcg_env);
+#endif
+
+    /* We only get here when helper_wrs_nto() doesn't raise an exception. */
+    return trans_wrs_sto(ctx, NULL);
+}
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

SBI defines a Debug Console extension "DBCN" that will, in time, replace
the legacy console putchar and getchar SBI extensions.

The appeal of the DBCN extension is that it allows multiple bytes to be
read/written in the SBI console in a single SBI call.

As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
module to userspace. But this will only happens if the KVM module
actually supports this SBI extension and we activate it.

We'll check for DBCN support during init time, checking if get-reg-list
is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
kvm_set_one_reg() during kvm_arch_init_vcpu().

Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
SBI_EXT_DBCN, reading and writing as required.

A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
host, takes around 20 seconds to boot without using DBCN. With this
patch we're taking around 14 seconds to boot due to the speed-up in the
terminal output.  There's no change in boot time if the guest isn't
using earlycon.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/sbi_ecall_interface.h |  17 +++++
 target/riscv/kvm/kvm-cpu.c         | 111 +++++++++++++++++++++++++++++
 2 files changed, 128 insertions(+)

diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/sbi_ecall_interface.h
+++ b/target/riscv/sbi_ecall_interface.h
@@ -XXX,XX +XXX,XX @@
 
 /* clang-format off */
 
+#define SBI_SUCCESS                      0
+#define SBI_ERR_FAILED                  -1
+#define SBI_ERR_NOT_SUPPORTED           -2
+#define SBI_ERR_INVALID_PARAM           -3
+#define SBI_ERR_DENIED                  -4
+#define SBI_ERR_INVALID_ADDRESS         -5
+#define SBI_ERR_ALREADY_AVAILABLE       -6
+#define SBI_ERR_ALREADY_STARTED         -7
+#define SBI_ERR_ALREADY_STOPPED         -8
+#define SBI_ERR_NO_SHMEM                -9
+
 /* SBI Extension IDs */
 #define SBI_EXT_0_1_SET_TIMER           0x0
 #define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
@@ -XXX,XX +XXX,XX @@
 #define SBI_EXT_IPI                     0x735049
 #define SBI_EXT_RFENCE                  0x52464E43
 #define SBI_EXT_HSM                     0x48534D
+#define SBI_EXT_DBCN                    0x4442434E
 
 /* SBI function IDs for BASE extension */
 #define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
@@ -XXX,XX +XXX,XX @@
 #define SBI_EXT_HSM_HART_STOP           0x1
 #define SBI_EXT_HSM_HART_GET_STATUS     0x2
 
+/* SBI function IDs for DBCN extension */
+#define SBI_EXT_DBCN_CONSOLE_WRITE      0x0
+#define SBI_EXT_DBCN_CONSOLE_READ       0x1
+#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
+
 #define SBI_HSM_HART_STATUS_STARTED     0x0
 #define SBI_HSM_HART_STATUS_STOPPED     0x1
 #define SBI_HSM_HART_STATUS_START_PENDING   0x2
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
                    KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
 };
 
+static KVMCPUConfig kvm_sbi_dbcn = {
+    .name = "sbi_dbcn",
+    .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
+                  KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
+};
+
 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
 {
     CPURISCVState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
     return 0;
 }
 
+static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
+                                             KVMScratchCPU *kvmcpu,
+                                             struct kvm_reg_list *reglist)
+{
+    struct kvm_reg_list *reg_search;
+
+    reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
+                         sizeof(uint64_t), uint64_cmp);
+
+    if (reg_search) {
+        kvm_sbi_dbcn.supported = true;
+    }
+}
+
 static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
                                  struct kvm_reg_list *reglist)
 {
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
     if (riscv_has_ext(&cpu->env, RVV)) {
         kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
     }
+
+    kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
 }
 
 static void riscv_init_kvm_registers(Object *cpu_obj)
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
     return ret;
 }
 
+static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
+{
+    target_ulong reg = 1;
+
+    if (!kvm_sbi_dbcn.supported) {
+        return 0;
+    }
+
+    return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
+}
+
 int kvm_arch_init_vcpu(CPUState *cs)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
     kvm_riscv_update_cpu_misa_ext(cpu, cs);
     kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
 
+    ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
+
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
     return true;
 }
 
+static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
+{
+    g_autofree uint8_t *buf = NULL;
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    target_ulong num_bytes;
+    uint64_t addr;
+    unsigned char ch;
+    int ret;
+
+    switch (run->riscv_sbi.function_id) {
+    case SBI_EXT_DBCN_CONSOLE_READ:
+    case SBI_EXT_DBCN_CONSOLE_WRITE:
+        num_bytes = run->riscv_sbi.args[0];
+
+        if (num_bytes == 0) {
+            run->riscv_sbi.ret[0] = SBI_SUCCESS;
+            run->riscv_sbi.ret[1] = 0;
+            break;
+        }
+
+        addr = run->riscv_sbi.args[1];
+
+        /*
+         * Handle the case where a 32 bit CPU is running in a
+         * 64 bit addressing env.
+         */
+        if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
+            addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
+        }
+
+        buf = g_malloc0(num_bytes);
+
+        if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
+            ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
+            if (ret < 0) {
+                error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
+                             "reading chardev");
+                exit(1);
+            }
+
+            cpu_physical_memory_write(addr, buf, ret);
+        } else {
+            cpu_physical_memory_read(addr, buf, num_bytes);
+
+            ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
+            if (ret < 0) {
+                error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
+                             "writing chardev");
+                exit(1);
+            }
+        }
+
+        run->riscv_sbi.ret[0] = SBI_SUCCESS;
+        run->riscv_sbi.ret[1] = ret;
+        break;
+    case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
+        ch = run->riscv_sbi.args[0];
+        ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
+
+        if (ret < 0) {
+            error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
+                         "writing chardev");
+            exit(1);
+        }
+
+        run->riscv_sbi.ret[0] = SBI_SUCCESS;
+        run->riscv_sbi.ret[1] = 0;
+        break;
+    default:
+        run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
+    }
+}
+
 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
         }
         ret = 0;
         break;
+    case SBI_EXT_DBCN:
+        kvm_riscv_handle_sbi_dbcn(cs, run);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP,
                       "%s: un-handled SBI EXIT, specific reasons is %lu\n",
-- 
2.45.1

From: Cheng Yang <yangcheng.work@foxmail.com>

Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
to set the address of initrd in FDT to support 64-bit address.

Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/boot.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
     /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
     if (fdt) {
         end = start + size;
-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
     }
 }
 
-- 
2.45.1

From: Clément Léger <cleger@rivosinc.com>

The current semihost exception number (16) is a reserved number (range
[16-17]). The upcoming double trap specification uses that number for
the double trap exception. Since the privileged spec (Table 22) defines
ranges for custom uses change the semihosting exception number to 63
which belongs to the range [48-63] in order to avoid any future
collisions with reserved exception.

Signed-off-by: Clément Léger <cleger@rivosinc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
-    RISCV_EXCP_SEMIHOST = 0x10,
     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
+    RISCV_EXCP_SEMIHOST = 0x3f,
 } RISCVException;
 
 #define RISCV_EXCP_INT_FLAG                0x80000000
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
enabled, will fail with a kernel oops SIGILL right at the start. The
reason is that we can't expose zkr without implementing the SEED CSR.
Disabling zkr in the guest would be a workaround, but if the KVM doesn't
allow it we'll error out and never boot.

In hindsight this is too strict. If we keep proceeding, despite not
disabling the extension in the KVM vcpu, we'll not add the extension in
the riscv,isa. The guest kernel will be unaware of the extension, i.e.
it doesn't matter if the KVM vcpu has it enabled underneath or not. So
it's ok to keep booting in this case.

Change our current logic to not error out if we fail to disable an
extension in kvm_set_one_reg(), but show a warning and keep booting. It
is important to throw a warning because we must make the user aware that
the extension is still available in the vcpu, meaning that an
ill-behaved guest can ignore the riscv,isa settings and  use the
extension.

The case we're handling happens with an EINVAL error code. If we fail to
disable the extension in KVM for any other reason, error out.

We'll also keep erroring out when we fail to enable an extension in KVM,
since adding the extension in riscv,isa at this point will cause a guest
malfunction because the extension isn't enabled in the vcpu.

Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
         reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
         ret = kvm_set_one_reg(cs, id, &reg);
         if (ret != 0) {
-            error_report("Unable to %s extension %s in KVM, error %d",
-                         reg ? "enable" : "disable",
-                         multi_ext_cfg->name, ret);
-            exit(EXIT_FAILURE);
+            if (!reg && ret == -EINVAL) {
+                warn_report("KVM cannot disable extension %s",
+                            multi_ext_cfg->name);
+            } else {
+                error_report("Unable to enable extension %s in KVM, error %d",
+                             multi_ext_cfg->name, ret);
+                exit(EXIT_FAILURE);
+            }
         }
     }
 }
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We're not setting (s/m)tval when triggering breakpoints of type 2
(mcontrol) and 6 (mcontrol6). According to the debug spec section
5.7.12, "Match Control Type 6":

"The Privileged Spec says that breakpoint exceptions that occur on
instruction fetches, loads, or stores update the tval CSR with either
zero or the faulting virtual address. The faulting virtual address for
an mcontrol6 trigger with action = 0 is the address being accessed and
which caused that trigger to fire."

A similar text is also found in the Debug spec section 5.7.11 w.r.t.
mcontrol.

Note that what we're doing ATM is not violating the spec, but it's
simple enough to set mtval/stval and it makes life easier for any
software that relies on this info.

Given that we always use action = 0, save the faulting address for the
mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
used as as scratch area for traps with address information. 'tval' is
then set during riscv_cpu_do_interrupt().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 1 +
 target/riscv/debug.c      | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
             tval = env->bins;
             break;
         case RISCV_EXCP_BREAKPOINT:
+            tval = env->badaddr;
             if (cs->watchpoint_hit) {
                 tval = cs->watchpoint_hit->hitaddr;
                 cs->watchpoint_hit = NULL;
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
                     /* check U/S/M bit against current privilege level */
                     if ((ctrl >> 3) & BIT(env->priv)) {
+                        env->badaddr = pc;
                         return true;
                     }
                 }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                     if (env->virt_enabled) {
                         /* check VU/VS bit against current privilege level */
                         if ((ctrl >> 23) & BIT(env->priv)) {
+                            env->badaddr = pc;
                             return true;
                         }
                     } else {
                         /* check U/S/M bit against current privilege level */
                         if ((ctrl >> 3) & BIT(env->priv)) {
+                            env->badaddr = pc;
                             return true;
                         }
                     }
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Privileged spec section 4.1.9 mentions:

"When a trap is taken into S-mode, stval is written with
exception-specific information to assist software in handling the trap.
(...)

If stval is written with a nonzero value when a breakpoint,
address-misaligned, access-fault, or page-fault exception occurs on an
instruction fetch, load, or store, then stval will contain the faulting
virtual address."

A similar text is found for mtval in section 3.1.16.

Setting mtval/stval in this scenario is optional, but some softwares read
these regs when handling ebreaks.

Write 'badaddr' in all ebreak breakpoints to write the appropriate
'tval' during riscv_do_cpu_interrrupt().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
     if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
     } else {
+        tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
+                      offsetof(CPURISCVState, badaddr));
         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
     }
     return true;
-- 
2.45.1

From: Jason Chien <jason.chien@sifive.com>

Add support for Zve32x extension and replace some checks for Zve32f with
Zve32x, since Zve32f depends on Zve32x.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h                  |  1 +
 target/riscv/cpu.c                      |  2 ++
 target/riscv/cpu_helper.c               |  2 +-
 target/riscv/csr.c                      |  2 +-
 target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
 target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
 6 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool ext_zhinx;
     bool ext_zhinxmin;
     bool ext_zve32f;
+    bool ext_zve32x;
     bool ext_zve64f;
     bool ext_zve64d;
     bool ext_zvbb;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
+    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
     MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
     MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
+    MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
     MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
     *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
     *cs_base = 0;
 
-    if (cpu->cfg.ext_zve32f) {
+    if (cpu->cfg.ext_zve32x) {
         /*
          * If env->vl equals to VLMAX, we can use generic vector operation
          * expanders (GVEC) to accerlate the vector operations.
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
 
 static RISCVException vs(CPURISCVState *env, int csrno)
 {
-    if (riscv_cpu_cfg(env)->ext_zve32f) {
+    if (riscv_cpu_cfg(env)->ext_zve32x) {
 #if !defined(CONFIG_USER_ONLY)
         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
             return RISCV_EXCP_ILLEGAL_INST;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
-    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
-        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
-        return;
+    /* The Zve32f extension depends on the Zve32x extension */
+    if (cpu->cfg.ext_zve32f) {
+        if (!riscv_has_ext(env, RVF)) {
+            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
+            return;
+        }
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
     }
 
     if (cpu->cfg.ext_zvfh) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
     }
 
-    /*
-     * In principle Zve*x would also suffice here, were they supported
-     * in qemu
-     */
     if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
          cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
-         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
+         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
         error_setg(errp,
                    "Vector crypto extensions require V or Zve* extensions");
         return;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
 {
     TCGv s1, dst;
 
-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
         return false;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
 {
     TCGv dst;
 
-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
         return false;
     }
 
-- 
2.45.1

From: Jason Chien <jason.chien@sifive.com>

Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
enabling Zve64x enables Zve32x according to their dependency.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h     |  1 +
 target/riscv/cpu.c         |  2 ++
 target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
 3 files changed, 14 insertions(+), 6 deletions(-)

From: Jason Chien <jason.chien@sifive.com>

In current implementation, the gdbstub allows reading vector registers
only if V extension is supported. However, all vector extensions and
vector crypto extensions have the vector registers and they all depend
on Zve32x. The gdbstub should check for Zve32x instead.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/gdbstub.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
                                  gdb_find_static_feature("riscv-32bit-fpu.xml"),
                                  0);
     }
-    if (env->misa_ext & RVV) {
+    if (cpu->cfg.ext_zve32x) {
         gdb_register_coprocessor(cs, riscv_gdb_get_vector,
                                  riscv_gdb_set_vector,
                                  ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
-- 
2.45.1

From: Huang Tao <eric.huang@linux.alibaba.com>

In RVV and vcrypto instructions, the masked and tail elements are set to 1s
using vext_set_elems_1s function if the vma/vta bit is set. It is the element
agnostic policy.

However, this function can't deal the big endian situation. This patch fixes
the problem by adding handling of such case.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_internals.c
+++ b/target/riscv/vector_internals.c
@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
     if (tot - cnt == 0) {
         return ;
     }
+
+    if (HOST_BIG_ENDIAN) {
+        /*
+         * Deal the situation when the elements are insdie
+         * only one uint64 block including setting the
+         * masked-off element.
+         */
+        if (((tot - 1) ^ cnt) < 8) {
+            memset(base + H1(tot - 1), -1, tot - cnt);
+            return;
+        }
+        /*
+         * Otherwise, at least cross two uint64_t blocks.
+         * Set first unaligned block.
+         */
+        if (cnt % 8 != 0) {
+            uint32_t j = ROUND_UP(cnt, 8);
+            memset(base + H1(j - 1), -1, j - cnt);
+            cnt = j;
+        }
+        /* Set other 64bit aligend blocks */
+    }
     memset(base + cnt, -1, tot - cnt);
 }
 
-- 
2.45.1

From: Yangyu Chen <cyy@cyyself.name>

This code has a typo that writes zvkb to zvkg, causing users can't
enable zvkb through the config. This patch gets this fixed.

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     /* Vector cryptography extensions */
     MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
     MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
-    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
+    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
     MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
     MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
     MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
-- 
2.45.1

From: Huang Tao <eric.huang@linux.alibaba.com>

In this patch, we modify the decoder to be a freely composable data
structure instead of a hardcoded one. It can be dynamically builded up
according to the extensions.
This approach has several benefits:
1. Provides support for heterogeneous cpu architectures. As we add decoder in
   RISCVCPU, each cpu can have their own decoder, and the decoders can be
   different due to cpu's features.
2. Improve the decoding efficiency. We run the guard_func to see if the decoder
   can be added to the dynamic_decoder when building up the decoder. Therefore,
   there is no need to run the guard_func when decoding each instruction. It can
   improve the decoding efficiency
3. For vendor or dynamic cpus, it allows them to customize their own decoder
   functions to improve decoding efficiency, especially when vendor-defined
   instruction sets increase. Because of dynamic building up, it can skip the other
   decoder guard functions when decoding.
4. Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
   overhead for users that don't need this particular vendor decoder.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  1 +
 target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
 target/riscv/cpu.c         |  1 +
 target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
 target/riscv/translate.c   | 31 +++++++++++++++----------------
 5 files changed, 47 insertions(+), 16 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
     uint32_t pmu_avail_ctrs;
     /* Mapping of events to counters */
     GHashTable *pmu_event_ctr_map;
+    const GPtrArray *decoders;
 };
 
 /**
diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.h
+++ b/target/riscv/tcg/tcg-cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
 
+struct DisasContext;
+struct RISCVCPUConfig;
+typedef struct RISCVDecoder {
+    bool (*guard_func)(const struct RISCVCPUConfig *);
+    bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
+} RISCVDecoder;
+
+typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
+
+extern const size_t decoder_table_size;
+
+extern const RISCVDecoder decoder_table[];
+
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
+
 #endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
             error_propagate(errp, local_err);
             return;
         }
+        riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
     } else if (kvm_enabled()) {
         riscv_kvm_cpu_finalize_features(cpu, &local_err);
         if (local_err != NULL) {
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
     }
 }
 
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
+{
+    GPtrArray *dynamic_decoders;
+    dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
+    for (size_t i = 0; i < decoder_table_size; ++i) {
+        if (decoder_table[i].guard_func &&
+            decoder_table[i].guard_func(&cpu->cfg)) {
+            g_ptr_array_add(dynamic_decoders,
+                            (gpointer)decoder_table[i].riscv_cpu_decode_fn);
+        }
+    }
+
+    cpu->decoders = dynamic_decoders;
+}
+
 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
 {
     return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/helper-info.c.inc"
 #undef  HELPER_H
 
+#include "tcg/tcg-cpu.h"
+
 /* global register indices */
 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     /* FRM is known to contain a valid value. */
     bool frm_valid;
     bool insn_start_updated;
+    const GPtrArray *decoders;
 } DisasContext;
 
 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
     return (first_word & 3) == 3 ? 4 : 2;
 }
 
+const RISCVDecoder decoder_table[] = {
+    { always_true_p, decode_insn32 },
+    { has_xthead_p, decode_xthead},
+    { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
+};
+
+const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
+
 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 {
-    /*
-     * A table with predicate (i.e., guard) functions and decoder functions
-     * that are tested in-order until a decoder matches onto the opcode.
-     */
-    static const struct {
-        bool (*guard_func)(const RISCVCPUConfig *);
-        bool (*decode_func)(DisasContext *, uint32_t);
-    } decoders[] = {
-        { always_true_p,  decode_insn32 },
-        { has_xthead_p, decode_xthead },
-        { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
-    };
-
     ctx->virt_inst_excp = false;
     ctx->cur_insn_len = insn_len(opcode);
     /* Check for compressed insn */
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
                                              ctx->base.pc_next + 2));
         ctx->opcode = opcode32;
 
-        for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
-            if (decoders[i].guard_func(ctx->cfg_ptr) &&
-                decoders[i].decode_func(ctx, opcode32)) {
+        for (guint i = 0; i < ctx->decoders->len; ++i) {
+            riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
+            if (func(ctx, opcode32)) {
                 return;
             }
         }
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
     ctx->zero = tcg_constant_tl(0);
     ctx->virt_inst_excp = false;
+    ctx->decoders = cpu->decoders;
 }
 
 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
-- 
2.45.1

From: Christoph Müllner <christoph.muellner@vrull.eu>

The th.sxstatus CSR can be used to identify available custom extension
on T-Head CPUs. The CSR is documented here:
  https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc

An important property of this patch is, that the th.sxstatus MAEE field
is not set (indicating that XTheadMae is not available).
XTheadMae is a memory attribute extension (similar to Svpbmt) which is
implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
in PTEs that are marked as reserved. QEMU maintainers prefer to not
implement XTheadMae, so we need give kernels a mechanism to identify
if XTheadMae is available in a system or not. And this patch introduces
this mechanism in QEMU in a way that's compatible with real HW
(i.e., probing the th.sxstatus.MAEE bit).

Further context can be found on the list:
https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html

Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 MAINTAINERS              |  1 +
 target/riscv/cpu.h       |  3 ++
 target/riscv/cpu.c       |  1 +
 target/riscv/th_csr.c    | 79 ++++++++++++++++++++++++++++++++++++++++
 target/riscv/meson.build |  1 +
 5 files changed, 85 insertions(+)
 create mode 100644 target/riscv/th_csr.c

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
 S: Supported
 F: target/riscv/insn_trans/trans_xthead.c.inc
 F: target/riscv/xthead*.decode
+F: target/riscv/th_*
 F: disas/riscv-xthead*
 
 RISC-V XVentanaCondOps extension
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
 uint8_t satp_mode_max_from_map(uint32_t map);
 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 
+/* Implemented in th_csr.c */
+void th_register_custom_csrs(RISCVCPU *cpu);
+
 #endif /* RISCV_CPU_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
     cpu->cfg.mvendorid = THEAD_VENDOR_ID;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_SV39);
+    th_register_custom_csrs(cpu);
 #endif
 
     /* inherited from parent obj via riscv_cpu_init() */
diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/th_csr.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * T-Head-specific CSRs.
+ *
+ * Copyright (c) 2024 VRULL GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "cpu_vendorid.h"
+
+#define CSR_TH_SXSTATUS 0x5c0
+
+/* TH_SXSTATUS bits */
+#define TH_SXSTATUS_UCME        BIT(16)
+#define TH_SXSTATUS_MAEE        BIT(21)
+#define TH_SXSTATUS_THEADISAEE  BIT(22)
+
+typedef struct {
+    int csrno;
+    int (*insertion_test)(RISCVCPU *cpu);
+    riscv_csr_operations csr_ops;
+} riscv_csr;
+
+static RISCVException smode(CPURISCVState *env, int csrno)
+{
+    if (riscv_has_ext(env, RVS)) {
+        return RISCV_EXCP_NONE;
+    }
+
+    return RISCV_EXCP_ILLEGAL_INST;
+}
+
+static int test_thead_mvendorid(RISCVCPU *cpu)
+{
+    if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
+        return -1;
+    }
+
+    return 0;
+}
+
+static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
+                                       target_ulong *val)
+{
+    /* We don't set MAEE here, because QEMU does not implement MAEE. */
+    *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
+    return RISCV_EXCP_NONE;
+}
+
+static riscv_csr th_csr_list[] = {
+    {
+        .csrno = CSR_TH_SXSTATUS,
+        .insertion_test = test_thead_mvendorid,
+        .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
+    }
+};
+
+void th_register_custom_csrs(RISCVCPU *cpu)
+{
+    for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
+        int csrno = th_csr_list[i].csrno;
+        riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
+        if (!th_csr_list[i].insertion_test(cpu)) {
+            riscv_set_csr_ops(csrno, csr_ops);
+        }
+    }
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
   'monitor.c',
   'machine.c',
   'pmu.c',
+  'th_csr.c',
   'time_helper.c',
   'riscv-qmp-cmds.c',
 ))
-- 
2.45.1

From: Max Chou <max.chou@sifive.com>

According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
instructions will be affected by Zvfhmin extension.
And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
conversions of

* From 1*SEW(16/32) to 2*SEW(32/64)
* From 2*SEW(32/64) to 1*SEW(16/32)

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

From: Max Chou <max.chou@sifive.com>

The require_scale_rvf function only checks the double width operator for
the vector floating point widen instructions, so most of the widen
checking functions need to add require_rvf for single width operator.

The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
integer to double width float, so the opfxv_widen_check function doesn’t
need require_rvf for the single width operator(integer).

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
 1 file changed, 5 insertions(+)

From: Max Chou <max.chou@sifive.com>

If the checking functions check both the single and double width
operators at the same time, then the single width operator checking
functions (require_rvf[min]) will check whether the SEW is 8.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_ds(s, a->rd, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dd(s, a->rd, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_widen_check(s, a) &&
            require_rvfmin(s) &&
-           require_scale_rvfmin(s) &&
-           (s->sew != MO_8);
+           require_scale_rvfmin(s);
 }
 
 #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_rvfmin(s) &&
-           require_scale_rvfmin(s) &&
-           (s->sew != MO_8);
+           require_scale_rvfmin(s);
 }
 
 static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_rvf(s) &&
-           require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           require_scale_rvf(s);
 }
 
 #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
 {
     return reduction_widen_check(s, a) &&
            require_rvf(s) &&
-           require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           require_scale_rvf(s);
 }
 
 GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

raise_mmu_exception(), as is today, is prioritizing guest page faults by
checking first if virt_enabled && !first_stage, and then considering the
regular inst/load/store faults.

There's no mention in the spec about guest page fault being a higher
priority that PMP faults. In fact, privileged spec section 3.7.1 says:

"Attempting to fetch an instruction from a PMP region that does not have
execute permissions raises an instruction access-fault exception.
Attempting to execute a load or load-reserved instruction which accesses
a physical address within a PMP region without read permissions raises a
load access-fault exception. Attempting to execute a store,
store-conditional, or AMO instruction which accesses a physical address
within a PMP region without write permissions raises a store
access-fault exception."

So, in fact, we're doing it wrong - PMP faults should always be thrown,
regardless of also being a first or second stage fault.

The way riscv_cpu_tlb_fill() and get_physical_address() work is
adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
reflected in the 'pmp_violation' flag. What we need is to change
raise_mmu_exception() to prioritize it.

Reported-by: Joseph Chan <jchan@ventanamicro.com>
Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
 
     switch (access_type) {
     case MMU_INST_FETCH:
-        if (env->virt_enabled && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
+        } else if (env->virt_enabled && !first_stage) {
             cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
         }
         break;
     case MMU_DATA_LOAD:
-        if (two_stage && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
+        } else if (two_stage && !first_stage) {
             cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
         }
         break;
     case MMU_DATA_STORE:
-        if (two_stage && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
+        } else if (two_stage && !first_stage) {
             cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
-                RISCV_EXCP_STORE_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
         }
         break;
     default:
-- 
2.45.1

From: Alexei Filippov <alexei.filippov@syntacore.com>

Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
translation part, mtval2 will be set in case of successes 2 stage translation but
failed pmp check.

In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
page-fault is taken into M-mode, mtval2 is written with either zero or guest
physical address that faulted, shifted by 2 bits. *For other traps, mtval2
is set to zero...*

Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                               __func__, pa, ret, prot_pmp, tlb_size);
 
                 prot &= prot_pmp;
-            }
-
-            if (ret != TRANSLATE_SUCCESS) {
+            } else {
                 /*
                  * Guest physical address translation failed, this is a HS
                  * level exception
                  */
                 first_stage_error = false;
-                env->guest_phys_fault_addr = (im_address |
-                                              (address &
-                                               (TARGET_PAGE_SIZE - 1))) >> 2;
+                if (ret != TRANSLATE_PMP_FAIL) {
+                    env->guest_phys_fault_addr = (im_address |
+                                                  (address &
+                                                   (TARGET_PAGE_SIZE - 1))) >> 2;
+                }
             }
         }
     } else {
-- 
2.45.1

From: Rob Bradford <rbradford@rivosinc.com>

This extension has now been ratified:
https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
removed.

Since this is now a ratified extension add it to the list of extensions
included in the "max" CPU variant.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c         | 2 +-
 target/riscv/tcg/tcg-cpu.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
     MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
     MISA_EXT_INFO(RVV, "v", "Vector operations"),
     MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
-    MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
+    MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
 };
 
 static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
     const RISCVCPUMultiExtConfig *prop;
 
     /* Enable RVG, RVJ and RVV that are disabled by default */
-    riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
+    riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
 
     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
         isa_ext_update_enabled(cpu, prop->offset, true);
-- 
2.45.1

From: Alistair Francis <alistair23@gmail.com>

When running the instruction

```
    cbo.flush 0(x0)
```

QEMU would segfault.

The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
allocated.

In order to fix this let's use the existing get_address()
helper. This also has the benefit of performing pointer mask
calculations on the address specified in rs1.

The pointer masking specificiation specifically states:

"""
Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
"""

So this is the correct behaviour and we previously have been incorrectly
not masking the address.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
@@ -XXX,XX +XXX,XX @@
 static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_clean_flush(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_clean_flush(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_inval(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
 {
     REQUIRE_ZICBOZ(ctx);
-    gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_zero(tcg_env, src);
     return true;
 }
-- 
2.45.1

From: Yong-Xuan Wang <yongxuan.wang@sifive.com>

In AIA spec, each hart (or each hart within a group) has a unique hart
number to locate the memory pages of interrupt files in the address
space. The number of bits required to represent any hart number is equal
to ceil(log2(hmax + 1)), where hmax is the largest hart number among
groups.

However, if the largest hart number among groups is a power of 2, QEMU
will pass an inaccurate hart-index-bit setting to Linux. For example, when
the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
to represent 4 harts, but we passes 3 to Linux. The code needs to be
updated to ensure accurate hart-index-bit settings.

Additionally, a Linux patch[1] is necessary to correctly recover the hart
index when the guest OS has only 1 hart, where the hart-index-bit is 0.

[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
         }
     }
 
-    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+
+    if (max_hart_per_socket > 1) {
+        max_hart_per_socket--;
+        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+    } else {
+        hart_bits = 0;
+    }
+
     ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
                             KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
                             &hart_bits, true, NULL);
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
in bytes, when in this context we want 'reg_width' as the length in
bits.

Fix 'reg_width' back to the value in bits like 7cb59921c05a
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
beforehand.

While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
clarity about what the variable represents. 'bitsize' is also used in
riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
gdb_feature_builder_append_reg().

Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/gdbstub.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
 static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
-    int reg_width = cpu->cfg.vlenb;
+    int bitsize = cpu->cfg.vlenb << 3;
     GDBFeatureBuilder builder;
     int i;
 
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
 
     /* First define types and totals in a whole VL */
     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
-        int count = reg_width / vec_lanes[i].size;
+        int count = bitsize / vec_lanes[i].size;
         gdb_feature_builder_append_tag(
             &builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
             vec_lanes[i].id, vec_lanes[i].gdb_type, count);
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
     /* Define vector registers */
     for (i = 0; i < 32; i++) {
         gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
-                                       reg_width, i, "riscv_vector", "vector");
+                                       bitsize, i, "riscv_vector", "vector");
     }
 
     gdb_feature_builder_end(&builder);
-- 
2.45.1

From: Alistair Francis <alistair23@gmail.com>

Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
CSRs are part of the disassembly.

Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Fixes: ea10325917 ("RISC-V Disassembler")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 64 insertions(+), 1 deletion(-)

diff --git a/disas/riscv.c b/disas/riscv.c
index XXXXXXX..XXXXXXX 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x0383: return "mibound";
     case 0x0384: return "mdbase";
     case 0x0385: return "mdbound";
-    case 0x03a0: return "pmpcfg3";
+    case 0x03a0: return "pmpcfg0";
+    case 0x03a1: return "pmpcfg1";
+    case 0x03a2: return "pmpcfg2";
+    case 0x03a3: return "pmpcfg3";
+    case 0x03a4: return "pmpcfg4";
+    case 0x03a5: return "pmpcfg5";
+    case 0x03a6: return "pmpcfg6";
+    case 0x03a7: return "pmpcfg7";
+    case 0x03a8: return "pmpcfg8";
+    case 0x03a9: return "pmpcfg9";
+    case 0x03aa: return "pmpcfg10";
+    case 0x03ab: return "pmpcfg11";
+    case 0x03ac: return "pmpcfg12";
+    case 0x03ad: return "pmpcfg13";
+    case 0x03ae: return "pmpcfg14";
+    case 0x03af: return "pmpcfg15";
     case 0x03b0: return "pmpaddr0";
     case 0x03b1: return "pmpaddr1";
     case 0x03b2: return "pmpaddr2";
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x03bd: return "pmpaddr13";
     case 0x03be: return "pmpaddr14";
     case 0x03bf: return "pmpaddr15";
+    case 0x03c0: return "pmpaddr16";
+    case 0x03c1: return "pmpaddr17";
+    case 0x03c2: return "pmpaddr18";
+    case 0x03c3: return "pmpaddr19";
+    case 0x03c4: return "pmpaddr20";
+    case 0x03c5: return "pmpaddr21";
+    case 0x03c6: return "pmpaddr22";
+    case 0x03c7: return "pmpaddr23";
+    case 0x03c8: return "pmpaddr24";
+    case 0x03c9: return "pmpaddr25";
+    case 0x03ca: return "pmpaddr26";
+    case 0x03cb: return "pmpaddr27";
+    case 0x03cc: return "pmpaddr28";
+    case 0x03cd: return "pmpaddr29";
+    case 0x03ce: return "pmpaddr30";
+    case 0x03cf: return "pmpaddr31";
+    case 0x03d0: return "pmpaddr32";
+    case 0x03d1: return "pmpaddr33";
+    case 0x03d2: return "pmpaddr34";
+    case 0x03d3: return "pmpaddr35";
+    case 0x03d4: return "pmpaddr36";
+    case 0x03d5: return "pmpaddr37";
+    case 0x03d6: return "pmpaddr38";
+    case 0x03d7: return "pmpaddr39";
+    case 0x03d8: return "pmpaddr40";
+    case 0x03d9: return "pmpaddr41";
+    case 0x03da: return "pmpaddr42";
+    case 0x03db: return "pmpaddr43";
+    case 0x03dc: return "pmpaddr44";
+    case 0x03dd: return "pmpaddr45";
+    case 0x03de: return "pmpaddr46";
+    case 0x03df: return "pmpaddr47";
+    case 0x03e0: return "pmpaddr48";
+    case 0x03e1: return "pmpaddr49";
+    case 0x03e2: return "pmpaddr50";
+    case 0x03e3: return "pmpaddr51";
+    case 0x03e4: return "pmpaddr52";
+    case 0x03e5: return "pmpaddr53";
+    case 0x03e6: return "pmpaddr54";
+    case 0x03e7: return "pmpaddr55";
+    case 0x03e8: return "pmpaddr56";
+    case 0x03e9: return "pmpaddr57";
+    case 0x03ea: return "pmpaddr58";
+    case 0x03eb: return "pmpaddr59";
+    case 0x03ec: return "pmpaddr60";
+    case 0x03ed: return "pmpaddr61";
+    case 0x03ee: return "pmpaddr62";
+    case 0x03ef: return "pmpaddr63";
     case 0x0780: return "mtohost";
     case 0x0781: return "mfromhost";
     case 0x0782: return "mreset";
-- 
2.45.1

From: Yu-Ming Chang <yumin686@andestech.com>

Both CSRRS and CSRRC always read the addressed CSR and cause any read side
effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
holding a zero value other than x0, the instruction will still attempt to write
the unmodified value back to the CSR and will cause any attendant side effects.

So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
a register holding a zero value, an illegal instruction exception should be
raised.

Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h       |  4 ++++
 target/riscv/csr.c       | 51 ++++++++++++++++++++++++++++++++++++----
 target/riscv/op_helper.c |  6 ++---
 3 files changed, 53 insertions(+), 8 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
 void riscv_cpu_update_mask(CPURISCVState *env);
 bool riscv_cpu_is_32bit(RISCVCPU *cpu);
 
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+                          target_ulong *ret_value);
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask);
@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
                                           target_ulong new_value,
                                           target_ulong write_mask);
 
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+                               Int128 *ret_value);
 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                 Int128 *ret_value,
                                 Int128 new_value, Int128 write_mask);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
 
 static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
                                                int csrno,
-                                               bool write_mask)
+                                               bool write)
 {
     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
     bool read_only = get_field(csrno, 0xC00) == 3;
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
     }
 
     /* read / write check */
-    if (write_mask && read_only) {
+    if (write && read_only) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+                           target_ulong *ret_value)
+{
+    RISCVException ret = riscv_csrrw_check(env, csrno, false);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
+}
+
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask)
 {
-    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
+    RISCVException ret = riscv_csrrw_check(env, csrno, true);
     if (ret != RISCV_EXCP_NONE) {
         return ret;
     }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+                               Int128 *ret_value)
+{
+    RISCVException ret;
+
+    ret = riscv_csrrw_check(env, csrno, false);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    if (csr_ops[csrno].read128) {
+        return riscv_csrrw_do128(env, csrno, ret_value,
+                                 int128_zero(), int128_zero());
+    }
+
+    /*
+     * Fall back to 64-bit version for now, if the 128-bit alternative isn't
+     * at all defined.
+     * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
+     * significant), for those, this fallback is correctly handling the
+     * accesses
+     */
+    target_ulong old_value;
+    ret = riscv_csrrw_do64(env, csrno, &old_value,
+                           (target_ulong)0,
+                           (target_ulong)0);
+    if (ret == RISCV_EXCP_NONE && ret_value) {
+        *ret_value = int128_make64(old_value);
+    }
+    return ret;
+}
+
 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                 Int128 *ret_value,
                                 Int128 new_value, Int128 write_mask)
 {
     RISCVException ret;
 
-    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
+    ret = riscv_csrrw_check(env, csrno, true);
     if (ret != RISCV_EXCP_NONE) {
         return ret;
     }
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
     }
 
     target_ulong val = 0;
-    RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
+    RISCVException ret = riscv_csrr(env, csr, &val);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
 target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
 {
     Int128 rv = int128_zero();
-    RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
-                                          int128_zero(),
-                                          int128_zero());
+    RISCVException ret = riscv_csrr_i128(env, csr, &rv);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
-- 
2.45.1