On 10/22/21 6:37 AM, Alistair Francis wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The following changes since commit 4c127fdbe81d66e7cafed90908d0fd1f6f2a6cd0:
>
> Merge remote-tracking branch 'remotes/rth/tags/pull-arm-20211021' into staging (2021-10-21 09:53:27 -0700)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211022-2
>
> for you to fetch changes up to 11ec06f9eaedc801ded34c79861367b76ab2b731:
>
> hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id (2021-10-22 23:35:47 +1000)
>
> ----------------------------------------------------------------
> Fourth RISC-V PR for QEMU 6.2
>
> - Vector extension bug fixes
> - Bit manipulation extension bug fix
> - Support vhost-user and numa mem options on all boards
> - Rationalise XLEN and operand lengths
> - Bump the OpenTitan FPGA support
> - Remove the Ibex PLIC
> - General code cleanup
>
> ----------------------------------------------------------------
> Alistair Francis (7):
> target/riscv: Remove some unused macros
> target/riscv: Organise the CPU properties
> hw/riscv: opentitan: Update to the latest build
> hw/intc: Remove the Ibex PLIC
> hw/intc: sifive_plic: Move the properties
> hw/intc: sifive_plic: Cleanup the realize function
> hw/intc: sifive_plic: Cleanup the irq_request function
>
> Bin Meng (6):
> hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
> hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
> hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id
> hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
> hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id
> hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id
>
> Frank Chang (2):
> target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v
> target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
>
> Mingwang Li (1):
> hw/riscv: virt: Use machine->ram as the system memory
>
> Philipp Tomsich (1):
> target/riscv: Fix orc.b implementation
>
> Richard Henderson (15):
> target/riscv: Move cpu_get_tb_cpu_state out of line
> target/riscv: Create RISCVMXL enumeration
> target/riscv: Split misa.mxl and misa.ext
> target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
> target/riscv: Add MXL/SXL/UXL to TB_FLAGS
> target/riscv: Use REQUIRE_64BIT in amo_check64
> target/riscv: Properly check SEW in amo_op
> target/riscv: Replace is_32bit with get_xl/get_xlen
> target/riscv: Replace DisasContext.w with DisasContext.ol
> target/riscv: Use gen_arith_per_ol for RVM
> target/riscv: Adjust trans_rev8_32 for riscv64
> target/riscv: Use gen_unary_per_ol for RVB
> target/riscv: Use gen_shift*_per_ol for RVB, RVI
> target/riscv: Use riscv_csrrw_debug for cpu_dump
> target/riscv: Compute mstatus.sd on demand
>
> Travis Geiselbrecht (1):
> target/riscv: line up all of the registers in the info register dump
>
> include/hw/riscv/opentitan.h | 6 +-
> target/riscv/cpu.h | 87 +++------
> target/riscv/cpu_bits.h | 16 +-
> hw/intc/ibex_plic.c | 307 --------------------------------
> hw/intc/sifive_plic.c | 85 ++++-----
> hw/riscv/boot.c | 2 +-
> hw/riscv/microchip_pfsoc.c | 36 ++--
> hw/riscv/opentitan.c | 38 +++-
> hw/riscv/shakti_c.c | 6 +-
> hw/riscv/sifive_e.c | 16 +-
> hw/riscv/sifive_u.c | 6 +-
> hw/riscv/spike.c | 6 +-
> hw/riscv/virt.c | 6 +-
> linux-user/elfload.c | 2 +-
> linux-user/riscv/cpu_loop.c | 2 +-
> semihosting/arm-compat-semi.c | 2 +-
> target/riscv/cpu.c | 216 ++++++++++++----------
> target/riscv/cpu_helper.c | 92 +++++++++-
> target/riscv/csr.c | 104 ++++++-----
> target/riscv/gdbstub.c | 10 +-
> target/riscv/machine.c | 10 +-
> target/riscv/monitor.c | 4 +-
> target/riscv/translate.c | 174 +++++++++++++-----
> target/riscv/insn_trans/trans_rvb.c.inc | 153 +++++++++-------
> target/riscv/insn_trans/trans_rvi.c.inc | 44 ++---
> target/riscv/insn_trans/trans_rvm.c.inc | 36 +++-
> target/riscv/insn_trans/trans_rvv.c.inc | 32 ++--
> hw/intc/meson.build | 1 -
> 28 files changed, 720 insertions(+), 779 deletions(-)
> delete mode 100644 hw/intc/ibex_plic.c
Applied, thanks.
r~