[RFC PATCH] target/mips: Fix DEXTRV_S.H DSP opcode

Philippe Mathieu-Daudé posted 1 patch 1 week, 3 days ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20211013215652.1764551-1-f4bug@amsat.org
Maintainers: Jiaxun Yang <jiaxun.yang@flygoat.com>, Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>, Aurelien Jarno <aurelien@aurel32.net>, "Philippe Mathieu-Daudé" <f4bug@amsat.org>
target/mips/tcg/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)

[RFC PATCH] target/mips: Fix DEXTRV_S.H DSP opcode

Posted by Philippe Mathieu-Daudé 1 week, 3 days ago
While for the DEXTR_S.H opcode:

  "The shift argument is provided in the instruction."

For the DEXTRV_S.H opcode we have:

  "The five least-significant bits of register rs provide the
   shift argument, interpreted as a five-bit unsigned integer;
   the remaining bits in rs are ignored."

While 't1' contains the 'rs' register content (the shift value
for DEXTR_S.H), we need to load the value of 'rs' for DEXTRV_S.H.
We can directly use the v1_t TCG register which already contains
this shift value.

Fixes: b53371ed5d4 ("target-mips: Add ASE DSP accumulator instructions")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/translate.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 148afec9dc0..794676d42ff 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -13807,8 +13807,7 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
             break;
         case OPC_DEXTRV_S_H:
             tcg_gen_movi_tl(t0, v2);
-            tcg_gen_movi_tl(t1, v1);
-            gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, cpu_env);
+            gen_helper_dextr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env);
             break;
         case OPC_DEXTRV_L:
             tcg_gen_movi_tl(t0, v2);
-- 
2.31.1

Re: [RFC PATCH] target/mips: Fix DEXTRV_S.H DSP opcode

Posted by Richard Henderson 1 week, 3 days ago
On 10/13/21 2:56 PM, Philippe Mathieu-Daudé wrote:
> While for the DEXTR_S.H opcode:
> 
>    "The shift argument is provided in the instruction."
> 
> For the DEXTRV_S.H opcode we have:
> 
>    "The five least-significant bits of register rs provide the
>     shift argument, interpreted as a five-bit unsigned integer;
>     the remaining bits in rs are ignored."
> 
> While 't1' contains the 'rs' register content (the shift value
> for DEXTR_S.H), we need to load the value of 'rs' for DEXTRV_S.H.
> We can directly use the v1_t TCG register which already contains
> this shift value.
> 
> Fixes: b53371ed5d4 ("target-mips: Add ASE DSP accumulator instructions")
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/tcg/translate.c | 3 +--
>   1 file changed, 1 insertion(+), 2 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~