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[81.36.146.213]) by smtp.gmail.com with ESMTPSA id g25sm648150wrc.88.2021.10.13.14.56.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Oct 2021 14:56:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=XvQIBSYHx12a/BVOjXjE2X8s1e9rx86Vec8AEgTlEes=; b=a34XM48qIBbQsneFlW369sCz1Th+UmJUYyrFopilwD4QbNwuVBYT8bX71uURjAspyu zW/nEz9EC5OEhvkfYvsDgDrVOMZKP967F4A2xe+rDZFu20IPiFnfdyKvPcuSVYyX9Ydv 7LWi6kwbv8iOKWsur8fyHOhf/J7vHFU3Tgug6TYwnnPh1qMeZUvwvxbROqqj8Ydt7AFi 2Tpv5sIOcj5Di4+LcIxKjW4kngBeQwKmjV9v+qFVo2wH8D0A0RoWNzsPbq2tpNNZiOH7 lmqALp0QnNuF7GM3iNIp33TQZ5fJsBn/KcoVBet/6IT5/mlXgGFcBNZX054sf2+JDKjb gP+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=XvQIBSYHx12a/BVOjXjE2X8s1e9rx86Vec8AEgTlEes=; b=Mq6Z9JLgZE++2JyWoYy+YOe0ZD0Ox9QTO9b7CJSplJDh905wZPwWl4HNMgPO+y+RA0 3EK3LR1j4ppR1NW6MA54LD3Q8YoL3I2KYcznP2Gba7AVFfEOTMI2NfUrNHIUiMrLDk7g VEsLbd2cpebx52x0Cktd8vK8fPDDdTCHfCO4zVEEzNQDpC+0zsx2F86nYex018dF7UkS HA3QunLw5XHAP1y1jzUWHpRXEu7CVVAiYMY1Bz8kJRO5yNP7uWT3iazUgmGGSnNsD/q/ hIywziesV38PNu1nOrBC23aMQEGU9xGPP0maqWQcrIZrxxLUvCJ/QxyYAQLDTMtPfwDu 605Q== X-Gm-Message-State: AOAM532+b+hTPkbiFrQZpcLpR13h3K+zQRHqC6q4Pg+v5DQlnnau0b18 owrc3IKBdriGxwdvtI+cTIk= X-Google-Smtp-Source: ABdhPJweOEDSFq1SfQUGBUCUlkrNl8Bx4+EXGt2LDQ96RFdxD6LrLxL3BiYwsYCxin3mL9ymhjeosQ== X-Received: by 2002:a05:600c:4f81:: with SMTP id n1mr15340878wmq.63.1634162214713; Wed, 13 Oct 2021 14:56:54 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aleksandar Rikalo , Aurelien Jarno , Jia Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [RFC PATCH] target/mips: Fix DEXTRV_S.H DSP opcode Date: Wed, 13 Oct 2021 23:56:52 +0200 Message-Id: <20211013215652.1764551-1-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1634162217730100001 While for the DEXTR_S.H opcode: "The shift argument is provided in the instruction." For the DEXTRV_S.H opcode we have: "The five least-significant bits of register rs provide the shift argument, interpreted as a five-bit unsigned integer; the remaining bits in rs are ignored." While 't1' contains the 'rs' register content (the shift value for DEXTR_S.H), we need to load the value of 'rs' for DEXTRV_S.H. We can directly use the v1_t TCG register which already contains this shift value. Fixes: b53371ed5d4 ("target-mips: Add ASE DSP accumulator instructions") Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/tcg/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 148afec9dc0..794676d42ff 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -13807,8 +13807,7 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, = uint32_t op1, uint32_t op2, break; case OPC_DEXTRV_S_H: tcg_gen_movi_tl(t0, v2); - tcg_gen_movi_tl(t1, v1); - gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, cpu_env); + gen_helper_dextr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env); break; case OPC_DEXTRV_L: tcg_gen_movi_tl(t0, v2); --=20 2.31.1