arm queue: big stuff here is my MVE codegen optimisation,

and Alex's Apple Silicon hvf support.

The following changes since commit 7adb961995a3744f51396502b33ad04a56a317c3:

Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20210916' into staging (2021-09-19 18:53:29 +0100)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210920

for you to fetch changes up to 1dc5a60bfe406bc1122d68cbdefda38d23134b27:

target/arm: Optimize MVE 1op-immediate insns (2021-09-20 14:18:01 +0100)

* Optimize codegen for MVE when predication not active

* hvf: Add Apple Silicon support

* hw/intc: Set GIC maintenance interrupt level to only 0 or 1

* Fix mishandling of MVE FPSCR.LTPSIZE reset for usermode emulator

* elf2dmp: Fix coverity nits

Alexander Graf (7):

arm: Move PMC register definitions to internals.h

hvf: Add execute to dirty log permission bitmap

hvf: Introduce hvf_arch_init() callback

hvf: Add Apple Silicon support

hvf: arm: Implement PSCI handling

arm: Add Hypervisor.framework build target

hvf: arm: Add rudimentary PMC support

Peter Collingbourne (1):

arm/hvf: Add a WFI handler

Peter Maydell (18):

elf2dmp: Check curl_easy_setopt() return value

elf2dmp: Fail cleanly if PDB file specifies zero block_size

target/arm: Don't skip M-profile reset entirely in user mode

target/arm: Always clear exclusive monitor on reset

target/arm: Consolidate ifdef blocks in reset

hvf: arm: Implement -cpu host

target/arm: Avoid goto_tb if we're trying to exit to the main loop

target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration

target/arm: Add TB flag for "MVE insns not predicated"

target/arm: Optimize MVE logic ops

target/arm: Optimize MVE arithmetic ops

target/arm: Optimize MVE VNEG, VABS

target/arm: Optimize MVE VDUP

target/arm: Optimize MVE VMVN

target/arm: Optimize MVE VSHL, VSHR immediate forms

target/arm: Optimize MVE VSHLL and VMOVL

target/arm: Optimize MVE VSLI and VSRI

target/arm: Optimize MVE 1op-immediate insns

Shashi Mallela (1):

hw/intc: Set GIC maintenance interrupt level to only 0 or 1

meson.build | 8 +

include/sysemu/hvf_int.h | 12 +-

target/arm/cpu.h | 6 +-

target/arm/hvf_arm.h | 18 +

target/arm/internals.h | 44 ++

target/arm/kvm_arm.h | 2 -

target/arm/translate.h | 2 +

accel/hvf/hvf-accel-ops.c | 21 +-

contrib/elf2dmp/download.c | 22 +-

contrib/elf2dmp/pdb.c | 4 +

hw/intc/arm_gicv3_cpuif.c | 5 +-

target/arm/cpu.c | 56 +-

target/arm/helper.c | 77 ++-

target/arm/hvf/hvf.c | 1278 +++++++++++++++++++++++++++++++++++++++++

target/arm/machine.c | 13 +

target/arm/translate-m-nocp.c | 8 +-

target/arm/translate-mve.c | 310 +++++++---

target/arm/translate-vfp.c | 33 +-

target/arm/translate.c | 42 +-

target/i386/hvf/hvf.c | 10 +

MAINTAINERS | 5 +

target/arm/hvf/meson.build | 3 +

target/arm/hvf/trace-events | 11 +

target/arm/meson.build | 2 +

24 files changed, 1824 insertions(+), 168 deletions(-)

create mode 100644 target/arm/hvf_arm.h

create mode 100644 target/arm/hvf/hvf.c

create mode 100644 target/arm/hvf/meson.build

create mode 100644 target/arm/hvf/trace-events

Now that we have working system register sync, we push more target CPU

properties into the virtual machine. That might be useful in some

situations, but is not the typical case that users want.

So let's add a -cpu host option that allows them to explicitly pass all

CPU capabilities of their host CPU into the guest.

Message-id: 20210916155404.86958-7-agraf@csgraf.de

[PMM: drop unnecessary #include line from .h file]

target/arm/cpu.h | 2 +

target/arm/hvf_arm.h | 18 +++++++++

target/arm/kvm_arm.h | 2 -

target/arm/cpu.c | 13 ++++--

target/arm/hvf/hvf.c | 95 ++++++++++++++++++++++++++++++++++++++++++++

5 files changed, 124 insertions(+), 6 deletions(-)

create mode 100644 target/arm/hvf_arm.h

@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);

#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)

#define CPU_RESOLVING_TYPE TYPE_ARM_CPU

+#define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU

#define cpu_signal_handler cpu_arm_signal_handler

#define cpu_list arm_cpu_list

diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/target/arm/hvf_arm.h

@@ -XXX,XX +XXX,XX @@

+/*

+ * QEMU Hypervisor.framework (HVF) support -- ARM specifics

+ *

+ * Copyright (c) 2021 Alexander Graf

+ *

+ * This work is licensed under the terms of the GNU GPL, version 2 or later.

+ * See the COPYING file in the top-level directory.

+ *

+ */

+

+#ifndef QEMU_HVF_ARM_H

+#define QEMU_HVF_ARM_H

+

+#include "cpu.h"

+

+void hvf_arm_set_cpu_features_from_host(struct ARMCPU *cpu);

+

+#endif

diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/kvm_arm.h

+++ b/target/arm/kvm_arm.h

@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,

*/

void kvm_arm_destroy_scratch_host_vcpu(int *fdarray);

-#define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU

-

/**

* ARMHostCPUFeatures: information about the host CPU (identified

* by asking the host kernel)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.c

+++ b/target/arm/cpu.c

@@ -XXX,XX +XXX,XX @@

#include "sysemu/tcg.h"

#include "sysemu/hw_accel.h"

#include "kvm_arm.h"

+#include "hvf_arm.h"

#include "disas/capstone.h"

#include "fpu/softfloat.h"

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)

* this is the first point where we can report it.

*/

if (cpu->host_cpu_probe_failed) {

- if (!kvm_enabled()) {

- error_setg(errp, "The 'host' CPU type can only be used with KVM");

+ if (!kvm_enabled() && !hvf_enabled()) {

+ error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF");

} else {

error_setg(errp, "Failed to retrieve host CPU features");

}

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)

#endif /* CONFIG_TCG */

}

-#ifdef CONFIG_KVM

+#if defined(CONFIG_KVM) || defined(CONFIG_HVF)

static void arm_host_initfn(Object *obj)

{

ARMCPU *cpu = ARM_CPU(obj);

+#ifdef CONFIG_KVM

kvm_arm_set_cpu_features_from_host(cpu);

if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {

aarch64_add_sve_properties(obj);

}

+#else

+ hvf_arm_set_cpu_features_from_host(cpu);

+#endif

arm_cpu_post_init(obj);

}

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_register_types(void)

{

type_register_static(&arm_cpu_type_info);

-#ifdef CONFIG_KVM

+#if defined(CONFIG_KVM) || defined(CONFIG_HVF)

type_register_static(&host_arm_cpu_type_info);

#endif

}

diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/hvf/hvf.c

+++ b/target/arm/hvf/hvf.c

@@ -XXX,XX +XXX,XX @@

#include "sysemu/hvf.h"

#include "sysemu/hvf_int.h"

#include "sysemu/hw_accel.h"

+#include "hvf_arm.h"

#include <mach/mach_time.h>

@@ -XXX,XX +XXX,XX @@ typedef struct HVFVTimer {

static HVFVTimer vtimer;

+typedef struct ARMHostCPUFeatures {

+ ARMISARegisters isar;

+ uint64_t features;

+ uint64_t midr;

+ uint32_t reset_sctlr;

+ const char *dtb_compatible;

+} ARMHostCPUFeatures;

+

+static ARMHostCPUFeatures arm_host_cpu_features;

+

struct hvf_reg_match {

int reg;

uint64_t offset;

@@ -XXX,XX +XXX,XX @@ static uint64_t hvf_get_reg(CPUState *cpu, int rt)

return val;

}

+static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)

+{

+ ARMISARegisters host_isar = {};

+ const struct isar_regs {

+ int reg;

+ uint64_t *val;

+ } regs[] = {

+ { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.id_aa64pfr0 },

+ { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 },

+ { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 },

+ { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 },

+ { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 },

+ { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 },

+ { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 },

+ { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 },

+ { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 },

+ };

+ hv_vcpu_t fd;

+ hv_return_t r = HV_SUCCESS;

+ hv_vcpu_exit_t *exit;

+ int i;

+

+ ahcf->dtb_compatible = "arm,arm-v8";

+ ahcf->features = (1ULL << ARM_FEATURE_V8) |

+ (1ULL << ARM_FEATURE_NEON) |

+ (1ULL << ARM_FEATURE_AARCH64) |

+ (1ULL << ARM_FEATURE_PMU) |

+ (1ULL << ARM_FEATURE_GENERIC_TIMER);

+

+ /* We set up a small vcpu to extract host registers */

+

+ if (hv_vcpu_create(&fd, &exit, NULL) != HV_SUCCESS) {

+ return false;

+ }

+

+ for (i = 0; i < ARRAY_SIZE(regs); i++) {

+ r |= hv_vcpu_get_sys_reg(fd, regs[i].reg, regs[i].val);

+ }

+ r |= hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr);

+ r |= hv_vcpu_destroy(fd);

+

+ ahcf->isar = host_isar;

+

+ /*

+ * A scratch vCPU returns SCTLR 0, so let's fill our default with the M1

+ * boot SCTLR from https://github.com/AsahiLinux/m1n1/issues/97

+ */

+ ahcf->reset_sctlr = 0x30100180;

+ /*

+ * SPAN is disabled by default when SCTLR.SPAN=1. To improve compatibility,

+ * let's disable it on boot and then allow guest software to turn it on by

+ * setting it to 0.

+ */

+ ahcf->reset_sctlr |= 0x00800000;

+

+ /* Make sure we don't advertise AArch32 support for EL0/EL1 */

+ if ((host_isar.id_aa64pfr0 & 0xff) != 0x11) {

+ return false;

+ }

+

+ return r == HV_SUCCESS;

+}

+

+void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu)

+{

+ if (!arm_host_cpu_features.dtb_compatible) {

+ if (!hvf_enabled() ||

+ !hvf_arm_get_host_cpu_features(&arm_host_cpu_features)) {

+ /*

+ * We can't report this error yet, so flag that we need to

+ * in arm_cpu_realizefn().

+ */

+ cpu->host_cpu_probe_failed = true;

+ return;

+ }

+ }

+

+ cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible;

+ cpu->isar = arm_host_cpu_features.isar;

+ cpu->env.features = arm_host_cpu_features.features;

+ cpu->midr = arm_host_cpu_features.midr;

+ cpu->reset_sctlr = arm_host_cpu_features.reset_sctlr;

+}

+

void hvf_arch_vcpu_destroy(CPUState *cpu)

{

}

2.20.1

Our current codegen for MVE always calls out to helper functions,

because some byte lanes might be predicated. The common case is that

in fact there is no predication active and all lanes should be

updated together, so we can produce better code by detecting that and

using the TCG generic vector infrastructure.

Add a TB flag that is set when we can guarantee that there is no

active MVE predication, and a bool in the DisasContext. Subsequent

patches will use this flag to generate improved code for some

instructions.

In most cases when the predication state changes we simply end the TB

after that instruction. For the code called from vfp_access_check()

that handles lazy state preservation and creating a new FP context,

we can usually avoid having to try to end the TB because luckily the

new value of the flag following the register changes in those

sequences doesn't depend on any runtime decisions. We do have to end

the TB if the guest has enabled lazy FP state preservation but not

automatic state preservation, but this is an odd corner case that is

not going to be common in real-world code.

target/arm/cpu.h | 4 +++-

target/arm/translate.h | 2 ++

target/arm/helper.c | 33 +++++++++++++++++++++++++++++++++

target/arm/translate-m-nocp.c | 8 +++++++-

target/arm/translate-mve.c | 13 ++++++++++++-

target/arm/translate-vfp.c | 33 +++++++++++++++++++++++++++------

target/arm/translate.c | 8 ++++++++

7 files changed, 92 insertions(+), 9 deletions(-)

@@ -XXX,XX +XXX,XX @@ typedef ARMCPU ArchCPU;

* | TBFLAG_AM32 | +-----+----------+

* | | |TBFLAG_M32|

* +-------------+----------------+----------+

- * 31 23 5 4 0

+ * 31 23 6 5 0

*

* Unless otherwise noted, these bits are cached in env->hflags.

*/

@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */

FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */

/* Set if FPCCR.S does not match current security state */

FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */

+/* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */

+FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */

* Bit usage when in AArch64 state

diff --git a/target/arm/translate.h b/target/arm/translate.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.h

+++ b/target/arm/translate.h

bool align_mem;

/* True if PSTATE.IL is set */

bool pstate_il;

+ /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */

+ bool mve_no_pred;

/*

* >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.

* < 0, set by the current instruction.

@@ -XXX,XX +XXX,XX @@ static inline void assert_hflags_rebuild_correctly(CPUARMState *env)

}

+static bool mve_no_pred(CPUARMState *env)

+{

+ /*

+ * Return true if there is definitely no predication of MVE

+ * instructions by VPR or LTPSIZE. (Returning false even if there

+ * isn't any predication is OK; generated code will just be

+ * a little worse.)

+ * If the CPU does not implement MVE then this TB flag is always 0.

+ *

+ * NOTE: if you change this logic, the "recalculate s->mve_no_pred"

+ * logic in gen_update_fp_context() needs to be updated to match.

+ *

+ * We do not include the effect of the ECI bits here -- they are

+ * tracked in other TB flags. This simplifies the logic for

+ * "when did we emit code that changes the MVE_NO_PRED TB flag

+ * and thus need to end the TB?".

+ */

+ if (cpu_isar_feature(aa32_mve, env_archcpu(env))) {

+ return false;

+ }

+ if (env->v7m.vpr) {

+ return false;

+ }

+ if (env->v7m.ltpsize < 4) {

+ return false;

+ }

+ return true;

+}

+

void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,

target_ulong *cs_base, uint32_t *pflags)

{

@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,

if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) {

DP_TBFLAG_M32(flags, LSPACT, 1);

}

+

+ if (mve_no_pred(env)) {

+ DP_TBFLAG_M32(flags, MVE_NO_PRED, 1);

+ }

} else {

/*

* Note that XSCALE_CPAR shares bits with VECSTRIDE.

diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-m-nocp.c

+++ b/target/arm/translate-m-nocp.c

@@ -XXX,XX +XXX,XX @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)

clear_eci_state(s);

- /* End the TB, because we have updated FP control bits */

+ /*

+ * End the TB, because we have updated FP control bits,

+ * and possibly VPR or LTPSIZE.

+ */

s->base.is_jmp = DISAS_UPDATE_EXIT;

return true;

}

@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,

store_cpu_field(control, v7m.control[M_REG_S]);

tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);

gen_helper_vfp_set_fpscr(cpu_env, tmp);

+ s->base.is_jmp = DISAS_UPDATE_NOCHAIN;

tcg_temp_free_i32(tmp);

tcg_temp_free_i32(sfpa);

break;

@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,

}

tmp = loadfn(s, opaque, true);

store_cpu_field(tmp, v7m.vpr);

+ s->base.is_jmp = DISAS_UPDATE_NOCHAIN;

break;

case ARM_VFP_P0:

{

@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,

tcg_gen_deposit_i32(vpr, vpr, tmp,

R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH);

store_cpu_field(vpr, v7m.vpr);

+ s->base.is_jmp = DISAS_UPDATE_NOCHAIN;

tcg_temp_free_i32(tmp);

break;

}

diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-mve.c

+++ b/target/arm/translate-mve.c

@@ -XXX,XX +XXX,XX @@ DO_LOGIC(VORR, gen_helper_mve_vorr)

DO_LOGIC(VORN, gen_helper_mve_vorn)

DO_LOGIC(VEOR, gen_helper_mve_veor)

-DO_LOGIC(VPSEL, gen_helper_mve_vpsel)

+static bool trans_VPSEL(DisasContext *s, arg_2op *a)

+{

+ /* This insn updates predication bits */

+ s->base.is_jmp = DISAS_UPDATE_NOCHAIN;

+ return do_2op(s, a, gen_helper_mve_vpsel);

+}

#define DO_2OP(INSN, FN) \

static bool trans_##INSN(DisasContext *s, arg_2op *a) \

@@ -XXX,XX +XXX,XX @@ static bool trans_VPNOT(DisasContext *s, arg_VPNOT *a)

}

gen_helper_mve_vpnot(cpu_env);

+ /* This insn updates predication bits */

+ s->base.is_jmp = DISAS_UPDATE_NOCHAIN;

mve_update_eci(s);

return true;

}

@@ -XXX,XX +XXX,XX @@ static bool do_vcmp(DisasContext *s, arg_vcmp *a, MVEGenCmpFn *fn)

/* VPT */

gen_vpst(s, a->mask);

}

+ /* This insn updates predication bits */

+ s->base.is_jmp = DISAS_UPDATE_NOCHAIN;

mve_update_eci(s);

return true;

}

@@ -XXX,XX +XXX,XX @@ static bool do_vcmp_scalar(DisasContext *s, arg_vcmp_scalar *a,

/* VPT */

gen_vpst(s, a->mask);

}

+ /* This insn updates predication bits */

+ s->base.is_jmp = DISAS_UPDATE_NOCHAIN;

mve_update_eci(s);

return true;

}

diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-vfp.c

+++ b/target/arm/translate-vfp.c

@@ -XXX,XX +XXX,XX @@ static inline long vfp_f16_offset(unsigned reg, bool top)

* Generate code for M-profile lazy FP state preservation if needed;

* this corresponds to the pseudocode PreserveFPState() function.

*/

-static void gen_preserve_fp_state(DisasContext *s)

+static void gen_preserve_fp_state(DisasContext *s, bool skip_context_update)

{

if (s->v7m_lspact) {

/*

@@ -XXX,XX +XXX,XX @@ static void gen_preserve_fp_state(DisasContext *s)

* any further FP insns in this TB.

*/

s->v7m_lspact = false;

+ /*

+ * The helper might have zeroed VPR, so we do not know the

+ * correct value for the MVE_NO_PRED TB flag any more.

+ * If we're about to create a new fp context then that

+ * will precisely determine the MVE_NO_PRED value (see

+ * gen_update_fp_context()). Otherwise, we must:

+ * - set s->mve_no_pred to false, so this instruction

+ * is generated to use helper functions

+ * - end the TB now, without chaining to the next TB

+ */

+ if (skip_context_update || !s->v7m_new_fp_ctxt_needed) {

+ s->mve_no_pred = false;

+ s->base.is_jmp = DISAS_UPDATE_NOCHAIN;

+ }

@@ -XXX,XX +XXX,XX @@ static void gen_update_fp_context(DisasContext *s)

TCGv_i32 z32 = tcg_const_i32(0);

store_cpu_field(z32, v7m.vpr);

}

/*

- * We don't need to arrange to end the TB, because the only

- * parts of FPSCR which we cache in the TB flags are the VECLEN

- * and VECSTRIDE, and those don't exist for M-profile.

+ * We just updated the FPSCR and VPR. Some of this state is cached

+ * in the MVE_NO_PRED TB flag. We want to avoid having to end the

+ * TB here, which means we need the new value of the MVE_NO_PRED

+ * flag to be exactly known here and the same for all executions.

+ * Luckily FPDSCR.LTPSIZE is always constant 4 and the VPR is

+ * always set to 0, so the new MVE_NO_PRED flag is always 1

+ * if and only if we have MVE.

+ *

+ * (The other FPSCR state cached in TB flags is VECLEN and VECSTRIDE,

+ * but those do not exist for M-profile, so are not relevant here.)

*/

+ s->mve_no_pred = dc_isar_feature(aa32_mve, s);

if (s->v8m_secure) {

bits |= R_V7M_CONTROL_SFPA_MASK;

@@ -XXX,XX +XXX,XX @@ bool vfp_access_check_m(DisasContext *s, bool skip_context_update)

/* Handle M-profile lazy FP state mechanics */

/* Trigger lazy-state preservation if necessary */

- gen_preserve_fp_state(s);

+ gen_preserve_fp_state(s, skip_context_update);

if (!skip_context_update) {

/* Update ownership of FP context and create new FP context if needed */

diff --git a/target/arm/translate.c b/target/arm/translate.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static bool trans_DLS(DisasContext *s, arg_DLS *a)

/* DLSTP: set FPSCR.LTPSIZE */

tmp = tcg_const_i32(a->size);

store_cpu_field(tmp, v7m.ltpsize);

+ s->base.is_jmp = DISAS_UPDATE_NOCHAIN;

return true;

@@ -XXX,XX +XXX,XX @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)

assert(ok);

tmp = tcg_const_i32(a->size);

store_cpu_field(tmp, v7m.ltpsize);

+ /*

+ * LTPSIZE updated, but MVE_NO_PRED will always be the same thing (0)

+ * when we take this upcoming exit from this TB, so gen_jmp_tb() is OK.

+ */

gen_jmp_tb(s, s->base.pc_next, 1);

@@ -XXX,XX +XXX,XX @@ static bool trans_VCTP(DisasContext *s, arg_VCTP *a)

gen_helper_mve_vctp(cpu_env, masklen);

tcg_temp_free_i32(masklen);

tcg_temp_free_i32(rn_shifted);

+ /* This insn updates predication bits */

+ s->base.is_jmp = DISAS_UPDATE_NOCHAIN;

mve_update_eci(s);

return true;

@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)

dc->v7m_new_fp_ctxt_needed =

EX_TBFLAG_M32(tb_flags, NEW_FP_CTXT_NEEDED);

dc->v7m_lspact = EX_TBFLAG_M32(tb_flags, LSPACT);

+ dc->mve_no_pred = EX_TBFLAG_M32(tb_flags, MVE_NO_PRED);

dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL);

dc->sctlr_b = EX_TBFLAG_A32(tb_flags, SCTLR__B);

2.20.1

From: Alexander Graf <agraf@csgraf.de>

We need to handle PSCI calls. Most of the TCG code works for us,

but we can simplify it to only handle aa64 mode and we need to

handle SUSPEND differently.

This patch takes the TCG code as template and duplicates it in HVF.

To tell the guest that we support PSCI 0.2 now, update the check in

arm_cpu_initfn() as well.

Signed-off-by: Alexander Graf <agraf@csgraf.de>

Reviewed-by: Sergio Lopez <slp@redhat.com>

Message-id: 20210916155404.86958-8-agraf@csgraf.de

target/arm/cpu.c | 4 +-

target/arm/hvf/hvf.c | 141 ++++++++++++++++++++++++++++++++++--

target/arm/hvf/trace-events | 1 +

3 files changed, 139 insertions(+), 7 deletions(-)

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)

cpu->psci_version = 1; /* By default assume PSCI v0.1 */

cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;

- if (tcg_enabled()) {

- cpu->psci_version = 2; /* TCG implements PSCI 0.2 */

+ if (tcg_enabled() || hvf_enabled()) {

+ cpu->psci_version = 2; /* TCG and HVF implement PSCI 0.2 */

diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/hvf/hvf.c

+++ b/target/arm/hvf/hvf.c

@@ -XXX,XX +XXX,XX @@

#include "hw/irq.h"

#include "qemu/main-loop.h"

#include "sysemu/cpus.h"

+#include "arm-powerctl.h"

#include "target/arm/cpu.h"

#include "target/arm/internals.h"

#include "trace/trace-target_arm_hvf.h"

@@ -XXX,XX +XXX,XX @@

#define TMR_CTL_IMASK (1 << 1)

#define TMR_CTL_ISTATUS (1 << 2)

+static void hvf_wfi(CPUState *cpu);

+

typedef struct HVFVTimer {

/* Vtimer value during migration and paused state */

uint64_t vtimer_val;

@@ -XXX,XX +XXX,XX @@ static void hvf_raise_exception(CPUState *cpu, uint32_t excp,

arm_cpu_do_interrupt(cpu);

}

+static void hvf_psci_cpu_off(ARMCPU *arm_cpu)

+{

+ int32_t ret = arm_set_cpu_off(arm_cpu->mp_affinity);

+ assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS);

+}

+

+/*

+ * Handle a PSCI call.

+ *

+ * Returns 0 on success

+ * -1 when the PSCI call is unknown,

+ */

+static bool hvf_handle_psci_call(CPUState *cpu)

+{

+ ARMCPU *arm_cpu = ARM_CPU(cpu);

+ CPUARMState *env = &arm_cpu->env;

+ uint64_t param[4] = {

+ env->xregs[0],

+ env->xregs[1],

+ env->xregs[2],

+ env->xregs[3]

+ };

+ uint64_t context_id, mpidr;

+ bool target_aarch64 = true;

+ CPUState *target_cpu_state;

+ ARMCPU *target_cpu;

+ target_ulong entry;

+ int target_el = 1;

+ int32_t ret = 0;

+

+ trace_hvf_psci_call(param[0], param[1], param[2], param[3],

+ arm_cpu->mp_affinity);

+

+ switch (param[0]) {

+ case QEMU_PSCI_0_2_FN_PSCI_VERSION:

+ ret = QEMU_PSCI_0_2_RET_VERSION_0_2;

+ case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:

+ ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */

+ case QEMU_PSCI_0_2_FN_AFFINITY_INFO:

+ case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:

+ mpidr = param[1];

+

+ switch (param[2]) {

+ case 0:

+ target_cpu_state = arm_get_cpu_by_id(mpidr);

+ if (!target_cpu_state) {

+ ret = QEMU_PSCI_RET_INVALID_PARAMS;

+ break;

+ }

+ target_cpu = ARM_CPU(target_cpu_state);

+

+ ret = target_cpu->power_state;

+ break;

+ default:

+ /* Everything above affinity level 0 is always on. */

+ ret = 0;

+ }

+ case QEMU_PSCI_0_2_FN_SYSTEM_RESET:

+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);

+ /*

+ * QEMU reset and shutdown are async requests, but PSCI

+ * mandates that we never return from the reset/shutdown

+ * call, so power the CPU off now so it doesn't execute

+ * anything further.

+ */

+ hvf_psci_cpu_off(arm_cpu);

+ break;

+ case QEMU_PSCI_0_2_FN_SYSTEM_OFF:

+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);

+ hvf_psci_cpu_off(arm_cpu);

+ break;

+ case QEMU_PSCI_0_1_FN_CPU_ON:

+ case QEMU_PSCI_0_2_FN_CPU_ON:

+ case QEMU_PSCI_0_2_FN64_CPU_ON:

+ mpidr = param[1];

+ entry = param[2];

+ context_id = param[3];

+ ret = arm_set_cpu_on(mpidr, entry, context_id,

+ target_el, target_aarch64);

+ break;

+ case QEMU_PSCI_0_1_FN_CPU_OFF:

+ case QEMU_PSCI_0_2_FN_CPU_OFF:

+ hvf_psci_cpu_off(arm_cpu);

+ break;

+ case QEMU_PSCI_0_1_FN_CPU_SUSPEND:

+ case QEMU_PSCI_0_2_FN_CPU_SUSPEND:

+ case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:

+ /* Affinity levels are not supported in QEMU */

+ if (param[1] & 0xfffe0000) {

+ ret = QEMU_PSCI_RET_INVALID_PARAMS;

+ break;

+ }

+ /* Powerdown is not supported, we always go into WFI */

+ env->xregs[0] = 0;

+ hvf_wfi(cpu);

+ break;

+ case QEMU_PSCI_0_1_FN_MIGRATE:

+ case QEMU_PSCI_0_2_FN_MIGRATE:

+ ret = QEMU_PSCI_RET_NOT_SUPPORTED;

+ break;

+ default:

+ return false;

+ }

+

+ env->xregs[0] = ret;

+ return true;

+}

+

static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)

{

ARMCPU *arm_cpu = ARM_CPU(cpu);

@@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *cpu)

break;

case EC_AA64_HVC:

cpu_synchronize_state(cpu);

- trace_hvf_unknown_hvc(env->xregs[0]);

- /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */

- env->xregs[0] = -1;

+ if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_HVC) {

+ if (!hvf_handle_psci_call(cpu)) {

+ trace_hvf_unknown_hvc(env->xregs[0]);

+ /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */

+ env->xregs[0] = -1;

+ }

+ } else {

+ trace_hvf_unknown_hvc(env->xregs[0]);

+ hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());

+ }

break;

case EC_AA64_SMC:

cpu_synchronize_state(cpu);

- trace_hvf_unknown_smc(env->xregs[0]);

- hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());

+ if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_SMC) {

+ advance_pc = true;

+

+ if (!hvf_handle_psci_call(cpu)) {

+ trace_hvf_unknown_smc(env->xregs[0]);

+ /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */

+ env->xregs[0] = -1;

+ }

+ } else {

+ trace_hvf_unknown_smc(env->xregs[0]);

+ hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());

+ }

cpu_synchronize_state(cpu);

diff --git a/target/arm/hvf/trace-events b/target/arm/hvf/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/hvf/trace-events

+++ b/target/arm/hvf/trace-events

@@ -XXX,XX +XXX,XX @@ hvf_sysreg_write(uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, uint32_

hvf_unknown_hvc(uint64_t x0) "unknown HVC! 0x%016"PRIx64

hvf_unknown_smc(uint64_t x0) "unknown SMC! 0x%016"PRIx64

hvf_exit(uint64_t syndrome, uint32_t ec, uint64_t pc) "exit: 0x%"PRIx64" [ec=0x%x pc=0x%"PRIx64"]"

+hvf_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t cpuid) "PSCI Call x0=0x%016"PRIx64" x1=0x%016"PRIx64" x2=0x%016"PRIx64" x3=0x%016"PRIx64" cpu=0x%x"

2.20.1

Move an ifndef CONFIG_USER_ONLY code block up in arm_cpu_reset() so

it can be merged with another earlier one.

target/arm/cpu.c | 22 ++++++++++------------

1 file changed, 10 insertions(+), 12 deletions(-)

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)

env->uncached_cpsr = ARM_CPU_MODE_SVC;

}

env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;

+

+ /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently

+ * executing as AArch32 then check if highvecs are enabled and

+ * adjust the PC accordingly.

+ */

+ if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {

+ env->regs[15] = 0xFFFF0000;

+ }

+

+ env->vfp.xregs[ARM_VFP_FPEXC] = 0;

#endif

if (arm_feature(env, ARM_FEATURE_M)) {

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)

2.20.1

Optimize the MVE 1op-immediate insns (VORR, VBIC, VMOV) to

use TCG vector ops when possible.

target/arm/translate-mve.c | 26 +++++++++++++++++++++-----

1 file changed, 21 insertions(+), 5 deletions(-)

diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c

--- a/target/arm/translate-mve.c

+++ b/target/arm/translate-mve.c

@@ -XXX,XX +XXX,XX @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)

return true;

}

-static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)

+static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn,

+ GVecGen2iFn *vecfn)

{

TCGv_ptr qd;

uint64_t imm;

@@ -XXX,XX +XXX,XX @@ static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)

imm = asimd_imm_const(a->imm, a->cmode, a->op);

- qd = mve_qreg_ptr(a->qd);

- fn(cpu_env, qd, tcg_constant_i64(imm));

- tcg_temp_free_ptr(qd);

+ if (vecfn && mve_no_predication(s)) {

+ vecfn(MO_64, mve_qreg_offset(a->qd), mve_qreg_offset(a->qd),

+ imm, 16, 16);

+ } else {

+ qd = mve_qreg_ptr(a->qd);

+ fn(cpu_env, qd, tcg_constant_i64(imm));

+ tcg_temp_free_ptr(qd);

+ }

mve_update_eci(s);

return true;

}

+static void gen_gvec_vmovi(unsigned vece, uint32_t dofs, uint32_t aofs,

+ int64_t c, uint32_t oprsz, uint32_t maxsz)

+ tcg_gen_gvec_dup_imm(vece, dofs, oprsz, maxsz, c);

static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)

/* Handle decode of cmode/op here between VORR/VBIC/VMOV */

MVEGenOneOpImmFn *fn;

+ GVecGen2iFn *vecfn;

if ((a->cmode & 1) && a->cmode < 12) {

if (a->op) {

@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)

* so the VBIC becomes a logical AND operation.

*/

fn = gen_helper_mve_vandi;

+ vecfn = tcg_gen_gvec_andi;

} else {

fn = gen_helper_mve_vorri;

+ vecfn = tcg_gen_gvec_ori;

}

} else {

/* There is one unallocated cmode/op combination in this space */

@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)

}

/* asimd_imm_const() sorts out VMVNI vs VMOVI for us */