The following changes since commit eae587e8e3694b1aceab23239493fb4c7e1a80f5:

Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-09-13' into staging (2021-09-13 11:00:30 +0100)

https://github.com/legoater/qemu/ tags/pull-aspeed-20210913

for you to fetch changes up to d7add12e20fa8982f5932ff4dca317c5d2dfe7d9:

hw/arm/aspeed: Add Fuji machine type (2021-09-13 15:19:20 +0200)

Aspeed patches :

* MAC enablement fixes (Guenter)

* Watchdog and pca9552 fixes (Andrew)

* GPIO fixes (Joel)

* AST2600A3 SoC and DPS310 models (Joel)

* New Fuji BMC machine (Peter)

Andrew Jeffery (3):

watchdog: aspeed: Sanitize control register values

watchdog: aspeed: Fix sequential control writes

misc/pca9552: Fix LED status register indexing in pca955x_get_led()

Guenter Roeck (2):

hw: arm: aspeed: Enable eth0 interface for aspeed-ast2600-evb

hw: arm: aspeed: Enable mac0/1 instead of mac1/2 for g220a

Joel Stanley (6):

hw: aspeed_gpio: Simplify 1.8V defines

hw: aspeed_gpio: Clarify GPIO controller name

arm/aspeed: rainier: Add i2c eeproms and muxes

aspeed: Emulate the AST2600A3

hw/misc: Add Infineon DPS310 sensor model

arm/aspeed: Add DPS310 to Witherspoon and Rainier

From: Guenter Roeck <linux@roeck-us.net>

According to its dts file in the Linux kernel, we need mac0 and mac1 enabled

instead of mac1 and mac2. Also, g220a is based on aspeed-g5 (ast2500) which

doesn't even have the third interface.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

Message-Id: <20210810035742.550391-1-linux@roeck-us.net>

hw/arm/aspeed.c | 2 +-

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c

--- a/hw/arm/aspeed.c

+++ b/hw/arm/aspeed.c

@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)

amc->fmc_model = "n25q512a";

amc->spi_model = "mx25l25635e";

amc->num_cs = 2;

- amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON;

+ amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;

amc->i2c_init = g220a_bmc_i2c_init;

mc->default_ram_size = 1024 * MiB;

mc->default_cpus = mc->min_cpus = mc->max_cpus =

2.31.1

From: Joel Stanley <joel@jms.id.au>

This contains some hardcoded register values that were obtained from the

hardware after reading the temperature.

It does enough to test the Linux kernel driver. The FIFO mode, IRQs and

operation modes other than the default as used by Linux are not modelled.

Signed-off-by: Joel Stanley <joel@jms.id.au>

Message-Id: <20210616073358.750472-2-joel@jms.id.au>

[ clg: - Fixed sequential reading

- Reworked regs_reset_state array

- Moved model under hw/sensor/ ]

Message-Id: <20210629142336.750058-4-clg@kaod.org>

hw/sensor/dps310.c | 225 ++++++++++++++++++++++++++++++++++++++++++

hw/arm/Kconfig | 1 +

hw/sensor/Kconfig | 4 +

hw/sensor/meson.build | 1 +

4 files changed, 231 insertions(+)

create mode 100644 hw/sensor/dps310.c

diff --git a/hw/sensor/dps310.c b/hw/sensor/dps310.c

+++ b/hw/sensor/dps310.c

+ * Copyright 2017-2021 Joel Stanley <joel@jms.id.au>, IBM Corporation

+ * Infineon DPS310 temperature and humidity sensor

+ * https://www.infineon.com/cms/en/product/sensor/pressure-sensors/pressure-sensors-for-iot/dps310/

+#include "qapi/visitor.h"

+#include "migration/vmstate.h"

+

+#define NUM_REGISTERS 0x33

+

+typedef struct DPS310State {

+ /*< private >*/

+ I2CSlave i2c;

+

+ /*< public >*/

+ uint8_t regs[NUM_REGISTERS];

+

+ uint8_t len;

+ uint8_t pointer;

+

+} DPS310State;

+

+#define TYPE_DPS310 "dps310"

+#define DPS310(obj) OBJECT_CHECK(DPS310State, (obj), TYPE_DPS310)

+

+#define DPS310_PRS_B2 0x00

+#define DPS310_PRS_B1 0x01

+#define DPS310_PRS_B0 0x02

+#define DPS310_TMP_B2 0x03

+#define DPS310_TMP_B1 0x04

+#define DPS310_TMP_B0 0x05

+#define DPS310_PRS_CFG 0x06

+#define DPS310_TMP_CFG 0x07

+#define DPS310_TMP_RATE_BITS (0x70)

+#define DPS310_MEAS_CFG 0x08

+#define DPS310_MEAS_CTRL_BITS (0x07)

+#define DPS310_PRESSURE_EN BIT(0)

+#define DPS310_TEMP_EN BIT(1)

+#define DPS310_BACKGROUND BIT(2)

+#define DPS310_PRS_RDY BIT(4)

+#define DPS310_TMP_RDY BIT(5)

+#define DPS310_SENSOR_RDY BIT(6)

+#define DPS310_COEF_RDY BIT(7)

+#define DPS310_CFG_REG 0x09

+#define DPS310_RESET 0x0c

+#define DPS310_RESET_MAGIC (BIT(0) | BIT(3))

+#define DPS310_COEF_BASE 0x10

+#define DPS310_COEF_LAST 0x21

+#define DPS310_COEF_SRC 0x28

+

+static void dps310_reset(DeviceState *dev)

+{

+ DPS310State *s = DPS310(dev);

+

+ static const uint8_t regs_reset_state[sizeof(s->regs)] = {

+ 0xfe, 0x2f, 0xee, 0x02, 0x69, 0xa6, 0x00, 0x80, 0xc7, 0x00, 0x00, 0x00,

+ 0x00, 0x10, 0x00, 0x00, 0x0e, 0x1e, 0xdd, 0x13, 0xca, 0x5f, 0x21, 0x52,

+ 0xf9, 0xc6, 0x04, 0xd1, 0xdb, 0x47, 0x00, 0x5b, 0xfb, 0x3a, 0x00, 0x00,

+ 0x20, 0x49, 0x4e, 0xa5, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+ 0x60, 0x15, 0x02

+ };

+

+ memcpy(s->regs, regs_reset_state, sizeof(s->regs));

+ s->pointer = 0;

+

+ /* TODO: assert these after some timeout ? */

+ s->regs[DPS310_MEAS_CFG] = DPS310_COEF_RDY | DPS310_SENSOR_RDY

+ | DPS310_TMP_RDY | DPS310_PRS_RDY;

+}

+

+static uint8_t dps310_read(DPS310State *s, uint8_t reg)

+{

+ if (reg >= sizeof(s->regs)) {

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: register 0x%02x out of bounds\n",

+ __func__, s->pointer);

+ return 0xFF;

+ switch (reg) {

+ case DPS310_PRS_B2:

+ case DPS310_PRS_B1:

+ case DPS310_PRS_B0:

+ case DPS310_TMP_B2:

+ case DPS310_TMP_B1:

+ case DPS310_TMP_B0:

+ case DPS310_PRS_CFG:

+ case DPS310_TMP_CFG:

+ case DPS310_MEAS_CFG:

+ case DPS310_CFG_REG:

+ case DPS310_COEF_BASE...DPS310_COEF_LAST:

+ case DPS310_COEF_SRC:

+ case 0x32: /* Undocumented register to indicate workaround not required */

+ return s->regs[reg];

+ default:

+ qemu_log_mask(LOG_UNIMP, "%s: register 0x%02x unimplemented\n",

+ __func__, reg);

+ return 0xFF;

+}

+

+static void dps310_write(DPS310State *s, uint8_t reg, uint8_t data)

+{

+ if (reg >= sizeof(s->regs)) {

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: register %d out of bounds\n",

+ __func__, s->pointer);

+ return;

+ }

+

+ switch (reg) {

+ case DPS310_RESET:

+ if (data == DPS310_RESET_MAGIC) {

+ device_cold_reset(DEVICE(s));

+ }

+ break;

+ case DPS310_PRS_CFG:

+ case DPS310_TMP_CFG:

+ case DPS310_MEAS_CFG:

+ case DPS310_CFG_REG:

+ s->regs[reg] = data;

+ break;

+ default:

+ qemu_log_mask(LOG_UNIMP, "%s: register 0x%02x unimplemented\n",

+ __func__, reg);

+ return;

+ }

+}

+

+static uint8_t dps310_rx(I2CSlave *i2c)

+{

+ DPS310State *s = DPS310(i2c);

+

+ if (s->len == 1) {

+ return dps310_read(s, s->pointer++);

+ } else {

+ return 0xFF;

+ }

+}

+

+static int dps310_tx(I2CSlave *i2c, uint8_t data)

+{

+ DPS310State *s = DPS310(i2c);

+

+ if (s->len == 0) {

+ /*

+ * first byte is the register pointer for a read or write

+ * operation

+ */

+ s->pointer = data;

+ s->len++;

+ } else if (s->len == 1) {

+ dps310_write(s, s->pointer++, data);

+ }

+

+ return 0;

+}

+

+static int dps310_event(I2CSlave *i2c, enum i2c_event event)

+{

+ DPS310State *s = DPS310(i2c);

+

+ switch (event) {

+ case I2C_START_SEND:

+ s->pointer = 0xFF;

+ s->len = 0;

+ break;

+ case I2C_START_RECV:

+ if (s->len != 1) {

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid recv sequence\n",

+ __func__);

+ }

+ break;

+ default:

+ break;

+ }

+

+ return 0;

+}

+

+static const VMStateDescription vmstate_dps310 = {

+ .name = "DPS310",

+ .version_id = 0,

+ .minimum_version_id = 0,

+ .fields = (VMStateField[]) {

+ VMSTATE_UINT8(len, DPS310State),

+ VMSTATE_UINT8_ARRAY(regs, DPS310State, NUM_REGISTERS),

+ VMSTATE_UINT8(pointer, DPS310State),

+ VMSTATE_I2C_SLAVE(i2c, DPS310State),

+ VMSTATE_END_OF_LIST()

+ }

+};

+

+static void dps310_class_init(ObjectClass *klass, void *data)

+{

+ DeviceClass *dc = DEVICE_CLASS(klass);

+ I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);

+

+ k->event = dps310_event;

+ k->recv = dps310_rx;

+ k->send = dps310_tx;

+ dc->reset = dps310_reset;

+ dc->vmsd = &vmstate_dps310;

+}

+

+static const TypeInfo dps310_info = {

+ .name = TYPE_DPS310,

+ .parent = TYPE_I2C_SLAVE,

+ .instance_size = sizeof(DPS310State),

+ .class_init = dps310_class_init,

+};

+

+static void dps310_register_types(void)

+{

+ type_register_static(&dps310_info);

+}

+

+type_init(dps310_register_types)

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig

--- a/hw/arm/Kconfig

+++ b/hw/arm/Kconfig

@@ -XXX,XX +XXX,XX @@ config ASPEED_SOC

select DS1338

select FTGMAC100

select I2C

+ select DPS310

select PCA9552

select SERIAL

select SMBUS_EEPROM

diff --git a/hw/sensor/Kconfig b/hw/sensor/Kconfig

index XXXXXXX..XXXXXXX 100644

--- a/hw/sensor/Kconfig

+++ b/hw/sensor/Kconfig

@@ -XXX,XX +XXX,XX @@ config TMP421

bool

depends on I2C

+config DPS310

+ bool

+ depends on I2C

+

config EMC141X

bool

depends on I2C

diff --git a/hw/sensor/meson.build b/hw/sensor/meson.build

index XXXXXXX..XXXXXXX 100644

--- a/hw/sensor/meson.build

+++ b/hw/sensor/meson.build

@@ -XXX,XX +XXX,XX @@

softmmu_ss.add(when: 'CONFIG_TMP105', if_true: files('tmp105.c'))

softmmu_ss.add(when: 'CONFIG_TMP421', if_true: files('tmp421.c'))

+softmmu_ss.add(when: 'CONFIG_DPS310', if_true: files('dps310.c'))

softmmu_ss.add(when: 'CONFIG_EMC141X', if_true: files('emc141x.c'))

softmmu_ss.add(when: 'CONFIG_ADM1272', if_true: files('adm1272.c'))

softmmu_ss.add(when: 'CONFIG_MAX34451', if_true: files('max34451.c'))

2.31.1

From: Peter Delevoryas <pdel@fb.com>

UART5 is typically used as the default debug UART on the AST2600, but

UART1 is also designed to be a debug UART. All the AST2600 UART's have

semi-configurable clock rates through registers in the System Control

Unit (SCU), but only UART5 works out of the box with zero-initialized

values. The rest of the UART's expect a few of the registers to be

initialized to non-zero values, or else the clock rate calculation will

yield zero or undefined (due to a divide-by-zero).

For reference, the U-Boot clock rate driver here shows the calculation:

https://github.com/facebook/openbmc-uboot/blob/15f7e0dc01d8/drivers/clk/aspeed/clk_ast2600.c#L357

To summarize, UART5 allows selection from 4 rates: 24 MHz, 192 MHz, 24 /

13 MHz, and 192 / 13 MHz. The other UART's allow selecting either the

"low" rate (UARTCLK) or the "high" rate (HUARTCLK). UARTCLK and HUARTCLK

are configurable themselves:

UARTCLK = UXCLK * R / (N * 2)

HUARTCLK = HUXCLK * HR / (HN * 2)

UXCLK and HUXCLK are also configurable, and depend on the APLL and/or

HPLL clock rates, which also derive from complicated calculations. Long

story short, there's lots of multiplication and division from

configurable registers, and most of these registers are zero-initialized

in QEMU, which at best is unexpected and at worst causes this clock rate

driver to hang from divide-by-zero's. This can also be difficult to

diagnose, because it may cause U-Boot to hang before serial console

initialization completes, requiring intervention from gdb.

This change just initializes all of these registers with default values

from the datasheet.

To test this, I used Facebook's AST2600 OpenBMC image for "fuji", with

the following diff applied (because fuji uses UART1 for console output,

not UART5).

@@ -323,8 +323,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)

}

/* UART - attach an 8250 to the IO space as our UART5 */

- serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,

- aspeed_soc_get_irq(s, ASPEED_DEV_UART5),

+ serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART1], 2,

+ aspeed_soc_get_irq(s, ASPEED_DEV_UART1),

38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);

/* I2C */

Without these clock rate registers being initialized, U-Boot hangs in

the clock rate driver from a divide-by-zero, because the UART1 clock

rate register reads return zero, and there's no console output. After

initializing them with default values, fuji boots successfully.

Signed-off-by: Peter Delevoryas <pdel@fb.com>

Reviewed-by: Joel Stanley <joel@jms.id.au>

[ clg: Removed _PARAM suffix ]

Message-Id: <20210906134023.3711031-2-pdel@fb.com>

hw/misc/aspeed_scu.c | 4 ++++

1 file changed, 4 insertions(+)

diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c

--- a/hw/misc/aspeed_scu.c

+++ b/hw/misc/aspeed_scu.c

@@ -XXX,XX +XXX,XX @@

#define AST2600_CLK_SEL3 TO_REG(0x308)

#define AST2600_CLK_SEL4 TO_REG(0x310)

#define AST2600_CLK_SEL5 TO_REG(0x314)

+#define AST2600_UARTCLK TO_REG(0x338)

+#define AST2600_HUARTCLK TO_REG(0x33C)

#define AST2600_HW_STRAP1 TO_REG(0x500)

#define AST2600_HW_STRAP1_CLR TO_REG(0x504)

#define AST2600_HW_STRAP1_PROT TO_REG(0x508)

@@ -XXX,XX +XXX,XX @@ static const uint32_t ast2600_a3_resets[ASPEED_AST2600_SCU_NR_REGS] = {

[AST2600_CLK_SEL3] = 0x00000000,

[AST2600_CLK_SEL4] = 0xF3F40000,

[AST2600_CLK_SEL5] = 0x30000000,

+ [AST2600_UARTCLK] = 0x00014506,

+ [AST2600_HUARTCLK] = 0x000145C0,

[AST2600_CHIP_ID0] = 0x1234ABCD,

[AST2600_CHIP_ID1] = 0x88884444,

2.31.1

From: Joel Stanley <joel@jms.id.au>

Witherspoon uses the DPS310 as a temperature sensor. Rainier uses it as

a temperature and humidity sensor.

Signed-off-by: Joel Stanley <joel@jms.id.au>

hw/arm/aspeed.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c

--- a/hw/arm/aspeed.c

+++ b/hw/arm/aspeed.c

@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)

/* Bus 3: TODO bmp280@77 */

/* Bus 3: TODO max31785@52 */

- /* Bus 3: TODO dps310@76 */

dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));

qdev_prop_set_string(dev, "description", "pca1");

i2c_slave_realize_and_unref(I2C_SLAVE(dev),

@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)

qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,

qdev_get_gpio_in(DEVICE(led), 0));

}

+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);

i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);

i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);

@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)

aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);

aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);

- /* Bus 7: TODO dps310@76 */

/* Bus 7: TODO max31785@52 */

i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x61);

+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);

/* Bus 7: TODO si7021-a20@20 */

i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,

0x48);

2.31.1

From: Peter Delevoryas <pdel@fb.com>

This adds a new machine type "fuji-bmc" based on the following device tree:

https://github.com/torvalds/linux/blob/40cb6373b46/arch/arm/boot/dts/aspeed-bmc-facebook-fuji.dts

Most of the i2c devices are not there, they're added here:

https://github.com/facebook/openbmc/blob/fb2ed12002fb/meta-facebook/meta-fuji/recipes-utils/openbmc-utils/files/setup_i2c.sh

I tested this by building a Fuji image from Facebook's OpenBMC repo,

booting, and ssh'ing from host-to-guest.

Signed-off-by: Peter Delevoryas <pdel@fb.com>

Reviewed-by: Joel Stanley <joel@jms.id.au>

Message-Id: <20210906133124.3674661-1-pdel@fb.com>

hw/arm/aspeed.c | 113 ++++++++++++++++++++++++++++++++++++++++++++++++

1 file changed, 113 insertions(+)

#define RAINIER_BMC_HW_STRAP1 0x00000000

#define RAINIER_BMC_HW_STRAP2 0x00000000

+/* Fuji hardware value */

+#define FUJI_BMC_HW_STRAP1 0x00000000

+#define FUJI_BMC_HW_STRAP2 0x00000000

+

/*

* The max ram region is for firmwares that scan the address space

* with load/store to guess how much RAM the SoC has.

@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)

aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);

+static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,

+ I2CBus **channels)

+{

+ I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);

+ for (int i = 0; i < 8; i++) {

+ channels[i] = pca954x_i2c_get_bus(mux, i);

+ }

+}

+

+#define TYPE_LM75 TYPE_TMP105

+#define TYPE_TMP75 TYPE_TMP105

+#define TYPE_TMP422 "tmp422"

+

+static void fuji_bmc_i2c_init(AspeedMachineState *bmc)

+{

+ AspeedSoCState *soc = &bmc->soc;

+ I2CBus *i2c[144] = {};

+

+ for (int i = 0; i < 16; i++) {

+ i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);

+ }

+ I2CBus *i2c180 = i2c[2];

+ I2CBus *i2c480 = i2c[8];

+ I2CBus *i2c600 = i2c[11];

+

+ get_pca9548_channels(i2c180, 0x70, &i2c[16]);

+ get_pca9548_channels(i2c480, 0x70, &i2c[24]);

+ /* NOTE: The device tree skips [32, 40) in the alias numbering */

+ get_pca9548_channels(i2c600, 0x77, &i2c[40]);

+ get_pca9548_channels(i2c[24], 0x71, &i2c[48]);

+ get_pca9548_channels(i2c[25], 0x72, &i2c[56]);

+ get_pca9548_channels(i2c[26], 0x76, &i2c[64]);

+ get_pca9548_channels(i2c[27], 0x76, &i2c[72]);

+ for (int i = 0; i < 8; i++) {

+ get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);

+ }

+

+ i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);

+ i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);

+

+ aspeed_eeprom_init(i2c[19], 0x52, 64 * KiB);

+ aspeed_eeprom_init(i2c[20], 0x50, 2 * KiB);

+ aspeed_eeprom_init(i2c[22], 0x52, 2 * KiB);

+

+ i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);

+ i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);

+ i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);

+ i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);

+

+ aspeed_eeprom_init(i2c[8], 0x51, 64 * KiB);

+ i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);

+

+ i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);

+ aspeed_eeprom_init(i2c[50], 0x52, 64 * KiB);

+ i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);

+ i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);

+

+ i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);

+ i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);

+

+ aspeed_eeprom_init(i2c[65], 0x53, 64 * KiB);

+ i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);

+ i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);

+ aspeed_eeprom_init(i2c[68], 0x52, 64 * KiB);

+ aspeed_eeprom_init(i2c[69], 0x52, 64 * KiB);

+ aspeed_eeprom_init(i2c[70], 0x52, 64 * KiB);

+ aspeed_eeprom_init(i2c[71], 0x52, 64 * KiB);

+

+ aspeed_eeprom_init(i2c[73], 0x53, 64 * KiB);

+ i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);

+ i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);

+ aspeed_eeprom_init(i2c[76], 0x52, 64 * KiB);

+ aspeed_eeprom_init(i2c[77], 0x52, 64 * KiB);

+ aspeed_eeprom_init(i2c[78], 0x52, 64 * KiB);

+ aspeed_eeprom_init(i2c[79], 0x52, 64 * KiB);

+ aspeed_eeprom_init(i2c[28], 0x50, 2 * KiB);

+

+ for (int i = 0; i < 8; i++) {

+ aspeed_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);

+ i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);

+ i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);

+ i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);

+ }

+}

+

static bool aspeed_get_mmio_exec(Object *obj, Error **errp)

{

return ASPEED_MACHINE(obj)->mmio_exec;

@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)

aspeed_soc_num_cpus(amc->soc_name);

};

+static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)

+{

+ MachineClass *mc = MACHINE_CLASS(oc);

+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);

+

+ mc->desc = "Facebook Fuji BMC (Cortex-A7)";

+ amc->soc_name = "ast2600-a3";

+ amc->hw_strap1 = FUJI_BMC_HW_STRAP1;

+ amc->hw_strap2 = FUJI_BMC_HW_STRAP2;

+ amc->fmc_model = "mx66l1g45g";

+ amc->spi_model = "mx66l1g45g";

+ amc->num_cs = 2;

+ amc->macs_mask = ASPEED_MAC3_ON;

+ amc->i2c_init = fuji_bmc_i2c_init;

+ amc->uart_default = ASPEED_DEV_UART1;

+ mc->default_ram_size = 2 * GiB;

+ mc->default_cpus = mc->min_cpus = mc->max_cpus =

+ aspeed_soc_num_cpus(amc->soc_name);

+};

+

static const TypeInfo aspeed_machine_types[] = {

{

.name = MACHINE_TYPE_NAME("palmetto-bmc"),

@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_machine_types[] = {

.name = MACHINE_TYPE_NAME("rainier-bmc"),

.parent = TYPE_ASPEED_MACHINE,

.class_init = aspeed_machine_rainier_class_init,

+ }, {

+ .name = MACHINE_TYPE_NAME("fuji-bmc"),

+ .parent = TYPE_ASPEED_MACHINE,

+ .class_init = aspeed_machine_fuji_class_init,

}, {

.name = TYPE_ASPEED_MACHINE,

.parent = TYPE_MACHINE,

2.31.1

From: Joel Stanley <joel@jms.id.au>

There are two GPIO controllers in the ast2600; one is 3.3V and the other

is 1.8V.

Signed-off-by: Joel Stanley <joel@jms.id.au>

Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com>

hw/gpio/aspeed_gpio.c | 26 +++++++++++++-------------

1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c

--- a/hw/gpio/aspeed_gpio.c

+++ b/hw/gpio/aspeed_gpio.c

@@ -XXX,XX +XXX,XX @@

#define GPIO_YZAAAB_DIRECTION (0x1E4 >> 2)

#define GPIO_AC_DATA_VALUE (0x1E8 >> 2)

#define GPIO_AC_DIRECTION (0x1EC >> 2)

-#define GPIO_3_6V_MEM_SIZE 0x1F0

-#define GPIO_3_6V_REG_ARRAY_SIZE (GPIO_3_6V_MEM_SIZE >> 2)

+#define GPIO_3_3V_MEM_SIZE 0x1F0

+#define GPIO_3_3V_REG_ARRAY_SIZE (GPIO_3_3V_MEM_SIZE >> 2)

/* AST2600 only - 1.8V gpios */

/*

- * The AST2600 two copies of the GPIO controller: the same 3.6V gpios as the

+ * The AST2600 two copies of the GPIO controller: the same 3.3V gpios as the

* AST2400 (memory offsets 0x0-0x198) and a second controller with 1.8V gpios

* (memory offsets 0x800-0x9D4).

*/

@@ -XXX,XX +XXX,XX @@ static uint32_t update_value_control_source(GPIOSets *regs, uint32_t old_value,

return new_value;

-static const AspeedGPIOReg aspeed_3_6v_gpios[GPIO_3_6V_REG_ARRAY_SIZE] = {

+static const AspeedGPIOReg aspeed_3_3v_gpios[GPIO_3_3V_REG_ARRAY_SIZE] = {

/* Set ABCD */

[GPIO_ABCD_DATA_VALUE] = { 0, gpio_reg_data_value },

[GPIO_ABCD_DIRECTION] = { 0, gpio_reg_direction },

@@ -XXX,XX +XXX,XX @@ static const GPIOSetProperties ast2500_set_props[] = {

[7] = {0x000000ff, 0x000000ff, {"AC"} },

-static GPIOSetProperties ast2600_3_6v_set_props[] = {

+static GPIOSetProperties ast2600_3_3v_set_props[] = {

[0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} },

[1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} },

[2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} },

@@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_ast2400_class_init(ObjectClass *klass, void *data)

agc->nr_gpio_pins = 216;

agc->nr_gpio_sets = 7;

agc->gap = 196;

- agc->reg_table = aspeed_3_6v_gpios;

+ agc->reg_table = aspeed_3_3v_gpios;

}

static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data)

@@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data)

agc->nr_gpio_pins = 228;

agc->nr_gpio_sets = 8;

agc->gap = 220;

- agc->reg_table = aspeed_3_6v_gpios;

+ agc->reg_table = aspeed_3_3v_gpios;

}

-static void aspeed_gpio_ast2600_3_6v_class_init(ObjectClass *klass, void *data)