Hi,

This version contains changes suggested by David and Matheus. No big
design changes were made.


Changes from v2:
- former patch 1: merged into patch 2 (former 3)
- patches 1 and 2 (former 2 and 3):
  * no more intermediate write reg functions that will replaced shortly after
  * do not name specialized write callbacks with '_generic'
  * put the read/write MMCR0 ureg bits in a macro
- patch 3 (former 4): 
  * do not call 'helper_store_mmcr0' in spr_write_MMCR0_ureg
- patch 4 (former 5):
  * use extract64 when extracting MMCR1 events
- patch 5 (former 6):
  * MMCR0_FC is now represented in a DisasContext flag to avoid poking into
  registers before calling the instruction count helper
- patch 6 (former 7):
  * writing SPR_CTRL now forces a new translation block
- patch 8 (former 9):
  * rename device_tree rfebb format and argument
  * crop EBBRR when !msr_is_64bit
  * put the helper inside an "#if defined(TARGET_PPPC64)"
  * use gen_invalid() when CONFIG_USER_ONLY
- v2 link: https://lists.gnu.org/archive/html/qemu-devel/2021-08/msg04062.html


Daniel Henrique Barboza (13):
  target/ppc: add user write access control for PMU SPRs
  target/ppc: PMU basic cycle count for pseries TCG
  target/ppc/power8_pmu.c: enable PMC1-PMC4 events
  target/ppc: PMU: add instruction counting
  target/ppc/power8_pmu.c: add PM_RUN_INST_CMPL (0xFA) event
  target/ppc/power8_pmu.c: add PMC14/PMC56 counter freeze bits
  PPC64/TCG: Implement 'rfebb' instruction
  target/ppc/excp_helper.c: EBB handling adjustments
  target/ppc/power8_pmu.c: enable PMC1 counter negative overflow
  target/ppc/power8_pmu.c: cycles overflow with all PMCs
  target/ppc: PMU: insns counter negative overflow support
  target/ppc/translate: PMU: handle setting of PMCs while running
  target/ppc/power8_pmu.c: handle overflow bits when PMU is running

Gustavo Romero (2):
  target/ppc: add user read functions for MMCR0 and MMCR2
  target/ppc: PMU Event-Based exception support

 hw/ppc/spapr_cpu_core.c                |   6 +
 target/ppc/cpu.h                       |  61 +++-
 target/ppc/cpu_init.c                  |  38 +-
 target/ppc/excp_helper.c               |  92 +++++
 target/ppc/helper.h                    |   4 +
 target/ppc/helper_regs.c               |   6 +
 target/ppc/insn32.decode               |   5 +
 target/ppc/meson.build                 |   1 +
 target/ppc/power8_pmu.c                | 470 +++++++++++++++++++++++++
 target/ppc/power8_pmu.h                |  25 ++
 target/ppc/spr_tcg.h                   |   9 +-
 target/ppc/translate.c                 | 214 ++++++++++-
 target/ppc/translate/branch-impl.c.inc |  33 ++
 13 files changed, 942 insertions(+), 22 deletions(-)
 create mode 100644 target/ppc/power8_pmu.c
 create mode 100644 target/ppc/power8_pmu.h
 create mode 100644 target/ppc/translate/branch-impl.c.inc

-- 
2.31.1