From nobody Fri May 3 01:48:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630701192501242.26418620534025; Fri, 3 Sep 2021 13:33:12 -0700 (PDT) Received: from localhost ([::1]:54862 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMFs7-0005N4-70 for importer@patchew.org; Fri, 03 Sep 2021 16:33:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52554) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMFqb-0001qU-DE; Fri, 03 Sep 2021 16:31:37 -0400 Received: from mail-qt1-x833.google.com ([2607:f8b0:4864:20::833]:40957) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mMFqY-0001St-W1; Fri, 03 Sep 2021 16:31:37 -0400 Received: by mail-qt1-x833.google.com with SMTP id c19so280488qte.7; Fri, 03 Sep 2021 13:31:34 -0700 (PDT) Received: from rekt.COMFAST ([179.247.136.122]) by smtp.gmail.com with ESMTPSA id z6sm285613qtq.78.2021.09.03.13.31.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 13:31:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YjMOqr9vdDapf4R6TWQ7u9CHNM/rukjIK/6Z92r4l20=; b=ejpsE1/s8tGECQ9PqgxVFgozAjNCq8hH/dsSPEAd2R+bwecfHhhVJ8RUGvVMNpADcn 45EuLWL3GmjoLom+NNVDG2QMmV0p5+He76mfYrk8YZZSZ7ZHQXPOO8SIPSPfmmgXwphP Gp2eWTdCEs3DYG8wMych2isT8wAzxHf00q2SexxvBvr5uMGyar+l2wEH5V/QFMWeBQqp T08w2Bb/5+LAMrwsAUseFL1+zyvFNy/1bbyGrZdseD/7xo9oGarJN09K2FRembfEPKS5 M1Cit/HddGeCrU5oUCSqz38xF3RbVPEI0q2UoXe9q7EPENoEmmSGTz4dW9yBSl2Gofnr desA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YjMOqr9vdDapf4R6TWQ7u9CHNM/rukjIK/6Z92r4l20=; b=qxU9poOGFZSsEGHJgmobRIOHVMmAMk/whq+Z/vvjL2viQhynpaRkxQZt+mWI614bIJ JG6caNaIYYB0gXtz2jzh+6skal1VNjrXP6B1aGca11ymGzBIpWLA2T95Xx9SfRjMCwno zj7xQfXWbgiQlBMxWL2xpDtBJEBcLlkuKvqfw9drvcSrUJ4ueP8LAnhYocUKoteNQLNh J3xh9gWxyASah6dMUkeYF8THF0cNcbGWObQ71sxFdC8HcvUX611IoPko2OqIwK+VssJO 4MimvWeer0u4Mhpou71m+wFUjl0PaPW3Lyx/LAorbZhtqsKdkRmrvUS9D2tzPQwD3ofA eRNw== X-Gm-Message-State: AOAM532vbVlGO34oMN4DEFegHfAAE+7chrQWf+TMSxNUV0WCgKqGLAKe eKs3Asr38BfP5g66v/ky3lTZHU+7VEU= X-Google-Smtp-Source: ABdhPJx7ZxF9UwL4TqZba4KRUj815ENYLv6uVBqdO02Drbg8Szisykchh8wT1d92UnS5KXVK7MbuNA== X-Received: by 2002:a05:622a:1347:: with SMTP id w7mr741319qtk.325.1630701093486; Fri, 03 Sep 2021 13:31:33 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v3 01/15] target/ppc: add user read functions for MMCR0 and MMCR2 Date: Fri, 3 Sep 2021 17:31:02 -0300 Message-Id: <20210903203116.80628-2-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210903203116.80628-1-danielhb413@gmail.com> References: <20210903203116.80628-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::833; envelope-from=danielhb413@gmail.com; helo=mail-qt1-x833.google.com X-Spam_score_int: 1 X-Spam_score: 0.1 X-Spam_bar: / X-Spam_report: (0.1 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Gustavo Romero , Gustavo Romero , Daniel Henrique Barboza , richard.henderson@linaro.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630701193507100001 Content-Type: text/plain; charset="utf-8" From: Gustavo Romero We're going to add PMU support for TCG PPC64 chips, based on IBM POWER8+ emulation and following PowerISA v3.1. Let's start by handling the user read of UMMCR0 and UMMCR2. According to PowerISA 3.1 these registers omit some of its bits from userspace. CC: Gustavo Romero Signed-off-by: Gustavo Romero Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 10 ++++++++++ target/ppc/cpu_init.c | 4 ++-- target/ppc/spr_tcg.h | 2 ++ target/ppc/translate.c | 37 +++++++++++++++++++++++++++++++++++++ 4 files changed, 51 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 500205229c..f68bb8d8aa 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -342,6 +342,16 @@ typedef struct ppc_v3_pate_t { #define MSR_RI 1 /* Recoverable interrupt 1 = */ #define MSR_LE 0 /* Little-endian mode 1 hfla= gs */ =20 +/* PMU bits */ +#define MMCR0_FC PPC_BIT(32) /* Freeze Counters */ +#define MMCR0_PMAO PPC_BIT(56) /* Perf Monitor Alert Ocurred */ +#define MMCR0_PMAE PPC_BIT(37) /* Perf Monitor Alert Enable */ +#define MMCR0_EBE PPC_BIT(43) /* Perf Monitor EBB Enable */ +#define MMCR0_FCECE PPC_BIT(38) /* FC on Enabled Cond or Event */ +#define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */ +/* MMCR0 userspace r/w mask */ +#define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE) + /* LPCR bits */ #define LPCR_VPM0 PPC_BIT(0) #define LPCR_VPM1 PPC_BIT(1) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index ad7abc6041..9efc6c2d87 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6867,7 +6867,7 @@ static void register_book3s_pmu_sup_sprs(CPUPPCState = *env) static void register_book3s_pmu_user_sprs(CPUPPCState *env) { spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", - &spr_read_ureg, SPR_NOACCESS, + &spr_read_MMCR0_ureg, SPR_NOACCESS, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", @@ -6975,7 +6975,7 @@ static void register_power8_pmu_sup_sprs(CPUPPCState = *env) static void register_power8_pmu_user_sprs(CPUPPCState *env) { spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", - &spr_read_ureg, SPR_NOACCESS, + &spr_read_MMCR2_ureg, SPR_NOACCESS, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_USIER, "USIER", diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h index 0be5f347d5..30cb6c3fdc 100644 --- a/target/ppc/spr_tcg.h +++ b/target/ppc/spr_tcg.h @@ -32,6 +32,8 @@ void spr_write_lr(DisasContext *ctx, int sprn, int gprn); void spr_read_ctr(DisasContext *ctx, int gprn, int sprn); void spr_write_ctr(DisasContext *ctx, int sprn, int gprn); void spr_read_ureg(DisasContext *ctx, int gprn, int sprn); +void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn); +void spr_read_MMCR2_ureg(DisasContext *ctx, int gprn, int sprn); void spr_read_tbl(DisasContext *ctx, int gprn, int sprn); void spr_read_tbu(DisasContext *ctx, int gprn, int sprn); void spr_read_atbl(DisasContext *ctx, int gprn, int sprn); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 171b216e17..b2ead144d1 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -519,6 +519,43 @@ void spr_read_ureg(DisasContext *ctx, int gprn, int sp= rn) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); } =20 +void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn) +{ + TCGv t0 =3D tcg_temp_new(); + + /* + * Filter out all bits but FC, PMAO, and PMAE, according + * to ISA v3.1, in 10.4.4 Monitor Mode Control Register 0, + * fourth paragraph. + */ + gen_load_spr(t0, SPR_POWER_MMCR0); + tcg_gen_andi_tl(t0, t0, MMCR0_UREG_MASK); + tcg_gen_mov_tl(cpu_gpr[gprn], t0); + + tcg_temp_free(t0); +} + +void spr_read_MMCR2_ureg(DisasContext *ctx, int gprn, int sprn) +{ + TCGv t0 =3D tcg_temp_new(); + + /* + * On read, filter out all bits that are not FCnP0 bits. + * When MMCR0[PMCC] is set to 0b10 or 0b11, providing + * problem state programs read/write access to MMCR2, + * only the FCnP0 bits can be accessed. All other bits are + * not changed when mtspr is executed in problem state, and + * all other bits return 0s when mfspr is executed in problem + * state, according to ISA v3.1, section 10.4.6 Monitor Mode + * Control Register 2, p. 1316, third paragraph. + */ + gen_load_spr(t0, SPR_POWER_MMCR2); + tcg_gen_andi_tl(t0, t0, 0x4020100804020000UL); + tcg_gen_mov_tl(cpu_gpr[gprn], t0); + + tcg_temp_free(t0); +} + #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) { --=20 2.31.1 From nobody Fri May 3 01:48:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630701563965601.5950282079573; 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Fri, 03 Sep 2021 13:31:35 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v3 02/15] target/ppc: add user write access control for PMU SPRs Date: Fri, 3 Sep 2021 17:31:03 -0300 Message-Id: <20210903203116.80628-3-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210903203116.80628-1-danielhb413@gmail.com> References: <20210903203116.80628-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f31; envelope-from=danielhb413@gmail.com; helo=mail-qv1-xf31.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , richard.henderson@linaro.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630701565962100001 Content-Type: text/plain; charset="utf-8" The PMU needs to enable writing of its uregs to userspace, otherwise Perf applications will not able to setup the counters correctly. This patch enables user space writing of all PMU uregs. MMCR0 is a special case because its userspace writing access is controlled by MMCR0_PMCC bits. There are 4 configurations available (0b00, 0b01, 0b10 and 0b11) but for our purposes here we're handling only MMCR0_PMCC =3D 0b00. In this case, if userspace tries to write MMCR0, a hypervisor emulation assistance interrupt occurs. This is being done by adding HFLAGS_PMCCCLEAR to hflags. This flag indicates if MMCR0_PMCC is cleared (0b00), and a new 'pmcc_clear' flag in DisasContext allow us to use it in spr_write_MMCR0_ureg(). Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 1 + target/ppc/cpu_init.c | 18 +++++++------- target/ppc/helper_regs.c | 3 +++ target/ppc/spr_tcg.h | 3 ++- target/ppc/translate.c | 53 +++++++++++++++++++++++++++++++++++++++- 5 files changed, 67 insertions(+), 11 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f68bb8d8aa..8dfbb62022 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -616,6 +616,7 @@ enum { HFLAGS_SE =3D 10, /* MSR_SE -- from elsewhere on embedded ppc */ HFLAGS_FP =3D 13, /* MSR_FP */ HFLAGS_PR =3D 14, /* MSR_PR */ + HFLAGS_PMCCCLEAR =3D 15, /* PMU MMCR0 PMCC equal to 0b00 */ HFLAGS_VSX =3D 23, /* MSR_VSX if cpu has VSX */ HFLAGS_VR =3D 25, /* MSR_VR if cpu has VRE */ =20 diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 9efc6c2d87..bb5ea04c61 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6867,7 +6867,7 @@ static void register_book3s_pmu_sup_sprs(CPUPPCState = *env) static void register_book3s_pmu_user_sprs(CPUPPCState *env) { spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", - &spr_read_MMCR0_ureg, SPR_NOACCESS, + &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", @@ -6875,31 +6875,31 @@ static void register_book3s_pmu_user_sprs(CPUPPCSta= te *env) &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", - &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, &spr_write_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UPMC1, "UPMC1", - &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, &spr_write_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UPMC2, "UPMC2", - &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, &spr_write_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UPMC3, "UPMC3", - &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, &spr_write_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UPMC4, "UPMC4", - &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, &spr_write_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UPMC5, "UPMC5", - &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, &spr_write_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UPMC6, "UPMC6", - &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, &spr_write_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_USIAR, "USIAR", @@ -6975,7 +6975,7 @@ static void register_power8_pmu_sup_sprs(CPUPPCState = *env) static void register_power8_pmu_user_sprs(CPUPPCState *env) { spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", - &spr_read_MMCR2_ureg, SPR_NOACCESS, + &spr_read_MMCR2_ureg, &spr_write_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_USIER, "USIER", diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 405450d863..4c1d9575ac 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -106,6 +106,9 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *= env) if (env->spr[SPR_LPCR] & LPCR_GTSE) { hflags |=3D 1 << HFLAGS_GTSE; } + if (((env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC) >> 18) =3D=3D 0) { + hflags |=3D 1 << HFLAGS_PMCCCLEAR; + } =20 #ifndef CONFIG_USER_ONLY if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h index 30cb6c3fdc..094466a2b2 100644 --- a/target/ppc/spr_tcg.h +++ b/target/ppc/spr_tcg.h @@ -42,6 +42,8 @@ void spr_read_601_rtcl(DisasContext *ctx, int gprn, int s= prn); void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn); void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn); void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn); +void spr_write_ureg(DisasContext *ctx, int sprn, int gprn); +void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn); =20 #ifndef CONFIG_USER_ONLY void spr_write_generic32(DisasContext *ctx, int sprn, int gprn); @@ -96,7 +98,6 @@ void spr_read_mas73(DisasContext *ctx, int gprn, int sprn= ); #ifdef TARGET_PPC64 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn); void spr_write_cfar(DisasContext *ctx, int sprn, int gprn); -void spr_write_ureg(DisasContext *ctx, int sprn, int gprn); void spr_read_purr(DisasContext *ctx, int gprn, int sprn); void spr_write_purr(DisasContext *ctx, int sprn, int gprn); void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index b2ead144d1..0babde3131 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -175,6 +175,7 @@ struct DisasContext { bool spe_enabled; bool tm_enabled; bool gtse; + bool pmcc_clear; ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ int singlestep_enabled; uint32_t flags; @@ -561,7 +562,56 @@ void spr_write_ureg(DisasContext *ctx, int sprn, int g= prn) { gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); } -#endif + +void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn) +{ + TCGv t0, t1; + + /* + * For group A PMU sprs, if PMCC =3D 0b00, PowerISA v3.1 + * dictates that: + * + * "If an attempt is made to write to an SPR in group A in + * problem state, a Hypervisor Emulation Assistance + * interrupt will occur." + * + * MMCR0 is a Group A SPR and can't be written by userspace + * if PMCC =3D 0b00. + */ + if (ctx->pmcc_clear) { + gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); + return; + } + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + + /* + * Filter out all bits but FC, PMAO, and PMAE, according + * to ISA v3.1, in 10.4.4 Monitor Mode Control Register 0, + * fourth paragraph. + */ + tcg_gen_andi_tl(t0, cpu_gpr[gprn], MMCR0_UREG_MASK); + gen_load_spr(t1, SPR_POWER_MMCR0); + tcg_gen_andi_tl(t1, t1, ~(MMCR0_UREG_MASK)); + /* Keep all other bits intact */ + tcg_gen_or_tl(t1, t1, t0); + gen_store_spr(SPR_POWER_MMCR0, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); +} +#else +void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) +{ + spr_noaccess(ctx, gprn, sprn); +} + +void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn) +{ + spr_noaccess(ctx, gprn, sprn); +} +#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ =20 /* SPR common to all non-embedded PowerPC */ /* DECR */ @@ -8576,6 +8626,7 @@ static void ppc_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->vsx_enabled =3D (hflags >> HFLAGS_VSX) & 1; ctx->tm_enabled =3D (hflags >> HFLAGS_TM) & 1; ctx->gtse =3D (hflags >> HFLAGS_GTSE) & 1; + ctx->pmcc_clear =3D (hflags >> HFLAGS_PMCCCLEAR) & 1; =20 ctx->singlestep_enabled =3D 0; if ((hflags >> HFLAGS_SE) & 1) { --=20 2.31.1 From nobody Fri May 3 01:48:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2f; envelope-from=danielhb413@gmail.com; helo=mail-qv1-xf2f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , richard.henderson@linaro.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630701594027100003 Content-Type: text/plain; charset="utf-8" This patch adds the barebones of the PMU logic by enabling cycle counting, done via the performance monitor counter 6. The overall logic goes as follows: - a helper is added to control the PMU state on each MMCR0 write. This allows for the PMU to start/stop as the frozen counter bit (MMCR0_FC) is cleared or set; - MMCR0 reg initial value is set to 0x80000000 (MMCR0_FC set) to avoid having to spin the PMU right at system init; - the intended usage is to freeze the counters by setting MMCR0_FC, do any additional setting of events to be counted via MMCR1 (not implemented yet) and enable the PMU by zeroing MMCR0_FC. Software must freeze counters to read the results - on the fly reading of the PMCs will return the starting value of each one. Since there will be more PMU exclusive code to be added next, put the PMU logic in its own helper to keep all in the same place. The name of the new helper file, power8_pmu.c, is an indicative that the PMU logic has been tested with the IBM POWER chip family, POWER8 being the oldest version tested. This doesn't mean that this PMU logic will break with any other PPC64 chip that implements Book3s, but since we can't assert that this PMU will work with all available Book3s emulated processors we're choosing to be explicit. Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 6 ++++ target/ppc/cpu_init.c | 6 ++-- target/ppc/helper.h | 1 + target/ppc/meson.build | 1 + target/ppc/power8_pmu.c | 74 +++++++++++++++++++++++++++++++++++++++++ target/ppc/spr_tcg.h | 1 + target/ppc/translate.c | 23 ++++++++++++- 7 files changed, 108 insertions(+), 4 deletions(-) create mode 100644 target/ppc/power8_pmu.c diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 8dfbb62022..a9b31736af 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1178,6 +1178,12 @@ struct CPUPPCState { uint32_t tm_vscr; uint64_t tm_dscr; uint64_t tm_tar; + + /* + * PMU base time value used by the PMU to calculate + * running cycles. + */ + uint64_t pmu_base_time; }; =20 #define SET_FIT_PERIOD(a_, b_, c_, d_) \ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index bb5ea04c61..07c79745ba 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6820,8 +6820,8 @@ static void register_book3s_pmu_sup_sprs(CPUPPCState = *env) { spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_MMCR0, 0x00000000); + &spr_read_generic, &spr_write_MMCR0, + KVM_REG_PPC_MMCR0, 0x80000000); spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, @@ -6869,7 +6869,7 @@ static void register_book3s_pmu_user_sprs(CPUPPCState= *env) spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, &spr_read_ureg, &spr_write_ureg, - 0x00000000); + 0x80000000); spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", &spr_read_ureg, SPR_NOACCESS, &spr_read_ureg, &spr_write_ureg, diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 4076aa281e..5122632784 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -20,6 +20,7 @@ DEF_HELPER_1(rfscv, void, env) DEF_HELPER_1(hrfid, void, env) DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) +DEF_HELPER_2(store_mmcr0, void, env, tl) #endif DEF_HELPER_1(check_tlb_flush_local, void, env) DEF_HELPER_1(check_tlb_flush_global, void, env) diff --git a/target/ppc/meson.build b/target/ppc/meson.build index b85f295703..278ce07da9 100644 --- a/target/ppc/meson.build +++ b/target/ppc/meson.build @@ -14,6 +14,7 @@ ppc_ss.add(when: 'CONFIG_TCG', if_true: files( 'int_helper.c', 'mem_helper.c', 'misc_helper.c', + 'power8_pmu.c', 'timebase_helper.c', 'translate.c', )) diff --git a/target/ppc/power8_pmu.c b/target/ppc/power8_pmu.c new file mode 100644 index 0000000000..47de38a99e --- /dev/null +++ b/target/ppc/power8_pmu.c @@ -0,0 +1,74 @@ +/* + * PMU emulation helpers for TCG IBM POWER chips + * + * Copyright IBM Corp. 2021 + * + * Authors: + * Daniel Henrique Barboza + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" + +#include "cpu.h" +#include "helper_regs.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "qemu/error-report.h" +#include "qemu/main-loop.h" + +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) + +static void update_PMC_PM_CYC(CPUPPCState *env, int sprn, + uint64_t time_delta) +{ + /* + * The pseries and pvn clock runs at 1Ghz, meaning that + * 1 nanosec equals 1 cycle. + */ + env->spr[sprn] +=3D time_delta; +} + +static void update_cycles_PMCs(CPUPPCState *env) +{ + uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + uint64_t time_delta =3D now - env->pmu_base_time; + + update_PMC_PM_CYC(env, SPR_POWER_PMC6, time_delta); +} + +void helper_store_mmcr0(CPUPPCState *env, target_ulong value) +{ + target_ulong curr_value =3D env->spr[SPR_POWER_MMCR0]; + bool curr_FC =3D curr_value & MMCR0_FC; + bool new_FC =3D value & MMCR0_FC; + + env->spr[SPR_POWER_MMCR0] =3D value; + + /* MMCR0 writes can change HFLAGS_PMCCCLEAR */ + if ((curr_value & MMCR0_PMCC) !=3D (value & MMCR0_PMCC)) { + hreg_compute_hflags(env); + } + + /* + * In an frozen count (FC) bit change: + * + * - if PMCs were running (curr_FC =3D false) and we're freezing + * them (new_FC =3D true), save the PMCs values in the registers. + * + * - if PMCs were frozen (curr_FC =3D true) and we're activating + * them (new_FC =3D false), set the new base_time for future cycle + * calculations. + */ + if (curr_FC !=3D new_FC) { + if (!curr_FC) { + update_cycles_PMCs(env); + } else { + env->pmu_base_time =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + } + } +} + +#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h index 094466a2b2..51fbc081de 100644 --- a/target/ppc/spr_tcg.h +++ b/target/ppc/spr_tcg.h @@ -25,6 +25,7 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn); void spr_read_generic(DisasContext *ctx, int gprn, int sprn); void spr_write_generic(DisasContext *ctx, int sprn, int gprn); +void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn); void spr_read_xer(DisasContext *ctx, int gprn, int sprn); void spr_write_xer(DisasContext *ctx, int sprn, int gprn); void spr_read_lr(DisasContext *ctx, int gprn, int sprn); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 0babde3131..c3e2e3d329 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -401,6 +401,24 @@ void spr_write_generic(DisasContext *ctx, int sprn, in= t gprn) spr_store_dump_spr(sprn); } =20 +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn) +{ + /* + * helper_store_mmcr0 will make clock based operations that + * will cause 'bad icount read' errors if we do not execute + * gen_icount_io_start() beforehand. + */ + gen_icount_io_start(ctx); + gen_helper_store_mmcr0(cpu_env, cpu_gpr[gprn]); +} +#else +void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn) +{ + spr_write_generic(ctx, sprn, gprn); +} +#endif + #if !defined(CONFIG_USER_ONLY) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) { @@ -596,7 +614,10 @@ void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn,= int gprn) tcg_gen_andi_tl(t1, t1, ~(MMCR0_UREG_MASK)); /* Keep all other bits intact */ tcg_gen_or_tl(t1, t1, t0); - gen_store_spr(SPR_POWER_MMCR0, t1); + + /* Overwrite cpu_gpr[gprn] and use spr_write_MMCR0() */ + tcg_gen_mov_tl(cpu_gpr[gprn], t1); + spr_write_MMCR0(ctx, sprn + 0x10, gprn); =20 tcg_temp_free(t0); tcg_temp_free(t1); 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charset="utf-8" This patch enable all PMCs but PMC5 to count cycles. To do that we need to implement MMCR1 bits where the event are stored, retrieve them, see if the PMC was configured with a PM_CYC event, and calculate cycles if that's the case. PowerISA v3.1 defines the following conditions to count cycles: - PMC1 set with the event 0xF0; - PMC6, which always count cycles However, the PowerISA also defines a range of 'implementation dependent' events that the chip can use in the 0x01-0xBF range. Turns out that IBM POWER chips implements some non-ISA events, and the Linux kernel makes uses of them. For instance, 0x1E is an implementation specific event that counts cycles in PMCs 1-4 that the kernel uses. Let's also support 0x1E to count cycles to allow for existing kernels to behave properly with the PMU. Signed-off-by: Daniel Henrique Barboza Reviewed-by: David Gibson --- target/ppc/cpu.h | 11 +++++++++ target/ppc/power8_pmu.c | 52 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index a9b31736af..74698a3600 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -352,6 +352,17 @@ typedef struct ppc_v3_pate_t { /* MMCR0 userspace r/w mask */ #define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE) =20 +#define MMCR1_EVT_SIZE 8 +/* extract64() does a right shift before extracting */ +#define MMCR1_PMC1SEL_START 32 +#define MMCR1_PMC1EVT_EXTR (64 - MMCR1_PMC1SEL_START - MMCR1_EVT_SIZE) +#define MMCR1_PMC2SEL_START 40 +#define MMCR1_PMC2EVT_EXTR (64 - MMCR1_PMC2SEL_START - MMCR1_EVT_SIZE) +#define MMCR1_PMC3SEL_START 48 +#define MMCR1_PMC3EVT_EXTR (64 - MMCR1_PMC3SEL_START - MMCR1_EVT_SIZE) +#define MMCR1_PMC4SEL_START 56 +#define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE) + /* LPCR bits */ #define LPCR_VPM0 PPC_BIT(0) #define LPCR_VPM1 PPC_BIT(1) diff --git a/target/ppc/power8_pmu.c b/target/ppc/power8_pmu.c index 47de38a99e..3f7b305f4f 100644 --- a/target/ppc/power8_pmu.c +++ b/target/ppc/power8_pmu.c @@ -31,10 +31,62 @@ static void update_PMC_PM_CYC(CPUPPCState *env, int spr= n, env->spr[sprn] +=3D time_delta; } =20 +static void update_programmable_PMC_reg(CPUPPCState *env, int sprn, + uint64_t time_delta) +{ + uint8_t event, evt_extr; + + switch (sprn) { + case SPR_POWER_PMC1: + evt_extr =3D MMCR1_PMC1EVT_EXTR; + break; + case SPR_POWER_PMC2: + evt_extr =3D MMCR1_PMC2EVT_EXTR; + break; + case SPR_POWER_PMC3: + evt_extr =3D MMCR1_PMC3EVT_EXTR; + break; + case SPR_POWER_PMC4: + evt_extr =3D MMCR1_PMC4EVT_EXTR; + break; + default: + return; + } + + event =3D extract64(env->spr[SPR_POWER_MMCR1], evt_extr, MMCR1_EVT_SIZ= E); + + /* + * MMCR0_PMC1SEL =3D 0xF0 is the architected PowerISA v3.1 event + * that counts cycles using PMC1. + * + * IBM POWER chips also has support for an implementation dependent + * event, 0x1E, that enables cycle counting on PMCs 1-4. The + * Linux kernel makes extensive use of 0x1E, so let's also support + * it. + */ + switch (event) { + case 0xF0: + if (sprn =3D=3D SPR_POWER_PMC1) { + update_PMC_PM_CYC(env, sprn, time_delta); + } + break; + case 0x1E: + update_PMC_PM_CYC(env, sprn, time_delta); + break; + default: + return; + } +} + static void update_cycles_PMCs(CPUPPCState *env) { uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); uint64_t time_delta =3D now - env->pmu_base_time; + int sprn; + + for (sprn =3D SPR_POWER_PMC1; sprn < SPR_POWER_PMC5; sprn++) { + update_programmable_PMC_reg(env, sprn, time_delta); + } =20 update_PMC_PM_CYC(env, SPR_POWER_PMC6, time_delta); } --=20 2.31.1 From nobody Fri May 3 01:48:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630701889738289.64691817460107; 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Fri, 03 Sep 2021 13:31:42 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v3 05/15] target/ppc: PMU: add instruction counting Date: Fri, 3 Sep 2021 17:31:06 -0300 Message-Id: <20210903203116.80628-6-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210903203116.80628-1-danielhb413@gmail.com> References: <20210903203116.80628-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::736; envelope-from=danielhb413@gmail.com; helo=mail-qk1-x736.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , richard.henderson@linaro.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630701890351100001 Content-Type: text/plain; charset="utf-8" The PMU is already counting cycles by calculating time elapsed in nanoseconds. Counting instructions is a different matter and requires another approach. This patch adds the capability of counting completed instructions (Perf event PM_INST_CMPL) by counting the amount of instructions translated in each translation block right before exiting it. A new pmu_count_insns() helper in translation.c was added to do that. After verifying that the PMU is running (MMCR0_FC bit not set), call helper_insns_inc(). This new helper from power8_pmu.c will add the instructions to the relevant counters. It'll also be responsible for triggering counter negative overflows later on. Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 1 + target/ppc/helper.h | 1 + target/ppc/helper_regs.c | 3 ++ target/ppc/power8_pmu.c | 70 ++++++++++++++++++++++++++++++++++++---- target/ppc/translate.c | 46 ++++++++++++++++++++++++++ 5 files changed, 114 insertions(+), 7 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 74698a3600..4d4886ac74 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -628,6 +628,7 @@ enum { HFLAGS_FP =3D 13, /* MSR_FP */ HFLAGS_PR =3D 14, /* MSR_PR */ HFLAGS_PMCCCLEAR =3D 15, /* PMU MMCR0 PMCC equal to 0b00 */ + HFLAGS_MMCR0FC =3D 16, /* MMCR0 FC bit */ HFLAGS_VSX =3D 23, /* MSR_VSX if cpu has VSX */ HFLAGS_VR =3D 25, /* MSR_VR if cpu has VRE */ =20 diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 5122632784..47dbbe6da1 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -21,6 +21,7 @@ DEF_HELPER_1(hrfid, void, env) DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) DEF_HELPER_2(store_mmcr0, void, env, tl) +DEF_HELPER_2(insns_inc, void, env, i32) #endif DEF_HELPER_1(check_tlb_flush_local, void, env) DEF_HELPER_1(check_tlb_flush_global, void, env) diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 4c1d9575ac..27d139edd8 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -109,6 +109,9 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *= env) if (((env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC) >> 18) =3D=3D 0) { hflags |=3D 1 << HFLAGS_PMCCCLEAR; } + if (env->spr[SPR_POWER_MMCR0] & MMCR0_FC) { + hflags |=3D 1 << HFLAGS_MMCR0FC; + } =20 #ifndef CONFIG_USER_ONLY if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { diff --git a/target/ppc/power8_pmu.c b/target/ppc/power8_pmu.c index 3f7b305f4f..9769c0ff35 100644 --- a/target/ppc/power8_pmu.c +++ b/target/ppc/power8_pmu.c @@ -31,10 +31,13 @@ static void update_PMC_PM_CYC(CPUPPCState *env, int spr= n, env->spr[sprn] +=3D time_delta; } =20 -static void update_programmable_PMC_reg(CPUPPCState *env, int sprn, - uint64_t time_delta) +static uint8_t get_PMC_event(CPUPPCState *env, int sprn) { - uint8_t event, evt_extr; + uint8_t evt_extr =3D 0; + + if (env->spr[SPR_POWER_MMCR1] =3D=3D 0) { + return 0; + } =20 switch (sprn) { case SPR_POWER_PMC1: @@ -50,10 +53,16 @@ static void update_programmable_PMC_reg(CPUPPCState *en= v, int sprn, evt_extr =3D MMCR1_PMC4EVT_EXTR; break; default: - return; + return 0; } =20 - event =3D extract64(env->spr[SPR_POWER_MMCR1], evt_extr, MMCR1_EVT_SIZ= E); + return extract64(env->spr[SPR_POWER_MMCR1], evt_extr, MMCR1_EVT_SIZE); +} + +static void update_programmable_PMC_reg(CPUPPCState *env, int sprn, + uint64_t time_delta) +{ + uint8_t event =3D get_PMC_event(env, sprn); =20 /* * MMCR0_PMC1SEL =3D 0xF0 is the architected PowerISA v3.1 event @@ -99,8 +108,9 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong v= alue) =20 env->spr[SPR_POWER_MMCR0] =3D value; =20 - /* MMCR0 writes can change HFLAGS_PMCCCLEAR */ - if ((curr_value & MMCR0_PMCC) !=3D (value & MMCR0_PMCC)) { + /* MMCR0 writes can change HFLAGS_PMCCCLEAR and HFLAGS_MMCR0FC */ + if (((curr_value & MMCR0_PMCC) !=3D (value & MMCR0_PMCC)) || + (curr_FC !=3D new_FC)) { hreg_compute_hflags(env); } =20 @@ -123,4 +133,50 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong= value) } } =20 +static bool pmc_counting_insns(CPUPPCState *env, int sprn) +{ + bool ret =3D false; + uint8_t event; + + if (sprn =3D=3D SPR_POWER_PMC5) { + return true; + } + + event =3D get_PMC_event(env, sprn); + + /* + * Event 0x2 is an implementation-dependent event that IBM + * POWER chips implement (at least since POWER8) that is + * equivalent to PM_INST_CMPL. Let's support this event on + * all programmable PMCs. + * + * Event 0xFE is the PowerISA v3.1 architected event to + * sample PM_INST_CMPL using PMC1. + */ + switch (sprn) { + case SPR_POWER_PMC1: + return event =3D=3D 0x2 || event =3D=3D 0xFE; + case SPR_POWER_PMC2: + case SPR_POWER_PMC3: + case SPR_POWER_PMC4: + return event =3D=3D 0x2; + default: + break; + } + + return ret; +} + +/* This helper assumes that the PMC is running. */ +void helper_insns_inc(CPUPPCState *env, uint32_t num_insns) +{ + int sprn; + + for (sprn =3D SPR_POWER_PMC1; sprn <=3D SPR_POWER_PMC5; sprn++) { + if (pmc_counting_insns(env, sprn)) { + env->spr[sprn] +=3D num_insns; + } + } +} + #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c3e2e3d329..b7235a2be0 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -176,6 +176,7 @@ struct DisasContext { bool tm_enabled; bool gtse; bool pmcc_clear; + bool pmu_frozen; ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ int singlestep_enabled; uint32_t flags; @@ -411,6 +412,12 @@ void spr_write_MMCR0(DisasContext *ctx, int sprn, int = gprn) */ gen_icount_io_start(ctx); gen_helper_store_mmcr0(cpu_env, cpu_gpr[gprn]); + + /* + * End the translation block because MMCR0 writes can change + * ctx->pmu_frozen. + */ + ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; } #else void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn) @@ -4407,6 +4414,22 @@ static inline void gen_update_cfar(DisasContext *ctx= , target_ulong nip) #endif } =20 +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +static void pmu_count_insns(DisasContext *ctx) +{ + /* Do not bother calling the helper if the PMU is frozen */ + if (ctx->pmu_frozen) { + return; + } + + gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); +} +#else +static void pmu_count_insns(DisasContext *ctx) +{ + return; +} +#endif static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) { return translator_use_goto_tb(&ctx->base, dest); @@ -4421,9 +4444,17 @@ static void gen_lookup_and_goto_ptr(DisasContext *ct= x) } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_= dbgex(ctx))); } else { + pmu_count_insns(ctx); tcg_gen_exit_tb(NULL, 0); } } else { + /* + * tcg_gen_lookup_and_goto_ptr will exit the TB if + * CF_NO_GOTO_PTR is set. Count insns now. + */ + if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { + pmu_count_insns(ctx); + } tcg_gen_lookup_and_goto_ptr(); } } @@ -4435,6 +4466,8 @@ static void gen_goto_tb(DisasContext *ctx, int n, tar= get_ulong dest) dest =3D (uint32_t) dest; } if (use_goto_tb(ctx, dest)) { + pmu_count_insns(ctx); + tcg_gen_goto_tb(n); tcg_gen_movi_tl(cpu_nip, dest & ~3); tcg_gen_exit_tb(ctx->base.tb, n); @@ -8648,6 +8681,7 @@ static void ppc_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->tm_enabled =3D (hflags >> HFLAGS_TM) & 1; ctx->gtse =3D (hflags >> HFLAGS_GTSE) & 1; ctx->pmcc_clear =3D (hflags >> HFLAGS_PMCCCLEAR) & 1; + ctx->pmu_frozen =3D (hflags >> HFLAGS_MMCR0FC) & 1; =20 ctx->singlestep_enabled =3D 0; if ((hflags >> HFLAGS_SE) & 1) { @@ -8767,6 +8801,8 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cs) switch (is_jmp) { case DISAS_TOO_MANY: if (use_goto_tb(ctx, nip)) { + pmu_count_insns(ctx); + tcg_gen_goto_tb(0); gen_update_nip(ctx, nip); tcg_gen_exit_tb(ctx->base.tb, 0); @@ -8777,6 +8813,14 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase,= CPUState *cs) gen_update_nip(ctx, nip); /* fall through */ case DISAS_CHAIN: + /* + * tcg_gen_lookup_and_goto_ptr will exit the TB if + * CF_NO_GOTO_PTR is set. Count insns now. + */ + if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { + pmu_count_insns(ctx); + } + tcg_gen_lookup_and_goto_ptr(); break; =20 @@ -8784,6 +8828,8 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cs) gen_update_nip(ctx, nip); /* fall through */ case DISAS_EXIT: + pmu_count_insns(ctx); + tcg_gen_exit_tb(NULL, 0); break; =20 --=20 2.31.1 From nobody Fri May 3 01:48:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630702201788913.6421150650564; Fri, 3 Sep 2021 13:50:01 -0700 (PDT) Received: from localhost ([::1]:44276 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMG8O-0004sG-Q4 for importer@patchew.org; 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Fri, 03 Sep 2021 13:31:44 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v3 06/15] target/ppc/power8_pmu.c: add PM_RUN_INST_CMPL (0xFA) event Date: Fri, 3 Sep 2021 17:31:07 -0300 Message-Id: <20210903203116.80628-7-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210903203116.80628-1-danielhb413@gmail.com> References: <20210903203116.80628-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::731; envelope-from=danielhb413@gmail.com; helo=mail-qk1-x731.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , richard.henderson@linaro.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630702203142100001 Content-Type: text/plain; charset="utf-8" PM_RUN_INST_CMPL, instructions completed with the run latch set, is the architected PowerISA v3.1 event defined with PMC4SEL =3D 0xFA. Implement it by checking for the CTRL RUN bit before incrementing the counter. To make this work properly we also need to force a new translation block each time SPR_CTRL is written. Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 3 +++ target/ppc/cpu_init.c | 2 +- target/ppc/power8_pmu.c | 27 ++++++++++++++++++++------- target/ppc/spr_tcg.h | 1 + target/ppc/translate.c | 12 ++++++++++++ 5 files changed, 37 insertions(+), 8 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 4d4886ac74..76b462c3c8 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -363,6 +363,9 @@ typedef struct ppc_v3_pate_t { #define MMCR1_PMC4SEL_START 56 #define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE) =20 +/* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */ +#define CTRL_RUN PPC_BIT(63) + /* LPCR bits */ #define LPCR_VPM0 PPC_BIT(0) #define LPCR_VPM1 PPC_BIT(1) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 07c79745ba..0013cba5ff 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6748,7 +6748,7 @@ static void register_book3s_ctrl_sprs(CPUPPCState *en= v) { spr_register(env, SPR_CTRL, "SPR_CTRL", SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, &spr_write_generic, + SPR_NOACCESS, &spr_write_CTRL, 0x00000000); spr_register(env, SPR_UCTRL, "SPR_UCTRL", &spr_read_ureg, SPR_NOACCESS, diff --git a/target/ppc/power8_pmu.c b/target/ppc/power8_pmu.c index 9769c0ff35..f584480fde 100644 --- a/target/ppc/power8_pmu.c +++ b/target/ppc/power8_pmu.c @@ -133,17 +133,15 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulon= g value) } } =20 -static bool pmc_counting_insns(CPUPPCState *env, int sprn) +static bool pmc_counting_insns(CPUPPCState *env, int sprn, + uint8_t event) { bool ret =3D false; - uint8_t event; =20 if (sprn =3D=3D SPR_POWER_PMC5) { return true; } =20 - event =3D get_PMC_event(env, sprn); - /* * Event 0x2 is an implementation-dependent event that IBM * POWER chips implement (at least since POWER8) that is @@ -158,8 +156,15 @@ static bool pmc_counting_insns(CPUPPCState *env, int s= prn) return event =3D=3D 0x2 || event =3D=3D 0xFE; case SPR_POWER_PMC2: case SPR_POWER_PMC3: - case SPR_POWER_PMC4: return event =3D=3D 0x2; + case SPR_POWER_PMC4: + /* + * Event 0xFA is the "instructions completed with run latch + * set" event. Consider it as instruction counting event. + * The caller is responsible for handling it separately + * from PM_INST_CMPL. + */ + return event =3D=3D 0x2 || event =3D=3D 0xFA; default: break; } @@ -173,8 +178,16 @@ void helper_insns_inc(CPUPPCState *env, uint32_t num_i= nsns) int sprn; =20 for (sprn =3D SPR_POWER_PMC1; sprn <=3D SPR_POWER_PMC5; sprn++) { - if (pmc_counting_insns(env, sprn)) { - env->spr[sprn] +=3D num_insns; + uint8_t event =3D get_PMC_event(env, sprn); + + if (pmc_counting_insns(env, sprn, event)) { + if (sprn =3D=3D SPR_POWER_PMC4 && event =3D=3D 0xFA) { + if (env->spr[SPR_CTRL] & CTRL_RUN) { + env->spr[SPR_POWER_PMC4] +=3D num_insns; + } + } else { + env->spr[sprn] +=3D num_insns; + } } } } diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h index 51fbc081de..5e6ed36eb1 100644 --- a/target/ppc/spr_tcg.h +++ b/target/ppc/spr_tcg.h @@ -26,6 +26,7 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn); void spr_read_generic(DisasContext *ctx, int gprn, int sprn); void spr_write_generic(DisasContext *ctx, int sprn, int gprn); void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn); +void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn); void spr_read_xer(DisasContext *ctx, int gprn, int sprn); void spr_write_xer(DisasContext *ctx, int sprn, int gprn); void spr_read_lr(DisasContext *ctx, int gprn, int sprn); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index b7235a2be0..866b1d2b34 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -402,6 +402,18 @@ void spr_write_generic(DisasContext *ctx, int sprn, in= t gprn) spr_store_dump_spr(sprn); } =20 +void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) +{ + spr_write_generic(ctx, sprn, gprn); + + /* + * Write in SPR_CTRL must force a new translation block, + * allowing the PMU to calculate the run latch events with + * more accuracy. + */ + ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; +} + #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn) { --=20 2.31.1 From nobody Fri May 3 01:48:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" We're missing two counter freeze bits that are used to further control how the PMCs behaves: MMCR0_FC14 and MMCR0_FC56. These bits can frozen PMCs separately: MMCR0_FC14 freezes PMCs 1 to 4 and MMCR0_FC56 freezes PMCs 5 and 6. Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 2 ++ target/ppc/power8_pmu.c | 25 ++++++++++++++++++++++--- 2 files changed, 24 insertions(+), 3 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 76b462c3c8..93f4a46827 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -351,6 +351,8 @@ typedef struct ppc_v3_pate_t { #define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */ /* MMCR0 userspace r/w mask */ #define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE) +#define MMCR0_FC14 PPC_BIT(58) /* MMCR0 Freeze Counters 1-4 bit */ +#define MMCR0_FC56 PPC_BIT(59) /* MMCR0 Freeze Counters 5-6 bit */ =20 #define MMCR1_EVT_SIZE 8 /* extract64() does a right shift before extracting */ diff --git a/target/ppc/power8_pmu.c b/target/ppc/power8_pmu.c index f584480fde..dd58f57f52 100644 --- a/target/ppc/power8_pmu.c +++ b/target/ppc/power8_pmu.c @@ -59,6 +59,15 @@ static uint8_t get_PMC_event(CPUPPCState *env, int sprn) return extract64(env->spr[SPR_POWER_MMCR1], evt_extr, MMCR1_EVT_SIZE); } =20 +static bool pmc_is_running(CPUPPCState *env, int sprn) +{ + if (sprn < SPR_POWER_PMC5) { + return !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC14); + } + + return !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC56); +} + static void update_programmable_PMC_reg(CPUPPCState *env, int sprn, uint64_t time_delta) { @@ -91,13 +100,19 @@ static void update_cycles_PMCs(CPUPPCState *env) { uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); uint64_t time_delta =3D now - env->pmu_base_time; + bool PMC14_running =3D !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC14); + bool PMC6_running =3D !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC56); int sprn; =20 - for (sprn =3D SPR_POWER_PMC1; sprn < SPR_POWER_PMC5; sprn++) { - update_programmable_PMC_reg(env, sprn, time_delta); + if (PMC14_running) { + for (sprn =3D SPR_POWER_PMC1; sprn < SPR_POWER_PMC5; sprn++) { + update_programmable_PMC_reg(env, sprn, time_delta); + } } =20 - update_PMC_PM_CYC(env, SPR_POWER_PMC6, time_delta); + if (PMC6_running) { + update_PMC_PM_CYC(env, SPR_POWER_PMC6, time_delta); + } } =20 void helper_store_mmcr0(CPUPPCState *env, target_ulong value) @@ -138,6 +153,10 @@ static bool pmc_counting_insns(CPUPPCState *env, int s= prn, { bool ret =3D false; =20 + if (!pmc_is_running(env, sprn)) { + return false; + } + if (sprn =3D=3D SPR_POWER_PMC5) { return true; } --=20 2.31.1 From nobody Fri May 3 01:48:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630701461043146.2633117529275; Fri, 3 Sep 2021 13:37:41 -0700 (PDT) Received: from localhost ([::1]:37632 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMFwS-0004yW-0K for importer@patchew.org; Fri, 03 Sep 2021 16:37:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52704) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMFqr-0002o5-9g; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f29; envelope-from=danielhb413@gmail.com; helo=mail-qv1-xf29.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , richard.henderson@linaro.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630701462081100001 Content-Type: text/plain; charset="utf-8" An Event-Based Branch (EBB) allows applications to change the NIA when a event-based exception occurs. Event-based exceptions are enabled by setting the Branch Event Status and Control Register (BESCR). If the event-based exception is enabled when the exception occurs, an EBB happens. The following operations happens during an EBB: - Global Enable (GE) bit of BESCR is set to 0; - bits 0-61 of the Event-Based Branch Return Register (EBBRR) are set to the the effective address of the NIA that would have executed if the EBB didn't happen; - Instruction fetch and execution will continue in the effective address contained in the Event-Based Branch Handler Register (EBBHR). The EBB Handler will process the event and then execute the Return From Event-Based Branch (rfebb) instruction. rfebb sets BESCR_GE and then redirects execution to the address pointed in EBBRR. This process is described in the PowerISA v3.1, Book II, Chapter 6 [1]. This patch implements the rfebb instruction. Descriptions of all relevant BESCR bits are also added - this patch is only using BESCR_GE, but the next patches will use the remaining bits. [1] https://wiki.raptorcs.com/w/images/f/f5/PowerISA_public.v3.1.pdf Signed-off-by: Daniel Henrique Barboza Reviewed-by: Matheus Ferst --- target/ppc/cpu.h | 13 ++++++++++ target/ppc/excp_helper.c | 31 ++++++++++++++++++++++++ target/ppc/helper.h | 1 + target/ppc/insn32.decode | 5 ++++ target/ppc/translate.c | 2 ++ target/ppc/translate/branch-impl.c.inc | 33 ++++++++++++++++++++++++++ 6 files changed, 85 insertions(+) create mode 100644 target/ppc/translate/branch-impl.c.inc diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 93f4a46827..26624508fa 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -368,6 +368,19 @@ typedef struct ppc_v3_pate_t { /* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */ #define CTRL_RUN PPC_BIT(63) =20 +/* EBB/BESCR bits */ +/* Global Enable */ +#define BESCR_GE PPC_BIT(0) +/* External Event-based Exception Enable */ +#define BESCR_EE PPC_BIT(30) +/* Performance Monitor Event-based Exception Enable */ +#define BESCR_PME PPC_BIT(31) +/* External Event-based Exception Occurred */ +#define BESCR_EEO PPC_BIT(62) +/* Performance Monitor Event-based Exception Occurred */ +#define BESCR_PMEO PPC_BIT(63) +#define BESCR_INVALID PPC_BITMASK(32, 33) + /* LPCR bits */ #define LPCR_VPM0 PPC_BIT(0) #define LPCR_VPM1 PPC_BIT(1) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 7b6ac16eef..22f9835383 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1281,6 +1281,37 @@ void helper_hrfid(CPUPPCState *env) } #endif =20 +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +void helper_rfebb(CPUPPCState *env, target_ulong s) +{ + target_ulong msr =3D env->msr; + + /* + * Handling of BESCR bits 32:33 according to PowerISA v3.1: + * + * "If BESCR 32:33 !=3D 0b00 the instruction is treated as if + * the instruction form were invalid." + */ + if (env->spr[SPR_BESCR] & BESCR_INVALID) { + raise_exception_err(env, POWERPC_EXCP_PROGRAM, + POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); + } + + env->nip =3D env->spr[SPR_EBBRR]; + + /* Switching to 32-bit ? Crop the nip */ + if (!msr_is_64bit(env, msr)) { + env->nip =3D (uint32_t)env->spr[SPR_EBBRR]; + } + + if (s) { + env->spr[SPR_BESCR] |=3D BESCR_GE; + } else { + env->spr[SPR_BESCR] &=3D ~BESCR_GE; + } +} +#endif + /*************************************************************************= ****/ /* Embedded PowerPC specific helpers */ void helper_40x_rfci(CPUPPCState *env) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 47dbbe6da1..91a86992a5 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -18,6 +18,7 @@ DEF_HELPER_2(pminsn, void, env, i32) DEF_HELPER_1(rfid, void, env) DEF_HELPER_1(rfscv, void, env) DEF_HELPER_1(hrfid, void, env) +DEF_HELPER_2(rfebb, void, env, tl) DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) DEF_HELPER_2(store_mmcr0, void, env, tl) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 9fd8d6b817..deb7374ea4 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -124,3 +124,8 @@ SETNBCR 011111 ..... ..... ----- 0111100000 - = @X_bi ## Vector Bit Manipulation Instruction =20 VCFUGED 000100 ..... ..... ..... 10101001101 @VX + +### rfebb +&XL_s s:uint8_t +@XL_s ......-------------- s:1 .......... - &XL_s +RFEBB 010011-------------- . 0010010010 - @XL_s diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 866b1d2b34..7a3104ecf9 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7636,6 +7636,8 @@ static int times_4(DisasContext *ctx, int x) =20 #include "translate/spe-impl.c.inc" =20 +#include "translate/branch-impl.c.inc" + /* Handles lfdp, lxsd, lxssp */ static void gen_dform39(DisasContext *ctx) { diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/= branch-impl.c.inc new file mode 100644 index 0000000000..9c991d9abb --- /dev/null +++ b/target/ppc/translate/branch-impl.c.inc @@ -0,0 +1,33 @@ +/* + * Power ISA decode for branch instructions + * + * Copyright IBM Corp. 2021 + * + * Authors: + * Daniel Henrique Barboza + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) + +static bool trans_RFEBB(DisasContext *ctx, arg_RFEBB *arg) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + + gen_icount_io_start(ctx); + gen_update_cfar(ctx, ctx->cia); + gen_helper_rfebb(cpu_env, cpu_gpr[arg->s]); + + ctx->base.is_jmp =3D DISAS_CHAIN; + + return true; +} +#else +static bool trans_RFEBB(DisasContext *ctx, arg_RFEBB *arg) +{ + gen_invalid(ctx); + return true; +} +#endif --=20 2.31.1 From nobody Fri May 3 01:48:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630701800000706.6007407495657; Fri, 3 Sep 2021 13:43:20 -0700 (PDT) Received: from localhost ([::1]:53446 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMG1u-000829-TE for importer@patchew.org; Fri, 03 Sep 2021 16:43:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52716) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMFqu-0002pw-E2; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f33; envelope-from=danielhb413@gmail.com; helo=mail-qv1-xf33.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Gustavo Romero , Gustavo Romero , Daniel Henrique Barboza , richard.henderson@linaro.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630701801733100001 Content-Type: text/plain; charset="utf-8" From: Gustavo Romero Following up the rfebb implementation, this patch adds the EBB exception support that are triggered by Performance Monitor alerts. This exception occurs when an enabled PMU condition or event happens and both MMCR0_EBE and BESCR_PME are set. The supported PM alerts will consist of counter negative conditions of the PMU counters. This will be achieved by a timer mechanism that will predict when a counter becomes negative. The PMU timer callback will set the appropriate bits in MMCR0 and fire a PMC interrupt. The EBB exception code will then set the appropriate BESCR bits, set the next instruction pointer to the address pointed by the return register (SPR_EBBRR), and redirect execution to the handler (pointed by SPR_EBBHR). This patch sets the basic structure of interrupts and timers. The following patches will add the counter negative logic for the registers. CC: Gustavo Romero Signed-off-by: Gustavo Romero Signed-off-by: Daniel Henrique Barboza --- hw/ppc/spapr_cpu_core.c | 6 ++++++ target/ppc/cpu.h | 12 +++++++++++- target/ppc/excp_helper.c | 28 +++++++++++++++++++++++++++ target/ppc/power8_pmu.c | 41 ++++++++++++++++++++++++++++++++++++++++ target/ppc/power8_pmu.h | 25 ++++++++++++++++++++++++ 5 files changed, 111 insertions(+), 1 deletion(-) create mode 100644 target/ppc/power8_pmu.h diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 4f316a6f9d..c7a342c4aa 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -20,6 +20,7 @@ #include "target/ppc/kvm_ppc.h" #include "hw/ppc/ppc.h" #include "target/ppc/mmu-hash64.h" +#include "target/ppc/power8_pmu.h" #include "sysemu/numa.h" #include "sysemu/reset.h" #include "sysemu/hw_accel.h" @@ -266,6 +267,11 @@ static bool spapr_realize_vcpu(PowerPCCPU *cpu, SpaprM= achineState *spapr, return false; } =20 + /* Init PMU interrupt timer (TCG only) */ + if (!kvm_enabled()) { + cpu_ppc_pmu_timer_init(env); + } + if (!sc->pre_3_0_migration) { vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state, cpu->machine_data); diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 26624508fa..780eab6f92 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -129,8 +129,9 @@ enum { /* ISA 3.00 additions */ POWERPC_EXCP_HVIRT =3D 101, POWERPC_EXCP_SYSCALL_VECTORED =3D 102, /* scv exception = */ + POWERPC_EXCP_EBB =3D 103, /* Event-based branch exception = */ /* EOL = */ - POWERPC_EXCP_NB =3D 103, + POWERPC_EXCP_NB =3D 104, /* QEMU exceptions: special cases we want to stop translation = */ POWERPC_EXCP_SYSCALL_USER =3D 0x203, /* System call in user mode only = */ }; @@ -1053,6 +1054,8 @@ struct ppc_radix_page_info { #define PPC_CPU_OPCODES_LEN 0x40 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20 =20 +#define PMU_TIMERS_LEN 5 + struct CPUPPCState { /* Most commonly used resources during translated code execution first= */ target_ulong gpr[32]; /* general purpose registers */ @@ -1214,6 +1217,12 @@ struct CPUPPCState { * running cycles. */ uint64_t pmu_base_time; + + /* + * Timers used to fire performance monitor alerts and + * interrupts. All PMCs but PMC5 has a timer. + */ + QEMUTimer *pmu_intr_timers[PMU_TIMERS_LEN]; }; =20 #define SET_FIT_PERIOD(a_, b_, c_, d_) \ @@ -2430,6 +2439,7 @@ enum { PPC_INTERRUPT_HMI, /* Hypervisor Maintenance interrupt */ PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt = */ PPC_INTERRUPT_HVIRT, /* Hypervisor virtualization interrupt = */ + PPC_INTERRUPT_PMC, /* Performance Monitor Counter interrupt= */ }; =20 /* Processor Compatibility mask (PCR) */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 22f9835383..d20447f171 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -821,6 +821,22 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int e= xcp_model, int excp) cpu_abort(cs, "Non maskable external exception " "is not implemented yet !\n"); break; + case POWERPC_EXCP_EBB: /* Event-based branch exception = */ + if ((env->spr[SPR_BESCR] & BESCR_GE) && + (env->spr[SPR_BESCR] & BESCR_PME)) { + target_ulong nip; + + env->spr[SPR_BESCR] &=3D ~BESCR_GE; /* Clear GE */ + env->spr[SPR_BESCR] |=3D BESCR_PMEO; /* Set PMEO */ + env->spr[SPR_EBBRR] =3D env->nip; /* Save NIP for rfebb in= sn */ + nip =3D env->spr[SPR_EBBHR]; /* EBB handler */ + powerpc_set_excp_state(cpu, nip, env->msr); + } + /* + * This interrupt is handled by userspace. No need + * to proceed. + */ + return; default: excp_invalid: cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); @@ -1068,6 +1084,18 @@ static void ppc_hw_interrupt(CPUPPCState *env) powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_THERM); return; } + /* PMC -> Event-based branch exception */ + if (env->pending_interrupts & (1 << PPC_INTERRUPT_PMC)) { + /* + * Performance Monitor event-based exception can only + * occur in problem state. + */ + if (msr_pr =3D=3D 1) { + env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_PMC); + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_EBB); + return; + } + } } =20 if (env->resume_as_sreset) { diff --git a/target/ppc/power8_pmu.c b/target/ppc/power8_pmu.c index dd58f57f52..aa5df6f51f 100644 --- a/target/ppc/power8_pmu.c +++ b/target/ppc/power8_pmu.c @@ -12,12 +12,14 @@ =20 #include "qemu/osdep.h" =20 +#include "power8_pmu.h" #include "cpu.h" #include "helper_regs.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" +#include "hw/ppc/ppc.h" =20 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) =20 @@ -115,6 +117,45 @@ static void update_cycles_PMCs(CPUPPCState *env) } } =20 +static void cpu_ppc_pmu_timer_cb(void *opaque) +{ + PowerPCCPU *cpu =3D opaque; + CPUPPCState *env =3D &cpu->env; + uint64_t mmcr0; + + mmcr0 =3D env->spr[SPR_POWER_MMCR0]; + if (env->spr[SPR_POWER_MMCR0] & MMCR0_EBE) { + /* freeeze counters if needed */ + if (mmcr0 & MMCR0_FCECE) { + mmcr0 &=3D ~MMCR0_FCECE; + mmcr0 |=3D MMCR0_FC; + } + + /* Clear PMAE and set PMAO */ + if (mmcr0 & MMCR0_PMAE) { + mmcr0 &=3D ~MMCR0_PMAE; + mmcr0 |=3D MMCR0_PMAO; + } + env->spr[SPR_POWER_MMCR0] =3D mmcr0; + + /* Fire the PMC hardware exception */ + ppc_set_irq(cpu, PPC_INTERRUPT_PMC, 1); + } +} + +void cpu_ppc_pmu_timer_init(CPUPPCState *env) +{ + PowerPCCPU *cpu =3D env_archcpu(env); + QEMUTimer *timer; + int i; + + for (i =3D 0; i < PMU_TIMERS_LEN; i++) { + timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_pmu_timer_cb, + cpu); + env->pmu_intr_timers[i] =3D timer; + } +} + void helper_store_mmcr0(CPUPPCState *env, target_ulong value) { target_ulong curr_value =3D env->spr[SPR_POWER_MMCR0]; diff --git a/target/ppc/power8_pmu.h b/target/ppc/power8_pmu.h new file mode 100644 index 0000000000..34a9d0e8a2 --- /dev/null +++ b/target/ppc/power8_pmu.h @@ -0,0 +1,25 @@ +/* + * PMU emulation helpers for TCG IBM POWER chips + * + * Copyright IBM Corp. 2021 + * + * Authors: + * Daniel Henrique Barboza + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef PMU_BOOK3S_HELPER +#define PMU_BOOK3S_HELPER + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "qemu/error-report.h" +#include "qemu/main-loop.h" + +void cpu_ppc_pmu_timer_init(CPUPPCState *env); + +#endif --=20 2.31.1 From nobody Fri May 3 01:48:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630702041107759.8411218165975; Fri, 3 Sep 2021 13:47:21 -0700 (PDT) Received: from localhost ([::1]:34552 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMG5n-0006oL-20 for importer@patchew.org; Fri, 03 Sep 2021 16:47:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52738) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMFqw-0002yx-Ai; Fri, 03 Sep 2021 16:31:58 -0400 Received: from mail-qv1-xf30.google.com ([2607:f8b0:4864:20::f30]:39716) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mMFqu-0001jt-H7; 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d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=n5657r1c1ytpRQ2DAcGa9/0aAphGsPfcwntR/5Sbm+0=; b=Gn6y8XVlhT1KevXDDdPpGGeZDLIkwk8nczgZnNUPANiMvnP7KDcMz6uhbVHs5n29Me TxlMsSC2X/+78kxPG4kdm+lWsOlCuuq4iAwo/LusRhk3JKsrgdO9I0GrJs0ljOjp0elU CwBUI+Ih9RntOTCLNKl/A73gfy9hODbC7Sgw9fABkAD/AVg8jDgjxWITu+nA0STQ9f12 bSsrpRv1fbZJXfDzjygATasNnQpvZI2wZHkUnAAHKF2ctPnDRYuawpZPF77v3uCOBzYE Xyn5Ie9jbGuwPdZpW46QkH2oD3rNzOVu5zPXGxITpWxGxgBvMtt1YMzJLvae7eq/ZDD4 uxQw== X-Gm-Message-State: AOAM532en1PLFaXjA4UnXlAX7408ze24VRdiKLX1muGJKo+E7bHAJIJ8 p7+aaFXmQJ33iWHhTgnjKg5xUTiqbLY= X-Google-Smtp-Source: ABdhPJwNT+bTJZLMqzO+kw9cCZBivpY2D9D74DrHgawD4Z/EvaWEMeNFBQJ4xkwLF79/oVOoZPhTwQ== X-Received: by 2002:a0c:f08f:: with SMTP id g15mr909891qvk.67.1630701113792; Fri, 03 Sep 2021 13:31:53 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v3 10/15] target/ppc/excp_helper.c: EBB handling adjustments Date: Fri, 3 Sep 2021 17:31:11 -0300 Message-Id: <20210903203116.80628-11-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210903203116.80628-1-danielhb413@gmail.com> References: <20210903203116.80628-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f30; envelope-from=danielhb413@gmail.com; helo=mail-qv1-xf30.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , richard.henderson@linaro.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630702041632100003 Content-Type: text/plain; charset="utf-8" The current logic is only considering event-based exceptions triggered by the performance monitor. This is true now, but we might want to add support for external event-based exceptions in the future. Let's make it a bit easier to do so by adding the bit logic that would happen in case we were dealing with an external event-based exception. While we're at it, add a few comments explaining why we're setting and clearing BESCR bits. Signed-off-by: Daniel Henrique Barboza --- target/ppc/excp_helper.c | 45 ++++++++++++++++++++++++++++++++++------ 1 file changed, 39 insertions(+), 6 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index d20447f171..6d16c986af 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -822,14 +822,47 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int = excp_model, int excp) "is not implemented yet !\n"); break; case POWERPC_EXCP_EBB: /* Event-based branch exception = */ - if ((env->spr[SPR_BESCR] & BESCR_GE) && - (env->spr[SPR_BESCR] & BESCR_PME)) { + if (env->spr[SPR_BESCR] & BESCR_GE) { target_ulong nip; =20 - env->spr[SPR_BESCR] &=3D ~BESCR_GE; /* Clear GE */ - env->spr[SPR_BESCR] |=3D BESCR_PMEO; /* Set PMEO */ - env->spr[SPR_EBBRR] =3D env->nip; /* Save NIP for rfebb in= sn */ - nip =3D env->spr[SPR_EBBHR]; /* EBB handler */ + /* + * If we have Performance Monitor Event-Based exception + * enabled (BESCR_PME) and a Performance Monitor alert + * occurred (MMCR0_PMAO), clear BESCR_PME and set BESCR_PMEO + * (Performance Monitor Event-Based Exception Occurred). + * + * Software is responsible for clearing both BESCR_PMEO and + * MMCR0_PMAO after the event has been handled. + */ + if ((env->spr[SPR_BESCR] & BESCR_PME) && + (env->spr[SPR_POWER_MMCR0] & MMCR0_PMAO)) { + env->spr[SPR_BESCR] &=3D ~BESCR_PME; + env->spr[SPR_BESCR] |=3D BESCR_PMEO; + } + + /* + * In the case of External Event-Based exceptions, do a + * similar logic with BESCR_EE and BESCR_EEO. BESCR_EEO must + * also be cleared by software. + * + * PowerISA 3.1 considers that we'll not have BESCR_PMEO and + * BESCR_EEO set at the same time. We can check for BESCR_PMEO + * being not set in step above to see if this exception was + * trigged by an external event. + */ + if (env->spr[SPR_BESCR] & BESCR_EE && + !(env->spr[SPR_BESCR] & BESCR_PMEO)) { + env->spr[SPR_BESCR] &=3D ~BESCR_EE; + env->spr[SPR_BESCR] |=3D BESCR_EEO; + } + + /* + * Clear BESCR_GE, save NIP for 'rfebb' and point the + * execution to the event handler (SPR_EBBHR) address. + */ + env->spr[SPR_BESCR] &=3D ~BESCR_GE; + env->spr[SPR_EBBRR] =3D env->nip; + nip =3D env->spr[SPR_EBBHR]; powerpc_set_excp_state(cpu, nip, env->msr); } /* --=20 2.31.1 From nobody Fri May 3 01:48:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630702469215422.5809907831739; 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Fri, 03 Sep 2021 13:31:55 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v3 11/15] target/ppc/power8_pmu.c: enable PMC1 counter negative overflow Date: Fri, 3 Sep 2021 17:31:12 -0300 Message-Id: <20210903203116.80628-12-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210903203116.80628-1-danielhb413@gmail.com> References: <20210903203116.80628-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::82d; envelope-from=danielhb413@gmail.com; helo=mail-qt1-x82d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , richard.henderson@linaro.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630702471165100001 Content-Type: text/plain; charset="utf-8" This patch starts the counter negative EBB support by enabling PMC1 counter negative overflow when PMC1 is counting cycles. A counter negative overflow happens when a performance monitor counter reaches the value 0x80000000. When that happens, if counter negative condition events are enabled in that counter, a performance monitor alert is triggered. For PMC1, this condition is enabled by MMCR0_PMC1CE. Cycle counting is done by calculating elapsed time between the time the PMU started to run and when the PMU is shut down. Our clock is fixed in 1Ghz, so 1 cycle equals 1 nanoseconds. The same idea is used to predict a counter negative overflow: calculate the amount of nanoseconds for the timer to reach 0x80000000, start a timer with it and trigger the performance monitor alert. If event-based exceptions are enabled (bit MMCR0_EBE), we'll go ahead and fire a PPC_INTERRUPT_PMC. A new function 'start_cycle_count_session' was added to encapsulate the most common steps of cycle calculation: redefine base time and start overflow timers. This will avoid code repetition in the next patches. Counter overflow for the remaining counters will be added shortly. Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 1 + target/ppc/power8_pmu.c | 99 +++++++++++++++++++++++++++++++++-------- 2 files changed, 82 insertions(+), 18 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 780eab6f92..ba93b30ae2 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -354,6 +354,7 @@ typedef struct ppc_v3_pate_t { #define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE) #define MMCR0_FC14 PPC_BIT(58) /* MMCR0 Freeze Counters 1-4 bit */ #define MMCR0_FC56 PPC_BIT(59) /* MMCR0 Freeze Counters 5-6 bit */ +#define MMCR0_PMC1CE PPC_BIT(48) /* MMCR0 PMC1 Condition Enabled */ =20 #define MMCR1_EVT_SIZE 8 /* extract64() does a right shift before extracting */ diff --git a/target/ppc/power8_pmu.c b/target/ppc/power8_pmu.c index aa5df6f51f..b2224d363a 100644 --- a/target/ppc/power8_pmu.c +++ b/target/ppc/power8_pmu.c @@ -33,6 +33,8 @@ static void update_PMC_PM_CYC(CPUPPCState *env, int sprn, env->spr[sprn] +=3D time_delta; } =20 +#define COUNTER_NEGATIVE_VAL 0x80000000 + static uint8_t get_PMC_event(CPUPPCState *env, int sprn) { uint8_t evt_extr =3D 0; @@ -117,30 +119,91 @@ static void update_cycles_PMCs(CPUPPCState *env) } } =20 +static int64_t get_CYC_timeout(CPUPPCState *env, int sprn) +{ + int64_t remaining_cyc; + + if (env->spr[sprn] >=3D COUNTER_NEGATIVE_VAL) { + return 0; + } + + remaining_cyc =3D COUNTER_NEGATIVE_VAL - env->spr[sprn]; + return remaining_cyc; +} + +static bool counter_negative_cond_enabled(uint64_t mmcr0) +{ + return mmcr0 & MMCR0_PMC1CE; +} + +/* + * A cycle count session consists of the basic operations we + * need to do to support PM_CYC events: redefine a new base_time + * to be used to calculate PMC values and start overflow timers. + */ +static void start_cycle_count_session(CPUPPCState *env) +{ + uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + uint64_t timeout; + + env->pmu_base_time =3D now; + + /* + * Always delete existing overflow timers when starting a + * new cycle counting session. + */ + timer_del(env->pmu_intr_timers[0]); + + if (!counter_negative_cond_enabled(env->spr[SPR_POWER_MMCR0])) { + return; + } + + if (!pmc_is_running(env, SPR_POWER_PMC1)) { + return; + } + + if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE)) { + return; + } + + switch (get_PMC_event(env, SPR_POWER_PMC1)) { + case 0xF0: + case 0x1E: + timeout =3D get_CYC_timeout(env, SPR_POWER_PMC1); + break; + default: + return; + } + + timer_mod(env->pmu_intr_timers[0], now + timeout); +} + static void cpu_ppc_pmu_timer_cb(void *opaque) { PowerPCCPU *cpu =3D opaque; CPUPPCState *env =3D &cpu->env; - uint64_t mmcr0; - - mmcr0 =3D env->spr[SPR_POWER_MMCR0]; - if (env->spr[SPR_POWER_MMCR0] & MMCR0_EBE) { - /* freeeze counters if needed */ - if (mmcr0 & MMCR0_FCECE) { - mmcr0 &=3D ~MMCR0_FCECE; - mmcr0 |=3D MMCR0_FC; - } =20 - /* Clear PMAE and set PMAO */ - if (mmcr0 & MMCR0_PMAE) { - mmcr0 &=3D ~MMCR0_PMAE; - mmcr0 |=3D MMCR0_PMAO; - } - env->spr[SPR_POWER_MMCR0] =3D mmcr0; + if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_EBE)) { + return; + } =20 - /* Fire the PMC hardware exception */ - ppc_set_irq(cpu, PPC_INTERRUPT_PMC, 1); + if (env->spr[SPR_POWER_MMCR0] & MMCR0_FCECE) { + env->spr[SPR_POWER_MMCR0] &=3D ~MMCR0_FCECE; + env->spr[SPR_POWER_MMCR0] |=3D MMCR0_FC; + + /* Changing MMCR0_FC demands a new hflags compute */ + hreg_compute_hflags(env); + } + + update_cycles_PMCs(env); + + if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMAE) { + env->spr[SPR_POWER_MMCR0] &=3D ~MMCR0_PMAE; + env->spr[SPR_POWER_MMCR0] |=3D MMCR0_PMAO; } + + /* Fire the PMC hardware exception */ + ppc_set_irq(cpu, PPC_INTERRUPT_PMC, 1); } =20 void cpu_ppc_pmu_timer_init(CPUPPCState *env) @@ -184,7 +247,7 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong = value) if (!curr_FC) { update_cycles_PMCs(env); } else { - env->pmu_base_time =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + start_cycle_count_session(env); } } } --=20 2.31.1 From nobody Fri May 3 01:48:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630702386800681.7832383529922; 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Fri, 03 Sep 2021 13:31:58 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v3 12/15] target/ppc/power8_pmu.c: cycles overflow with all PMCs Date: Fri, 3 Sep 2021 17:31:13 -0300 Message-Id: <20210903203116.80628-13-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210903203116.80628-1-danielhb413@gmail.com> References: <20210903203116.80628-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::833; envelope-from=danielhb413@gmail.com; helo=mail-qt1-x833.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , richard.henderson@linaro.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630702387788100001 Content-Type: text/plain; charset="utf-8" All performance monitor counters can trigger a counter negative condition if the proper MMCR0 bits are set. This patch does that for all PMCs that can count cycles by doing the following: - pmc_counter_negative_enabled() will check whether a given PMC is eligible to trigger the counter negative alert; - get_counter_neg_timeout() will return the timeout for the counter negative condition for a given PMC, or -1 if the PMC is not able to trigger this alert; - the existing counter_negative_cond_enabled() now must consider the counter negative bit for PMCs 2-6, MMCR0_PMCjCE; - start_cycle_count_session() will start overflow timers for all eligible PMCs. Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 1 + target/ppc/power8_pmu.c | 116 ++++++++++++++++++++++++++++++++++------ 2 files changed, 100 insertions(+), 17 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index ba93b30ae2..02177e584e 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -355,6 +355,7 @@ typedef struct ppc_v3_pate_t { #define MMCR0_FC14 PPC_BIT(58) /* MMCR0 Freeze Counters 1-4 bit */ #define MMCR0_FC56 PPC_BIT(59) /* MMCR0 Freeze Counters 5-6 bit */ #define MMCR0_PMC1CE PPC_BIT(48) /* MMCR0 PMC1 Condition Enabled */ +#define MMCR0_PMCjCE PPC_BIT(49) /* MMCR0 PMCj Condition Enabled */ =20 #define MMCR1_EVT_SIZE 8 /* extract64() does a right shift before extracting */ diff --git a/target/ppc/power8_pmu.c b/target/ppc/power8_pmu.c index b2224d363a..9125ba29ae 100644 --- a/target/ppc/power8_pmu.c +++ b/target/ppc/power8_pmu.c @@ -131,9 +131,81 @@ static int64_t get_CYC_timeout(CPUPPCState *env, int s= prn) return remaining_cyc; } =20 +static bool pmc_counter_negative_enabled(CPUPPCState *env, int sprn) +{ + if (!pmc_is_running(env, sprn)) { + return false; + } + + switch (sprn) { + case SPR_POWER_PMC1: + return env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE; + + case SPR_POWER_PMC2: + case SPR_POWER_PMC3: + case SPR_POWER_PMC4: + case SPR_POWER_PMC5: + case SPR_POWER_PMC6: + return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE; + + default: + break; + } + + return false; +} + +static int64_t get_counter_neg_timeout(CPUPPCState *env, int sprn) +{ + int64_t timeout =3D -1; + + if (!pmc_counter_negative_enabled(env, sprn)) { + return -1; + } + + if (env->spr[sprn] >=3D COUNTER_NEGATIVE_VAL) { + return 0; + } + + switch (sprn) { + case SPR_POWER_PMC1: + case SPR_POWER_PMC2: + case SPR_POWER_PMC3: + case SPR_POWER_PMC4: + switch (get_PMC_event(env, sprn)) { + case 0xF0: + if (sprn =3D=3D SPR_POWER_PMC1) { + timeout =3D get_CYC_timeout(env, sprn); + } + break; + case 0x1E: + timeout =3D get_CYC_timeout(env, sprn); + break; + } + + break; + case SPR_POWER_PMC6: + timeout =3D get_CYC_timeout(env, sprn); + break; + default: + break; + } + + return timeout; +} + static bool counter_negative_cond_enabled(uint64_t mmcr0) { - return mmcr0 & MMCR0_PMC1CE; + return mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE); +} + +static void pmu_delete_timers(CPUPPCState *env) +{ + int i; + + for (i =3D 0; i < PMU_TIMERS_LEN; i++) { + timer_del(env->pmu_intr_timers[i]); + } } =20 /* @@ -144,7 +216,8 @@ static bool counter_negative_cond_enabled(uint64_t mmcr= 0) static void start_cycle_count_session(CPUPPCState *env) { uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - uint64_t timeout; + int64_t timeout; + int i; =20 env->pmu_base_time =3D now; =20 @@ -152,30 +225,32 @@ static void start_cycle_count_session(CPUPPCState *en= v) * Always delete existing overflow timers when starting a * new cycle counting session. */ - timer_del(env->pmu_intr_timers[0]); + pmu_delete_timers(env); =20 if (!counter_negative_cond_enabled(env->spr[SPR_POWER_MMCR0])) { return; } =20 - if (!pmc_is_running(env, SPR_POWER_PMC1)) { - return; - } + /* + * Scroll through all programmable PMCs start counter overflow + * timers for PM_CYC events, if needed. + */ + for (i =3D SPR_POWER_PMC1; i < SPR_POWER_PMC5; i++) { + timeout =3D get_counter_neg_timeout(env, i); =20 - if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE)) { - return; - } + if (timeout =3D=3D -1) { + continue; + } =20 - switch (get_PMC_event(env, SPR_POWER_PMC1)) { - case 0xF0: - case 0x1E: - timeout =3D get_CYC_timeout(env, SPR_POWER_PMC1); - break; - default: - return; + timer_mod(env->pmu_intr_timers[i - SPR_POWER_PMC1], + now + timeout); } =20 - timer_mod(env->pmu_intr_timers[0], now + timeout); + /* Check for counter neg timeout in PMC6 */ + timeout =3D get_counter_neg_timeout(env, SPR_POWER_PMC6); + if (timeout !=3D -1) { + timer_mod(env->pmu_intr_timers[PMU_TIMERS_LEN - 1], now + timeout); + } } =20 static void cpu_ppc_pmu_timer_cb(void *opaque) @@ -193,6 +268,13 @@ static void cpu_ppc_pmu_timer_cb(void *opaque) =20 /* Changing MMCR0_FC demands a new hflags compute */ hreg_compute_hflags(env); + + /* + * Delete all pending timers if we need to freeze + * the PMC. We'll restart them when the PMC starts + * running again. + */ + pmu_delete_timers(env); } =20 update_cycles_PMCs(env); --=20 2.31.1 From nobody Fri May 3 01:48:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630701601355502.902631903489; Fri, 3 Sep 2021 13:40:01 -0700 (PDT) Received: from localhost ([::1]:44330 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMFyi-0001cP-By for importer@patchew.org; Fri, 03 Sep 2021 16:40:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52768) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMFr1-0003Hj-GV; Fri, 03 Sep 2021 16:32:03 -0400 Received: from mail-qt1-x835.google.com ([2607:f8b0:4864:20::835]:36753) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mMFqz-0001ox-Rb; Fri, 03 Sep 2021 16:32:03 -0400 Received: by mail-qt1-x835.google.com with SMTP id d11so292617qtw.3; Fri, 03 Sep 2021 13:32:01 -0700 (PDT) Received: from rekt.COMFAST ([179.247.136.122]) by smtp.gmail.com with ESMTPSA id z6sm285613qtq.78.2021.09.03.13.31.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 13:32:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KodW1W3UapdxzGinl4ph1E19T3Up3sSRrUYz7X6sIMA=; b=Kg3CMomxjX9X+zlxpDLNbP5F+8dd9JJHx7mVDIo1Aox1iNRDiSuaHG6ZsZNx8V0EId STN9wUmQscvJNRiY7E+On/oacn+yCmomfg6HX1xXyzBizNrVG72djaxOVdy/hFGPOiWL 9Wi99VLan+voxGzfLxRXL/7CM7ufu2xKUM/SvIdHbPt9Jurd7nvtuEHJbKjEqHVnsmeZ A76Eqf2CL5Grs49uOIk6sE0Pg6VuxVGrODTl5magmhlFt3xQ/DbTkJpcPFVajaL9rprD a2sR0r2m/jkoSXuH0zxFRnHXNLQ6vg7DayIsOE07jemRVdFP8xw5SfRyKXZzlLI/Y5pJ rYuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KodW1W3UapdxzGinl4ph1E19T3Up3sSRrUYz7X6sIMA=; b=qzbx1kxFDJ6OwcdYF4iwHlsQlDk/VFC7uIT5RXQnPl+iLxH2EEuY2dGXN7Fd1iQjRK InJQjLBQ+neZK0NskciBGwrzLNcmSrm8WV9z9FT5DDbaVRU3LLkre7g0e7/v3sY+Mq5W nJyCgy59XPYOzrn/LryVCnJROuITzWekb7H/WGBa3UXdFYSvw3638fuEFDPrcOCLtUZa aROaWu4/k/2gpEkOcVW9+6m9bDNhraJZiK3KiI/OD9bG0ewkiecieEVrYKgZ+94iMIyX M9Jcgg+ETdUpZXYDPssxAc2ExaEb5594/4ucShdqrrST8zLrH9eWy3JvQBaFx+uqmCqi /j7A== X-Gm-Message-State: AOAM531LBmjAEVr03y3W9xMgjt0QUoVghQ28Kl9b/AMBX7oK+5tocaq5 WpfBMKE6pzjoLs2Be8jSomWySKBd/w8= X-Google-Smtp-Source: ABdhPJx8MMyX9t16ETSjQwaghkLNnt7PpOyVb33bHhUFG7mNkQVfAFwLbVX3R0YuvhVpOFrdci7UUg== X-Received: by 2002:ac8:544e:: with SMTP id d14mr759743qtq.133.1630701120431; Fri, 03 Sep 2021 13:32:00 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v3 13/15] target/ppc: PMU: insns counter negative overflow support Date: Fri, 3 Sep 2021 17:31:14 -0300 Message-Id: <20210903203116.80628-14-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210903203116.80628-1-danielhb413@gmail.com> References: <20210903203116.80628-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::835; envelope-from=danielhb413@gmail.com; helo=mail-qt1-x835.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , richard.henderson@linaro.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630701602615100001 Content-Type: text/plain; charset="utf-8" Enabling counter negative overflow for the PMCs that are counting instructions is simpler than when counting cycles. Instruction counting is done via helper_insns_inc(), which is called every time a TB ends. Firing a performance monitor alert due to a counter negative overflow in this case is a matter of checking if the counter value is over 0x80000000 each time the counters are incremented and, if counter negative events are enabled for that specific counter, trigger the PM alert. Signed-off-by: Daniel Henrique Barboza --- target/ppc/power8_pmu.c | 23 +++++++++++++++++++++-- target/ppc/translate.c | 8 ++++++++ 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/target/ppc/power8_pmu.c b/target/ppc/power8_pmu.c index 9125ba29ae..edece140aa 100644 --- a/target/ppc/power8_pmu.c +++ b/target/ppc/power8_pmu.c @@ -253,9 +253,8 @@ static void start_cycle_count_session(CPUPPCState *env) } } =20 -static void cpu_ppc_pmu_timer_cb(void *opaque) +static void fire_PMC_interrupt(PowerPCCPU *cpu) { - PowerPCCPU *cpu =3D opaque; CPUPPCState *env =3D &cpu->env; =20 if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_EBE)) { @@ -288,6 +287,13 @@ static void cpu_ppc_pmu_timer_cb(void *opaque) ppc_set_irq(cpu, PPC_INTERRUPT_PMC, 1); } =20 +static void cpu_ppc_pmu_timer_cb(void *opaque) +{ + PowerPCCPU *cpu =3D opaque; + + fire_PMC_interrupt(cpu); +} + void cpu_ppc_pmu_timer_init(CPUPPCState *env) { PowerPCCPU *cpu =3D env_archcpu(env); @@ -380,6 +386,8 @@ static bool pmc_counting_insns(CPUPPCState *env, int sp= rn, /* This helper assumes that the PMC is running. */ void helper_insns_inc(CPUPPCState *env, uint32_t num_insns) { + bool overflow_triggered =3D false; + PowerPCCPU *cpu; int sprn; =20 for (sprn =3D SPR_POWER_PMC1; sprn <=3D SPR_POWER_PMC5; sprn++) { @@ -393,8 +401,19 @@ void helper_insns_inc(CPUPPCState *env, uint32_t num_i= nsns) } else { env->spr[sprn] +=3D num_insns; } + + if (env->spr[sprn] >=3D COUNTER_NEGATIVE_VAL && + pmc_counter_negative_enabled(env, sprn)) { + overflow_triggered =3D true; + env->spr[sprn] =3D COUNTER_NEGATIVE_VAL; + } } } + + if (overflow_triggered) { + cpu =3D env_archcpu(env); + fire_PMC_interrupt(cpu); + } } =20 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 7a3104ecf9..c23ae2479c 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4434,6 +4434,14 @@ static void pmu_count_insns(DisasContext *ctx) return; } =20 + /* + * The PMU insns_inc() helper stops the internal PMU timer if a + * counter overflows happens. In that case, if the guest is + * running with icount and we do not handle it beforehand, + * the helper can trigger a 'bad icount read'. + */ + gen_icount_io_start(ctx); + gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); } #else --=20 2.31.1 From nobody Fri May 3 01:48:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630701633320342.0579888234977; Fri, 3 Sep 2021 13:40:33 -0700 (PDT) Received: from localhost ([::1]:46108 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMFzE-0002pR-2M for importer@patchew.org; Fri, 03 Sep 2021 16:40:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52782) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMFr4-0003RD-AT; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f33; envelope-from=danielhb413@gmail.com; helo=mail-qv1-xf33.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , richard.henderson@linaro.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630701633698100001 Content-Type: text/plain; charset="utf-8" The initial PMU support were made under the assumption that the counters would be set before running the PMU and read after either freezing the PMU manually or via a performance monitor alert. Turns out that some EBB powerpc kernel tests set the counters after unfreezing the counters. Setting a PMC value when the PMU is running means that, at that moment, the baseline for calculating cycle events needs to be updated. Updating this baseline means that we need to update all the PMCs with their actual value at that moment. Any xisting counter negative timer needs to be discarded an a new one, with the updated values, must be set again. This patch does that via a new 'helper_store_pmc()' that is called in the mtspr() callbacks of PMU counters. With this change, EBB powerpc kernel tests such as 'no_handler_test' are now passing. Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu_init.c | 24 ++++++++++++------------ target/ppc/helper.h | 1 + target/ppc/power8_pmu.c | 27 +++++++++++++++++++++++++++ target/ppc/spr_tcg.h | 2 ++ target/ppc/translate.c | 35 +++++++++++++++++++++++++++++++++++ 5 files changed, 77 insertions(+), 12 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 0013cba5ff..ee300d5931 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6832,27 +6832,27 @@ static void register_book3s_pmu_sup_sprs(CPUPPCStat= e *env) KVM_REG_PPC_MMCRA, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_PMC, KVM_REG_PPC_PMC1, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_PMC, KVM_REG_PPC_PMC2, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_PMC, KVM_REG_PPC_PMC3, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_PMC, KVM_REG_PPC_PMC4, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_PMC, KVM_REG_PPC_PMC5, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_PMC, KVM_REG_PPC_PMC6, 0x00000000); spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", SPR_NOACCESS, SPR_NOACCESS, @@ -6879,27 +6879,27 @@ static void register_book3s_pmu_user_sprs(CPUPPCSta= te *env) &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UPMC1, "UPMC1", - &spr_read_ureg, &spr_write_ureg, + &spr_read_ureg, &spr_write_PMC_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UPMC2, "UPMC2", - &spr_read_ureg, &spr_write_ureg, + &spr_read_ureg, &spr_write_PMC_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UPMC3, "UPMC3", - &spr_read_ureg, &spr_write_ureg, + &spr_read_ureg, &spr_write_PMC_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UPMC4, "UPMC4", - &spr_read_ureg, &spr_write_ureg, + &spr_read_ureg, &spr_write_PMC_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UPMC5, "UPMC5", - &spr_read_ureg, &spr_write_ureg, + &spr_read_ureg, &spr_write_PMC_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_UPMC6, "UPMC6", - &spr_read_ureg, &spr_write_ureg, + &spr_read_ureg, &spr_write_PMC_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); spr_register(env, SPR_POWER_USIAR, "USIAR", diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 91a86992a5..52cb62b9e1 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -23,6 +23,7 @@ DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) DEF_HELPER_2(store_mmcr0, void, env, tl) DEF_HELPER_2(insns_inc, void, env, i32) +DEF_HELPER_3(store_pmc, void, env, i32, i64) #endif DEF_HELPER_1(check_tlb_flush_local, void, env) DEF_HELPER_1(check_tlb_flush_global, void, env) diff --git a/target/ppc/power8_pmu.c b/target/ppc/power8_pmu.c index edece140aa..9707f6e3cf 100644 --- a/target/ppc/power8_pmu.c +++ b/target/ppc/power8_pmu.c @@ -117,6 +117,14 @@ static void update_cycles_PMCs(CPUPPCState *env) if (PMC6_running) { update_PMC_PM_CYC(env, SPR_POWER_PMC6, time_delta); } + + /* + * Update base_time for future calculations if we updated + * the PMCs while the PMU was running. + */ + if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_FC)) { + env->pmu_base_time =3D now; + } } =20 static int64_t get_CYC_timeout(CPUPPCState *env, int sprn) @@ -416,4 +424,23 @@ void helper_insns_inc(CPUPPCState *env, uint32_t num_i= nsns) } } =20 +void helper_store_pmc(CPUPPCState *env, uint32_t sprn, uint64_t value) +{ + bool pmu_frozen =3D env->spr[SPR_POWER_MMCR0] & MMCR0_FC; + + if (pmu_frozen) { + env->spr[sprn] =3D value; + return; + } + + /* + * Update counters with the events counted so far, define + * the new value of the PMC and start a new cycle count + * session. + */ + update_cycles_PMCs(env); + env->spr[sprn] =3D value; + start_cycle_count_session(env); +} + #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h index 5e6ed36eb1..ced714bd09 100644 --- a/target/ppc/spr_tcg.h +++ b/target/ppc/spr_tcg.h @@ -27,6 +27,7 @@ void spr_read_generic(DisasContext *ctx, int gprn, int sp= rn); void spr_write_generic(DisasContext *ctx, int sprn, int gprn); void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn); void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn); +void spr_write_PMC(DisasContext *ctx, int sprn, int gprn); void spr_read_xer(DisasContext *ctx, int gprn, int sprn); void spr_write_xer(DisasContext *ctx, int sprn, int gprn); void spr_read_lr(DisasContext *ctx, int gprn, int sprn); @@ -46,6 +47,7 @@ void spr_read_spefscr(DisasContext *ctx, int gprn, int sp= rn); void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn); void spr_write_ureg(DisasContext *ctx, int sprn, int gprn); void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn); +void spr_write_PMC_ureg(DisasContext *ctx, int sprn, int gprn); =20 #ifndef CONFIG_USER_ONLY void spr_write_generic32(DisasContext *ctx, int sprn, int gprn); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c23ae2479c..2c5c14b4f1 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -431,13 +431,29 @@ void spr_write_MMCR0(DisasContext *ctx, int sprn, int= gprn) */ ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; } + +void spr_write_PMC(DisasContext *ctx, int sprn, int gprn) +{ + TCGv_i32 t_sprn =3D tcg_const_i32(sprn); + + gen_icount_io_start(ctx); + gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]); + + tcg_temp_free_i32(t_sprn); +} #else void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn) { spr_write_generic(ctx, sprn, gprn); } +void spr_write_PMC(DisasContext *ctx, int sprn, int gprn) +{ + spr_write_generic(ctx, sprn, gprn); +} #endif =20 + + #if !defined(CONFIG_USER_ONLY) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) { @@ -641,6 +657,20 @@ void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn,= int gprn) tcg_temp_free(t0); tcg_temp_free(t1); } + +void spr_write_PMC_ureg(DisasContext *ctx, int sprn, int gprn) +{ + /* + * All PMCs belongs to Group A SPRs and can't be written by + * userspace if PMCC =3D 0b00. + */ + if (ctx->pmcc_clear) { + gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); + return; + } + + spr_write_PMC(ctx, sprn + 0x10, gprn); +} #else void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) { @@ -651,6 +681,11 @@ void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn,= int gprn) { spr_noaccess(ctx, gprn, sprn); } + +void spr_write_PMC_ureg(DisasContext *ctx, int sprn, int gprn) +{ + spr_noaccess(ctx, gprn, sprn); +} #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ =20 /* SPR common to all non-embedded PowerPC */ --=20 2.31.1 From nobody Fri May 3 01:48:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630701798129779.8249348006807; Fri, 3 Sep 2021 13:43:18 -0700 (PDT) Received: from localhost ([::1]:53364 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMG1s-0007yZ-Qs for importer@patchew.org; Fri, 03 Sep 2021 16:43:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52794) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMFr5-0003X5-Pi; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2e; envelope-from=danielhb413@gmail.com; helo=mail-qv1-xf2e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , richard.henderson@linaro.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1630701799590100001 Content-Type: text/plain; charset="utf-8" Up until this moment we were assuming that the counter negative enabled bits, PMC1CE and PMCjCE, would never be changed when the PMU is already started. Turns out that there is no such restriction in the PowerISA v3.1, and software can enable/disable overflow conditions of the counters at any time. To support this scenario, track the overflow bits state when a write in MMCR0 is made in which the run state of the PMU (MMCR0_FC bit) didn't change and, if some overflow bit were changed in the middle of a cycle count session, restart it. Signed-off-by: Daniel Henrique Barboza --- target/ppc/power8_pmu.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/target/ppc/power8_pmu.c b/target/ppc/power8_pmu.c index 9707f6e3cf..c9b096f0de 100644 --- a/target/ppc/power8_pmu.c +++ b/target/ppc/power8_pmu.c @@ -345,6 +345,30 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong= value) } else { start_cycle_count_session(env); } + } else { + /* + * No change in MMCR0_FC state, but if the PMU is running and + * a change in the counter negative overflow bits is made, + * we need to restart a new cycle count session to restart + * the appropriate overflow timers. + */ + if (curr_FC) { + return; + } + + bool pmc1ce_curr =3D curr_value & MMCR0_PMC1CE; + bool pmc1ce_new =3D value & MMCR0_PMC1CE; + bool pmcjce_curr =3D curr_value & MMCR0_PMCjCE; + bool pmcjce_new =3D value & MMCR0_PMCjCE; + + if (pmc1ce_curr =3D=3D pmc1ce_new && pmcjce_curr =3D=3D pmcjce_new= ) { + return; + } + + /* Update the counter with the events counted so far */ + update_cycles_PMCs(env); + + start_cycle_count_session(env); } } =20 --=20 2.31.1