[v2] escc: fix reset and R_STATUS when SDLC mode is enabled

[PATCH v2 0/9] escc: fix reset and R_STATUS when SDLC mode is enabled

Mark Cave-Ayland posted 9 patches 2 years, 7 months ago

Diff against v3
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Maintainers: "Marc-André Lureau" <marcandre.lureau@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>

There is a newer version of this series

hw/char/escc.c | 281 ++++++++++++++++++++++++++++++++++---------------
1 file changed, 197 insertions(+), 84 deletions(-)

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[PATCH v2 0/9] escc: fix reset and R_STATUS when SDLC mode is enabled

Posted by Mark Cave-Ayland 2 years, 7 months ago

Here are another set of ESCC fixes from my attempts to boot MacOS on the q800
machine.

Patch 1 fixes up the formatting so that the remainder of the patchset keeps
checkpatch happy.

Patches 2-8 rework the reset handling so that the QEMU device reset is separate
from the ESCC in-built hardware and software reset as defined in the datasheet.
The aim here is two-fold: allow QEMU's device reset to place the ESCC device in
a known state (although we assume all registers are zeroed whilst their values are
undefined according to the datasheet) and ensure that the reset commands sent by
the MacOS OpenTransport extension on boot don't re-assert the active low
STATUS_SYNC bit in R_STATUS.

Finally patch 9 is the real fix: when entering SDLC mode using an "Enter hunt"
command the STATUS_SYNC bit in R_STATUS must remain high until the flag byte
is detected. Without this fix the active low STATUS_SYNC is continually asserted
causing the MacOS OpenTransport extension to hang on startup as it believes it is
constantly receiving LocalTalk traffic during its initial negotiation phase.

NOTE: this patchset currently fails CI because it exposed a bug that OpenBIOS
doesn't send ESCC channel reset commands before attempting to configure and use
the serial port. Those patches have just been posted to the OpenBIOS mailing list
here: https://mail.coreboot.org/hyperkitty/list/openbios@openbios.org/thread/PQCW5RDIDIEUYBVAHNIY3OMHCEVYYWPU/.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


v2:
- Rebase onto master
- Rewrite cover letter to cover new reset changes
- Change reset to separate out QEMU device reset, soft reset and hard reset
  (ensuring register values are updated as specified in the datasheet)
- Add R-B tags from Peter


Mark Cave-Ayland (9):
  escc: checkpatch fixes
  escc: reset register values to zero in escc_reset()
  escc: introduce escc_soft_reset_chn() for software reset
  escc: introduce escc_hard_reset_chn() for hardware reset
  escc: implement soft reset as described in the datasheet
  escc: implement hard reset as described in the datasheet
  escc: remove register changes from escc_reset_chn()
  escc: re-use escc_reset_chn() for hard and soft reset
  escc: fix STATUS_SYNC bit in R_STATUS register

 hw/char/escc.c | 281 ++++++++++++++++++++++++++++++++++---------------
 1 file changed, 197 insertions(+), 84 deletions(-)

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2.20.1