From nobody Mon May 6 10:10:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630578239733104.8772982461087; Thu, 2 Sep 2021 03:23:59 -0700 (PDT) Received: from localhost ([::1]:50782 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLjt0-000871-IQ for importer@patchew.org; Thu, 02 Sep 2021 06:23:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34624) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLjrX-0005aG-Rr for qemu-devel@nongnu.org; Thu, 02 Sep 2021 06:22:27 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:57624 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLjrV-0001Jo-AU for qemu-devel@nongnu.org; Thu, 02 Sep 2021 06:22:27 -0400 Received: from host86-133-17-27.range86-133.btcentralplus.com ([86.133.17.27] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mLjr2-0000t5-9T; Thu, 02 Sep 2021 11:22:01 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, laurent@vivier.eu Date: Thu, 2 Sep 2021 11:21:57 +0100 Message-Id: <20210902102205.7554-2-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210902102205.7554-1-mark.cave-ayland@ilande.co.uk> References: <20210902102205.7554-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.133.17.27 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 1/9] escc: checkpatch fixes X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630578241563100001 Content-Type: text/plain; charset="utf-8" Also fix a couple of spelling mistakes in comments. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/char/escc.c | 162 +++++++++++++++++++++++++++++-------------------- 1 file changed, 97 insertions(+), 65 deletions(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index 52e7978287..c87ecd59d8 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -230,20 +230,23 @@ static uint32_t get_queue(void *opaque) q->count--; } trace_escc_get_queue(CHN_C(s), val); - if (q->count > 0) + if (q->count > 0) { serial_receive_byte(s, 0); + } return val; } =20 static int escc_update_irq_chn(ESCCChannelState *s) { if ((((s->wregs[W_INTR] & INTR_TXINT) && (s->txint =3D=3D 1)) || - // tx ints enabled, pending - ((((s->wregs[W_INTR] & INTR_RXMODEMSK) =3D=3D INTR_RXINT1ST) || - ((s->wregs[W_INTR] & INTR_RXMODEMSK) =3D=3D INTR_RXINTALL)) && - s->rxint =3D=3D 1) || // rx ints enabled, pending - ((s->wregs[W_EXTINT] & EXTINT_BRKINT) && - (s->rregs[R_STATUS] & STATUS_BRK)))) { // break int e&p + /* tx ints enabled, pending */ + ((((s->wregs[W_INTR] & INTR_RXMODEMSK) =3D=3D INTR_RXINT1ST) || + ((s->wregs[W_INTR] & INTR_RXMODEMSK) =3D=3D INTR_RXINTALL)) && + s->rxint =3D=3D 1) || + /* rx ints enabled, pending */ + ((s->wregs[W_EXTINT] & EXTINT_BRKINT) && + (s->rregs[R_STATUS] & STATUS_BRK)))) { + /* break int e&p */ return 1; } return 0; @@ -269,17 +272,22 @@ static void escc_reset_chn(ESCCChannelState *s) s->rregs[i] =3D 0; s->wregs[i] =3D 0; } - s->wregs[W_TXCTRL1] =3D TXCTRL1_1STOP; // 1X divisor, 1 stop bit, no p= arity + /* 1X divisor, 1 stop bit, no parity */ + s->wregs[W_TXCTRL1] =3D TXCTRL1_1STOP; s->wregs[W_MINTR] =3D MINTR_RST_ALL; - s->wregs[W_CLOCK] =3D CLOCK_TRXC; // Synch mode tx clock =3D TRxC - s->wregs[W_MISC2] =3D MISC2_PLLDIS; // PLL disabled + /* Synch mode tx clock =3D TRxC */ + s->wregs[W_CLOCK] =3D CLOCK_TRXC; + /* PLL disabled */ + s->wregs[W_MISC2] =3D MISC2_PLLDIS; + /* Enable most interrupts */ s->wregs[W_EXTINT] =3D EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT | - EXTINT_TXUNDRN | EXTINT_BRKINT; // Enable most interrupts - if (s->disabled) + EXTINT_TXUNDRN | EXTINT_BRKINT; + if (s->disabled) { s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC | - STATUS_CTS | STATUS_TXUNDRN; - else + STATUS_CTS | STATUS_TXUNDRN; + } else { s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_TXUNDRN; + } s->rregs[R_SPEC] =3D SPEC_BITS8 | SPEC_ALLSENT; =20 s->rx =3D s->tx =3D 0; @@ -300,21 +308,25 @@ static void escc_reset(DeviceState *d) static inline void set_rxint(ESCCChannelState *s) { s->rxint =3D 1; - /* XXX: missing daisy chainnig: escc_chn_b rx should have a lower prio= rity - than chn_a rx/tx/special_condition service*/ + /* + * XXX: missing daisy chaining: escc_chn_b rx should have a lower prio= rity + * than chn_a rx/tx/special_condition service + */ s->rxint_under_svc =3D 1; if (s->chn =3D=3D escc_chn_a) { s->rregs[R_INTR] |=3D INTR_RXINTA; - if (s->wregs[W_MINTR] & MINTR_STATUSHI) + if (s->wregs[W_MINTR] & MINTR_STATUSHI) { s->otherchn->rregs[R_IVEC] =3D IVEC_HIRXINTA; - else + } else { s->otherchn->rregs[R_IVEC] =3D IVEC_LORXINTA; + } } else { s->otherchn->rregs[R_INTR] |=3D INTR_RXINTB; - if (s->wregs[W_MINTR] & MINTR_STATUSHI) + if (s->wregs[W_MINTR] & MINTR_STATUSHI) { s->rregs[R_IVEC] =3D IVEC_HIRXINTB; - else + } else { s->rregs[R_IVEC] =3D IVEC_LORXINTB; + } } escc_update_irq(s); } @@ -328,17 +340,18 @@ static inline void set_txint(ESCCChannelState *s) if (s->wregs[W_INTR] & INTR_TXINT) { s->rregs[R_INTR] |=3D INTR_TXINTA; } - if (s->wregs[W_MINTR] & MINTR_STATUSHI) + if (s->wregs[W_MINTR] & MINTR_STATUSHI) { s->otherchn->rregs[R_IVEC] =3D IVEC_HITXINTA; - else + } else { s->otherchn->rregs[R_IVEC] =3D IVEC_LOTXINTA; + } } else { s->rregs[R_IVEC] =3D IVEC_TXINTB; if (s->wregs[W_INTR] & INTR_TXINT) { s->otherchn->rregs[R_INTR] |=3D INTR_TXINTB; } } - escc_update_irq(s); + escc_update_irq(s); } } =20 @@ -347,20 +360,23 @@ static inline void clr_rxint(ESCCChannelState *s) s->rxint =3D 0; s->rxint_under_svc =3D 0; if (s->chn =3D=3D escc_chn_a) { - if (s->wregs[W_MINTR] & MINTR_STATUSHI) + if (s->wregs[W_MINTR] & MINTR_STATUSHI) { s->otherchn->rregs[R_IVEC] =3D IVEC_HINOINT; - else + } else { s->otherchn->rregs[R_IVEC] =3D IVEC_LONOINT; + } s->rregs[R_INTR] &=3D ~INTR_RXINTA; } else { - if (s->wregs[W_MINTR] & MINTR_STATUSHI) + if (s->wregs[W_MINTR] & MINTR_STATUSHI) { s->rregs[R_IVEC] =3D IVEC_HINOINT; - else + } else { s->rregs[R_IVEC] =3D IVEC_LONOINT; + } s->otherchn->rregs[R_INTR] &=3D ~INTR_RXINTB; } - if (s->txint) + if (s->txint) { set_txint(s); + } escc_update_irq(s); } =20 @@ -369,21 +385,24 @@ static inline void clr_txint(ESCCChannelState *s) s->txint =3D 0; s->txint_under_svc =3D 0; if (s->chn =3D=3D escc_chn_a) { - if (s->wregs[W_MINTR] & MINTR_STATUSHI) + if (s->wregs[W_MINTR] & MINTR_STATUSHI) { s->otherchn->rregs[R_IVEC] =3D IVEC_HINOINT; - else + } else { s->otherchn->rregs[R_IVEC] =3D IVEC_LONOINT; + } s->rregs[R_INTR] &=3D ~INTR_TXINTA; } else { s->otherchn->rregs[R_INTR] &=3D ~INTR_TXINTB; - if (s->wregs[W_MINTR] & MINTR_STATUSHI) + if (s->wregs[W_MINTR] & MINTR_STATUSHI) { s->rregs[R_IVEC] =3D IVEC_HINOINT; - else + } else { s->rregs[R_IVEC] =3D IVEC_LONOINT; + } s->otherchn->rregs[R_INTR] &=3D ~INTR_TXINTB; } - if (s->rxint) + if (s->rxint) { set_rxint(s); + } escc_update_irq(s); } =20 @@ -392,21 +411,24 @@ static void escc_update_parameters(ESCCChannelState *= s) int speed, parity, data_bits, stop_bits; QEMUSerialSetParams ssp; =20 - if (!qemu_chr_fe_backend_connected(&s->chr) || s->type !=3D escc_seria= l) + if (!qemu_chr_fe_backend_connected(&s->chr) || s->type !=3D escc_seria= l) { return; + } =20 if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREN) { - if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREV) + if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREV) { parity =3D 'E'; - else + } else { parity =3D 'O'; + } } else { parity =3D 'N'; } - if ((s->wregs[W_TXCTRL1] & TXCTRL1_STPMSK) =3D=3D TXCTRL1_2STOP) + if ((s->wregs[W_TXCTRL1] & TXCTRL1_STPMSK) =3D=3D TXCTRL1_2STOP) { stop_bits =3D 2; - else + } else { stop_bits =3D 1; + } switch (s->wregs[W_TXCTRL2] & TXCTRL2_BITMSK) { case TXCTRL2_5BITS: data_bits =3D 5; @@ -523,10 +545,11 @@ static void escc_mem_write(void *opaque, hwaddr addr, default: break; } - if (s->reg =3D=3D 0) + if (s->reg =3D=3D 0) { s->reg =3D newreg; - else + } else { s->reg =3D 0; + } break; case SERIAL_DATA: trace_escc_mem_writeb_data(CHN_C(s), val); @@ -538,17 +561,19 @@ static void escc_mem_write(void *opaque, hwaddr addr, s->txint =3D 0; escc_update_irq(s); s->tx =3D val; - if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { // tx enabled + if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { /* tx enabled */ if (qemu_chr_fe_backend_connected(&s->chr)) { - /* XXX this blocks entire thread. Rewrite to use - * qemu_chr_fe_write and background I/O callbacks */ + /* + * XXX this blocks entire thread. Rewrite to use + * qemu_chr_fe_write and background I/O callbacks + */ qemu_chr_fe_write_all(&s->chr, &s->tx, 1); } else if (s->type =3D=3D escc_kbd && !s->disabled) { handle_kbd_command(s, val); } } - s->rregs[R_STATUS] |=3D STATUS_TXEMPTY; // Tx buffer empty - s->rregs[R_SPEC] |=3D SPEC_ALLSENT; // All sent + s->rregs[R_STATUS] |=3D STATUS_TXEMPTY; /* Tx buffer empty */ + s->rregs[R_SPEC] |=3D SPEC_ALLSENT; /* All sent */ set_txint(s); break; default: @@ -606,12 +631,13 @@ static int serial_can_receive(void *opaque) ESCCChannelState *s =3D opaque; int ret; =20 - if (((s->wregs[W_RXCTRL] & RXCTRL_RXEN) =3D=3D 0) // Rx not enabled - || ((s->rregs[R_STATUS] & STATUS_RXAV) =3D=3D STATUS_RXAV)) - // char already available + if (((s->wregs[W_RXCTRL] & RXCTRL_RXEN) =3D=3D 0) /* Rx not enabled */ + || ((s->rregs[R_STATUS] & STATUS_RXAV) =3D=3D STATUS_RXAV)) { + /* char already available */ ret =3D 0; - else + } else { ret =3D 1; + } return ret; } =20 @@ -638,12 +664,13 @@ static void serial_receive1(void *opaque, const uint8= _t *buf, int size) static void serial_event(void *opaque, QEMUChrEvent event) { ESCCChannelState *s =3D opaque; - if (event =3D=3D CHR_EVENT_BREAK) + if (event =3D=3D CHR_EVENT_BREAK) { serial_receive_break(s); + } } =20 static const VMStateDescription vmstate_escc_chn =3D { - .name =3D"escc_chn", + .name =3D "escc_chn", .version_id =3D 2, .minimum_version_id =3D 1, .fields =3D (VMStateField[]) { @@ -662,7 +689,7 @@ static const VMStateDescription vmstate_escc_chn =3D { }; =20 static const VMStateDescription vmstate_escc =3D { - .name =3D"escc", + .name =3D "escc", .version_id =3D 2, .minimum_version_id =3D 1, .fields =3D (VMStateField[]) { @@ -734,21 +761,21 @@ static QemuInputHandler sunkbd_handler =3D { static void handle_kbd_command(ESCCChannelState *s, int val) { trace_escc_kbd_command(val); - if (s->led_mode) { // Ignore led byte + if (s->led_mode) { /* Ignore led byte */ s->led_mode =3D 0; return; } switch (val) { - case 1: // Reset, return type code + case 1: /* Reset, return type code */ clear_queue(s); put_queue(s, 0xff); - put_queue(s, 4); // Type 4 + put_queue(s, 4); /* Type 4 */ put_queue(s, 0x7f); break; - case 0xe: // Set leds + case 0xe: /* Set leds */ s->led_mode =3D 1; break; - case 7: // Query layout + case 7: /* Query layout */ case 0xf: clear_queue(s); put_queue(s, 0xfe); @@ -768,34 +795,39 @@ static void sunmouse_event(void *opaque, trace_escc_sunmouse_event(dx, dy, buttons_state); ch =3D 0x80 | 0x7; /* protocol start byte, no buttons pressed */ =20 - if (buttons_state & MOUSE_EVENT_LBUTTON) + if (buttons_state & MOUSE_EVENT_LBUTTON) { ch ^=3D 0x4; - if (buttons_state & MOUSE_EVENT_MBUTTON) + } + if (buttons_state & MOUSE_EVENT_MBUTTON) { ch ^=3D 0x2; - if (buttons_state & MOUSE_EVENT_RBUTTON) + } + if (buttons_state & MOUSE_EVENT_RBUTTON) { ch ^=3D 0x1; + } =20 put_queue(s, ch); =20 ch =3D dx; =20 - if (ch > 127) + if (ch > 127) { ch =3D 127; - else if (ch < -127) + } else if (ch < -127) { ch =3D -127; + } =20 put_queue(s, ch & 0xff); =20 ch =3D -dy; =20 - if (ch > 127) + if (ch > 127) { ch =3D 127; - else if (ch < -127) + } else if (ch < -127) { ch =3D -127; + } =20 put_queue(s, ch & 0xff); =20 - // MSC protocol specify two extra motion bytes + /* MSC protocol specifies two extra motion bytes */ =20 put_queue(s, 0); put_queue(s, 0); --=20 2.20.1 From nobody Mon May 6 10:10:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630578250019596.9876887657955; Thu, 2 Sep 2021 03:24:10 -0700 (PDT) Received: from localhost ([::1]:51876 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLjtA-0000Pm-St for importer@patchew.org; Thu, 02 Sep 2021 06:24:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34644) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLjrb-0005dj-6O for qemu-devel@nongnu.org; Thu, 02 Sep 2021 06:22:31 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:57630 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLjrY-0001O9-Ke for qemu-devel@nongnu.org; Thu, 02 Sep 2021 06:22:29 -0400 Received: from host86-133-17-27.range86-133.btcentralplus.com ([86.133.17.27] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mLjr7-0000t5-Fy; Thu, 02 Sep 2021 11:22:06 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, laurent@vivier.eu Date: Thu, 2 Sep 2021 11:21:58 +0100 Message-Id: <20210902102205.7554-3-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210902102205.7554-1-mark.cave-ayland@ilande.co.uk> References: <20210902102205.7554-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.133.17.27 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 2/9] escc: reset register values to zero in escc_reset() X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630578252153100003 Content-Type: text/plain; charset="utf-8" This is to ensure that a device reset always returns the ESCC to a known st= ate. Note that this is currently redundant with the same code in escc_reset_chn() but that will change shortly. Signed-off-by: Mark Cave-Ayland --- hw/char/escc.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index c87ecd59d8..b0d3b92dc1 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -300,9 +300,24 @@ static void escc_reset_chn(ESCCChannelState *s) static void escc_reset(DeviceState *d) { ESCCState *s =3D ESCC(d); + int i, j; =20 - escc_reset_chn(&s->chn[0]); - escc_reset_chn(&s->chn[1]); + for (i =3D 0; i < 2; i++) { + ESCCChannelState *cs =3D &s->chn[i]; + + /* + * According to the ESCC datasheet "Miscellaneous Questions" secti= on + * on page 384, the values of the ESCC registers are not guarantee= d on + * power-on until an explicit hardware or software reset has been + * issued. For now we zero the registers so that a device reset al= ways + * returns the emulated device to a fixed state. + */ + for (j =3D 0; j < ESCC_SERIAL_REGS; j++) { + cs->rregs[j] =3D 0; + cs->wregs[j] =3D 0; + } + escc_reset_chn(cs); + } } =20 static inline void set_rxint(ESCCChannelState *s) --=20 2.20.1 From nobody Mon May 6 10:10:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630578438289282.3568137344279; Thu, 2 Sep 2021 03:27:18 -0700 (PDT) Received: from localhost ([::1]:59382 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLjwC-0005W4-49 for importer@patchew.org; Thu, 02 Sep 2021 06:27:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34666) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLjrg-0005ja-3r for qemu-devel@nongnu.org; Thu, 02 Sep 2021 06:22:36 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:57638 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLjrd-0001Rr-Jh for qemu-devel@nongnu.org; Thu, 02 Sep 2021 06:22:34 -0400 Received: from host86-133-17-27.range86-133.btcentralplus.com ([86.133.17.27] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mLjrC-0000t5-MI; Thu, 02 Sep 2021 11:22:11 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, laurent@vivier.eu Date: Thu, 2 Sep 2021 11:21:59 +0100 Message-Id: <20210902102205.7554-4-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210902102205.7554-1-mark.cave-ayland@ilande.co.uk> References: <20210902102205.7554-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.133.17.27 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 3/9] escc: introduce escc_soft_reset_chn() for software reset X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630578438991100001 Content-Type: text/plain; charset="utf-8" This new software reset function is to be called when the appropriate chann= el software reset bit is written to register WR9. Its initial implementation is the same as the existing escc_reset_chn() function used for device reset. Signed-off-by: Mark Cave-Ayland --- hw/char/escc.c | 38 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index b0d3b92dc1..935ec1aef6 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -297,6 +297,40 @@ static void escc_reset_chn(ESCCChannelState *s) clear_queue(s); } =20 +static void escc_soft_reset_chn(ESCCChannelState *s) +{ + int i; + + s->reg =3D 0; + for (i =3D 0; i < ESCC_SERIAL_REGS; i++) { + s->rregs[i] =3D 0; + s->wregs[i] =3D 0; + } + /* 1X divisor, 1 stop bit, no parity */ + s->wregs[W_TXCTRL1] =3D TXCTRL1_1STOP; + s->wregs[W_MINTR] =3D MINTR_RST_ALL; + /* Synch mode tx clock =3D TRxC */ + s->wregs[W_CLOCK] =3D CLOCK_TRXC; + /* PLL disabled */ + s->wregs[W_MISC2] =3D MISC2_PLLDIS; + /* Enable most interrupts */ + s->wregs[W_EXTINT] =3D EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT | + EXTINT_TXUNDRN | EXTINT_BRKINT; + if (s->disabled) { + s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC | + STATUS_CTS | STATUS_TXUNDRN; + } else { + s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_TXUNDRN; + } + s->rregs[R_SPEC] =3D SPEC_BITS8 | SPEC_ALLSENT; + + s->rx =3D s->tx =3D 0; + s->rxint =3D s->txint =3D 0; + s->rxint_under_svc =3D s->txint_under_svc =3D 0; + s->e0_mode =3D s->led_mode =3D s->caps_lock_mode =3D s->num_lock_mode = =3D 0; + clear_queue(s); +} + static void escc_reset(DeviceState *d) { ESCCState *s =3D ESCC(d); @@ -547,10 +581,10 @@ static void escc_mem_write(void *opaque, hwaddr addr, default: break; case MINTR_RST_B: - escc_reset_chn(&serial->chn[0]); + escc_soft_reset_chn(&serial->chn[0]); return; case MINTR_RST_A: - escc_reset_chn(&serial->chn[1]); + escc_soft_reset_chn(&serial->chn[1]); return; case MINTR_RST_ALL: escc_reset(DEVICE(serial)); --=20 2.20.1 From nobody Mon May 6 10:10:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630578770016118.19207014732694; Thu, 2 Sep 2021 03:32:50 -0700 (PDT) Received: from localhost ([::1]:47330 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLk1R-0000Ge-GR for importer@patchew.org; Thu, 02 Sep 2021 06:32:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34716) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLjrl-0005y3-E0 for qemu-devel@nongnu.org; Thu, 02 Sep 2021 06:22:41 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:57644 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLjrh-0001Vc-Vr for qemu-devel@nongnu.org; Thu, 02 Sep 2021 06:22:41 -0400 Received: from host86-133-17-27.range86-133.btcentralplus.com ([86.133.17.27] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mLjrH-0000t5-UQ; Thu, 02 Sep 2021 11:22:16 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, laurent@vivier.eu Date: Thu, 2 Sep 2021 11:22:00 +0100 Message-Id: <20210902102205.7554-5-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210902102205.7554-1-mark.cave-ayland@ilande.co.uk> References: <20210902102205.7554-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.133.17.27 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 4/9] escc: introduce escc_hard_reset_chn() for hardware reset X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630578771391100001 Content-Type: text/plain; charset="utf-8" This new hardware reset function is to be called for both channels when the hardware reset bit is written to register WR9. Its initial implementation is the same as the existing escc_reset_chn() function used for device reset. Signed-off-by: Mark Cave-Ayland --- hw/char/escc.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index 935ec1aef6..691086d97d 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -331,6 +331,40 @@ static void escc_soft_reset_chn(ESCCChannelState *s) clear_queue(s); } =20 +static void escc_hard_reset_chn(ESCCChannelState *s) +{ + int i; + + s->reg =3D 0; + for (i =3D 0; i < ESCC_SERIAL_REGS; i++) { + s->rregs[i] =3D 0; + s->wregs[i] =3D 0; + } + /* 1X divisor, 1 stop bit, no parity */ + s->wregs[W_TXCTRL1] =3D TXCTRL1_1STOP; + s->wregs[W_MINTR] =3D MINTR_RST_ALL; + /* Synch mode tx clock =3D TRxC */ + s->wregs[W_CLOCK] =3D CLOCK_TRXC; + /* PLL disabled */ + s->wregs[W_MISC2] =3D MISC2_PLLDIS; + /* Enable most interrupts */ + s->wregs[W_EXTINT] =3D EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT | + EXTINT_TXUNDRN | EXTINT_BRKINT; + if (s->disabled) { + s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC | + STATUS_CTS | STATUS_TXUNDRN; + } else { + s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_TXUNDRN; + } + s->rregs[R_SPEC] =3D SPEC_BITS8 | SPEC_ALLSENT; + + s->rx =3D s->tx =3D 0; + s->rxint =3D s->txint =3D 0; + s->rxint_under_svc =3D s->txint_under_svc =3D 0; + s->e0_mode =3D s->led_mode =3D s->caps_lock_mode =3D s->num_lock_mode = =3D 0; + clear_queue(s); +} + static void escc_reset(DeviceState *d) { ESCCState *s =3D ESCC(d); @@ -587,7 +621,8 @@ static void escc_mem_write(void *opaque, hwaddr addr, escc_soft_reset_chn(&serial->chn[1]); return; case MINTR_RST_ALL: - escc_reset(DEVICE(serial)); + escc_hard_reset_chn(&serial->chn[0]); + escc_hard_reset_chn(&serial->chn[1]); return; } break; --=20 2.20.1 From nobody Mon May 6 10:10:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630578458228716.8717558723924; Thu, 2 Sep 2021 03:27:38 -0700 (PDT) Received: from localhost ([::1]:60392 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLjwW-0006CU-Th for importer@patchew.org; Thu, 02 Sep 2021 06:27:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34742) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLjro-00065C-0H for qemu-devel@nongnu.org; Thu, 02 Sep 2021 06:22:44 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:57650 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLjrm-0001Yw-4P for qemu-devel@nongnu.org; Thu, 02 Sep 2021 06:22:43 -0400 Received: from host86-133-17-27.range86-133.btcentralplus.com ([86.133.17.27] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mLjrM-0000t5-5T; Thu, 02 Sep 2021 11:22:20 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, laurent@vivier.eu Date: Thu, 2 Sep 2021 11:22:01 +0100 Message-Id: <20210902102205.7554-6-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210902102205.7554-1-mark.cave-ayland@ilande.co.uk> References: <20210902102205.7554-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.133.17.27 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 5/9] escc: implement soft reset as described in the datasheet X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630578458471100001 Content-Type: text/plain; charset="utf-8" The software reset differs from a device reset in that it only changes the = contents of specific registers. Remove the code that resets all the registers to zer= o during soft reset and implement the default values listed in the table in the "Z85= C30 Reset" section. Signed-off-by: Mark Cave-Ayland --- hw/char/escc.c | 47 ++++++++++++++++++++++++++++++++--------------- 1 file changed, 32 insertions(+), 15 deletions(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index 691086d97d..9a4e5ae20d 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -89,6 +89,8 @@ #define INTR_RXMODEMSK 0x18 #define INTR_RXINT1ST 0x08 #define INTR_RXINTALL 0x10 +#define INTR_WTDMA_EN 0x40 +#define INTR_WTDMA_RQ 0x80 #define W_IVEC 2 #define W_RXCTRL 3 #define RXCTRL_RXEN 0x01 @@ -105,27 +107,38 @@ #define TXCTRL1_CLK64X 0xc0 #define TXCTRL1_CLKMSK 0xc0 #define W_TXCTRL2 5 +#define TXCTRL2_RTS 0x02 +#define TXCTRL2_CRCPLY 0x04 #define TXCTRL2_TXEN 0x08 #define TXCTRL2_BITMSK 0x60 #define TXCTRL2_5BITS 0x00 +#define TXCTRL2_SNDBRK 0x10 #define TXCTRL2_7BITS 0x20 #define TXCTRL2_6BITS 0x40 #define TXCTRL2_8BITS 0x60 +#define TXCTRL2_DTR 0x80 #define W_SYNC1 6 #define W_SYNC2 7 #define W_TXBUF 8 #define W_MINTR 9 #define MINTR_STATUSHI 0x10 +#define MINTR_SOFTIACK 0x20 #define MINTR_RST_MASK 0xc0 #define MINTR_RST_B 0x40 #define MINTR_RST_A 0x80 #define MINTR_RST_ALL 0xc0 #define W_MISC1 10 +#define MISC1_ENC_MASK 0x60 #define W_CLOCK 11 #define CLOCK_TRXC 0x08 #define W_BRGLO 12 #define W_BRGHI 13 #define W_MISC2 14 +#define MISC2_DTRREQ 0x04 +#define MISC2_AUTOECHO 0x08 +#define MISC2_LCL_LOOP 0x10 +#define MISC2_PLLCMD0 0x20 +#define MISC2_PLLCMD1 0x40 #define MISC2_PLLDIS 0x30 #define W_EXTINT 15 #define EXTINT_DCD 0x08 @@ -170,6 +183,7 @@ #define R_RXBUF 8 #define R_RXCTRL 9 #define R_MISC 10 +#define MISC_2CLKMISS 0x40 #define R_MISC1 11 #define R_BRGLO 12 #define R_BRGHI 13 @@ -299,30 +313,33 @@ static void escc_reset_chn(ESCCChannelState *s) =20 static void escc_soft_reset_chn(ESCCChannelState *s) { - int i; - s->reg =3D 0; - for (i =3D 0; i < ESCC_SERIAL_REGS; i++) { - s->rregs[i] =3D 0; - s->wregs[i] =3D 0; - } + s->wregs[W_CMD] =3D 0; + s->wregs[W_INTR] &=3D ~(INTR_INTALL | INTR_TXINT | INTR_RXINT1ST | + INTR_RXINTALL | INTR_WTDMA_EN | INTR_WTDMA_RQ); + s->wregs[W_RXCTRL] &=3D ~RXCTRL_RXEN; /* 1X divisor, 1 stop bit, no parity */ s->wregs[W_TXCTRL1] =3D TXCTRL1_1STOP; - s->wregs[W_MINTR] =3D MINTR_RST_ALL; - /* Synch mode tx clock =3D TRxC */ - s->wregs[W_CLOCK] =3D CLOCK_TRXC; + s->wregs[W_TXCTRL2] &=3D ~(TXCTRL2_RTS | TXCTRL2_CRCPLY | TXCTRL2_TXEN= | + TXCTRL2_SNDBRK | TXCTRL2_DTR); + s->wregs[W_MINTR] &=3D ~MINTR_SOFTIACK; + s->wregs[W_MISC1] &=3D ~MISC1_ENC_MASK; /* PLL disabled */ - s->wregs[W_MISC2] =3D MISC2_PLLDIS; + s->wregs[W_MISC2] &=3D ~(MISC2_DTRREQ | MISC2_AUTOECHO | MISC2_PLLCMD0= ); + s->wregs[W_MISC2] |=3D MISC2_PLLCMD1; /* Enable most interrupts */ s->wregs[W_EXTINT] =3D EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT | EXTINT_TXUNDRN | EXTINT_BRKINT; + + s->rregs[R_STATUS] &=3D ~(STATUS_RXAV | STATUS_ZERO); + s->rregs[R_STATUS] |=3D STATUS_TXEMPTY | STATUS_TXUNDRN; if (s->disabled) { - s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC | - STATUS_CTS | STATUS_TXUNDRN; - } else { - s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_TXUNDRN; + s->rregs[R_STATUS] |=3D STATUS_DCD | STATUS_SYNC | STATUS_CTS; } - s->rregs[R_SPEC] =3D SPEC_BITS8 | SPEC_ALLSENT; + s->rregs[R_SPEC] &=3D SPEC_ALLSENT; + s->rregs[R_SPEC] |=3D SPEC_BITS8; + s->rregs[R_INTR] =3D 0; + s->rregs[R_MISC] &=3D ~MISC_2CLKMISS; =20 s->rx =3D s->tx =3D 0; s->rxint =3D s->txint =3D 0; --=20 2.20.1 From nobody Mon May 6 10:10:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630578257188777.2382617437625; Thu, 2 Sep 2021 03:24:17 -0700 (PDT) Received: from localhost ([::1]:52040 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLjtI-0000W0-54 for importer@patchew.org; Thu, 02 Sep 2021 06:24:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34754) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLjrs-0006C8-Pt for qemu-devel@nongnu.org; Thu, 02 Sep 2021 06:22:48 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:57656 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLjrr-0001ca-7S for qemu-devel@nongnu.org; Thu, 02 Sep 2021 06:22:48 -0400 Received: from host86-133-17-27.range86-133.btcentralplus.com ([86.133.17.27] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mLjrQ-0000t5-DB; Thu, 02 Sep 2021 11:22:24 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, laurent@vivier.eu Date: Thu, 2 Sep 2021 11:22:02 +0100 Message-Id: <20210902102205.7554-7-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210902102205.7554-1-mark.cave-ayland@ilande.co.uk> References: <20210902102205.7554-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.133.17.27 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 6/9] escc: implement hard reset as described in the datasheet X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630578258659100001 Content-Type: text/plain; charset="utf-8" The hardware reset differs from a device reset in that it only changes the = contents of specific registers. Remove the code that resets all the registers to zer= o during hardware reset and implement the default values listed in the table in the = "Z85C30 Reset" section. Signed-off-by: Mark Cave-Ayland --- hw/char/escc.c | 36 ++++++++++++++++++++++-------------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index 9a4e5ae20d..1d90e77db7 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -121,6 +121,8 @@ #define W_SYNC2 7 #define W_TXBUF 8 #define W_MINTR 9 +#define MINTR_VIS 0x01 +#define MINTR_NV 0x02 #define MINTR_STATUSHI 0x10 #define MINTR_SOFTIACK 0x20 #define MINTR_RST_MASK 0xc0 @@ -139,6 +141,7 @@ #define MISC2_LCL_LOOP 0x10 #define MISC2_PLLCMD0 0x20 #define MISC2_PLLCMD1 0x40 +#define MISC2_PLLCMD2 0x80 #define MISC2_PLLDIS 0x30 #define W_EXTINT 15 #define EXTINT_DCD 0x08 @@ -350,30 +353,35 @@ static void escc_soft_reset_chn(ESCCChannelState *s) =20 static void escc_hard_reset_chn(ESCCChannelState *s) { - int i; - s->reg =3D 0; - for (i =3D 0; i < ESCC_SERIAL_REGS; i++) { - s->rregs[i] =3D 0; - s->wregs[i] =3D 0; - } + s->wregs[W_CMD] =3D 0; + s->wregs[W_INTR] &=3D ~(INTR_INTALL | INTR_TXINT | INTR_RXINT1ST | + INTR_RXINTALL | INTR_WTDMA_EN | INTR_WTDMA_RQ); + s->wregs[W_RXCTRL] &=3D ~RXCTRL_RXEN; /* 1X divisor, 1 stop bit, no parity */ s->wregs[W_TXCTRL1] =3D TXCTRL1_1STOP; - s->wregs[W_MINTR] =3D MINTR_RST_ALL; - /* Synch mode tx clock =3D TRxC */ + s->wregs[W_TXCTRL2] &=3D ~(TXCTRL2_RTS | TXCTRL2_CRCPLY | TXCTRL2_TXEN= | + TXCTRL2_SNDBRK | TXCTRL2_DTR); + s->wregs[W_MINTR] &=3D MINTR_VIS | MINTR_NV; + s->wregs[W_MINTR] |=3D MINTR_RST_B | MINTR_RST_A; + s->wregs[W_MISC1] =3D 0; s->wregs[W_CLOCK] =3D CLOCK_TRXC; /* PLL disabled */ - s->wregs[W_MISC2] =3D MISC2_PLLDIS; + s->wregs[W_MISC2] &=3D MISC2_PLLCMD1 | MISC2_PLLCMD2; + s->wregs[W_MISC2] |=3D MISC2_LCL_LOOP | MISC2_PLLCMD0; /* Enable most interrupts */ s->wregs[W_EXTINT] =3D EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT | EXTINT_TXUNDRN | EXTINT_BRKINT; + + s->rregs[R_STATUS] &=3D ~(STATUS_RXAV | STATUS_ZERO); + s->rregs[R_STATUS] |=3D STATUS_TXEMPTY | STATUS_TXUNDRN; if (s->disabled) { - s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC | - STATUS_CTS | STATUS_TXUNDRN; - } else { - s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_TXUNDRN; + s->rregs[R_STATUS] |=3D STATUS_DCD | STATUS_SYNC | STATUS_CTS; } - s->rregs[R_SPEC] =3D SPEC_BITS8 | SPEC_ALLSENT; + s->rregs[R_SPEC] &=3D SPEC_ALLSENT; + s->rregs[R_SPEC] |=3D SPEC_BITS8; + s->rregs[R_INTR] =3D 0; + s->rregs[R_MISC] &=3D ~MISC_2CLKMISS; =20 s->rx =3D s->tx =3D 0; s->rxint =3D s->txint =3D 0; --=20 2.20.1 From nobody Mon May 6 10:10:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630578464938930.5089733150216; Thu, 2 Sep 2021 03:27:44 -0700 (PDT) Received: from localhost ([::1]:60706 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLjwd-0006P3-Sc for importer@patchew.org; Thu, 02 Sep 2021 06:27:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34790) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLjrx-0006Nz-TL for qemu-devel@nongnu.org; Thu, 02 Sep 2021 06:22:53 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:57662 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLjru-0001gK-FR for qemu-devel@nongnu.org; Thu, 02 Sep 2021 06:22:52 -0400 Received: from host86-133-17-27.range86-133.btcentralplus.com ([86.133.17.27] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mLjrU-0000t5-Kc; Thu, 02 Sep 2021 11:22:28 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, laurent@vivier.eu Date: Thu, 2 Sep 2021 11:22:03 +0100 Message-Id: <20210902102205.7554-8-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210902102205.7554-1-mark.cave-ayland@ilande.co.uk> References: <20210902102205.7554-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.133.17.27 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 7/9] escc: remove register changes from escc_reset_chn() X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630578467119100001 Content-Type: text/plain; charset="utf-8" Now that register values at reset are handled elsewhere for all of device r= eset, soft reset and hard reset, escc_reset_chn() only needs to handle initialisa= tion of internal device state. Signed-off-by: Mark Cave-Ayland --- hw/char/escc.c | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index 1d90e77db7..c6b477ef78 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -142,7 +142,6 @@ #define MISC2_PLLCMD0 0x20 #define MISC2_PLLCMD1 0x40 #define MISC2_PLLCMD2 0x80 -#define MISC2_PLLDIS 0x30 #define W_EXTINT 15 #define EXTINT_DCD 0x08 #define EXTINT_SYNCINT 0x10 @@ -282,31 +281,7 @@ static void escc_update_irq(ESCCChannelState *s) =20 static void escc_reset_chn(ESCCChannelState *s) { - int i; - s->reg =3D 0; - for (i =3D 0; i < ESCC_SERIAL_REGS; i++) { - s->rregs[i] =3D 0; - s->wregs[i] =3D 0; - } - /* 1X divisor, 1 stop bit, no parity */ - s->wregs[W_TXCTRL1] =3D TXCTRL1_1STOP; - s->wregs[W_MINTR] =3D MINTR_RST_ALL; - /* Synch mode tx clock =3D TRxC */ - s->wregs[W_CLOCK] =3D CLOCK_TRXC; - /* PLL disabled */ - s->wregs[W_MISC2] =3D MISC2_PLLDIS; - /* Enable most interrupts */ - s->wregs[W_EXTINT] =3D EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT | - EXTINT_TXUNDRN | EXTINT_BRKINT; - if (s->disabled) { - s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC | - STATUS_CTS | STATUS_TXUNDRN; - } else { - s->rregs[R_STATUS] =3D STATUS_TXEMPTY | STATUS_TXUNDRN; - } - s->rregs[R_SPEC] =3D SPEC_BITS8 | SPEC_ALLSENT; - s->rx =3D s->tx =3D 0; s->rxint =3D s->txint =3D 0; s->rxint_under_svc =3D s->txint_under_svc =3D 0; --=20 2.20.1 From nobody Mon May 6 10:10:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630578285603110.34348286484442; Thu, 2 Sep 2021 03:24:45 -0700 (PDT) Received: from localhost ([::1]:53870 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLjtk-0001iW-J2 for importer@patchew.org; Thu, 02 Sep 2021 06:24:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34828) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLjs2-0006Zj-0Z for qemu-devel@nongnu.org; Thu, 02 Sep 2021 06:22:58 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:57668 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLjs0-0001lC-9o for qemu-devel@nongnu.org; Thu, 02 Sep 2021 06:22:57 -0400 Received: from host86-133-17-27.range86-133.btcentralplus.com ([86.133.17.27] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mLjrY-0000t5-RY; Thu, 02 Sep 2021 11:22:34 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, laurent@vivier.eu Date: Thu, 2 Sep 2021 11:22:04 +0100 Message-Id: <20210902102205.7554-9-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210902102205.7554-1-mark.cave-ayland@ilande.co.uk> References: <20210902102205.7554-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.133.17.27 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 8/9] escc: re-use escc_reset_chn() for hard and soft reset X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630578286761100001 Content-Type: text/plain; charset="utf-8" This removes duplication of the internal device state initialisation from a= ll of device reset, soft reset and hard reset. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/char/escc.c | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index c6b477ef78..29fcdcb625 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -291,7 +291,8 @@ static void escc_reset_chn(ESCCChannelState *s) =20 static void escc_soft_reset_chn(ESCCChannelState *s) { - s->reg =3D 0; + escc_reset_chn(s); + s->wregs[W_CMD] =3D 0; s->wregs[W_INTR] &=3D ~(INTR_INTALL | INTR_TXINT | INTR_RXINT1ST | INTR_RXINTALL | INTR_WTDMA_EN | INTR_WTDMA_RQ); @@ -318,17 +319,12 @@ static void escc_soft_reset_chn(ESCCChannelState *s) s->rregs[R_SPEC] |=3D SPEC_BITS8; s->rregs[R_INTR] =3D 0; s->rregs[R_MISC] &=3D ~MISC_2CLKMISS; - - s->rx =3D s->tx =3D 0; - s->rxint =3D s->txint =3D 0; - s->rxint_under_svc =3D s->txint_under_svc =3D 0; - s->e0_mode =3D s->led_mode =3D s->caps_lock_mode =3D s->num_lock_mode = =3D 0; - clear_queue(s); } =20 static void escc_hard_reset_chn(ESCCChannelState *s) { - s->reg =3D 0; + escc_reset_chn(s); + s->wregs[W_CMD] =3D 0; s->wregs[W_INTR] &=3D ~(INTR_INTALL | INTR_TXINT | INTR_RXINT1ST | INTR_RXINTALL | INTR_WTDMA_EN | INTR_WTDMA_RQ); @@ -357,12 +353,6 @@ static void escc_hard_reset_chn(ESCCChannelState *s) s->rregs[R_SPEC] |=3D SPEC_BITS8; s->rregs[R_INTR] =3D 0; s->rregs[R_MISC] &=3D ~MISC_2CLKMISS; - - s->rx =3D s->tx =3D 0; - s->rxint =3D s->txint =3D 0; - s->rxint_under_svc =3D s->txint_under_svc =3D 0; - s->e0_mode =3D s->led_mode =3D s->caps_lock_mode =3D s->num_lock_mode = =3D 0; - clear_queue(s); } =20 static void escc_reset(DeviceState *d) --=20 2.20.1 From nobody Mon May 6 10:10:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1630578610035703.6638791574567; Thu, 2 Sep 2021 03:30:10 -0700 (PDT) Received: from localhost ([::1]:40418 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLjyy-0003pg-Rh for importer@patchew.org; Thu, 02 Sep 2021 06:30:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34882) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLjs6-0006o3-Hv for qemu-devel@nongnu.org; Thu, 02 Sep 2021 06:23:02 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:57670 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLjs4-0001or-TH for qemu-devel@nongnu.org; Thu, 02 Sep 2021 06:23:02 -0400 Received: from host86-133-17-27.range86-133.btcentralplus.com ([86.133.17.27] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mLjre-0000t5-3A; Thu, 02 Sep 2021 11:22:39 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, laurent@vivier.eu Date: Thu, 2 Sep 2021 11:22:05 +0100 Message-Id: <20210902102205.7554-10-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210902102205.7554-1-mark.cave-ayland@ilande.co.uk> References: <20210902102205.7554-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.133.17.27 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 9/9] escc: fix STATUS_SYNC bit in R_STATUS register X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630578611530100001 Content-Type: text/plain; charset="utf-8" After an SDLC "Enter hunt" command has been sent the STATUS_SYNC bit should= remain high until the flag byte has been detected. Whilst the ESCC device doesn't = yet implement SDLC mode, without this change the active low STATUS_SYNC is cons= tantly asserted causing the MacOS OpenTransport extension to hang on startup as it= thinks it is constantly receiving LocalTalk responses during its initial negotiati= on phase. Signed-off-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- hw/char/escc.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index 29fcdcb625..b566758d62 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -94,6 +94,7 @@ #define W_IVEC 2 #define W_RXCTRL 3 #define RXCTRL_RXEN 0x01 +#define RXCTRL_HUNT 0x10 #define W_TXCTRL1 4 #define TXCTRL1_PAREN 0x01 #define TXCTRL1_PAREV 0x02 @@ -582,7 +583,13 @@ static void escc_mem_write(void *opaque, hwaddr addr, break; } break; - case W_INTR ... W_RXCTRL: + case W_RXCTRL: + s->wregs[s->reg] =3D val; + if (val & RXCTRL_HUNT) { + s->rregs[R_STATUS] |=3D STATUS_SYNC; + } + break; + case W_INTR ... W_IVEC: case W_SYNC1 ... W_TXBUF: case W_MISC1 ... W_CLOCK: case W_MISC2 ... W_EXTINT: --=20 2.20.1