Series comparison

-[PULL 00/17] target-arm queue
+[PULL 00/24] target-arm queue
-Arm changes for before softfreeze: mostly my PL061/GPIO patches,
+Hi; here's the latest round of arm patches. I have included also
-but also a new M-profile board and various other things.
+my patchset for the RTC devices to avoid keeping time_t and
 time_t diffs in 32-bit variables.
 thanks
 -- PMM
-The following changes since commit 05de778b5b8ab0b402996769117b88c7ea5c7c61:
+The following changes since commit 156618d9ea67f2f2e31d9dedd97f2dcccbe6808c:
-  Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2021-07-09 14:30:01 +0100)
+  Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-08-30 09:20:27 -0400)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210709
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230831
-for you to fetch changes up to 05449abb1d4c5f0c69ceb3d8d03cbc75de39b646:
+for you to fetch changes up to e73b8bb8a3e9a162f70e9ffbf922d4fafc96bbfb:
-  hw/intc: Improve formatting of MEMTX_ERROR guest error message (2021-07-09 16:09:12 +0100)
+  hw/arm: Set number of MPU regions correctly for an505, an521, an524 (2023-08-31 11:07:02 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * New machine type: stm32vldiscovery
+ * Some of the preliminary patches for Cortex-A710 support
- * hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write
+ * i.MX7 and i.MX6UL refactoring
- * hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
+ * Implement SRC device for i.MX7
- * virt: Fix implementation of GPIO-based powerdown/shutdown mechanism
+ * Catch illegal-exception-return from EL3 with bad NSE/NS
- * Correct the encoding of MDCCSR_EL0 and DBGDSCRint
+ * Use 64-bit offsets for holding time_t differences in RTC devices
- * hw/intc: Improve formatting of MEMTX_ERROR guest error message
+ * Model correct number of MPU regions for an505, an521, an524 boards
 ----------------------------------------------------------------
-Alexandre Iooss (4):
+Alex Bennée (1):
-      stm32f100: Add the stm32f100 SoC
+      target/arm: properly document FEAT_CRC32
       stm32vldiscovery: Add the STM32VLDISCOVERY Machine
       docs/system: arm: Add stm32 boards description
       tests/boot-serial-test: Add STM32VLDISCOVERY board testcase
-Peter Maydell (10):
+Jean-Christophe Dubois (6):
-      hw/gpio/pl061: Convert DPRINTF to tracepoints
+      Remove i.MX7 IOMUX GPR device from i.MX6UL
-      hw/gpio/pl061: Clean up read/write offset handling logic
+      Refactor i.MX6UL processor code
-      hw/gpio/pl061: Add tracepoints for register read and write
+      Add i.MX6UL missing devices.
-      hw/gpio/pl061: Document the interface of this device
+      Refactor i.MX7 processor code
-      hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
+      Add i.MX7 missing TZ devices and memory regions
-      hw/gpio/pl061: Make pullup/pulldown of outputs configurable
+      Add i.MX7 SRC device implementation
       hw/arm/virt: Make PL061 GPIO lines pulled low, not high
       hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset
       hw/gpio/pl061: Document a shortcoming in our implementation
       hw/arm/stellaris: Expand comment about handling of OLED chipselect
-Rebecca Cran (1):
+Peter Maydell (8):
-      hw/intc: Improve formatting of MEMTX_ERROR guest error message
+      target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS
       hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()
       hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec
       hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference
       rtc: Use time_t for passing and returning time offsets
       target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init
       hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties
       hw/arm: Set number of MPU regions correctly for an505, an521, an524
-Ricardo Koller (1):
+Richard Henderson (9):
-      hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write
+      target/arm: Reduce dcz_blocksize to uint8_t
       target/arm: Allow cpu to configure GM blocksize
       target/arm: Support more GM blocksizes
       target/arm: When tag memory is not present, set MTE=1
       target/arm: Introduce make_ccsidr64
       target/arm: Apply access checks to neoverse-n1 special registers
       target/arm: Apply access checks to neoverse-v1 special registers
       target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)
       target/arm: Implement FEAT_HPDS2 as a no-op
-hnick@vmware.com (1):
+ docs/system/arm/emulation.rst  |   2 +
-      target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint
+ include/hw/arm/armsse.h        |   5 +
  include/hw/arm/armv7m.h        |   8 +
  include/hw/arm/fsl-imx6ul.h    | 158 ++++++++++++++++---
  include/hw/arm/fsl-imx7.h      | 338 ++++++++++++++++++++++++++++++-----------
  include/hw/misc/imx7_src.h     |  66 ++++++++
  include/hw/rtc/aspeed_rtc.h    |   2 +-
  include/sysemu/rtc.h           |   4 +-
  target/arm/cpregs.h            |   2 +
  target/arm/cpu.h               |   5 +-
  target/arm/internals.h         |   6 -
  target/arm/tcg/translate.h     |   2 +
  hw/arm/armsse.c                |  16 ++
  hw/arm/armv7m.c                |  21 +++
  hw/arm/fsl-imx6ul.c            | 174 +++++++++++++--------
  hw/arm/fsl-imx7.c              | 201 +++++++++++++++++++-----
  hw/arm/mps2-tz.c               |  29 ++++
  hw/misc/imx7_src.c             | 276 +++++++++++++++++++++++++++++++++
  hw/rtc/aspeed_rtc.c            |   5 +-
  hw/rtc/m48t59.c                |   2 +-
  hw/rtc/twl92230.c              |   4 +-
  softmmu/rtc.c                  |   4 +-
  target/arm/cpu.c               | 207 ++++++++++++++-----------
  target/arm/helper.c            |  15 +-
  target/arm/tcg/cpu32.c         |   2 +-
  target/arm/tcg/cpu64.c         | 102 +++++++++----
  target/arm/tcg/helper-a64.c    |   9 ++
  target/arm/tcg/mte_helper.c    |  90 ++++++++---
  target/arm/tcg/translate-a64.c |   5 +-
  hw/misc/meson.build            |   1 +
  hw/misc/trace-events           |   4 +
 files changed, 1393 insertions(+), 372 deletions(-)
  create mode 100644 include/hw/misc/imx7_src.h
  create mode 100644 hw/misc/imx7_src.c
- docs/system/arm/stm32.rst               |  66 +++++++
- docs/system/target-arm.rst              |   1 +
- default-configs/devices/arm-softmmu.mak |   1 +
- include/hw/arm/stm32f100_soc.h          |  57 ++++++
- hw/arm/stellaris.c                      |  56 +++++-
- hw/arm/stm32f100_soc.c                  | 182 +++++++++++++++++
- hw/arm/stm32vldiscovery.c               |  66 +++++++
- hw/arm/virt.c                           |   3 +
- hw/gpio/pl061.c                         | 341 +++++++++++++++++++++++++-------
- hw/intc/arm_gicv3_cpuif.c               |   4 +-
- hw/intc/arm_gicv3_redist.c              |   4 +-
- target/arm/helper.c                     |  16 +-
- tests/qtest/boot-serial-test.c          |  37 ++++
- MAINTAINERS                             |  13 ++
- hw/arm/Kconfig                          |  10 +
- hw/arm/meson.build                      |   2 +
- hw/gpio/trace-events                    |   9 +
-files changed, 790 insertions(+), 78 deletions(-)
- create mode 100644 docs/system/arm/stm32.rst
- create mode 100644 include/hw/arm/stm32f100_soc.h
- create mode 100644 hw/arm/stm32f100_soc.c
- create mode 100644 hw/arm/stm32vldiscovery.c

-[PULL 15/17] hw/arm/stellaris: Expand comment about handling of OLED chipselect
+[PULL 01/24] target/arm: Reduce dcz_blocksize to uint8_t
-The stellaris board doesn't emulate the handling of the OLED
+From: Richard Henderson <richard.henderson@linaro.org>
 chipselect line correctly.  Expand the comment describing this,
 including a sketch of the theoretical correct way to do it.
+This value is only 4 bits wide.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230811214031.171020-2-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/stellaris.c | 56 +++++++++++++++++++++++++++++++++++++++++++++-
+ target/arm/cpu.h | 3 ++-
-file changed, 55 insertions(+), 1 deletion(-)
+file changed, 2 insertions(+), 1 deletion(-)
-diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/stellaris.c
+--- a/target/arm/cpu.h
-+++ b/hw/arm/stellaris.c
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
+@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
-             DeviceState *sddev;
+     bool prop_lpa2;
-             DeviceState *ssddev;
+     /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
--            /* Some boards have both an OLED controller and SD card connected to
+-    uint32_t dcz_blocksize;
-+            /*
++    uint8_t dcz_blocksize;
-+             * Some boards have both an OLED controller and SD card connected to
++
-              * the same SSI port, with the SD card chip select connected to a
+     uint64_t rvbar_prop; /* Property/input signals.  */
-              * GPIO pin.  Technically the OLED chip select is connected to the
-              * SSI Fss pin.  We do not bother emulating that as both devices
+     /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
               * should never be selected simultaneously, and our OLED controller
               * ignores stray 0xff commands that occur when deselecting the SD
               * card.
 +             *
 +             * The h/w wiring is:
 +             *  - GPIO pin D0 is wired to the active-low SD card chip select
 +             *  - GPIO pin A3 is wired to the active-low OLED chip select
 +             *  - The SoC wiring of the PL061 "auxiliary function" for A3 is
 +             *    SSI0Fss ("frame signal"), which is an output from the SoC's
 +             *    SSI controller. The SSI controller takes SSI0Fss low when it
 +             *    transmits a frame, so it can work as a chip-select signal.
 +             *  - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx
 +             *    (the OLED never sends data to the CPU, so no wiring needed)
 +             *  - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx
 +             *    and the OLED display-data-in
 +             *  - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED
 +             *    serial-clock input
 +             * So a guest that wants to use the OLED can configure the PL061
 +             * to make pins A2, A3, A5 aux-function, so they are connected
 +             * directly to the SSI controller. When the SSI controller sends
 +             * data it asserts SSI0Fss which selects the OLED.
 +             * A guest that wants to use the SD card configures A2, A4 and A5
 +             * as aux-function, but leaves A3 as a software-controlled GPIO
 +             * line. It asserts the SD card chip-select by using the PL061
 +             * to control pin D0, and lets the SSI controller handle Clk, Tx
 +             * and Rx. (The SSI controller asserts Fss during tx cycles as
 +             * usual, but because A3 is not set to aux-function this is not
 +             * forwarded to the OLED, and so the OLED stays unselected.)
 +             *
 +             * The QEMU implementation instead is:
 +             *  - GPIO pin D0 is wired to the active-low SD card chip select,
 +             *    and also to the OLED chip-select which is implemented
 +             *    as *active-high*
 +             *  - SSI controller signals go to the devices regardless of
 +             *    whether the guest programs A2, A4, A5 as aux-function or not
 +             *
 +             * The problem with this implementation is if the guest doesn't
 +             * care about the SD card and only uses the OLED. In that case it
 +             * may choose never to do anything with D0 (leaving it in its
 +             * default floating state, which reliably leaves the card disabled
 +             * because an SD card has a pullup on CS within the card itself),
 +             * and only set up A2, A3, A5. This for us would mean the OLED
 +             * never gets the chip-select assert it needs. We work around
 +             * this with a manual raise of D0 here (despite board creation
 +             * code being the wrong place to raise IRQ lines) to put the OLED
 +             * into an initially selected state.
 +             *
 +             * In theory the right way to model this would be:
 +             *  - Implement aux-function support in the PL061, with an
 +             *    extra set of AFIN and AFOUT GPIO lines (set up so that
 +             *    if a GPIO line is in auxfn mode the main GPIO in and out
 +             *    track the AFIN and AFOUT lines)
 +             *  - Wire the AFOUT for D0 up to either a line from the
 +             *    SSI controller that's pulled low around every transmit,
 +             *    or at least to an always-0 line here on the board
 +             *  - Make the ssd0323 OLED controller chipselect active-low
               */
              bus = qdev_get_child_bus(dev, "ssi");
 --
-.20.1
+.34.1

-[PULL 13/17] hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset
+[PULL 02/24] target/arm: Allow cpu to configure GM blocksize
-The PL061 comes out of reset with all its lines configured as input,
+From: Richard Henderson <richard.henderson@linaro.org>
-which means they might need to be pulled to 0 or 1 depending on the
-'pullups' and 'pulldowns' properties.  Currently we do not assert
+Previously we hard-coded the blocksize with GMID_EL1_BS.
-these lines on reset; they will only be set whenever the guest first
+But the value we choose for -cpu max does not match the
-touches a register that triggers a call to pl061_update().
+value that cortex-a710 uses.
-Convert the device to three-phase reset so we have a place where we
+Mirror the way we handle dcz_blocksize.
-can safely call qemu_set_irq() to set the floating lines to their
-correct values.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230811214031.171020-3-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- hw/gpio/pl061.c      | 29 +++++++++++++++++++++++++----
+ target/arm/cpu.h               |  2 ++
- hw/gpio/trace-events |  1 +
+ target/arm/internals.h         |  6 -----
-files changed, 26 insertions(+), 4 deletions(-)
+ target/arm/tcg/translate.h     |  2 ++
+ target/arm/helper.c            | 11 +++++---
-diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
+ target/arm/tcg/cpu64.c         |  1 +
-index XXXXXXX..XXXXXXX 100644
+ target/arm/tcg/mte_helper.c    | 46 ++++++++++++++++++++++------------
---- a/hw/gpio/pl061.c
+ target/arm/tcg/translate-a64.c |  5 ++--
-+++ b/hw/gpio/pl061.c
+files changed, 45 insertions(+), 28 deletions(-)
-@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,
-     return;
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
      /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
      uint8_t dcz_blocksize;
 +    /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */
 +    uint8_t gm_blocksize;
      uint64_t rvbar_prop; /* Property/input signals.  */
 diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/internals.h
 +++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs);
  #endif /* !CONFIG_USER_ONLY */
 -/*
 - * The log2 of the words in the tag block, for GMID_EL1.BS.
 - * The is the maximum, 256 bytes, which manipulates 64-bits of tags.
 - */
 -#define GMID_EL1_BS  6
 -
  /*
   * SVE predicates are 1/8 the size of SVE vectors, and cannot use
   * the same simd_desc() encoding due to restrictions on size.
 diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/translate.h
 +++ b/target/arm/tcg/translate.h
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
      int8_t btype;
      /* A copy of cpu->dcz_blocksize. */
      uint8_t dcz_blocksize;
 +    /* A copy of cpu->gm_blocksize. */
 +    uint8_t gm_blocksize;
      /* True if this page is guarded.  */
      bool guarded_page;
      /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
        .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6,
        .access = PL1_RW, .accessfn = access_mte,
        .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) },
 -    { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
 -      .access = PL1_R, .accessfn = access_aa64_tid5,
 -      .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS },
      { .name = "TCO", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
        .type = ARM_CP_NO_RAW,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
       * then define only a RAZ/WI version of PSTATE.TCO.
       */
      if (cpu_isar_feature(aa64_mte, cpu)) {
 +        ARMCPRegInfo gmid_reginfo = {
 +            .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
 +            .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
 +            .access = PL1_R, .accessfn = access_aa64_tid5,
 +            .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize,
 +        };
 +        define_one_arm_cp_reg(cpu, &gmid_reginfo);
          define_arm_cp_regs(cpu, mte_reginfo);
          define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
      } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) {
 diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/cpu64.c
 +++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
      cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
      cpu->dcz_blocksize = 7; /*  512 bytes */
  #endif
 +    cpu->gm_blocksize = 6;  /*  256 bytes */
      cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
      cpu->sme_vq.supported = SVE_VQ_POW2_MAP;
 diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/mte_helper.c
 +++ b/target/arm/tcg/mte_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr)
      }
  }
--static void pl061_reset(DeviceState *dev)
+-#define LDGM_STGM_SIZE  (4 << GMID_EL1_BS)
-+static void pl061_enter_reset(Object *obj, ResetType type)
+-
  uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
  {
--    PL061State *s = PL061(dev);
+     int mmu_idx = cpu_mmu_index(env, false);
-+    PL061State *s = PL061(obj);
+     uintptr_t ra = GETPC();
-+
++    int gm_bs = env_archcpu(env)->gm_blocksize;
-+    trace_pl061_reset(DEVICE(s)->canonical_path);
++    int gm_bs_bytes = 4 << gm_bs;
+     void *tag_mem;
-     /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */
-     s->data = 0;
+-    ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
--    s->old_out_data = 0;
++    ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
-     s->old_in_data = 0;
-     s->dir = 0;
+     /* Trap if accessing an invalid page.  */
-     s->isense = 0;
+     tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD,
-@@ -XXX,XX +XXX,XX @@ static void pl061_reset(DeviceState *dev)
+-                                 LDGM_STGM_SIZE, MMU_DATA_LOAD,
-     s->amsel = 0;
+-                                 LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
 +                                 gm_bs_bytes, MMU_DATA_LOAD,
 +                                 gm_bs_bytes / (2 * TAG_GRANULE), ra);
      /* The tag is squashed to zero if the page does not support tags.  */
      if (!tag_mem) {
          return 0;
      }
 -    QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
      /*
 -     * We are loading 64-bits worth of tags.  The ordering of elements
 -     * within the word corresponds to a 64-bit little-endian operation.
 +     * The ordering of elements within the word corresponds to
 +     * a little-endian operation.
       */
 -    return ldq_le_p(tag_mem);
 +    switch (gm_bs) {
 +    case 6:
 +        /* 256 bytes -> 16 tags -> 64 result bits */
 +        return ldq_le_p(tag_mem);
 +    default:
 +        /* cpu configured with unsupported gm blocksize. */
 +        g_assert_not_reached();
 +    }
  }
-+static void pl061_hold_reset(Object *obj)
+ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
-+{
+ {
-+    PL061State *s = PL061(obj);
+     int mmu_idx = cpu_mmu_index(env, false);
-+    int i, level;
+     uintptr_t ra = GETPC();
-+    uint8_t floating = pl061_floating(s);
++    int gm_bs = env_archcpu(env)->gm_blocksize;
-+    uint8_t pullups = pl061_pullups(s);
++    int gm_bs_bytes = 4 << gm_bs;
-+
+     void *tag_mem;
-+    for (i = 0; i < N_GPIOS; i++) {
-+        if (extract32(floating, i, 1)) {
+-    ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
-+            continue;
++    ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
-+        }
-+        level = extract32(pullups, i, 1);
+     /* Trap if accessing an invalid page.  */
-+        trace_pl061_set_output(DEVICE(s)->canonical_path, i, level);
+     tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE,
-+        qemu_set_irq(s->out[i], level);
+-                                 LDGM_STGM_SIZE, MMU_DATA_LOAD,
 -                                 LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
 +                                 gm_bs_bytes, MMU_DATA_LOAD,
 +                                 gm_bs_bytes / (2 * TAG_GRANULE), ra);
      /*
       * Tag store only happens if the page support tags,
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
          return;
      }
 -    QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
      /*
 -     * We are storing 64-bits worth of tags.  The ordering of elements
 -     * within the word corresponds to a 64-bit little-endian operation.
 +     * The ordering of elements within the word corresponds to
 +     * a little-endian operation.
       */
 -    stq_le_p(tag_mem, val);
 +    switch (gm_bs) {
 +    case 6:
 +        stq_le_p(tag_mem, val);
 +        break;
 +    default:
 +        /* cpu configured with unsupported gm blocksize. */
 +        g_assert_not_reached();
 +    }
-+    s->old_out_data = pullups;
-+}
-+
- static void pl061_set_irq(void * opaque, int irq, int level)
- {
-     PL061State *s = (PL061State *)opaque;
-@@ -XXX,XX +XXX,XX @@ static Property pl061_props[] = {
- static void pl061_class_init(ObjectClass *klass, void *data)
- {
-     DeviceClass *dc = DEVICE_CLASS(klass);
-+    ResettableClass *rc = RESETTABLE_CLASS(klass);
-     dc->vmsd = &vmstate_pl061;
--    dc->reset = &pl061_reset;
-     dc->realize = pl061_realize;
-     device_class_set_props(dc, pl061_props);
-+    rc->phases.enter = pl061_enter_reset;
-+    rc->phases.hold = pl061_hold_reset;
  }
- static const TypeInfo pl061_info = {
+ void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val)
-diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
+diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/gpio/trace-events
+--- a/target/arm/tcg/translate-a64.c
-+++ b/hw/gpio/trace-events
++++ b/target/arm/tcg/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to
+@@ -XXX,XX +XXX,XX @@ static bool trans_STGM(DisasContext *s, arg_ldst_tag *a)
- pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
+         gen_helper_stgm(cpu_env, addr, tcg_rt);
- pl061_read(const char *id, uint64_t offset, uint64_t r) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
+     } else {
- pl061_write(const char *id, uint64_t offset, uint64_t value) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
+         MMUAccessType acc = MMU_DATA_STORE;
-+pl061_reset(const char *id) "%s reset"
+-        int size = 4 << GMID_EL1_BS;
++        int size = 4 << s->gm_blocksize;
- # sifive_gpio.c
- sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
+         clean_addr = clean_data_tbi(s, addr);
          tcg_gen_andi_i64(clean_addr, clean_addr, -size);
@@ -XXX,XX +XXX,XX @@ static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a)
          gen_helper_ldgm(tcg_rt, cpu_env, addr);
      } else {
          MMUAccessType acc = MMU_DATA_LOAD;
 -        int size = 4 << GMID_EL1_BS;
 +        int size = 4 << s->gm_blocksize;
          clean_addr = clean_data_tbi(s, addr);
          tcg_gen_andi_i64(clean_addr, clean_addr, -size);
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
      dc->cp_regs = arm_cpu->cp_regs;
      dc->features = env->features;
      dc->dcz_blocksize = arm_cpu->dcz_blocksize;
 +    dc->gm_blocksize = arm_cpu->gm_blocksize;
  #ifdef CONFIG_USER_ONLY
      /* In sve_probe_page, we assume TBI is enabled. */
 --
-.20.1
+.34.1

-New patch
+[PULL 03/24] target/arm: Support more GM blocksizes
+From: Richard Henderson <richard.henderson@linaro.org>
+Support all of the easy GM block sizes.
+Use direct memory operations, since the pointers are aligned.
+While BS=2 (16 bytes, 1 tag) is a legal setting, that requires
+an atomic store of one nibble.  This is not difficult, but there
+is also no point in supporting it until required.
+Note that cortex-a710 sets GM blocksize to match its cacheline
+size of 64 bytes.  I expect many implementations will also
+match the cacheline, which makes 16 bytes very unlikely.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-4-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.c            | 18 +++++++++---
+ target/arm/tcg/mte_helper.c | 56 +++++++++++++++++++++++++++++++------
+files changed, 62 insertions(+), 12 deletions(-)
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.c
++++ b/target/arm/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
+                                        ID_PFR1, VIRTUALIZATION, 0);
+     }
++    if (cpu_isar_feature(aa64_mte, cpu)) {
++        /*
++         * The architectural range of GM blocksize is 2-6, however qemu
++         * doesn't support blocksize of 2 (see HELPER(ldgm)).
++         */
++        if (tcg_enabled()) {
++            assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6);
++        }
++
+ #ifndef CONFIG_USER_ONLY
+-    if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) {
+         /*
+          * Disable the MTE feature bits if we do not have tag-memory
+          * provided by the machine.
+          */
+-        cpu->isar.id_aa64pfr1 =
+-            FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
+-    }
++        if (cpu->tag_memory == NULL) {
++            cpu->isar.id_aa64pfr1 =
++                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
++        }
+ #endif
++    }
+     if (tcg_enabled()) {
+         /*
+diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/mte_helper.c
++++ b/target/arm/tcg/mte_helper.c
+@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
+     int gm_bs = env_archcpu(env)->gm_blocksize;
+     int gm_bs_bytes = 4 << gm_bs;
+     void *tag_mem;
++    uint64_t ret;
++    int shift;
+     ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
+@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
+     /*
+      * The ordering of elements within the word corresponds to
+-     * a little-endian operation.
++     * a little-endian operation.  Computation of shift comes from
++     *
++     *     index = address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE>
++     *     data<index*4+3:index*4> = tag
++     *
++     * Because of the alignment of ptr above, BS=6 has shift=0.
++     * All memory operations are aligned.  Defer support for BS=2,
++     * requiring insertion or extraction of a nibble, until we
++     * support a cpu that requires it.
+      */
+     switch (gm_bs) {
++    case 3:
++        /* 32 bytes -> 2 tags -> 8 result bits */
++        ret = *(uint8_t *)tag_mem;
++        break;
++    case 4:
++        /* 64 bytes -> 4 tags -> 16 result bits */
++        ret = cpu_to_le16(*(uint16_t *)tag_mem);
++        break;
++    case 5:
++        /* 128 bytes -> 8 tags -> 32 result bits */
++        ret = cpu_to_le32(*(uint32_t *)tag_mem);
++        break;
+     case 6:
+         /* 256 bytes -> 16 tags -> 64 result bits */
+-        return ldq_le_p(tag_mem);
++        return cpu_to_le64(*(uint64_t *)tag_mem);
+     default:
+-        /* cpu configured with unsupported gm blocksize. */
++        /*
++         * CPU configured with unsupported/invalid gm blocksize.
++         * This is detected early in arm_cpu_realizefn.
++         */
+         g_assert_not_reached();
+     }
++    shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
++    return ret << shift;
+ }
+ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
+@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
+     int gm_bs = env_archcpu(env)->gm_blocksize;
+     int gm_bs_bytes = 4 << gm_bs;
+     void *tag_mem;
++    int shift;
+     ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
+@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
+         return;
+     }
+-    /*
+-     * The ordering of elements within the word corresponds to
+-     * a little-endian operation.
+-     */
++    /* See LDGM for comments on BS and on shift.  */
++    shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
++    val >>= shift;
+     switch (gm_bs) {
++    case 3:
++        /* 32 bytes -> 2 tags -> 8 result bits */
++        *(uint8_t *)tag_mem = val;
++        break;
++    case 4:
++        /* 64 bytes -> 4 tags -> 16 result bits */
++        *(uint16_t *)tag_mem = cpu_to_le16(val);
++        break;
++    case 5:
++        /* 128 bytes -> 8 tags -> 32 result bits */
++        *(uint32_t *)tag_mem = cpu_to_le32(val);
++        break;
+     case 6:
+-        stq_le_p(tag_mem, val);
++        /* 256 bytes -> 16 tags -> 64 result bits */
++        *(uint64_t *)tag_mem = cpu_to_le64(val);
+         break;
+     default:
+         /* cpu configured with unsupported gm blocksize. */
+--
+.34.1

-New patch
+[PULL 04/24] target/arm: When tag memory is not present, set MTE=1
+From: Richard Henderson <richard.henderson@linaro.org>
+When the cpu support MTE, but the system does not, reduce cpu
+support to user instructions at EL0 instead of completely
+disabling MTE.  If we encounter a cpu implementation which does
+something else, we can revisit this setting.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-5-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.c | 7 ++++---
+file changed, 4 insertions(+), 3 deletions(-)
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.c
++++ b/target/arm/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
+ #ifndef CONFIG_USER_ONLY
+         /*
+-         * Disable the MTE feature bits if we do not have tag-memory
+-         * provided by the machine.
++         * If we do not have tag-memory provided by the machine,
++         * reduce MTE support to instructions enabled at EL0.
++         * This matches Cortex-A710 BROADCASTMTE input being LOW.
+          */
+         if (cpu->tag_memory == NULL) {
+             cpu->isar.id_aa64pfr1 =
+-                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
++                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
+         }
+ #endif
+     }
+--
+.34.1

-[PULL 02/17] stm32vldiscovery: Add the STM32VLDISCOVERY Machine
+[PULL 05/24] target/arm: Introduce make_ccsidr64
-From: Alexandre Iooss <erdnaxe@crans.org>
+From: Richard Henderson <richard.henderson@linaro.org>
-This is a Cortex-M3 based machine. Information can be found at:
+Do not hard-code the constants for Neoverse V1.
 https://www.st.com/en/evaluation-tools/stm32vldiscovery.html
-Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20210617165647.2575955-3-erdnaxe@crans.org
+Message-id: 20230811214031.171020-6-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- default-configs/devices/arm-softmmu.mak |  1 +
+ target/arm/tcg/cpu64.c | 48 ++++++++++++++++++++++++++++--------------
- hw/arm/stm32vldiscovery.c               | 66 +++++++++++++++++++++++++
+file changed, 32 insertions(+), 16 deletions(-)
  MAINTAINERS                             |  6 +++
  hw/arm/Kconfig                          |  4 ++
  hw/arm/meson.build                      |  1 +
 files changed, 78 insertions(+)
  create mode 100644 hw/arm/stm32vldiscovery.c
-diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
 index XXXXXXX..XXXXXXX 100644
---- a/default-configs/devices/arm-softmmu.mak
+--- a/target/arm/tcg/cpu64.c
-+++ b/default-configs/devices/arm-softmmu.mak
++++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ CONFIG_CHEETAH=y
  CONFIG_SX1=y
  CONFIG_NSERIES=y
  CONFIG_STELLARIS=y
 +CONFIG_STM32VLDISCOVERY=y
  CONFIG_REALVIEW=y
  CONFIG_VERSATILE=y
  CONFIG_VEXPRESS=y
 diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/arm/stm32vldiscovery.c
 @@ -XXX,XX +XXX,XX @@
-+/*
+ #include "qemu/module.h"
-+ * ST STM32VLDISCOVERY machine
+ #include "qapi/visitor.h"
-+ *
+ #include "hw/qdev-properties.h"
-+ * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
++#include "qemu/units.h"
-+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ #include "internals.h"
-+ *
+ #include "cpregs.h"
-+ * Permission is hereby granted, free of charge, to any person obtaining a copy
-+ * of this software and associated documentation files (the "Software"), to deal
++static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize,
-+ * in the Software without restriction, including without limitation the rights
++                              unsigned cachesize)
 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 + * copies of the Software, and to permit persons to whom the Software is
 + * furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice shall be included in
 + * all copies or substantial portions of the Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qapi/error.h"
 +#include "hw/boards.h"
 +#include "hw/qdev-properties.h"
 +#include "qemu/error-report.h"
 +#include "hw/arm/stm32f100_soc.h"
 +#include "hw/arm/boot.h"
 +
 +/* stm32vldiscovery implementation is derived from netduinoplus2 */
 +
 +/* Main SYSCLK frequency in Hz (24MHz) */
 +#define SYSCLK_FRQ 24000000ULL
 +
 +static void stm32vldiscovery_init(MachineState *machine)
 +{
-+    DeviceState *dev;
++    unsigned lg_linesize = ctz32(linesize);
 +    unsigned sets;
 +
 +    /*
-+     * TODO: ideally we would model the SoC RCC and let it handle
++     * The 64-bit CCSIDR_EL1 format is:
-+     * system_clock_scale, including its ability to define different
++     *   [55:32] number of sets - 1
-+     * possible SYSCLK sources.
++     *   [23:3]  associativity - 1
 +     *   [2:0]   log2(linesize) - 4
 +     *           so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
 +     */
-+    system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
++    assert(assoc != 0);
 +    assert(is_power_of_2(linesize));
 +    assert(lg_linesize >= 4 && lg_linesize <= 7 + 4);
 +
-+    dev = qdev_new(TYPE_STM32F100_SOC);
++    /* sets * associativity * linesize == cachesize. */
-+    qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
++    sets = cachesize / (assoc * linesize);
-+    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
++    assert(cachesize % (assoc * linesize) == 0);
 +
-+    armv7m_load_kernel(ARM_CPU(first_cpu),
++    return ((uint64_t)(sets - 1) << 32)
-+                       machine->kernel_filename,
++         | ((assoc - 1) << 3)
-+                       FLASH_SIZE);
++         | (lg_linesize - 4);
 +}
 +
-+static void stm32vldiscovery_machine_init(MachineClass *mc)
+ static void aarch64_a35_initfn(Object *obj)
-+{
+ {
-+    mc->desc = "ST STM32VLDISCOVERY (Cortex-M3)";
+     ARMCPU *cpu = ARM_CPU(obj);
-+    mc->init = stm32vldiscovery_init;
+@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj)
-+}
+      * The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values,
-+
+      * but also says it implements CCIDX, which means they should be
-+DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init)
+      * 64-bit format. So we here use values which are based on the textual
-+
+-     * information in chapter 2 of the TRM (and on the fact that
-diff --git a/MAINTAINERS b/MAINTAINERS
+-     * sets * associativity * linesize == cachesize).
-index XXXXXXX..XXXXXXX 100644
+-     *
---- a/MAINTAINERS
+-     * The 64-bit CCSIDR_EL1 format is:
-+++ b/MAINTAINERS
+-     *   [55:32] number of sets - 1
-@@ -XXX,XX +XXX,XX @@ F: hw/*/stellaris*
+-     *   [23:3]  associativity - 1
- F: include/hw/input/gamepad.h
+-     *   [2:0]   log2(linesize) - 4
- F: docs/system/arm/stellaris.rst
+-     *           so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
+-     *
-+STM32VLDISCOVERY
+-     * L1: 4-way set associative 64-byte line size, total size 64K,
-+M: Alexandre Iooss <erdnaxe@crans.org>
+-     * so sets is 256.
-+L: qemu-arm@nongnu.org
++     * information in chapter 2 of the TRM:
-+S: Maintained
+      *
-+F: hw/arm/stm32vldiscovery.c
++     * L1: 4-way set associative 64-byte line size, total size 64K.
-+
+      * L2: 8-way set associative, 64 byte line size, either 512K or 1MB.
- Versatile Express
+-     * We pick 1MB, so this has 2048 sets.
- M: Peter Maydell <peter.maydell@linaro.org>
+-     *
- L: qemu-arm@nongnu.org
+      * L3: No L3 (this matches the CLIDR_EL1 value).
-diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
+      */
-index XXXXXXX..XXXXXXX 100644
+-    cpu->ccsidr[0] = 0x000000ff0000001aull; /* 64KB L1 dcache */
---- a/hw/arm/Kconfig
+-    cpu->ccsidr[1] = 0x000000ff0000001aull; /* 64KB L1 icache */
-+++ b/hw/arm/Kconfig
+-    cpu->ccsidr[2] = 0x000007ff0000003aull; /* 1MB L2 cache */
-@@ -XXX,XX +XXX,XX @@ config STELLARIS
++    cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */
-     select STELLARIS_ENET # ethernet
++    cpu->ccsidr[1] = cpu->ccsidr[0];                 /* L1 icache */
-     select UNIMP
++    cpu->ccsidr[2] = make_ccsidr64(8, 64, 1 * MiB);  /* L2 cache */
-+config STM32VLDISCOVERY
+     /* From 3.2.115 SCTLR_EL3 */
-+    bool
+     cpu->reset_sctlr = 0x30c50838;
 +    select STM32F100_SOC
 +
  config STRONGARM
      bool
      select PXA2XX
 diff --git a/hw/arm/meson.build b/hw/arm/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/meson.build
 +++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c'))
  arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
  arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
  arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
 +arm_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c'))
  arm_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c'))
  arm_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c'))
  arm_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c'))
 --
-.20.1
+.34.1

-[PULL 16/17] target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint
+[PULL 06/24] target/arm: Apply access checks to neoverse-n1 special registers
-From: "hnick@vmware.com" <hnick@vmware.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Signed-off-by: Nick Hudson <hnick@vmware.com>
+Access to many of the special registers is enabled or disabled
 by ACTLR_EL[23], which we implement as constant 0, which means
 that all writes outside EL3 should trap.
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-7-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 16 +++++++++++++---
+ target/arm/cpregs.h    |  2 ++
-file changed, 13 insertions(+), 3 deletions(-)
+ target/arm/helper.c    |  4 ++--
  target/arm/tcg/cpu64.c | 46 +++++++++++++++++++++++++++++++++---------
 files changed, 41 insertions(+), 11 deletions(-)
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpregs.h
++++ b/target/arm/cpregs.h
+@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
+ void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
+ #endif
++CPAccessResult access_tvm_trvm(CPUARMState *, const ARMCPRegInfo *, bool);
++
+ #endif /* TARGET_ARM_CPREGS_H */
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
+@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
-       .access = PL1_RW, .accessfn = access_tda,
+ }
-       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
-       .resetvalue = 0 },
+ /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM.  */
--    /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
+-static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
-+    /*
+-                                      bool isread)
-+     * MDCCSR_EL0[30:29] map to EDSCR[30:29].  Simply RAZ as the external
++CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
-+     * Debug Communication Channel is not implemented.
++                               bool isread)
-+     */
+ {
-+    { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64,
+     if (arm_current_el(env) == 1) {
-+      .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
+         uint64_t trap = isread ? HCR_TRVM : HCR_TVM;
-+      .access = PL0_R, .accessfn = access_tda,
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
-+      .type = ARM_CP_CONST, .resetvalue = 0 },
+index XXXXXXX..XXXXXXX 100644
-+    /*
+--- a/target/arm/tcg/cpu64.c
-+     * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2].  Map all bits as
++++ b/target/arm/tcg/cpu64.c
-+     * it is unlikely a guest will care.
+@@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj)
-      * We don't implement the configurable EL0 access.
+     /* TODO:  Add A64FX specific HPC extension registers */
-      */
+ }
--    { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
--      .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
++static CPAccessResult access_actlr_w(CPUARMState *env, const ARMCPRegInfo *r,
-+    { .name = "DBGDSCRint", .state = ARM_CP_STATE_AA32,
++                                     bool read)
-+      .cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
++{
-       .type = ARM_CP_ALIAS,
++    if (!read) {
-       .access = PL1_R, .accessfn = access_tda,
++        int el = arm_current_el(env);
-       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
++
 +        /* Because ACTLR_EL2 is constant 0, writes below EL2 trap to EL2. */
 +        if (el < 2 && arm_is_el2_enabled(env)) {
 +            return CP_ACCESS_TRAP_EL2;
 +        }
 +        /* Because ACTLR_EL3 is constant 0, writes below EL3 trap to EL3. */
 +        if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) {
 +            return CP_ACCESS_TRAP_EL3;
 +        }
 +    }
 +    return CP_ACCESS_OK;
 +}
 +
  static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
      { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 +      /* Traps and enables are the same as for TCR_EL1. */
 +      .accessfn = access_tvm_trvm, .fgt = FGT_TCR_EL1, },
      { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
        .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
        .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
      { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 +      .accessfn = access_actlr_w },
      { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 +      .accessfn = access_actlr_w },
      { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 +      .accessfn = access_actlr_w },
      /*
       * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
       * (and in particular its system registers).
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
        .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
      { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 },
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010,
 +      .accessfn = access_actlr_w },
      { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1,
        .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
        .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
      { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 +      .accessfn = access_actlr_w },
      { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 +      .accessfn = access_actlr_w },
      { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 +      .accessfn = access_actlr_w },
      { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 +      .accessfn = access_actlr_w },
  };
  static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
 --
-.20.1
+.34.1

-New patch
+[PULL 07/24] target/arm: Apply access checks to neoverse-v1 special registers
+From: Richard Henderson <richard.henderson@linaro.org>
+There is only one additional EL1 register modeled, which
+also needs to use access_actlr_w.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-8-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/tcg/cpu64.c | 3 ++-
+file changed, 2 insertions(+), 1 deletion(-)
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/cpu64.c
++++ b/target/arm/tcg/cpu64.c
+@@ -XXX,XX +XXX,XX @@ static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
+ static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = {
+     { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
++      .accessfn = access_actlr_w },
+     { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0,
+       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+--
+.34.1

-New patch
+[PULL 08/24] target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)
+From: Richard Henderson <richard.henderson@linaro.org>
+Like FEAT_TRF (Self-hosted Trace Extension), suppress tracing
+external to the cpu, which is out of scope for QEMU.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-10-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.c | 3 +++
+file changed, 3 insertions(+)
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.c
++++ b/target/arm/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
+         /* FEAT_SPE (Statistical Profiling Extension) */
+         cpu->isar.id_aa64dfr0 =
+             FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
++        /* FEAT_TRBE (Trace Buffer Extension) */
++        cpu->isar.id_aa64dfr0 =
++            FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0);
+         /* FEAT_TRF (Self-hosted Trace Extension) */
+         cpu->isar.id_aa64dfr0 =
+             FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0);
+--
+.34.1

-New patch
+[PULL 09/24] target/arm: Implement FEAT_HPDS2 as a no-op
+From: Richard Henderson <richard.henderson@linaro.org>
+This feature allows the operating system to set TCR_ELx.HWU*
+to allow the implementation to use the PBHA bits from the
+block and page descriptors for for IMPLEMENTATION DEFINED
+purposes.  Since QEMU has no need to use these bits, we may
+simply ignore them.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-11-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ docs/system/arm/emulation.rst | 1 +
+ target/arm/tcg/cpu32.c        | 2 +-
+ target/arm/tcg/cpu64.c        | 2 +-
+files changed, 3 insertions(+), 2 deletions(-)
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
+index XXXXXXX..XXXXXXX 100644
+--- a/docs/system/arm/emulation.rst
++++ b/docs/system/arm/emulation.rst
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
+ - FEAT_HAFDBS (Hardware management of the access flag and dirty bit state)
+ - FEAT_HCX (Support for the HCRX_EL2 register)
+ - FEAT_HPDS (Hierarchical permission disables)
++- FEAT_HPDS2 (Translation table page-based hardware attributes)
+ - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
+ - FEAT_IDST (ID space trap handling)
+ - FEAT_IESB (Implicit error synchronization event)
+diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/cpu32.c
++++ b/target/arm/tcg/cpu32.c
+@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
+     cpu->isar.id_mmfr3 = t;
+     t = cpu->isar.id_mmfr4;
+-    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1);         /* FEAT_AA32HPD */
++    t = FIELD_DP32(t, ID_MMFR4, HPDS, 2);         /* FEAT_HPDS2 */
+     t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
+     t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
+     t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX */
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/cpu64.c
++++ b/target/arm/tcg/cpu64.c
+@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
+     t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2);   /* FEAT_HAFDBS */
+     t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
+     t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);       /* FEAT_VHE */
+-    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1);     /* FEAT_HPDS */
++    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2);     /* FEAT_HPDS2 */
+     t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
+     t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3);      /* FEAT_PAN3 */
+     t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
+--
+.34.1

-[PULL 03/17] docs/system: arm: Add stm32 boards description
+[PULL 10/24] target/arm: properly document FEAT_CRC32
-From: Alexandre Iooss <erdnaxe@crans.org>
+From: Alex Bennée <alex.bennee@linaro.org>
-This adds the target guide for Netduino 2, Netduino Plus 2 and STM32VLDISCOVERY.
+This is a mandatory feature for Armv8.1 architectures but we don't
 state the feature clearly in our emulation list. Also include
 FEAT_CRC32 comment in aarch64_max_tcg_initfn for ease of grepping.
-Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Message-id: 20210617165647.2575955-4-erdnaxe@crans.org
+Message-id: 20230824075406.1515566-1-alex.bennee@linaro.org
 Cc: qemu-stable@nongnu.org
 Message-Id: <20230222110104.3996971-1-alex.bennee@linaro.org>
 [PMM: pluralize 'instructions' in docs]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- docs/system/arm/stm32.rst  | 66 ++++++++++++++++++++++++++++++++++++++
+ docs/system/arm/emulation.rst | 1 +
- docs/system/target-arm.rst |  1 +
+ target/arm/tcg/cpu64.c        | 2 +-
- MAINTAINERS                |  1 +
+files changed, 2 insertions(+), 1 deletion(-)
 files changed, 68 insertions(+)
  create mode 100644 docs/system/arm/stm32.rst
-diff --git a/docs/system/arm/stm32.rst b/docs/system/arm/stm32.rst
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/docs/system/arm/stm32.rst
@@ -XXX,XX +XXX,XX @@
 +STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``stm32vldiscovery``)
 +========================================================================================
 +
 +The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by
 +STMicroelectronics.
 +
 +.. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html
 +
 +The STM32F1 series is based on ARM Cortex-M3 core. The following machines are
 +based on this chip :
 +
 +- ``stm32vldiscovery``  STM32VLDISCOVERY board with STM32F100RBT6 microcontroller
 +
 +The STM32F2 series is based on ARM Cortex-M3 core. The following machines are
 +based on this chip :
 +
 +- ``netduino2``         Netduino 2 board with STM32F205RFT6 microcontroller
 +
 +The STM32F4 series is based on ARM Cortex-M4F core. This series is pin-to-pin
 +compatible with STM32F2 series. The following machines are based on this chip :
 +
 +- ``netduinoplus2``     Netduino Plus 2 board with STM32F405RGT6 microcontroller
 +
 +There are many other STM32 series that are currently not supported by QEMU.
 +
 +Supported devices
 +-----------------
 +
 + * ARM Cortex-M3, Cortex M4F
 + * Analog to Digital Converter (ADC)
 + * EXTI interrupt
 + * Serial ports (USART)
 + * SPI controller
 + * System configuration (SYSCFG)
 + * Timer controller (TIMER)
 +
 +Missing devices
 +---------------
 +
 + * Camera interface (DCMI)
 + * Controller Area Network (CAN)
 + * Cycle Redundancy Check (CRC) calculation unit
 + * Digital to Analog Converter (DAC)
 + * DMA controller
 + * Ethernet controller
 + * Flash Interface Unit
 + * GPIO controller
 + * I2C controller
 + * Inter-Integrated Sound (I2S) controller
 + * Power supply configuration (PWR)
 + * Random Number Generator (RNG)
 + * Real-Time Clock (RTC) controller
 + * Reset and Clock Controller (RCC)
 + * Secure Digital Input/Output (SDIO) interface
 + * USB OTG
 + * Watchdog controller (IWDG, WWDG)
 +
 +Boot options
 +------------
 +
 +The STM32 machines can be started using the ``-kernel`` option to load a
 +firmware. Example:
 +
 +.. code-block:: bash
 +
 +  $ qemu-system-arm -M stm32vldiscovery -kernel firmware.bin
 diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/target-arm.rst
+--- a/docs/system/arm/emulation.rst
-+++ b/docs/system/target-arm.rst
++++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
-    arm/collie
+ - FEAT_BBM at level 2 (Translation table break-before-make levels)
-    arm/sx1
+ - FEAT_BF16 (AArch64 BFloat16 instructions)
-    arm/stellaris
+ - FEAT_BTI (Branch Target Identification)
-+   arm/stm32
++- FEAT_CRC32 (CRC32 instructions)
-    arm/virt
+ - FEAT_CSV2 (Cache speculation variant 2)
-    arm/xlnx-versal-virt
+ - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
+ - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
-diff --git a/MAINTAINERS b/MAINTAINERS
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
 index XXXXXXX..XXXXXXX 100644
---- a/MAINTAINERS
+--- a/target/arm/tcg/cpu64.c
-+++ b/MAINTAINERS
++++ b/target/arm/tcg/cpu64.c
-@@ -XXX,XX +XXX,XX @@ M: Alexandre Iooss <erdnaxe@crans.org>
+@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
- L: qemu-arm@nongnu.org
+     t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2);      /* FEAT_PMULL */
- S: Maintained
+     t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);     /* FEAT_SHA1 */
- F: hw/arm/stm32vldiscovery.c
+     t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2);     /* FEAT_SHA512 */
-+F: docs/system/arm/stm32.rst
+-    t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
++    t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);    /* FEAT_CRC32 */
- Versatile Express
+     t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);   /* FEAT_LSE */
- M: Peter Maydell <peter.maydell@linaro.org>
+     t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);      /* FEAT_RDM */
      t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);     /* FEAT_SHA3 */
 --
-.20.1
+.34.1

-New patch
+[PULL 11/24] Remove i.MX7 IOMUX GPR device from i.MX6UL
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
+i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device.
+In particular, register 22 is not present on i.MX6UL and this is actualy
+The only register that is really emulated in the i.MX7 IOMUX GPR device.
+Note: The i.MX6UL code is actually also implementing the IOMUX GPR device
+as an unimplemented device at the same bus adress and the 2 instantiations
+were actualy colliding. So we go back to the unimplemented device for now.
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
+Message-id: 48681bf51ee97646479bb261bee19abebbc8074e.1692964892.git.jcd@tribudubois.net
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/fsl-imx6ul.h |  2 --
+ hw/arm/fsl-imx6ul.c         | 11 -----------
+files changed, 13 deletions(-)
+diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/fsl-imx6ul.h
++++ b/include/hw/arm/fsl-imx6ul.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/misc/imx6ul_ccm.h"
+ #include "hw/misc/imx6_src.h"
+ #include "hw/misc/imx7_snvs.h"
+-#include "hw/misc/imx7_gpr.h"
+ #include "hw/intc/imx_gpcv2.h"
+ #include "hw/watchdog/wdt_imx2.h"
+ #include "hw/gpio/imx_gpio.h"
+@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
+     IMX6SRCState       src;
+     IMX7SNVSState      snvs;
+     IMXGPCv2State      gpcv2;
+-    IMX7GPRState       gpr;
+     IMXSPIState        spi[FSL_IMX6UL_NUM_ECSPIS];
+     IMXI2CState        i2c[FSL_IMX6UL_NUM_I2CS];
+     IMXSerialState     uart[FSL_IMX6UL_NUM_UARTS];
+diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/fsl-imx6ul.c
++++ b/hw/arm/fsl-imx6ul.c
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+      */
+     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
+-    /*
+-     * GPR
+-     */
+-    object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
+-
+     /*
+      * GPIOs 1 to 5
+      */
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+                                             FSL_IMX6UL_WDOGn_IRQ[i]));
+     }
+-    /*
+-     * GPR
+-     */
+-    sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
+-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR);
+-
+     /*
+      * SDMA
+      */
+--
+.34.1

-New patch
+[PULL 12/24] Refactor i.MX6UL processor code
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
+* Add Addr and size definition for most i.MX6UL devices in i.MX6UL header file.
+* Use those newly defined named constants whenever possible.
+* Standardize the way we init a familly of unimplemented devices
+  - SAI
+  - PWM
+  - CAN
+* Add/rework few comments
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
+Message-id: d579043fbd4e4b490370783fda43fc02c8e9be75.1692964892.git.jcd@tribudubois.net
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/fsl-imx6ul.h | 156 +++++++++++++++++++++++++++++++-----
+ hw/arm/fsl-imx6ul.c         | 147 ++++++++++++++++++++++-----------
+files changed, 232 insertions(+), 71 deletions(-)
+diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/fsl-imx6ul.h
++++ b/include/hw/arm/fsl-imx6ul.h
+@@ -XXX,XX +XXX,XX @@
+ #include "exec/memory.h"
+ #include "cpu.h"
+ #include "qom/object.h"
++#include "qemu/units.h"
+ #define TYPE_FSL_IMX6UL "fsl-imx6ul"
+ OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6ULState, FSL_IMX6UL)
+@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
+     FSL_IMX6UL_NUM_ADCS         = 2,
+     FSL_IMX6UL_NUM_USB_PHYS     = 2,
+     FSL_IMX6UL_NUM_USBS         = 2,
++    FSL_IMX6UL_NUM_SAIS         = 3,
++    FSL_IMX6UL_NUM_CANS         = 2,
++    FSL_IMX6UL_NUM_PWMS         = 4,
+ };
+ struct FslIMX6ULState {
+@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
+ enum FslIMX6ULMemoryMap {
+     FSL_IMX6UL_MMDC_ADDR            = 0x80000000,
+-    FSL_IMX6UL_MMDC_SIZE            = 2 * 1024 * 1024 * 1024UL,
++    FSL_IMX6UL_MMDC_SIZE            = (2 * GiB),
+     FSL_IMX6UL_QSPI1_MEM_ADDR       = 0x60000000,
+-    FSL_IMX6UL_EIM_ALIAS_ADDR       = 0x58000000,
+-    FSL_IMX6UL_EIM_CS_ADDR          = 0x50000000,
+-    FSL_IMX6UL_AES_ENCRYPT_ADDR     = 0x10000000,
+-    FSL_IMX6UL_QSPI1_RX_ADDR        = 0x0C000000,
++    FSL_IMX6UL_QSPI1_MEM_SIZE       = (256 * MiB),
+-    /* AIPS-2 */
++    FSL_IMX6UL_EIM_ALIAS_ADDR       = 0x58000000,
++    FSL_IMX6UL_EIM_ALIAS_SIZE       = (128 * MiB),
++
++    FSL_IMX6UL_EIM_CS_ADDR          = 0x50000000,
++    FSL_IMX6UL_EIM_CS_SIZE          = (128 * MiB),
++
++    FSL_IMX6UL_AES_ENCRYPT_ADDR     = 0x10000000,
++    FSL_IMX6UL_AES_ENCRYPT_SIZE     = (1 * MiB),
++
++    FSL_IMX6UL_QSPI1_RX_ADDR        = 0x0C000000,
++    FSL_IMX6UL_QSPI1_RX_SIZE        = (32 * MiB),
++
++    /* AIPS-2 Begin */
+     FSL_IMX6UL_UART6_ADDR           = 0x021FC000,
++
+     FSL_IMX6UL_I2C4_ADDR            = 0x021F8000,
++
+     FSL_IMX6UL_UART5_ADDR           = 0x021F4000,
+     FSL_IMX6UL_UART4_ADDR           = 0x021F0000,
+     FSL_IMX6UL_UART3_ADDR           = 0x021EC000,
+     FSL_IMX6UL_UART2_ADDR           = 0x021E8000,
++
+     FSL_IMX6UL_WDOG3_ADDR           = 0x021E4000,
++
+     FSL_IMX6UL_QSPI_ADDR            = 0x021E0000,
++    FSL_IMX6UL_QSPI_SIZE            = 0x500,
++
+     FSL_IMX6UL_SYS_CNT_CTRL_ADDR    = 0x021DC000,
++    FSL_IMX6UL_SYS_CNT_CTRL_SIZE    = (16 * KiB),
++
+     FSL_IMX6UL_SYS_CNT_CMP_ADDR     = 0x021D8000,
++    FSL_IMX6UL_SYS_CNT_CMP_SIZE     = (16 * KiB),
++
+     FSL_IMX6UL_SYS_CNT_RD_ADDR      = 0x021D4000,
++    FSL_IMX6UL_SYS_CNT_RD_SIZE      = (16 * KiB),
++
+     FSL_IMX6UL_TZASC_ADDR           = 0x021D0000,
++    FSL_IMX6UL_TZASC_SIZE           = (16 * KiB),
++
+     FSL_IMX6UL_PXP_ADDR             = 0x021CC000,
++    FSL_IMX6UL_PXP_SIZE             = (16 * KiB),
++
+     FSL_IMX6UL_LCDIF_ADDR           = 0x021C8000,
++    FSL_IMX6UL_LCDIF_SIZE           = 0x100,
++
+     FSL_IMX6UL_CSI_ADDR             = 0x021C4000,
++    FSL_IMX6UL_CSI_SIZE             = 0x100,
++
+     FSL_IMX6UL_CSU_ADDR             = 0x021C0000,
++    FSL_IMX6UL_CSU_SIZE             = (16 * KiB),
++
+     FSL_IMX6UL_OCOTP_CTRL_ADDR      = 0x021BC000,
++    FSL_IMX6UL_OCOTP_CTRL_SIZE      = (4 * KiB),
++
+     FSL_IMX6UL_EIM_ADDR             = 0x021B8000,
++    FSL_IMX6UL_EIM_SIZE             = 0x100,
++
+     FSL_IMX6UL_SIM2_ADDR            = 0x021B4000,
++
+     FSL_IMX6UL_MMDC_CFG_ADDR        = 0x021B0000,
++    FSL_IMX6UL_MMDC_CFG_SIZE        = (4 * KiB),
++
+     FSL_IMX6UL_ROMCP_ADDR           = 0x021AC000,
++    FSL_IMX6UL_ROMCP_SIZE           = 0x300,
++
+     FSL_IMX6UL_I2C3_ADDR            = 0x021A8000,
+     FSL_IMX6UL_I2C2_ADDR            = 0x021A4000,
+     FSL_IMX6UL_I2C1_ADDR            = 0x021A0000,
++
+     FSL_IMX6UL_ADC2_ADDR            = 0x0219C000,
+     FSL_IMX6UL_ADC1_ADDR            = 0x02198000,
++    FSL_IMX6UL_ADCn_SIZE            = 0x100,
++
+     FSL_IMX6UL_USDHC2_ADDR          = 0x02194000,
+     FSL_IMX6UL_USDHC1_ADDR          = 0x02190000,
+-    FSL_IMX6UL_SIM1_ADDR            = 0x0218C000,
+-    FSL_IMX6UL_ENET1_ADDR           = 0x02188000,
+-    FSL_IMX6UL_USBO2_USBMISC_ADDR   = 0x02184800,
+-    FSL_IMX6UL_USBO2_USB_ADDR       = 0x02184000,
+-    FSL_IMX6UL_USBO2_PL301_ADDR     = 0x02180000,
+-    FSL_IMX6UL_AIPS2_CFG_ADDR       = 0x0217C000,
+-    FSL_IMX6UL_CAAM_ADDR            = 0x02140000,
+-    FSL_IMX6UL_A7MPCORE_DAP_ADDR    = 0x02100000,
+-    /* AIPS-1 */
++    FSL_IMX6UL_SIM1_ADDR            = 0x0218C000,
++    FSL_IMX6UL_SIMn_SIZE            = (16 * KiB),
++
++    FSL_IMX6UL_ENET1_ADDR           = 0x02188000,
++
++    FSL_IMX6UL_USBO2_USBMISC_ADDR   = 0x02184800,
++    FSL_IMX6UL_USBO2_USB1_ADDR      = 0x02184000,
++    FSL_IMX6UL_USBO2_USB2_ADDR      = 0x02184200,
++
++    FSL_IMX6UL_USBO2_PL301_ADDR     = 0x02180000,
++    FSL_IMX6UL_USBO2_PL301_SIZE     = (16 * KiB),
++
++    FSL_IMX6UL_AIPS2_CFG_ADDR       = 0x0217C000,
++    FSL_IMX6UL_AIPS2_CFG_SIZE       = 0x100,
++
++    FSL_IMX6UL_CAAM_ADDR            = 0x02140000,
++    FSL_IMX6UL_CAAM_SIZE            = (16 * KiB),
++
++    FSL_IMX6UL_A7MPCORE_DAP_ADDR    = 0x02100000,
++    FSL_IMX6UL_A7MPCORE_DAP_SIZE    = (4 * KiB),
++    /* AIPS-2 End */
++
++    /* AIPS-1 Begin */
+     FSL_IMX6UL_PWM8_ADDR            = 0x020FC000,
+     FSL_IMX6UL_PWM7_ADDR            = 0x020F8000,
+     FSL_IMX6UL_PWM6_ADDR            = 0x020F4000,
+     FSL_IMX6UL_PWM5_ADDR            = 0x020F0000,
++
+     FSL_IMX6UL_SDMA_ADDR            = 0x020EC000,
++    FSL_IMX6UL_SDMA_SIZE            = 0x300,
++
+     FSL_IMX6UL_GPT2_ADDR            = 0x020E8000,
++
+     FSL_IMX6UL_IOMUXC_GPR_ADDR      = 0x020E4000,
++    FSL_IMX6UL_IOMUXC_GPR_SIZE      = 0x40,
++
+     FSL_IMX6UL_IOMUXC_ADDR          = 0x020E0000,
++    FSL_IMX6UL_IOMUXC_SIZE          = 0x700,
++
+     FSL_IMX6UL_GPC_ADDR             = 0x020DC000,
++
+     FSL_IMX6UL_SRC_ADDR             = 0x020D8000,
++
+     FSL_IMX6UL_EPIT2_ADDR           = 0x020D4000,
+     FSL_IMX6UL_EPIT1_ADDR           = 0x020D0000,
++
+     FSL_IMX6UL_SNVS_HP_ADDR         = 0x020CC000,
++
+     FSL_IMX6UL_USBPHY2_ADDR         = 0x020CA000,
+-    FSL_IMX6UL_USBPHY2_SIZE         = (4 * 1024),
+     FSL_IMX6UL_USBPHY1_ADDR         = 0x020C9000,
+-    FSL_IMX6UL_USBPHY1_SIZE         = (4 * 1024),
++
+     FSL_IMX6UL_ANALOG_ADDR          = 0x020C8000,
++    FSL_IMX6UL_ANALOG_SIZE          = 0x300,
++
+     FSL_IMX6UL_CCM_ADDR             = 0x020C4000,
++
+     FSL_IMX6UL_WDOG2_ADDR           = 0x020C0000,
+     FSL_IMX6UL_WDOG1_ADDR           = 0x020BC000,
++
+     FSL_IMX6UL_KPP_ADDR             = 0x020B8000,
++    FSL_IMX6UL_KPP_SIZE             = 0x10,
++
+     FSL_IMX6UL_ENET2_ADDR           = 0x020B4000,
++
+     FSL_IMX6UL_SNVS_LP_ADDR         = 0x020B0000,
++    FSL_IMX6UL_SNVS_LP_SIZE         = (16 * KiB),
++
+     FSL_IMX6UL_GPIO5_ADDR           = 0x020AC000,
+     FSL_IMX6UL_GPIO4_ADDR           = 0x020A8000,
+     FSL_IMX6UL_GPIO3_ADDR           = 0x020A4000,
+     FSL_IMX6UL_GPIO2_ADDR           = 0x020A0000,
+     FSL_IMX6UL_GPIO1_ADDR           = 0x0209C000,
++
+     FSL_IMX6UL_GPT1_ADDR            = 0x02098000,
++
+     FSL_IMX6UL_CAN2_ADDR            = 0x02094000,
+     FSL_IMX6UL_CAN1_ADDR            = 0x02090000,
++    FSL_IMX6UL_CANn_SIZE            = (4 * KiB),
++
+     FSL_IMX6UL_PWM4_ADDR            = 0x0208C000,
+     FSL_IMX6UL_PWM3_ADDR            = 0x02088000,
+     FSL_IMX6UL_PWM2_ADDR            = 0x02084000,
+     FSL_IMX6UL_PWM1_ADDR            = 0x02080000,
++    FSL_IMX6UL_PWMn_SIZE            = 0x20,
++
+     FSL_IMX6UL_AIPS1_CFG_ADDR       = 0x0207C000,
++    FSL_IMX6UL_AIPS1_CFG_SIZE       = (16 * KiB),
++
+     FSL_IMX6UL_BEE_ADDR             = 0x02044000,
++    FSL_IMX6UL_BEE_SIZE             = (16 * KiB),
++
+     FSL_IMX6UL_TOUCH_CTRL_ADDR      = 0x02040000,
++    FSL_IMX6UL_TOUCH_CTRL_SIZE      = 0x100,
++
+     FSL_IMX6UL_SPBA_ADDR            = 0x0203C000,
++    FSL_IMX6UL_SPBA_SIZE            = 0x100,
++
+     FSL_IMX6UL_ASRC_ADDR            = 0x02034000,
++    FSL_IMX6UL_ASRC_SIZE            = 0x100,
++
+     FSL_IMX6UL_SAI3_ADDR            = 0x02030000,
+     FSL_IMX6UL_SAI2_ADDR            = 0x0202C000,
+     FSL_IMX6UL_SAI1_ADDR            = 0x02028000,
++    FSL_IMX6UL_SAIn_SIZE            = 0x200,
++
+     FSL_IMX6UL_UART8_ADDR           = 0x02024000,
+     FSL_IMX6UL_UART1_ADDR           = 0x02020000,
+     FSL_IMX6UL_UART7_ADDR           = 0x02018000,
++
+     FSL_IMX6UL_ECSPI4_ADDR          = 0x02014000,
+     FSL_IMX6UL_ECSPI3_ADDR          = 0x02010000,
+     FSL_IMX6UL_ECSPI2_ADDR          = 0x0200C000,
+     FSL_IMX6UL_ECSPI1_ADDR          = 0x02008000,
++
+     FSL_IMX6UL_SPDIF_ADDR           = 0x02004000,
++    FSL_IMX6UL_SPDIF_SIZE           = 0x100,
++    /* AIPS-1 End */
++
++    FSL_IMX6UL_BCH_ADDR             = 0x01808000,
++    FSL_IMX6UL_BCH_SIZE             = 0x200,
++
++    FSL_IMX6UL_GPMI_ADDR            = 0x01806000,
++    FSL_IMX6UL_GPMI_SIZE            = 0x200,
+     FSL_IMX6UL_APBH_DMA_ADDR        = 0x01804000,
+-    FSL_IMX6UL_APBH_DMA_SIZE        = (32 * 1024),
++    FSL_IMX6UL_APBH_DMA_SIZE        = (4 * KiB),
+     FSL_IMX6UL_A7MPCORE_ADDR        = 0x00A00000,
+     FSL_IMX6UL_OCRAM_ALIAS_ADDR     = 0x00920000,
+-    FSL_IMX6UL_OCRAM_ALIAS_SIZE     = 0x00060000,
++    FSL_IMX6UL_OCRAM_ALIAS_SIZE     = (384 * KiB),
++
+     FSL_IMX6UL_OCRAM_MEM_ADDR       = 0x00900000,
+-    FSL_IMX6UL_OCRAM_MEM_SIZE       = 0x00020000,
++    FSL_IMX6UL_OCRAM_MEM_SIZE       = (128 * KiB),
++
+     FSL_IMX6UL_CAAM_MEM_ADDR        = 0x00100000,
+-    FSL_IMX6UL_CAAM_MEM_SIZE        = 0x00008000,
++    FSL_IMX6UL_CAAM_MEM_SIZE        = (32 * KiB),
++
+     FSL_IMX6UL_ROM_ADDR             = 0x00000000,
+-    FSL_IMX6UL_ROM_SIZE             = 0x00018000,
++    FSL_IMX6UL_ROM_SIZE             = (96 * KiB),
+ };
+ enum FslIMX6ULIRQs {
+diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/fsl-imx6ul.c
++++ b/hw/arm/fsl-imx6ul.c
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
+     /*
+-     * GPIOs 1 to 5
++     * GPIOs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
+         snprintf(name, NAME_SIZE, "gpio%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * GPT 1, 2
++     * GPTs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
+         snprintf(name, NAME_SIZE, "gpt%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * EPIT 1, 2
++     * EPITs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
+         snprintf(name, NAME_SIZE, "epit%d", i + 1);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * eCSPI
++     * eCSPIs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
+         snprintf(name, NAME_SIZE, "spi%d", i + 1);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * I2C
++     * I2Cs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
+         snprintf(name, NAME_SIZE, "i2c%d", i + 1);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * UART
++     * UARTs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
+         snprintf(name, NAME_SIZE, "uart%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * Ethernet
++     * Ethernets
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
+         snprintf(name, NAME_SIZE, "eth%d", i);
+         object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
+     }
+-    /* USB */
++    /*
++     * USB PHYs
++     */
+     for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
+         snprintf(name, NAME_SIZE, "usbphy%d", i);
+         object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
+     }
++
++    /*
++     * USBs
++     */
+     for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
+         snprintf(name, NAME_SIZE, "usb%d", i);
+         object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
+     }
+     /*
+-     * SDHCI
++     * SDHCIs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
+         snprintf(name, NAME_SIZE, "usdhc%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * Watchdog
++     * Watchdogs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
+         snprintf(name, NAME_SIZE, "wdt%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+      * A7MPCORE DAP
+      */
+     create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR,
+-                                0x100000);
++                                FSL_IMX6UL_A7MPCORE_DAP_SIZE);
+     /*
+-     * GPT 1, 2
++     * GPTs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
+         static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * EPIT 1, 2
++     * EPITs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
+         static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * GPIO
++     * GPIOs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
+         static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * IOMUXC and IOMUXC_GPR
++     * IOMUXC
+      */
+-    for (i = 0; i < 1; i++) {
+-        static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = {
+-            FSL_IMX6UL_IOMUXC_ADDR,
+-            FSL_IMX6UL_IOMUXC_GPR_ADDR,
+-        };
+-
+-        snprintf(name, NAME_SIZE, "iomuxc%d", i);
+-        create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000);
+-    }
++    create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR,
++                                FSL_IMX6UL_IOMUXC_SIZE);
++    create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR,
++                                FSL_IMX6UL_IOMUXC_GPR_SIZE);
+     /*
+      * CCM
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
+     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
+-    /* Initialize all ECSPI */
++    /*
++     * ECSPIs
++     */
+     for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
+         static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = {
+             FSL_IMX6UL_ECSPI1_ADDR,
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * I2C
++     * I2Cs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
+         static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * UART
++     * UARTs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
+         static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * Ethernet
++     * Ethernets
+      *
+      * We must use two loops since phy_connected affects the other interface
+      * and we have to set all properties before calling sysbus_realize().
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+                                             FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
+     }
+-    /* USB */
++    /*
++     * USB PHYs
++     */
+     for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
++        static const hwaddr
++                     FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] = {
++            FSL_IMX6UL_USBPHY1_ADDR,
++            FSL_IMX6UL_USBPHY2_ADDR,
++        };
++
+         sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
+         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
+-                        FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000);
++                        FSL_IMX6UL_USB_PHYn_ADDR[i]);
+     }
++    /*
++     * USBs
++     */
+     for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
++        static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS] = {
++            FSL_IMX6UL_USBO2_USB1_ADDR,
++            FSL_IMX6UL_USBO2_USB2_ADDR,
++        };
++
+         static const int FSL_IMX6UL_USBn_IRQ[] = {
+             FSL_IMX6UL_USB1_IRQ,
+             FSL_IMX6UL_USB2_IRQ,
+         };
++
+         sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
+         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
+-                        FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200);
++                        FSL_IMX6UL_USB02_USBn_ADDR[i]);
+         sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
+                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+                                             FSL_IMX6UL_USBn_IRQ[i]));
+     }
+     /*
+-     * USDHC
++     * USDHCs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
+         static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
+     /*
+-     * Watchdog
++     * Watchdogs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
+         static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+             FSL_IMX6UL_WDOG2_ADDR,
+             FSL_IMX6UL_WDOG3_ADDR,
+         };
++
+         static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = {
+             FSL_IMX6UL_WDOG1_IRQ,
+             FSL_IMX6UL_WDOG2_IRQ,
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     /*
+      * SDMA
+      */
+-    create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
++    create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR,
++                                FSL_IMX6UL_SDMA_SIZE);
+     /*
+-     * SAI (Audio SSI (Synchronous Serial Interface))
++     * SAIs (Audio SSI (Synchronous Serial Interface))
+      */
+-    create_unimplemented_device("sai1", FSL_IMX6UL_SAI1_ADDR, 0x4000);
+-    create_unimplemented_device("sai2", FSL_IMX6UL_SAI2_ADDR, 0x4000);
+-    create_unimplemented_device("sai3", FSL_IMX6UL_SAI3_ADDR, 0x4000);
++    for (i = 0; i < FSL_IMX6UL_NUM_SAIS; i++) {
++        static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] = {
++            FSL_IMX6UL_SAI1_ADDR,
++            FSL_IMX6UL_SAI2_ADDR,
++            FSL_IMX6UL_SAI3_ADDR,
++        };
++
++        snprintf(name, NAME_SIZE, "sai%d", i);
++        create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i],
++                                    FSL_IMX6UL_SAIn_SIZE);
++    }
+     /*
+-     * PWM
++     * PWMs
+      */
+-    create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000);
+-    create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000);
+-    create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000);
+-    create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000);
++    for (i = 0; i < FSL_IMX6UL_NUM_PWMS; i++) {
++        static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] = {
++            FSL_IMX6UL_PWM1_ADDR,
++            FSL_IMX6UL_PWM2_ADDR,
++            FSL_IMX6UL_PWM3_ADDR,
++            FSL_IMX6UL_PWM4_ADDR,
++        };
++
++        snprintf(name, NAME_SIZE, "pwm%d", i);
++        create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i],
++                                    FSL_IMX6UL_PWMn_SIZE);
++    }
+     /*
+      * Audio ASRC (asynchronous sample rate converter)
+      */
+-    create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, 0x4000);
++    create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR,
++                                FSL_IMX6UL_ASRC_SIZE);
+     /*
+-     * CAN
++     * CANs
+      */
+-    create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000);
+-    create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000);
++    for (i = 0; i < FSL_IMX6UL_NUM_CANS; i++) {
++        static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] = {
++            FSL_IMX6UL_CAN1_ADDR,
++            FSL_IMX6UL_CAN2_ADDR,
++        };
++
++        snprintf(name, NAME_SIZE, "can%d", i);
++        create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i],
++                                    FSL_IMX6UL_CANn_SIZE);
++    }
+     /*
+      * APHB_DMA
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+         };
+         snprintf(name, NAME_SIZE, "adc%d", i);
+-        create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000);
++        create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i],
++                                    FSL_IMX6UL_ADCn_SIZE);
+     }
+     /*
+      * LCD
+      */
+-    create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000);
++    create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
++                                FSL_IMX6UL_LCDIF_SIZE);
+     /*
+      * ROM memory
+--
+.34.1

-[PULL 04/17] tests/boot-serial-test: Add STM32VLDISCOVERY board testcase
+[PULL 13/24] Add i.MX6UL missing devices.
-From: Alexandre Iooss <erdnaxe@crans.org>
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
-New mini-kernel test for STM32VLDISCOVERY USART1.
+* Add TZASC as unimplemented device.
   - Allow bare metal application to access this (unimplemented) device
 * Add CSU as unimplemented device.
   - Allow bare metal application to access this (unimplemented) device
 * Add 4 missing PWM devices
-Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
-Acked-by: Thomas Huth <thuth@redhat.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 59e4dc56e14eccfefd379275ec19048dff9c10b3.1692964892.git.jcd@tribudubois.net
 Message-id: 20210617165647.2575955-5-erdnaxe@crans.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- tests/qtest/boot-serial-test.c | 37 ++++++++++++++++++++++++++++++++++
+ include/hw/arm/fsl-imx6ul.h |  2 +-
-file changed, 37 insertions(+)
+ hw/arm/fsl-imx6ul.c         | 16 ++++++++++++++++
 files changed, 17 insertions(+), 1 deletion(-)
-diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
+diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
 index XXXXXXX..XXXXXXX 100644
---- a/tests/qtest/boot-serial-test.c
+--- a/include/hw/arm/fsl-imx6ul.h
-+++ b/tests/qtest/boot-serial-test.c
++++ b/include/hw/arm/fsl-imx6ul.h
-@@ -XXX,XX +XXX,XX @@ static const uint8_t kernel_nrf51[] = {
+@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
-x1c, 0x25, 0x00, 0x40                  /* 0x4000251c = UART TXD */
+     FSL_IMX6UL_NUM_USBS         = 2,
      FSL_IMX6UL_NUM_SAIS         = 3,
      FSL_IMX6UL_NUM_CANS         = 2,
 -    FSL_IMX6UL_NUM_PWMS         = 4,
 +    FSL_IMX6UL_NUM_PWMS         = 8,
  };
-+static const uint8_t kernel_stm32vldiscovery[] = {
+ struct FslIMX6ULState {
-+    0x00, 0x00, 0x00, 0x00,                 /* Stack top address */
+diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
-+    0x1d, 0x00, 0x00, 0x00,                 /* Reset handler address */
+index XXXXXXX..XXXXXXX 100644
-+    0x00, 0x00, 0x00, 0x00,                 /* NMI */
+--- a/hw/arm/fsl-imx6ul.c
-+    0x00, 0x00, 0x00, 0x00,                 /* Hard fault */
++++ b/hw/arm/fsl-imx6ul.c
-+    0x00, 0x00, 0x00, 0x00,                 /* Memory management fault */
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
-+    0x00, 0x00, 0x00, 0x00,                 /* Bus fault */
+             FSL_IMX6UL_PWM2_ADDR,
-+    0x00, 0x00, 0x00, 0x00,                 /* Usage fault */
+             FSL_IMX6UL_PWM3_ADDR,
-+    0x0b, 0x4b,                             /* ldr  r3, [pc, #44] Get RCC */
+             FSL_IMX6UL_PWM4_ADDR,
-+    0x44, 0xf2, 0x04, 0x02,                 /* movw r2, #16388 */
++            FSL_IMX6UL_PWM5_ADDR,
-+    0x1a, 0x60,                             /* str  r2, [r3] */
++            FSL_IMX6UL_PWM6_ADDR,
-+    0x0a, 0x4b,                             /* ldr  r3, [pc, #40] Get GPIOA */
++            FSL_IMX6UL_PWM7_ADDR,
-+    0x1a, 0x68,                             /* ldr  r2, [r3] */
++            FSL_IMX6UL_PWM8_ADDR,
-+    0x22, 0xf0, 0xf0, 0x02,                 /* bic  r2, r2, #240 */
+         };
-+    0x1a, 0x60,                             /* str  r2, [r3] */
-+    0x1a, 0x68,                             /* ldr  r2, [r3] */
+         snprintf(name, NAME_SIZE, "pwm%d", i);
-+    0x42, 0xf0, 0xb0, 0x02,                 /* orr  r2, r2, #176 */
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
-+    0x1a, 0x60,                             /* str  r2, [r3] */
+     create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
-+    0x07, 0x4b,                             /* ldr  r3, [pc, #26] Get BAUD */
+                                 FSL_IMX6UL_LCDIF_SIZE);
-+    0x45, 0x22,                             /* movs r2, #69 */
-+    0x1a, 0x60,                             /* str  r2, [r3] */
++    /*
-+    0x06, 0x4b,                             /* ldr  r3, [pc, #24] Get ENABLE */
++     * CSU
-+    0x42, 0xf2, 0x08, 0x02,                 /* movw r2, #8200 */
++     */
-+    0x1a, 0x60,                             /* str  r2, [r3] */
++    create_unimplemented_device("csu", FSL_IMX6UL_CSU_ADDR,
-+    0x05, 0x4b,                             /* ldr  r3, [pc, #20] Get TXD */
++                                FSL_IMX6UL_CSU_SIZE);
 +    0x54, 0x22,                             /* movs r2, 'T' */
 +    0x1a, 0x60,                             /* str  r2, [r3] */
 +    0xfe, 0xe7,                             /* b    . */
 +    0x18, 0x10, 0x02, 0x40,                 /* 0x40021018 = RCC */
 +    0x04, 0x08, 0x01, 0x40,                 /* 0x40010804 = GPIOA */
 +    0x08, 0x38, 0x01, 0x40,                 /* 0x40013808 = USART1 BAUD */
 +    0x0c, 0x38, 0x01, 0x40,                 /* 0x4001380c = USART1 ENABLE */
 +    0x04, 0x38, 0x01, 0x40                  /* 0x40013804 = USART1 TXD */
 +};
 +
- typedef struct testdef {
++    /*
-     const char *arch;       /* Target architecture */
++     * TZASC
-     const char *machine;    /* Name of the machine */
++     */
-@@ -XXX,XX +XXX,XX @@ static testdef_t tests[] = {
++    create_unimplemented_device("tzasc", FSL_IMX6UL_TZASC_ADDR,
-     { "aarch64", "virt", "-cpu max", "TT", sizeof(kernel_aarch64),
++                                FSL_IMX6UL_TZASC_SIZE);
-       kernel_aarch64 },
++
-     { "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 },
+     /*
-+    { "arm", "stm32vldiscovery", "", "T",
+      * ROM memory
-+      sizeof(kernel_stm32vldiscovery), kernel_stm32vldiscovery },
+      */
      { NULL }
  };
 --
-.20.1
+.34.1

-[PULL 05/17] hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write
+[PULL 14/24] Refactor i.MX7 processor code
-From: Ricardo Koller <ricarkol@google.com>
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
-icv_eoir_write() and icv_dir_write() ignore invalid virtual IRQ numbers
+* Add Addr and size definition for all i.MX7 devices in i.MX7 header file.
-(like LPIs).  The issue is that these functions check against the number
+* Use those newly defined named constants whenever possible.
-of implemented IRQs (QEMU's default is num_irq=288) which can be lower
+* Standardize the way we init a familly of unimplemented devices
-than the maximum virtual IRQ number (1020 - 1).  The consequence is that
+  - SAI
-if a hypervisor creates an LR for an IRQ between 288 and 1020, then the
+  - PWM
-guest is unable to deactivate the resulting IRQ. Note that other
+  - CAN
-functions that deal with large IRQ numbers, like icv_iar_read, check
+* Add/rework few comments
 against 1020 and not against num_irq.
-Fix the checks by using GICV3_MAXIRQ (1020) instead of the number of
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
-implemented IRQs.
+Message-id: 59e195d33e4d486a8d131392acd46633c8c10ed7.1692964892.git.jcd@tribudubois.net
 Signed-off-by: Ricardo Koller <ricarkol@google.com>
 Message-id: 20210702233701.3369-1-ricarkol@google.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/intc/arm_gicv3_cpuif.c | 4 ++--
+ include/hw/arm/fsl-imx7.h | 330 ++++++++++++++++++++++++++++----------
-file changed, 2 insertions(+), 2 deletions(-)
+ hw/arm/fsl-imx7.c         | 130 ++++++++++-----
 files changed, 335 insertions(+), 125 deletions(-)
-diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
+diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_cpuif.c
+--- a/include/hw/arm/fsl-imx7.h
-+++ b/hw/intc/arm_gicv3_cpuif.c
++++ b/include/hw/arm/fsl-imx7.h
-@@ -XXX,XX +XXX,XX @@ static void icv_dir_write(CPUARMState *env, const ARMCPRegInfo *ri,
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/misc/imx7_ccm.h"
-     trace_gicv3_icv_dir_write(gicv3_redist_affid(cs), value);
+ #include "hw/misc/imx7_snvs.h"
+ #include "hw/misc/imx7_gpr.h"
--    if (irq >= cs->gic->num_irq) {
+-#include "hw/misc/imx6_src.h"
-+    if (irq >= GICV3_MAXIRQ) {
+ #include "hw/watchdog/wdt_imx2.h"
-         /* Also catches special interrupt numbers and LPIs */
+ #include "hw/gpio/imx_gpio.h"
  #include "hw/char/imx_serial.h"
@@ -XXX,XX +XXX,XX @@
  #include "hw/usb/chipidea.h"
  #include "cpu.h"
  #include "qom/object.h"
 +#include "qemu/units.h"
  #define TYPE_FSL_IMX7 "fsl-imx7"
  OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7)
@@ -XXX,XX +XXX,XX @@ enum FslIMX7Configuration {
      FSL_IMX7_NUM_ECSPIS       = 4,
      FSL_IMX7_NUM_USBS         = 3,
      FSL_IMX7_NUM_ADCS         = 2,
 +    FSL_IMX7_NUM_SAIS         = 3,
 +    FSL_IMX7_NUM_CANS         = 2,
 +    FSL_IMX7_NUM_PWMS         = 4,
  };
  struct FslIMX7State {
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
  enum FslIMX7MemoryMap {
      FSL_IMX7_MMDC_ADDR            = 0x80000000,
 -    FSL_IMX7_MMDC_SIZE            = 2 * 1024 * 1024 * 1024UL,
 +    FSL_IMX7_MMDC_SIZE            = (2 * GiB),
 -    FSL_IMX7_GPIO1_ADDR           = 0x30200000,
 -    FSL_IMX7_GPIO2_ADDR           = 0x30210000,
 -    FSL_IMX7_GPIO3_ADDR           = 0x30220000,
 -    FSL_IMX7_GPIO4_ADDR           = 0x30230000,
 -    FSL_IMX7_GPIO5_ADDR           = 0x30240000,
 -    FSL_IMX7_GPIO6_ADDR           = 0x30250000,
 -    FSL_IMX7_GPIO7_ADDR           = 0x30260000,
 +    FSL_IMX7_QSPI1_MEM_ADDR       = 0x60000000,
 +    FSL_IMX7_QSPI1_MEM_SIZE       = (256 * MiB),
 -    FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
 +    FSL_IMX7_PCIE1_MEM_ADDR       = 0x40000000,
 +    FSL_IMX7_PCIE1_MEM_SIZE       = (256 * MiB),
 -    FSL_IMX7_WDOG1_ADDR           = 0x30280000,
 -    FSL_IMX7_WDOG2_ADDR           = 0x30290000,
 -    FSL_IMX7_WDOG3_ADDR           = 0x302A0000,
 -    FSL_IMX7_WDOG4_ADDR           = 0x302B0000,
 +    FSL_IMX7_QSPI1_RX_BUF_ADDR    = 0x34000000,
 +    FSL_IMX7_QSPI1_RX_BUF_SIZE    = (32 * MiB),
 -    FSL_IMX7_IOMUXC_LPSR_ADDR     = 0x302C0000,
 +    /* PCIe Peripherals */
 +    FSL_IMX7_PCIE_REG_ADDR        = 0x33800000,
 -    FSL_IMX7_GPT1_ADDR            = 0x302D0000,
 -    FSL_IMX7_GPT2_ADDR            = 0x302E0000,
 -    FSL_IMX7_GPT3_ADDR            = 0x302F0000,
 -    FSL_IMX7_GPT4_ADDR            = 0x30300000,
 +    /* MMAP Peripherals */
 +    FSL_IMX7_DMA_APBH_ADDR        = 0x33000000,
 +    FSL_IMX7_DMA_APBH_SIZE        = 0x8000,
 -    FSL_IMX7_IOMUXC_ADDR          = 0x30330000,
 -    FSL_IMX7_IOMUXC_GPR_ADDR      = 0x30340000,
 -    FSL_IMX7_IOMUXCn_SIZE         = 0x1000,
 +    /* GPV configuration */
 +    FSL_IMX7_GPV6_ADDR            = 0x32600000,
 +    FSL_IMX7_GPV5_ADDR            = 0x32500000,
 +    FSL_IMX7_GPV4_ADDR            = 0x32400000,
 +    FSL_IMX7_GPV3_ADDR            = 0x32300000,
 +    FSL_IMX7_GPV2_ADDR            = 0x32200000,
 +    FSL_IMX7_GPV1_ADDR            = 0x32100000,
 +    FSL_IMX7_GPV0_ADDR            = 0x32000000,
 +    FSL_IMX7_GPVn_SIZE            = (1 * MiB),
 -    FSL_IMX7_OCOTP_ADDR           = 0x30350000,
 -    FSL_IMX7_OCOTP_SIZE           = 0x10000,
 +    /* Arm Peripherals */
 +    FSL_IMX7_A7MPCORE_ADDR        = 0x31000000,
 -    FSL_IMX7_ANALOG_ADDR          = 0x30360000,
 -    FSL_IMX7_SNVS_ADDR            = 0x30370000,
 -    FSL_IMX7_CCM_ADDR             = 0x30380000,
 +    /* AIPS-3 Begin */
 -    FSL_IMX7_SRC_ADDR             = 0x30390000,
 -    FSL_IMX7_SRC_SIZE             = 0x1000,
 +    FSL_IMX7_ENET2_ADDR           = 0x30BF0000,
 +    FSL_IMX7_ENET1_ADDR           = 0x30BE0000,
 -    FSL_IMX7_ADC1_ADDR            = 0x30610000,
 -    FSL_IMX7_ADC2_ADDR            = 0x30620000,
 -    FSL_IMX7_ADCn_SIZE            = 0x1000,
 +    FSL_IMX7_SDMA_ADDR            = 0x30BD0000,
 +    FSL_IMX7_SDMA_SIZE            = (4 * KiB),
 -    FSL_IMX7_PWM1_ADDR            = 0x30660000,
 -    FSL_IMX7_PWM2_ADDR            = 0x30670000,
 -    FSL_IMX7_PWM3_ADDR            = 0x30680000,
 -    FSL_IMX7_PWM4_ADDR            = 0x30690000,
 -    FSL_IMX7_PWMn_SIZE            = 0x10000,
 +    FSL_IMX7_EIM_ADDR             = 0x30BC0000,
 +    FSL_IMX7_EIM_SIZE             = (4 * KiB),
 -    FSL_IMX7_PCIE_PHY_ADDR        = 0x306D0000,
 -    FSL_IMX7_PCIE_PHY_SIZE        = 0x10000,
 +    FSL_IMX7_QSPI_ADDR            = 0x30BB0000,
 +    FSL_IMX7_QSPI_SIZE            = 0x8000,
 -    FSL_IMX7_GPC_ADDR             = 0x303A0000,
 +    FSL_IMX7_SIM2_ADDR            = 0x30BA0000,
 +    FSL_IMX7_SIM1_ADDR            = 0x30B90000,
 +    FSL_IMX7_SIMn_SIZE            = (4 * KiB),
 +
 +    FSL_IMX7_USDHC3_ADDR          = 0x30B60000,
 +    FSL_IMX7_USDHC2_ADDR          = 0x30B50000,
 +    FSL_IMX7_USDHC1_ADDR          = 0x30B40000,
 +
 +    FSL_IMX7_USB3_ADDR            = 0x30B30000,
 +    FSL_IMX7_USBMISC3_ADDR        = 0x30B30200,
 +    FSL_IMX7_USB2_ADDR            = 0x30B20000,
 +    FSL_IMX7_USBMISC2_ADDR        = 0x30B20200,
 +    FSL_IMX7_USB1_ADDR            = 0x30B10000,
 +    FSL_IMX7_USBMISC1_ADDR        = 0x30B10200,
 +    FSL_IMX7_USBMISCn_SIZE        = 0x200,
 +
 +    FSL_IMX7_USB_PL301_ADDR       = 0x30AD0000,
 +    FSL_IMX7_USB_PL301_SIZE       = (64 * KiB),
 +
 +    FSL_IMX7_SEMAPHORE_HS_ADDR    = 0x30AC0000,
 +    FSL_IMX7_SEMAPHORE_HS_SIZE    = (64 * KiB),
 +
 +    FSL_IMX7_MUB_ADDR             = 0x30AB0000,
 +    FSL_IMX7_MUA_ADDR             = 0x30AA0000,
 +    FSL_IMX7_MUn_SIZE             = (KiB),
 +
 +    FSL_IMX7_UART7_ADDR           = 0x30A90000,
 +    FSL_IMX7_UART6_ADDR           = 0x30A80000,
 +    FSL_IMX7_UART5_ADDR           = 0x30A70000,
 +    FSL_IMX7_UART4_ADDR           = 0x30A60000,
 +
 +    FSL_IMX7_I2C4_ADDR            = 0x30A50000,
 +    FSL_IMX7_I2C3_ADDR            = 0x30A40000,
 +    FSL_IMX7_I2C2_ADDR            = 0x30A30000,
 +    FSL_IMX7_I2C1_ADDR            = 0x30A20000,
 +
 +    FSL_IMX7_CAN2_ADDR            = 0x30A10000,
 +    FSL_IMX7_CAN1_ADDR            = 0x30A00000,
 +    FSL_IMX7_CANn_SIZE            = (4 * KiB),
 +
 +    FSL_IMX7_AIPS3_CONF_ADDR      = 0x309F0000,
 +    FSL_IMX7_AIPS3_CONF_SIZE      = (64 * KiB),
      FSL_IMX7_CAAM_ADDR            = 0x30900000,
 -    FSL_IMX7_CAAM_SIZE            = 0x40000,
 +    FSL_IMX7_CAAM_SIZE            = (256 * KiB),
 -    FSL_IMX7_CAN1_ADDR            = 0x30A00000,
 -    FSL_IMX7_CAN2_ADDR            = 0x30A10000,
 -    FSL_IMX7_CANn_SIZE            = 0x10000,
 +    FSL_IMX7_SPBA_ADDR            = 0x308F0000,
 +    FSL_IMX7_SPBA_SIZE            = (4 * KiB),
 -    FSL_IMX7_I2C1_ADDR            = 0x30A20000,
 -    FSL_IMX7_I2C2_ADDR            = 0x30A30000,
 -    FSL_IMX7_I2C3_ADDR            = 0x30A40000,
 -    FSL_IMX7_I2C4_ADDR            = 0x30A50000,
 +    FSL_IMX7_SAI3_ADDR            = 0x308C0000,
 +    FSL_IMX7_SAI2_ADDR            = 0x308B0000,
 +    FSL_IMX7_SAI1_ADDR            = 0x308A0000,
 +    FSL_IMX7_SAIn_SIZE            = (4 * KiB),
 -    FSL_IMX7_ECSPI1_ADDR          = 0x30820000,
 -    FSL_IMX7_ECSPI2_ADDR          = 0x30830000,
 -    FSL_IMX7_ECSPI3_ADDR          = 0x30840000,
 -    FSL_IMX7_ECSPI4_ADDR          = 0x30630000,
 -
 -    FSL_IMX7_LCDIF_ADDR           = 0x30730000,
 -    FSL_IMX7_LCDIF_SIZE           = 0x1000,
 -
 -    FSL_IMX7_UART1_ADDR           = 0x30860000,
 +    FSL_IMX7_UART3_ADDR           = 0x30880000,
      /*
       * Some versions of the reference manual claim that UART2 is @
       * 0x30870000, but experiments with HW + DT files in upstream
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
       * actually located @ 0x30890000
       */
      FSL_IMX7_UART2_ADDR           = 0x30890000,
 -    FSL_IMX7_UART3_ADDR           = 0x30880000,
 -    FSL_IMX7_UART4_ADDR           = 0x30A60000,
 -    FSL_IMX7_UART5_ADDR           = 0x30A70000,
 -    FSL_IMX7_UART6_ADDR           = 0x30A80000,
 -    FSL_IMX7_UART7_ADDR           = 0x30A90000,
 +    FSL_IMX7_UART1_ADDR           = 0x30860000,
 -    FSL_IMX7_SAI1_ADDR            = 0x308A0000,
 -    FSL_IMX7_SAI2_ADDR            = 0x308B0000,
 -    FSL_IMX7_SAI3_ADDR            = 0x308C0000,
 -    FSL_IMX7_SAIn_SIZE            = 0x10000,
 +    FSL_IMX7_ECSPI3_ADDR          = 0x30840000,
 +    FSL_IMX7_ECSPI2_ADDR          = 0x30830000,
 +    FSL_IMX7_ECSPI1_ADDR          = 0x30820000,
 +    FSL_IMX7_ECSPIn_SIZE          = (4 * KiB),
 -    FSL_IMX7_ENET1_ADDR           = 0x30BE0000,
 -    FSL_IMX7_ENET2_ADDR           = 0x30BF0000,
 +    /* AIPS-3 End */
 -    FSL_IMX7_USB1_ADDR            = 0x30B10000,
 -    FSL_IMX7_USBMISC1_ADDR        = 0x30B10200,
 -    FSL_IMX7_USB2_ADDR            = 0x30B20000,
 -    FSL_IMX7_USBMISC2_ADDR        = 0x30B20200,
 -    FSL_IMX7_USB3_ADDR            = 0x30B30000,
 -    FSL_IMX7_USBMISC3_ADDR        = 0x30B30200,
 -    FSL_IMX7_USBMISCn_SIZE        = 0x200,
 +    /* AIPS-2 Begin */
 -    FSL_IMX7_USDHC1_ADDR          = 0x30B40000,
 -    FSL_IMX7_USDHC2_ADDR          = 0x30B50000,
 -    FSL_IMX7_USDHC3_ADDR          = 0x30B60000,
 +    FSL_IMX7_AXI_DEBUG_MON_ADDR   = 0x307E0000,
 +    FSL_IMX7_AXI_DEBUG_MON_SIZE   = (64 * KiB),
 -    FSL_IMX7_SDMA_ADDR            = 0x30BD0000,
 -    FSL_IMX7_SDMA_SIZE            = 0x1000,
 +    FSL_IMX7_PERFMON2_ADDR        = 0x307D0000,
 +    FSL_IMX7_PERFMON1_ADDR        = 0x307C0000,
 +    FSL_IMX7_PERFMONn_SIZE        = (64 * KiB),
 +
 +    FSL_IMX7_DDRC_ADDR            = 0x307A0000,
 +    FSL_IMX7_DDRC_SIZE            = (4 * KiB),
 +
 +    FSL_IMX7_DDRC_PHY_ADDR        = 0x30790000,
 +    FSL_IMX7_DDRC_PHY_SIZE        = (4 * KiB),
 +
 +    FSL_IMX7_TZASC_ADDR           = 0x30780000,
 +    FSL_IMX7_TZASC_SIZE           = (64 * KiB),
 +
 +    FSL_IMX7_MIPI_DSI_ADDR        = 0x30760000,
 +    FSL_IMX7_MIPI_DSI_SIZE        = (4 * KiB),
 +
 +    FSL_IMX7_MIPI_CSI_ADDR        = 0x30750000,
 +    FSL_IMX7_MIPI_CSI_SIZE        = 0x4000,
 +
 +    FSL_IMX7_LCDIF_ADDR           = 0x30730000,
 +    FSL_IMX7_LCDIF_SIZE           = 0x8000,
 +
 +    FSL_IMX7_CSI_ADDR             = 0x30710000,
 +    FSL_IMX7_CSI_SIZE             = (4 * KiB),
 +
 +    FSL_IMX7_PXP_ADDR             = 0x30700000,
 +    FSL_IMX7_PXP_SIZE             = 0x4000,
 +
 +    FSL_IMX7_EPDC_ADDR            = 0x306F0000,
 +    FSL_IMX7_EPDC_SIZE            = (4 * KiB),
 +
 +    FSL_IMX7_PCIE_PHY_ADDR        = 0x306D0000,
 +    FSL_IMX7_PCIE_PHY_SIZE        = (4 * KiB),
 +
 +    FSL_IMX7_SYSCNT_CTRL_ADDR     = 0x306C0000,
 +    FSL_IMX7_SYSCNT_CMP_ADDR      = 0x306B0000,
 +    FSL_IMX7_SYSCNT_RD_ADDR       = 0x306A0000,
 +
 +    FSL_IMX7_PWM4_ADDR            = 0x30690000,
 +    FSL_IMX7_PWM3_ADDR            = 0x30680000,
 +    FSL_IMX7_PWM2_ADDR            = 0x30670000,
 +    FSL_IMX7_PWM1_ADDR            = 0x30660000,
 +    FSL_IMX7_PWMn_SIZE            = (4 * KiB),
 +
 +    FSL_IMX7_FlEXTIMER2_ADDR      = 0x30650000,
 +    FSL_IMX7_FlEXTIMER1_ADDR      = 0x30640000,
 +    FSL_IMX7_FLEXTIMERn_SIZE      = (4 * KiB),
 +
 +    FSL_IMX7_ECSPI4_ADDR          = 0x30630000,
 +
 +    FSL_IMX7_ADC2_ADDR            = 0x30620000,
 +    FSL_IMX7_ADC1_ADDR            = 0x30610000,
 +    FSL_IMX7_ADCn_SIZE            = (4 * KiB),
 +
 +    FSL_IMX7_AIPS2_CONF_ADDR      = 0x305F0000,
 +    FSL_IMX7_AIPS2_CONF_SIZE      = (64 * KiB),
 +
 +    /* AIPS-2 End */
 +
 +    /* AIPS-1 Begin */
 +
 +    FSL_IMX7_CSU_ADDR             = 0x303E0000,
 +    FSL_IMX7_CSU_SIZE             = (64 * KiB),
 +
 +    FSL_IMX7_RDC_ADDR             = 0x303D0000,
 +    FSL_IMX7_RDC_SIZE             = (4 * KiB),
 +
 +    FSL_IMX7_SEMAPHORE2_ADDR      = 0x303C0000,
 +    FSL_IMX7_SEMAPHORE1_ADDR      = 0x303B0000,
 +    FSL_IMX7_SEMAPHOREn_SIZE      = (4 * KiB),
 +
 +    FSL_IMX7_GPC_ADDR             = 0x303A0000,
 +
 +    FSL_IMX7_SRC_ADDR             = 0x30390000,
 +    FSL_IMX7_SRC_SIZE             = (4 * KiB),
 +
 +    FSL_IMX7_CCM_ADDR             = 0x30380000,
 +
 +    FSL_IMX7_SNVS_HP_ADDR         = 0x30370000,
 +
 +    FSL_IMX7_ANALOG_ADDR          = 0x30360000,
 +
 +    FSL_IMX7_OCOTP_ADDR           = 0x30350000,
 +    FSL_IMX7_OCOTP_SIZE           = 0x10000,
 +
 +    FSL_IMX7_IOMUXC_GPR_ADDR      = 0x30340000,
 +    FSL_IMX7_IOMUXC_GPR_SIZE      = (4 * KiB),
 +
 +    FSL_IMX7_IOMUXC_ADDR          = 0x30330000,
 +    FSL_IMX7_IOMUXC_SIZE          = (4 * KiB),
 +
 +    FSL_IMX7_KPP_ADDR             = 0x30320000,
 +    FSL_IMX7_KPP_SIZE             = (4 * KiB),
 +
 +    FSL_IMX7_ROMCP_ADDR           = 0x30310000,
 +    FSL_IMX7_ROMCP_SIZE           = (4 * KiB),
 +
 +    FSL_IMX7_GPT4_ADDR            = 0x30300000,
 +    FSL_IMX7_GPT3_ADDR            = 0x302F0000,
 +    FSL_IMX7_GPT2_ADDR            = 0x302E0000,
 +    FSL_IMX7_GPT1_ADDR            = 0x302D0000,
 +
 +    FSL_IMX7_IOMUXC_LPSR_ADDR     = 0x302C0000,
 +    FSL_IMX7_IOMUXC_LPSR_SIZE     = (4 * KiB),
 +
 +    FSL_IMX7_WDOG4_ADDR           = 0x302B0000,
 +    FSL_IMX7_WDOG3_ADDR           = 0x302A0000,
 +    FSL_IMX7_WDOG2_ADDR           = 0x30290000,
 +    FSL_IMX7_WDOG1_ADDR           = 0x30280000,
 +
 +    FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
 +
 +    FSL_IMX7_GPIO7_ADDR           = 0x30260000,
 +    FSL_IMX7_GPIO6_ADDR           = 0x30250000,
 +    FSL_IMX7_GPIO5_ADDR           = 0x30240000,
 +    FSL_IMX7_GPIO4_ADDR           = 0x30230000,
 +    FSL_IMX7_GPIO3_ADDR           = 0x30220000,
 +    FSL_IMX7_GPIO2_ADDR           = 0x30210000,
 +    FSL_IMX7_GPIO1_ADDR           = 0x30200000,
 +
 +    FSL_IMX7_AIPS1_CONF_ADDR      = 0x301F0000,
 +    FSL_IMX7_AIPS1_CONF_SIZE      = (64 * KiB),
 -    FSL_IMX7_A7MPCORE_ADDR        = 0x31000000,
      FSL_IMX7_A7MPCORE_DAP_ADDR    = 0x30000000,
 +    FSL_IMX7_A7MPCORE_DAP_SIZE    = (1 * MiB),
 -    FSL_IMX7_PCIE_REG_ADDR        = 0x33800000,
 -    FSL_IMX7_PCIE_REG_SIZE        = 16 * 1024,
 +    /* AIPS-1 End */
 -    FSL_IMX7_GPR_ADDR             = 0x30340000,
 +    FSL_IMX7_EIM_CS0_ADDR         = 0x28000000,
 +    FSL_IMX7_EIM_CS0_SIZE         = (128 * MiB),
 -    FSL_IMX7_DMA_APBH_ADDR        = 0x33000000,
 -    FSL_IMX7_DMA_APBH_SIZE        = 0x2000,
 +    FSL_IMX7_OCRAM_PXP_ADDR       = 0x00940000,
 +    FSL_IMX7_OCRAM_PXP_SIZE       = (32 * KiB),
 +
 +    FSL_IMX7_OCRAM_EPDC_ADDR      = 0x00920000,
 +    FSL_IMX7_OCRAM_EPDC_SIZE      = (128 * KiB),
 +
 +    FSL_IMX7_OCRAM_MEM_ADDR       = 0x00900000,
 +    FSL_IMX7_OCRAM_MEM_SIZE       = (128 * KiB),
 +
 +    FSL_IMX7_TCMU_ADDR            = 0x00800000,
 +    FSL_IMX7_TCMU_SIZE            = (32 * KiB),
 +
 +    FSL_IMX7_TCML_ADDR            = 0x007F8000,
 +    FSL_IMX7_TCML_SIZE            = (32 * KiB),
 +
 +    FSL_IMX7_OCRAM_S_ADDR         = 0x00180000,
 +    FSL_IMX7_OCRAM_S_SIZE         = (32 * KiB),
 +
 +    FSL_IMX7_CAAM_MEM_ADDR        = 0x00100000,
 +    FSL_IMX7_CAAM_MEM_SIZE        = (32 * KiB),
 +
 +    FSL_IMX7_ROM_ADDR             = 0x00000000,
 +    FSL_IMX7_ROM_SIZE             = (96 * KiB),
  };
  enum FslIMX7IRQs {
 diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/fsl-imx7.c
 +++ b/hw/arm/fsl-imx7.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      char name[NAME_SIZE];
      int i;
 +    /*
 +     * CPUs
 +     */
      for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) {
          snprintf(name, NAME_SIZE, "cpu%d", i);
          object_initialize_child(obj, name, &s->cpu[i],
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
                              TYPE_A15MPCORE_PRIV);
      /*
 -     * GPIOs 1 to 7
 +     * GPIOs
       */
      for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
          snprintf(name, NAME_SIZE, "gpio%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      }
      /*
 -     * GPT1, 2, 3, 4
 +     * GPTs
       */
      for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
          snprintf(name, NAME_SIZE, "gpt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
       */
      object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
 +    /*
 +     * ECSPIs
 +     */
      for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
          snprintf(name, NAME_SIZE, "spi%d", i + 1);
          object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
      }
 -
 +    /*
 +     * I2Cs
 +     */
      for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
          snprintf(name, NAME_SIZE, "i2c%d", i + 1);
          object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
      }
      /*
 -     * UART
 +     * UARTs
       */
      for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
              snprintf(name, NAME_SIZE, "uart%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      }
      /*
 -     * Ethernet
 +     * Ethernets
       */
      for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
              snprintf(name, NAME_SIZE, "eth%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      }
      /*
 -     * SDHCI
 +     * SDHCIs
       */
      for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
              snprintf(name, NAME_SIZE, "usdhc%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
      /*
 -     * Watchdog
 +     * Watchdogs
       */
      for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
              snprintf(name, NAME_SIZE, "wdt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
       */
      object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
 +    /*
 +     * PCIE
 +     */
      object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
 +    /*
 +     * USBs
 +     */
      for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
          snprintf(name, NAME_SIZE, "usb%d", i);
          object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
          return;
      }
-@@ -XXX,XX +XXX,XX @@ static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri,
-     trace_gicv3_icv_eoir_write(ri->crm == 8 ? 0 : 1,
++    /*
-                                gicv3_redist_affid(cs), value);
++     * CPUs
++     */
--    if (irq >= cs->gic->num_irq) {
+     for (i = 0; i < smp_cpus; i++) {
-+    if (irq >= GICV3_MAXIRQ) {
+         o = OBJECT(&s->cpu[i]);
-         /* Also catches special interrupt numbers and LPIs */
-         return;
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
-     }
+      * A7MPCORE DAP
       */
      create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR,
 -                                0x100000);
 +                                FSL_IMX7_A7MPCORE_DAP_SIZE);
      /*
 -     * GPT1, 2, 3, 4
 +     * GPTs
       */
      for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
          static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
                                              FSL_IMX7_GPTn_IRQ[i]));
      }
 +    /*
 +     * GPIOs
 +     */
      for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
          static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = {
              FSL_IMX7_GPIO1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      /*
       * IOMUXC and IOMUXC_LPSR
       */
 -    for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) {
 -        static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = {
 -            FSL_IMX7_IOMUXC_ADDR,
 -            FSL_IMX7_IOMUXC_LPSR_ADDR,
 -        };
 -
 -        snprintf(name, NAME_SIZE, "iomuxc%d", i);
 -        create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i],
 -                                    FSL_IMX7_IOMUXCn_SIZE);
 -    }
 +    create_unimplemented_device("iomuxc", FSL_IMX7_IOMUXC_ADDR,
 +                                FSL_IMX7_IOMUXC_SIZE);
 +    create_unimplemented_device("iomuxc_lspr", FSL_IMX7_IOMUXC_LPSR_ADDR,
 +                                FSL_IMX7_IOMUXC_LPSR_SIZE);
      /*
       * CCM
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
      sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
 -    /* Initialize all ECSPI */
 +    /*
 +     * ECSPIs
 +     */
      for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
          static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = {
              FSL_IMX7_ECSPI1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
                                              FSL_IMX7_SPIn_IRQ[i]));
      }
 +    /*
 +     * I2Cs
 +     */
      for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
          static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = {
              FSL_IMX7_I2C1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      }
      /*
 -     * UART
 +     * UARTs
       */
      for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
          static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      }
      /*
 -     * Ethernet
 +     * Ethernets
       *
       * We must use two loops since phy_connected affects the other interface
       * and we have to set all properties before calling sysbus_realize().
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      }
      /*
 -     * USDHC
 +     * USDHCs
       */
      for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
          static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
       * SNVS
       */
      sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
 -    sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_HP_ADDR);
      /*
       * SRC
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
      /*
 -     * Watchdog
 +     * Watchdogs
       */
      for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
          static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE);
      /*
 -     * PWM
 +     * PWMs
       */
 -    create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE);
 -    create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE);
 -    create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE);
 -    create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE);
 +    for (i = 0; i < FSL_IMX7_NUM_PWMS; i++) {
 +        static const hwaddr FSL_IMX7_PWMn_ADDR[FSL_IMX7_NUM_PWMS] = {
 +            FSL_IMX7_PWM1_ADDR,
 +            FSL_IMX7_PWM2_ADDR,
 +            FSL_IMX7_PWM3_ADDR,
 +            FSL_IMX7_PWM4_ADDR,
 +        };
 +
 +        snprintf(name, NAME_SIZE, "pwm%d", i);
 +        create_unimplemented_device(name, FSL_IMX7_PWMn_ADDR[i],
 +                                    FSL_IMX7_PWMn_SIZE);
 +    }
      /*
 -     * CAN
 +     * CANs
       */
 -    create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE);
 -    create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE);
 +    for (i = 0; i < FSL_IMX7_NUM_CANS; i++) {
 +        static const hwaddr FSL_IMX7_CANn_ADDR[FSL_IMX7_NUM_CANS] = {
 +            FSL_IMX7_CAN1_ADDR,
 +            FSL_IMX7_CAN2_ADDR,
 +        };
 +
 +        snprintf(name, NAME_SIZE, "can%d", i);
 +        create_unimplemented_device(name, FSL_IMX7_CANn_ADDR[i],
 +                                    FSL_IMX7_CANn_SIZE);
 +    }
      /*
 -     * SAI (Audio SSI (Synchronous Serial Interface))
 +     * SAIs (Audio SSI (Synchronous Serial Interface))
       */
 -    create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR, FSL_IMX7_SAIn_SIZE);
 -    create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR, FSL_IMX7_SAIn_SIZE);
 -    create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR, FSL_IMX7_SAIn_SIZE);
 +    for (i = 0; i < FSL_IMX7_NUM_SAIS; i++) {
 +        static const hwaddr FSL_IMX7_SAIn_ADDR[FSL_IMX7_NUM_SAIS] = {
 +            FSL_IMX7_SAI1_ADDR,
 +            FSL_IMX7_SAI2_ADDR,
 +            FSL_IMX7_SAI3_ADDR,
 +        };
 +
 +        snprintf(name, NAME_SIZE, "sai%d", i);
 +        create_unimplemented_device(name, FSL_IMX7_SAIn_ADDR[i],
 +                                    FSL_IMX7_SAIn_SIZE);
 +    }
      /*
       * OCOTP
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
                                  FSL_IMX7_OCOTP_SIZE);
 +    /*
 +     * GPR
 +     */
      sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
 -    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_IOMUXC_GPR_ADDR);
 +    /*
 +     * PCIE
 +     */
      sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
      sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ);
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
 -
 +    /*
 +     * USBs
 +     */
      for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
          static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = {
              FSL_IMX7_USBMISC1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
       */
      create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
                                  FSL_IMX7_PCIE_PHY_SIZE);
 +
  }
  static Property fsl_imx7_properties[] = {
 --
-.20.1
+.34.1

-[PULL 14/17] hw/gpio/pl061: Document a shortcoming in our implementation
+[PULL 15/24] Add i.MX7 missing TZ devices and memory regions
-The Luminary PL061s in the Stellaris LM3S9695 don't all have the same
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
 reset value for GPIOPUR.  We can get away with not letting the board
 configure the PUR reset value because we don't actually wire anything
 up to the lines which should reset to pull-up.  Add a comment noting
 this omission.
+* Add TZASC as unimplemented device.
+  - Allow bare metal application to access this (unimplemented) device
+* Add CSU as unimplemented device.
+  - Allow bare metal application to access this (unimplemented) device
+* Add various memory segments
+  - OCRAM
+  - OCRAM EPDC
+  - OCRAM PXP
+  - OCRAM S
+  - ROM
+  - CAAM
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: f887a3483996ba06d40bd62ffdfb0ecf68621987.1692964892.git.jcd@tribudubois.net
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 ---
- hw/gpio/pl061.c | 9 +++++++++
+ include/hw/arm/fsl-imx7.h |  7 +++++
-file changed, 9 insertions(+)
+ hw/arm/fsl-imx7.c         | 63 +++++++++++++++++++++++++++++++++++++++
 files changed, 70 insertions(+)
-diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
+diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/gpio/pl061.c
+--- a/include/hw/arm/fsl-imx7.h
-+++ b/hw/gpio/pl061.c
++++ b/include/hw/arm/fsl-imx7.h
-@@ -XXX,XX +XXX,XX @@ static void pl061_enter_reset(Object *obj, ResetType type)
+@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
-     trace_pl061_reset(DEVICE(s)->canonical_path);
+     IMX7GPRState       gpr;
+     ChipideaState      usb[FSL_IMX7_NUM_USBS];
-     /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */
+     DesignwarePCIEHost pcie;
 +    MemoryRegion       rom;
 +    MemoryRegion       caam;
 +    MemoryRegion       ocram;
 +    MemoryRegion       ocram_epdc;
 +    MemoryRegion       ocram_pxp;
 +    MemoryRegion       ocram_s;
 +
      uint32_t           phy_num[FSL_IMX7_NUM_ETHS];
      bool               phy_connected[FSL_IMX7_NUM_ETHS];
  };
 diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/fsl-imx7.c
 +++ b/hw/arm/fsl-imx7.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
                                  FSL_IMX7_PCIE_PHY_SIZE);
 +    /*
 +     * CSU
 +     */
 +    create_unimplemented_device("csu", FSL_IMX7_CSU_ADDR,
 +                                FSL_IMX7_CSU_SIZE);
 +
 +    /*
-+     * FIXME: For the LM3S6965, not all of the PL061 instances have the
++     * TZASC
 +     * same reset values for GPIOPUR, GPIOAFSEL and GPIODEN, so in theory
 +     * we should allow the board to configure these via properties.
 +     * In practice, we don't wire anything up to the affected GPIO lines
 +     * (PB7, PC0, PC1, PC2, PC3 -- they're used for JTAG), so we can
 +     * get away with this inaccuracy.
 +     */
-     s->data = 0;
++    create_unimplemented_device("tzasc", FSL_IMX7_TZASC_ADDR,
-     s->old_in_data = 0;
++                                FSL_IMX7_TZASC_SIZE);
-     s->dir = 0;
++
 +    /*
 +     * OCRAM memory
 +     */
 +    memory_region_init_ram(&s->ocram, NULL, "imx7.ocram",
 +                           FSL_IMX7_OCRAM_MEM_SIZE,
 +                           &error_abort);
 +    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_MEM_ADDR,
 +                                &s->ocram);
 +
 +    /*
 +     * OCRAM EPDC memory
 +     */
 +    memory_region_init_ram(&s->ocram_epdc, NULL, "imx7.ocram_epdc",
 +                           FSL_IMX7_OCRAM_EPDC_SIZE,
 +                           &error_abort);
 +    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_EPDC_ADDR,
 +                                &s->ocram_epdc);
 +
 +    /*
 +     * OCRAM PXP memory
 +     */
 +    memory_region_init_ram(&s->ocram_pxp, NULL, "imx7.ocram_pxp",
 +                           FSL_IMX7_OCRAM_PXP_SIZE,
 +                           &error_abort);
 +    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_PXP_ADDR,
 +                                &s->ocram_pxp);
 +
 +    /*
 +     * OCRAM_S memory
 +     */
 +    memory_region_init_ram(&s->ocram_s, NULL, "imx7.ocram_s",
 +                           FSL_IMX7_OCRAM_S_SIZE,
 +                           &error_abort);
 +    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_S_ADDR,
 +                                &s->ocram_s);
 +
 +    /*
 +     * ROM memory
 +     */
 +    memory_region_init_rom(&s->rom, OBJECT(dev), "imx7.rom",
 +                           FSL_IMX7_ROM_SIZE, &error_abort);
 +    memory_region_add_subregion(get_system_memory(), FSL_IMX7_ROM_ADDR,
 +                                &s->rom);
 +
 +    /*
 +     * CAAM memory
 +     */
 +    memory_region_init_rom(&s->caam, OBJECT(dev), "imx7.caam",
 +                           FSL_IMX7_CAAM_MEM_SIZE, &error_abort);
 +    memory_region_add_subregion(get_system_memory(), FSL_IMX7_CAAM_MEM_ADDR,
 +                                &s->caam);
  }
  static Property fsl_imx7_properties[] = {
 --
-.20.1
+.34.1

-[PULL 01/17] stm32f100: Add the stm32f100 SoC
+[PULL 16/24] Add i.MX7 SRC device implementation
-From: Alexandre Iooss <erdnaxe@crans.org>
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
-This SoC is similar to stm32f205 SoC.
+The SRC device is normally used to start the secondary CPU.
-This will be used by the STM32VLDISCOVERY to create a machine.
+When running Linux directly, QEMU is emulating a PSCI interface that UBOOT
-Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
+is installing at boot time and therefore the fact that the SRC device is
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+unimplemented is hidden as Qemu respond directly to PSCI requets without
-Message-id: 20210617165647.2575955-2-erdnaxe@crans.org
+using the SRC device.
 But if you try to run a more bare metal application (maybe uboot itself),
 then it is not possible to start the secondary CPU as the SRC is an
 unimplemented device.
 This patch adds the ability to start the secondary CPU through the SRC
 device so that you can use this feature in bare metal applications.
 Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: ce9a0162defd2acee5dc7f8a674743de0cded569.1692964892.git.jcd@tribudubois.net
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/stm32f100_soc.h |  57 +++++++++++
+ include/hw/arm/fsl-imx7.h  |   3 +-
- hw/arm/stm32f100_soc.c         | 182 +++++++++++++++++++++++++++++++++
+ include/hw/misc/imx7_src.h |  66 +++++++++
- MAINTAINERS                    |   6 ++
+ hw/arm/fsl-imx7.c          |   8 +-
- hw/arm/Kconfig                 |   6 ++
+ hw/misc/imx7_src.c         | 276 +++++++++++++++++++++++++++++++++++++
- hw/arm/meson.build             |   1 +
+ hw/misc/meson.build        |   1 +
-files changed, 252 insertions(+)
+ hw/misc/trace-events       |   4 +
- create mode 100644 include/hw/arm/stm32f100_soc.h
+files changed, 356 insertions(+), 2 deletions(-)
- create mode 100644 hw/arm/stm32f100_soc.c
+ create mode 100644 include/hw/misc/imx7_src.h
+ create mode 100644 hw/misc/imx7_src.c
-diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h
 diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/fsl-imx7.h
 +++ b/include/hw/arm/fsl-imx7.h
@@ -XXX,XX +XXX,XX @@
  #include "hw/misc/imx7_ccm.h"
  #include "hw/misc/imx7_snvs.h"
  #include "hw/misc/imx7_gpr.h"
 +#include "hw/misc/imx7_src.h"
  #include "hw/watchdog/wdt_imx2.h"
  #include "hw/gpio/imx_gpio.h"
  #include "hw/char/imx_serial.h"
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
      IMX7CCMState       ccm;
      IMX7AnalogState    analog;
      IMX7SNVSState      snvs;
 +    IMX7SRCState       src;
      IMXGPCv2State      gpcv2;
      IMXSPIState        spi[FSL_IMX7_NUM_ECSPIS];
      IMXI2CState        i2c[FSL_IMX7_NUM_I2CS];
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
      FSL_IMX7_GPC_ADDR             = 0x303A0000,
      FSL_IMX7_SRC_ADDR             = 0x30390000,
 -    FSL_IMX7_SRC_SIZE             = (4 * KiB),
      FSL_IMX7_CCM_ADDR             = 0x30380000,
 diff --git a/include/hw/misc/imx7_src.h b/include/hw/misc/imx7_src.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/include/hw/arm/stm32f100_soc.h
++++ b/include/hw/misc/imx7_src.h
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * STM32F100 SoC
++ * IMX7 System Reset Controller
 + *
-+ * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
++ * Copyright (C) 2023 Jean-Christophe Dubois <jcd@tribudubois.net>
 + *
-+ * Permission is hereby granted, free of charge, to any person obtaining a copy
++ * This work is licensed under the terms of the GNU GPL, version 2 or later.
-+ * of this software and associated documentation files (the "Software"), to deal
++ * See the COPYING file in the top-level directory.
 + * in the Software without restriction, including without limitation the rights
 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 + * copies of the Software, and to permit persons to whom the Software is
 + * furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice shall be included in
 + * all copies or substantial portions of the Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
 +
-+#ifndef HW_ARM_STM32F100_SOC_H
++#ifndef IMX7_SRC_H
-+#define HW_ARM_STM32F100_SOC_H
++#define IMX7_SRC_H
 +
-+#include "hw/char/stm32f2xx_usart.h"
++#include "hw/sysbus.h"
-+#include "hw/ssi/stm32f2xx_spi.h"
++#include "qemu/bitops.h"
 +#include "hw/arm/armv7m.h"
 +#include "qom/object.h"
 +
-+#define TYPE_STM32F100_SOC "stm32f100-soc"
++#define SRC_SCR 0
-+OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC)
++#define SRC_A7RCR0 1
-+
++#define SRC_A7RCR1 2
-+#define STM_NUM_USARTS 3
++#define SRC_M4RCR 3
-+#define STM_NUM_SPIS 2
++#define SRC_ERCR 5
-+
++#define SRC_HSICPHY_RCR 7
-+#define FLASH_BASE_ADDRESS 0x08000000
++#define SRC_USBOPHY1_RCR 8
-+#define FLASH_SIZE (128 * 1024)
++#define SRC_USBOPHY2_RCR 9
-+#define SRAM_BASE_ADDRESS 0x20000000
++#define SRC_MPIPHY_RCR 10
-+#define SRAM_SIZE (8 * 1024)
++#define SRC_PCIEPHY_RCR 11
-+
++#define SRC_SBMR1 22
-+struct STM32F100State {
++#define SRC_SRSR 23
-+    /*< private >*/
++#define SRC_SISR 26
 +#define SRC_SIMR 27
 +#define SRC_SBMR2 28
 +#define SRC_GPR1 29
 +#define SRC_GPR2 30
 +#define SRC_GPR3 31
 +#define SRC_GPR4 32
 +#define SRC_GPR5 33
 +#define SRC_GPR6 34
 +#define SRC_GPR7 35
 +#define SRC_GPR8 36
 +#define SRC_GPR9 37
 +#define SRC_GPR10 38
 +#define SRC_MAX 39
 +
 +/* SRC_A7SCR1 */
 +#define R_CORE1_ENABLE_SHIFT     1
 +#define R_CORE1_ENABLE_LENGTH    1
 +/* SRC_A7SCR0 */
 +#define R_CORE1_RST_SHIFT        5
 +#define R_CORE1_RST_LENGTH       1
 +#define R_CORE0_RST_SHIFT        4
 +#define R_CORE0_RST_LENGTH       1
 +
 +#define TYPE_IMX7_SRC "imx7.src"
 +OBJECT_DECLARE_SIMPLE_TYPE(IMX7SRCState, IMX7_SRC)
 +
 +struct IMX7SRCState {
 +    /* <private> */
 +    SysBusDevice parent_obj;
 +
-+    /*< public >*/
++    /* <public> */
-+    char *cpu_type;
++    MemoryRegion iomem;
 +
-+    ARMv7MState armv7m;
++    uint32_t regs[SRC_MAX];
 +
 +    STM32F2XXUsartState usart[STM_NUM_USARTS];
 +    STM32F2XXSPIState spi[STM_NUM_SPIS];
 +};
 +
-+#endif
++#endif /* IMX7_SRC_H */
-diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c
+diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/fsl-imx7.c
 +++ b/hw/arm/fsl-imx7.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
       */
      object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
 +    /*
 +     * SRC
 +     */
 +    object_initialize_child(obj, "src", &s->src, TYPE_IMX7_SRC);
 +
      /*
       * ECSPIs
       */
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      /*
       * SRC
       */
 -    create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
 +    sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX7_SRC_ADDR);
      /*
       * Watchdogs
 diff --git a/hw/misc/imx7_src.c b/hw/misc/imx7_src.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/hw/arm/stm32f100_soc.c
++++ b/hw/misc/imx7_src.c
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * STM32F100 SoC
++ * IMX7 System Reset Controller
 + *
-+ * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
++ * Copyright (c) 2023 Jean-Christophe Dubois <jcd@tribudubois.net>
 + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
 + *
-+ * Permission is hereby granted, free of charge, to any person obtaining a copy
++ * This work is licensed under the terms of the GNU GPL, version 2 or later.
-+ * of this software and associated documentation files (the "Software"), to deal
++ * See the COPYING file in the top-level directory.
 + * in the Software without restriction, including without limitation the rights
 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 + * copies of the Software, and to permit persons to whom the Software is
 + * furnished to do so, subject to the following conditions:
 + *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-+ * THE SOFTWARE.
 + */
 +
 +#include "qemu/osdep.h"
-+#include "qapi/error.h"
++#include "hw/misc/imx7_src.h"
 +#include "migration/vmstate.h"
 +#include "qemu/bitops.h"
 +#include "qemu/log.h"
 +#include "qemu/main-loop.h"
 +#include "qemu/module.h"
-+#include "hw/arm/boot.h"
++#include "target/arm/arm-powerctl.h"
-+#include "exec/address-spaces.h"
++#include "hw/core/cpu.h"
-+#include "hw/arm/stm32f100_soc.h"
++#include "hw/registerfields.h"
-+#include "hw/qdev-properties.h"
++
-+#include "hw/misc/unimp.h"
++#include "trace.h"
-+#include "sysemu/sysemu.h"
++
-+
++static const char *imx7_src_reg_name(uint32_t reg)
-+/* stm32f100_soc implementation is derived from stm32f205_soc */
++{
-+
++    static char unknown[20];
-+static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40013800, 0x40004400,
++
-+    0x40004800 };
++    switch (reg) {
-+static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800 };
++    case SRC_SCR:
-+
++        return "SRC_SCR";
-+static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39};
++    case SRC_A7RCR0:
-+static const int spi_irq[STM_NUM_SPIS] = {35, 36};
++        return "SRC_A7RCR0";
-+
++    case SRC_A7RCR1:
-+static void stm32f100_soc_initfn(Object *obj)
++        return "SRC_A7RCR1";
-+{
++    case SRC_M4RCR:
-+    STM32F100State *s = STM32F100_SOC(obj);
++        return "SRC_M4RCR";
-+    int i;
++    case SRC_ERCR:
-+
++        return "SRC_ERCR";
-+    object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
++    case SRC_HSICPHY_RCR:
-+
++        return "SRC_HSICPHY_RCR";
-+    for (i = 0; i < STM_NUM_USARTS; i++) {
++    case SRC_USBOPHY1_RCR:
-+        object_initialize_child(obj, "usart[*]", &s->usart[i],
++        return "SRC_USBOPHY1_RCR";
-+                                TYPE_STM32F2XX_USART);
++    case SRC_USBOPHY2_RCR:
 +        return "SRC_USBOPHY2_RCR";
 +    case SRC_PCIEPHY_RCR:
 +        return "SRC_PCIEPHY_RCR";
 +    case SRC_SBMR1:
 +        return "SRC_SBMR1";
 +    case SRC_SRSR:
 +        return "SRC_SRSR";
 +    case SRC_SISR:
 +        return "SRC_SISR";
 +    case SRC_SIMR:
 +        return "SRC_SIMR";
 +    case SRC_SBMR2:
 +        return "SRC_SBMR2";
 +    case SRC_GPR1:
 +        return "SRC_GPR1";
 +    case SRC_GPR2:
 +        return "SRC_GPR2";
 +    case SRC_GPR3:
 +        return "SRC_GPR3";
 +    case SRC_GPR4:
 +        return "SRC_GPR4";
 +    case SRC_GPR5:
 +        return "SRC_GPR5";
 +    case SRC_GPR6:
 +        return "SRC_GPR6";
 +    case SRC_GPR7:
 +        return "SRC_GPR7";
 +    case SRC_GPR8:
 +        return "SRC_GPR8";
 +    case SRC_GPR9:
 +        return "SRC_GPR9";
 +    case SRC_GPR10:
 +        return "SRC_GPR10";
 +    default:
 +        sprintf(unknown, "%u ?", reg);
 +        return unknown;
 +    }
-+
++}
-+    for (i = 0; i < STM_NUM_SPIS; i++) {
++
-+        object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
++static const VMStateDescription vmstate_imx7_src = {
 +    .name = TYPE_IMX7_SRC,
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32_ARRAY(regs, IMX7SRCState, SRC_MAX),
 +        VMSTATE_END_OF_LIST()
 +    },
 +};
 +
 +static void imx7_src_reset(DeviceState *dev)
 +{
 +    IMX7SRCState *s = IMX7_SRC(dev);
 +
 +    memset(s->regs, 0, sizeof(s->regs));
 +
 +    /* Set reset values */
 +    s->regs[SRC_SCR] = 0xA0;
 +    s->regs[SRC_SRSR] = 0x1;
 +    s->regs[SRC_SIMR] = 0x1F;
 +}
 +
 +static uint64_t imx7_src_read(void *opaque, hwaddr offset, unsigned size)
 +{
 +    uint32_t value = 0;
 +    IMX7SRCState *s = (IMX7SRCState *)opaque;
 +    uint32_t index = offset >> 2;
 +
 +    if (index < SRC_MAX) {
 +        value = s->regs[index];
 +    } else {
 +        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 +                      HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset);
 +    }
-+}
++
-+
++    trace_imx7_src_read(imx7_src_reg_name(index), value);
-+static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
++
-+{
++    return value;
-+    STM32F100State *s = STM32F100_SOC(dev_soc);
++}
-+    DeviceState *dev, *armv7m;
++
-+    SysBusDevice *busdev;
++
-+    int i;
++/*
-+
++ * The reset is asynchronous so we need to defer clearing the reset
-+    MemoryRegion *system_memory = get_system_memory();
++ * bit until the work is completed.
-+    MemoryRegion *sram = g_new(MemoryRegion, 1);
++ */
-+    MemoryRegion *flash = g_new(MemoryRegion, 1);
++
-+    MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
++struct SRCSCRResetInfo {
-+
++    IMX7SRCState *s;
-+    /*
++    uint32_t reset_bit;
-+     * Init flash region
++};
-+     * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0
++
-+     */
++static void imx7_clear_reset_bit(CPUState *cpu, run_on_cpu_data data)
-+    memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F100.flash",
++{
-+                           FLASH_SIZE, &error_fatal);
++    struct SRCSCRResetInfo *ri = data.host_ptr;
-+    memory_region_init_alias(flash_alias, OBJECT(dev_soc),
++    IMX7SRCState *s = ri->s;
-+                             "STM32F100.flash.alias", flash, 0, FLASH_SIZE);
++
-+    memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
++    assert(qemu_mutex_iothread_locked());
-+    memory_region_add_subregion(system_memory, 0, flash_alias);
++
-+
++    s->regs[SRC_A7RCR0] = deposit32(s->regs[SRC_A7RCR0], ri->reset_bit, 1, 0);
-+    /* Init SRAM region */
++
-+    memory_region_init_ram(sram, NULL, "STM32F100.sram", SRAM_SIZE,
++    trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]);
-+                           &error_fatal);
++
-+    memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
++    g_free(ri);
-+
++}
-+    /* Init ARMv7m */
++
-+    armv7m = DEVICE(&s->armv7m);
++static void imx7_defer_clear_reset_bit(uint32_t cpuid,
-+    qdev_prop_set_uint32(armv7m, "num-irq", 61);
++                                       IMX7SRCState *s,
-+    qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
++                                       uint32_t reset_shift)
-+    qdev_prop_set_bit(armv7m, "enable-bitband", true);
++{
-+    object_property_set_link(OBJECT(&s->armv7m), "memory",
++    struct SRCSCRResetInfo *ri;
-+                             OBJECT(get_system_memory()), &error_abort);
++    CPUState *cpu = arm_get_cpu_by_id(cpuid);
-+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
++
 +    if (!cpu) {
 +        return;
 +    }
 +
-+    /* Attach UART (uses USART registers) and USART controllers */
++    ri = g_new(struct SRCSCRResetInfo, 1);
-+    for (i = 0; i < STM_NUM_USARTS; i++) {
++    ri->s = s;
-+        dev = DEVICE(&(s->usart[i]));
++    ri->reset_bit = reset_shift;
-+        qdev_prop_set_chr(dev, "chardev", serial_hd(i));
++
-+        if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) {
++    async_run_on_cpu(cpu, imx7_clear_reset_bit, RUN_ON_CPU_HOST_PTR(ri));
-+            return;
++}
 +
 +
 +static void imx7_src_write(void *opaque, hwaddr offset, uint64_t value,
 +                           unsigned size)
 +{
 +    IMX7SRCState *s = (IMX7SRCState *)opaque;
 +    uint32_t index = offset >> 2;
 +    long unsigned int change_mask;
 +    uint32_t current_value = value;
 +
 +    if (index >= SRC_MAX) {
 +        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 +                      HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset);
 +        return;
 +    }
 +
 +    trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]);
 +
 +    change_mask = s->regs[index] ^ (uint32_t)current_value;
 +
 +    switch (index) {
 +    case SRC_A7RCR0:
 +        if (FIELD_EX32(change_mask, CORE0, RST)) {
 +            arm_reset_cpu(0);
 +            imx7_defer_clear_reset_bit(0, s, R_CORE0_RST_SHIFT);
 +        }
-+        busdev = SYS_BUS_DEVICE(dev);
++        if (FIELD_EX32(change_mask, CORE1, RST)) {
-+        sysbus_mmio_map(busdev, 0, usart_addr[i]);
++            arm_reset_cpu(1);
-+        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
++            imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT);
 +        }
 +        s->regs[index] = current_value;
 +        break;
 +    case SRC_A7RCR1:
 +        /*
 +         * On real hardware when the system reset controller starts a
 +         * secondary CPU it runs through some boot ROM code which reads
 +         * the SRC_GPRX registers controlling the start address and branches
 +         * to it.
 +         * Here we are taking a short cut and branching directly to the
 +         * requested address (we don't want to run the boot ROM code inside
 +         * QEMU)
 +         */
 +        if (FIELD_EX32(change_mask, CORE1, ENABLE)) {
 +            if (FIELD_EX32(current_value, CORE1, ENABLE)) {
 +                /* CORE 1 is brought up */
 +                arm_set_cpu_on(1, s->regs[SRC_GPR3], s->regs[SRC_GPR4],
 +                               3, false);
 +            } else {
 +                /* CORE 1 is shut down */
 +                arm_set_cpu_off(1);
 +            }
 +            /* We clear the reset bits as the processor changed state */
 +            imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT);
 +            clear_bit(R_CORE1_RST_SHIFT, &change_mask);
 +        }
 +        s->regs[index] = current_value;
 +        break;
 +    default:
 +        s->regs[index] = current_value;
 +        break;
 +    }
-+
++}
-+    /* SPI 1 and 2 */
++
-+    for (i = 0; i < STM_NUM_SPIS; i++) {
++static const struct MemoryRegionOps imx7_src_ops = {
-+        dev = DEVICE(&(s->spi[i]));
++    .read = imx7_src_read,
-+        if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
++    .write = imx7_src_write,
-+            return;
++    .endianness = DEVICE_NATIVE_ENDIAN,
-+        }
++    .valid = {
-+        busdev = SYS_BUS_DEVICE(dev);
++        /*
-+        sysbus_mmio_map(busdev, 0, spi_addr[i]);
++         * Our device would not work correctly if the guest was doing
-+        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
++         * unaligned access. This might not be a limitation on the real
-+    }
++         * device but in practice there is no reason for a guest to access
-+
++         * this device unaligned.
-+    create_unimplemented_device("timer[2]",  0x40000000, 0x400);
++         */
-+    create_unimplemented_device("timer[3]",  0x40000400, 0x400);
++        .min_access_size = 4,
-+    create_unimplemented_device("timer[4]",  0x40000800, 0x400);
++        .max_access_size = 4,
-+    create_unimplemented_device("timer[6]",  0x40001000, 0x400);
++        .unaligned = false,
-+    create_unimplemented_device("timer[7]",  0x40001400, 0x400);
++    },
 +    create_unimplemented_device("RTC",       0x40002800, 0x400);
 +    create_unimplemented_device("WWDG",      0x40002C00, 0x400);
 +    create_unimplemented_device("IWDG",      0x40003000, 0x400);
 +    create_unimplemented_device("I2C1",      0x40005400, 0x400);
 +    create_unimplemented_device("I2C2",      0x40005800, 0x400);
 +    create_unimplemented_device("BKP",       0x40006C00, 0x400);
 +    create_unimplemented_device("PWR",       0x40007000, 0x400);
 +    create_unimplemented_device("DAC",       0x40007400, 0x400);
 +    create_unimplemented_device("CEC",       0x40007800, 0x400);
 +    create_unimplemented_device("AFIO",      0x40010000, 0x400);
 +    create_unimplemented_device("EXTI",      0x40010400, 0x400);
 +    create_unimplemented_device("GPIOA",     0x40010800, 0x400);
 +    create_unimplemented_device("GPIOB",     0x40010C00, 0x400);
 +    create_unimplemented_device("GPIOC",     0x40011000, 0x400);
 +    create_unimplemented_device("GPIOD",     0x40011400, 0x400);
 +    create_unimplemented_device("GPIOE",     0x40011800, 0x400);
 +    create_unimplemented_device("ADC1",      0x40012400, 0x400);
 +    create_unimplemented_device("timer[1]",  0x40012C00, 0x400);
 +    create_unimplemented_device("timer[15]", 0x40014000, 0x400);
 +    create_unimplemented_device("timer[16]", 0x40014400, 0x400);
 +    create_unimplemented_device("timer[17]", 0x40014800, 0x400);
 +    create_unimplemented_device("DMA",       0x40020000, 0x400);
 +    create_unimplemented_device("RCC",       0x40021000, 0x400);
 +    create_unimplemented_device("Flash Int", 0x40022000, 0x400);
 +    create_unimplemented_device("CRC",       0x40023000, 0x400);
 +}
 +
 +static Property stm32f100_soc_properties[] = {
 +    DEFINE_PROP_STRING("cpu-type", STM32F100State, cpu_type),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
-+static void stm32f100_soc_class_init(ObjectClass *klass, void *data)
++static void imx7_src_realize(DeviceState *dev, Error **errp)
 +{
 +    IMX7SRCState *s = IMX7_SRC(dev);
 +
 +    memory_region_init_io(&s->iomem, OBJECT(dev), &imx7_src_ops, s,
 +                          TYPE_IMX7_SRC, 0x1000);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
 +}
 +
 +static void imx7_src_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
-+    dc->realize = stm32f100_soc_realize;
++    dc->realize = imx7_src_realize;
-+    device_class_set_props(dc, stm32f100_soc_properties);
++    dc->reset = imx7_src_reset;
-+}
++    dc->vmsd = &vmstate_imx7_src;
-+
++    dc->desc = "i.MX6 System Reset Controller";
-+static const TypeInfo stm32f100_soc_info = {
++}
-+    .name          = TYPE_STM32F100_SOC,
++
 +static const TypeInfo imx7_src_info = {
 +    .name          = TYPE_IMX7_SRC,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
-+    .instance_size = sizeof(STM32F100State),
++    .instance_size = sizeof(IMX7SRCState),
-+    .instance_init = stm32f100_soc_initfn,
++    .class_init    = imx7_src_class_init,
 +    .class_init    = stm32f100_soc_class_init,
 +};
 +
-+static void stm32f100_soc_types(void)
++static void imx7_src_register_types(void)
 +{
-+    type_register_static(&stm32f100_soc_info);
++    type_register_static(&imx7_src_info);
 +}
 +
-+type_init(stm32f100_soc_types)
++type_init(imx7_src_register_types)
-diff --git a/MAINTAINERS b/MAINTAINERS
+diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
---- a/MAINTAINERS
+--- a/hw/misc/meson.build
-+++ b/MAINTAINERS
++++ b/hw/misc/meson.build
-@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
+@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_IMX', if_true: files(
- S: Maintained
+   'imx6_src.c',
- F: hw/arm/virt-acpi-build.c
+   'imx6ul_ccm.c',
+   'imx7_ccm.c',
-+STM32F100
++  'imx7_src.c',
-+M: Alexandre Iooss <erdnaxe@crans.org>
+   'imx7_gpr.c',
-+L: qemu-arm@nongnu.org
+   'imx7_snvs.c',
-+S: Maintained
+   'imx_ccm.c',
-+F: hw/arm/stm32f100_soc.c
+diff --git a/hw/misc/trace-events b/hw/misc/trace-events
 +
  STM32F205
  M: Alistair Francis <alistair@alistair23.me>
  M: Peter Maydell <peter.maydell@linaro.org>
 diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/Kconfig
+--- a/hw/misc/trace-events
-+++ b/hw/arm/Kconfig
++++ b/hw/misc/trace-events
-@@ -XXX,XX +XXX,XX @@ config RASPI
+@@ -XXX,XX +XXX,XX @@ ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d"
-     select SDHCI
+ ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32
-     select USB_DWC2
+ ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32
-+config STM32F100_SOC
++# imx7_src.c
-+    bool
++imx7_src_read(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32
-+    select ARM_V7M
++imx7_src_write(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32
-+    select STM32F2XX_USART
++
-+    select STM32F2XX_SPI
+ # iotkit-sysinfo.c
-+
+ iotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
- config STM32F205_SOC
+ iotkit_sysinfo_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
      bool
      select ARM_V7M
 diff --git a/hw/arm/meson.build b/hw/arm/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/meson.build
 +++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c'))
  arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c'))
  arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))
  arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c', 'bcm2836.c', 'raspi.c'))
 +arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c'))
  arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c'))
  arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c'))
  arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c'))
 --
-.20.1
+.34.1

-[PULL 12/17] hw/arm/virt: Make PL061 GPIO lines pulled low, not high
+[PULL 17/24] target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS
-For the virt board we have two PL061 devices -- one for NonSecure which
+The architecture requires (R_TYTWB) that an attempt to return from EL3
-is inputs only, and one for Secure which is outputs only. For the former,
+when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This
-we don't care whether its outputs are pulled low or high when the line is
+enforces that the CPU can't ever be executing below EL3 with the
-configured as an input, because we don't connect them. For the latter,
+NSE,NS bits indicating an invalid security state.)
 we do care, because we wire the lines up to the gpio-pwr device, which
 assumes that level 1 means "do the action" and 1 means "do nothing".
 For consistency in case we add more outputs in future, configure both
 PL061s to pull GPIO lines down to 0.
-Reported-by: Maxim Uvarov <maxim.uvarov@linaro.org>
+We were missing this check; add it.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230807150618.101357-1-peter.maydell@linaro.org
 ---
- hw/arm/virt.c | 3 +++
+ target/arm/tcg/helper-a64.c | 9 +++++++++
-file changed, 3 insertions(+)
+file changed, 9 insertions(+)
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt.c
+--- a/target/arm/tcg/helper-a64.c
-+++ b/hw/arm/virt.c
++++ b/target/arm/tcg/helper-a64.c
-@@ -XXX,XX +XXX,XX @@ static void create_gpio_devices(const VirtMachineState *vms, int gpio,
+@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
-     MachineState *ms = MACHINE(vms);
+         spsr &= ~PSTATE_SS;
+     }
-     pl061_dev = qdev_new("pl061");
-+    /* Pull lines down to 0 if not driven by the PL061 */
++    /*
-+    qdev_prop_set_uint32(pl061_dev, "pullups", 0);
++     * FEAT_RME forbids return from EL3 with an invalid security state.
-+    qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff);
++     * We don't need an explicit check for FEAT_RME here because we enforce
-     s = SYS_BUS_DEVICE(pl061_dev);
++     * in scr_write() that you can't set the NSE bit without it.
-     sysbus_realize_and_unref(s, &error_fatal);
++     */
-     memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0));
++    if (cur_el == 3 && (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) == SCR_NSE) {
 +        goto illegal_return;
 +    }
 +
      new_el = el_from_spsr(spsr);
      if (new_el == -1) {
          goto illegal_return;
 --
-.20.1
+.34.1

-[PULL 11/17] hw/gpio/pl061: Make pullup/pulldown of outputs configurable
+[PULL 18/24] hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()
-The PL061 GPIO does not itself include pullup or pulldown resistors
+In the m48t59 device we almost always use 64-bit arithmetic when
-to set the value of a GPIO line treated as an output when it is
+dealing with time_t deltas.  The one exception is in set_alarm(),
-configured as an input (ie when the PL061 itself is not driving it).
+which currently uses a plain 'int' to hold the difference between two
-In real hardware it is up to the board to add suitable pullups or
+time_t values.  Switch to int64_t instead to avoid any possible
-pulldowns.  Currently our implementation hardwires this to "outputs
+overflow issues.
 pulled high", which is correct for some boards (eg the realview ones:
 see figure 3-29 in the "RealView Platform Baseboard for ARM926EJ-S
 User Guide" DUI0224I), but wrong for others.
 In particular, the wiring in the 'virt' board and the gpio-pwr device
 assumes that wires should be pulled low, because otherwise the
 pull-to-high will trigger a shutdown or reset action.  (The only
 reason this doesn't happen immediately on startup is due to another
 bug in the PL061, where we don't assert the GPIOs to the correct
 value on reset, but will do so as soon as the guest touches a
 register and pl061_update() gets called.)
 Add properties to the pl061 so the board can configure whether it
 wants GPIO lines to have pullup, pulldown, or neither.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 ---
- hw/gpio/pl061.c | 51 +++++++++++++++++++++++++++++++++++++++++++++----
+ hw/rtc/m48t59.c | 2 +-
-file changed, 47 insertions(+), 4 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
+diff --git a/hw/rtc/m48t59.c b/hw/rtc/m48t59.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/gpio/pl061.c
+--- a/hw/rtc/m48t59.c
-+++ b/hw/gpio/pl061.c
++++ b/hw/rtc/m48t59.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void alarm_cb (void *opaque)
-  *  + unnamed GPIO inputs 0..7: inputs to connect to the emulated GPIO lines
-  *  + unnamed GPIO outputs 0..7: the emulated GPIO lines, considered as
+ static void set_alarm(M48t59State *NVRAM)
   *    outputs
 + *  + QOM property "pullups": an integer defining whether non-floating lines
 + *    configured as inputs should be pulled up to logical 1 (ie whether in
 + *    real hardware they have a pullup resistor on the line out of the PL061).
 + *    This should be an 8-bit value, where bit 0 is 1 if GPIO line 0 should
 + *    be pulled high, bit 1 configures line 1, and so on. The default is 0xff,
 + *    indicating that all GPIO lines are pulled up to logical 1.
 + *  + QOM property "pulldowns": an integer defining whether non-floating lines
 + *    configured as inputs should be pulled down to logical 0 (ie whether in
 + *    real hardware they have a pulldown resistor on the line out of the PL061).
 + *    This should be an 8-bit value, where bit 0 is 1 if GPIO line 0 should
 + *    be pulled low, bit 1 configures line 1, and so on. The default is 0x0.
 + *    It is an error to set a bit in both "pullups" and "pulldowns". If a bit
 + *    is 0 in both, then the line is considered to be floating, and it will
 + *    not have qemu_set_irq() called on it when it is configured as an input.
   */
  #include "qemu/osdep.h"
  #include "hw/irq.h"
  #include "hw/sysbus.h"
 +#include "hw/qdev-properties.h"
  #include "migration/vmstate.h"
 +#include "qapi/error.h"
  #include "qemu/log.h"
  #include "qemu/module.h"
  #include "qom/object.h"
@@ -XXX,XX +XXX,XX @@ struct PL061State {
      qemu_irq irq;
      qemu_irq out[N_GPIOS];
      const unsigned char *id;
 +    /* Properties, for non-Luminary PL061 */
 +    uint32_t pullups;
 +    uint32_t pulldowns;
  };
  static const VMStateDescription vmstate_pl061 = {
@@ -XXX,XX +XXX,XX @@ static uint8_t pl061_floating(PL061State *s)
           */
          floating = ~(s->pur | s->pdr);
      } else {
 -        /* Assume outputs are pulled high. FIXME: this is board dependent. */
 -        floating = 0;
 +        floating = ~(s->pullups | s->pulldowns);
      }
      return floating & ~s->dir;
  }
@@ -XXX,XX +XXX,XX @@ static uint8_t pl061_pullups(PL061State *s)
           */
          pullups = s->pur;
      } else {
 -        /* Assume outputs are pulled high. FIXME: this is board dependent. */
 -        pullups = 0xff;
 +        pullups = s->pullups;
      }
      return pullups & ~s->dir;
  }
@@ -XXX,XX +XXX,XX @@ static void pl061_init(Object *obj)
      qdev_init_gpio_out(dev, s->out, N_GPIOS);
  }
 +static void pl061_realize(DeviceState *dev, Error **errp)
 +{
 +    PL061State *s = PL061(dev);
 +
 +    if (s->pullups > 0xff) {
 +        error_setg(errp, "pullups property must be between 0 and 0xff");
 +        return;
 +    }
 +    if (s->pulldowns > 0xff) {
 +        error_setg(errp, "pulldowns property must be between 0 and 0xff");
 +        return;
 +    }
 +    if (s->pullups & s->pulldowns) {
 +        error_setg(errp, "no bit may be set both in pullups and pulldowns");
 +        return;
 +    }
 +}
 +
 +static Property pl061_props[] = {
 +    DEFINE_PROP_UINT32("pullups", PL061State, pullups, 0xff),
 +    DEFINE_PROP_UINT32("pulldowns", PL061State, pulldowns, 0x0),
 +    DEFINE_PROP_END_OF_LIST()
 +};
 +
  static void pl061_class_init(ObjectClass *klass, void *data)
  {
-     DeviceClass *dc = DEVICE_CLASS(klass);
+-    int diff;
++    int64_t diff;
-     dc->vmsd = &vmstate_pl061;
+     if (NVRAM->alrm_timer != NULL) {
-     dc->reset = &pl061_reset;
+         timer_del(NVRAM->alrm_timer);
-+    dc->realize = pl061_realize;
+         diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
 +    device_class_set_props(dc, pl061_props);
  }
  static const TypeInfo pl061_info = {
 --
-.20.1
+.34.1

-[PULL 17/17] hw/intc: Improve formatting of MEMTX_ERROR guest error message
+[PULL 19/24] hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec
-From: Rebecca Cran <rebecca@nuviainc.com>
+In the twl92230 device, use int64_t for the two state fields
 sec_offset and alm_sec, because we set these to values that
 are either time_t or differences between two time_t values.
-Add a space in the message printed when gicr_read*/gicr_write* returns
+These fields aren't saved in vmstate anywhere, so we can
-MEMTX_ERROR in arm_gicv3_redist.c.
+safely widen them.
-Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20210706211432.31902-1-rebecca@nuviainc.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 ---
- hw/intc/arm_gicv3_redist.c | 4 ++--
+ hw/rtc/twl92230.c | 4 ++--
 file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
+diff --git a/hw/rtc/twl92230.c b/hw/rtc/twl92230.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_redist.c
+--- a/hw/rtc/twl92230.c
-+++ b/hw/intc/arm_gicv3_redist.c
++++ b/hw/rtc/twl92230.c
-@@ -XXX,XX +XXX,XX @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data,
+@@ -XXX,XX +XXX,XX @@ struct MenelausState {
-     if (r == MEMTX_ERROR) {
+         struct tm tm;
-         qemu_log_mask(LOG_GUEST_ERROR,
+         struct tm new;
-                       "%s: invalid guest read at offset " TARGET_FMT_plx
+         struct tm alm;
--                      "size %u\n", __func__, offset, size);
+-        int sec_offset;
-+                      " size %u\n", __func__, offset, size);
+-        int alm_sec;
-         trace_gicv3_redist_badread(gicv3_redist_affid(cs), offset,
++        int64_t sec_offset;
-                                    size, attrs.secure);
++        int64_t alm_sec;
-         /* The spec requires that reserved registers are RAZ/WI;
+         int next_comp;
-@@ -XXX,XX +XXX,XX @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data,
+     } rtc;
-     if (r == MEMTX_ERROR) {
+     uint16_t rtc_next_vmstate;
          qemu_log_mask(LOG_GUEST_ERROR,
                        "%s: invalid guest write at offset " TARGET_FMT_plx
 -                      "size %u\n", __func__, offset, size);
 +                      " size %u\n", __func__, offset, size);
          trace_gicv3_redist_badwrite(gicv3_redist_affid(cs), offset, data,
                                      size, attrs.secure);
          /* The spec requires that reserved registers are RAZ/WI;
 --
-.20.1
+.34.1

-[PULL 10/17] hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
+[PULL 20/24] hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference
-The Luminary variant of the PL061 has registers GPIOPUR and GPIOPDR
+In the aspeed_rtc device we store a difference between two time_t
-which lets the guest configure whether the GPIO lines are pull-up,
+values in an 'int'. This is not really correct when time_t could
-pull-down, or truly floating. Instead of assuming all lines are pulled
+be 64 bits. Enlarge the field to 'int64_t'.
 high, honour the PUR and PDR registers.
-For the plain PL061, continue to assume that lines have an external
+This is a migration compatibility break for the aspeed boards.
-pull-up resistor, as we did before.
+While we are changing the vmstate, remove the accidental
+duplicate of the offset field.
 The stellaris board actually relies on this behaviour -- the CD line
 of the ssd0323 display device is connected to GPIO output C7, and it
 is only because of a different bug which we're about to fix that we
 weren't incorrectly driving this line high on reset and putting the
 ssd0323 into data mode.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/gpio/pl061.c      | 58 +++++++++++++++++++++++++++++++++++++++++---
+ include/hw/rtc/aspeed_rtc.h | 2 +-
- hw/gpio/trace-events |  2 +-
+ hw/rtc/aspeed_rtc.c         | 5 ++---
-files changed, 55 insertions(+), 5 deletions(-)
+files changed, 3 insertions(+), 4 deletions(-)
-diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
+diff --git a/include/hw/rtc/aspeed_rtc.h b/include/hw/rtc/aspeed_rtc.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/gpio/pl061.c
+--- a/include/hw/rtc/aspeed_rtc.h
-+++ b/hw/gpio/pl061.c
++++ b/include/hw/rtc/aspeed_rtc.h
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl061 = {
+@@ -XXX,XX +XXX,XX @@ struct AspeedRtcState {
      qemu_irq irq;
      uint32_t reg[0x18];
 -    int offset;
 +    int64_t offset;
  };
 diff --git a/hw/rtc/aspeed_rtc.c b/hw/rtc/aspeed_rtc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/rtc/aspeed_rtc.c
 +++ b/hw/rtc/aspeed_rtc.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_rtc_ops = {
  static const VMStateDescription vmstate_aspeed_rtc = {
      .name = TYPE_ASPEED_RTC,
 -    .version_id = 1,
 +    .version_id = 2,
      .fields = (VMStateField[]) {
          VMSTATE_UINT32_ARRAY(reg, AspeedRtcState, 0x18),
 -        VMSTATE_INT32(offset, AspeedRtcState),
 -        VMSTATE_INT32(offset, AspeedRtcState),
 +        VMSTATE_INT64(offset, AspeedRtcState),
          VMSTATE_END_OF_LIST()
      }
  };
-+static uint8_t pl061_floating(PL061State *s)
-+{
-+    /*
-+     * Return mask of bits which correspond to pins configured as inputs
-+     * and which are floating (neither pulled up to 1 nor down to 0).
-+     */
-+    uint8_t floating;
-+
-+    if (s->id == pl061_id_luminary) {
-+        /*
-+         * If both PUR and PDR bits are clear, there is neither a pullup
-+         * nor a pulldown in place, and the output truly floats.
-+         */
-+        floating = ~(s->pur | s->pdr);
-+    } else {
-+        /* Assume outputs are pulled high. FIXME: this is board dependent. */
-+        floating = 0;
-+    }
-+    return floating & ~s->dir;
-+}
-+
-+static uint8_t pl061_pullups(PL061State *s)
-+{
-+    /*
-+     * Return mask of bits which correspond to pins configured as inputs
-+     * and which are pulled up to 1.
-+     */
-+    uint8_t pullups;
-+
-+    if (s->id == pl061_id_luminary) {
-+        /*
-+         * The Luminary variant of the PL061 has an extra registers which
-+         * the guest can use to configure whether lines should be pullup
-+         * or pulldown.
-+         */
-+        pullups = s->pur;
-+    } else {
-+        /* Assume outputs are pulled high. FIXME: this is board dependent. */
-+        pullups = 0xff;
-+    }
-+    return pullups & ~s->dir;
-+}
-+
- static void pl061_update(PL061State *s)
- {
-     uint8_t changed;
-     uint8_t mask;
-     uint8_t out;
-     int i;
-+    uint8_t pullups = pl061_pullups(s);
-+    uint8_t floating = pl061_floating(s);
--    trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data);
-+    trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data,
-+                       pullups, floating);
--    /* Outputs float high.  */
--    /* FIXME: This is board dependent.  */
--    out = (s->data & s->dir) | ~s->dir;
-+    /*
-+     * Pins configured as output are driven from the data register;
-+     * otherwise if they're pulled up they're 1, and if they're floating
-+     * then we give them the same value they had previously, so we don't
-+     * report any change to the other end.
-+     */
-+    out = (s->data & s->dir) | pullups | (s->old_out_data & floating);
-     changed = s->old_out_data ^ out;
-     if (changed) {
-         s->old_out_data = out;
-diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
-index XXXXXXX..XXXXXXX 100644
---- a/hw/gpio/trace-events
-+++ b/hw/gpio/trace-events
-@@ -XXX,XX +XXX,XX @@ nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
- nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
- # pl061.c
--pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIODATA 0x%x"
-+pl061_update(const char *id, uint32_t dir, uint32_t data, uint32_t pullups, uint32_t floating) "%s GPIODIR 0x%x GPIODATA 0x%x pullups 0x%x floating 0x%x"
- pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"
- pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"
- pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
 --
-.20.1
+.34.1

-[PULL 08/17] hw/gpio/pl061: Add tracepoints for register read and write
+[PULL 21/24] rtc: Use time_t for passing and returning time offsets
-Add tracepoints for reads and writes to the PL061 registers. This requires
+The functions qemu_get_timedate() and qemu_timedate_diff() take
-restructuring pl061_read() to only return after the tracepoint, rather
+and return a time offset as an integer. Coverity points out that
-than having lots of early-returns.
+means that when an RTC device implementation holds an offset
 as a time_t, as the m48t59 does, the time_t will get truncated.
 (CID 1507157, 1517772).
 The functions work with time_t internally, so make them use that type
 in their APIs.
 Note that this won't help any Y2038 issues where either the device
 model itself is keeping the offset in a 32-bit integer, or where the
 hardware under emulation has Y2038 or other rollover problems.  If we
 missed any cases of the former then hopefully Coverity will warn us
 about them since after this patch we'd be truncating a time_t in
 assignments from qemu_timedate_diff().)
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- hw/gpio/pl061.c      | 70 ++++++++++++++++++++++++++++++--------------
+ include/sysemu/rtc.h | 4 ++--
- hw/gpio/trace-events |  2 ++
+ softmmu/rtc.c        | 4 ++--
-files changed, 50 insertions(+), 22 deletions(-)
+files changed, 4 insertions(+), 4 deletions(-)
-diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
+diff --git a/include/sysemu/rtc.h b/include/sysemu/rtc.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/gpio/pl061.c
+--- a/include/sysemu/rtc.h
-+++ b/hw/gpio/pl061.c
++++ b/include/sysemu/rtc.h
-@@ -XXX,XX +XXX,XX @@ static uint64_t pl061_read(void *opaque, hwaddr offset,
+@@ -XXX,XX +XXX,XX @@
-                            unsigned size)
+  * The behaviour of the clock whose value this function returns will
   * depend on the -rtc command line option passed by the user.
   */
 -void qemu_get_timedate(struct tm *tm, int offset);
 +void qemu_get_timedate(struct tm *tm, time_t offset);
  /**
   * qemu_timedate_diff: Return difference between a struct tm and the RTC
@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset);
   * a timestamp one hour further ahead than the current RTC time
   * then this function will return 3600.
   */
 -int qemu_timedate_diff(struct tm *tm);
 +time_t qemu_timedate_diff(struct tm *tm);
  #endif
 diff --git a/softmmu/rtc.c b/softmmu/rtc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/softmmu/rtc.c
 +++ b/softmmu/rtc.c
@@ -XXX,XX +XXX,XX @@ static time_t qemu_ref_timedate(QEMUClockType clock)
      return value;
  }
 -void qemu_get_timedate(struct tm *tm, int offset)
 +void qemu_get_timedate(struct tm *tm, time_t offset)
  {
-     PL061State *s = (PL061State *)opaque;
+     time_t ti = qemu_ref_timedate(rtc_clock);
-+    uint64_t r = 0;
+@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset)
      switch (offset) {
      case 0x0 ... 0x3ff: /* Data */
 -        return s->data & (offset >> 2);
 +        r = s->data & (offset >> 2);
 +        break;
      case 0x400: /* Direction */
 -        return s->dir;
 +        r = s->dir;
 +        break;
      case 0x404: /* Interrupt sense */
 -        return s->isense;
 +        r = s->isense;
 +        break;
      case 0x408: /* Interrupt both edges */
 -        return s->ibe;
 +        r = s->ibe;
 +        break;
      case 0x40c: /* Interrupt event */
 -        return s->iev;
 +        r = s->iev;
 +        break;
      case 0x410: /* Interrupt mask */
 -        return s->im;
 +        r = s->im;
 +        break;
      case 0x414: /* Raw interrupt status */
 -        return s->istate;
 +        r = s->istate;
 +        break;
      case 0x418: /* Masked interrupt status */
 -        return s->istate & s->im;
 +        r = s->istate & s->im;
 +        break;
      case 0x420: /* Alternate function select */
 -        return s->afsel;
 +        r = s->afsel;
 +        break;
      case 0x500: /* 2mA drive */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->dr2r;
 +        r = s->dr2r;
 +        break;
      case 0x504: /* 4mA drive */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->dr4r;
 +        r = s->dr4r;
 +        break;
      case 0x508: /* 8mA drive */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->dr8r;
 +        r = s->dr8r;
 +        break;
      case 0x50c: /* Open drain */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->odr;
 +        r = s->odr;
 +        break;
      case 0x510: /* Pull-up */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->pur;
 +        r = s->pur;
 +        break;
      case 0x514: /* Pull-down */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->pdr;
 +        r = s->pdr;
 +        break;
      case 0x518: /* Slew rate control */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->slr;
 +        r = s->slr;
 +        break;
      case 0x51c: /* Digital enable */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->den;
 +        r = s->den;
 +        break;
      case 0x520: /* Lock */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->locked;
 +        r = s->locked;
 +        break;
      case 0x524: /* Commit */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->cr;
 +        r = s->cr;
 +        break;
      case 0x528: /* Analog mode select */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->amsel;
 +        r = s->amsel;
 +        break;
      case 0xfd0 ... 0xfff: /* ID registers */
 -        return s->id[(offset - 0xfd0) >> 2];
 +        r = s->id[(offset - 0xfd0) >> 2];
 +        break;
      default:
      bad_offset:
          qemu_log_mask(LOG_GUEST_ERROR,
                        "pl061_read: Bad offset %x\n", (int)offset);
          break;
      }
--    return 0;
-+
-+    trace_pl061_read(DEVICE(s)->canonical_path, offset, r);
-+    return r;
  }
- static void pl061_write(void *opaque, hwaddr offset,
+-int qemu_timedate_diff(struct tm *tm)
-@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,
++time_t qemu_timedate_diff(struct tm *tm)
-     PL061State *s = (PL061State *)opaque;
+ {
-     uint8_t mask;
+     time_t seconds;
 +    trace_pl061_write(DEVICE(s)->canonical_path, offset, value);
 +
      switch (offset) {
      case 0 ... 0x3ff:
          mask = (offset >> 2) & s->dir;
 diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/gpio/trace-events
 +++ b/hw/gpio/trace-events
@@ -XXX,XX +XXX,XX @@ pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIOD
  pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"
  pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"
  pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
 +pl061_read(const char *id, uint64_t offset, uint64_t r) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
 +pl061_write(const char *id, uint64_t offset, uint64_t value) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
  # sifive_gpio.c
  sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
 --
-.20.1
+.34.1

-[PULL 09/17] hw/gpio/pl061: Document the interface of this device
+[PULL 22/24] target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init
-Add a comment documenting the "QEMU interface" of this device:
+Where architecturally one ARM_FEATURE_X flag implies another
-which MMIO regions, IRQ lines, GPIO lines, etc it exposes.
+ARM_FEATURE_Y, we allow the CPU init function to only set X, and then
 set Y for it.  Currently we do this in two places -- we set a few
 flags in arm_cpu_post_init() because we need them to decide which
 properties to create on the CPU object, and then we do the rest in
 arm_cpu_realizefn().  However, this is fragile, because it's easy to
 add a new property and not notice that this means that an X-implies-Y
 check now has to move from realize to post-init.
 As a specific example, the pmsav7-dregion property is conditional
 on ARM_FEATURE_PMSA && ARM_FEATURE_V7, which means it won't appear
 on the Cortex-M33 and -M55, because they set ARM_FEATURE_V8 and
 rely on V8-implies-V7, which doesn't happen until the realizefn.
 Move all of these X-implies-Y checks into a new function, which
 we call at the top of arm_cpu_post_init(), so the feature bits
 are available at that point.
 This does now give us the reverse issue, that if there's a feature
 bit which is enabled or disabled by the setting of a property then
 then X-implies-Y features that are dependent on that property need to
 be in realize, not in this new function.  But the only one of those
 is the "EL3 implies VBAR" which is already in the right place, so
 putting things this way round seems better to me.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230724174335.2150499-2-peter.maydell@linaro.org
 ---
- hw/gpio/pl061.c | 7 +++++++
+ target/arm/cpu.c | 179 +++++++++++++++++++++++++----------------------
-file changed, 7 insertions(+)
+file changed, 97 insertions(+), 82 deletions(-)
-diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/gpio/pl061.c
+--- a/target/arm/cpu.c
-+++ b/hw/gpio/pl061.c
++++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
-  * Written by Paul Brook
+       NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
-  *
+ }
-  * This code is licensed under the GPL.
-+ *
++static void arm_cpu_propagate_feature_implications(ARMCPU *cpu)
-+ * QEMU interface:
++{
-+ *  + sysbus MMIO region 0: the device registers
++    CPUARMState *env = &cpu->env;
-+ *  + sysbus IRQ: the GPIOINTR interrupt line
++    bool no_aa32 = false;
-+ *  + unnamed GPIO inputs 0..7: inputs to connect to the emulated GPIO lines
++
-+ *  + unnamed GPIO outputs 0..7: the emulated GPIO lines, considered as
++    /*
-+ *    outputs
++     * Some features automatically imply others: set the feature
-  */
++     * bits explicitly for these cases.
++     */
- #include "qemu/osdep.h"
++
 +    if (arm_feature(env, ARM_FEATURE_M)) {
 +        set_feature(env, ARM_FEATURE_PMSA);
 +    }
 +
 +    if (arm_feature(env, ARM_FEATURE_V8)) {
 +        if (arm_feature(env, ARM_FEATURE_M)) {
 +            set_feature(env, ARM_FEATURE_V7);
 +        } else {
 +            set_feature(env, ARM_FEATURE_V7VE);
 +        }
 +    }
 +
 +    /*
 +     * There exist AArch64 cpus without AArch32 support.  When KVM
 +     * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
 +     * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
 +     * As a general principle, we also do not make ID register
 +     * consistency checks anywhere unless using TCG, because only
 +     * for TCG would a consistency-check failure be a QEMU bug.
 +     */
 +    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 +        no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
 +    }
 +
 +    if (arm_feature(env, ARM_FEATURE_V7VE)) {
 +        /*
 +         * v7 Virtualization Extensions. In real hardware this implies
 +         * EL2 and also the presence of the Security Extensions.
 +         * For QEMU, for backwards-compatibility we implement some
 +         * CPUs or CPU configs which have no actual EL2 or EL3 but do
 +         * include the various other features that V7VE implies.
 +         * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
 +         * Security Extensions is ARM_FEATURE_EL3.
 +         */
 +        assert(!tcg_enabled() || no_aa32 ||
 +               cpu_isar_feature(aa32_arm_div, cpu));
 +        set_feature(env, ARM_FEATURE_LPAE);
 +        set_feature(env, ARM_FEATURE_V7);
 +    }
 +    if (arm_feature(env, ARM_FEATURE_V7)) {
 +        set_feature(env, ARM_FEATURE_VAPA);
 +        set_feature(env, ARM_FEATURE_THUMB2);
 +        set_feature(env, ARM_FEATURE_MPIDR);
 +        if (!arm_feature(env, ARM_FEATURE_M)) {
 +            set_feature(env, ARM_FEATURE_V6K);
 +        } else {
 +            set_feature(env, ARM_FEATURE_V6);
 +        }
 +
 +        /*
 +         * Always define VBAR for V7 CPUs even if it doesn't exist in
 +         * non-EL3 configs. This is needed by some legacy boards.
 +         */
 +        set_feature(env, ARM_FEATURE_VBAR);
 +    }
 +    if (arm_feature(env, ARM_FEATURE_V6K)) {
 +        set_feature(env, ARM_FEATURE_V6);
 +        set_feature(env, ARM_FEATURE_MVFR);
 +    }
 +    if (arm_feature(env, ARM_FEATURE_V6)) {
 +        set_feature(env, ARM_FEATURE_V5);
 +        if (!arm_feature(env, ARM_FEATURE_M)) {
 +            assert(!tcg_enabled() || no_aa32 ||
 +                   cpu_isar_feature(aa32_jazelle, cpu));
 +            set_feature(env, ARM_FEATURE_AUXCR);
 +        }
 +    }
 +    if (arm_feature(env, ARM_FEATURE_V5)) {
 +        set_feature(env, ARM_FEATURE_V4T);
 +    }
 +    if (arm_feature(env, ARM_FEATURE_LPAE)) {
 +        set_feature(env, ARM_FEATURE_V7MP);
 +    }
 +    if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 +        set_feature(env, ARM_FEATURE_CBAR);
 +    }
 +    if (arm_feature(env, ARM_FEATURE_THUMB2) &&
 +        !arm_feature(env, ARM_FEATURE_M)) {
 +        set_feature(env, ARM_FEATURE_THUMB_DSP);
 +    }
 +}
 +
  void arm_cpu_post_init(Object *obj)
  {
      ARMCPU *cpu = ARM_CPU(obj);
 -    /* M profile implies PMSA. We have to do this here rather than
 -     * in realize with the other feature-implication checks because
 -     * we look at the PMSA bit to see if we should add some properties.
 +    /*
 +     * Some features imply others. Figure this out now, because we
 +     * are going to look at the feature bits in deciding which
 +     * properties to add.
       */
 -    if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
 -        set_feature(&cpu->env, ARM_FEATURE_PMSA);
 -    }
 +    arm_cpu_propagate_feature_implications(cpu);
      if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
          arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
      CPUARMState *env = &cpu->env;
      int pagebits;
      Error *local_err = NULL;
 -    bool no_aa32 = false;
      /* Use pc-relative instructions in system-mode */
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
          cpu->isar.id_isar3 = u;
      }
 -    /* Some features automatically imply others: */
 -    if (arm_feature(env, ARM_FEATURE_V8)) {
 -        if (arm_feature(env, ARM_FEATURE_M)) {
 -            set_feature(env, ARM_FEATURE_V7);
 -        } else {
 -            set_feature(env, ARM_FEATURE_V7VE);
 -        }
 -    }
 -
 -    /*
 -     * There exist AArch64 cpus without AArch32 support.  When KVM
 -     * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
 -     * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
 -     * As a general principle, we also do not make ID register
 -     * consistency checks anywhere unless using TCG, because only
 -     * for TCG would a consistency-check failure be a QEMU bug.
 -     */
 -    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 -        no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
 -    }
 -
 -    if (arm_feature(env, ARM_FEATURE_V7VE)) {
 -        /* v7 Virtualization Extensions. In real hardware this implies
 -         * EL2 and also the presence of the Security Extensions.
 -         * For QEMU, for backwards-compatibility we implement some
 -         * CPUs or CPU configs which have no actual EL2 or EL3 but do
 -         * include the various other features that V7VE implies.
 -         * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
 -         * Security Extensions is ARM_FEATURE_EL3.
 -         */
 -        assert(!tcg_enabled() || no_aa32 ||
 -               cpu_isar_feature(aa32_arm_div, cpu));
 -        set_feature(env, ARM_FEATURE_LPAE);
 -        set_feature(env, ARM_FEATURE_V7);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_V7)) {
 -        set_feature(env, ARM_FEATURE_VAPA);
 -        set_feature(env, ARM_FEATURE_THUMB2);
 -        set_feature(env, ARM_FEATURE_MPIDR);
 -        if (!arm_feature(env, ARM_FEATURE_M)) {
 -            set_feature(env, ARM_FEATURE_V6K);
 -        } else {
 -            set_feature(env, ARM_FEATURE_V6);
 -        }
 -
 -        /* Always define VBAR for V7 CPUs even if it doesn't exist in
 -         * non-EL3 configs. This is needed by some legacy boards.
 -         */
 -        set_feature(env, ARM_FEATURE_VBAR);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_V6K)) {
 -        set_feature(env, ARM_FEATURE_V6);
 -        set_feature(env, ARM_FEATURE_MVFR);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_V6)) {
 -        set_feature(env, ARM_FEATURE_V5);
 -        if (!arm_feature(env, ARM_FEATURE_M)) {
 -            assert(!tcg_enabled() || no_aa32 ||
 -                   cpu_isar_feature(aa32_jazelle, cpu));
 -            set_feature(env, ARM_FEATURE_AUXCR);
 -        }
 -    }
 -    if (arm_feature(env, ARM_FEATURE_V5)) {
 -        set_feature(env, ARM_FEATURE_V4T);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_LPAE)) {
 -        set_feature(env, ARM_FEATURE_V7MP);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 -        set_feature(env, ARM_FEATURE_CBAR);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_THUMB2) &&
 -        !arm_feature(env, ARM_FEATURE_M)) {
 -        set_feature(env, ARM_FEATURE_THUMB_DSP);
 -    }
      /*
       * We rely on no XScale CPU having VFP so we can use the same bits in the
 --
-.20.1
+.34.1

-[PULL 06/17] hw/gpio/pl061: Convert DPRINTF to tracepoints
+[PULL 23/24] hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties
-Convert the use of the DPRINTF debug macro in the PL061 model to
+M-profile CPUs generally allow configuration of the number of MPU
-use tracepoints.
+regions that they have.  We don't currently model this, so our
 implementations of some of the board models provide CPUs with the
 wrong number of regions.  RTOSes like Zephyr that hardcode the
 expected number of regions may therefore not run on the model if they
 are set up to run on real hardware.
 Add properties mpu-ns-regions and mpu-s-regions to the ARMV7M object,
 matching the ability of hardware to configure the number of Secure
 and NonSecure regions separately.  Our actual CPU implementation
 doesn't currently support that, and it happens that none of the MPS
 boards we model set the number of regions differently for Secure vs
 NonSecure, so we provide an interface to the boards and SoCs that
 won't need to change if we ever do add that functionality in future,
 but make it an error to configure the two properties to different
 values.
 (The property name on the CPU is the somewhat misnamed-for-M-profile
 "pmsav7-dregion", so we don't follow that naming convention for
 the properties here. The TRM doesn't say what the CPU configuration
 variable names are, so we pick something, and follow the lowercase
 convention we already have for properties here.)
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230724174335.2150499-3-peter.maydell@linaro.org
 ---
- hw/gpio/pl061.c      | 27 +++++++++------------------
+ include/hw/arm/armv7m.h |  8 ++++++++
- hw/gpio/trace-events |  6 ++++++
+ hw/arm/armv7m.c         | 21 +++++++++++++++++++++
-files changed, 15 insertions(+), 18 deletions(-)
+files changed, 29 insertions(+)
-diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
+diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/gpio/pl061.c
+--- a/include/hw/arm/armv7m.h
-+++ b/hw/gpio/pl061.c
++++ b/include/hw/arm/armv7m.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M)
- #include "qemu/log.h"
+  * + Property "vfp": enable VFP (forwarded to CPU object)
- #include "qemu/module.h"
+  * + Property "dsp": enable DSP (forwarded to CPU object)
- #include "qom/object.h"
+  * + Property "enable-bitband": expose bitbanded IO
--
++ * + Property "mpu-ns-regions": number of Non-Secure MPU regions (forwarded
--//#define DEBUG_PL061 1
++ *   to CPU object pmsav7-dregion property; default is whatever the default
--
++ *   for the CPU is)
--#ifdef DEBUG_PL061
++ * + Property "mpu-s-regions": number of Secure MPU regions (default is
--#define DPRINTF(fmt, ...) \
++ *   whatever the default for the CPU is; must currently be set to the same
--do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0)
++ *   value as mpu-ns-regions if the CPU implements the Security Extension)
--#define BADF(fmt, ...) \
+  * + Clock input "refclk" is the external reference clock for the systick timers
--do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
+  * + Clock input "cpuclk" is the main CPU clock
--#else
+  */
--#define DPRINTF(fmt, ...) do {} while(0)
+@@ -XXX,XX +XXX,XX @@ struct ARMv7MState {
--#define BADF(fmt, ...) \
+     Object *idau;
--do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0)
+     uint32_t init_svtor;
--#endif
+     uint32_t init_nsvtor;
-+#include "trace.h"
++    uint32_t mpu_ns_regions;
++    uint32_t mpu_s_regions;
- static const uint8_t pl061_id[12] =
+     bool enable_bitband;
-   { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
+     bool start_powered_off;
-@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
+     bool vfp;
-     uint8_t out;
+diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
-     int i;
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/armv7m.c
--    DPRINTF("dir = %d, data = %d\n", s->dir, s->data);
++++ b/hw/arm/armv7m.c
-+    trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data);
+@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
      /* Outputs float high.  */
      /* FIXME: This is board dependent.  */
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
          for (i = 0; i < N_GPIOS; i++) {
              mask = 1 << i;
              if (changed & mask) {
 -                DPRINTF("Set output %d = %d\n", i, (out & mask) != 0);
 -                qemu_set_irq(s->out[i], (out & mask) != 0);
 +                int level = (out & mask) != 0;
 +                trace_pl061_set_output(DEVICE(s)->canonical_path, i, level);
 +                qemu_set_irq(s->out[i], level);
              }
          }
      }
-@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
-         for (i = 0; i < N_GPIOS; i++) {
++    /*
-             mask = 1 << i;
++     * Real M-profile hardware can be configured with a different number of
-             if (changed & mask) {
++     * MPU regions for Secure vs NonSecure. QEMU's CPU implementation doesn't
--                DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0);
++     * support that yet, so catch attempts to select that.
-+                trace_pl061_input_change(DEVICE(s)->canonical_path, i,
++     */
-+                                         (s->data & mask) != 0);
++    if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
++        s->mpu_ns_regions != s->mpu_s_regions) {
-                 if (!(s->isense & mask)) {
++        error_setg(errp,
-                     /* Edge interrupt */
++                   "mpu-ns-regions and mpu-s-regions properties must have the same value");
-@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
++        return;
-     /* Level interrupt */
++    }
-     s->istate |= ~(s->data ^ s->iev) & s->isense;
++    if (s->mpu_ns_regions != UINT_MAX &&
++        object_property_find(OBJECT(s->cpu), "pmsav7-dregion")) {
--    DPRINTF("istate = %02X\n", s->istate);
++        if (!object_property_set_uint(OBJECT(s->cpu), "pmsav7-dregion",
-+    trace_pl061_update_istate(DEVICE(s)->canonical_path,
++                                      s->mpu_ns_regions, errp)) {
-+                              s->istate, s->im, (s->istate & s->im) != 0);
++            return;
++        }
-     qemu_set_irq(s->irq, (s->istate & s->im) != 0);
++    }
  }
 diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/gpio/trace-events
 +++ b/hw/gpio/trace-events
@@ -XXX,XX +XXX,XX @@ nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x
  nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
  nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 +# pl061.c
 +pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIODATA 0x%x"
 +pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"
 +pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"
 +pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
 +
- # sifive_gpio.c
+     /*
- sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
+      * Tell the CPU where the NVIC is; it will fail realize if it doesn't
- sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
+      * have one. Similarly, tell the NVIC where its CPU is.
@@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = {
                       false),
      DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true),
      DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true),
 +    DEFINE_PROP_UINT32("mpu-ns-regions", ARMv7MState, mpu_ns_regions, UINT_MAX),
 +    DEFINE_PROP_UINT32("mpu-s-regions", ARMv7MState, mpu_s_regions, UINT_MAX),
      DEFINE_PROP_END_OF_LIST(),
  };
 --
-.20.1
+.34.1

-[PULL 07/17] hw/gpio/pl061: Clean up read/write offset handling logic
+[PULL 24/24] hw/arm: Set number of MPU regions correctly for an505, an521, an524
-Currently the pl061_read() and pl061_write() functions handle offsets
+The IoTKit, SSE200 and SSE300 all default to 8 MPU regions.  The
-using a combination of three if() statements and a switch().  Clean
+MPS2/MPS3 FPGA images don't override these except in the case of
-this up to use just a switch, using case ranges.
+AN547, which uses 16 MPU regions.
-This requires that instead of catching accesses to the luminary-only
+Define properties on the ARMSSE object for the MPU regions (using the
-registers on a stock PL061 via a check on s->rsvd_start we use
+same names as the documented RTL configuration settings, and
-an "is this luminary?" check in the cases for each luminary-only
+following the pattern we already have for this device of using
-register.
+all-caps names as the RTL does), and set them in the board code.
 We don't actually need to override the default except on AN547,
 but it's simpler code to have the board code set them always
 rather than tracking which board subtypes want to set them to
 a non-default value separately from what that value is.
 Tho overall effect is that for mps2-an505, mps2-an521 and mps3-an524
 we now correctly use 8 MPU regions, while mps3-an547 stays at its
 current 16 regions.
 It's possible some guest code wrongly depended on the previous
 incorrectly modeled number of memory regions. (Such guest code
 should ideally check the number of regions via the MPU_TYPE
 register.) The old behaviour can be obtained with additional
 -global arguments to QEMU:
 For mps2-an521 and mps2-an524:
  -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 -global sse-200.CPU1_MPU_NS=16 -global sse-200.CPU1_MPU_S=16
 For mps2-an505:
  -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16
 NB that the way the implementation allows this use of -global
 is slightly fragile: if the board code explicitly sets the
 properties on the sse-200 object, this overrides the -global
 command line option. So we rely on:
  - the boards that need fixing all happen to use the SSE defaults
  - we can write the board code to only set the property if it
    is different from the default, rather than having all boards
    explicitly set the property
  - the board that does need to use a non-default value happens
    to need to set it to the same value (16) we previously used
 This works, but there are some kinds of refactoring of the
 mps2-tz.c code that would break the support for -global here.
 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1772
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230724174335.2150499-4-peter.maydell@linaro.org
 ---
- hw/gpio/pl061.c | 104 ++++++++++++++++++++++++++++++++++++------------
+ include/hw/arm/armsse.h |  5 +++++
-file changed, 79 insertions(+), 25 deletions(-)
+ hw/arm/armsse.c         | 16 ++++++++++++++++
+ hw/arm/mps2-tz.c        | 29 +++++++++++++++++++++++++++++
-diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
+files changed, 50 insertions(+)
 diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/gpio/pl061.c
+--- a/include/hw/arm/armsse.h
-+++ b/hw/gpio/pl061.c
++++ b/include/hw/arm/armsse.h
-@@ -XXX,XX +XXX,XX @@ struct PL061State {
+@@ -XXX,XX +XXX,XX @@
-     qemu_irq irq;
+  *    (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an
-     qemu_irq out[N_GPIOS];
+  *    SSE-200 both are present; CPU0 in an SSE-200 has neither.
-     const unsigned char *id;
+  *    Since the IoTKit has only one CPU, it does not have the CPU1_* properties.
--    uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */
++ *  + QOM properties "CPU0_MPU_NS", "CPU0_MPU_S", "CPU1_MPU_NS" and "CPU1_MPU_S"
- };
++ *    which set the number of MPU regions on the CPUs. If there is only one
++ *    CPU the CPU1 properties are not present.
- static const VMStateDescription vmstate_pl061 = {
+  *  + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
-@@ -XXX,XX +XXX,XX @@ static uint64_t pl061_read(void *opaque, hwaddr offset,
+  *    which are wired to its NVIC lines 32 .. n+32
   *  + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for
@@ -XXX,XX +XXX,XX @@ struct ARMSSE {
      uint32_t exp_numirq;
      uint32_t sram_addr_width;
      uint32_t init_svtor;
 +    uint32_t cpu_mpu_ns[SSE_MAX_CPUS];
 +    uint32_t cpu_mpu_s[SSE_MAX_CPUS];
      bool cpu_fpu[SSE_MAX_CPUS];
      bool cpu_dsp[SSE_MAX_CPUS];
  };
 diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/armsse.c
 +++ b/hw/arm/armsse.c
@@ -XXX,XX +XXX,XX @@ static Property iotkit_properties[] = {
      DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
      DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
      DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
 +    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
 +    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
      DEFINE_PROP_END_OF_LIST()
  };
@@ -XXX,XX +XXX,XX @@ static Property sse200_properties[] = {
      DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false),
      DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true),
      DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true),
 +    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
 +    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
 +    DEFINE_PROP_UINT32("CPU1_MPU_NS", ARMSSE, cpu_mpu_ns[1], 8),
 +    DEFINE_PROP_UINT32("CPU1_MPU_S", ARMSSE, cpu_mpu_s[1], 8),
      DEFINE_PROP_END_OF_LIST()
  };
@@ -XXX,XX +XXX,XX @@ static Property sse300_properties[] = {
      DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
      DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
      DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
 +    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
 +    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
      DEFINE_PROP_END_OF_LIST()
  };
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
                  return;
              }
          }
 +        if (!object_property_set_uint(cpuobj, "mpu-ns-regions",
 +                                      s->cpu_mpu_ns[i], errp)) {
 +            return;
 +        }
 +        if (!object_property_set_uint(cpuobj, "mpu-s-regions",
 +                                      s->cpu_mpu_s[i], errp)) {
 +            return;
 +        }
          if (i > 0) {
              memory_region_add_subregion_overlap(&s->cpu_container[i], 0,
 diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/mps2-tz.c
 +++ b/hw/arm/mps2-tz.c
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass {
      int uart_overflow_irq; /* number of the combined UART overflow IRQ */
      uint32_t init_svtor; /* init-svtor setting for SSE */
      uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */
 +    uint32_t cpu0_mpu_ns; /* CPU0_MPU_NS setting for SSE */
 +    uint32_t cpu0_mpu_s; /* CPU0_MPU_S setting for SSE */
 +    uint32_t cpu1_mpu_ns; /* CPU1_MPU_NS setting for SSE */
 +    uint32_t cpu1_mpu_s; /* CPU1_MPU_S setting for SSE */
      const RAMInfo *raminfo;
      const char *armsse_type;
      uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
  #define MPS3_DDR_SIZE (2 * GiB)
  #endif
 +/* For cpu{0,1}_mpu_{ns,s}, means "leave at SSE's default value" */
 +#define MPU_REGION_DEFAULT UINT32_MAX
 +
  static const uint32_t an505_oscclk[] = {
      40000000,
      24580000,
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
                               OBJECT(system_memory), &error_abort);
      qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq);
      qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor);
 +    if (mmc->cpu0_mpu_ns != MPU_REGION_DEFAULT) {
 +        qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_NS", mmc->cpu0_mpu_ns);
 +    }
 +    if (mmc->cpu0_mpu_s != MPU_REGION_DEFAULT) {
 +        qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_S", mmc->cpu0_mpu_s);
 +    }
 +    if (object_property_find(OBJECT(iotkitdev), "CPU1_MPU_NS")) {
 +        if (mmc->cpu1_mpu_ns != MPU_REGION_DEFAULT) {
 +            qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_NS", mmc->cpu1_mpu_ns);
 +        }
 +        if (mmc->cpu1_mpu_s != MPU_REGION_DEFAULT) {
 +            qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_S", mmc->cpu1_mpu_s);
 +        }
 +    }
      qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
      qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
      qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
@@ -XXX,XX +XXX,XX @@ static void mps2tz_class_init(ObjectClass *oc, void *data)
  {
-     PL061State *s = (PL061State *)opaque;
+     MachineClass *mc = MACHINE_CLASS(oc);
+     IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc);
--    if (offset < 0x400) {
++    MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
--        return s->data & (offset >> 2);
--    }
+     mc->init = mps2tz_common_init;
--    if (offset >= s->rsvd_start && offset <= 0xfcc) {
+     mc->reset = mps2_machine_reset;
--        goto err_out;
+     iic->check = mps2_tz_idau_check;
--    }
++
--    if (offset >= 0xfd0 && offset < 0x1000) {
++    /* Most machines leave these at the SSE defaults */
--        return s->id[(offset - 0xfd0) >> 2];
++    mmc->cpu0_mpu_ns = MPU_REGION_DEFAULT;
--    }
++    mmc->cpu0_mpu_s = MPU_REGION_DEFAULT;
-     switch (offset) {
++    mmc->cpu1_mpu_ns = MPU_REGION_DEFAULT;
-+    case 0x0 ... 0x3ff: /* Data */
++    mmc->cpu1_mpu_s = MPU_REGION_DEFAULT;
 +        return s->data & (offset >> 2);
      case 0x400: /* Direction */
          return s->dir;
      case 0x404: /* Interrupt sense */
@@ -XXX,XX +XXX,XX @@ static uint64_t pl061_read(void *opaque, hwaddr offset,
      case 0x420: /* Alternate function select */
          return s->afsel;
      case 0x500: /* 2mA drive */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          return s->dr2r;
      case 0x504: /* 4mA drive */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          return s->dr4r;
      case 0x508: /* 8mA drive */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          return s->dr8r;
      case 0x50c: /* Open drain */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          return s->odr;
      case 0x510: /* Pull-up */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          return s->pur;
      case 0x514: /* Pull-down */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          return s->pdr;
      case 0x518: /* Slew rate control */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          return s->slr;
      case 0x51c: /* Digital enable */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          return s->den;
      case 0x520: /* Lock */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          return s->locked;
      case 0x524: /* Commit */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          return s->cr;
      case 0x528: /* Analog mode select */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          return s->amsel;
 +    case 0xfd0 ... 0xfff: /* ID registers */
 +        return s->id[(offset - 0xfd0) >> 2];
      default:
 +    bad_offset:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "pl061_read: Bad offset %x\n", (int)offset);
          break;
      }
 -err_out:
 -    qemu_log_mask(LOG_GUEST_ERROR,
 -                  "pl061_read: Bad offset %x\n", (int)offset);
      return 0;
  }
-@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,
+ static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc)
-     PL061State *s = (PL061State *)opaque;
+@@ -XXX,XX +XXX,XX @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data)
-     uint8_t mask;
+     mmc->numirq = 96;
+     mmc->uart_overflow_irq = 48;
--    if (offset < 0x400) {
+     mmc->init_svtor = 0x00000000;
-+    switch (offset) {
++    mmc->cpu0_mpu_s = mmc->cpu0_mpu_ns = 16;
-+    case 0 ... 0x3ff:
+     mmc->sram_addr_width = 21;
-         mask = (offset >> 2) & s->dir;
+     mmc->raminfo = an547_raminfo;
-         s->data = (s->data & ~mask) | (value & mask);
+     mmc->armsse_type = TYPE_SSE300;
          pl061_update(s);
          return;
 -    }
 -    if (offset >= s->rsvd_start) {
 -        goto err_out;
 -    }
 -    switch (offset) {
      case 0x400: /* Direction */
          s->dir = value & 0xff;
          break;
@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,
          s->afsel = (s->afsel & ~mask) | (value & mask);
          break;
      case 0x500: /* 2mA drive */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          s->dr2r = value & 0xff;
          break;
      case 0x504: /* 4mA drive */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          s->dr4r = value & 0xff;
          break;
      case 0x508: /* 8mA drive */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          s->dr8r = value & 0xff;
          break;
      case 0x50c: /* Open drain */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          s->odr = value & 0xff;
          break;
      case 0x510: /* Pull-up */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          s->pur = value & 0xff;
          break;
      case 0x514: /* Pull-down */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          s->pdr = value & 0xff;
          break;
      case 0x518: /* Slew rate control */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          s->slr = value & 0xff;
          break;
      case 0x51c: /* Digital enable */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          s->den = value & 0xff;
          break;
      case 0x520: /* Lock */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          s->locked = (value != 0xacce551);
          break;
      case 0x524: /* Commit */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          if (!s->locked)
              s->cr = value & 0xff;
          break;
      case 0x528:
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          s->amsel = value & 0xff;
          break;
      default:
 -        goto err_out;
 +    bad_offset:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "pl061_write: Bad offset %x\n", (int)offset);
 +        return;
      }
      pl061_update(s);
      return;
 -err_out:
 -    qemu_log_mask(LOG_GUEST_ERROR,
 -                  "pl061_write: Bad offset %x\n", (int)offset);
  }
  static void pl061_reset(DeviceState *dev)
@@ -XXX,XX +XXX,XX @@ static void pl061_luminary_init(Object *obj)
      PL061State *s = PL061(obj);
      s->id = pl061_id_luminary;
 -    s->rsvd_start = 0x52c;
  }
  static void pl061_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void pl061_init(Object *obj)
      SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
      s->id = pl061_id;
 -    s->rsvd_start = 0x424;
      memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000);
      sysbus_init_mmio(sbd, &s->iomem);
 --
-.20.1
+.34.1

Arm changes for before softfreeze: mostly my PL061/GPIO patches,
but also a new M-profile board and various other things.

thanks
-- PMM

The following changes since commit 05de778b5b8ab0b402996769117b88c7ea5c7c61:

Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2021-07-09 14:30:01 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210709

for you to fetch changes up to 05449abb1d4c5f0c69ceb3d8d03cbc75de39b646:

hw/intc: Improve formatting of MEMTX_ERROR guest error message (2021-07-09 16:09:12 +0100)

----------------------------------------------------------------
target-arm queue:
 * New machine type: stm32vldiscovery
 * hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write
 * hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
 * virt: Fix implementation of GPIO-based powerdown/shutdown mechanism
 * Correct the encoding of MDCCSR_EL0 and DBGDSCRint
 * hw/intc: Improve formatting of MEMTX_ERROR guest error message

----------------------------------------------------------------
Alexandre Iooss (4):
      stm32f100: Add the stm32f100 SoC
      stm32vldiscovery: Add the STM32VLDISCOVERY Machine
      docs/system: arm: Add stm32 boards description
      tests/boot-serial-test: Add STM32VLDISCOVERY board testcase

Peter Maydell (10):
      hw/gpio/pl061: Convert DPRINTF to tracepoints
      hw/gpio/pl061: Clean up read/write offset handling logic
      hw/gpio/pl061: Add tracepoints for register read and write
      hw/gpio/pl061: Document the interface of this device
      hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
      hw/gpio/pl061: Make pullup/pulldown of outputs configurable
      hw/arm/virt: Make PL061 GPIO lines pulled low, not high
      hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset
      hw/gpio/pl061: Document a shortcoming in our implementation
      hw/arm/stellaris: Expand comment about handling of OLED chipselect

Rebecca Cran (1):
      hw/intc: Improve formatting of MEMTX_ERROR guest error message

Ricardo Koller (1):
      hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write

hnick@vmware.com (1):
      target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint

docs/system/arm/stm32.rst               |  66 +++++++
 docs/system/target-arm.rst              |   1 +
 default-configs/devices/arm-softmmu.mak |   1 +
 include/hw/arm/stm32f100_soc.h          |  57 ++++++
 hw/arm/stellaris.c                      |  56 +++++-
 hw/arm/stm32f100_soc.c                  | 182 +++++++++++++++++
 hw/arm/stm32vldiscovery.c               |  66 +++++++
 hw/arm/virt.c                           |   3 +
 hw/gpio/pl061.c                         | 341 +++++++++++++++++++++++++-------
 hw/intc/arm_gicv3_cpuif.c               |   4 +-
 hw/intc/arm_gicv3_redist.c              |   4 +-
 target/arm/helper.c                     |  16 +-
 tests/qtest/boot-serial-test.c          |  37 ++++
 MAINTAINERS                             |  13 ++
 hw/arm/Kconfig                          |  10 +
 hw/arm/meson.build                      |   2 +
 hw/gpio/trace-events                    |   9 +
 17 files changed, 790 insertions(+), 78 deletions(-)
 create mode 100644 docs/system/arm/stm32.rst
 create mode 100644 include/hw/arm/stm32f100_soc.h
 create mode 100644 hw/arm/stm32f100_soc.c
 create mode 100644 hw/arm/stm32vldiscovery.c

From: Alexandre Iooss <erdnaxe@crans.org>

This SoC is similar to stm32f205 SoC.
This will be used by the STM32VLDISCOVERY to create a machine.

Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210617165647.2575955-2-erdnaxe@crans.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/stm32f100_soc.h |  57 +++++++++++
 hw/arm/stm32f100_soc.c         | 182 +++++++++++++++++++++++++++++++++
 MAINTAINERS                    |   6 ++
 hw/arm/Kconfig                 |   6 ++
 hw/arm/meson.build             |   1 +
 5 files changed, 252 insertions(+)
 create mode 100644 include/hw/arm/stm32f100_soc.h
 create mode 100644 hw/arm/stm32f100_soc.c

diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/arm/stm32f100_soc.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * STM32F100 SoC
+ *
+ * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_ARM_STM32F100_SOC_H
+#define HW_ARM_STM32F100_SOC_H
+
+#include "hw/char/stm32f2xx_usart.h"
+#include "hw/ssi/stm32f2xx_spi.h"
+#include "hw/arm/armv7m.h"
+#include "qom/object.h"
+
+#define TYPE_STM32F100_SOC "stm32f100-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC)
+
+#define STM_NUM_USARTS 3
+#define STM_NUM_SPIS 2
+
+#define FLASH_BASE_ADDRESS 0x08000000
+#define FLASH_SIZE (128 * 1024)
+#define SRAM_BASE_ADDRESS 0x20000000
+#define SRAM_SIZE (8 * 1024)
+
+struct STM32F100State {
+    /*< private >*/
+    SysBusDevice parent_obj;
+
+    /*< public >*/
+    char *cpu_type;
+
+    ARMv7MState armv7m;
+
+    STM32F2XXUsartState usart[STM_NUM_USARTS];
+    STM32F2XXSPIState spi[STM_NUM_SPIS];
+};
+
+#endif
diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/arm/stm32f100_soc.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * STM32F100 SoC
+ *
+ * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/module.h"
+#include "hw/arm/boot.h"
+#include "exec/address-spaces.h"
+#include "hw/arm/stm32f100_soc.h"
+#include "hw/qdev-properties.h"
+#include "hw/misc/unimp.h"
+#include "sysemu/sysemu.h"
+
+/* stm32f100_soc implementation is derived from stm32f205_soc */
+
+static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40013800, 0x40004400,
+    0x40004800 };
+static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800 };
+
+static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39};
+static const int spi_irq[STM_NUM_SPIS] = {35, 36};
+
+static void stm32f100_soc_initfn(Object *obj)
+{
+    STM32F100State *s = STM32F100_SOC(obj);
+    int i;
+
+    object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
+
+    for (i = 0; i < STM_NUM_USARTS; i++) {
+        object_initialize_child(obj, "usart[*]", &s->usart[i],
+                                TYPE_STM32F2XX_USART);
+    }
+
+    for (i = 0; i < STM_NUM_SPIS; i++) {
+        object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
+    }
+}
+
+static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
+{
+    STM32F100State *s = STM32F100_SOC(dev_soc);
+    DeviceState *dev, *armv7m;
+    SysBusDevice *busdev;
+    int i;
+
+    MemoryRegion *system_memory = get_system_memory();
+    MemoryRegion *sram = g_new(MemoryRegion, 1);
+    MemoryRegion *flash = g_new(MemoryRegion, 1);
+    MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
+
+    /*
+     * Init flash region
+     * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0
+     */
+    memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F100.flash",
+                           FLASH_SIZE, &error_fatal);
+    memory_region_init_alias(flash_alias, OBJECT(dev_soc),
+                             "STM32F100.flash.alias", flash, 0, FLASH_SIZE);
+    memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
+    memory_region_add_subregion(system_memory, 0, flash_alias);
+
+    /* Init SRAM region */
+    memory_region_init_ram(sram, NULL, "STM32F100.sram", SRAM_SIZE,
+                           &error_fatal);
+    memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
+
+    /* Init ARMv7m */
+    armv7m = DEVICE(&s->armv7m);
+    qdev_prop_set_uint32(armv7m, "num-irq", 61);
+    qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
+    qdev_prop_set_bit(armv7m, "enable-bitband", true);
+    object_property_set_link(OBJECT(&s->armv7m), "memory",
+                             OBJECT(get_system_memory()), &error_abort);
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
+        return;
+    }
+
+    /* Attach UART (uses USART registers) and USART controllers */
+    for (i = 0; i < STM_NUM_USARTS; i++) {
+        dev = DEVICE(&(s->usart[i]));
+        qdev_prop_set_chr(dev, "chardev", serial_hd(i));
+        if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) {
+            return;
+        }
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, usart_addr[i]);
+        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
+    }
+
+    /* SPI 1 and 2 */
+    for (i = 0; i < STM_NUM_SPIS; i++) {
+        dev = DEVICE(&(s->spi[i]));
+        if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
+            return;
+        }
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, spi_addr[i]);
+        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
+    }
+
+    create_unimplemented_device("timer[2]",  0x40000000, 0x400);
+    create_unimplemented_device("timer[3]",  0x40000400, 0x400);
+    create_unimplemented_device("timer[4]",  0x40000800, 0x400);
+    create_unimplemented_device("timer[6]",  0x40001000, 0x400);
+    create_unimplemented_device("timer[7]",  0x40001400, 0x400);
+    create_unimplemented_device("RTC",       0x40002800, 0x400);
+    create_unimplemented_device("WWDG",      0x40002C00, 0x400);
+    create_unimplemented_device("IWDG",      0x40003000, 0x400);
+    create_unimplemented_device("I2C1",      0x40005400, 0x400);
+    create_unimplemented_device("I2C2",      0x40005800, 0x400);
+    create_unimplemented_device("BKP",       0x40006C00, 0x400);
+    create_unimplemented_device("PWR",       0x40007000, 0x400);
+    create_unimplemented_device("DAC",       0x40007400, 0x400);
+    create_unimplemented_device("CEC",       0x40007800, 0x400);
+    create_unimplemented_device("AFIO",      0x40010000, 0x400);
+    create_unimplemented_device("EXTI",      0x40010400, 0x400);
+    create_unimplemented_device("GPIOA",     0x40010800, 0x400);
+    create_unimplemented_device("GPIOB",     0x40010C00, 0x400);
+    create_unimplemented_device("GPIOC",     0x40011000, 0x400);
+    create_unimplemented_device("GPIOD",     0x40011400, 0x400);
+    create_unimplemented_device("GPIOE",     0x40011800, 0x400);
+    create_unimplemented_device("ADC1",      0x40012400, 0x400);
+    create_unimplemented_device("timer[1]",  0x40012C00, 0x400);
+    create_unimplemented_device("timer[15]", 0x40014000, 0x400);
+    create_unimplemented_device("timer[16]", 0x40014400, 0x400);
+    create_unimplemented_device("timer[17]", 0x40014800, 0x400);
+    create_unimplemented_device("DMA",       0x40020000, 0x400);
+    create_unimplemented_device("RCC",       0x40021000, 0x400);
+    create_unimplemented_device("Flash Int", 0x40022000, 0x400);
+    create_unimplemented_device("CRC",       0x40023000, 0x400);
+}
+
+static Property stm32f100_soc_properties[] = {
+    DEFINE_PROP_STRING("cpu-type", STM32F100State, cpu_type),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void stm32f100_soc_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = stm32f100_soc_realize;
+    device_class_set_props(dc, stm32f100_soc_properties);
+}
+
+static const TypeInfo stm32f100_soc_info = {
+    .name          = TYPE_STM32F100_SOC,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(STM32F100State),
+    .instance_init = stm32f100_soc_initfn,
+    .class_init    = stm32f100_soc_class_init,
+};
+
+static void stm32f100_soc_types(void)
+{
+    type_register_static(&stm32f100_soc_info);
+}
+
+type_init(stm32f100_soc_types)
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/arm/virt-acpi-build.c
 
+STM32F100
+M: Alexandre Iooss <erdnaxe@crans.org>
+L: qemu-arm@nongnu.org
+S: Maintained
+F: hw/arm/stm32f100_soc.c
+
 STM32F205
 M: Alistair Francis <alistair@alistair23.me>
 M: Peter Maydell <peter.maydell@linaro.org>
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config RASPI
     select SDHCI
     select USB_DWC2
 
+config STM32F100_SOC
+    bool
+    select ARM_V7M
+    select STM32F2XX_USART
+    select STM32F2XX_SPI
+
 config STM32F205_SOC
     bool
     select ARM_V7M
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c'))
 arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c'))
 arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))
 arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c', 'bcm2836.c', 'raspi.c'))
+arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c'))
 arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c'))
 arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c'))
 arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c'))
-- 
2.20.1

From: Alexandre Iooss <erdnaxe@crans.org>

This is a Cortex-M3 based machine. Information can be found at:
https://www.st.com/en/evaluation-tools/stm32vldiscovery.html

Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210617165647.2575955-3-erdnaxe@crans.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 default-configs/devices/arm-softmmu.mak |  1 +
 hw/arm/stm32vldiscovery.c               | 66 +++++++++++++++++++++++++
 MAINTAINERS                             |  6 +++
 hw/arm/Kconfig                          |  4 ++
 hw/arm/meson.build                      |  1 +
 5 files changed, 78 insertions(+)
 create mode 100644 hw/arm/stm32vldiscovery.c

diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak
index XXXXXXX..XXXXXXX 100644
--- a/default-configs/devices/arm-softmmu.mak
+++ b/default-configs/devices/arm-softmmu.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_CHEETAH=y
 CONFIG_SX1=y
 CONFIG_NSERIES=y
 CONFIG_STELLARIS=y
+CONFIG_STM32VLDISCOVERY=y
 CONFIG_REALVIEW=y
 CONFIG_VERSATILE=y
 CONFIG_VEXPRESS=y
diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/arm/stm32vldiscovery.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * ST STM32VLDISCOVERY machine
+ *
+ * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "hw/qdev-properties.h"
+#include "qemu/error-report.h"
+#include "hw/arm/stm32f100_soc.h"
+#include "hw/arm/boot.h"
+
+/* stm32vldiscovery implementation is derived from netduinoplus2 */
+
+/* Main SYSCLK frequency in Hz (24MHz) */
+#define SYSCLK_FRQ 24000000ULL
+
+static void stm32vldiscovery_init(MachineState *machine)
+{
+    DeviceState *dev;
+
+    /*
+     * TODO: ideally we would model the SoC RCC and let it handle
+     * system_clock_scale, including its ability to define different
+     * possible SYSCLK sources.
+     */
+    system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
+
+    dev = qdev_new(TYPE_STM32F100_SOC);
+    qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
+    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+
+    armv7m_load_kernel(ARM_CPU(first_cpu),
+                       machine->kernel_filename,
+                       FLASH_SIZE);
+}
+
+static void stm32vldiscovery_machine_init(MachineClass *mc)
+{
+    mc->desc = "ST STM32VLDISCOVERY (Cortex-M3)";
+    mc->init = stm32vldiscovery_init;
+}
+
+DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init)
+
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: hw/*/stellaris*
 F: include/hw/input/gamepad.h
 F: docs/system/arm/stellaris.rst
 
+STM32VLDISCOVERY
+M: Alexandre Iooss <erdnaxe@crans.org>
+L: qemu-arm@nongnu.org
+S: Maintained
+F: hw/arm/stm32vldiscovery.c
+
 Versatile Express
 M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config STELLARIS
     select STELLARIS_ENET # ethernet
     select UNIMP
 
+config STM32VLDISCOVERY
+    bool
+    select STM32F100_SOC
+
 config STRONGARM
     bool
     select PXA2XX
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c'))
 arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
 arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
 arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
+arm_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c'))
 arm_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c'))
 arm_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c'))
 arm_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c'))
-- 
2.20.1

From: Alexandre Iooss <erdnaxe@crans.org>

This adds the target guide for Netduino 2, Netduino Plus 2 and STM32VLDISCOVERY.

Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210617165647.2575955-4-erdnaxe@crans.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/stm32.rst  | 66 ++++++++++++++++++++++++++++++++++++++
 docs/system/target-arm.rst |  1 +
 MAINTAINERS                |  1 +
 3 files changed, 68 insertions(+)
 create mode 100644 docs/system/arm/stm32.rst

diff --git a/docs/system/arm/stm32.rst b/docs/system/arm/stm32.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/system/arm/stm32.rst
@@ -XXX,XX +XXX,XX @@
+STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``stm32vldiscovery``)
+========================================================================================
+
+The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by
+STMicroelectronics.
+
+.. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html
+
+The STM32F1 series is based on ARM Cortex-M3 core. The following machines are
+based on this chip :
+
+- ``stm32vldiscovery``  STM32VLDISCOVERY board with STM32F100RBT6 microcontroller
+
+The STM32F2 series is based on ARM Cortex-M3 core. The following machines are
+based on this chip :
+
+- ``netduino2``         Netduino 2 board with STM32F205RFT6 microcontroller
+
+The STM32F4 series is based on ARM Cortex-M4F core. This series is pin-to-pin
+compatible with STM32F2 series. The following machines are based on this chip :
+
+- ``netduinoplus2``     Netduino Plus 2 board with STM32F405RGT6 microcontroller
+
+There are many other STM32 series that are currently not supported by QEMU.
+
+Supported devices
+-----------------
+
+ * ARM Cortex-M3, Cortex M4F
+ * Analog to Digital Converter (ADC)
+ * EXTI interrupt
+ * Serial ports (USART)
+ * SPI controller
+ * System configuration (SYSCFG)
+ * Timer controller (TIMER)
+
+Missing devices
+---------------
+
+ * Camera interface (DCMI)
+ * Controller Area Network (CAN)
+ * Cycle Redundancy Check (CRC) calculation unit
+ * Digital to Analog Converter (DAC)
+ * DMA controller
+ * Ethernet controller
+ * Flash Interface Unit
+ * GPIO controller
+ * I2C controller
+ * Inter-Integrated Sound (I2S) controller
+ * Power supply configuration (PWR)
+ * Random Number Generator (RNG)
+ * Real-Time Clock (RTC) controller
+ * Reset and Clock Controller (RCC)
+ * Secure Digital Input/Output (SDIO) interface
+ * USB OTG
+ * Watchdog controller (IWDG, WWDG)
+
+Boot options
+------------
+
+The STM32 machines can be started using the ``-kernel`` option to load a
+firmware. Example:
+
+.. code-block:: bash
+
+  $ qemu-system-arm -M stm32vldiscovery -kernel firmware.bin
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/target-arm.rst
+++ b/docs/system/target-arm.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
    arm/collie
    arm/sx1
    arm/stellaris
+   arm/stm32
    arm/virt
    arm/xlnx-versal-virt
 
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ M: Alexandre Iooss <erdnaxe@crans.org>
 L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/arm/stm32vldiscovery.c
+F: docs/system/arm/stm32.rst
 
 Versatile Express
 M: Peter Maydell <peter.maydell@linaro.org>
-- 
2.20.1

From: Alexandre Iooss <erdnaxe@crans.org>

New mini-kernel test for STM32VLDISCOVERY USART1.

Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
Acked-by: Thomas Huth <thuth@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210617165647.2575955-5-erdnaxe@crans.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/boot-serial-test.c | 37 ++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/boot-serial-test.c
+++ b/tests/qtest/boot-serial-test.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t kernel_nrf51[] = {
     0x1c, 0x25, 0x00, 0x40                  /* 0x4000251c = UART TXD */
 };
 
+static const uint8_t kernel_stm32vldiscovery[] = {
+    0x00, 0x00, 0x00, 0x00,                 /* Stack top address */
+    0x1d, 0x00, 0x00, 0x00,                 /* Reset handler address */
+    0x00, 0x00, 0x00, 0x00,                 /* NMI */
+    0x00, 0x00, 0x00, 0x00,                 /* Hard fault */
+    0x00, 0x00, 0x00, 0x00,                 /* Memory management fault */
+    0x00, 0x00, 0x00, 0x00,                 /* Bus fault */
+    0x00, 0x00, 0x00, 0x00,                 /* Usage fault */
+    0x0b, 0x4b,                             /* ldr  r3, [pc, #44] Get RCC */
+    0x44, 0xf2, 0x04, 0x02,                 /* movw r2, #16388 */
+    0x1a, 0x60,                             /* str  r2, [r3] */
+    0x0a, 0x4b,                             /* ldr  r3, [pc, #40] Get GPIOA */
+    0x1a, 0x68,                             /* ldr  r2, [r3] */
+    0x22, 0xf0, 0xf0, 0x02,                 /* bic  r2, r2, #240 */
+    0x1a, 0x60,                             /* str  r2, [r3] */
+    0x1a, 0x68,                             /* ldr  r2, [r3] */
+    0x42, 0xf0, 0xb0, 0x02,                 /* orr  r2, r2, #176 */
+    0x1a, 0x60,                             /* str  r2, [r3] */
+    0x07, 0x4b,                             /* ldr  r3, [pc, #26] Get BAUD */
+    0x45, 0x22,                             /* movs r2, #69 */
+    0x1a, 0x60,                             /* str  r2, [r3] */
+    0x06, 0x4b,                             /* ldr  r3, [pc, #24] Get ENABLE */
+    0x42, 0xf2, 0x08, 0x02,                 /* movw r2, #8200 */
+    0x1a, 0x60,                             /* str  r2, [r3] */
+    0x05, 0x4b,                             /* ldr  r3, [pc, #20] Get TXD */
+    0x54, 0x22,                             /* movs r2, 'T' */
+    0x1a, 0x60,                             /* str  r2, [r3] */
+    0xfe, 0xe7,                             /* b    . */
+    0x18, 0x10, 0x02, 0x40,                 /* 0x40021018 = RCC */
+    0x04, 0x08, 0x01, 0x40,                 /* 0x40010804 = GPIOA */
+    0x08, 0x38, 0x01, 0x40,                 /* 0x40013808 = USART1 BAUD */
+    0x0c, 0x38, 0x01, 0x40,                 /* 0x4001380c = USART1 ENABLE */
+    0x04, 0x38, 0x01, 0x40                  /* 0x40013804 = USART1 TXD */
+};
+
 typedef struct testdef {
     const char *arch;       /* Target architecture */
     const char *machine;    /* Name of the machine */
@@ -XXX,XX +XXX,XX @@ static testdef_t tests[] = {
     { "aarch64", "virt", "-cpu max", "TT", sizeof(kernel_aarch64),
       kernel_aarch64 },
     { "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 },
+    { "arm", "stm32vldiscovery", "", "T",
+      sizeof(kernel_stm32vldiscovery), kernel_stm32vldiscovery },
 
     { NULL }
 };
-- 
2.20.1

From: Ricardo Koller <ricarkol@google.com>

icv_eoir_write() and icv_dir_write() ignore invalid virtual IRQ numbers
(like LPIs).  The issue is that these functions check against the number
of implemented IRQs (QEMU's default is num_irq=288) which can be lower
than the maximum virtual IRQ number (1020 - 1).  The consequence is that
if a hypervisor creates an LR for an IRQ between 288 and 1020, then the
guest is unable to deactivate the resulting IRQ. Note that other
functions that deal with large IRQ numbers, like icv_iar_read, check
against 1020 and not against num_irq.

Fix the checks by using GICV3_MAXIRQ (1020) instead of the number of
implemented IRQs.

Signed-off-by: Ricardo Koller <ricarkol@google.com>
Message-id: 20210702233701.3369-1-ricarkol@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_cpuif.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@ static void icv_dir_write(CPUARMState *env, const ARMCPRegInfo *ri,
 
     trace_gicv3_icv_dir_write(gicv3_redist_affid(cs), value);
 
-    if (irq >= cs->gic->num_irq) {
+    if (irq >= GICV3_MAXIRQ) {
         /* Also catches special interrupt numbers and LPIs */
         return;
     }
@@ -XXX,XX +XXX,XX @@ static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri,
     trace_gicv3_icv_eoir_write(ri->crm == 8 ? 0 : 1,
                                gicv3_redist_affid(cs), value);
 
-    if (irq >= cs->gic->num_irq) {
+    if (irq >= GICV3_MAXIRQ) {
         /* Also catches special interrupt numbers and LPIs */
         return;
     }
-- 
2.20.1

Convert the use of the DPRINTF debug macro in the PL061 model to
use tracepoints.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/gpio/pl061.c      | 27 +++++++++------------------
 hw/gpio/trace-events |  6 ++++++
 2 files changed, 15 insertions(+), 18 deletions(-)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/pl061.c
+++ b/hw/gpio/pl061.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/log.h"
 #include "qemu/module.h"
 #include "qom/object.h"
-
-//#define DEBUG_PL061 1
-
-#ifdef DEBUG_PL061
-#define DPRINTF(fmt, ...) \
-do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0)
-#define BADF(fmt, ...) \
-do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
-#else
-#define DPRINTF(fmt, ...) do {} while(0)
-#define BADF(fmt, ...) \
-do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0)
-#endif
+#include "trace.h"
 
 static const uint8_t pl061_id[12] =
   { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
     uint8_t out;
     int i;
 
-    DPRINTF("dir = %d, data = %d\n", s->dir, s->data);
+    trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data);
 
     /* Outputs float high.  */
     /* FIXME: This is board dependent.  */
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
         for (i = 0; i < N_GPIOS; i++) {
             mask = 1 << i;
             if (changed & mask) {
-                DPRINTF("Set output %d = %d\n", i, (out & mask) != 0);
-                qemu_set_irq(s->out[i], (out & mask) != 0);
+                int level = (out & mask) != 0;
+                trace_pl061_set_output(DEVICE(s)->canonical_path, i, level);
+                qemu_set_irq(s->out[i], level);
             }
         }
     }
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
         for (i = 0; i < N_GPIOS; i++) {
             mask = 1 << i;
             if (changed & mask) {
-                DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0);
+                trace_pl061_input_change(DEVICE(s)->canonical_path, i,
+                                         (s->data & mask) != 0);
 
                 if (!(s->isense & mask)) {
                     /* Edge interrupt */
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
     /* Level interrupt */
     s->istate |= ~(s->data ^ s->iev) & s->isense;
 
-    DPRINTF("istate = %02X\n", s->istate);
+    trace_pl061_update_istate(DEVICE(s)->canonical_path,
+                              s->istate, s->im, (s->istate & s->im) != 0);
 
     qemu_set_irq(s->irq, (s->istate & s->im) != 0);
 }
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/trace-events
+++ b/hw/gpio/trace-events
@@ -XXX,XX +XXX,XX @@ nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x
 nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 
+# pl061.c
+pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIODATA 0x%x"
+pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"
+pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"
+pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
+
 # sifive_gpio.c
 sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
 sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
-- 
2.20.1

Currently the pl061_read() and pl061_write() functions handle offsets
using a combination of three if() statements and a switch().  Clean
this up to use just a switch, using case ranges.

This requires that instead of catching accesses to the luminary-only
registers on a stock PL061 via a check on s->rsvd_start we use
an "is this luminary?" check in the cases for each luminary-only
register.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/gpio/pl061.c | 104 ++++++++++++++++++++++++++++++++++++------------
 1 file changed, 79 insertions(+), 25 deletions(-)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/pl061.c
+++ b/hw/gpio/pl061.c
@@ -XXX,XX +XXX,XX @@ struct PL061State {
     qemu_irq irq;
     qemu_irq out[N_GPIOS];
     const unsigned char *id;
-    uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */
 };
 
 static const VMStateDescription vmstate_pl061 = {
@@ -XXX,XX +XXX,XX @@ static uint64_t pl061_read(void *opaque, hwaddr offset,
 {
     PL061State *s = (PL061State *)opaque;
 
-    if (offset < 0x400) {
-        return s->data & (offset >> 2);
-    }
-    if (offset >= s->rsvd_start && offset <= 0xfcc) {
-        goto err_out;
-    }
-    if (offset >= 0xfd0 && offset < 0x1000) {
-        return s->id[(offset - 0xfd0) >> 2];
-    }
     switch (offset) {
+    case 0x0 ... 0x3ff: /* Data */
+        return s->data & (offset >> 2);
     case 0x400: /* Direction */
         return s->dir;
     case 0x404: /* Interrupt sense */
@@ -XXX,XX +XXX,XX @@ static uint64_t pl061_read(void *opaque, hwaddr offset,
     case 0x420: /* Alternate function select */
         return s->afsel;
     case 0x500: /* 2mA drive */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->dr2r;
     case 0x504: /* 4mA drive */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->dr4r;
     case 0x508: /* 8mA drive */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->dr8r;
     case 0x50c: /* Open drain */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->odr;
     case 0x510: /* Pull-up */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->pur;
     case 0x514: /* Pull-down */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->pdr;
     case 0x518: /* Slew rate control */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->slr;
     case 0x51c: /* Digital enable */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->den;
     case 0x520: /* Lock */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->locked;
     case 0x524: /* Commit */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->cr;
     case 0x528: /* Analog mode select */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->amsel;
+    case 0xfd0 ... 0xfff: /* ID registers */
+        return s->id[(offset - 0xfd0) >> 2];
     default:
+    bad_offset:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "pl061_read: Bad offset %x\n", (int)offset);
         break;
     }
-err_out:
-    qemu_log_mask(LOG_GUEST_ERROR,
-                  "pl061_read: Bad offset %x\n", (int)offset);
     return 0;
 }
 
@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,
     PL061State *s = (PL061State *)opaque;
     uint8_t mask;
 
-    if (offset < 0x400) {
+    switch (offset) {
+    case 0 ... 0x3ff:
         mask = (offset >> 2) & s->dir;
         s->data = (s->data & ~mask) | (value & mask);
         pl061_update(s);
         return;
-    }
-    if (offset >= s->rsvd_start) {
-        goto err_out;
-    }
-    switch (offset) {
     case 0x400: /* Direction */
         s->dir = value & 0xff;
         break;
@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,
         s->afsel = (s->afsel & ~mask) | (value & mask);
         break;
     case 0x500: /* 2mA drive */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->dr2r = value & 0xff;
         break;
     case 0x504: /* 4mA drive */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->dr4r = value & 0xff;
         break;
     case 0x508: /* 8mA drive */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->dr8r = value & 0xff;
         break;
     case 0x50c: /* Open drain */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->odr = value & 0xff;
         break;
     case 0x510: /* Pull-up */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->pur = value & 0xff;
         break;
     case 0x514: /* Pull-down */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->pdr = value & 0xff;
         break;
     case 0x518: /* Slew rate control */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->slr = value & 0xff;
         break;
     case 0x51c: /* Digital enable */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->den = value & 0xff;
         break;
     case 0x520: /* Lock */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->locked = (value != 0xacce551);
         break;
     case 0x524: /* Commit */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         if (!s->locked)
             s->cr = value & 0xff;
         break;
     case 0x528:
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->amsel = value & 0xff;
         break;
     default:
-        goto err_out;
+    bad_offset:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "pl061_write: Bad offset %x\n", (int)offset);
+        return;
     }
     pl061_update(s);
     return;
-err_out:
-    qemu_log_mask(LOG_GUEST_ERROR,
-                  "pl061_write: Bad offset %x\n", (int)offset);
 }
 
 static void pl061_reset(DeviceState *dev)
@@ -XXX,XX +XXX,XX @@ static void pl061_luminary_init(Object *obj)
     PL061State *s = PL061(obj);
 
     s->id = pl061_id_luminary;
-    s->rsvd_start = 0x52c;
 }
 
 static void pl061_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void pl061_init(Object *obj)
     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 
     s->id = pl061_id;
-    s->rsvd_start = 0x424;
 
     memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000);
     sysbus_init_mmio(sbd, &s->iomem);
-- 
2.20.1

Add tracepoints for reads and writes to the PL061 registers. This requires
restructuring pl061_read() to only return after the tracepoint, rather
than having lots of early-returns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/gpio/pl061.c      | 70 ++++++++++++++++++++++++++++++--------------
 hw/gpio/trace-events |  2 ++
 2 files changed, 50 insertions(+), 22 deletions(-)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/pl061.c
+++ b/hw/gpio/pl061.c
@@ -XXX,XX +XXX,XX @@ static uint64_t pl061_read(void *opaque, hwaddr offset,
                            unsigned size)
 {
     PL061State *s = (PL061State *)opaque;
+    uint64_t r = 0;
 
     switch (offset) {
     case 0x0 ... 0x3ff: /* Data */
-        return s->data & (offset >> 2);
+        r = s->data & (offset >> 2);
+        break;
     case 0x400: /* Direction */
-        return s->dir;
+        r = s->dir;
+        break;
     case 0x404: /* Interrupt sense */
-        return s->isense;
+        r = s->isense;
+        break;
     case 0x408: /* Interrupt both edges */
-        return s->ibe;
+        r = s->ibe;
+        break;
     case 0x40c: /* Interrupt event */
-        return s->iev;
+        r = s->iev;
+        break;
     case 0x410: /* Interrupt mask */
-        return s->im;
+        r = s->im;
+        break;
     case 0x414: /* Raw interrupt status */
-        return s->istate;
+        r = s->istate;
+        break;
     case 0x418: /* Masked interrupt status */
-        return s->istate & s->im;
+        r = s->istate & s->im;
+        break;
     case 0x420: /* Alternate function select */
-        return s->afsel;
+        r = s->afsel;
+        break;
     case 0x500: /* 2mA drive */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->dr2r;
+        r = s->dr2r;
+        break;
     case 0x504: /* 4mA drive */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->dr4r;
+        r = s->dr4r;
+        break;
     case 0x508: /* 8mA drive */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->dr8r;
+        r = s->dr8r;
+        break;
     case 0x50c: /* Open drain */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->odr;
+        r = s->odr;
+        break;
     case 0x510: /* Pull-up */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->pur;
+        r = s->pur;
+        break;
     case 0x514: /* Pull-down */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->pdr;
+        r = s->pdr;
+        break;
     case 0x518: /* Slew rate control */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->slr;
+        r = s->slr;
+        break;
     case 0x51c: /* Digital enable */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->den;
+        r = s->den;
+        break;
     case 0x520: /* Lock */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->locked;
+        r = s->locked;
+        break;
     case 0x524: /* Commit */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->cr;
+        r = s->cr;
+        break;
     case 0x528: /* Analog mode select */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->amsel;
+        r = s->amsel;
+        break;
     case 0xfd0 ... 0xfff: /* ID registers */
-        return s->id[(offset - 0xfd0) >> 2];
+        r = s->id[(offset - 0xfd0) >> 2];
+        break;
     default:
     bad_offset:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "pl061_read: Bad offset %x\n", (int)offset);
         break;
     }
-    return 0;
+
+    trace_pl061_read(DEVICE(s)->canonical_path, offset, r);
+    return r;
 }
 
 static void pl061_write(void *opaque, hwaddr offset,
@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,
     PL061State *s = (PL061State *)opaque;
     uint8_t mask;
 
+    trace_pl061_write(DEVICE(s)->canonical_path, offset, value);
+
     switch (offset) {
     case 0 ... 0x3ff:
         mask = (offset >> 2) & s->dir;
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/trace-events
+++ b/hw/gpio/trace-events
@@ -XXX,XX +XXX,XX @@ pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIOD
 pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"
 pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"
 pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
+pl061_read(const char *id, uint64_t offset, uint64_t r) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
+pl061_write(const char *id, uint64_t offset, uint64_t value) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
 
 # sifive_gpio.c
 sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
-- 
2.20.1

The Luminary variant of the PL061 has registers GPIOPUR and GPIOPDR
which lets the guest configure whether the GPIO lines are pull-up,
pull-down, or truly floating. Instead of assuming all lines are pulled
high, honour the PUR and PDR registers.

For the plain PL061, continue to assume that lines have an external
pull-up resistor, as we did before.

The stellaris board actually relies on this behaviour -- the CD line
of the ssd0323 display device is connected to GPIO output C7, and it
is only because of a different bug which we're about to fix that we
weren't incorrectly driving this line high on reset and putting the
ssd0323 into data mode.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/gpio/pl061.c      | 58 +++++++++++++++++++++++++++++++++++++++++---
 hw/gpio/trace-events |  2 +-
 2 files changed, 55 insertions(+), 5 deletions(-)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/pl061.c
+++ b/hw/gpio/pl061.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl061 = {
     }
 };
 
+static uint8_t pl061_floating(PL061State *s)
+{
+    /*
+     * Return mask of bits which correspond to pins configured as inputs
+     * and which are floating (neither pulled up to 1 nor down to 0).
+     */
+    uint8_t floating;
+
+    if (s->id == pl061_id_luminary) {
+        /*
+         * If both PUR and PDR bits are clear, there is neither a pullup
+         * nor a pulldown in place, and the output truly floats.
+         */
+        floating = ~(s->pur | s->pdr);
+    } else {
+        /* Assume outputs are pulled high. FIXME: this is board dependent. */
+        floating = 0;
+    }
+    return floating & ~s->dir;
+}
+
+static uint8_t pl061_pullups(PL061State *s)
+{
+    /*
+     * Return mask of bits which correspond to pins configured as inputs
+     * and which are pulled up to 1.
+     */
+    uint8_t pullups;
+
+    if (s->id == pl061_id_luminary) {
+        /*
+         * The Luminary variant of the PL061 has an extra registers which
+         * the guest can use to configure whether lines should be pullup
+         * or pulldown.
+         */
+        pullups = s->pur;
+    } else {
+        /* Assume outputs are pulled high. FIXME: this is board dependent. */
+        pullups = 0xff;
+    }
+    return pullups & ~s->dir;
+}
+
 static void pl061_update(PL061State *s)
 {
     uint8_t changed;
     uint8_t mask;
     uint8_t out;
     int i;
+    uint8_t pullups = pl061_pullups(s);
+    uint8_t floating = pl061_floating(s);
 
-    trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data);
+    trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data,
+                       pullups, floating);
 
-    /* Outputs float high.  */
-    /* FIXME: This is board dependent.  */
-    out = (s->data & s->dir) | ~s->dir;
+    /*
+     * Pins configured as output are driven from the data register;
+     * otherwise if they're pulled up they're 1, and if they're floating
+     * then we give them the same value they had previously, so we don't
+     * report any change to the other end.
+     */
+    out = (s->data & s->dir) | pullups | (s->old_out_data & floating);
     changed = s->old_out_data ^ out;
     if (changed) {
         s->old_out_data = out;
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/trace-events
+++ b/hw/gpio/trace-events
@@ -XXX,XX +XXX,XX @@ nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 
 # pl061.c
-pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIODATA 0x%x"
+pl061_update(const char *id, uint32_t dir, uint32_t data, uint32_t pullups, uint32_t floating) "%s GPIODIR 0x%x GPIODATA 0x%x pullups 0x%x floating 0x%x"
 pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"
 pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"
 pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
-- 
2.20.1

The PL061 GPIO does not itself include pullup or pulldown resistors
to set the value of a GPIO line treated as an output when it is
configured as an input (ie when the PL061 itself is not driving it).
In real hardware it is up to the board to add suitable pullups or
pulldowns.  Currently our implementation hardwires this to "outputs
pulled high", which is correct for some boards (eg the realview ones:
see figure 3-29 in the "RealView Platform Baseboard for ARM926EJ-S
User Guide" DUI0224I), but wrong for others.

In particular, the wiring in the 'virt' board and the gpio-pwr device
assumes that wires should be pulled low, because otherwise the
pull-to-high will trigger a shutdown or reset action.  (The only
reason this doesn't happen immediately on startup is due to another
bug in the PL061, where we don't assert the GPIOs to the correct
value on reset, but will do so as soon as the guest touches a
register and pl061_update() gets called.)

Add properties to the pl061 so the board can configure whether it
wants GPIO lines to have pullup, pulldown, or neither.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/gpio/pl061.c | 51 +++++++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 47 insertions(+), 4 deletions(-)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/pl061.c
+++ b/hw/gpio/pl061.c
@@ -XXX,XX +XXX,XX @@
  *  + unnamed GPIO inputs 0..7: inputs to connect to the emulated GPIO lines
  *  + unnamed GPIO outputs 0..7: the emulated GPIO lines, considered as
  *    outputs
+ *  + QOM property "pullups": an integer defining whether non-floating lines
+ *    configured as inputs should be pulled up to logical 1 (ie whether in
+ *    real hardware they have a pullup resistor on the line out of the PL061).
+ *    This should be an 8-bit value, where bit 0 is 1 if GPIO line 0 should
+ *    be pulled high, bit 1 configures line 1, and so on. The default is 0xff,
+ *    indicating that all GPIO lines are pulled up to logical 1.
+ *  + QOM property "pulldowns": an integer defining whether non-floating lines
+ *    configured as inputs should be pulled down to logical 0 (ie whether in
+ *    real hardware they have a pulldown resistor on the line out of the PL061).
+ *    This should be an 8-bit value, where bit 0 is 1 if GPIO line 0 should
+ *    be pulled low, bit 1 configures line 1, and so on. The default is 0x0.
+ *    It is an error to set a bit in both "pullups" and "pulldowns". If a bit
+ *    is 0 in both, then the line is considered to be floating, and it will
+ *    not have qemu_set_irq() called on it when it is configured as an input.
  */
 
 #include "qemu/osdep.h"
 #include "hw/irq.h"
 #include "hw/sysbus.h"
+#include "hw/qdev-properties.h"
 #include "migration/vmstate.h"
+#include "qapi/error.h"
 #include "qemu/log.h"
 #include "qemu/module.h"
 #include "qom/object.h"
@@ -XXX,XX +XXX,XX @@ struct PL061State {
     qemu_irq irq;
     qemu_irq out[N_GPIOS];
     const unsigned char *id;
+    /* Properties, for non-Luminary PL061 */
+    uint32_t pullups;
+    uint32_t pulldowns;
 };
 
 static const VMStateDescription vmstate_pl061 = {
@@ -XXX,XX +XXX,XX @@ static uint8_t pl061_floating(PL061State *s)
          */
         floating = ~(s->pur | s->pdr);
     } else {
-        /* Assume outputs are pulled high. FIXME: this is board dependent. */
-        floating = 0;
+        floating = ~(s->pullups | s->pulldowns);
     }
     return floating & ~s->dir;
 }
@@ -XXX,XX +XXX,XX @@ static uint8_t pl061_pullups(PL061State *s)
          */
         pullups = s->pur;
     } else {
-        /* Assume outputs are pulled high. FIXME: this is board dependent. */
-        pullups = 0xff;
+        pullups = s->pullups;
     }
     return pullups & ~s->dir;
 }
@@ -XXX,XX +XXX,XX @@ static void pl061_init(Object *obj)
     qdev_init_gpio_out(dev, s->out, N_GPIOS);
 }
 
+static void pl061_realize(DeviceState *dev, Error **errp)
+{
+    PL061State *s = PL061(dev);
+
+    if (s->pullups > 0xff) {
+        error_setg(errp, "pullups property must be between 0 and 0xff");
+        return;
+    }
+    if (s->pulldowns > 0xff) {
+        error_setg(errp, "pulldowns property must be between 0 and 0xff");
+        return;
+    }
+    if (s->pullups & s->pulldowns) {
+        error_setg(errp, "no bit may be set both in pullups and pulldowns");
+        return;
+    }
+}
+
+static Property pl061_props[] = {
+    DEFINE_PROP_UINT32("pullups", PL061State, pullups, 0xff),
+    DEFINE_PROP_UINT32("pulldowns", PL061State, pulldowns, 0x0),
+    DEFINE_PROP_END_OF_LIST()
+};
+
 static void pl061_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
 
     dc->vmsd = &vmstate_pl061;
     dc->reset = &pl061_reset;
+    dc->realize = pl061_realize;
+    device_class_set_props(dc, pl061_props);
 }
 
 static const TypeInfo pl061_info = {
-- 
2.20.1

For the virt board we have two PL061 devices -- one for NonSecure which
is inputs only, and one for Secure which is outputs only. For the former,
we don't care whether its outputs are pulled low or high when the line is
configured as an input, because we don't connect them. For the latter,
we do care, because we wire the lines up to the gpio-pwr device, which
assumes that level 1 means "do the action" and 1 means "do nothing".
For consistency in case we add more outputs in future, configure both
PL061s to pull GPIO lines down to 0.

Reported-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/arm/virt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_gpio_devices(const VirtMachineState *vms, int gpio,
     MachineState *ms = MACHINE(vms);
 
     pl061_dev = qdev_new("pl061");
+    /* Pull lines down to 0 if not driven by the PL061 */
+    qdev_prop_set_uint32(pl061_dev, "pullups", 0);
+    qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff);
     s = SYS_BUS_DEVICE(pl061_dev);
     sysbus_realize_and_unref(s, &error_fatal);
     memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0));
-- 
2.20.1

The PL061 comes out of reset with all its lines configured as input,
which means they might need to be pulled to 0 or 1 depending on the
'pullups' and 'pulldowns' properties.  Currently we do not assert
these lines on reset; they will only be set whenever the guest first
touches a register that triggers a call to pl061_update().

Convert the device to three-phase reset so we have a place where we
can safely call qemu_set_irq() to set the floating lines to their
correct values.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/gpio/pl061.c      | 29 +++++++++++++++++++++++++----
 hw/gpio/trace-events |  1 +
 2 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/pl061.c
+++ b/hw/gpio/pl061.c
@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,
     return;
 }
 
-static void pl061_reset(DeviceState *dev)
+static void pl061_enter_reset(Object *obj, ResetType type)
 {
-    PL061State *s = PL061(dev);
+    PL061State *s = PL061(obj);
+
+    trace_pl061_reset(DEVICE(s)->canonical_path);
 
     /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */
     s->data = 0;
-    s->old_out_data = 0;
     s->old_in_data = 0;
     s->dir = 0;
     s->isense = 0;
@@ -XXX,XX +XXX,XX @@ static void pl061_reset(DeviceState *dev)
     s->amsel = 0;
 }
 
+static void pl061_hold_reset(Object *obj)
+{
+    PL061State *s = PL061(obj);
+    int i, level;
+    uint8_t floating = pl061_floating(s);
+    uint8_t pullups = pl061_pullups(s);
+
+    for (i = 0; i < N_GPIOS; i++) {
+        if (extract32(floating, i, 1)) {
+            continue;
+        }
+        level = extract32(pullups, i, 1);
+        trace_pl061_set_output(DEVICE(s)->canonical_path, i, level);
+        qemu_set_irq(s->out[i], level);
+    }
+    s->old_out_data = pullups;
+}
+
 static void pl061_set_irq(void * opaque, int irq, int level)
 {
     PL061State *s = (PL061State *)opaque;
@@ -XXX,XX +XXX,XX @@ static Property pl061_props[] = {
 static void pl061_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
     dc->vmsd = &vmstate_pl061;
-    dc->reset = &pl061_reset;
     dc->realize = pl061_realize;
     device_class_set_props(dc, pl061_props);
+    rc->phases.enter = pl061_enter_reset;
+    rc->phases.hold = pl061_hold_reset;
 }
 
 static const TypeInfo pl061_info = {
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/trace-events
+++ b/hw/gpio/trace-events
@@ -XXX,XX +XXX,XX @@ pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to
 pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
 pl061_read(const char *id, uint64_t offset, uint64_t r) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
 pl061_write(const char *id, uint64_t offset, uint64_t value) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
+pl061_reset(const char *id) "%s reset"
 
 # sifive_gpio.c
 sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
-- 
2.20.1

The Luminary PL061s in the Stellaris LM3S9695 don't all have the same
reset value for GPIOPUR.  We can get away with not letting the board
configure the PUR reset value because we don't actually wire anything
up to the lines which should reset to pull-up.  Add a comment noting
this omission.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 hw/gpio/pl061.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/pl061.c
+++ b/hw/gpio/pl061.c
@@ -XXX,XX +XXX,XX @@ static void pl061_enter_reset(Object *obj, ResetType type)
     trace_pl061_reset(DEVICE(s)->canonical_path);
 
     /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */
+
+    /*
+     * FIXME: For the LM3S6965, not all of the PL061 instances have the
+     * same reset values for GPIOPUR, GPIOAFSEL and GPIODEN, so in theory
+     * we should allow the board to configure these via properties.
+     * In practice, we don't wire anything up to the affected GPIO lines
+     * (PB7, PC0, PC1, PC2, PC3 -- they're used for JTAG), so we can
+     * get away with this inaccuracy.
+     */
     s->data = 0;
     s->old_in_data = 0;
     s->dir = 0;
-- 
2.20.1

The stellaris board doesn't emulate the handling of the OLED
chipselect line correctly.  Expand the comment describing this,
including a sketch of the theoretical correct way to do it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/stellaris.c | 56 +++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 55 insertions(+), 1 deletion(-)

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
             DeviceState *sddev;
             DeviceState *ssddev;
 
-            /* Some boards have both an OLED controller and SD card connected to
+            /*
+             * Some boards have both an OLED controller and SD card connected to
              * the same SSI port, with the SD card chip select connected to a
              * GPIO pin.  Technically the OLED chip select is connected to the
              * SSI Fss pin.  We do not bother emulating that as both devices
              * should never be selected simultaneously, and our OLED controller
              * ignores stray 0xff commands that occur when deselecting the SD
              * card.
+             *
+             * The h/w wiring is:
+             *  - GPIO pin D0 is wired to the active-low SD card chip select
+             *  - GPIO pin A3 is wired to the active-low OLED chip select
+             *  - The SoC wiring of the PL061 "auxiliary function" for A3 is
+             *    SSI0Fss ("frame signal"), which is an output from the SoC's
+             *    SSI controller. The SSI controller takes SSI0Fss low when it
+             *    transmits a frame, so it can work as a chip-select signal.
+             *  - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx
+             *    (the OLED never sends data to the CPU, so no wiring needed)
+             *  - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx
+             *    and the OLED display-data-in
+             *  - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED
+             *    serial-clock input
+             * So a guest that wants to use the OLED can configure the PL061
+             * to make pins A2, A3, A5 aux-function, so they are connected
+             * directly to the SSI controller. When the SSI controller sends
+             * data it asserts SSI0Fss which selects the OLED.
+             * A guest that wants to use the SD card configures A2, A4 and A5
+             * as aux-function, but leaves A3 as a software-controlled GPIO
+             * line. It asserts the SD card chip-select by using the PL061
+             * to control pin D0, and lets the SSI controller handle Clk, Tx
+             * and Rx. (The SSI controller asserts Fss during tx cycles as
+             * usual, but because A3 is not set to aux-function this is not
+             * forwarded to the OLED, and so the OLED stays unselected.)
+             *
+             * The QEMU implementation instead is:
+             *  - GPIO pin D0 is wired to the active-low SD card chip select,
+             *    and also to the OLED chip-select which is implemented
+             *    as *active-high*
+             *  - SSI controller signals go to the devices regardless of
+             *    whether the guest programs A2, A4, A5 as aux-function or not
+             *
+             * The problem with this implementation is if the guest doesn't
+             * care about the SD card and only uses the OLED. In that case it
+             * may choose never to do anything with D0 (leaving it in its
+             * default floating state, which reliably leaves the card disabled
+             * because an SD card has a pullup on CS within the card itself),
+             * and only set up A2, A3, A5. This for us would mean the OLED
+             * never gets the chip-select assert it needs. We work around
+             * this with a manual raise of D0 here (despite board creation
+             * code being the wrong place to raise IRQ lines) to put the OLED
+             * into an initially selected state.
+             *
+             * In theory the right way to model this would be:
+             *  - Implement aux-function support in the PL061, with an
+             *    extra set of AFIN and AFOUT GPIO lines (set up so that
+             *    if a GPIO line is in auxfn mode the main GPIO in and out
+             *    track the AFIN and AFOUT lines)
+             *  - Wire the AFOUT for D0 up to either a line from the
+             *    SSI controller that's pulled low around every transmit,
+             *    or at least to an always-0 line here on the board
+             *  - Make the ssd0323 OLED controller chipselect active-low
              */
             bus = qdev_get_child_bus(dev, "ssi");
 
-- 
2.20.1

From: "hnick@vmware.com" <hnick@vmware.com>

Signed-off-by: Nick Hudson <hnick@vmware.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
       .access = PL1_RW, .accessfn = access_tda,
       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
       .resetvalue = 0 },
-    /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
+    /*
+     * MDCCSR_EL0[30:29] map to EDSCR[30:29].  Simply RAZ as the external
+     * Debug Communication Channel is not implemented.
+     */
+    { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64,
+      .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
+      .access = PL0_R, .accessfn = access_tda,
+      .type = ARM_CP_CONST, .resetvalue = 0 },
+    /*
+     * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2].  Map all bits as
+     * it is unlikely a guest will care.
      * We don't implement the configurable EL0 access.
      */
-    { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
-      .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
+    { .name = "DBGDSCRint", .state = ARM_CP_STATE_AA32,
+      .cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
       .type = ARM_CP_ALIAS,
       .access = PL1_R, .accessfn = access_tda,
       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
-- 
2.20.1

From: Rebecca Cran <rebecca@nuviainc.com>

Add a space in the message printed when gicr_read*/gicr_write* returns
MEMTX_ERROR in arm_gicv3_redist.c.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210706211432.31902-1-rebecca@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_redist.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -XXX,XX +XXX,XX @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data,
     if (r == MEMTX_ERROR) {
         qemu_log_mask(LOG_GUEST_ERROR,
                       "%s: invalid guest read at offset " TARGET_FMT_plx
-                      "size %u\n", __func__, offset, size);
+                      " size %u\n", __func__, offset, size);
         trace_gicv3_redist_badread(gicv3_redist_affid(cs), offset,
                                    size, attrs.secure);
         /* The spec requires that reserved registers are RAZ/WI;
@@ -XXX,XX +XXX,XX @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data,
     if (r == MEMTX_ERROR) {
         qemu_log_mask(LOG_GUEST_ERROR,
                       "%s: invalid guest write at offset " TARGET_FMT_plx
-                      "size %u\n", __func__, offset, size);
+                      " size %u\n", __func__, offset, size);
         trace_gicv3_redist_badwrite(gicv3_redist_affid(cs), offset, data,
                                     size, attrs.secure);
         /* The spec requires that reserved registers are RAZ/WI;
-- 
2.20.1

Hi; here's the latest round of arm patches. I have included also
my patchset for the RTC devices to avoid keeping time_t and
time_t diffs in 32-bit variables.

thanks
-- PMM

The following changes since commit 156618d9ea67f2f2e31d9dedd97f2dcccbe6808c:

Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-08-30 09:20:27 -0400)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230831

for you to fetch changes up to e73b8bb8a3e9a162f70e9ffbf922d4fafc96bbfb:

hw/arm: Set number of MPU regions correctly for an505, an521, an524 (2023-08-31 11:07:02 +0100)

----------------------------------------------------------------
target-arm queue:
 * Some of the preliminary patches for Cortex-A710 support
 * i.MX7 and i.MX6UL refactoring
 * Implement SRC device for i.MX7
 * Catch illegal-exception-return from EL3 with bad NSE/NS
 * Use 64-bit offsets for holding time_t differences in RTC devices
 * Model correct number of MPU regions for an505, an521, an524 boards

----------------------------------------------------------------
Alex Bennée (1):
      target/arm: properly document FEAT_CRC32

Jean-Christophe Dubois (6):
      Remove i.MX7 IOMUX GPR device from i.MX6UL
      Refactor i.MX6UL processor code
      Add i.MX6UL missing devices.
      Refactor i.MX7 processor code
      Add i.MX7 missing TZ devices and memory regions
      Add i.MX7 SRC device implementation

Peter Maydell (8):
      target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS
      hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()
      hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec
      hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference
      rtc: Use time_t for passing and returning time offsets
      target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init
      hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties
      hw/arm: Set number of MPU regions correctly for an505, an521, an524

Richard Henderson (9):
      target/arm: Reduce dcz_blocksize to uint8_t
      target/arm: Allow cpu to configure GM blocksize
      target/arm: Support more GM blocksizes
      target/arm: When tag memory is not present, set MTE=1
      target/arm: Introduce make_ccsidr64
      target/arm: Apply access checks to neoverse-n1 special registers
      target/arm: Apply access checks to neoverse-v1 special registers
      target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)
      target/arm: Implement FEAT_HPDS2 as a no-op

From: Richard Henderson <richard.henderson@linaro.org>

Previously we hard-coded the blocksize with GMID_EL1_BS.
But the value we choose for -cpu max does not match the
value that cortex-a710 uses.

Mirror the way we handle dcz_blocksize.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230811214031.171020-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h               |  2 ++
 target/arm/internals.h         |  6 -----
 target/arm/tcg/translate.h     |  2 ++
 target/arm/helper.c            | 11 +++++---
 target/arm/tcg/cpu64.c         |  1 +
 target/arm/tcg/mte_helper.c    | 46 ++++++++++++++++++++++------------
 target/arm/tcg/translate-a64.c |  5 ++--
 7 files changed, 45 insertions(+), 28 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
 
     /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
     uint8_t dcz_blocksize;
+    /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */
+    uint8_t gm_blocksize;
 
     uint64_t rvbar_prop; /* Property/input signals.  */
 
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs);
 
 #endif /* !CONFIG_USER_ONLY */
 
-/*
- * The log2 of the words in the tag block, for GMID_EL1.BS.
- * The is the maximum, 256 bytes, which manipulates 64-bits of tags.
- */
-#define GMID_EL1_BS  6
-
 /*
  * SVE predicates are 1/8 the size of SVE vectors, and cannot use
  * the same simd_desc() encoding due to restrictions on size.
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     int8_t btype;
     /* A copy of cpu->dcz_blocksize. */
     uint8_t dcz_blocksize;
+    /* A copy of cpu->gm_blocksize. */
+    uint8_t gm_blocksize;
     /* True if this page is guarded.  */
     bool guarded_page;
     /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
       .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6,
       .access = PL1_RW, .accessfn = access_mte,
       .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) },
-    { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
-      .access = PL1_R, .accessfn = access_aa64_tid5,
-      .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS },
     { .name = "TCO", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
       .type = ARM_CP_NO_RAW,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
      * then define only a RAZ/WI version of PSTATE.TCO.
      */
     if (cpu_isar_feature(aa64_mte, cpu)) {
+        ARMCPRegInfo gmid_reginfo = {
+            .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
+            .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
+            .access = PL1_R, .accessfn = access_aa64_tid5,
+            .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize,
+        };
+        define_one_arm_cp_reg(cpu, &gmid_reginfo);
         define_arm_cp_regs(cpu, mte_reginfo);
         define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
     } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) {
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
     cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
     cpu->dcz_blocksize = 7; /*  512 bytes */
 #endif
+    cpu->gm_blocksize = 6;  /*  256 bytes */
 
     cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
     cpu->sme_vq.supported = SVE_VQ_POW2_MAP;
diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/mte_helper.c
+++ b/target/arm/tcg/mte_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr)
     }
 }
 
-#define LDGM_STGM_SIZE  (4 << GMID_EL1_BS)
-
 uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
 {
     int mmu_idx = cpu_mmu_index(env, false);
     uintptr_t ra = GETPC();
+    int gm_bs = env_archcpu(env)->gm_blocksize;
+    int gm_bs_bytes = 4 << gm_bs;
     void *tag_mem;
 
-    ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
+    ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
 
     /* Trap if accessing an invalid page.  */
     tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD,
-                                 LDGM_STGM_SIZE, MMU_DATA_LOAD,
-                                 LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
+                                 gm_bs_bytes, MMU_DATA_LOAD,
+                                 gm_bs_bytes / (2 * TAG_GRANULE), ra);
 
     /* The tag is squashed to zero if the page does not support tags.  */
     if (!tag_mem) {
         return 0;
     }
 
-    QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
     /*
-     * We are loading 64-bits worth of tags.  The ordering of elements
-     * within the word corresponds to a 64-bit little-endian operation.
+     * The ordering of elements within the word corresponds to
+     * a little-endian operation.
      */
-    return ldq_le_p(tag_mem);
+    switch (gm_bs) {
+    case 6:
+        /* 256 bytes -> 16 tags -> 64 result bits */
+        return ldq_le_p(tag_mem);
+    default:
+        /* cpu configured with unsupported gm blocksize. */
+        g_assert_not_reached();
+    }
 }
 
 void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
 {
     int mmu_idx = cpu_mmu_index(env, false);
     uintptr_t ra = GETPC();
+    int gm_bs = env_archcpu(env)->gm_blocksize;
+    int gm_bs_bytes = 4 << gm_bs;
     void *tag_mem;
 
-    ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
+    ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
 
     /* Trap if accessing an invalid page.  */
     tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE,
-                                 LDGM_STGM_SIZE, MMU_DATA_LOAD,
-                                 LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
+                                 gm_bs_bytes, MMU_DATA_LOAD,
+                                 gm_bs_bytes / (2 * TAG_GRANULE), ra);
 
     /*
      * Tag store only happens if the page support tags,
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
         return;
     }
 
-    QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
     /*
-     * We are storing 64-bits worth of tags.  The ordering of elements
-     * within the word corresponds to a 64-bit little-endian operation.
+     * The ordering of elements within the word corresponds to
+     * a little-endian operation.
      */
-    stq_le_p(tag_mem, val);
+    switch (gm_bs) {
+    case 6:
+        stq_le_p(tag_mem, val);
+        break;
+    default:
+        /* cpu configured with unsupported gm blocksize. */
+        g_assert_not_reached();
+    }
 }
 
 void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static bool trans_STGM(DisasContext *s, arg_ldst_tag *a)
         gen_helper_stgm(cpu_env, addr, tcg_rt);
     } else {
         MMUAccessType acc = MMU_DATA_STORE;
-        int size = 4 << GMID_EL1_BS;
+        int size = 4 << s->gm_blocksize;
 
         clean_addr = clean_data_tbi(s, addr);
         tcg_gen_andi_i64(clean_addr, clean_addr, -size);
@@ -XXX,XX +XXX,XX @@ static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a)
         gen_helper_ldgm(tcg_rt, cpu_env, addr);
     } else {
         MMUAccessType acc = MMU_DATA_LOAD;
-        int size = 4 << GMID_EL1_BS;
+        int size = 4 << s->gm_blocksize;
 
         clean_addr = clean_data_tbi(s, addr);
         tcg_gen_andi_i64(clean_addr, clean_addr, -size);
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
     dc->cp_regs = arm_cpu->cp_regs;
     dc->features = env->features;
     dc->dcz_blocksize = arm_cpu->dcz_blocksize;
+    dc->gm_blocksize = arm_cpu->gm_blocksize;
 
 #ifdef CONFIG_USER_ONLY
     /* In sve_probe_page, we assume TBI is enabled. */
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Support all of the easy GM block sizes.
Use direct memory operations, since the pointers are aligned.

While BS=2 (16 bytes, 1 tag) is a legal setting, that requires
an atomic store of one nibble.  This is not difficult, but there
is also no point in supporting it until required.

Note that cortex-a710 sets GM blocksize to match its cacheline
size of 64 bytes.  I expect many implementations will also
match the cacheline, which makes 16 bytes very unlikely.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c            | 18 +++++++++---
 target/arm/tcg/mte_helper.c | 56 +++++++++++++++++++++++++++++++------
 2 files changed, 62 insertions(+), 12 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
                                        ID_PFR1, VIRTUALIZATION, 0);
     }
 
+    if (cpu_isar_feature(aa64_mte, cpu)) {
+        /*
+         * The architectural range of GM blocksize is 2-6, however qemu
+         * doesn't support blocksize of 2 (see HELPER(ldgm)).
+         */
+        if (tcg_enabled()) {
+            assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6);
+        }
+
 #ifndef CONFIG_USER_ONLY
-    if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) {
         /*
          * Disable the MTE feature bits if we do not have tag-memory
          * provided by the machine.
          */
-        cpu->isar.id_aa64pfr1 =
-            FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
-    }
+        if (cpu->tag_memory == NULL) {
+            cpu->isar.id_aa64pfr1 =
+                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
+        }
 #endif
+    }
 
     if (tcg_enabled()) {
         /*
diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/mte_helper.c
+++ b/target/arm/tcg/mte_helper.c
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
     int gm_bs = env_archcpu(env)->gm_blocksize;
     int gm_bs_bytes = 4 << gm_bs;
     void *tag_mem;
+    uint64_t ret;
+    int shift;
 
     ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
 
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
 
     /*
      * The ordering of elements within the word corresponds to
-     * a little-endian operation.
+     * a little-endian operation.  Computation of shift comes from
+     *
+     *     index = address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE>
+     *     data<index*4+3:index*4> = tag
+     *
+     * Because of the alignment of ptr above, BS=6 has shift=0.
+     * All memory operations are aligned.  Defer support for BS=2,
+     * requiring insertion or extraction of a nibble, until we
+     * support a cpu that requires it.
      */
     switch (gm_bs) {
+    case 3:
+        /* 32 bytes -> 2 tags -> 8 result bits */
+        ret = *(uint8_t *)tag_mem;
+        break;
+    case 4:
+        /* 64 bytes -> 4 tags -> 16 result bits */
+        ret = cpu_to_le16(*(uint16_t *)tag_mem);
+        break;
+    case 5:
+        /* 128 bytes -> 8 tags -> 32 result bits */
+        ret = cpu_to_le32(*(uint32_t *)tag_mem);
+        break;
     case 6:
         /* 256 bytes -> 16 tags -> 64 result bits */
-        return ldq_le_p(tag_mem);
+        return cpu_to_le64(*(uint64_t *)tag_mem);
     default:
-        /* cpu configured with unsupported gm blocksize. */
+        /*
+         * CPU configured with unsupported/invalid gm blocksize.
+         * This is detected early in arm_cpu_realizefn.
+         */
         g_assert_not_reached();
     }
+    shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
+    return ret << shift;
 }
 
 void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
     int gm_bs = env_archcpu(env)->gm_blocksize;
     int gm_bs_bytes = 4 << gm_bs;
     void *tag_mem;
+    int shift;
 
     ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
 
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
         return;
     }
 
-    /*
-     * The ordering of elements within the word corresponds to
-     * a little-endian operation.
-     */
+    /* See LDGM for comments on BS and on shift.  */
+    shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
+    val >>= shift;
     switch (gm_bs) {
+    case 3:
+        /* 32 bytes -> 2 tags -> 8 result bits */
+        *(uint8_t *)tag_mem = val;
+        break;
+    case 4:
+        /* 64 bytes -> 4 tags -> 16 result bits */
+        *(uint16_t *)tag_mem = cpu_to_le16(val);
+        break;
+    case 5:
+        /* 128 bytes -> 8 tags -> 32 result bits */
+        *(uint32_t *)tag_mem = cpu_to_le32(val);
+        break;
     case 6:
-        stq_le_p(tag_mem, val);
+        /* 256 bytes -> 16 tags -> 64 result bits */
+        *(uint64_t *)tag_mem = cpu_to_le64(val);
         break;
     default:
         /* cpu configured with unsupported gm blocksize. */
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

When the cpu support MTE, but the system does not, reduce cpu
support to user instructions at EL0 instead of completely
disabling MTE.  If we encounter a cpu implementation which does
something else, we can revisit this setting.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 
 #ifndef CONFIG_USER_ONLY
         /*
-         * Disable the MTE feature bits if we do not have tag-memory
-         * provided by the machine.
+         * If we do not have tag-memory provided by the machine,
+         * reduce MTE support to instructions enabled at EL0.
+         * This matches Cortex-A710 BROADCASTMTE input being LOW.
          */
         if (cpu->tag_memory == NULL) {
             cpu->isar.id_aa64pfr1 =
-                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
+                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
         }
 #endif
     }
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Do not hard-code the constants for Neoverse V1.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/tcg/cpu64.c | 48 ++++++++++++++++++++++++++++--------------
 1 file changed, 32 insertions(+), 16 deletions(-)

diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/module.h"
 #include "qapi/visitor.h"
 #include "hw/qdev-properties.h"
+#include "qemu/units.h"
 #include "internals.h"
 #include "cpregs.h"
 
+static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize,
+                              unsigned cachesize)
+{
+    unsigned lg_linesize = ctz32(linesize);
+    unsigned sets;
+
+    /*
+     * The 64-bit CCSIDR_EL1 format is:
+     *   [55:32] number of sets - 1
+     *   [23:3]  associativity - 1
+     *   [2:0]   log2(linesize) - 4
+     *           so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
+     */
+    assert(assoc != 0);
+    assert(is_power_of_2(linesize));
+    assert(lg_linesize >= 4 && lg_linesize <= 7 + 4);
+
+    /* sets * associativity * linesize == cachesize. */
+    sets = cachesize / (assoc * linesize);
+    assert(cachesize % (assoc * linesize) == 0);
+
+    return ((uint64_t)(sets - 1) << 32)
+         | ((assoc - 1) << 3)
+         | (lg_linesize - 4);
+}
+
 static void aarch64_a35_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj)
      * The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values,
      * but also says it implements CCIDX, which means they should be
      * 64-bit format. So we here use values which are based on the textual
-     * information in chapter 2 of the TRM (and on the fact that
-     * sets * associativity * linesize == cachesize).
-     *
-     * The 64-bit CCSIDR_EL1 format is:
-     *   [55:32] number of sets - 1
-     *   [23:3]  associativity - 1
-     *   [2:0]   log2(linesize) - 4
-     *           so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
-     *
-     * L1: 4-way set associative 64-byte line size, total size 64K,
-     * so sets is 256.
+     * information in chapter 2 of the TRM:
      *
+     * L1: 4-way set associative 64-byte line size, total size 64K.
      * L2: 8-way set associative, 64 byte line size, either 512K or 1MB.
-     * We pick 1MB, so this has 2048 sets.
-     *
      * L3: No L3 (this matches the CLIDR_EL1 value).
      */
-    cpu->ccsidr[0] = 0x000000ff0000001aull; /* 64KB L1 dcache */
-    cpu->ccsidr[1] = 0x000000ff0000001aull; /* 64KB L1 icache */
-    cpu->ccsidr[2] = 0x000007ff0000003aull; /* 1MB L2 cache */
+    cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */
+    cpu->ccsidr[1] = cpu->ccsidr[0];                 /* L1 icache */
+    cpu->ccsidr[2] = make_ccsidr64(8, 64, 1 * MiB);  /* L2 cache */
 
     /* From 3.2.115 SCTLR_EL3 */
     cpu->reset_sctlr = 0x30c50838;
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Access to many of the special registers is enabled or disabled
by ACTLR_EL[23], which we implement as constant 0, which means
that all writes outside EL3 should trap.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h    |  2 ++
 target/arm/helper.c    |  4 ++--
 target/arm/tcg/cpu64.c | 46 +++++++++++++++++++++++++++++++++---------
 3 files changed, 41 insertions(+), 11 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
 void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
 #endif
 
+CPAccessResult access_tvm_trvm(CPUARMState *, const ARMCPRegInfo *, bool);
+
 #endif /* TARGET_ARM_CPREGS_H */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
 }
 
 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM.  */
-static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
-                                      bool isread)
+CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
+                               bool isread)
 {
     if (arm_current_el(env) == 1) {
         uint64_t trap = isread ? HCR_TRVM : HCR_TVM;
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj)
     /* TODO:  Add A64FX specific HPC extension registers */
 }
 
+static CPAccessResult access_actlr_w(CPUARMState *env, const ARMCPRegInfo *r,
+                                     bool read)
+{
+    if (!read) {
+        int el = arm_current_el(env);
+
+        /* Because ACTLR_EL2 is constant 0, writes below EL2 trap to EL2. */
+        if (el < 2 && arm_is_el2_enabled(env)) {
+            return CP_ACCESS_TRAP_EL2;
+        }
+        /* Because ACTLR_EL3 is constant 0, writes below EL3 trap to EL3. */
+        if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) {
+            return CP_ACCESS_TRAP_EL3;
+        }
+    }
+    return CP_ACCESS_OK;
+}
+
 static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
     { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      /* Traps and enables are the same as for TCR_EL1. */
+      .accessfn = access_tvm_trvm, .fgt = FGT_TCR_EL1, },
     { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     /*
      * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
      * (and in particular its system registers).
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
     { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010,
+      .accessfn = access_actlr_w },
     { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1,
       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
 };
 
 static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

There is only one additional EL1 register modeled, which
also needs to use access_actlr_w.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/tcg/cpu64.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
 static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = {
     { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0,
       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Like FEAT_TRF (Self-hosted Trace Extension), suppress tracing
external to the cpu, which is out of scope for QEMU.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         /* FEAT_SPE (Statistical Profiling Extension) */
         cpu->isar.id_aa64dfr0 =
             FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
+        /* FEAT_TRBE (Trace Buffer Extension) */
+        cpu->isar.id_aa64dfr0 =
+            FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0);
         /* FEAT_TRF (Self-hosted Trace Extension) */
         cpu->isar.id_aa64dfr0 =
             FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0);
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

This feature allows the operating system to set TCR_ELx.HWU*
to allow the implementation to use the PBHA bits from the
block and page descriptors for for IMPLEMENTATION DEFINED
purposes.  Since QEMU has no need to use these bits, we may
simply ignore them.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/tcg/cpu32.c        | 2 +-
 target/arm/tcg/cpu64.c        | 2 +-
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_HAFDBS (Hardware management of the access flag and dirty bit state)
 - FEAT_HCX (Support for the HCRX_EL2 register)
 - FEAT_HPDS (Hierarchical permission disables)
+- FEAT_HPDS2 (Translation table page-based hardware attributes)
 - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
 - FEAT_IDST (ID space trap handling)
 - FEAT_IESB (Implicit error synchronization event)
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
     cpu->isar.id_mmfr3 = t;
 
     t = cpu->isar.id_mmfr4;
-    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1);         /* FEAT_AA32HPD */
+    t = FIELD_DP32(t, ID_MMFR4, HPDS, 2);         /* FEAT_HPDS2 */
     t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
     t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
     t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX */
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2);   /* FEAT_HAFDBS */
     t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
     t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);       /* FEAT_VHE */
-    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1);     /* FEAT_HPDS */
+    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2);     /* FEAT_HPDS2 */
     t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
     t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3);      /* FEAT_PAN3 */
     t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
-- 
2.34.1

From: Alex Bennée <alex.bennee@linaro.org>

This is a mandatory feature for Armv8.1 architectures but we don't
state the feature clearly in our emulation list. Also include
FEAT_CRC32 comment in aarch64_max_tcg_initfn for ease of grepping.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20230824075406.1515566-1-alex.bennee@linaro.org
Cc: qemu-stable@nongnu.org
Message-Id: <20230222110104.3996971-1-alex.bennee@linaro.org>
[PMM: pluralize 'instructions' in docs]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/tcg/cpu64.c        | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

From: Jean-Christophe Dubois <jcd@tribudubois.net>

i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device.
In particular, register 22 is not present on i.MX6UL and this is actualy
The only register that is really emulated in the i.MX7 IOMUX GPR device.

Note: The i.MX6UL code is actually also implementing the IOMUX GPR device
as an unimplemented device at the same bus adress and the 2 instantiations
were actualy colliding. So we go back to the unimplemented device for now.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: 48681bf51ee97646479bb261bee19abebbc8074e.1692964892.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6ul.h |  2 --
 hw/arm/fsl-imx6ul.c         | 11 -----------
 2 files changed, 13 deletions(-)

diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/imx6ul_ccm.h"
 #include "hw/misc/imx6_src.h"
 #include "hw/misc/imx7_snvs.h"
-#include "hw/misc/imx7_gpr.h"
 #include "hw/intc/imx_gpcv2.h"
 #include "hw/watchdog/wdt_imx2.h"
 #include "hw/gpio/imx_gpio.h"
@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
     IMX6SRCState       src;
     IMX7SNVSState      snvs;
     IMXGPCv2State      gpcv2;
-    IMX7GPRState       gpr;
     IMXSPIState        spi[FSL_IMX6UL_NUM_ECSPIS];
     IMXI2CState        i2c[FSL_IMX6UL_NUM_I2CS];
     IMXSerialState     uart[FSL_IMX6UL_NUM_UARTS];
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
      */
     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
 
-    /*
-     * GPR
-     */
-    object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
-
     /*
      * GPIOs 1 to 5
      */
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
                                             FSL_IMX6UL_WDOGn_IRQ[i]));
     }
 
-    /*
-     * GPR
-     */
-    sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR);
-
     /*
      * SDMA
      */
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

* Add Addr and size definition for most i.MX6UL devices in i.MX6UL header file.
* Use those newly defined named constants whenever possible.
* Standardize the way we init a familly of unimplemented devices
  - SAI
  - PWM
  - CAN
* Add/rework few comments

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: d579043fbd4e4b490370783fda43fc02c8e9be75.1692964892.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6ul.h | 156 +++++++++++++++++++++++++++++++-----
 hw/arm/fsl-imx6ul.c         | 147 ++++++++++++++++++++++-----------
 2 files changed, 232 insertions(+), 71 deletions(-)

diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@
 #include "exec/memory.h"
 #include "cpu.h"
 #include "qom/object.h"
+#include "qemu/units.h"
 
 #define TYPE_FSL_IMX6UL "fsl-imx6ul"
 OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6ULState, FSL_IMX6UL)
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
     FSL_IMX6UL_NUM_ADCS         = 2,
     FSL_IMX6UL_NUM_USB_PHYS     = 2,
     FSL_IMX6UL_NUM_USBS         = 2,
+    FSL_IMX6UL_NUM_SAIS         = 3,
+    FSL_IMX6UL_NUM_CANS         = 2,
+    FSL_IMX6UL_NUM_PWMS         = 4,
 };
 
 struct FslIMX6ULState {
@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
 
 enum FslIMX6ULMemoryMap {
     FSL_IMX6UL_MMDC_ADDR            = 0x80000000,
-    FSL_IMX6UL_MMDC_SIZE            = 2 * 1024 * 1024 * 1024UL,
+    FSL_IMX6UL_MMDC_SIZE            = (2 * GiB),
 
     FSL_IMX6UL_QSPI1_MEM_ADDR       = 0x60000000,
-    FSL_IMX6UL_EIM_ALIAS_ADDR       = 0x58000000,
-    FSL_IMX6UL_EIM_CS_ADDR          = 0x50000000,
-    FSL_IMX6UL_AES_ENCRYPT_ADDR     = 0x10000000,
-    FSL_IMX6UL_QSPI1_RX_ADDR        = 0x0C000000,
+    FSL_IMX6UL_QSPI1_MEM_SIZE       = (256 * MiB),
 
-    /* AIPS-2 */
+    FSL_IMX6UL_EIM_ALIAS_ADDR       = 0x58000000,
+    FSL_IMX6UL_EIM_ALIAS_SIZE       = (128 * MiB),
+
+    FSL_IMX6UL_EIM_CS_ADDR          = 0x50000000,
+    FSL_IMX6UL_EIM_CS_SIZE          = (128 * MiB),
+
+    FSL_IMX6UL_AES_ENCRYPT_ADDR     = 0x10000000,
+    FSL_IMX6UL_AES_ENCRYPT_SIZE     = (1 * MiB),
+
+    FSL_IMX6UL_QSPI1_RX_ADDR        = 0x0C000000,
+    FSL_IMX6UL_QSPI1_RX_SIZE        = (32 * MiB),
+
+    /* AIPS-2 Begin */
     FSL_IMX6UL_UART6_ADDR           = 0x021FC000,
+
     FSL_IMX6UL_I2C4_ADDR            = 0x021F8000,
+
     FSL_IMX6UL_UART5_ADDR           = 0x021F4000,
     FSL_IMX6UL_UART4_ADDR           = 0x021F0000,
     FSL_IMX6UL_UART3_ADDR           = 0x021EC000,
     FSL_IMX6UL_UART2_ADDR           = 0x021E8000,
+
     FSL_IMX6UL_WDOG3_ADDR           = 0x021E4000,
+
     FSL_IMX6UL_QSPI_ADDR            = 0x021E0000,
+    FSL_IMX6UL_QSPI_SIZE            = 0x500,
+
     FSL_IMX6UL_SYS_CNT_CTRL_ADDR    = 0x021DC000,
+    FSL_IMX6UL_SYS_CNT_CTRL_SIZE    = (16 * KiB),
+
     FSL_IMX6UL_SYS_CNT_CMP_ADDR     = 0x021D8000,
+    FSL_IMX6UL_SYS_CNT_CMP_SIZE     = (16 * KiB),
+
     FSL_IMX6UL_SYS_CNT_RD_ADDR      = 0x021D4000,
+    FSL_IMX6UL_SYS_CNT_RD_SIZE      = (16 * KiB),
+
     FSL_IMX6UL_TZASC_ADDR           = 0x021D0000,
+    FSL_IMX6UL_TZASC_SIZE           = (16 * KiB),
+
     FSL_IMX6UL_PXP_ADDR             = 0x021CC000,
+    FSL_IMX6UL_PXP_SIZE             = (16 * KiB),
+
     FSL_IMX6UL_LCDIF_ADDR           = 0x021C8000,
+    FSL_IMX6UL_LCDIF_SIZE           = 0x100,
+
     FSL_IMX6UL_CSI_ADDR             = 0x021C4000,
+    FSL_IMX6UL_CSI_SIZE             = 0x100,
+
     FSL_IMX6UL_CSU_ADDR             = 0x021C0000,
+    FSL_IMX6UL_CSU_SIZE             = (16 * KiB),
+
     FSL_IMX6UL_OCOTP_CTRL_ADDR      = 0x021BC000,
+    FSL_IMX6UL_OCOTP_CTRL_SIZE      = (4 * KiB),
+
     FSL_IMX6UL_EIM_ADDR             = 0x021B8000,
+    FSL_IMX6UL_EIM_SIZE             = 0x100,
+
     FSL_IMX6UL_SIM2_ADDR            = 0x021B4000,
+
     FSL_IMX6UL_MMDC_CFG_ADDR        = 0x021B0000,
+    FSL_IMX6UL_MMDC_CFG_SIZE        = (4 * KiB),
+
     FSL_IMX6UL_ROMCP_ADDR           = 0x021AC000,
+    FSL_IMX6UL_ROMCP_SIZE           = 0x300,
+
     FSL_IMX6UL_I2C3_ADDR            = 0x021A8000,
     FSL_IMX6UL_I2C2_ADDR            = 0x021A4000,
     FSL_IMX6UL_I2C1_ADDR            = 0x021A0000,
+
     FSL_IMX6UL_ADC2_ADDR            = 0x0219C000,
     FSL_IMX6UL_ADC1_ADDR            = 0x02198000,
+    FSL_IMX6UL_ADCn_SIZE            = 0x100,
+
     FSL_IMX6UL_USDHC2_ADDR          = 0x02194000,
     FSL_IMX6UL_USDHC1_ADDR          = 0x02190000,
-    FSL_IMX6UL_SIM1_ADDR            = 0x0218C000,
-    FSL_IMX6UL_ENET1_ADDR           = 0x02188000,
-    FSL_IMX6UL_USBO2_USBMISC_ADDR   = 0x02184800,
-    FSL_IMX6UL_USBO2_USB_ADDR       = 0x02184000,
-    FSL_IMX6UL_USBO2_PL301_ADDR     = 0x02180000,
-    FSL_IMX6UL_AIPS2_CFG_ADDR       = 0x0217C000,
-    FSL_IMX6UL_CAAM_ADDR            = 0x02140000,
-    FSL_IMX6UL_A7MPCORE_DAP_ADDR    = 0x02100000,
 
-    /* AIPS-1 */
+    FSL_IMX6UL_SIM1_ADDR            = 0x0218C000,
+    FSL_IMX6UL_SIMn_SIZE            = (16 * KiB),
+
+    FSL_IMX6UL_ENET1_ADDR           = 0x02188000,
+
+    FSL_IMX6UL_USBO2_USBMISC_ADDR   = 0x02184800,
+    FSL_IMX6UL_USBO2_USB1_ADDR      = 0x02184000,
+    FSL_IMX6UL_USBO2_USB2_ADDR      = 0x02184200,
+
+    FSL_IMX6UL_USBO2_PL301_ADDR     = 0x02180000,
+    FSL_IMX6UL_USBO2_PL301_SIZE     = (16 * KiB),
+
+    FSL_IMX6UL_AIPS2_CFG_ADDR       = 0x0217C000,
+    FSL_IMX6UL_AIPS2_CFG_SIZE       = 0x100,
+
+    FSL_IMX6UL_CAAM_ADDR            = 0x02140000,
+    FSL_IMX6UL_CAAM_SIZE            = (16 * KiB),
+
+    FSL_IMX6UL_A7MPCORE_DAP_ADDR    = 0x02100000,
+    FSL_IMX6UL_A7MPCORE_DAP_SIZE    = (4 * KiB),
+    /* AIPS-2 End */
+
+    /* AIPS-1 Begin */
     FSL_IMX6UL_PWM8_ADDR            = 0x020FC000,
     FSL_IMX6UL_PWM7_ADDR            = 0x020F8000,
     FSL_IMX6UL_PWM6_ADDR            = 0x020F4000,
     FSL_IMX6UL_PWM5_ADDR            = 0x020F0000,
+
     FSL_IMX6UL_SDMA_ADDR            = 0x020EC000,
+    FSL_IMX6UL_SDMA_SIZE            = 0x300,
+
     FSL_IMX6UL_GPT2_ADDR            = 0x020E8000,
+
     FSL_IMX6UL_IOMUXC_GPR_ADDR      = 0x020E4000,
+    FSL_IMX6UL_IOMUXC_GPR_SIZE      = 0x40,
+
     FSL_IMX6UL_IOMUXC_ADDR          = 0x020E0000,
+    FSL_IMX6UL_IOMUXC_SIZE          = 0x700,
+
     FSL_IMX6UL_GPC_ADDR             = 0x020DC000,
+
     FSL_IMX6UL_SRC_ADDR             = 0x020D8000,
+
     FSL_IMX6UL_EPIT2_ADDR           = 0x020D4000,
     FSL_IMX6UL_EPIT1_ADDR           = 0x020D0000,
+
     FSL_IMX6UL_SNVS_HP_ADDR         = 0x020CC000,
+
     FSL_IMX6UL_USBPHY2_ADDR         = 0x020CA000,
-    FSL_IMX6UL_USBPHY2_SIZE         = (4 * 1024),
     FSL_IMX6UL_USBPHY1_ADDR         = 0x020C9000,
-    FSL_IMX6UL_USBPHY1_SIZE         = (4 * 1024),
+
     FSL_IMX6UL_ANALOG_ADDR          = 0x020C8000,
+    FSL_IMX6UL_ANALOG_SIZE          = 0x300,
+
     FSL_IMX6UL_CCM_ADDR             = 0x020C4000,
+
     FSL_IMX6UL_WDOG2_ADDR           = 0x020C0000,
     FSL_IMX6UL_WDOG1_ADDR           = 0x020BC000,
+
     FSL_IMX6UL_KPP_ADDR             = 0x020B8000,
+    FSL_IMX6UL_KPP_SIZE             = 0x10,
+
     FSL_IMX6UL_ENET2_ADDR           = 0x020B4000,
+
     FSL_IMX6UL_SNVS_LP_ADDR         = 0x020B0000,
+    FSL_IMX6UL_SNVS_LP_SIZE         = (16 * KiB),
+
     FSL_IMX6UL_GPIO5_ADDR           = 0x020AC000,
     FSL_IMX6UL_GPIO4_ADDR           = 0x020A8000,
     FSL_IMX6UL_GPIO3_ADDR           = 0x020A4000,
     FSL_IMX6UL_GPIO2_ADDR           = 0x020A0000,
     FSL_IMX6UL_GPIO1_ADDR           = 0x0209C000,
+
     FSL_IMX6UL_GPT1_ADDR            = 0x02098000,
+
     FSL_IMX6UL_CAN2_ADDR            = 0x02094000,
     FSL_IMX6UL_CAN1_ADDR            = 0x02090000,
+    FSL_IMX6UL_CANn_SIZE            = (4 * KiB),
+
     FSL_IMX6UL_PWM4_ADDR            = 0x0208C000,
     FSL_IMX6UL_PWM3_ADDR            = 0x02088000,
     FSL_IMX6UL_PWM2_ADDR            = 0x02084000,
     FSL_IMX6UL_PWM1_ADDR            = 0x02080000,
+    FSL_IMX6UL_PWMn_SIZE            = 0x20,
+
     FSL_IMX6UL_AIPS1_CFG_ADDR       = 0x0207C000,
+    FSL_IMX6UL_AIPS1_CFG_SIZE       = (16 * KiB),
+
     FSL_IMX6UL_BEE_ADDR             = 0x02044000,
+    FSL_IMX6UL_BEE_SIZE             = (16 * KiB),
+
     FSL_IMX6UL_TOUCH_CTRL_ADDR      = 0x02040000,
+    FSL_IMX6UL_TOUCH_CTRL_SIZE      = 0x100,
+
     FSL_IMX6UL_SPBA_ADDR            = 0x0203C000,
+    FSL_IMX6UL_SPBA_SIZE            = 0x100,
+
     FSL_IMX6UL_ASRC_ADDR            = 0x02034000,
+    FSL_IMX6UL_ASRC_SIZE            = 0x100,
+
     FSL_IMX6UL_SAI3_ADDR            = 0x02030000,
     FSL_IMX6UL_SAI2_ADDR            = 0x0202C000,
     FSL_IMX6UL_SAI1_ADDR            = 0x02028000,
+    FSL_IMX6UL_SAIn_SIZE            = 0x200,
+
     FSL_IMX6UL_UART8_ADDR           = 0x02024000,
     FSL_IMX6UL_UART1_ADDR           = 0x02020000,
     FSL_IMX6UL_UART7_ADDR           = 0x02018000,
+
     FSL_IMX6UL_ECSPI4_ADDR          = 0x02014000,
     FSL_IMX6UL_ECSPI3_ADDR          = 0x02010000,
     FSL_IMX6UL_ECSPI2_ADDR          = 0x0200C000,
     FSL_IMX6UL_ECSPI1_ADDR          = 0x02008000,
+
     FSL_IMX6UL_SPDIF_ADDR           = 0x02004000,
+    FSL_IMX6UL_SPDIF_SIZE           = 0x100,
+    /* AIPS-1 End */
+
+    FSL_IMX6UL_BCH_ADDR             = 0x01808000,
+    FSL_IMX6UL_BCH_SIZE             = 0x200,
+
+    FSL_IMX6UL_GPMI_ADDR            = 0x01806000,
+    FSL_IMX6UL_GPMI_SIZE            = 0x200,
 
     FSL_IMX6UL_APBH_DMA_ADDR        = 0x01804000,
-    FSL_IMX6UL_APBH_DMA_SIZE        = (32 * 1024),
+    FSL_IMX6UL_APBH_DMA_SIZE        = (4 * KiB),
 
     FSL_IMX6UL_A7MPCORE_ADDR        = 0x00A00000,
 
     FSL_IMX6UL_OCRAM_ALIAS_ADDR     = 0x00920000,
-    FSL_IMX6UL_OCRAM_ALIAS_SIZE     = 0x00060000,
+    FSL_IMX6UL_OCRAM_ALIAS_SIZE     = (384 * KiB),
+
     FSL_IMX6UL_OCRAM_MEM_ADDR       = 0x00900000,
-    FSL_IMX6UL_OCRAM_MEM_SIZE       = 0x00020000,
+    FSL_IMX6UL_OCRAM_MEM_SIZE       = (128 * KiB),
+
     FSL_IMX6UL_CAAM_MEM_ADDR        = 0x00100000,
-    FSL_IMX6UL_CAAM_MEM_SIZE        = 0x00008000,
+    FSL_IMX6UL_CAAM_MEM_SIZE        = (32 * KiB),
+
     FSL_IMX6UL_ROM_ADDR             = 0x00000000,
-    FSL_IMX6UL_ROM_SIZE             = 0x00018000,
+    FSL_IMX6UL_ROM_SIZE             = (96 * KiB),
 };
 
 enum FslIMX6ULIRQs {
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
 
     /*
-     * GPIOs 1 to 5
+     * GPIOs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
         snprintf(name, NAME_SIZE, "gpio%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * GPT 1, 2
+     * GPTs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
         snprintf(name, NAME_SIZE, "gpt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * EPIT 1, 2
+     * EPITs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
         snprintf(name, NAME_SIZE, "epit%d", i + 1);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * eCSPI
+     * eCSPIs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
         snprintf(name, NAME_SIZE, "spi%d", i + 1);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * I2C
+     * I2Cs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
         snprintf(name, NAME_SIZE, "i2c%d", i + 1);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * UART
+     * UARTs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
         snprintf(name, NAME_SIZE, "uart%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * Ethernet
+     * Ethernets
      */
     for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
         snprintf(name, NAME_SIZE, "eth%d", i);
         object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
     }
 
-    /* USB */
+    /*
+     * USB PHYs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
         snprintf(name, NAME_SIZE, "usbphy%d", i);
         object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
     }
+
+    /*
+     * USBs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
         snprintf(name, NAME_SIZE, "usb%d", i);
         object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
     }
 
     /*
-     * SDHCI
+     * SDHCIs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
         snprintf(name, NAME_SIZE, "usdhc%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * Watchdog
+     * Watchdogs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
         snprintf(name, NAME_SIZE, "wdt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
      * A7MPCORE DAP
      */
     create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR,
-                                0x100000);
+                                FSL_IMX6UL_A7MPCORE_DAP_SIZE);
 
     /*
-     * GPT 1, 2
+     * GPTs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
         static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * EPIT 1, 2
+     * EPITs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
         static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * GPIO
+     * GPIOs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
         static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * IOMUXC and IOMUXC_GPR
+     * IOMUXC
      */
-    for (i = 0; i < 1; i++) {
-        static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = {
-            FSL_IMX6UL_IOMUXC_ADDR,
-            FSL_IMX6UL_IOMUXC_GPR_ADDR,
-        };
-
-        snprintf(name, NAME_SIZE, "iomuxc%d", i);
-        create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000);
-    }
+    create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR,
+                                FSL_IMX6UL_IOMUXC_SIZE);
+    create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR,
+                                FSL_IMX6UL_IOMUXC_GPR_SIZE);
 
     /*
      * CCM
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
 
-    /* Initialize all ECSPI */
+    /*
+     * ECSPIs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
         static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = {
             FSL_IMX6UL_ECSPI1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * I2C
+     * I2Cs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
         static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * UART
+     * UARTs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
         static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * Ethernet
+     * Ethernets
      *
      * We must use two loops since phy_connected affects the other interface
      * and we have to set all properties before calling sysbus_realize().
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
                                             FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
     }
 
-    /* USB */
+    /*
+     * USB PHYs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
+        static const hwaddr
+                     FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] = {
+            FSL_IMX6UL_USBPHY1_ADDR,
+            FSL_IMX6UL_USBPHY2_ADDR,
+        };
+
         sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
-                        FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000);
+                        FSL_IMX6UL_USB_PHYn_ADDR[i]);
     }
 
+    /*
+     * USBs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
+        static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS] = {
+            FSL_IMX6UL_USBO2_USB1_ADDR,
+            FSL_IMX6UL_USBO2_USB2_ADDR,
+        };
+
         static const int FSL_IMX6UL_USBn_IRQ[] = {
             FSL_IMX6UL_USB1_IRQ,
             FSL_IMX6UL_USB2_IRQ,
         };
+
         sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
-                        FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200);
+                        FSL_IMX6UL_USB02_USBn_ADDR[i]);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
                                             FSL_IMX6UL_USBn_IRQ[i]));
     }
 
     /*
-     * USDHC
+     * USDHCs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
         static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
 
     /*
-     * Watchdog
+     * Watchdogs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
         static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
             FSL_IMX6UL_WDOG2_ADDR,
             FSL_IMX6UL_WDOG3_ADDR,
         };
+
         static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = {
             FSL_IMX6UL_WDOG1_IRQ,
             FSL_IMX6UL_WDOG2_IRQ,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     /*
      * SDMA
      */
-    create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
+    create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR,
+                                FSL_IMX6UL_SDMA_SIZE);
 
     /*
-     * SAI (Audio SSI (Synchronous Serial Interface))
+     * SAIs (Audio SSI (Synchronous Serial Interface))
      */
-    create_unimplemented_device("sai1", FSL_IMX6UL_SAI1_ADDR, 0x4000);
-    create_unimplemented_device("sai2", FSL_IMX6UL_SAI2_ADDR, 0x4000);
-    create_unimplemented_device("sai3", FSL_IMX6UL_SAI3_ADDR, 0x4000);
+    for (i = 0; i < FSL_IMX6UL_NUM_SAIS; i++) {
+        static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] = {
+            FSL_IMX6UL_SAI1_ADDR,
+            FSL_IMX6UL_SAI2_ADDR,
+            FSL_IMX6UL_SAI3_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "sai%d", i);
+        create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i],
+                                    FSL_IMX6UL_SAIn_SIZE);
+    }
 
     /*
-     * PWM
+     * PWMs
      */
-    create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000);
-    create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000);
-    create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000);
-    create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000);
+    for (i = 0; i < FSL_IMX6UL_NUM_PWMS; i++) {
+        static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] = {
+            FSL_IMX6UL_PWM1_ADDR,
+            FSL_IMX6UL_PWM2_ADDR,
+            FSL_IMX6UL_PWM3_ADDR,
+            FSL_IMX6UL_PWM4_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "pwm%d", i);
+        create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i],
+                                    FSL_IMX6UL_PWMn_SIZE);
+    }
 
     /*
      * Audio ASRC (asynchronous sample rate converter)
      */
-    create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, 0x4000);
+    create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR,
+                                FSL_IMX6UL_ASRC_SIZE);
 
     /*
-     * CAN
+     * CANs
      */
-    create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000);
-    create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000);
+    for (i = 0; i < FSL_IMX6UL_NUM_CANS; i++) {
+        static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] = {
+            FSL_IMX6UL_CAN1_ADDR,
+            FSL_IMX6UL_CAN2_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "can%d", i);
+        create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i],
+                                    FSL_IMX6UL_CANn_SIZE);
+    }
 
     /*
      * APHB_DMA
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
         };
 
         snprintf(name, NAME_SIZE, "adc%d", i);
-        create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000);
+        create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i],
+                                    FSL_IMX6UL_ADCn_SIZE);
     }
 
     /*
      * LCD
      */
-    create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000);
+    create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
+                                FSL_IMX6UL_LCDIF_SIZE);
 
     /*
      * ROM memory
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

* Add TZASC as unimplemented device.
  - Allow bare metal application to access this (unimplemented) device
* Add CSU as unimplemented device.
  - Allow bare metal application to access this (unimplemented) device
* Add 4 missing PWM devices

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 59e4dc56e14eccfefd379275ec19048dff9c10b3.1692964892.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6ul.h |  2 +-
 hw/arm/fsl-imx6ul.c         | 16 ++++++++++++++++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
     FSL_IMX6UL_NUM_USBS         = 2,
     FSL_IMX6UL_NUM_SAIS         = 3,
     FSL_IMX6UL_NUM_CANS         = 2,
-    FSL_IMX6UL_NUM_PWMS         = 4,
+    FSL_IMX6UL_NUM_PWMS         = 8,
 };
 
 struct FslIMX6ULState {
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
             FSL_IMX6UL_PWM2_ADDR,
             FSL_IMX6UL_PWM3_ADDR,
             FSL_IMX6UL_PWM4_ADDR,
+            FSL_IMX6UL_PWM5_ADDR,
+            FSL_IMX6UL_PWM6_ADDR,
+            FSL_IMX6UL_PWM7_ADDR,
+            FSL_IMX6UL_PWM8_ADDR,
         };
 
         snprintf(name, NAME_SIZE, "pwm%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
                                 FSL_IMX6UL_LCDIF_SIZE);
 
+    /*
+     * CSU
+     */
+    create_unimplemented_device("csu", FSL_IMX6UL_CSU_ADDR,
+                                FSL_IMX6UL_CSU_SIZE);
+
+    /*
+     * TZASC
+     */
+    create_unimplemented_device("tzasc", FSL_IMX6UL_TZASC_ADDR,
+                                FSL_IMX6UL_TZASC_SIZE);
+
     /*
      * ROM memory
      */
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

* Add Addr and size definition for all i.MX7 devices in i.MX7 header file.
* Use those newly defined named constants whenever possible.
* Standardize the way we init a familly of unimplemented devices
  - SAI
  - PWM
  - CAN
* Add/rework few comments

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: 59e195d33e4d486a8d131392acd46633c8c10ed7.1692964892.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx7.h | 330 ++++++++++++++++++++++++++++----------
 hw/arm/fsl-imx7.c         | 130 ++++++++++-----
 2 files changed, 335 insertions(+), 125 deletions(-)

diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/imx7_ccm.h"
 #include "hw/misc/imx7_snvs.h"
 #include "hw/misc/imx7_gpr.h"
-#include "hw/misc/imx6_src.h"
 #include "hw/watchdog/wdt_imx2.h"
 #include "hw/gpio/imx_gpio.h"
 #include "hw/char/imx_serial.h"
@@ -XXX,XX +XXX,XX @@
 #include "hw/usb/chipidea.h"
 #include "cpu.h"
 #include "qom/object.h"
+#include "qemu/units.h"
 
 #define TYPE_FSL_IMX7 "fsl-imx7"
 OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7)
@@ -XXX,XX +XXX,XX @@ enum FslIMX7Configuration {
     FSL_IMX7_NUM_ECSPIS       = 4,
     FSL_IMX7_NUM_USBS         = 3,
     FSL_IMX7_NUM_ADCS         = 2,
+    FSL_IMX7_NUM_SAIS         = 3,
+    FSL_IMX7_NUM_CANS         = 2,
+    FSL_IMX7_NUM_PWMS         = 4,
 };
 
 struct FslIMX7State {
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
 
 enum FslIMX7MemoryMap {
     FSL_IMX7_MMDC_ADDR            = 0x80000000,
-    FSL_IMX7_MMDC_SIZE            = 2 * 1024 * 1024 * 1024UL,
+    FSL_IMX7_MMDC_SIZE            = (2 * GiB),
 
-    FSL_IMX7_GPIO1_ADDR           = 0x30200000,
-    FSL_IMX7_GPIO2_ADDR           = 0x30210000,
-    FSL_IMX7_GPIO3_ADDR           = 0x30220000,
-    FSL_IMX7_GPIO4_ADDR           = 0x30230000,
-    FSL_IMX7_GPIO5_ADDR           = 0x30240000,
-    FSL_IMX7_GPIO6_ADDR           = 0x30250000,
-    FSL_IMX7_GPIO7_ADDR           = 0x30260000,
+    FSL_IMX7_QSPI1_MEM_ADDR       = 0x60000000,
+    FSL_IMX7_QSPI1_MEM_SIZE       = (256 * MiB),
 
-    FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
+    FSL_IMX7_PCIE1_MEM_ADDR       = 0x40000000,
+    FSL_IMX7_PCIE1_MEM_SIZE       = (256 * MiB),
 
-    FSL_IMX7_WDOG1_ADDR           = 0x30280000,
-    FSL_IMX7_WDOG2_ADDR           = 0x30290000,
-    FSL_IMX7_WDOG3_ADDR           = 0x302A0000,
-    FSL_IMX7_WDOG4_ADDR           = 0x302B0000,
+    FSL_IMX7_QSPI1_RX_BUF_ADDR    = 0x34000000,
+    FSL_IMX7_QSPI1_RX_BUF_SIZE    = (32 * MiB),
 
-    FSL_IMX7_IOMUXC_LPSR_ADDR     = 0x302C0000,
+    /* PCIe Peripherals */
+    FSL_IMX7_PCIE_REG_ADDR        = 0x33800000,
 
-    FSL_IMX7_GPT1_ADDR            = 0x302D0000,
-    FSL_IMX7_GPT2_ADDR            = 0x302E0000,
-    FSL_IMX7_GPT3_ADDR            = 0x302F0000,
-    FSL_IMX7_GPT4_ADDR            = 0x30300000,
+    /* MMAP Peripherals */
+    FSL_IMX7_DMA_APBH_ADDR        = 0x33000000,
+    FSL_IMX7_DMA_APBH_SIZE        = 0x8000,
 
-    FSL_IMX7_IOMUXC_ADDR          = 0x30330000,
-    FSL_IMX7_IOMUXC_GPR_ADDR      = 0x30340000,
-    FSL_IMX7_IOMUXCn_SIZE         = 0x1000,
+    /* GPV configuration */
+    FSL_IMX7_GPV6_ADDR            = 0x32600000,
+    FSL_IMX7_GPV5_ADDR            = 0x32500000,
+    FSL_IMX7_GPV4_ADDR            = 0x32400000,
+    FSL_IMX7_GPV3_ADDR            = 0x32300000,
+    FSL_IMX7_GPV2_ADDR            = 0x32200000,
+    FSL_IMX7_GPV1_ADDR            = 0x32100000,
+    FSL_IMX7_GPV0_ADDR            = 0x32000000,
+    FSL_IMX7_GPVn_SIZE            = (1 * MiB),
 
-    FSL_IMX7_OCOTP_ADDR           = 0x30350000,
-    FSL_IMX7_OCOTP_SIZE           = 0x10000,
+    /* Arm Peripherals */
+    FSL_IMX7_A7MPCORE_ADDR        = 0x31000000,
 
-    FSL_IMX7_ANALOG_ADDR          = 0x30360000,
-    FSL_IMX7_SNVS_ADDR            = 0x30370000,
-    FSL_IMX7_CCM_ADDR             = 0x30380000,
+    /* AIPS-3 Begin */
 
-    FSL_IMX7_SRC_ADDR             = 0x30390000,
-    FSL_IMX7_SRC_SIZE             = 0x1000,
+    FSL_IMX7_ENET2_ADDR           = 0x30BF0000,
+    FSL_IMX7_ENET1_ADDR           = 0x30BE0000,
 
-    FSL_IMX7_ADC1_ADDR            = 0x30610000,
-    FSL_IMX7_ADC2_ADDR            = 0x30620000,
-    FSL_IMX7_ADCn_SIZE            = 0x1000,
+    FSL_IMX7_SDMA_ADDR            = 0x30BD0000,
+    FSL_IMX7_SDMA_SIZE            = (4 * KiB),
 
-    FSL_IMX7_PWM1_ADDR            = 0x30660000,
-    FSL_IMX7_PWM2_ADDR            = 0x30670000,
-    FSL_IMX7_PWM3_ADDR            = 0x30680000,
-    FSL_IMX7_PWM4_ADDR            = 0x30690000,
-    FSL_IMX7_PWMn_SIZE            = 0x10000,
+    FSL_IMX7_EIM_ADDR             = 0x30BC0000,
+    FSL_IMX7_EIM_SIZE             = (4 * KiB),
 
-    FSL_IMX7_PCIE_PHY_ADDR        = 0x306D0000,
-    FSL_IMX7_PCIE_PHY_SIZE        = 0x10000,
+    FSL_IMX7_QSPI_ADDR            = 0x30BB0000,
+    FSL_IMX7_QSPI_SIZE            = 0x8000,
 
-    FSL_IMX7_GPC_ADDR             = 0x303A0000,
+    FSL_IMX7_SIM2_ADDR            = 0x30BA0000,
+    FSL_IMX7_SIM1_ADDR            = 0x30B90000,
+    FSL_IMX7_SIMn_SIZE            = (4 * KiB),
+
+    FSL_IMX7_USDHC3_ADDR          = 0x30B60000,
+    FSL_IMX7_USDHC2_ADDR          = 0x30B50000,
+    FSL_IMX7_USDHC1_ADDR          = 0x30B40000,
+
+    FSL_IMX7_USB3_ADDR            = 0x30B30000,
+    FSL_IMX7_USBMISC3_ADDR        = 0x30B30200,
+    FSL_IMX7_USB2_ADDR            = 0x30B20000,
+    FSL_IMX7_USBMISC2_ADDR        = 0x30B20200,
+    FSL_IMX7_USB1_ADDR            = 0x30B10000,
+    FSL_IMX7_USBMISC1_ADDR        = 0x30B10200,
+    FSL_IMX7_USBMISCn_SIZE        = 0x200,
+
+    FSL_IMX7_USB_PL301_ADDR       = 0x30AD0000,
+    FSL_IMX7_USB_PL301_SIZE       = (64 * KiB),
+
+    FSL_IMX7_SEMAPHORE_HS_ADDR    = 0x30AC0000,
+    FSL_IMX7_SEMAPHORE_HS_SIZE    = (64 * KiB),
+
+    FSL_IMX7_MUB_ADDR             = 0x30AB0000,
+    FSL_IMX7_MUA_ADDR             = 0x30AA0000,
+    FSL_IMX7_MUn_SIZE             = (KiB),
+
+    FSL_IMX7_UART7_ADDR           = 0x30A90000,
+    FSL_IMX7_UART6_ADDR           = 0x30A80000,
+    FSL_IMX7_UART5_ADDR           = 0x30A70000,
+    FSL_IMX7_UART4_ADDR           = 0x30A60000,
+
+    FSL_IMX7_I2C4_ADDR            = 0x30A50000,
+    FSL_IMX7_I2C3_ADDR            = 0x30A40000,
+    FSL_IMX7_I2C2_ADDR            = 0x30A30000,
+    FSL_IMX7_I2C1_ADDR            = 0x30A20000,
+
+    FSL_IMX7_CAN2_ADDR            = 0x30A10000,
+    FSL_IMX7_CAN1_ADDR            = 0x30A00000,
+    FSL_IMX7_CANn_SIZE            = (4 * KiB),
+
+    FSL_IMX7_AIPS3_CONF_ADDR      = 0x309F0000,
+    FSL_IMX7_AIPS3_CONF_SIZE      = (64 * KiB),
 
     FSL_IMX7_CAAM_ADDR            = 0x30900000,
-    FSL_IMX7_CAAM_SIZE            = 0x40000,
+    FSL_IMX7_CAAM_SIZE            = (256 * KiB),
 
-    FSL_IMX7_CAN1_ADDR            = 0x30A00000,
-    FSL_IMX7_CAN2_ADDR            = 0x30A10000,
-    FSL_IMX7_CANn_SIZE            = 0x10000,
+    FSL_IMX7_SPBA_ADDR            = 0x308F0000,
+    FSL_IMX7_SPBA_SIZE            = (4 * KiB),
 
-    FSL_IMX7_I2C1_ADDR            = 0x30A20000,
-    FSL_IMX7_I2C2_ADDR            = 0x30A30000,
-    FSL_IMX7_I2C3_ADDR            = 0x30A40000,
-    FSL_IMX7_I2C4_ADDR            = 0x30A50000,
+    FSL_IMX7_SAI3_ADDR            = 0x308C0000,
+    FSL_IMX7_SAI2_ADDR            = 0x308B0000,
+    FSL_IMX7_SAI1_ADDR            = 0x308A0000,
+    FSL_IMX7_SAIn_SIZE            = (4 * KiB),
 
-    FSL_IMX7_ECSPI1_ADDR          = 0x30820000,
-    FSL_IMX7_ECSPI2_ADDR          = 0x30830000,
-    FSL_IMX7_ECSPI3_ADDR          = 0x30840000,
-    FSL_IMX7_ECSPI4_ADDR          = 0x30630000,
-
-    FSL_IMX7_LCDIF_ADDR           = 0x30730000,
-    FSL_IMX7_LCDIF_SIZE           = 0x1000,
-
-    FSL_IMX7_UART1_ADDR           = 0x30860000,
+    FSL_IMX7_UART3_ADDR           = 0x30880000,
     /*
      * Some versions of the reference manual claim that UART2 is @
      * 0x30870000, but experiments with HW + DT files in upstream
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
      * actually located @ 0x30890000
      */
     FSL_IMX7_UART2_ADDR           = 0x30890000,
-    FSL_IMX7_UART3_ADDR           = 0x30880000,
-    FSL_IMX7_UART4_ADDR           = 0x30A60000,
-    FSL_IMX7_UART5_ADDR           = 0x30A70000,
-    FSL_IMX7_UART6_ADDR           = 0x30A80000,
-    FSL_IMX7_UART7_ADDR           = 0x30A90000,
+    FSL_IMX7_UART1_ADDR           = 0x30860000,
 
-    FSL_IMX7_SAI1_ADDR            = 0x308A0000,
-    FSL_IMX7_SAI2_ADDR            = 0x308B0000,
-    FSL_IMX7_SAI3_ADDR            = 0x308C0000,
-    FSL_IMX7_SAIn_SIZE            = 0x10000,
+    FSL_IMX7_ECSPI3_ADDR          = 0x30840000,
+    FSL_IMX7_ECSPI2_ADDR          = 0x30830000,
+    FSL_IMX7_ECSPI1_ADDR          = 0x30820000,
+    FSL_IMX7_ECSPIn_SIZE          = (4 * KiB),
 
-    FSL_IMX7_ENET1_ADDR           = 0x30BE0000,
-    FSL_IMX7_ENET2_ADDR           = 0x30BF0000,
+    /* AIPS-3 End */
 
-    FSL_IMX7_USB1_ADDR            = 0x30B10000,
-    FSL_IMX7_USBMISC1_ADDR        = 0x30B10200,
-    FSL_IMX7_USB2_ADDR            = 0x30B20000,
-    FSL_IMX7_USBMISC2_ADDR        = 0x30B20200,
-    FSL_IMX7_USB3_ADDR            = 0x30B30000,
-    FSL_IMX7_USBMISC3_ADDR        = 0x30B30200,
-    FSL_IMX7_USBMISCn_SIZE        = 0x200,
+    /* AIPS-2 Begin */
 
-    FSL_IMX7_USDHC1_ADDR          = 0x30B40000,
-    FSL_IMX7_USDHC2_ADDR          = 0x30B50000,
-    FSL_IMX7_USDHC3_ADDR          = 0x30B60000,
+    FSL_IMX7_AXI_DEBUG_MON_ADDR   = 0x307E0000,
+    FSL_IMX7_AXI_DEBUG_MON_SIZE   = (64 * KiB),
 
-    FSL_IMX7_SDMA_ADDR            = 0x30BD0000,
-    FSL_IMX7_SDMA_SIZE            = 0x1000,
+    FSL_IMX7_PERFMON2_ADDR        = 0x307D0000,
+    FSL_IMX7_PERFMON1_ADDR        = 0x307C0000,
+    FSL_IMX7_PERFMONn_SIZE        = (64 * KiB),
+
+    FSL_IMX7_DDRC_ADDR            = 0x307A0000,
+    FSL_IMX7_DDRC_SIZE            = (4 * KiB),
+
+    FSL_IMX7_DDRC_PHY_ADDR        = 0x30790000,
+    FSL_IMX7_DDRC_PHY_SIZE        = (4 * KiB),
+
+    FSL_IMX7_TZASC_ADDR           = 0x30780000,
+    FSL_IMX7_TZASC_SIZE           = (64 * KiB),
+
+    FSL_IMX7_MIPI_DSI_ADDR        = 0x30760000,
+    FSL_IMX7_MIPI_DSI_SIZE        = (4 * KiB),
+
+    FSL_IMX7_MIPI_CSI_ADDR        = 0x30750000,
+    FSL_IMX7_MIPI_CSI_SIZE        = 0x4000,
+
+    FSL_IMX7_LCDIF_ADDR           = 0x30730000,
+    FSL_IMX7_LCDIF_SIZE           = 0x8000,
+
+    FSL_IMX7_CSI_ADDR             = 0x30710000,
+    FSL_IMX7_CSI_SIZE             = (4 * KiB),
+
+    FSL_IMX7_PXP_ADDR             = 0x30700000,
+    FSL_IMX7_PXP_SIZE             = 0x4000,
+
+    FSL_IMX7_EPDC_ADDR            = 0x306F0000,
+    FSL_IMX7_EPDC_SIZE            = (4 * KiB),
+
+    FSL_IMX7_PCIE_PHY_ADDR        = 0x306D0000,
+    FSL_IMX7_PCIE_PHY_SIZE        = (4 * KiB),
+
+    FSL_IMX7_SYSCNT_CTRL_ADDR     = 0x306C0000,
+    FSL_IMX7_SYSCNT_CMP_ADDR      = 0x306B0000,
+    FSL_IMX7_SYSCNT_RD_ADDR       = 0x306A0000,
+
+    FSL_IMX7_PWM4_ADDR            = 0x30690000,
+    FSL_IMX7_PWM3_ADDR            = 0x30680000,
+    FSL_IMX7_PWM2_ADDR            = 0x30670000,
+    FSL_IMX7_PWM1_ADDR            = 0x30660000,
+    FSL_IMX7_PWMn_SIZE            = (4 * KiB),
+
+    FSL_IMX7_FlEXTIMER2_ADDR      = 0x30650000,
+    FSL_IMX7_FlEXTIMER1_ADDR      = 0x30640000,
+    FSL_IMX7_FLEXTIMERn_SIZE      = (4 * KiB),
+
+    FSL_IMX7_ECSPI4_ADDR          = 0x30630000,
+
+    FSL_IMX7_ADC2_ADDR            = 0x30620000,
+    FSL_IMX7_ADC1_ADDR            = 0x30610000,
+    FSL_IMX7_ADCn_SIZE            = (4 * KiB),
+
+    FSL_IMX7_AIPS2_CONF_ADDR      = 0x305F0000,
+    FSL_IMX7_AIPS2_CONF_SIZE      = (64 * KiB),
+
+    /* AIPS-2 End */
+
+    /* AIPS-1 Begin */
+
+    FSL_IMX7_CSU_ADDR             = 0x303E0000,
+    FSL_IMX7_CSU_SIZE             = (64 * KiB),
+
+    FSL_IMX7_RDC_ADDR             = 0x303D0000,
+    FSL_IMX7_RDC_SIZE             = (4 * KiB),
+
+    FSL_IMX7_SEMAPHORE2_ADDR      = 0x303C0000,
+    FSL_IMX7_SEMAPHORE1_ADDR      = 0x303B0000,
+    FSL_IMX7_SEMAPHOREn_SIZE      = (4 * KiB),
+
+    FSL_IMX7_GPC_ADDR             = 0x303A0000,
+
+    FSL_IMX7_SRC_ADDR             = 0x30390000,
+    FSL_IMX7_SRC_SIZE             = (4 * KiB),
+
+    FSL_IMX7_CCM_ADDR             = 0x30380000,
+
+    FSL_IMX7_SNVS_HP_ADDR         = 0x30370000,
+
+    FSL_IMX7_ANALOG_ADDR          = 0x30360000,
+
+    FSL_IMX7_OCOTP_ADDR           = 0x30350000,
+    FSL_IMX7_OCOTP_SIZE           = 0x10000,
+
+    FSL_IMX7_IOMUXC_GPR_ADDR      = 0x30340000,
+    FSL_IMX7_IOMUXC_GPR_SIZE      = (4 * KiB),
+
+    FSL_IMX7_IOMUXC_ADDR          = 0x30330000,
+    FSL_IMX7_IOMUXC_SIZE          = (4 * KiB),
+
+    FSL_IMX7_KPP_ADDR             = 0x30320000,
+    FSL_IMX7_KPP_SIZE             = (4 * KiB),
+
+    FSL_IMX7_ROMCP_ADDR           = 0x30310000,
+    FSL_IMX7_ROMCP_SIZE           = (4 * KiB),
+
+    FSL_IMX7_GPT4_ADDR            = 0x30300000,
+    FSL_IMX7_GPT3_ADDR            = 0x302F0000,
+    FSL_IMX7_GPT2_ADDR            = 0x302E0000,
+    FSL_IMX7_GPT1_ADDR            = 0x302D0000,
+
+    FSL_IMX7_IOMUXC_LPSR_ADDR     = 0x302C0000,
+    FSL_IMX7_IOMUXC_LPSR_SIZE     = (4 * KiB),
+
+    FSL_IMX7_WDOG4_ADDR           = 0x302B0000,
+    FSL_IMX7_WDOG3_ADDR           = 0x302A0000,
+    FSL_IMX7_WDOG2_ADDR           = 0x30290000,
+    FSL_IMX7_WDOG1_ADDR           = 0x30280000,
+
+    FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
+
+    FSL_IMX7_GPIO7_ADDR           = 0x30260000,
+    FSL_IMX7_GPIO6_ADDR           = 0x30250000,
+    FSL_IMX7_GPIO5_ADDR           = 0x30240000,
+    FSL_IMX7_GPIO4_ADDR           = 0x30230000,
+    FSL_IMX7_GPIO3_ADDR           = 0x30220000,
+    FSL_IMX7_GPIO2_ADDR           = 0x30210000,
+    FSL_IMX7_GPIO1_ADDR           = 0x30200000,
+
+    FSL_IMX7_AIPS1_CONF_ADDR      = 0x301F0000,
+    FSL_IMX7_AIPS1_CONF_SIZE      = (64 * KiB),
 
-    FSL_IMX7_A7MPCORE_ADDR        = 0x31000000,
     FSL_IMX7_A7MPCORE_DAP_ADDR    = 0x30000000,
+    FSL_IMX7_A7MPCORE_DAP_SIZE    = (1 * MiB),
 
-    FSL_IMX7_PCIE_REG_ADDR        = 0x33800000,
-    FSL_IMX7_PCIE_REG_SIZE        = 16 * 1024,
+    /* AIPS-1 End */
 
-    FSL_IMX7_GPR_ADDR             = 0x30340000,
+    FSL_IMX7_EIM_CS0_ADDR         = 0x28000000,
+    FSL_IMX7_EIM_CS0_SIZE         = (128 * MiB),
 
-    FSL_IMX7_DMA_APBH_ADDR        = 0x33000000,
-    FSL_IMX7_DMA_APBH_SIZE        = 0x2000,
+    FSL_IMX7_OCRAM_PXP_ADDR       = 0x00940000,
+    FSL_IMX7_OCRAM_PXP_SIZE       = (32 * KiB),
+
+    FSL_IMX7_OCRAM_EPDC_ADDR      = 0x00920000,
+    FSL_IMX7_OCRAM_EPDC_SIZE      = (128 * KiB),
+
+    FSL_IMX7_OCRAM_MEM_ADDR       = 0x00900000,
+    FSL_IMX7_OCRAM_MEM_SIZE       = (128 * KiB),
+
+    FSL_IMX7_TCMU_ADDR            = 0x00800000,
+    FSL_IMX7_TCMU_SIZE            = (32 * KiB),
+
+    FSL_IMX7_TCML_ADDR            = 0x007F8000,
+    FSL_IMX7_TCML_SIZE            = (32 * KiB),
+
+    FSL_IMX7_OCRAM_S_ADDR         = 0x00180000,
+    FSL_IMX7_OCRAM_S_SIZE         = (32 * KiB),
+
+    FSL_IMX7_CAAM_MEM_ADDR        = 0x00100000,
+    FSL_IMX7_CAAM_MEM_SIZE        = (32 * KiB),
+
+    FSL_IMX7_ROM_ADDR             = 0x00000000,
+    FSL_IMX7_ROM_SIZE             = (96 * KiB),
 };
 
 enum FslIMX7IRQs {
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     char name[NAME_SIZE];
     int i;
 
+    /*
+     * CPUs
+     */
     for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) {
         snprintf(name, NAME_SIZE, "cpu%d", i);
         object_initialize_child(obj, name, &s->cpu[i],
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
                             TYPE_A15MPCORE_PRIV);
 
     /*
-     * GPIOs 1 to 7
+     * GPIOs
      */
     for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
         snprintf(name, NAME_SIZE, "gpio%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     }
 
     /*
-     * GPT1, 2, 3, 4
+     * GPTs
      */
     for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
         snprintf(name, NAME_SIZE, "gpt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      */
     object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
 
+    /*
+     * ECSPIs
+     */
     for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
         snprintf(name, NAME_SIZE, "spi%d", i + 1);
         object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
     }
 
-
+    /*
+     * I2Cs
+     */
     for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
         snprintf(name, NAME_SIZE, "i2c%d", i + 1);
         object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
     }
 
     /*
-     * UART
+     * UARTs
      */
     for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
             snprintf(name, NAME_SIZE, "uart%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     }
 
     /*
-     * Ethernet
+     * Ethernets
      */
     for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
             snprintf(name, NAME_SIZE, "eth%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     }
 
     /*
-     * SDHCI
+     * SDHCIs
      */
     for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
             snprintf(name, NAME_SIZE, "usdhc%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
 
     /*
-     * Watchdog
+     * Watchdogs
      */
     for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
             snprintf(name, NAME_SIZE, "wdt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      */
     object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
 
+    /*
+     * PCIE
+     */
     object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
 
+    /*
+     * USBs
+     */
     for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
         snprintf(name, NAME_SIZE, "usb%d", i);
         object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
         return;
     }
 
+    /*
+     * CPUs
+     */
     for (i = 0; i < smp_cpus; i++) {
         o = OBJECT(&s->cpu[i]);
 
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      * A7MPCORE DAP
      */
     create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR,
-                                0x100000);
+                                FSL_IMX7_A7MPCORE_DAP_SIZE);
 
     /*
-     * GPT1, 2, 3, 4
+     * GPTs
      */
     for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
         static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
                                             FSL_IMX7_GPTn_IRQ[i]));
     }
 
+    /*
+     * GPIOs
+     */
     for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
         static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = {
             FSL_IMX7_GPIO1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     /*
      * IOMUXC and IOMUXC_LPSR
      */
-    for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) {
-        static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = {
-            FSL_IMX7_IOMUXC_ADDR,
-            FSL_IMX7_IOMUXC_LPSR_ADDR,
-        };
-
-        snprintf(name, NAME_SIZE, "iomuxc%d", i);
-        create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i],
-                                    FSL_IMX7_IOMUXCn_SIZE);
-    }
+    create_unimplemented_device("iomuxc", FSL_IMX7_IOMUXC_ADDR,
+                                FSL_IMX7_IOMUXC_SIZE);
+    create_unimplemented_device("iomuxc_lspr", FSL_IMX7_IOMUXC_LPSR_ADDR,
+                                FSL_IMX7_IOMUXC_LPSR_SIZE);
 
     /*
      * CCM
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
 
-    /* Initialize all ECSPI */
+    /*
+     * ECSPIs
+     */
     for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
         static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = {
             FSL_IMX7_ECSPI1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
                                             FSL_IMX7_SPIn_IRQ[i]));
     }
 
+    /*
+     * I2Cs
+     */
     for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
         static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = {
             FSL_IMX7_I2C1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * UART
+     * UARTs
      */
     for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
         static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * Ethernet
+     * Ethernets
      *
      * We must use two loops since phy_connected affects the other interface
      * and we have to set all properties before calling sysbus_realize().
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * USDHC
+     * USDHCs
      */
     for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
         static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      * SNVS
      */
     sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_HP_ADDR);
 
     /*
      * SRC
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
 
     /*
-     * Watchdog
+     * Watchdogs
      */
     for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
         static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE);
 
     /*
-     * PWM
+     * PWMs
      */
-    create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE);
-    create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE);
-    create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE);
-    create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE);
+    for (i = 0; i < FSL_IMX7_NUM_PWMS; i++) {
+        static const hwaddr FSL_IMX7_PWMn_ADDR[FSL_IMX7_NUM_PWMS] = {
+            FSL_IMX7_PWM1_ADDR,
+            FSL_IMX7_PWM2_ADDR,
+            FSL_IMX7_PWM3_ADDR,
+            FSL_IMX7_PWM4_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "pwm%d", i);
+        create_unimplemented_device(name, FSL_IMX7_PWMn_ADDR[i],
+                                    FSL_IMX7_PWMn_SIZE);
+    }
 
     /*
-     * CAN
+     * CANs
      */
-    create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE);
-    create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE);
+    for (i = 0; i < FSL_IMX7_NUM_CANS; i++) {
+        static const hwaddr FSL_IMX7_CANn_ADDR[FSL_IMX7_NUM_CANS] = {
+            FSL_IMX7_CAN1_ADDR,
+            FSL_IMX7_CAN2_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "can%d", i);
+        create_unimplemented_device(name, FSL_IMX7_CANn_ADDR[i],
+                                    FSL_IMX7_CANn_SIZE);
+    }
 
     /*
-     * SAI (Audio SSI (Synchronous Serial Interface))
+     * SAIs (Audio SSI (Synchronous Serial Interface))
      */
-    create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR, FSL_IMX7_SAIn_SIZE);
-    create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR, FSL_IMX7_SAIn_SIZE);
-    create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR, FSL_IMX7_SAIn_SIZE);
+    for (i = 0; i < FSL_IMX7_NUM_SAIS; i++) {
+        static const hwaddr FSL_IMX7_SAIn_ADDR[FSL_IMX7_NUM_SAIS] = {
+            FSL_IMX7_SAI1_ADDR,
+            FSL_IMX7_SAI2_ADDR,
+            FSL_IMX7_SAI3_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "sai%d", i);
+        create_unimplemented_device(name, FSL_IMX7_SAIn_ADDR[i],
+                                    FSL_IMX7_SAIn_SIZE);
+    }
 
     /*
      * OCOTP
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
                                 FSL_IMX7_OCOTP_SIZE);
 
+    /*
+     * GPR
+     */
     sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_IOMUXC_GPR_ADDR);
 
+    /*
+     * PCIE
+     */
     sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
 
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
 
-
+    /*
+     * USBs
+     */
     for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
         static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = {
             FSL_IMX7_USBMISC1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      */
     create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
                                 FSL_IMX7_PCIE_PHY_SIZE);
+
 }
 
 static Property fsl_imx7_properties[] = {
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: f887a3483996ba06d40bd62ffdfb0ecf68621987.1692964892.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx7.h |  7 +++++
 hw/arm/fsl-imx7.c         | 63 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 70 insertions(+)

diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
     IMX7GPRState       gpr;
     ChipideaState      usb[FSL_IMX7_NUM_USBS];
     DesignwarePCIEHost pcie;
+    MemoryRegion       rom;
+    MemoryRegion       caam;
+    MemoryRegion       ocram;
+    MemoryRegion       ocram_epdc;
+    MemoryRegion       ocram_pxp;
+    MemoryRegion       ocram_s;
+
     uint32_t           phy_num[FSL_IMX7_NUM_ETHS];
     bool               phy_connected[FSL_IMX7_NUM_ETHS];
 };
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
                                 FSL_IMX7_PCIE_PHY_SIZE);
 
+    /*
+     * CSU
+     */
+    create_unimplemented_device("csu", FSL_IMX7_CSU_ADDR,
+                                FSL_IMX7_CSU_SIZE);
+
+    /*
+     * TZASC
+     */
+    create_unimplemented_device("tzasc", FSL_IMX7_TZASC_ADDR,
+                                FSL_IMX7_TZASC_SIZE);
+
+    /*
+     * OCRAM memory
+     */
+    memory_region_init_ram(&s->ocram, NULL, "imx7.ocram",
+                           FSL_IMX7_OCRAM_MEM_SIZE,
+                           &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_MEM_ADDR,
+                                &s->ocram);
+
+    /*
+     * OCRAM EPDC memory
+     */
+    memory_region_init_ram(&s->ocram_epdc, NULL, "imx7.ocram_epdc",
+                           FSL_IMX7_OCRAM_EPDC_SIZE,
+                           &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_EPDC_ADDR,
+                                &s->ocram_epdc);
+
+    /*
+     * OCRAM PXP memory
+     */
+    memory_region_init_ram(&s->ocram_pxp, NULL, "imx7.ocram_pxp",
+                           FSL_IMX7_OCRAM_PXP_SIZE,
+                           &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_PXP_ADDR,
+                                &s->ocram_pxp);
+
+    /*
+     * OCRAM_S memory
+     */
+    memory_region_init_ram(&s->ocram_s, NULL, "imx7.ocram_s",
+                           FSL_IMX7_OCRAM_S_SIZE,
+                           &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_S_ADDR,
+                                &s->ocram_s);
+
+    /*
+     * ROM memory
+     */
+    memory_region_init_rom(&s->rom, OBJECT(dev), "imx7.rom",
+                           FSL_IMX7_ROM_SIZE, &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_ROM_ADDR,
+                                &s->rom);
+
+    /*
+     * CAAM memory
+     */
+    memory_region_init_rom(&s->caam, OBJECT(dev), "imx7.caam",
+                           FSL_IMX7_CAAM_MEM_SIZE, &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_CAAM_MEM_ADDR,
+                                &s->caam);
 }
 
 static Property fsl_imx7_properties[] = {
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

The SRC device is normally used to start the secondary CPU.

When running Linux directly, QEMU is emulating a PSCI interface that UBOOT
is installing at boot time and therefore the fact that the SRC device is
unimplemented is hidden as Qemu respond directly to PSCI requets without
using the SRC device.

But if you try to run a more bare metal application (maybe uboot itself),
then it is not possible to start the secondary CPU as the SRC is an
unimplemented device.

This patch adds the ability to start the secondary CPU through the SRC
device so that you can use this feature in bare metal applications.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: ce9a0162defd2acee5dc7f8a674743de0cded569.1692964892.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx7.h  |   3 +-
 include/hw/misc/imx7_src.h |  66 +++++++++
 hw/arm/fsl-imx7.c          |   8 +-
 hw/misc/imx7_src.c         | 276 +++++++++++++++++++++++++++++++++++++
 hw/misc/meson.build        |   1 +
 hw/misc/trace-events       |   4 +
 6 files changed, 356 insertions(+), 2 deletions(-)
 create mode 100644 include/hw/misc/imx7_src.h
 create mode 100644 hw/misc/imx7_src.c

The architecture requires (R_TYTWB) that an attempt to return from EL3
when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This
enforces that the CPU can't ever be executing below EL3 with the
NSE,NS bits indicating an invalid security state.)

We were missing this check; add it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807150618.101357-1-peter.maydell@linaro.org
---
 target/arm/tcg/helper-a64.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
         spsr &= ~PSTATE_SS;
     }
 
+    /*
+     * FEAT_RME forbids return from EL3 with an invalid security state.
+     * We don't need an explicit check for FEAT_RME here because we enforce
+     * in scr_write() that you can't set the NSE bit without it.
+     */
+    if (cur_el == 3 && (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) == SCR_NSE) {
+        goto illegal_return;
+    }
+
     new_el = el_from_spsr(spsr);
     if (new_el == -1) {
         goto illegal_return;
-- 
2.34.1

In the aspeed_rtc device we store a difference between two time_t
values in an 'int'. This is not really correct when time_t could
be 64 bits. Enlarge the field to 'int64_t'.

This is a migration compatibility break for the aspeed boards.
While we are changing the vmstate, remove the accidental
duplicate of the offset field.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/rtc/aspeed_rtc.h | 2 +-
 hw/rtc/aspeed_rtc.c         | 5 ++---
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/include/hw/rtc/aspeed_rtc.h b/include/hw/rtc/aspeed_rtc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/rtc/aspeed_rtc.h
+++ b/include/hw/rtc/aspeed_rtc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedRtcState {
     qemu_irq irq;
 
     uint32_t reg[0x18];
-    int offset;
+    int64_t offset;
 
 };
 
diff --git a/hw/rtc/aspeed_rtc.c b/hw/rtc/aspeed_rtc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/rtc/aspeed_rtc.c
+++ b/hw/rtc/aspeed_rtc.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_rtc_ops = {
 
 static const VMStateDescription vmstate_aspeed_rtc = {
     .name = TYPE_ASPEED_RTC,
-    .version_id = 1,
+    .version_id = 2,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32_ARRAY(reg, AspeedRtcState, 0x18),
-        VMSTATE_INT32(offset, AspeedRtcState),
-        VMSTATE_INT32(offset, AspeedRtcState),
+        VMSTATE_INT64(offset, AspeedRtcState),
         VMSTATE_END_OF_LIST()
     }
 };
-- 
2.34.1

The functions qemu_get_timedate() and qemu_timedate_diff() take
and return a time offset as an integer. Coverity points out that
means that when an RTC device implementation holds an offset
as a time_t, as the m48t59 does, the time_t will get truncated.
(CID 1507157, 1517772).

The functions work with time_t internally, so make them use that type
in their APIs.

Note that this won't help any Y2038 issues where either the device
model itself is keeping the offset in a 32-bit integer, or where the
hardware under emulation has Y2038 or other rollover problems.  If we
missed any cases of the former then hopefully Coverity will warn us
about them since after this patch we'd be truncating a time_t in
assignments from qemu_timedate_diff().)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/sysemu/rtc.h | 4 ++--
 softmmu/rtc.c        | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/sysemu/rtc.h b/include/sysemu/rtc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/sysemu/rtc.h
+++ b/include/sysemu/rtc.h
@@ -XXX,XX +XXX,XX @@
  * The behaviour of the clock whose value this function returns will
  * depend on the -rtc command line option passed by the user.
  */
-void qemu_get_timedate(struct tm *tm, int offset);
+void qemu_get_timedate(struct tm *tm, time_t offset);
 
 /**
  * qemu_timedate_diff: Return difference between a struct tm and the RTC
@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset);
  * a timestamp one hour further ahead than the current RTC time
  * then this function will return 3600.
  */
-int qemu_timedate_diff(struct tm *tm);
+time_t qemu_timedate_diff(struct tm *tm);
 
 #endif
diff --git a/softmmu/rtc.c b/softmmu/rtc.c
index XXXXXXX..XXXXXXX 100644
--- a/softmmu/rtc.c
+++ b/softmmu/rtc.c
@@ -XXX,XX +XXX,XX @@ static time_t qemu_ref_timedate(QEMUClockType clock)
     return value;
 }
 
-void qemu_get_timedate(struct tm *tm, int offset)
+void qemu_get_timedate(struct tm *tm, time_t offset)
 {
     time_t ti = qemu_ref_timedate(rtc_clock);
 
@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset)
     }
 }
 
-int qemu_timedate_diff(struct tm *tm)
+time_t qemu_timedate_diff(struct tm *tm)
 {
     time_t seconds;
 
-- 
2.34.1

Where architecturally one ARM_FEATURE_X flag implies another
ARM_FEATURE_Y, we allow the CPU init function to only set X, and then
set Y for it.  Currently we do this in two places -- we set a few
flags in arm_cpu_post_init() because we need them to decide which
properties to create on the CPU object, and then we do the rest in
arm_cpu_realizefn().  However, this is fragile, because it's easy to
add a new property and not notice that this means that an X-implies-Y
check now has to move from realize to post-init.

As a specific example, the pmsav7-dregion property is conditional
on ARM_FEATURE_PMSA && ARM_FEATURE_V7, which means it won't appear
on the Cortex-M33 and -M55, because they set ARM_FEATURE_V8 and
rely on V8-implies-V7, which doesn't happen until the realizefn.

Move all of these X-implies-Y checks into a new function, which
we call at the top of arm_cpu_post_init(), so the feature bits
are available at that point.

This does now give us the reverse issue, that if there's a feature
bit which is enabled or disabled by the setting of a property then
then X-implies-Y features that are dependent on that property need to
be in realize, not in this new function.  But the only one of those
is the "EL3 implies VBAR" which is already in the right place, so
putting things this way round seems better to me.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230724174335.2150499-2-peter.maydell@linaro.org
---
 target/arm/cpu.c | 179 +++++++++++++++++++++++++----------------------
 1 file changed, 97 insertions(+), 82 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
       NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
 }
 
+static void arm_cpu_propagate_feature_implications(ARMCPU *cpu)
+{
+    CPUARMState *env = &cpu->env;
+    bool no_aa32 = false;
+
+    /*
+     * Some features automatically imply others: set the feature
+     * bits explicitly for these cases.
+     */
+
+    if (arm_feature(env, ARM_FEATURE_M)) {
+        set_feature(env, ARM_FEATURE_PMSA);
+    }
+
+    if (arm_feature(env, ARM_FEATURE_V8)) {
+        if (arm_feature(env, ARM_FEATURE_M)) {
+            set_feature(env, ARM_FEATURE_V7);
+        } else {
+            set_feature(env, ARM_FEATURE_V7VE);
+        }
+    }
+
+    /*
+     * There exist AArch64 cpus without AArch32 support.  When KVM
+     * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
+     * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
+     * As a general principle, we also do not make ID register
+     * consistency checks anywhere unless using TCG, because only
+     * for TCG would a consistency-check failure be a QEMU bug.
+     */
+    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
+        no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
+    }
+
+    if (arm_feature(env, ARM_FEATURE_V7VE)) {
+        /*
+         * v7 Virtualization Extensions. In real hardware this implies
+         * EL2 and also the presence of the Security Extensions.
+         * For QEMU, for backwards-compatibility we implement some
+         * CPUs or CPU configs which have no actual EL2 or EL3 but do
+         * include the various other features that V7VE implies.
+         * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
+         * Security Extensions is ARM_FEATURE_EL3.
+         */
+        assert(!tcg_enabled() || no_aa32 ||
+               cpu_isar_feature(aa32_arm_div, cpu));
+        set_feature(env, ARM_FEATURE_LPAE);
+        set_feature(env, ARM_FEATURE_V7);
+    }
+    if (arm_feature(env, ARM_FEATURE_V7)) {
+        set_feature(env, ARM_FEATURE_VAPA);
+        set_feature(env, ARM_FEATURE_THUMB2);
+        set_feature(env, ARM_FEATURE_MPIDR);
+        if (!arm_feature(env, ARM_FEATURE_M)) {
+            set_feature(env, ARM_FEATURE_V6K);
+        } else {
+            set_feature(env, ARM_FEATURE_V6);
+        }
+
+        /*
+         * Always define VBAR for V7 CPUs even if it doesn't exist in
+         * non-EL3 configs. This is needed by some legacy boards.
+         */
+        set_feature(env, ARM_FEATURE_VBAR);
+    }
+    if (arm_feature(env, ARM_FEATURE_V6K)) {
+        set_feature(env, ARM_FEATURE_V6);
+        set_feature(env, ARM_FEATURE_MVFR);
+    }
+    if (arm_feature(env, ARM_FEATURE_V6)) {
+        set_feature(env, ARM_FEATURE_V5);
+        if (!arm_feature(env, ARM_FEATURE_M)) {
+            assert(!tcg_enabled() || no_aa32 ||
+                   cpu_isar_feature(aa32_jazelle, cpu));
+            set_feature(env, ARM_FEATURE_AUXCR);
+        }
+    }
+    if (arm_feature(env, ARM_FEATURE_V5)) {
+        set_feature(env, ARM_FEATURE_V4T);
+    }
+    if (arm_feature(env, ARM_FEATURE_LPAE)) {
+        set_feature(env, ARM_FEATURE_V7MP);
+    }
+    if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
+        set_feature(env, ARM_FEATURE_CBAR);
+    }
+    if (arm_feature(env, ARM_FEATURE_THUMB2) &&
+        !arm_feature(env, ARM_FEATURE_M)) {
+        set_feature(env, ARM_FEATURE_THUMB_DSP);
+    }
+}
+
 void arm_cpu_post_init(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
 
-    /* M profile implies PMSA. We have to do this here rather than
-     * in realize with the other feature-implication checks because
-     * we look at the PMSA bit to see if we should add some properties.
+    /*
+     * Some features imply others. Figure this out now, because we
+     * are going to look at the feature bits in deciding which
+     * properties to add.
      */
-    if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
-        set_feature(&cpu->env, ARM_FEATURE_PMSA);
-    }
+    arm_cpu_propagate_feature_implications(cpu);
 
     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     CPUARMState *env = &cpu->env;
     int pagebits;
     Error *local_err = NULL;
-    bool no_aa32 = false;
 
     /* Use pc-relative instructions in system-mode */
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         cpu->isar.id_isar3 = u;
     }
 
-    /* Some features automatically imply others: */
-    if (arm_feature(env, ARM_FEATURE_V8)) {
-        if (arm_feature(env, ARM_FEATURE_M)) {
-            set_feature(env, ARM_FEATURE_V7);
-        } else {
-            set_feature(env, ARM_FEATURE_V7VE);
-        }
-    }
-
-    /*
-     * There exist AArch64 cpus without AArch32 support.  When KVM
-     * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
-     * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
-     * As a general principle, we also do not make ID register
-     * consistency checks anywhere unless using TCG, because only
-     * for TCG would a consistency-check failure be a QEMU bug.
-     */
-    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
-        no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
-    }
-
-    if (arm_feature(env, ARM_FEATURE_V7VE)) {
-        /* v7 Virtualization Extensions. In real hardware this implies
-         * EL2 and also the presence of the Security Extensions.
-         * For QEMU, for backwards-compatibility we implement some
-         * CPUs or CPU configs which have no actual EL2 or EL3 but do
-         * include the various other features that V7VE implies.
-         * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
-         * Security Extensions is ARM_FEATURE_EL3.
-         */
-        assert(!tcg_enabled() || no_aa32 ||
-               cpu_isar_feature(aa32_arm_div, cpu));
-        set_feature(env, ARM_FEATURE_LPAE);
-        set_feature(env, ARM_FEATURE_V7);
-    }
-    if (arm_feature(env, ARM_FEATURE_V7)) {
-        set_feature(env, ARM_FEATURE_VAPA);
-        set_feature(env, ARM_FEATURE_THUMB2);
-        set_feature(env, ARM_FEATURE_MPIDR);
-        if (!arm_feature(env, ARM_FEATURE_M)) {
-            set_feature(env, ARM_FEATURE_V6K);
-        } else {
-            set_feature(env, ARM_FEATURE_V6);
-        }
-
-        /* Always define VBAR for V7 CPUs even if it doesn't exist in
-         * non-EL3 configs. This is needed by some legacy boards.
-         */
-        set_feature(env, ARM_FEATURE_VBAR);
-    }
-    if (arm_feature(env, ARM_FEATURE_V6K)) {
-        set_feature(env, ARM_FEATURE_V6);
-        set_feature(env, ARM_FEATURE_MVFR);
-    }
-    if (arm_feature(env, ARM_FEATURE_V6)) {
-        set_feature(env, ARM_FEATURE_V5);
-        if (!arm_feature(env, ARM_FEATURE_M)) {
-            assert(!tcg_enabled() || no_aa32 ||
-                   cpu_isar_feature(aa32_jazelle, cpu));
-            set_feature(env, ARM_FEATURE_AUXCR);
-        }
-    }
-    if (arm_feature(env, ARM_FEATURE_V5)) {
-        set_feature(env, ARM_FEATURE_V4T);
-    }
-    if (arm_feature(env, ARM_FEATURE_LPAE)) {
-        set_feature(env, ARM_FEATURE_V7MP);
-    }
-    if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
-        set_feature(env, ARM_FEATURE_CBAR);
-    }
-    if (arm_feature(env, ARM_FEATURE_THUMB2) &&
-        !arm_feature(env, ARM_FEATURE_M)) {
-        set_feature(env, ARM_FEATURE_THUMB_DSP);
-    }
 
     /*
      * We rely on no XScale CPU having VFP so we can use the same bits in the
-- 
2.34.1

M-profile CPUs generally allow configuration of the number of MPU
regions that they have.  We don't currently model this, so our
implementations of some of the board models provide CPUs with the
wrong number of regions.  RTOSes like Zephyr that hardcode the
expected number of regions may therefore not run on the model if they
are set up to run on real hardware.

Add properties mpu-ns-regions and mpu-s-regions to the ARMV7M object,
matching the ability of hardware to configure the number of Secure
and NonSecure regions separately.  Our actual CPU implementation
doesn't currently support that, and it happens that none of the MPS
boards we model set the number of regions differently for Secure vs
NonSecure, so we provide an interface to the boards and SoCs that
won't need to change if we ever do add that functionality in future,
but make it an error to configure the two properties to different
values.

(The property name on the CPU is the somewhat misnamed-for-M-profile
"pmsav7-dregion", so we don't follow that naming convention for
the properties here. The TRM doesn't say what the CPU configuration
variable names are, so we pick something, and follow the lowercase
convention we already have for properties here.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230724174335.2150499-3-peter.maydell@linaro.org
---
 include/hw/arm/armv7m.h |  8 ++++++++
 hw/arm/armv7m.c         | 21 +++++++++++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/armv7m.h
+++ b/include/hw/arm/armv7m.h
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M)
  * + Property "vfp": enable VFP (forwarded to CPU object)
  * + Property "dsp": enable DSP (forwarded to CPU object)
  * + Property "enable-bitband": expose bitbanded IO
+ * + Property "mpu-ns-regions": number of Non-Secure MPU regions (forwarded
+ *   to CPU object pmsav7-dregion property; default is whatever the default
+ *   for the CPU is)
+ * + Property "mpu-s-regions": number of Secure MPU regions (default is
+ *   whatever the default for the CPU is; must currently be set to the same
+ *   value as mpu-ns-regions if the CPU implements the Security Extension)
  * + Clock input "refclk" is the external reference clock for the systick timers
  * + Clock input "cpuclk" is the main CPU clock
  */
@@ -XXX,XX +XXX,XX @@ struct ARMv7MState {
     Object *idau;
     uint32_t init_svtor;
     uint32_t init_nsvtor;
+    uint32_t mpu_ns_regions;
+    uint32_t mpu_s_regions;
     bool enable_bitband;
     bool start_powered_off;
     bool vfp;
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
         }
     }
 
+    /*
+     * Real M-profile hardware can be configured with a different number of
+     * MPU regions for Secure vs NonSecure. QEMU's CPU implementation doesn't
+     * support that yet, so catch attempts to select that.
+     */
+    if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
+        s->mpu_ns_regions != s->mpu_s_regions) {
+        error_setg(errp,
+                   "mpu-ns-regions and mpu-s-regions properties must have the same value");
+        return;
+    }
+    if (s->mpu_ns_regions != UINT_MAX &&
+        object_property_find(OBJECT(s->cpu), "pmsav7-dregion")) {
+        if (!object_property_set_uint(OBJECT(s->cpu), "pmsav7-dregion",
+                                      s->mpu_ns_regions, errp)) {
+            return;
+        }
+    }
+
     /*
      * Tell the CPU where the NVIC is; it will fail realize if it doesn't
      * have one. Similarly, tell the NVIC where its CPU is.
@@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = {
                      false),
     DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true),
     DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true),
+    DEFINE_PROP_UINT32("mpu-ns-regions", ARMv7MState, mpu_ns_regions, UINT_MAX),
+    DEFINE_PROP_UINT32("mpu-s-regions", ARMv7MState, mpu_s_regions, UINT_MAX),
     DEFINE_PROP_END_OF_LIST(),
 };
 
-- 
2.34.1

The IoTKit, SSE200 and SSE300 all default to 8 MPU regions.  The
MPS2/MPS3 FPGA images don't override these except in the case of
AN547, which uses 16 MPU regions.

Define properties on the ARMSSE object for the MPU regions (using the
same names as the documented RTL configuration settings, and
following the pattern we already have for this device of using
all-caps names as the RTL does), and set them in the board code.

We don't actually need to override the default except on AN547,
but it's simpler code to have the board code set them always
rather than tracking which board subtypes want to set them to
a non-default value separately from what that value is.

Tho overall effect is that for mps2-an505, mps2-an521 and mps3-an524
we now correctly use 8 MPU regions, while mps3-an547 stays at its
current 16 regions.

It's possible some guest code wrongly depended on the previous
incorrectly modeled number of memory regions. (Such guest code
should ideally check the number of regions via the MPU_TYPE
register.) The old behaviour can be obtained with additional
-global arguments to QEMU:

For mps2-an521 and mps2-an524:
 -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 -global sse-200.CPU1_MPU_NS=16 -global sse-200.CPU1_MPU_S=16

For mps2-an505:
 -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16

NB that the way the implementation allows this use of -global
is slightly fragile: if the board code explicitly sets the
properties on the sse-200 object, this overrides the -global
command line option. So we rely on:
 - the boards that need fixing all happen to use the SSE defaults
 - we can write the board code to only set the property if it
   is different from the default, rather than having all boards
   explicitly set the property
 - the board that does need to use a non-default value happens
   to need to set it to the same value (16) we previously used
This works, but there are some kinds of refactoring of the
mps2-tz.c code that would break the support for -global here.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1772
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230724174335.2150499-4-peter.maydell@linaro.org
---
 include/hw/arm/armsse.h |  5 +++++
 hw/arm/armsse.c         | 16 ++++++++++++++++
 hw/arm/mps2-tz.c        | 29 +++++++++++++++++++++++++++++
 3 files changed, 50 insertions(+)

diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/armsse.h
+++ b/include/hw/arm/armsse.h
@@ -XXX,XX +XXX,XX @@
  *    (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an
  *    SSE-200 both are present; CPU0 in an SSE-200 has neither.
  *    Since the IoTKit has only one CPU, it does not have the CPU1_* properties.
+ *  + QOM properties "CPU0_MPU_NS", "CPU0_MPU_S", "CPU1_MPU_NS" and "CPU1_MPU_S"
+ *    which set the number of MPU regions on the CPUs. If there is only one
+ *    CPU the CPU1 properties are not present.
  *  + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
  *    which are wired to its NVIC lines 32 .. n+32
  *  + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for
@@ -XXX,XX +XXX,XX @@ struct ARMSSE {
     uint32_t exp_numirq;
     uint32_t sram_addr_width;
     uint32_t init_svtor;
+    uint32_t cpu_mpu_ns[SSE_MAX_CPUS];
+    uint32_t cpu_mpu_s[SSE_MAX_CPUS];
     bool cpu_fpu[SSE_MAX_CPUS];
     bool cpu_dsp[SSE_MAX_CPUS];
 };
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -XXX,XX +XXX,XX @@ static Property iotkit_properties[] = {
     DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
     DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
     DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
+    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
+    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
     DEFINE_PROP_END_OF_LIST()
 };
 
@@ -XXX,XX +XXX,XX @@ static Property sse200_properties[] = {
     DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false),
     DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true),
     DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true),
+    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
+    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
+    DEFINE_PROP_UINT32("CPU1_MPU_NS", ARMSSE, cpu_mpu_ns[1], 8),
+    DEFINE_PROP_UINT32("CPU1_MPU_S", ARMSSE, cpu_mpu_s[1], 8),
     DEFINE_PROP_END_OF_LIST()
 };
 
@@ -XXX,XX +XXX,XX @@ static Property sse300_properties[] = {
     DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
     DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
     DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
+    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
+    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
     DEFINE_PROP_END_OF_LIST()
 };
 
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
                 return;
             }
         }
+        if (!object_property_set_uint(cpuobj, "mpu-ns-regions",
+                                      s->cpu_mpu_ns[i], errp)) {
+            return;
+        }
+        if (!object_property_set_uint(cpuobj, "mpu-s-regions",
+                                      s->cpu_mpu_s[i], errp)) {
+            return;
+        }
 
         if (i > 0) {
             memory_region_add_subregion_overlap(&s->cpu_container[i], 0,
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass {
     int uart_overflow_irq; /* number of the combined UART overflow IRQ */
     uint32_t init_svtor; /* init-svtor setting for SSE */
     uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */
+    uint32_t cpu0_mpu_ns; /* CPU0_MPU_NS setting for SSE */
+    uint32_t cpu0_mpu_s; /* CPU0_MPU_S setting for SSE */
+    uint32_t cpu1_mpu_ns; /* CPU1_MPU_NS setting for SSE */
+    uint32_t cpu1_mpu_s; /* CPU1_MPU_S setting for SSE */
     const RAMInfo *raminfo;
     const char *armsse_type;
     uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
 #define MPS3_DDR_SIZE (2 * GiB)
 #endif
 
+/* For cpu{0,1}_mpu_{ns,s}, means "leave at SSE's default value" */
+#define MPU_REGION_DEFAULT UINT32_MAX
+
 static const uint32_t an505_oscclk[] = {
     40000000,
     24580000,
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
                              OBJECT(system_memory), &error_abort);
     qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq);
     qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor);
+    if (mmc->cpu0_mpu_ns != MPU_REGION_DEFAULT) {
+        qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_NS", mmc->cpu0_mpu_ns);
+    }
+    if (mmc->cpu0_mpu_s != MPU_REGION_DEFAULT) {
+        qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_S", mmc->cpu0_mpu_s);
+    }
+    if (object_property_find(OBJECT(iotkitdev), "CPU1_MPU_NS")) {
+        if (mmc->cpu1_mpu_ns != MPU_REGION_DEFAULT) {
+            qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_NS", mmc->cpu1_mpu_ns);
+        }
+        if (mmc->cpu1_mpu_s != MPU_REGION_DEFAULT) {
+            qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_S", mmc->cpu1_mpu_s);
+        }
+    }
     qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
     qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
     qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
@@ -XXX,XX +XXX,XX @@ static void mps2tz_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
     IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc);
+    MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
 
     mc->init = mps2tz_common_init;
     mc->reset = mps2_machine_reset;
     iic->check = mps2_tz_idau_check;
+
+    /* Most machines leave these at the SSE defaults */
+    mmc->cpu0_mpu_ns = MPU_REGION_DEFAULT;
+    mmc->cpu0_mpu_s = MPU_REGION_DEFAULT;
+    mmc->cpu1_mpu_ns = MPU_REGION_DEFAULT;
+    mmc->cpu1_mpu_s = MPU_REGION_DEFAULT;
 }
 
 static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc)
@@ -XXX,XX +XXX,XX @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data)
     mmc->numirq = 96;
     mmc->uart_overflow_irq = 48;
     mmc->init_svtor = 0x00000000;
+    mmc->cpu0_mpu_s = mmc->cpu0_mpu_ns = 16;
     mmc->sram_addr_width = 21;
     mmc->raminfo = an547_raminfo;
     mmc->armsse_type = TYPE_SSE300;
-- 
2.34.1