1 | The following changes since commit 4cc10cae64c51e17844dc4358481c393d7bf1ed4: | 1 | First arm pullreq for 7.1. The bulk of this is the qemu_split_irq |
---|---|---|---|
2 | removal. | ||
2 | 3 | ||
3 | Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging (2021-05-06 18:56:17 +0100) | 4 | I have enough stuff in my to-review queue that I expect to do another |
5 | pullreq early next week, but 31 patches is enough to not hang on to. | ||
6 | |||
7 | thanks | ||
8 | -- PMM | ||
9 | |||
10 | The following changes since commit 9c125d17e9402c232c46610802e5931b3639d77b: | ||
11 | |||
12 | Merge tag 'pull-tcg-20220420' of https://gitlab.com/rth7680/qemu into staging (2022-04-20 16:43:11 -0700) | ||
4 | 13 | ||
5 | are available in the Git repository at: | 14 | are available in the Git repository at: |
6 | 15 | ||
7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210510 | 16 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220421 |
8 | 17 | ||
9 | for you to fetch changes up to 8f96812baa53005f32aece3e30b140826c20aa19: | 18 | for you to fetch changes up to 5b415dd61bdbf61fb4be0e9f1a7172b8bce682c6: |
10 | 19 | ||
11 | hw/arm/xlnx: Fix PHY address for xilinx-zynq-a9 (2021-05-10 13:24:09 +0100) | 20 | hw/arm: Use bit fields for NPCM7XX PWRON STRAPs (2022-04-21 11:37:05 +0100) |
12 | 21 | ||
13 | ---------------------------------------------------------------- | 22 | ---------------------------------------------------------------- |
14 | target-arm queue: | 23 | target-arm queue: |
15 | * docs: fix link in sbsa description | 24 | * hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF |
16 | * linux-user/aarch64: Enable hwcap for RND, BTI, and MTE | 25 | * versal: Add the Cortex-R5s in the Real-Time Processing Unit (RPU) subsystem |
17 | * target/arm: Fix tlbbits calculation in tlbi_aa64_vae2is_write() | 26 | * versal: model enough of the Clock/Reset Low-power domain (CRL) to allow control of the Cortex-R5s |
18 | * target/arm: Split neon and vfp translation to their own | 27 | * xlnx-zynqmp: Connect 4 TTC timers |
19 | compilation units | 28 | * exynos4210: Refactor GIC/combiner code to stop using qemu_split_irq |
20 | * target/arm: Make WFI a NOP for userspace emulators | 29 | * realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ' |
21 | * hw/sd/omap_mmc: Use device_cold_reset() instead of | 30 | * stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ' |
22 | device_legacy_reset() | 31 | * hw/core/irq: remove unused 'qemu_irq_split' function |
23 | * include: More fixes for 'extern "C"' block use | 32 | * npcm7xx: use symbolic constants for PWRON STRAP bit fields |
24 | * hw/arm/imx25_pdk: Fix error message for invalid RAM size | 33 | * virt: document impact of gic-version on max CPUs |
25 | * hw/arm/mps2-tz: Implement AN524 memory remapping via machine property | ||
26 | * hw/arm/xlnx: Fix PHY address for xilinx-zynq-a9 | ||
27 | 34 | ||
28 | ---------------------------------------------------------------- | 35 | ---------------------------------------------------------------- |
29 | Alex Bennée (1): | 36 | Edgar E. Iglesias (6): |
30 | docs: fix link in sbsa description | 37 | timer: cadence_ttc: Break out header file to allow embedding |
38 | hw/arm/xlnx-zynqmp: Connect 4 TTC timers | ||
39 | hw/arm: versal: Create an APU CPU Cluster | ||
40 | hw/arm: versal: Add the Cortex-R5Fs | ||
41 | hw/misc: Add a model of the Xilinx Versal CRL | ||
42 | hw/arm: versal: Connect the CRL | ||
31 | 43 | ||
32 | Guenter Roeck (1): | 44 | Hao Wu (2): |
33 | hw/arm/xlnx: Fix PHY address for xilinx-zynq-a9 | 45 | hw/misc: Add PWRON STRAP bit fields in GCR module |
46 | hw/arm: Use bit fields for NPCM7XX PWRON STRAPs | ||
34 | 47 | ||
35 | Peter Maydell (22): | 48 | Heinrich Schuchardt (1): |
36 | target/arm: Fix tlbbits calculation in tlbi_aa64_vae2is_write() | 49 | hw/arm/virt: impact of gic-version on max CPUs |
37 | target/arm: Move constant expanders to translate.h | ||
38 | target/arm: Share unallocated_encoding() and gen_exception_insn() | ||
39 | target/arm: Make functions used by m-nocp global | ||
40 | target/arm: Split m-nocp trans functions into their own file | ||
41 | target/arm: Move gen_aa32 functions to translate-a32.h | ||
42 | target/arm: Move vfp_{load, store}_reg{32, 64} to translate-vfp.c.inc | ||
43 | target/arm: Make functions used by translate-vfp global | ||
44 | target/arm: Make translate-vfp.c.inc its own compilation unit | ||
45 | target/arm: Move vfp_reg_ptr() to translate-neon.c.inc | ||
46 | target/arm: Delete unused typedef | ||
47 | target/arm: Move NeonGenThreeOpEnvFn typedef to translate.h | ||
48 | target/arm: Make functions used by translate-neon global | ||
49 | target/arm: Make translate-neon.c.inc its own compilation unit | ||
50 | target/arm: Make WFI a NOP for userspace emulators | ||
51 | hw/sd/omap_mmc: Use device_cold_reset() instead of device_legacy_reset() | ||
52 | osdep: Make os-win32.h and os-posix.h handle 'extern "C"' themselves | ||
53 | include/qemu/bswap.h: Handle being included outside extern "C" block | ||
54 | include/disas/dis-asm.h: Handle being included outside 'extern "C"' | ||
55 | hw/misc/mps2-scc: Add "QEMU interface" comment | ||
56 | hw/misc/mps2-scc: Support using CFG0 bit 0 for remapping | ||
57 | hw/arm/mps2-tz: Implement AN524 memory remapping via machine property | ||
58 | 50 | ||
59 | Philippe Mathieu-Daudé (1): | 51 | Peter Maydell (19): |
60 | hw/arm/imx25_pdk: Fix error message for invalid RAM size | 52 | hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF |
53 | hw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom OR-gate device | ||
54 | hw/intc/exynos4210_gic: Remove unused TYPE_EXYNOS4210_IRQ_GATE | ||
55 | hw/arm/exynos4210: Put a9mpcore device into state struct | ||
56 | hw/arm/exynos4210: Drop int_gic_irq[] from Exynos4210Irq struct | ||
57 | hw/arm/exynos4210: Coalesce board_irqs and irq_table | ||
58 | hw/arm/exynos4210: Fix code style nit in combiner_grp_to_gic_id[] | ||
59 | hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.c | ||
60 | hw/arm/exynos4210: Put external GIC into state struct | ||
61 | hw/arm/exynos4210: Drop ext_gic_irq[] from Exynos4210Irq struct | ||
62 | hw/arm/exynos4210: Move exynos4210_combiner_get_gpioin() into exynos4210.c | ||
63 | hw/arm/exynos4210: Delete unused macro definitions | ||
64 | hw/arm/exynos4210: Use TYPE_SPLIT_IRQ in exynos4210_init_board_irqs() | ||
65 | hw/arm/exynos4210: Fill in irq_table[] for internal-combiner-only IRQ lines | ||
66 | hw/arm/exynos4210: Connect MCT_G0 and MCT_G1 to both combiners | ||
67 | hw/arm/exynos4210: Don't connect multiple lines to external GIC inputs | ||
68 | hw/arm/exynos4210: Fold combiner splits into exynos4210_init_board_irqs() | ||
69 | hw/arm/exynos4210: Put combiners into state struct | ||
70 | hw/arm/exynos4210: Drop Exynos4210Irq struct | ||
61 | 71 | ||
62 | Richard Henderson (1): | 72 | Zongyuan Li (3): |
63 | linux-user/aarch64: Enable hwcap for RND, BTI, and MTE | 73 | hw/arm/realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ' |
74 | hw/arm/stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ' | ||
75 | hw/core/irq: remove unused 'qemu_irq_split' function | ||
64 | 76 | ||
65 | docs/system/arm/mps2.rst | 10 + | 77 | docs/system/arm/virt.rst | 4 +- |
66 | docs/system/arm/sbsa.rst | 2 +- | 78 | include/hw/arm/exynos4210.h | 50 ++-- |
67 | include/disas/dis-asm.h | 12 +- | 79 | include/hw/arm/xlnx-versal.h | 16 ++ |
68 | include/hw/misc/mps2-scc.h | 21 ++ | 80 | include/hw/arm/xlnx-zynqmp.h | 4 + |
69 | include/qemu/bswap.h | 26 ++- | 81 | include/hw/intc/exynos4210_combiner.h | 57 +++++ |
70 | include/qemu/osdep.h | 8 +- | 82 | include/hw/intc/exynos4210_gic.h | 43 ++++ |
71 | include/sysemu/os-posix.h | 8 + | 83 | include/hw/irq.h | 5 - |
72 | include/sysemu/os-win32.h | 8 + | 84 | include/hw/misc/npcm7xx_gcr.h | 30 +++ |
73 | target/arm/translate-a32.h | 144 +++++++++++++ | 85 | include/hw/misc/xlnx-versal-crl.h | 235 +++++++++++++++++++ |
74 | target/arm/translate-a64.h | 2 - | 86 | include/hw/timer/cadence_ttc.h | 54 +++++ |
75 | target/arm/translate.h | 29 +++ | 87 | hw/arm/exynos4210.c | 430 ++++++++++++++++++++++++++++++---- |
76 | hw/arm/imx25_pdk.c | 5 +- | 88 | hw/arm/npcm7xx_boards.c | 24 +- |
77 | hw/arm/mps2-tz.c | 108 +++++++++- | 89 | hw/arm/realview.c | 33 ++- |
78 | hw/arm/xilinx_zynq.c | 2 +- | 90 | hw/arm/stellaris.c | 15 +- |
79 | hw/misc/mps2-scc.c | 13 +- | 91 | hw/arm/virt.c | 7 + |
80 | hw/sd/omap_mmc.c | 2 +- | 92 | hw/arm/xlnx-versal-virt.c | 6 +- |
81 | linux-user/elfload.c | 13 ++ | 93 | hw/arm/xlnx-versal.c | 99 +++++++- |
82 | target/arm/helper.c | 2 +- | 94 | hw/arm/xlnx-zynqmp.c | 22 ++ |
83 | target/arm/op_helper.c | 12 ++ | 95 | hw/core/irq.c | 15 -- |
84 | target/arm/translate-a64.c | 15 -- | 96 | hw/intc/exynos4210_combiner.c | 108 +-------- |
85 | target/arm/translate-m-nocp.c | 221 ++++++++++++++++++++ | 97 | hw/intc/exynos4210_gic.c | 344 +-------------------------- |
86 | .../arm/{translate-neon.c.inc => translate-neon.c} | 19 +- | 98 | hw/misc/xlnx-versal-crl.c | 421 +++++++++++++++++++++++++++++++++ |
87 | .../arm/{translate-vfp.c.inc => translate-vfp.c} | 230 +++------------------ | 99 | hw/timer/cadence_ttc.c | 32 +-- |
88 | target/arm/translate.c | 200 ++++-------------- | 100 | MAINTAINERS | 2 +- |
89 | disas/arm-a64.cc | 2 - | 101 | hw/misc/meson.build | 1 + |
90 | disas/nanomips.cpp | 2 - | 102 | 25 files changed, 1457 insertions(+), 600 deletions(-) |
91 | target/arm/meson.build | 15 +- | 103 | create mode 100644 include/hw/intc/exynos4210_combiner.h |
92 | 27 files changed, 718 insertions(+), 413 deletions(-) | 104 | create mode 100644 include/hw/intc/exynos4210_gic.h |
93 | create mode 100644 target/arm/translate-a32.h | 105 | create mode 100644 include/hw/misc/xlnx-versal-crl.h |
94 | create mode 100644 target/arm/translate-m-nocp.c | 106 | create mode 100644 include/hw/timer/cadence_ttc.h |
95 | rename target/arm/{translate-neon.c.inc => translate-neon.c} (99%) | 107 | create mode 100644 hw/misc/xlnx-versal-crl.c |
96 | rename target/arm/{translate-vfp.c.inc => translate-vfp.c} (94%) | ||
97 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | It's not possible to provide the guest with the Security extensions | ||
2 | (TrustZone) when using KVM or HVF, because the hardware | ||
3 | virtualization extensions don't permit running EL3 guest code. | ||
4 | However, we weren't checking for this combination, with the result | ||
5 | that QEMU would assert if you tried it: | ||
1 | 6 | ||
7 | $ qemu-system-aarch64 -enable-kvm -machine virt,secure=on -cpu host -display none | ||
8 | Unexpected error in object_property_find_err() at ../../qom/object.c:1304: | ||
9 | qemu-system-aarch64: Property 'host-arm-cpu.secure-memory' not found | ||
10 | Aborted | ||
11 | |||
12 | Check for this combination of options and report an error, in the | ||
13 | same way we already do for attempts to give a KVM or HVF guest the | ||
14 | Virtualization or MTE extensions. Now we will report: | ||
15 | |||
16 | qemu-system-aarch64: mach-virt: KVM does not support providing Security extensions (TrustZone) to the guest CPU | ||
17 | |||
18 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/961 | ||
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
20 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
21 | Message-id: 20220404155301.566542-1-peter.maydell@linaro.org | ||
22 | --- | ||
23 | hw/arm/virt.c | 7 +++++++ | ||
24 | 1 file changed, 7 insertions(+) | ||
25 | |||
26 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/hw/arm/virt.c | ||
29 | +++ b/hw/arm/virt.c | ||
30 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | ||
31 | exit(1); | ||
32 | } | ||
33 | |||
34 | + if (vms->secure && (kvm_enabled() || hvf_enabled())) { | ||
35 | + error_report("mach-virt: %s does not support providing " | ||
36 | + "Security extensions (TrustZone) to the guest CPU", | ||
37 | + kvm_enabled() ? "KVM" : "HVF"); | ||
38 | + exit(1); | ||
39 | + } | ||
40 | + | ||
41 | if (vms->virt && (kvm_enabled() || hvf_enabled())) { | ||
42 | error_report("mach-virt: %s does not support providing " | ||
43 | "Virtualization extensions to the guest CPU", | ||
44 | -- | ||
45 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: "Edgar E. Iglesias" <edgar.iglesias@amd.com> | ||
1 | 2 | ||
3 | Break out header file to allow embedding of the the TTC. | ||
4 | |||
5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> | ||
6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
7 | Reviewed-by: Luc Michel <luc@lmichel.fr> | ||
8 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> | ||
9 | Message-id: 20220331222017.2914409-2-edgar.iglesias@gmail.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | include/hw/timer/cadence_ttc.h | 54 ++++++++++++++++++++++++++++++++++ | ||
13 | hw/timer/cadence_ttc.c | 32 ++------------------ | ||
14 | 2 files changed, 56 insertions(+), 30 deletions(-) | ||
15 | create mode 100644 include/hw/timer/cadence_ttc.h | ||
16 | |||
17 | diff --git a/include/hw/timer/cadence_ttc.h b/include/hw/timer/cadence_ttc.h | ||
18 | new file mode 100644 | ||
19 | index XXXXXXX..XXXXXXX | ||
20 | --- /dev/null | ||
21 | +++ b/include/hw/timer/cadence_ttc.h | ||
22 | @@ -XXX,XX +XXX,XX @@ | ||
23 | +/* | ||
24 | + * Xilinx Zynq cadence TTC model | ||
25 | + * | ||
26 | + * Copyright (c) 2011 Xilinx Inc. | ||
27 | + * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) | ||
28 | + * Copyright (c) 2012 PetaLogix Pty Ltd. | ||
29 | + * Written By Haibing Ma | ||
30 | + * M. Habib | ||
31 | + * | ||
32 | + * This program is free software; you can redistribute it and/or | ||
33 | + * modify it under the terms of the GNU General Public License | ||
34 | + * as published by the Free Software Foundation; either version | ||
35 | + * 2 of the License, or (at your option) any later version. | ||
36 | + * | ||
37 | + * You should have received a copy of the GNU General Public License along | ||
38 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
39 | + */ | ||
40 | +#ifndef HW_TIMER_CADENCE_TTC_H | ||
41 | +#define HW_TIMER_CADENCE_TTC_H | ||
42 | + | ||
43 | +#include "hw/sysbus.h" | ||
44 | +#include "qemu/timer.h" | ||
45 | + | ||
46 | +typedef struct { | ||
47 | + QEMUTimer *timer; | ||
48 | + int freq; | ||
49 | + | ||
50 | + uint32_t reg_clock; | ||
51 | + uint32_t reg_count; | ||
52 | + uint32_t reg_value; | ||
53 | + uint16_t reg_interval; | ||
54 | + uint16_t reg_match[3]; | ||
55 | + uint32_t reg_intr; | ||
56 | + uint32_t reg_intr_en; | ||
57 | + uint32_t reg_event_ctrl; | ||
58 | + uint32_t reg_event; | ||
59 | + | ||
60 | + uint64_t cpu_time; | ||
61 | + unsigned int cpu_time_valid; | ||
62 | + | ||
63 | + qemu_irq irq; | ||
64 | +} CadenceTimerState; | ||
65 | + | ||
66 | +#define TYPE_CADENCE_TTC "cadence_ttc" | ||
67 | +OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC) | ||
68 | + | ||
69 | +struct CadenceTTCState { | ||
70 | + SysBusDevice parent_obj; | ||
71 | + | ||
72 | + MemoryRegion iomem; | ||
73 | + CadenceTimerState timer[3]; | ||
74 | +}; | ||
75 | + | ||
76 | +#endif | ||
77 | diff --git a/hw/timer/cadence_ttc.c b/hw/timer/cadence_ttc.c | ||
78 | index XXXXXXX..XXXXXXX 100644 | ||
79 | --- a/hw/timer/cadence_ttc.c | ||
80 | +++ b/hw/timer/cadence_ttc.c | ||
81 | @@ -XXX,XX +XXX,XX @@ | ||
82 | #include "qemu/timer.h" | ||
83 | #include "qom/object.h" | ||
84 | |||
85 | +#include "hw/timer/cadence_ttc.h" | ||
86 | + | ||
87 | #ifdef CADENCE_TTC_ERR_DEBUG | ||
88 | #define DB_PRINT(...) do { \ | ||
89 | fprintf(stderr, ": %s: ", __func__); \ | ||
90 | @@ -XXX,XX +XXX,XX @@ | ||
91 | #define CLOCK_CTRL_PS_EN 0x00000001 | ||
92 | #define CLOCK_CTRL_PS_V 0x0000001e | ||
93 | |||
94 | -typedef struct { | ||
95 | - QEMUTimer *timer; | ||
96 | - int freq; | ||
97 | - | ||
98 | - uint32_t reg_clock; | ||
99 | - uint32_t reg_count; | ||
100 | - uint32_t reg_value; | ||
101 | - uint16_t reg_interval; | ||
102 | - uint16_t reg_match[3]; | ||
103 | - uint32_t reg_intr; | ||
104 | - uint32_t reg_intr_en; | ||
105 | - uint32_t reg_event_ctrl; | ||
106 | - uint32_t reg_event; | ||
107 | - | ||
108 | - uint64_t cpu_time; | ||
109 | - unsigned int cpu_time_valid; | ||
110 | - | ||
111 | - qemu_irq irq; | ||
112 | -} CadenceTimerState; | ||
113 | - | ||
114 | -#define TYPE_CADENCE_TTC "cadence_ttc" | ||
115 | -OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC) | ||
116 | - | ||
117 | -struct CadenceTTCState { | ||
118 | - SysBusDevice parent_obj; | ||
119 | - | ||
120 | - MemoryRegion iomem; | ||
121 | - CadenceTimerState timer[3]; | ||
122 | -}; | ||
123 | - | ||
124 | static void cadence_timer_update(CadenceTimerState *s) | ||
125 | { | ||
126 | qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en)); | ||
127 | -- | ||
128 | 2.25.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: "Edgar E. Iglesias" <edgar.iglesias@amd.com> | ||
1 | 2 | ||
3 | Connect the 4 TTC timers on the ZynqMP. | ||
4 | |||
5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> | ||
6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
7 | Reviewed-by: Luc Michel <luc@lmichel.fr> | ||
8 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> | ||
9 | Message-id: 20220331222017.2914409-3-edgar.iglesias@gmail.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | include/hw/arm/xlnx-zynqmp.h | 4 ++++ | ||
13 | hw/arm/xlnx-zynqmp.c | 22 ++++++++++++++++++++++ | ||
14 | 2 files changed, 26 insertions(+) | ||
15 | |||
16 | diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/include/hw/arm/xlnx-zynqmp.h | ||
19 | +++ b/include/hw/arm/xlnx-zynqmp.h | ||
20 | @@ -XXX,XX +XXX,XX @@ | ||
21 | #include "hw/or-irq.h" | ||
22 | #include "hw/misc/xlnx-zynqmp-apu-ctrl.h" | ||
23 | #include "hw/misc/xlnx-zynqmp-crf.h" | ||
24 | +#include "hw/timer/cadence_ttc.h" | ||
25 | |||
26 | #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" | ||
27 | OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) | ||
28 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) | ||
29 | #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \ | ||
30 | XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE) | ||
31 | |||
32 | +#define XLNX_ZYNQMP_NUM_TTC 4 | ||
33 | + | ||
34 | /* | ||
35 | * Unimplemented mmio regions needed to boot some images. | ||
36 | */ | ||
37 | @@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState { | ||
38 | qemu_or_irq qspi_irq_orgate; | ||
39 | XlnxZynqMPAPUCtrl apu_ctrl; | ||
40 | XlnxZynqMPCRF crf; | ||
41 | + CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC]; | ||
42 | |||
43 | char *boot_cpu; | ||
44 | ARMCPU *boot_cpu_ptr; | ||
45 | diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c | ||
46 | index XXXXXXX..XXXXXXX 100644 | ||
47 | --- a/hw/arm/xlnx-zynqmp.c | ||
48 | +++ b/hw/arm/xlnx-zynqmp.c | ||
49 | @@ -XXX,XX +XXX,XX @@ | ||
50 | #define APU_ADDR 0xfd5c0000 | ||
51 | #define APU_IRQ 153 | ||
52 | |||
53 | +#define TTC0_ADDR 0xFF110000 | ||
54 | +#define TTC0_IRQ 36 | ||
55 | + | ||
56 | #define IPI_ADDR 0xFF300000 | ||
57 | #define IPI_IRQ 64 | ||
58 | |||
59 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic) | ||
60 | sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]); | ||
61 | } | ||
62 | |||
63 | +static void xlnx_zynqmp_create_ttc(XlnxZynqMPState *s, qemu_irq *gic) | ||
64 | +{ | ||
65 | + SysBusDevice *sbd; | ||
66 | + int i, irq; | ||
67 | + | ||
68 | + for (i = 0; i < XLNX_ZYNQMP_NUM_TTC; i++) { | ||
69 | + object_initialize_child(OBJECT(s), "ttc[*]", &s->ttc[i], | ||
70 | + TYPE_CADENCE_TTC); | ||
71 | + sbd = SYS_BUS_DEVICE(&s->ttc[i]); | ||
72 | + | ||
73 | + sysbus_realize(sbd, &error_fatal); | ||
74 | + sysbus_mmio_map(sbd, 0, TTC0_ADDR + i * 0x10000); | ||
75 | + for (irq = 0; irq < 3; irq++) { | ||
76 | + sysbus_connect_irq(sbd, irq, gic[TTC0_IRQ + i * 3 + irq]); | ||
77 | + } | ||
78 | + } | ||
79 | +} | ||
80 | + | ||
81 | static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) | ||
82 | { | ||
83 | static const struct UnimpInfo { | ||
84 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) | ||
85 | xlnx_zynqmp_create_efuse(s, gic_spi); | ||
86 | xlnx_zynqmp_create_apu_ctrl(s, gic_spi); | ||
87 | xlnx_zynqmp_create_crf(s, gic_spi); | ||
88 | + xlnx_zynqmp_create_ttc(s, gic_spi); | ||
89 | xlnx_zynqmp_create_unimp_mmio(s); | ||
90 | |||
91 | for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { | ||
92 | -- | ||
93 | 2.25.1 | diff view generated by jsdifflib |
1 | The omap_mmc_reset() function resets its SD card via | 1 | From: "Edgar E. Iglesias" <edgar.iglesias@amd.com> |
---|---|---|---|
2 | device_legacy_reset(). We know that the SD card does not have a qbus | ||
3 | of its own, so the new device_cold_reset() function (which resets | ||
4 | both the device and its child buses) is equivalent here to | ||
5 | device_legacy_reset() and we can just switch to the new API. | ||
6 | 2 | ||
3 | Create an APU CPU Cluster. This is in preparation to add the RPU. | ||
4 | |||
5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> | ||
6 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | ||
7 | Message-id: 20220406174303.2022038-2-edgar.iglesias@xilinx.com | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Message-id: 20210430222348.8514-1-peter.maydell@linaro.org | ||
10 | --- | 9 | --- |
11 | hw/sd/omap_mmc.c | 2 +- | 10 | include/hw/arm/xlnx-versal.h | 2 ++ |
12 | 1 file changed, 1 insertion(+), 1 deletion(-) | 11 | hw/arm/xlnx-versal.c | 9 ++++++++- |
12 | 2 files changed, 10 insertions(+), 1 deletion(-) | ||
13 | 13 | ||
14 | diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c | 14 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h |
15 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/sd/omap_mmc.c | 16 | --- a/include/hw/arm/xlnx-versal.h |
17 | +++ b/hw/sd/omap_mmc.c | 17 | +++ b/include/hw/arm/xlnx-versal.h |
18 | @@ -XXX,XX +XXX,XX @@ void omap_mmc_reset(struct omap_mmc_s *host) | 18 | @@ -XXX,XX +XXX,XX @@ |
19 | * into any bus, and we must reset it manually. When omap_mmc is | 19 | |
20 | * QOMified this must move into the QOM reset function. | 20 | #include "hw/sysbus.h" |
21 | */ | 21 | #include "hw/arm/boot.h" |
22 | - device_legacy_reset(DEVICE(host->card)); | 22 | +#include "hw/cpu/cluster.h" |
23 | + device_cold_reset(DEVICE(host->card)); | 23 | #include "hw/or-irq.h" |
24 | #include "hw/sd/sdhci.h" | ||
25 | #include "hw/intc/arm_gicv3.h" | ||
26 | @@ -XXX,XX +XXX,XX @@ struct Versal { | ||
27 | struct { | ||
28 | struct { | ||
29 | MemoryRegion mr; | ||
30 | + CPUClusterState cluster; | ||
31 | ARMCPU cpu[XLNX_VERSAL_NR_ACPUS]; | ||
32 | GICv3State gic; | ||
33 | } apu; | ||
34 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/hw/arm/xlnx-versal.c | ||
37 | +++ b/hw/arm/xlnx-versal.c | ||
38 | @@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s) | ||
39 | { | ||
40 | int i; | ||
41 | |||
42 | + object_initialize_child(OBJECT(s), "apu-cluster", &s->fpd.apu.cluster, | ||
43 | + TYPE_CPU_CLUSTER); | ||
44 | + qdev_prop_set_uint32(DEVICE(&s->fpd.apu.cluster), "cluster-id", 0); | ||
45 | + | ||
46 | for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) { | ||
47 | Object *obj; | ||
48 | |||
49 | - object_initialize_child(OBJECT(s), "apu-cpu[*]", &s->fpd.apu.cpu[i], | ||
50 | + object_initialize_child(OBJECT(&s->fpd.apu.cluster), | ||
51 | + "apu-cpu[*]", &s->fpd.apu.cpu[i], | ||
52 | XLNX_VERSAL_ACPU_TYPE); | ||
53 | obj = OBJECT(&s->fpd.apu.cpu[i]); | ||
54 | if (i) { | ||
55 | @@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s) | ||
56 | &error_abort); | ||
57 | qdev_realize(DEVICE(obj), NULL, &error_fatal); | ||
58 | } | ||
59 | + | ||
60 | + qdev_realize(DEVICE(&s->fpd.apu.cluster), NULL, &error_fatal); | ||
24 | } | 61 | } |
25 | 62 | ||
26 | static uint64_t omap_mmc_read(void *opaque, hwaddr offset, | 63 | static void versal_create_apu_gic(Versal *s, qemu_irq *pic) |
27 | -- | 64 | -- |
28 | 2.20.1 | 65 | 2.25.1 |
29 | |||
30 | diff view generated by jsdifflib |
1 | Make the remaining functions needed by the translate-neon code | 1 | From: "Edgar E. Iglesias" <edgar.iglesias@amd.com> |
---|---|---|---|
2 | global. | ||
3 | 2 | ||
3 | Add the Cortex-R5Fs of the Versal RPU (Real-time Processing Unit) | ||
4 | subsystem. | ||
5 | |||
6 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> | ||
7 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | ||
8 | Message-id: 20220406174303.2022038-3-edgar.iglesias@xilinx.com | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20210430132740.10391-13-peter.maydell@linaro.org | ||
8 | --- | 10 | --- |
9 | target/arm/translate-a32.h | 8 ++++++++ | 11 | include/hw/arm/xlnx-versal.h | 10 ++++++++++ |
10 | target/arm/translate.c | 10 ++-------- | 12 | hw/arm/xlnx-versal-virt.c | 6 +++--- |
11 | 2 files changed, 10 insertions(+), 8 deletions(-) | 13 | hw/arm/xlnx-versal.c | 36 ++++++++++++++++++++++++++++++++++++ |
14 | 3 files changed, 49 insertions(+), 3 deletions(-) | ||
12 | 15 | ||
13 | diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h | 16 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h |
14 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/translate-a32.h | 18 | --- a/include/hw/arm/xlnx-versal.h |
16 | +++ b/target/arm/translate-a32.h | 19 | +++ b/include/hw/arm/xlnx-versal.h |
17 | @@ -XXX,XX +XXX,XX @@ void gen_set_pc_im(DisasContext *s, target_ulong val); | 20 | @@ -XXX,XX +XXX,XX @@ |
18 | void gen_lookup_tb(DisasContext *s); | 21 | OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) |
19 | long vfp_reg_offset(bool dp, unsigned reg); | 22 | |
20 | long neon_full_reg_offset(unsigned reg); | 23 | #define XLNX_VERSAL_NR_ACPUS 2 |
21 | +long neon_element_offset(int reg, int element, MemOp memop); | 24 | +#define XLNX_VERSAL_NR_RCPUS 2 |
22 | +void gen_rev16(TCGv_i32 dest, TCGv_i32 var); | 25 | #define XLNX_VERSAL_NR_UARTS 2 |
23 | 26 | #define XLNX_VERSAL_NR_GEMS 2 | |
24 | static inline TCGv_i32 load_cpu_offset(int offset) | 27 | #define XLNX_VERSAL_NR_ADMAS 8 |
25 | { | 28 | @@ -XXX,XX +XXX,XX @@ struct Versal { |
26 | @@ -XXX,XX +XXX,XX @@ DO_GEN_ST(32, MO_UL) | 29 | VersalUsb2 usb; |
27 | /* Set NZCV flags from the high 4 bits of var. */ | 30 | } iou; |
28 | #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV) | 31 | |
29 | 32 | + /* Real-time Processing Unit. */ | |
30 | +/* Swap low and high halfwords. */ | 33 | + struct { |
31 | +static inline void gen_swap_half(TCGv_i32 dest, TCGv_i32 var) | 34 | + MemoryRegion mr; |
35 | + MemoryRegion mr_ps_alias; | ||
36 | + | ||
37 | + CPUClusterState cluster; | ||
38 | + ARMCPU cpu[XLNX_VERSAL_NR_RCPUS]; | ||
39 | + } rpu; | ||
40 | + | ||
41 | struct { | ||
42 | qemu_or_irq irq_orgate; | ||
43 | XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; | ||
44 | diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/hw/arm/xlnx-versal-virt.c | ||
47 | +++ b/hw/arm/xlnx-versal-virt.c | ||
48 | @@ -XXX,XX +XXX,XX @@ static void versal_virt_machine_class_init(ObjectClass *oc, void *data) | ||
49 | |||
50 | mc->desc = "Xilinx Versal Virtual development board"; | ||
51 | mc->init = versal_virt_init; | ||
52 | - mc->min_cpus = XLNX_VERSAL_NR_ACPUS; | ||
53 | - mc->max_cpus = XLNX_VERSAL_NR_ACPUS; | ||
54 | - mc->default_cpus = XLNX_VERSAL_NR_ACPUS; | ||
55 | + mc->min_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS; | ||
56 | + mc->max_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS; | ||
57 | + mc->default_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS; | ||
58 | mc->no_cdrom = true; | ||
59 | mc->default_ram_id = "ddr"; | ||
60 | } | ||
61 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/hw/arm/xlnx-versal.c | ||
64 | +++ b/hw/arm/xlnx-versal.c | ||
65 | @@ -XXX,XX +XXX,XX @@ | ||
66 | #include "hw/sysbus.h" | ||
67 | |||
68 | #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") | ||
69 | +#define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") | ||
70 | #define GEM_REVISION 0x40070106 | ||
71 | |||
72 | #define VERSAL_NUM_PMC_APB_IRQS 3 | ||
73 | @@ -XXX,XX +XXX,XX @@ static void versal_create_apu_gic(Versal *s, qemu_irq *pic) | ||
74 | } | ||
75 | } | ||
76 | |||
77 | +static void versal_create_rpu_cpus(Versal *s) | ||
32 | +{ | 78 | +{ |
33 | + tcg_gen_rotri_i32(dest, var, 16); | 79 | + int i; |
80 | + | ||
81 | + object_initialize_child(OBJECT(s), "rpu-cluster", &s->lpd.rpu.cluster, | ||
82 | + TYPE_CPU_CLUSTER); | ||
83 | + qdev_prop_set_uint32(DEVICE(&s->lpd.rpu.cluster), "cluster-id", 1); | ||
84 | + | ||
85 | + for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) { | ||
86 | + Object *obj; | ||
87 | + | ||
88 | + object_initialize_child(OBJECT(&s->lpd.rpu.cluster), | ||
89 | + "rpu-cpu[*]", &s->lpd.rpu.cpu[i], | ||
90 | + XLNX_VERSAL_RCPU_TYPE); | ||
91 | + obj = OBJECT(&s->lpd.rpu.cpu[i]); | ||
92 | + object_property_set_bool(obj, "start-powered-off", true, | ||
93 | + &error_abort); | ||
94 | + | ||
95 | + object_property_set_int(obj, "mp-affinity", 0x100 | i, &error_abort); | ||
96 | + object_property_set_int(obj, "core-count", ARRAY_SIZE(s->lpd.rpu.cpu), | ||
97 | + &error_abort); | ||
98 | + object_property_set_link(obj, "memory", OBJECT(&s->lpd.rpu.mr), | ||
99 | + &error_abort); | ||
100 | + qdev_realize(DEVICE(obj), NULL, &error_fatal); | ||
101 | + } | ||
102 | + | ||
103 | + qdev_realize(DEVICE(&s->lpd.rpu.cluster), NULL, &error_fatal); | ||
34 | +} | 104 | +} |
35 | + | 105 | + |
36 | #endif | 106 | static void versal_create_uarts(Versal *s, qemu_irq *pic) |
37 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 107 | { |
38 | index XXXXXXX..XXXXXXX 100644 | 108 | int i; |
39 | --- a/target/arm/translate.c | 109 | @@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp) |
40 | +++ b/target/arm/translate.c | 110 | |
41 | @@ -XXX,XX +XXX,XX @@ static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b) | 111 | versal_create_apu_cpus(s); |
112 | versal_create_apu_gic(s, pic); | ||
113 | + versal_create_rpu_cpus(s); | ||
114 | versal_create_uarts(s, pic); | ||
115 | versal_create_usbs(s, pic); | ||
116 | versal_create_gems(s, pic); | ||
117 | @@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp) | ||
118 | |||
119 | memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0); | ||
120 | memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0); | ||
121 | + memory_region_add_subregion_overlap(&s->lpd.rpu.mr, 0, | ||
122 | + &s->lpd.rpu.mr_ps_alias, 0); | ||
42 | } | 123 | } |
43 | 124 | ||
44 | /* Byteswap each halfword. */ | 125 | static void versal_init(Object *obj) |
45 | -static void gen_rev16(TCGv_i32 dest, TCGv_i32 var) | 126 | @@ -XXX,XX +XXX,XX @@ static void versal_init(Object *obj) |
46 | +void gen_rev16(TCGv_i32 dest, TCGv_i32 var) | 127 | Versal *s = XLNX_VERSAL(obj); |
47 | { | 128 | |
48 | TCGv_i32 tmp = tcg_temp_new_i32(); | 129 | memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX); |
49 | TCGv_i32 mask = tcg_const_i32(0x00ff00ff); | 130 | + memory_region_init(&s->lpd.rpu.mr, obj, "mr-rpu", UINT64_MAX); |
50 | @@ -XXX,XX +XXX,XX @@ static void gen_revsh(TCGv_i32 dest, TCGv_i32 var) | 131 | memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX); |
51 | tcg_gen_ext16s_i32(dest, var); | 132 | + memory_region_init_alias(&s->lpd.rpu.mr_ps_alias, OBJECT(s), |
133 | + "mr-rpu-ps-alias", &s->mr_ps, 0, UINT64_MAX); | ||
52 | } | 134 | } |
53 | 135 | ||
54 | -/* Swap low and high halfwords. */ | 136 | static Property versal_properties[] = { |
55 | -static void gen_swap_half(TCGv_i32 dest, TCGv_i32 var) | ||
56 | -{ | ||
57 | - tcg_gen_rotri_i32(dest, var, 16); | ||
58 | -} | ||
59 | - | ||
60 | /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead. | ||
61 | tmp = (t0 ^ t1) & 0x8000; | ||
62 | t0 &= ~0x8000; | ||
63 | @@ -XXX,XX +XXX,XX @@ long neon_full_reg_offset(unsigned reg) | ||
64 | * Return the offset of a 2**SIZE piece of a NEON register, at index ELE, | ||
65 | * where 0 is the least significant end of the register. | ||
66 | */ | ||
67 | -static long neon_element_offset(int reg, int element, MemOp memop) | ||
68 | +long neon_element_offset(int reg, int element, MemOp memop) | ||
69 | { | ||
70 | int element_size = 1 << (memop & MO_SIZE); | ||
71 | int ofs = element * element_size; | ||
72 | -- | 137 | -- |
73 | 2.20.1 | 138 | 2.25.1 |
74 | |||
75 | diff view generated by jsdifflib |
1 | In tlbi_aa64_vae2is_write() the calculation | 1 | From: "Edgar E. Iglesias" <edgar.iglesias@amd.com> |
---|---|---|---|
2 | bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_E2 : ARMMMUIdx_SE2, | ||
3 | pageaddr) | ||
4 | 2 | ||
5 | has the two arms of the ?: expression reversed. Fix the bug. | 3 | Add a model of the Xilinx Versal CRL. |
6 | 4 | ||
7 | Fixes: b6ad6062f1e5 | 5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> |
8 | Reported-by: Rebecca Cran <rebecca@nuviainc.com> | 6 | Reviewed-by: Frederic Konrad <fkonrad@amd.com> |
7 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | ||
8 | Message-id: 20220406174303.2022038-4-edgar.iglesias@xilinx.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
11 | Reviewed-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | ||
12 | Reviewed-by: Rebecca Cran <rebecca@nuviainc.com> | ||
13 | Message-id: 20210420123106.10861-1-peter.maydell@linaro.org | ||
14 | --- | 10 | --- |
15 | target/arm/helper.c | 2 +- | 11 | include/hw/misc/xlnx-versal-crl.h | 235 +++++++++++++++++ |
16 | 1 file changed, 1 insertion(+), 1 deletion(-) | 12 | hw/misc/xlnx-versal-crl.c | 421 ++++++++++++++++++++++++++++++ |
13 | hw/misc/meson.build | 1 + | ||
14 | 3 files changed, 657 insertions(+) | ||
15 | create mode 100644 include/hw/misc/xlnx-versal-crl.h | ||
16 | create mode 100644 hw/misc/xlnx-versal-crl.c | ||
17 | 17 | ||
18 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 18 | diff --git a/include/hw/misc/xlnx-versal-crl.h b/include/hw/misc/xlnx-versal-crl.h |
19 | new file mode 100644 | ||
20 | index XXXXXXX..XXXXXXX | ||
21 | --- /dev/null | ||
22 | +++ b/include/hw/misc/xlnx-versal-crl.h | ||
23 | @@ -XXX,XX +XXX,XX @@ | ||
24 | +/* | ||
25 | + * QEMU model of the Clock-Reset-LPD (CRL). | ||
26 | + * | ||
27 | + * Copyright (c) 2022 Xilinx Inc. | ||
28 | + * SPDX-License-Identifier: GPL-2.0-or-later | ||
29 | + * | ||
30 | + * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
31 | + */ | ||
32 | +#ifndef HW_MISC_XLNX_VERSAL_CRL_H | ||
33 | +#define HW_MISC_XLNX_VERSAL_CRL_H | ||
34 | + | ||
35 | +#include "hw/sysbus.h" | ||
36 | +#include "hw/register.h" | ||
37 | +#include "target/arm/cpu.h" | ||
38 | + | ||
39 | +#define TYPE_XLNX_VERSAL_CRL "xlnx,versal-crl" | ||
40 | +OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL) | ||
41 | + | ||
42 | +REG32(ERR_CTRL, 0x0) | ||
43 | + FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1) | ||
44 | +REG32(IR_STATUS, 0x4) | ||
45 | + FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1) | ||
46 | +REG32(IR_MASK, 0x8) | ||
47 | + FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1) | ||
48 | +REG32(IR_ENABLE, 0xc) | ||
49 | + FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1) | ||
50 | +REG32(IR_DISABLE, 0x10) | ||
51 | + FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1) | ||
52 | +REG32(WPROT, 0x1c) | ||
53 | + FIELD(WPROT, ACTIVE, 0, 1) | ||
54 | +REG32(PLL_CLK_OTHER_DMN, 0x20) | ||
55 | + FIELD(PLL_CLK_OTHER_DMN, APLL_BYPASS, 0, 1) | ||
56 | +REG32(RPLL_CTRL, 0x40) | ||
57 | + FIELD(RPLL_CTRL, POST_SRC, 24, 3) | ||
58 | + FIELD(RPLL_CTRL, PRE_SRC, 20, 3) | ||
59 | + FIELD(RPLL_CTRL, CLKOUTDIV, 16, 2) | ||
60 | + FIELD(RPLL_CTRL, FBDIV, 8, 8) | ||
61 | + FIELD(RPLL_CTRL, BYPASS, 3, 1) | ||
62 | + FIELD(RPLL_CTRL, RESET, 0, 1) | ||
63 | +REG32(RPLL_CFG, 0x44) | ||
64 | + FIELD(RPLL_CFG, LOCK_DLY, 25, 7) | ||
65 | + FIELD(RPLL_CFG, LOCK_CNT, 13, 10) | ||
66 | + FIELD(RPLL_CFG, LFHF, 10, 2) | ||
67 | + FIELD(RPLL_CFG, CP, 5, 4) | ||
68 | + FIELD(RPLL_CFG, RES, 0, 4) | ||
69 | +REG32(RPLL_FRAC_CFG, 0x48) | ||
70 | + FIELD(RPLL_FRAC_CFG, ENABLED, 31, 1) | ||
71 | + FIELD(RPLL_FRAC_CFG, SEED, 22, 3) | ||
72 | + FIELD(RPLL_FRAC_CFG, ALGRTHM, 19, 1) | ||
73 | + FIELD(RPLL_FRAC_CFG, ORDER, 18, 1) | ||
74 | + FIELD(RPLL_FRAC_CFG, DATA, 0, 16) | ||
75 | +REG32(PLL_STATUS, 0x50) | ||
76 | + FIELD(PLL_STATUS, RPLL_STABLE, 2, 1) | ||
77 | + FIELD(PLL_STATUS, RPLL_LOCK, 0, 1) | ||
78 | +REG32(RPLL_TO_XPD_CTRL, 0x100) | ||
79 | + FIELD(RPLL_TO_XPD_CTRL, CLKACT, 25, 1) | ||
80 | + FIELD(RPLL_TO_XPD_CTRL, DIVISOR0, 8, 10) | ||
81 | +REG32(LPD_TOP_SWITCH_CTRL, 0x104) | ||
82 | + FIELD(LPD_TOP_SWITCH_CTRL, CLKACT_ADMA, 26, 1) | ||
83 | + FIELD(LPD_TOP_SWITCH_CTRL, CLKACT, 25, 1) | ||
84 | + FIELD(LPD_TOP_SWITCH_CTRL, DIVISOR0, 8, 10) | ||
85 | + FIELD(LPD_TOP_SWITCH_CTRL, SRCSEL, 0, 3) | ||
86 | +REG32(LPD_LSBUS_CTRL, 0x108) | ||
87 | + FIELD(LPD_LSBUS_CTRL, CLKACT, 25, 1) | ||
88 | + FIELD(LPD_LSBUS_CTRL, DIVISOR0, 8, 10) | ||
89 | + FIELD(LPD_LSBUS_CTRL, SRCSEL, 0, 3) | ||
90 | +REG32(CPU_R5_CTRL, 0x10c) | ||
91 | + FIELD(CPU_R5_CTRL, CLKACT_OCM2, 28, 1) | ||
92 | + FIELD(CPU_R5_CTRL, CLKACT_OCM, 27, 1) | ||
93 | + FIELD(CPU_R5_CTRL, CLKACT_CORE, 26, 1) | ||
94 | + FIELD(CPU_R5_CTRL, CLKACT, 25, 1) | ||
95 | + FIELD(CPU_R5_CTRL, DIVISOR0, 8, 10) | ||
96 | + FIELD(CPU_R5_CTRL, SRCSEL, 0, 3) | ||
97 | +REG32(IOU_SWITCH_CTRL, 0x114) | ||
98 | + FIELD(IOU_SWITCH_CTRL, CLKACT, 25, 1) | ||
99 | + FIELD(IOU_SWITCH_CTRL, DIVISOR0, 8, 10) | ||
100 | + FIELD(IOU_SWITCH_CTRL, SRCSEL, 0, 3) | ||
101 | +REG32(GEM0_REF_CTRL, 0x118) | ||
102 | + FIELD(GEM0_REF_CTRL, CLKACT_RX, 27, 1) | ||
103 | + FIELD(GEM0_REF_CTRL, CLKACT_TX, 26, 1) | ||
104 | + FIELD(GEM0_REF_CTRL, CLKACT, 25, 1) | ||
105 | + FIELD(GEM0_REF_CTRL, DIVISOR0, 8, 10) | ||
106 | + FIELD(GEM0_REF_CTRL, SRCSEL, 0, 3) | ||
107 | +REG32(GEM1_REF_CTRL, 0x11c) | ||
108 | + FIELD(GEM1_REF_CTRL, CLKACT_RX, 27, 1) | ||
109 | + FIELD(GEM1_REF_CTRL, CLKACT_TX, 26, 1) | ||
110 | + FIELD(GEM1_REF_CTRL, CLKACT, 25, 1) | ||
111 | + FIELD(GEM1_REF_CTRL, DIVISOR0, 8, 10) | ||
112 | + FIELD(GEM1_REF_CTRL, SRCSEL, 0, 3) | ||
113 | +REG32(GEM_TSU_REF_CTRL, 0x120) | ||
114 | + FIELD(GEM_TSU_REF_CTRL, CLKACT, 25, 1) | ||
115 | + FIELD(GEM_TSU_REF_CTRL, DIVISOR0, 8, 10) | ||
116 | + FIELD(GEM_TSU_REF_CTRL, SRCSEL, 0, 3) | ||
117 | +REG32(USB0_BUS_REF_CTRL, 0x124) | ||
118 | + FIELD(USB0_BUS_REF_CTRL, CLKACT, 25, 1) | ||
119 | + FIELD(USB0_BUS_REF_CTRL, DIVISOR0, 8, 10) | ||
120 | + FIELD(USB0_BUS_REF_CTRL, SRCSEL, 0, 3) | ||
121 | +REG32(UART0_REF_CTRL, 0x128) | ||
122 | + FIELD(UART0_REF_CTRL, CLKACT, 25, 1) | ||
123 | + FIELD(UART0_REF_CTRL, DIVISOR0, 8, 10) | ||
124 | + FIELD(UART0_REF_CTRL, SRCSEL, 0, 3) | ||
125 | +REG32(UART1_REF_CTRL, 0x12c) | ||
126 | + FIELD(UART1_REF_CTRL, CLKACT, 25, 1) | ||
127 | + FIELD(UART1_REF_CTRL, DIVISOR0, 8, 10) | ||
128 | + FIELD(UART1_REF_CTRL, SRCSEL, 0, 3) | ||
129 | +REG32(SPI0_REF_CTRL, 0x130) | ||
130 | + FIELD(SPI0_REF_CTRL, CLKACT, 25, 1) | ||
131 | + FIELD(SPI0_REF_CTRL, DIVISOR0, 8, 10) | ||
132 | + FIELD(SPI0_REF_CTRL, SRCSEL, 0, 3) | ||
133 | +REG32(SPI1_REF_CTRL, 0x134) | ||
134 | + FIELD(SPI1_REF_CTRL, CLKACT, 25, 1) | ||
135 | + FIELD(SPI1_REF_CTRL, DIVISOR0, 8, 10) | ||
136 | + FIELD(SPI1_REF_CTRL, SRCSEL, 0, 3) | ||
137 | +REG32(CAN0_REF_CTRL, 0x138) | ||
138 | + FIELD(CAN0_REF_CTRL, CLKACT, 25, 1) | ||
139 | + FIELD(CAN0_REF_CTRL, DIVISOR0, 8, 10) | ||
140 | + FIELD(CAN0_REF_CTRL, SRCSEL, 0, 3) | ||
141 | +REG32(CAN1_REF_CTRL, 0x13c) | ||
142 | + FIELD(CAN1_REF_CTRL, CLKACT, 25, 1) | ||
143 | + FIELD(CAN1_REF_CTRL, DIVISOR0, 8, 10) | ||
144 | + FIELD(CAN1_REF_CTRL, SRCSEL, 0, 3) | ||
145 | +REG32(I2C0_REF_CTRL, 0x140) | ||
146 | + FIELD(I2C0_REF_CTRL, CLKACT, 25, 1) | ||
147 | + FIELD(I2C0_REF_CTRL, DIVISOR0, 8, 10) | ||
148 | + FIELD(I2C0_REF_CTRL, SRCSEL, 0, 3) | ||
149 | +REG32(I2C1_REF_CTRL, 0x144) | ||
150 | + FIELD(I2C1_REF_CTRL, CLKACT, 25, 1) | ||
151 | + FIELD(I2C1_REF_CTRL, DIVISOR0, 8, 10) | ||
152 | + FIELD(I2C1_REF_CTRL, SRCSEL, 0, 3) | ||
153 | +REG32(DBG_LPD_CTRL, 0x148) | ||
154 | + FIELD(DBG_LPD_CTRL, CLKACT, 25, 1) | ||
155 | + FIELD(DBG_LPD_CTRL, DIVISOR0, 8, 10) | ||
156 | + FIELD(DBG_LPD_CTRL, SRCSEL, 0, 3) | ||
157 | +REG32(TIMESTAMP_REF_CTRL, 0x14c) | ||
158 | + FIELD(TIMESTAMP_REF_CTRL, CLKACT, 25, 1) | ||
159 | + FIELD(TIMESTAMP_REF_CTRL, DIVISOR0, 8, 10) | ||
160 | + FIELD(TIMESTAMP_REF_CTRL, SRCSEL, 0, 3) | ||
161 | +REG32(CRL_SAFETY_CHK, 0x150) | ||
162 | +REG32(PSM_REF_CTRL, 0x154) | ||
163 | + FIELD(PSM_REF_CTRL, DIVISOR0, 8, 10) | ||
164 | + FIELD(PSM_REF_CTRL, SRCSEL, 0, 3) | ||
165 | +REG32(DBG_TSTMP_CTRL, 0x158) | ||
166 | + FIELD(DBG_TSTMP_CTRL, CLKACT, 25, 1) | ||
167 | + FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 10) | ||
168 | + FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3) | ||
169 | +REG32(CPM_TOPSW_REF_CTRL, 0x15c) | ||
170 | + FIELD(CPM_TOPSW_REF_CTRL, CLKACT, 25, 1) | ||
171 | + FIELD(CPM_TOPSW_REF_CTRL, DIVISOR0, 8, 10) | ||
172 | + FIELD(CPM_TOPSW_REF_CTRL, SRCSEL, 0, 3) | ||
173 | +REG32(USB3_DUAL_REF_CTRL, 0x160) | ||
174 | + FIELD(USB3_DUAL_REF_CTRL, CLKACT, 25, 1) | ||
175 | + FIELD(USB3_DUAL_REF_CTRL, DIVISOR0, 8, 10) | ||
176 | + FIELD(USB3_DUAL_REF_CTRL, SRCSEL, 0, 3) | ||
177 | +REG32(RST_CPU_R5, 0x300) | ||
178 | + FIELD(RST_CPU_R5, RESET_PGE, 4, 1) | ||
179 | + FIELD(RST_CPU_R5, RESET_AMBA, 2, 1) | ||
180 | + FIELD(RST_CPU_R5, RESET_CPU1, 1, 1) | ||
181 | + FIELD(RST_CPU_R5, RESET_CPU0, 0, 1) | ||
182 | +REG32(RST_ADMA, 0x304) | ||
183 | + FIELD(RST_ADMA, RESET, 0, 1) | ||
184 | +REG32(RST_GEM0, 0x308) | ||
185 | + FIELD(RST_GEM0, RESET, 0, 1) | ||
186 | +REG32(RST_GEM1, 0x30c) | ||
187 | + FIELD(RST_GEM1, RESET, 0, 1) | ||
188 | +REG32(RST_SPARE, 0x310) | ||
189 | + FIELD(RST_SPARE, RESET, 0, 1) | ||
190 | +REG32(RST_USB0, 0x314) | ||
191 | + FIELD(RST_USB0, RESET, 0, 1) | ||
192 | +REG32(RST_UART0, 0x318) | ||
193 | + FIELD(RST_UART0, RESET, 0, 1) | ||
194 | +REG32(RST_UART1, 0x31c) | ||
195 | + FIELD(RST_UART1, RESET, 0, 1) | ||
196 | +REG32(RST_SPI0, 0x320) | ||
197 | + FIELD(RST_SPI0, RESET, 0, 1) | ||
198 | +REG32(RST_SPI1, 0x324) | ||
199 | + FIELD(RST_SPI1, RESET, 0, 1) | ||
200 | +REG32(RST_CAN0, 0x328) | ||
201 | + FIELD(RST_CAN0, RESET, 0, 1) | ||
202 | +REG32(RST_CAN1, 0x32c) | ||
203 | + FIELD(RST_CAN1, RESET, 0, 1) | ||
204 | +REG32(RST_I2C0, 0x330) | ||
205 | + FIELD(RST_I2C0, RESET, 0, 1) | ||
206 | +REG32(RST_I2C1, 0x334) | ||
207 | + FIELD(RST_I2C1, RESET, 0, 1) | ||
208 | +REG32(RST_DBG_LPD, 0x338) | ||
209 | + FIELD(RST_DBG_LPD, RPU_DBG1_RESET, 5, 1) | ||
210 | + FIELD(RST_DBG_LPD, RPU_DBG0_RESET, 4, 1) | ||
211 | + FIELD(RST_DBG_LPD, RESET_HSDP, 1, 1) | ||
212 | + FIELD(RST_DBG_LPD, RESET, 0, 1) | ||
213 | +REG32(RST_GPIO, 0x33c) | ||
214 | + FIELD(RST_GPIO, RESET, 0, 1) | ||
215 | +REG32(RST_TTC, 0x344) | ||
216 | + FIELD(RST_TTC, TTC3_RESET, 3, 1) | ||
217 | + FIELD(RST_TTC, TTC2_RESET, 2, 1) | ||
218 | + FIELD(RST_TTC, TTC1_RESET, 1, 1) | ||
219 | + FIELD(RST_TTC, TTC0_RESET, 0, 1) | ||
220 | +REG32(RST_TIMESTAMP, 0x348) | ||
221 | + FIELD(RST_TIMESTAMP, RESET, 0, 1) | ||
222 | +REG32(RST_SWDT, 0x34c) | ||
223 | + FIELD(RST_SWDT, RESET, 0, 1) | ||
224 | +REG32(RST_OCM, 0x350) | ||
225 | + FIELD(RST_OCM, RESET, 0, 1) | ||
226 | +REG32(RST_IPI, 0x354) | ||
227 | + FIELD(RST_IPI, RESET, 0, 1) | ||
228 | +REG32(RST_SYSMON, 0x358) | ||
229 | + FIELD(RST_SYSMON, SEQ_RST, 1, 1) | ||
230 | + FIELD(RST_SYSMON, CFG_RST, 0, 1) | ||
231 | +REG32(RST_FPD, 0x360) | ||
232 | + FIELD(RST_FPD, SRST, 1, 1) | ||
233 | + FIELD(RST_FPD, POR, 0, 1) | ||
234 | +REG32(PSM_RST_MODE, 0x370) | ||
235 | + FIELD(PSM_RST_MODE, WAKEUP, 2, 1) | ||
236 | + FIELD(PSM_RST_MODE, RST_MODE, 0, 2) | ||
237 | + | ||
238 | +#define CRL_R_MAX (R_PSM_RST_MODE + 1) | ||
239 | + | ||
240 | +#define RPU_MAX_CPU 2 | ||
241 | + | ||
242 | +struct XlnxVersalCRL { | ||
243 | + SysBusDevice parent_obj; | ||
244 | + qemu_irq irq; | ||
245 | + | ||
246 | + struct { | ||
247 | + ARMCPU *cpu_r5[RPU_MAX_CPU]; | ||
248 | + DeviceState *adma[8]; | ||
249 | + DeviceState *uart[2]; | ||
250 | + DeviceState *gem[2]; | ||
251 | + DeviceState *usb; | ||
252 | + } cfg; | ||
253 | + | ||
254 | + RegisterInfoArray *reg_array; | ||
255 | + uint32_t regs[CRL_R_MAX]; | ||
256 | + RegisterInfo regs_info[CRL_R_MAX]; | ||
257 | +}; | ||
258 | +#endif | ||
259 | diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c | ||
260 | new file mode 100644 | ||
261 | index XXXXXXX..XXXXXXX | ||
262 | --- /dev/null | ||
263 | +++ b/hw/misc/xlnx-versal-crl.c | ||
264 | @@ -XXX,XX +XXX,XX @@ | ||
265 | +/* | ||
266 | + * QEMU model of the Clock-Reset-LPD (CRL). | ||
267 | + * | ||
268 | + * Copyright (c) 2022 Advanced Micro Devices, Inc. | ||
269 | + * SPDX-License-Identifier: GPL-2.0-or-later | ||
270 | + * | ||
271 | + * Written by Edgar E. Iglesias <edgar.iglesias@amd.com> | ||
272 | + */ | ||
273 | + | ||
274 | +#include "qemu/osdep.h" | ||
275 | +#include "qapi/error.h" | ||
276 | +#include "qemu/log.h" | ||
277 | +#include "qemu/bitops.h" | ||
278 | +#include "migration/vmstate.h" | ||
279 | +#include "hw/qdev-properties.h" | ||
280 | +#include "hw/sysbus.h" | ||
281 | +#include "hw/irq.h" | ||
282 | +#include "hw/register.h" | ||
283 | +#include "hw/resettable.h" | ||
284 | + | ||
285 | +#include "target/arm/arm-powerctl.h" | ||
286 | +#include "hw/misc/xlnx-versal-crl.h" | ||
287 | + | ||
288 | +#ifndef XLNX_VERSAL_CRL_ERR_DEBUG | ||
289 | +#define XLNX_VERSAL_CRL_ERR_DEBUG 0 | ||
290 | +#endif | ||
291 | + | ||
292 | +static void crl_update_irq(XlnxVersalCRL *s) | ||
293 | +{ | ||
294 | + bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK]; | ||
295 | + qemu_set_irq(s->irq, pending); | ||
296 | +} | ||
297 | + | ||
298 | +static void crl_status_postw(RegisterInfo *reg, uint64_t val64) | ||
299 | +{ | ||
300 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
301 | + crl_update_irq(s); | ||
302 | +} | ||
303 | + | ||
304 | +static uint64_t crl_enable_prew(RegisterInfo *reg, uint64_t val64) | ||
305 | +{ | ||
306 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
307 | + uint32_t val = val64; | ||
308 | + | ||
309 | + s->regs[R_IR_MASK] &= ~val; | ||
310 | + crl_update_irq(s); | ||
311 | + return 0; | ||
312 | +} | ||
313 | + | ||
314 | +static uint64_t crl_disable_prew(RegisterInfo *reg, uint64_t val64) | ||
315 | +{ | ||
316 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
317 | + uint32_t val = val64; | ||
318 | + | ||
319 | + s->regs[R_IR_MASK] |= val; | ||
320 | + crl_update_irq(s); | ||
321 | + return 0; | ||
322 | +} | ||
323 | + | ||
324 | +static void crl_reset_dev(XlnxVersalCRL *s, DeviceState *dev, | ||
325 | + bool rst_old, bool rst_new) | ||
326 | +{ | ||
327 | + device_cold_reset(dev); | ||
328 | +} | ||
329 | + | ||
330 | +static void crl_reset_cpu(XlnxVersalCRL *s, ARMCPU *armcpu, | ||
331 | + bool rst_old, bool rst_new) | ||
332 | +{ | ||
333 | + if (rst_new) { | ||
334 | + arm_set_cpu_off(armcpu->mp_affinity); | ||
335 | + } else { | ||
336 | + arm_set_cpu_on_and_reset(armcpu->mp_affinity); | ||
337 | + } | ||
338 | +} | ||
339 | + | ||
340 | +#define REGFIELD_RESET(type, s, reg, f, new_val, dev) { \ | ||
341 | + bool old_f = ARRAY_FIELD_EX32((s)->regs, reg, f); \ | ||
342 | + bool new_f = FIELD_EX32(new_val, reg, f); \ | ||
343 | + \ | ||
344 | + /* Detect edges. */ \ | ||
345 | + if (dev && old_f != new_f) { \ | ||
346 | + crl_reset_ ## type(s, dev, old_f, new_f); \ | ||
347 | + } \ | ||
348 | +} | ||
349 | + | ||
350 | +static uint64_t crl_rst_r5_prew(RegisterInfo *reg, uint64_t val64) | ||
351 | +{ | ||
352 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
353 | + | ||
354 | + REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU0, val64, s->cfg.cpu_r5[0]); | ||
355 | + REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU1, val64, s->cfg.cpu_r5[1]); | ||
356 | + return val64; | ||
357 | +} | ||
358 | + | ||
359 | +static uint64_t crl_rst_adma_prew(RegisterInfo *reg, uint64_t val64) | ||
360 | +{ | ||
361 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
362 | + int i; | ||
363 | + | ||
364 | + /* A single register fans out to all ADMA reset inputs. */ | ||
365 | + for (i = 0; i < ARRAY_SIZE(s->cfg.adma); i++) { | ||
366 | + REGFIELD_RESET(dev, s, RST_ADMA, RESET, val64, s->cfg.adma[i]); | ||
367 | + } | ||
368 | + return val64; | ||
369 | +} | ||
370 | + | ||
371 | +static uint64_t crl_rst_uart0_prew(RegisterInfo *reg, uint64_t val64) | ||
372 | +{ | ||
373 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
374 | + | ||
375 | + REGFIELD_RESET(dev, s, RST_UART0, RESET, val64, s->cfg.uart[0]); | ||
376 | + return val64; | ||
377 | +} | ||
378 | + | ||
379 | +static uint64_t crl_rst_uart1_prew(RegisterInfo *reg, uint64_t val64) | ||
380 | +{ | ||
381 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
382 | + | ||
383 | + REGFIELD_RESET(dev, s, RST_UART1, RESET, val64, s->cfg.uart[1]); | ||
384 | + return val64; | ||
385 | +} | ||
386 | + | ||
387 | +static uint64_t crl_rst_gem0_prew(RegisterInfo *reg, uint64_t val64) | ||
388 | +{ | ||
389 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
390 | + | ||
391 | + REGFIELD_RESET(dev, s, RST_GEM0, RESET, val64, s->cfg.gem[0]); | ||
392 | + return val64; | ||
393 | +} | ||
394 | + | ||
395 | +static uint64_t crl_rst_gem1_prew(RegisterInfo *reg, uint64_t val64) | ||
396 | +{ | ||
397 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
398 | + | ||
399 | + REGFIELD_RESET(dev, s, RST_GEM1, RESET, val64, s->cfg.gem[1]); | ||
400 | + return val64; | ||
401 | +} | ||
402 | + | ||
403 | +static uint64_t crl_rst_usb_prew(RegisterInfo *reg, uint64_t val64) | ||
404 | +{ | ||
405 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); | ||
406 | + | ||
407 | + REGFIELD_RESET(dev, s, RST_USB0, RESET, val64, s->cfg.usb); | ||
408 | + return val64; | ||
409 | +} | ||
410 | + | ||
411 | +static const RegisterAccessInfo crl_regs_info[] = { | ||
412 | + { .name = "ERR_CTRL", .addr = A_ERR_CTRL, | ||
413 | + },{ .name = "IR_STATUS", .addr = A_IR_STATUS, | ||
414 | + .w1c = 0x1, | ||
415 | + .post_write = crl_status_postw, | ||
416 | + },{ .name = "IR_MASK", .addr = A_IR_MASK, | ||
417 | + .reset = 0x1, | ||
418 | + .ro = 0x1, | ||
419 | + },{ .name = "IR_ENABLE", .addr = A_IR_ENABLE, | ||
420 | + .pre_write = crl_enable_prew, | ||
421 | + },{ .name = "IR_DISABLE", .addr = A_IR_DISABLE, | ||
422 | + .pre_write = crl_disable_prew, | ||
423 | + },{ .name = "WPROT", .addr = A_WPROT, | ||
424 | + },{ .name = "PLL_CLK_OTHER_DMN", .addr = A_PLL_CLK_OTHER_DMN, | ||
425 | + .reset = 0x1, | ||
426 | + .rsvd = 0xe, | ||
427 | + },{ .name = "RPLL_CTRL", .addr = A_RPLL_CTRL, | ||
428 | + .reset = 0x24809, | ||
429 | + .rsvd = 0xf88c00f6, | ||
430 | + },{ .name = "RPLL_CFG", .addr = A_RPLL_CFG, | ||
431 | + .reset = 0x2000000, | ||
432 | + .rsvd = 0x1801210, | ||
433 | + },{ .name = "RPLL_FRAC_CFG", .addr = A_RPLL_FRAC_CFG, | ||
434 | + .rsvd = 0x7e330000, | ||
435 | + },{ .name = "PLL_STATUS", .addr = A_PLL_STATUS, | ||
436 | + .reset = R_PLL_STATUS_RPLL_STABLE_MASK | | ||
437 | + R_PLL_STATUS_RPLL_LOCK_MASK, | ||
438 | + .rsvd = 0xfa, | ||
439 | + .ro = 0x5, | ||
440 | + },{ .name = "RPLL_TO_XPD_CTRL", .addr = A_RPLL_TO_XPD_CTRL, | ||
441 | + .reset = 0x2000100, | ||
442 | + .rsvd = 0xfdfc00ff, | ||
443 | + },{ .name = "LPD_TOP_SWITCH_CTRL", .addr = A_LPD_TOP_SWITCH_CTRL, | ||
444 | + .reset = 0x6000300, | ||
445 | + .rsvd = 0xf9fc00f8, | ||
446 | + },{ .name = "LPD_LSBUS_CTRL", .addr = A_LPD_LSBUS_CTRL, | ||
447 | + .reset = 0x2000800, | ||
448 | + .rsvd = 0xfdfc00f8, | ||
449 | + },{ .name = "CPU_R5_CTRL", .addr = A_CPU_R5_CTRL, | ||
450 | + .reset = 0xe000300, | ||
451 | + .rsvd = 0xe1fc00f8, | ||
452 | + },{ .name = "IOU_SWITCH_CTRL", .addr = A_IOU_SWITCH_CTRL, | ||
453 | + .reset = 0x2000500, | ||
454 | + .rsvd = 0xfdfc00f8, | ||
455 | + },{ .name = "GEM0_REF_CTRL", .addr = A_GEM0_REF_CTRL, | ||
456 | + .reset = 0xe000a00, | ||
457 | + .rsvd = 0xf1fc00f8, | ||
458 | + },{ .name = "GEM1_REF_CTRL", .addr = A_GEM1_REF_CTRL, | ||
459 | + .reset = 0xe000a00, | ||
460 | + .rsvd = 0xf1fc00f8, | ||
461 | + },{ .name = "GEM_TSU_REF_CTRL", .addr = A_GEM_TSU_REF_CTRL, | ||
462 | + .reset = 0x300, | ||
463 | + .rsvd = 0xfdfc00f8, | ||
464 | + },{ .name = "USB0_BUS_REF_CTRL", .addr = A_USB0_BUS_REF_CTRL, | ||
465 | + .reset = 0x2001900, | ||
466 | + .rsvd = 0xfdfc00f8, | ||
467 | + },{ .name = "UART0_REF_CTRL", .addr = A_UART0_REF_CTRL, | ||
468 | + .reset = 0xc00, | ||
469 | + .rsvd = 0xfdfc00f8, | ||
470 | + },{ .name = "UART1_REF_CTRL", .addr = A_UART1_REF_CTRL, | ||
471 | + .reset = 0xc00, | ||
472 | + .rsvd = 0xfdfc00f8, | ||
473 | + },{ .name = "SPI0_REF_CTRL", .addr = A_SPI0_REF_CTRL, | ||
474 | + .reset = 0x600, | ||
475 | + .rsvd = 0xfdfc00f8, | ||
476 | + },{ .name = "SPI1_REF_CTRL", .addr = A_SPI1_REF_CTRL, | ||
477 | + .reset = 0x600, | ||
478 | + .rsvd = 0xfdfc00f8, | ||
479 | + },{ .name = "CAN0_REF_CTRL", .addr = A_CAN0_REF_CTRL, | ||
480 | + .reset = 0xc00, | ||
481 | + .rsvd = 0xfdfc00f8, | ||
482 | + },{ .name = "CAN1_REF_CTRL", .addr = A_CAN1_REF_CTRL, | ||
483 | + .reset = 0xc00, | ||
484 | + .rsvd = 0xfdfc00f8, | ||
485 | + },{ .name = "I2C0_REF_CTRL", .addr = A_I2C0_REF_CTRL, | ||
486 | + .reset = 0xc00, | ||
487 | + .rsvd = 0xfdfc00f8, | ||
488 | + },{ .name = "I2C1_REF_CTRL", .addr = A_I2C1_REF_CTRL, | ||
489 | + .reset = 0xc00, | ||
490 | + .rsvd = 0xfdfc00f8, | ||
491 | + },{ .name = "DBG_LPD_CTRL", .addr = A_DBG_LPD_CTRL, | ||
492 | + .reset = 0x300, | ||
493 | + .rsvd = 0xfdfc00f8, | ||
494 | + },{ .name = "TIMESTAMP_REF_CTRL", .addr = A_TIMESTAMP_REF_CTRL, | ||
495 | + .reset = 0x2000c00, | ||
496 | + .rsvd = 0xfdfc00f8, | ||
497 | + },{ .name = "CRL_SAFETY_CHK", .addr = A_CRL_SAFETY_CHK, | ||
498 | + },{ .name = "PSM_REF_CTRL", .addr = A_PSM_REF_CTRL, | ||
499 | + .reset = 0xf04, | ||
500 | + .rsvd = 0xfffc00f8, | ||
501 | + },{ .name = "DBG_TSTMP_CTRL", .addr = A_DBG_TSTMP_CTRL, | ||
502 | + .reset = 0x300, | ||
503 | + .rsvd = 0xfdfc00f8, | ||
504 | + },{ .name = "CPM_TOPSW_REF_CTRL", .addr = A_CPM_TOPSW_REF_CTRL, | ||
505 | + .reset = 0x300, | ||
506 | + .rsvd = 0xfdfc00f8, | ||
507 | + },{ .name = "USB3_DUAL_REF_CTRL", .addr = A_USB3_DUAL_REF_CTRL, | ||
508 | + .reset = 0x3c00, | ||
509 | + .rsvd = 0xfdfc00f8, | ||
510 | + },{ .name = "RST_CPU_R5", .addr = A_RST_CPU_R5, | ||
511 | + .reset = 0x17, | ||
512 | + .rsvd = 0x8, | ||
513 | + .pre_write = crl_rst_r5_prew, | ||
514 | + },{ .name = "RST_ADMA", .addr = A_RST_ADMA, | ||
515 | + .reset = 0x1, | ||
516 | + .pre_write = crl_rst_adma_prew, | ||
517 | + },{ .name = "RST_GEM0", .addr = A_RST_GEM0, | ||
518 | + .reset = 0x1, | ||
519 | + .pre_write = crl_rst_gem0_prew, | ||
520 | + },{ .name = "RST_GEM1", .addr = A_RST_GEM1, | ||
521 | + .reset = 0x1, | ||
522 | + .pre_write = crl_rst_gem1_prew, | ||
523 | + },{ .name = "RST_SPARE", .addr = A_RST_SPARE, | ||
524 | + .reset = 0x1, | ||
525 | + },{ .name = "RST_USB0", .addr = A_RST_USB0, | ||
526 | + .reset = 0x1, | ||
527 | + .pre_write = crl_rst_usb_prew, | ||
528 | + },{ .name = "RST_UART0", .addr = A_RST_UART0, | ||
529 | + .reset = 0x1, | ||
530 | + .pre_write = crl_rst_uart0_prew, | ||
531 | + },{ .name = "RST_UART1", .addr = A_RST_UART1, | ||
532 | + .reset = 0x1, | ||
533 | + .pre_write = crl_rst_uart1_prew, | ||
534 | + },{ .name = "RST_SPI0", .addr = A_RST_SPI0, | ||
535 | + .reset = 0x1, | ||
536 | + },{ .name = "RST_SPI1", .addr = A_RST_SPI1, | ||
537 | + .reset = 0x1, | ||
538 | + },{ .name = "RST_CAN0", .addr = A_RST_CAN0, | ||
539 | + .reset = 0x1, | ||
540 | + },{ .name = "RST_CAN1", .addr = A_RST_CAN1, | ||
541 | + .reset = 0x1, | ||
542 | + },{ .name = "RST_I2C0", .addr = A_RST_I2C0, | ||
543 | + .reset = 0x1, | ||
544 | + },{ .name = "RST_I2C1", .addr = A_RST_I2C1, | ||
545 | + .reset = 0x1, | ||
546 | + },{ .name = "RST_DBG_LPD", .addr = A_RST_DBG_LPD, | ||
547 | + .reset = 0x33, | ||
548 | + .rsvd = 0xcc, | ||
549 | + },{ .name = "RST_GPIO", .addr = A_RST_GPIO, | ||
550 | + .reset = 0x1, | ||
551 | + },{ .name = "RST_TTC", .addr = A_RST_TTC, | ||
552 | + .reset = 0xf, | ||
553 | + },{ .name = "RST_TIMESTAMP", .addr = A_RST_TIMESTAMP, | ||
554 | + .reset = 0x1, | ||
555 | + },{ .name = "RST_SWDT", .addr = A_RST_SWDT, | ||
556 | + .reset = 0x1, | ||
557 | + },{ .name = "RST_OCM", .addr = A_RST_OCM, | ||
558 | + },{ .name = "RST_IPI", .addr = A_RST_IPI, | ||
559 | + },{ .name = "RST_FPD", .addr = A_RST_FPD, | ||
560 | + .reset = 0x3, | ||
561 | + },{ .name = "PSM_RST_MODE", .addr = A_PSM_RST_MODE, | ||
562 | + .reset = 0x1, | ||
563 | + .rsvd = 0xf8, | ||
564 | + } | ||
565 | +}; | ||
566 | + | ||
567 | +static void crl_reset_enter(Object *obj, ResetType type) | ||
568 | +{ | ||
569 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj); | ||
570 | + unsigned int i; | ||
571 | + | ||
572 | + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { | ||
573 | + register_reset(&s->regs_info[i]); | ||
574 | + } | ||
575 | +} | ||
576 | + | ||
577 | +static void crl_reset_hold(Object *obj) | ||
578 | +{ | ||
579 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj); | ||
580 | + | ||
581 | + crl_update_irq(s); | ||
582 | +} | ||
583 | + | ||
584 | +static const MemoryRegionOps crl_ops = { | ||
585 | + .read = register_read_memory, | ||
586 | + .write = register_write_memory, | ||
587 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
588 | + .valid = { | ||
589 | + .min_access_size = 4, | ||
590 | + .max_access_size = 4, | ||
591 | + }, | ||
592 | +}; | ||
593 | + | ||
594 | +static void crl_init(Object *obj) | ||
595 | +{ | ||
596 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj); | ||
597 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
598 | + int i; | ||
599 | + | ||
600 | + s->reg_array = | ||
601 | + register_init_block32(DEVICE(obj), crl_regs_info, | ||
602 | + ARRAY_SIZE(crl_regs_info), | ||
603 | + s->regs_info, s->regs, | ||
604 | + &crl_ops, | ||
605 | + XLNX_VERSAL_CRL_ERR_DEBUG, | ||
606 | + CRL_R_MAX * 4); | ||
607 | + sysbus_init_mmio(sbd, &s->reg_array->mem); | ||
608 | + sysbus_init_irq(sbd, &s->irq); | ||
609 | + | ||
610 | + for (i = 0; i < ARRAY_SIZE(s->cfg.cpu_r5); ++i) { | ||
611 | + object_property_add_link(obj, "cpu_r5[*]", TYPE_ARM_CPU, | ||
612 | + (Object **)&s->cfg.cpu_r5[i], | ||
613 | + qdev_prop_allow_set_link_before_realize, | ||
614 | + OBJ_PROP_LINK_STRONG); | ||
615 | + } | ||
616 | + | ||
617 | + for (i = 0; i < ARRAY_SIZE(s->cfg.adma); ++i) { | ||
618 | + object_property_add_link(obj, "adma[*]", TYPE_DEVICE, | ||
619 | + (Object **)&s->cfg.adma[i], | ||
620 | + qdev_prop_allow_set_link_before_realize, | ||
621 | + OBJ_PROP_LINK_STRONG); | ||
622 | + } | ||
623 | + | ||
624 | + for (i = 0; i < ARRAY_SIZE(s->cfg.uart); ++i) { | ||
625 | + object_property_add_link(obj, "uart[*]", TYPE_DEVICE, | ||
626 | + (Object **)&s->cfg.uart[i], | ||
627 | + qdev_prop_allow_set_link_before_realize, | ||
628 | + OBJ_PROP_LINK_STRONG); | ||
629 | + } | ||
630 | + | ||
631 | + for (i = 0; i < ARRAY_SIZE(s->cfg.gem); ++i) { | ||
632 | + object_property_add_link(obj, "gem[*]", TYPE_DEVICE, | ||
633 | + (Object **)&s->cfg.gem[i], | ||
634 | + qdev_prop_allow_set_link_before_realize, | ||
635 | + OBJ_PROP_LINK_STRONG); | ||
636 | + } | ||
637 | + | ||
638 | + object_property_add_link(obj, "usb", TYPE_DEVICE, | ||
639 | + (Object **)&s->cfg.gem[i], | ||
640 | + qdev_prop_allow_set_link_before_realize, | ||
641 | + OBJ_PROP_LINK_STRONG); | ||
642 | +} | ||
643 | + | ||
644 | +static void crl_finalize(Object *obj) | ||
645 | +{ | ||
646 | + XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj); | ||
647 | + register_finalize_block(s->reg_array); | ||
648 | +} | ||
649 | + | ||
650 | +static const VMStateDescription vmstate_crl = { | ||
651 | + .name = TYPE_XLNX_VERSAL_CRL, | ||
652 | + .version_id = 1, | ||
653 | + .minimum_version_id = 1, | ||
654 | + .fields = (VMStateField[]) { | ||
655 | + VMSTATE_UINT32_ARRAY(regs, XlnxVersalCRL, CRL_R_MAX), | ||
656 | + VMSTATE_END_OF_LIST(), | ||
657 | + } | ||
658 | +}; | ||
659 | + | ||
660 | +static void crl_class_init(ObjectClass *klass, void *data) | ||
661 | +{ | ||
662 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
663 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
664 | + | ||
665 | + dc->vmsd = &vmstate_crl; | ||
666 | + | ||
667 | + rc->phases.enter = crl_reset_enter; | ||
668 | + rc->phases.hold = crl_reset_hold; | ||
669 | +} | ||
670 | + | ||
671 | +static const TypeInfo crl_info = { | ||
672 | + .name = TYPE_XLNX_VERSAL_CRL, | ||
673 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
674 | + .instance_size = sizeof(XlnxVersalCRL), | ||
675 | + .class_init = crl_class_init, | ||
676 | + .instance_init = crl_init, | ||
677 | + .instance_finalize = crl_finalize, | ||
678 | +}; | ||
679 | + | ||
680 | +static void crl_register_types(void) | ||
681 | +{ | ||
682 | + type_register_static(&crl_info); | ||
683 | +} | ||
684 | + | ||
685 | +type_init(crl_register_types) | ||
686 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
19 | index XXXXXXX..XXXXXXX 100644 | 687 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/helper.c | 688 | --- a/hw/misc/meson.build |
21 | +++ b/target/arm/helper.c | 689 | +++ b/hw/misc/meson.build |
22 | @@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, | 690 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) |
23 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | 691 | softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c')) |
24 | bool secure = arm_is_secure_below_el3(env); | 692 | specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c')) |
25 | int mask = secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; | 693 | specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c')) |
26 | - int bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_E2 : ARMMMUIdx_SE2, | 694 | +specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c')) |
27 | + int bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2, | 695 | softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files( |
28 | pageaddr); | 696 | 'xlnx-versal-xramc.c', |
29 | 697 | 'xlnx-versal-pmc-iou-slcr.c', | |
30 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); | ||
31 | -- | 698 | -- |
32 | 2.20.1 | 699 | 2.25.1 |
33 | |||
34 | diff view generated by jsdifflib |
1 | Move the various gen_aa32* functions and macros out of translate.c | 1 | From: "Edgar E. Iglesias" <edgar.iglesias@amd.com> |
---|---|---|---|
2 | and into translate-a32.h. | ||
3 | 2 | ||
3 | Connect the CRL (Clock Reset LPD) to the Versal SoC. | ||
4 | |||
5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> | ||
6 | Reviewed-by: Frederic Konrad <fkonrad@amd.com> | ||
7 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | ||
8 | Message-id: 20220406174303.2022038-5-edgar.iglesias@xilinx.com | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20210430132740.10391-6-peter.maydell@linaro.org | ||
8 | --- | 10 | --- |
9 | target/arm/translate-a32.h | 53 ++++++++++++++++++++++++++++++++++++++ | 11 | include/hw/arm/xlnx-versal.h | 4 +++ |
10 | target/arm/translate.c | 51 ++++++++++++------------------------ | 12 | hw/arm/xlnx-versal.c | 54 ++++++++++++++++++++++++++++++++++-- |
11 | 2 files changed, 69 insertions(+), 35 deletions(-) | 13 | 2 files changed, 56 insertions(+), 2 deletions(-) |
12 | 14 | ||
13 | diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h | 15 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h |
14 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/translate-a32.h | 17 | --- a/include/hw/arm/xlnx-versal.h |
16 | +++ b/target/arm/translate-a32.h | 18 | +++ b/include/hw/arm/xlnx-versal.h |
17 | @@ -XXX,XX +XXX,XX @@ static inline TCGv_i32 load_reg(DisasContext *s, int reg) | 19 | @@ -XXX,XX +XXX,XX @@ |
18 | return tmp; | 20 | #include "hw/nvram/xlnx-versal-efuse.h" |
21 | #include "hw/ssi/xlnx-versal-ospi.h" | ||
22 | #include "hw/dma/xlnx_csu_dma.h" | ||
23 | +#include "hw/misc/xlnx-versal-crl.h" | ||
24 | #include "hw/misc/xlnx-versal-pmc-iou-slcr.h" | ||
25 | |||
26 | #define TYPE_XLNX_VERSAL "xlnx-versal" | ||
27 | @@ -XXX,XX +XXX,XX @@ struct Versal { | ||
28 | qemu_or_irq irq_orgate; | ||
29 | XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; | ||
30 | } xram; | ||
31 | + | ||
32 | + XlnxVersalCRL crl; | ||
33 | } lpd; | ||
34 | |||
35 | /* The Platform Management Controller subsystem. */ | ||
36 | @@ -XXX,XX +XXX,XX @@ struct Versal { | ||
37 | #define VERSAL_TIMER_NS_EL1_IRQ 14 | ||
38 | #define VERSAL_TIMER_NS_EL2_IRQ 10 | ||
39 | |||
40 | +#define VERSAL_CRL_IRQ 10 | ||
41 | #define VERSAL_UART0_IRQ_0 18 | ||
42 | #define VERSAL_UART1_IRQ_0 19 | ||
43 | #define VERSAL_USB0_IRQ_0 22 | ||
44 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/hw/arm/xlnx-versal.c | ||
47 | +++ b/hw/arm/xlnx-versal.c | ||
48 | @@ -XXX,XX +XXX,XX @@ static void versal_create_ospi(Versal *s, qemu_irq *pic) | ||
49 | qdev_connect_gpio_out(orgate, 0, pic[VERSAL_OSPI_IRQ]); | ||
19 | } | 50 | } |
20 | 51 | ||
21 | +void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, | 52 | +static void versal_create_crl(Versal *s, qemu_irq *pic) |
22 | + TCGv_i32 a32, int index, MemOp opc); | 53 | +{ |
23 | +void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, | 54 | + SysBusDevice *sbd; |
24 | + TCGv_i32 a32, int index, MemOp opc); | 55 | + int i; |
25 | +void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, | ||
26 | + TCGv_i32 a32, int index, MemOp opc); | ||
27 | +void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, | ||
28 | + TCGv_i32 a32, int index, MemOp opc); | ||
29 | +void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, | ||
30 | + int index, MemOp opc); | ||
31 | +void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, | ||
32 | + int index, MemOp opc); | ||
33 | +void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, | ||
34 | + int index, MemOp opc); | ||
35 | +void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, | ||
36 | + int index, MemOp opc); | ||
37 | + | 56 | + |
38 | +#define DO_GEN_LD(SUFF, OPC) \ | 57 | + object_initialize_child(OBJECT(s), "crl", &s->lpd.crl, |
39 | + static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ | 58 | + TYPE_XLNX_VERSAL_CRL); |
40 | + TCGv_i32 a32, int index) \ | 59 | + sbd = SYS_BUS_DEVICE(&s->lpd.crl); |
41 | + { \ | 60 | + |
42 | + gen_aa32_ld_i32(s, val, a32, index, OPC); \ | 61 | + for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) { |
62 | + g_autofree gchar *name = g_strdup_printf("cpu_r5[%d]", i); | ||
63 | + | ||
64 | + object_property_set_link(OBJECT(&s->lpd.crl), | ||
65 | + name, OBJECT(&s->lpd.rpu.cpu[i]), | ||
66 | + &error_abort); | ||
43 | + } | 67 | + } |
44 | + | 68 | + |
45 | +#define DO_GEN_ST(SUFF, OPC) \ | 69 | + for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) { |
46 | + static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \ | 70 | + g_autofree gchar *name = g_strdup_printf("gem[%d]", i); |
47 | + TCGv_i32 a32, int index) \ | 71 | + |
48 | + { \ | 72 | + object_property_set_link(OBJECT(&s->lpd.crl), |
49 | + gen_aa32_st_i32(s, val, a32, index, OPC); \ | 73 | + name, OBJECT(&s->lpd.iou.gem[i]), |
74 | + &error_abort); | ||
50 | + } | 75 | + } |
51 | + | 76 | + |
52 | +static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val, | 77 | + for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) { |
53 | + TCGv_i32 a32, int index) | 78 | + g_autofree gchar *name = g_strdup_printf("adma[%d]", i); |
54 | +{ | 79 | + |
55 | + gen_aa32_ld_i64(s, val, a32, index, MO_Q); | 80 | + object_property_set_link(OBJECT(&s->lpd.crl), |
81 | + name, OBJECT(&s->lpd.iou.adma[i]), | ||
82 | + &error_abort); | ||
83 | + } | ||
84 | + | ||
85 | + for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) { | ||
86 | + g_autofree gchar *name = g_strdup_printf("uart[%d]", i); | ||
87 | + | ||
88 | + object_property_set_link(OBJECT(&s->lpd.crl), | ||
89 | + name, OBJECT(&s->lpd.iou.uart[i]), | ||
90 | + &error_abort); | ||
91 | + } | ||
92 | + | ||
93 | + object_property_set_link(OBJECT(&s->lpd.crl), | ||
94 | + "usb", OBJECT(&s->lpd.iou.usb), | ||
95 | + &error_abort); | ||
96 | + | ||
97 | + sysbus_realize(sbd, &error_fatal); | ||
98 | + memory_region_add_subregion(&s->mr_ps, MM_CRL, | ||
99 | + sysbus_mmio_get_region(sbd, 0)); | ||
100 | + sysbus_connect_irq(sbd, 0, pic[VERSAL_CRL_IRQ]); | ||
56 | +} | 101 | +} |
57 | + | 102 | + |
58 | +static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, | 103 | /* This takes the board allocated linear DDR memory and creates aliases |
59 | + TCGv_i32 a32, int index) | 104 | * for each split DDR range/aperture on the Versal address map. |
60 | +{ | ||
61 | + gen_aa32_st_i64(s, val, a32, index, MO_Q); | ||
62 | +} | ||
63 | + | ||
64 | +DO_GEN_LD(8u, MO_UB) | ||
65 | +DO_GEN_LD(16u, MO_UW) | ||
66 | +DO_GEN_LD(32u, MO_UL) | ||
67 | +DO_GEN_ST(8, MO_UB) | ||
68 | +DO_GEN_ST(16, MO_UW) | ||
69 | +DO_GEN_ST(32, MO_UL) | ||
70 | + | ||
71 | +#undef DO_GEN_LD | ||
72 | +#undef DO_GEN_ST | ||
73 | + | ||
74 | #endif | ||
75 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
76 | index XXXXXXX..XXXXXXX 100644 | ||
77 | --- a/target/arm/translate.c | ||
78 | +++ b/target/arm/translate.c | ||
79 | @@ -XXX,XX +XXX,XX @@ static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op) | ||
80 | * Internal routines are used for NEON cases where the endianness | ||
81 | * and/or alignment has already been taken into account and manipulated. | ||
82 | */ | 105 | */ |
83 | -static void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, | 106 | @@ -XXX,XX +XXX,XX @@ static void versal_unimp(Versal *s) |
84 | - TCGv_i32 a32, int index, MemOp opc) | 107 | |
85 | +void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, | 108 | versal_unimp_area(s, "psm", &s->mr_ps, |
86 | + TCGv_i32 a32, int index, MemOp opc) | 109 | MM_PSM_START, MM_PSM_END - MM_PSM_START); |
87 | { | 110 | - versal_unimp_area(s, "crl", &s->mr_ps, |
88 | TCGv addr = gen_aa32_addr(s, a32, opc); | 111 | - MM_CRL, MM_CRL_SIZE); |
89 | tcg_gen_qemu_ld_i32(val, addr, index, opc); | 112 | versal_unimp_area(s, "crf", &s->mr_ps, |
90 | tcg_temp_free(addr); | 113 | MM_FPD_CRF, MM_FPD_CRF_SIZE); |
91 | } | 114 | versal_unimp_area(s, "apu", &s->mr_ps, |
92 | 115 | @@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp) | |
93 | -static void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, | 116 | versal_create_efuse(s, pic); |
94 | - TCGv_i32 a32, int index, MemOp opc) | 117 | versal_create_pmc_iou_slcr(s, pic); |
95 | +void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, | 118 | versal_create_ospi(s, pic); |
96 | + TCGv_i32 a32, int index, MemOp opc) | 119 | + versal_create_crl(s, pic); |
97 | { | 120 | versal_map_ddr(s); |
98 | TCGv addr = gen_aa32_addr(s, a32, opc); | 121 | versal_unimp(s); |
99 | tcg_gen_qemu_st_i32(val, addr, index, opc); | 122 | |
100 | tcg_temp_free(addr); | ||
101 | } | ||
102 | |||
103 | -static void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, | ||
104 | - TCGv_i32 a32, int index, MemOp opc) | ||
105 | +void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, | ||
106 | + TCGv_i32 a32, int index, MemOp opc) | ||
107 | { | ||
108 | TCGv addr = gen_aa32_addr(s, a32, opc); | ||
109 | |||
110 | @@ -XXX,XX +XXX,XX @@ static void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, | ||
111 | tcg_temp_free(addr); | ||
112 | } | ||
113 | |||
114 | -static void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, | ||
115 | - TCGv_i32 a32, int index, MemOp opc) | ||
116 | +void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, | ||
117 | + TCGv_i32 a32, int index, MemOp opc) | ||
118 | { | ||
119 | TCGv addr = gen_aa32_addr(s, a32, opc); | ||
120 | |||
121 | @@ -XXX,XX +XXX,XX @@ static void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, | ||
122 | tcg_temp_free(addr); | ||
123 | } | ||
124 | |||
125 | -static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, | ||
126 | - int index, MemOp opc) | ||
127 | +void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, | ||
128 | + int index, MemOp opc) | ||
129 | { | ||
130 | gen_aa32_ld_internal_i32(s, val, a32, index, finalize_memop(s, opc)); | ||
131 | } | ||
132 | |||
133 | -static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, | ||
134 | - int index, MemOp opc) | ||
135 | +void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, | ||
136 | + int index, MemOp opc) | ||
137 | { | ||
138 | gen_aa32_st_internal_i32(s, val, a32, index, finalize_memop(s, opc)); | ||
139 | } | ||
140 | |||
141 | -static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, | ||
142 | - int index, MemOp opc) | ||
143 | +void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, | ||
144 | + int index, MemOp opc) | ||
145 | { | ||
146 | gen_aa32_ld_internal_i64(s, val, a32, index, finalize_memop(s, opc)); | ||
147 | } | ||
148 | |||
149 | -static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, | ||
150 | - int index, MemOp opc) | ||
151 | +void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, | ||
152 | + int index, MemOp opc) | ||
153 | { | ||
154 | gen_aa32_st_internal_i64(s, val, a32, index, finalize_memop(s, opc)); | ||
155 | } | ||
156 | @@ -XXX,XX +XXX,XX @@ static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, | ||
157 | gen_aa32_st_i32(s, val, a32, index, OPC); \ | ||
158 | } | ||
159 | |||
160 | -static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val, | ||
161 | - TCGv_i32 a32, int index) | ||
162 | -{ | ||
163 | - gen_aa32_ld_i64(s, val, a32, index, MO_Q); | ||
164 | -} | ||
165 | - | ||
166 | -static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, | ||
167 | - TCGv_i32 a32, int index) | ||
168 | -{ | ||
169 | - gen_aa32_st_i64(s, val, a32, index, MO_Q); | ||
170 | -} | ||
171 | - | ||
172 | -DO_GEN_LD(8u, MO_UB) | ||
173 | -DO_GEN_LD(16u, MO_UW) | ||
174 | -DO_GEN_LD(32u, MO_UL) | ||
175 | -DO_GEN_ST(8, MO_UB) | ||
176 | -DO_GEN_ST(16, MO_UW) | ||
177 | -DO_GEN_ST(32, MO_UL) | ||
178 | - | ||
179 | static inline void gen_hvc(DisasContext *s, int imm16) | ||
180 | { | ||
181 | /* The pre HVC helper handles cases when HVC gets trapped | ||
182 | -- | 123 | -- |
183 | 2.20.1 | 124 | 2.25.1 |
184 | |||
185 | diff view generated by jsdifflib |
1 | Both os-win32.h and os-posix.h include system header files. Instead | 1 | The Exynos4210 SoC device currently uses a custom device |
---|---|---|---|
2 | of having osdep.h include them inside its 'extern "C"' block, make | 2 | "exynos4210.irq_gate" to model the OR gate that feeds each CPU's IRQ |
3 | these headers handle that themselves, so that we don't include the | 3 | line. We have a standard TYPE_OR_IRQ device for this now, so use |
4 | system headers inside 'extern "C"'. | 4 | that instead. |
5 | 5 | ||
6 | This doesn't fix any current problems, but it's conceptually the | 6 | (This is a migration compatibility break, but that is OK for this |
7 | right way to handle system headers. | 7 | machine type.) |
8 | 8 | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
11 | Message-id: 20220404154658.565020-2-peter.maydell@linaro.org | ||
11 | --- | 12 | --- |
12 | include/qemu/osdep.h | 8 ++++---- | 13 | include/hw/arm/exynos4210.h | 1 + |
13 | include/sysemu/os-posix.h | 8 ++++++++ | 14 | hw/arm/exynos4210.c | 31 ++++++++++++++++--------------- |
14 | include/sysemu/os-win32.h | 8 ++++++++ | 15 | 2 files changed, 17 insertions(+), 15 deletions(-) |
15 | 3 files changed, 20 insertions(+), 4 deletions(-) | ||
16 | 16 | ||
17 | diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h | 17 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h |
18 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/include/qemu/osdep.h | 19 | --- a/include/hw/arm/exynos4210.h |
20 | +++ b/include/qemu/osdep.h | 20 | +++ b/include/hw/arm/exynos4210.h |
21 | @@ -XXX,XX +XXX,XX @@ QEMU_EXTERN_C int daemon(int, int); | 21 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { |
22 | */ | 22 | MemoryRegion bootreg_mem; |
23 | #include "glib-compat.h" | 23 | I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; |
24 | 24 | qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; | |
25 | -#ifdef __cplusplus | 25 | + qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; |
26 | -extern "C" { | 26 | }; |
27 | -#endif | 27 | |
28 | #define TYPE_EXYNOS4210_SOC "exynos4210" | ||
29 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/hw/arm/exynos4210.c | ||
32 | +++ b/hw/arm/exynos4210.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
34 | { | ||
35 | Exynos4210State *s = EXYNOS4210_SOC(socdev); | ||
36 | MemoryRegion *system_mem = get_system_memory(); | ||
37 | - qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; | ||
38 | SysBusDevice *busdev; | ||
39 | DeviceState *dev, *uart[4], *pl330[3]; | ||
40 | int i, n; | ||
41 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
42 | |||
43 | /* IRQ Gate */ | ||
44 | for (i = 0; i < EXYNOS4210_NCPUS; i++) { | ||
45 | - dev = qdev_new("exynos4210.irq_gate"); | ||
46 | - qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS); | ||
47 | - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | ||
48 | - /* Get IRQ Gate input in gate_irq */ | ||
49 | - for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) { | ||
50 | - gate_irq[i][n] = qdev_get_gpio_in(dev, n); | ||
51 | - } | ||
52 | - busdev = SYS_BUS_DEVICE(dev); | ||
28 | - | 53 | - |
29 | #ifdef _WIN32 | 54 | - /* Connect IRQ Gate output to CPU's IRQ line */ |
30 | #include "sysemu/os-win32.h" | 55 | - sysbus_connect_irq(busdev, 0, |
31 | #endif | 56 | - qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); |
32 | @@ -XXX,XX +XXX,XX @@ extern "C" { | 57 | + DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]); |
33 | #include "sysemu/os-posix.h" | 58 | + object_property_set_int(OBJECT(orgate), "num-lines", |
34 | #endif | 59 | + EXYNOS4210_IRQ_GATE_NINPUTS, |
35 | 60 | + &error_abort); | |
36 | +#ifdef __cplusplus | 61 | + qdev_realize(orgate, NULL, &error_abort); |
37 | +extern "C" { | 62 | + qdev_connect_gpio_out(orgate, 0, |
38 | +#endif | 63 | + qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); |
64 | } | ||
65 | |||
66 | /* Private memory region and Internal GIC */ | ||
67 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
68 | sysbus_realize_and_unref(busdev, &error_fatal); | ||
69 | sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); | ||
70 | for (n = 0; n < EXYNOS4210_NCPUS; n++) { | ||
71 | - sysbus_connect_irq(busdev, n, gate_irq[n][0]); | ||
72 | + sysbus_connect_irq(busdev, n, | ||
73 | + qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0)); | ||
74 | } | ||
75 | for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { | ||
76 | s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n); | ||
77 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
78 | /* Map Distributer interface */ | ||
79 | sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR); | ||
80 | for (n = 0; n < EXYNOS4210_NCPUS; n++) { | ||
81 | - sysbus_connect_irq(busdev, n, gate_irq[n][1]); | ||
82 | + sysbus_connect_irq(busdev, n, | ||
83 | + qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1)); | ||
84 | } | ||
85 | for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { | ||
86 | s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n); | ||
87 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj) | ||
88 | object_initialize_child(obj, name, orgate, TYPE_OR_IRQ); | ||
89 | g_free(name); | ||
90 | } | ||
39 | + | 91 | + |
40 | #include "qemu/typedefs.h" | 92 | + for (i = 0; i < ARRAY_SIZE(s->cpu_irq_orgate); i++) { |
41 | 93 | + g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i); | |
42 | /* | 94 | + object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ); |
43 | diff --git a/include/sysemu/os-posix.h b/include/sysemu/os-posix.h | 95 | + } |
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/include/sysemu/os-posix.h | ||
46 | +++ b/include/sysemu/os-posix.h | ||
47 | @@ -XXX,XX +XXX,XX @@ | ||
48 | #include <sys/sysmacros.h> | ||
49 | #endif | ||
50 | |||
51 | +#ifdef __cplusplus | ||
52 | +extern "C" { | ||
53 | +#endif | ||
54 | + | ||
55 | void os_set_line_buffering(void); | ||
56 | void os_set_proc_name(const char *s); | ||
57 | void os_setup_signal_handling(void); | ||
58 | @@ -XXX,XX +XXX,XX @@ static inline void qemu_funlockfile(FILE *f) | ||
59 | funlockfile(f); | ||
60 | } | 96 | } |
61 | 97 | ||
62 | +#ifdef __cplusplus | 98 | static void exynos4210_class_init(ObjectClass *klass, void *data) |
63 | +} | ||
64 | +#endif | ||
65 | + | ||
66 | #endif | ||
67 | diff --git a/include/sysemu/os-win32.h b/include/sysemu/os-win32.h | ||
68 | index XXXXXXX..XXXXXXX 100644 | ||
69 | --- a/include/sysemu/os-win32.h | ||
70 | +++ b/include/sysemu/os-win32.h | ||
71 | @@ -XXX,XX +XXX,XX @@ | ||
72 | #include <windows.h> | ||
73 | #include <ws2tcpip.h> | ||
74 | |||
75 | +#ifdef __cplusplus | ||
76 | +extern "C" { | ||
77 | +#endif | ||
78 | + | ||
79 | #if defined(_WIN64) | ||
80 | /* On w64, setjmp is implemented by _setjmp which needs a second parameter. | ||
81 | * If this parameter is NULL, longjump does no stack unwinding. | ||
82 | @@ -XXX,XX +XXX,XX @@ ssize_t qemu_recv_wrap(int sockfd, void *buf, size_t len, int flags); | ||
83 | ssize_t qemu_recvfrom_wrap(int sockfd, void *buf, size_t len, int flags, | ||
84 | struct sockaddr *addr, socklen_t *addrlen); | ||
85 | |||
86 | +#ifdef __cplusplus | ||
87 | +} | ||
88 | +#endif | ||
89 | + | ||
90 | #endif | ||
91 | -- | 99 | -- |
92 | 2.20.1 | 100 | 2.25.1 |
93 | |||
94 | diff view generated by jsdifflib |
1 | Some of the constant expanders defined in translate.c are generically | 1 | Now we have removed the only use of TYPE_EXYNOS4210_IRQ_GATE we can |
---|---|---|---|
2 | useful and will be used by the separate C files for VFP and Neon once | 2 | delete the device entirely. |
3 | they are created; move the expander definitions to translate.h. | ||
4 | 3 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 5 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Message-id: 20220404154658.565020-3-peter.maydell@linaro.org |
8 | Message-id: 20210430132740.10391-2-peter.maydell@linaro.org | ||
9 | --- | 7 | --- |
10 | target/arm/translate.h | 24 ++++++++++++++++++++++++ | 8 | hw/intc/exynos4210_gic.c | 107 --------------------------------------- |
11 | target/arm/translate.c | 24 ------------------------ | 9 | 1 file changed, 107 deletions(-) |
12 | 2 files changed, 24 insertions(+), 24 deletions(-) | ||
13 | 10 | ||
14 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 11 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c |
15 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/translate.h | 13 | --- a/hw/intc/exynos4210_gic.c |
17 | +++ b/target/arm/translate.h | 14 | +++ b/hw/intc/exynos4210_gic.c |
18 | @@ -XXX,XX +XXX,XX @@ extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; | 15 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_register_types(void) |
19 | extern TCGv_i64 cpu_exclusive_addr; | ||
20 | extern TCGv_i64 cpu_exclusive_val; | ||
21 | |||
22 | +/* | ||
23 | + * Constant expanders for the decoders. | ||
24 | + */ | ||
25 | + | ||
26 | +static inline int negate(DisasContext *s, int x) | ||
27 | +{ | ||
28 | + return -x; | ||
29 | +} | ||
30 | + | ||
31 | +static inline int plus_2(DisasContext *s, int x) | ||
32 | +{ | ||
33 | + return x + 2; | ||
34 | +} | ||
35 | + | ||
36 | +static inline int times_2(DisasContext *s, int x) | ||
37 | +{ | ||
38 | + return x * 2; | ||
39 | +} | ||
40 | + | ||
41 | +static inline int times_4(DisasContext *s, int x) | ||
42 | +{ | ||
43 | + return x * 4; | ||
44 | +} | ||
45 | + | ||
46 | static inline int arm_dc_feature(DisasContext *dc, int feature) | ||
47 | { | ||
48 | return (dc->features & (1ULL << feature)) != 0; | ||
49 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
50 | index XXXXXXX..XXXXXXX 100644 | ||
51 | --- a/target/arm/translate.c | ||
52 | +++ b/target/arm/translate.c | ||
53 | @@ -XXX,XX +XXX,XX @@ static void arm_gen_condlabel(DisasContext *s) | ||
54 | } | ||
55 | } | 16 | } |
56 | 17 | ||
57 | -/* | 18 | type_init(exynos4210_gic_register_types) |
58 | - * Constant expanders for the decoders. | 19 | - |
20 | -/* IRQ OR Gate struct. | ||
21 | - * | ||
22 | - * This device models an OR gate. There are n_in input qdev gpio lines and one | ||
23 | - * output sysbus IRQ line. The output IRQ level is formed as OR between all | ||
24 | - * gpio inputs. | ||
59 | - */ | 25 | - */ |
60 | - | 26 | - |
61 | -static int negate(DisasContext *s, int x) | 27 | -#define TYPE_EXYNOS4210_IRQ_GATE "exynos4210.irq_gate" |
28 | -OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210IRQGateState, EXYNOS4210_IRQ_GATE) | ||
29 | - | ||
30 | -struct Exynos4210IRQGateState { | ||
31 | - SysBusDevice parent_obj; | ||
32 | - | ||
33 | - uint32_t n_in; /* inputs amount */ | ||
34 | - uint32_t *level; /* input levels */ | ||
35 | - qemu_irq out; /* output IRQ */ | ||
36 | -}; | ||
37 | - | ||
38 | -static Property exynos4210_irq_gate_properties[] = { | ||
39 | - DEFINE_PROP_UINT32("n_in", Exynos4210IRQGateState, n_in, 1), | ||
40 | - DEFINE_PROP_END_OF_LIST(), | ||
41 | -}; | ||
42 | - | ||
43 | -static const VMStateDescription vmstate_exynos4210_irq_gate = { | ||
44 | - .name = "exynos4210.irq_gate", | ||
45 | - .version_id = 2, | ||
46 | - .minimum_version_id = 2, | ||
47 | - .fields = (VMStateField[]) { | ||
48 | - VMSTATE_VBUFFER_UINT32(level, Exynos4210IRQGateState, 1, NULL, n_in), | ||
49 | - VMSTATE_END_OF_LIST() | ||
50 | - } | ||
51 | -}; | ||
52 | - | ||
53 | -/* Process a change in IRQ input. */ | ||
54 | -static void exynos4210_irq_gate_handler(void *opaque, int irq, int level) | ||
62 | -{ | 55 | -{ |
63 | - return -x; | 56 | - Exynos4210IRQGateState *s = (Exynos4210IRQGateState *)opaque; |
57 | - uint32_t i; | ||
58 | - | ||
59 | - assert(irq < s->n_in); | ||
60 | - | ||
61 | - s->level[irq] = level; | ||
62 | - | ||
63 | - for (i = 0; i < s->n_in; i++) { | ||
64 | - if (s->level[i] >= 1) { | ||
65 | - qemu_irq_raise(s->out); | ||
66 | - return; | ||
67 | - } | ||
68 | - } | ||
69 | - | ||
70 | - qemu_irq_lower(s->out); | ||
64 | -} | 71 | -} |
65 | - | 72 | - |
66 | -static int plus_2(DisasContext *s, int x) | 73 | -static void exynos4210_irq_gate_reset(DeviceState *d) |
67 | -{ | 74 | -{ |
68 | - return x + 2; | 75 | - Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(d); |
76 | - | ||
77 | - memset(s->level, 0, s->n_in * sizeof(*s->level)); | ||
69 | -} | 78 | -} |
70 | - | 79 | - |
71 | -static int times_2(DisasContext *s, int x) | 80 | -/* |
81 | - * IRQ Gate initialization. | ||
82 | - */ | ||
83 | -static void exynos4210_irq_gate_init(Object *obj) | ||
72 | -{ | 84 | -{ |
73 | - return x * 2; | 85 | - Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(obj); |
86 | - SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
87 | - | ||
88 | - sysbus_init_irq(sbd, &s->out); | ||
74 | -} | 89 | -} |
75 | - | 90 | - |
76 | -static int times_4(DisasContext *s, int x) | 91 | -static void exynos4210_irq_gate_realize(DeviceState *dev, Error **errp) |
77 | -{ | 92 | -{ |
78 | - return x * 4; | 93 | - Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(dev); |
94 | - | ||
95 | - /* Allocate general purpose input signals and connect a handler to each of | ||
96 | - * them */ | ||
97 | - qdev_init_gpio_in(dev, exynos4210_irq_gate_handler, s->n_in); | ||
98 | - | ||
99 | - s->level = g_malloc0(s->n_in * sizeof(*s->level)); | ||
79 | -} | 100 | -} |
80 | - | 101 | - |
81 | /* Flags for the disas_set_da_iss info argument: | 102 | -static void exynos4210_irq_gate_class_init(ObjectClass *klass, void *data) |
82 | * lower bits hold the Rt register number, higher bits are flags. | 103 | -{ |
83 | */ | 104 | - DeviceClass *dc = DEVICE_CLASS(klass); |
105 | - | ||
106 | - dc->reset = exynos4210_irq_gate_reset; | ||
107 | - dc->vmsd = &vmstate_exynos4210_irq_gate; | ||
108 | - device_class_set_props(dc, exynos4210_irq_gate_properties); | ||
109 | - dc->realize = exynos4210_irq_gate_realize; | ||
110 | -} | ||
111 | - | ||
112 | -static const TypeInfo exynos4210_irq_gate_info = { | ||
113 | - .name = TYPE_EXYNOS4210_IRQ_GATE, | ||
114 | - .parent = TYPE_SYS_BUS_DEVICE, | ||
115 | - .instance_size = sizeof(Exynos4210IRQGateState), | ||
116 | - .instance_init = exynos4210_irq_gate_init, | ||
117 | - .class_init = exynos4210_irq_gate_class_init, | ||
118 | -}; | ||
119 | - | ||
120 | -static void exynos4210_irq_gate_register_types(void) | ||
121 | -{ | ||
122 | - type_register_static(&exynos4210_irq_gate_info); | ||
123 | -} | ||
124 | - | ||
125 | -type_init(exynos4210_irq_gate_register_types) | ||
84 | -- | 126 | -- |
85 | 2.20.1 | 127 | 2.25.1 |
86 | |||
87 | diff view generated by jsdifflib |
1 | The WFI insn is not system-mode only, though it doesn't usually make | 1 | The exynos4210 SoC mostly creates its child devices as if it were |
---|---|---|---|
2 | a huge amount of sense for userspace code to execute it. Currently | 2 | board code. This includes the a9mpcore object. Switch that to a |
3 | if you try it in qemu-arm then the helper function will raise an | 3 | new-style "embedded in the state struct" creation, because in the |
4 | EXCP_HLT exception, which is not covered by the switch in cpu_loop() | 4 | next commit we're going to want to refer to the object again further |
5 | and results in an abort: | 5 | down in the exynos4210_realize() function. |
6 | 6 | ||
7 | qemu: unhandled CPU exception 0x10001 - aborting | ||
8 | R00=00000001 R01=408003e4 R02=408003ec R03=000102ec | ||
9 | R04=00010a28 R05=00010158 R06=00087460 R07=00010158 | ||
10 | R08=00000000 R09=00000000 R10=00085b7c R11=408002a4 | ||
11 | R12=408002b8 R13=408002a0 R14=0001057c R15=000102f8 | ||
12 | PSR=60000010 -ZC- A usr32 | ||
13 | qemu:handle_cpu_signal received signal outside vCPU context @ pc=0x7fcbfa4f0a12 | ||
14 | |||
15 | Make the WFI helper function return immediately in the usermode | ||
16 | emulator. This turns WFI into a NOP, which is OK because: | ||
17 | * architecturally "WFI is a NOP" is a permitted implementation | ||
18 | * aarch64 Linux kernels use the SCTLR_EL1.nTWI bit to trap | ||
19 | userspace WFI and NOP it (though aarch32 kernels currently | ||
20 | just let WFI do whatever it would do) | ||
21 | |||
22 | We could in theory make the translate.c code special case user-mode | ||
23 | emulation and NOP the insn entirely rather than making the helper | ||
24 | do nothing, but because no real world code will be trying to | ||
25 | execute WFI we don't care about efficiency and the helper provides | ||
26 | a single place where we can make the change rather than having | ||
27 | to touch multiple places in translate.c and translate-a64.c. | ||
28 | |||
29 | Fixes: https://bugs.launchpad.net/qemu/+bug/1926759 | ||
30 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
31 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
32 | Message-id: 20210430162212.825-1-peter.maydell@linaro.org | 9 | Message-id: 20220404154658.565020-4-peter.maydell@linaro.org |
33 | --- | 10 | --- |
34 | target/arm/op_helper.c | 12 ++++++++++++ | 11 | include/hw/arm/exynos4210.h | 2 ++ |
35 | 1 file changed, 12 insertions(+) | 12 | hw/arm/exynos4210.c | 11 ++++++----- |
13 | 2 files changed, 8 insertions(+), 5 deletions(-) | ||
36 | 14 | ||
37 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | 15 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h |
38 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
39 | --- a/target/arm/op_helper.c | 17 | --- a/include/hw/arm/exynos4210.h |
40 | +++ b/target/arm/op_helper.c | 18 | +++ b/include/hw/arm/exynos4210.h |
41 | @@ -XXX,XX +XXX,XX @@ static inline int check_wfx_trap(CPUARMState *env, bool is_wfe) | 19 | @@ -XXX,XX +XXX,XX @@ |
42 | 20 | ||
43 | void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) | 21 | #include "hw/or-irq.h" |
44 | { | 22 | #include "hw/sysbus.h" |
45 | +#ifdef CONFIG_USER_ONLY | 23 | +#include "hw/cpu/a9mpcore.h" |
46 | + /* | 24 | #include "target/arm/cpu-qom.h" |
47 | + * WFI in the user-mode emulator is technically permitted but not | 25 | #include "qom/object.h" |
48 | + * something any real-world code would do. AArch64 Linux kernels | 26 | |
49 | + * trap it via SCTRL_EL1.nTWI and make it an (expensive) NOP; | 27 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { |
50 | + * AArch32 kernels don't trap it so it will delay a bit. | 28 | I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; |
51 | + * For QEMU, make it NOP here, because trying to raise EXCP_HLT | 29 | qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; |
52 | + * would trigger an abort. | 30 | qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; |
53 | + */ | 31 | + A9MPPrivState a9mpcore; |
54 | + return; | 32 | }; |
55 | +#else | 33 | |
56 | CPUState *cs = env_cpu(env); | 34 | #define TYPE_EXYNOS4210_SOC "exynos4210" |
57 | int target_el = check_wfx_trap(env, false); | 35 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c |
58 | 36 | index XXXXXXX..XXXXXXX 100644 | |
59 | @@ -XXX,XX +XXX,XX @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) | 37 | --- a/hw/arm/exynos4210.c |
60 | cs->exception_index = EXCP_HLT; | 38 | +++ b/hw/arm/exynos4210.c |
61 | cs->halted = 1; | 39 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) |
62 | cpu_loop_exit(cs); | 40 | } |
63 | +#endif | 41 | |
42 | /* Private memory region and Internal GIC */ | ||
43 | - dev = qdev_new(TYPE_A9MPCORE_PRIV); | ||
44 | - qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); | ||
45 | - busdev = SYS_BUS_DEVICE(dev); | ||
46 | - sysbus_realize_and_unref(busdev, &error_fatal); | ||
47 | + qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS); | ||
48 | + busdev = SYS_BUS_DEVICE(&s->a9mpcore); | ||
49 | + sysbus_realize(busdev, &error_fatal); | ||
50 | sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); | ||
51 | for (n = 0; n < EXYNOS4210_NCPUS; n++) { | ||
52 | sysbus_connect_irq(busdev, n, | ||
53 | qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0)); | ||
54 | } | ||
55 | for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { | ||
56 | - s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n); | ||
57 | + s->irqs.int_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->a9mpcore), n); | ||
58 | } | ||
59 | |||
60 | /* Cache controller */ | ||
61 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj) | ||
62 | g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i); | ||
63 | object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ); | ||
64 | } | ||
65 | + | ||
66 | + object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); | ||
64 | } | 67 | } |
65 | 68 | ||
66 | void HELPER(wfe)(CPUARMState *env) | 69 | static void exynos4210_class_init(ObjectClass *klass, void *data) |
67 | -- | 70 | -- |
68 | 2.20.1 | 71 | 2.25.1 |
69 | |||
70 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The only time we use the int_gic_irq[] array in the Exynos4210Irq | ||
2 | struct is in the exynos4210_realize() function: we initialize it with | ||
3 | the GPIO inputs of the a9mpcore device, and then a bit later on we | ||
4 | connect those to the outputs of the internal combiner. Now that the | ||
5 | a9mpcore object is easily accessible as s->a9mpcore we can make the | ||
6 | connection directly from one device to the other without going via | ||
7 | this array. | ||
1 | 8 | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20220404154658.565020-5-peter.maydell@linaro.org | ||
12 | --- | ||
13 | include/hw/arm/exynos4210.h | 1 - | ||
14 | hw/arm/exynos4210.c | 6 ++---- | ||
15 | 2 files changed, 2 insertions(+), 5 deletions(-) | ||
16 | |||
17 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/include/hw/arm/exynos4210.h | ||
20 | +++ b/include/hw/arm/exynos4210.h | ||
21 | @@ -XXX,XX +XXX,XX @@ | ||
22 | typedef struct Exynos4210Irq { | ||
23 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
24 | qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; | ||
25 | - qemu_irq int_gic_irq[EXYNOS4210_INT_GIC_NIRQ]; | ||
26 | qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ]; | ||
27 | qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
28 | } Exynos4210Irq; | ||
29 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/hw/arm/exynos4210.c | ||
32 | +++ b/hw/arm/exynos4210.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
34 | sysbus_connect_irq(busdev, n, | ||
35 | qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0)); | ||
36 | } | ||
37 | - for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { | ||
38 | - s->irqs.int_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->a9mpcore), n); | ||
39 | - } | ||
40 | |||
41 | /* Cache controller */ | ||
42 | sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); | ||
43 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
44 | busdev = SYS_BUS_DEVICE(dev); | ||
45 | sysbus_realize_and_unref(busdev, &error_fatal); | ||
46 | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { | ||
47 | - sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]); | ||
48 | + sysbus_connect_irq(busdev, n, | ||
49 | + qdev_get_gpio_in(DEVICE(&s->a9mpcore), n)); | ||
50 | } | ||
51 | exynos4210_combiner_get_gpioin(&s->irqs, dev, 0); | ||
52 | sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); | ||
53 | -- | ||
54 | 2.25.1 | diff view generated by jsdifflib |
1 | The unallocated_encoding() function is the same in both | 1 | The exynos4210 code currently has two very similar arrays of IRQs: |
---|---|---|---|
2 | translate-a64.c and translate.c; make the translate.c function global | ||
3 | and drop the translate-a64.c version. To do this we need to also | ||
4 | share gen_exception_insn(), which currently exists in two slightly | ||
5 | different versions for A32 and A64: merge those into a single | ||
6 | function that can work for both. | ||
7 | 2 | ||
8 | This will be useful for splitting up translate.c, which will require | 3 | * board_irqs is a field of the Exynos4210Irq struct which is filled |
9 | unallocated_encoding() to no longer be file-local. It's also | 4 | in by exynos4210_init_board_irqs() with the appropriate qemu_irqs |
10 | hopefully less confusing to have only one version of the function | 5 | for each IRQ the board/SoC can assert |
11 | rather than two. | 6 | * irq_table is a set of qemu_irqs pointed to from the |
7 | Exynos4210State struct. It's allocated in exynos4210_init_irq, | ||
8 | and the only behaviour these irqs have is that they pass on the | ||
9 | level to the equivalent board_irqs[] irq | ||
10 | |||
11 | The extra indirection through irq_table is unnecessary, so coalesce | ||
12 | these into a single irq_table[] array as a direct field in | ||
13 | Exynos4210State which exynos4210_init_board_irqs() fills in. | ||
12 | 14 | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
15 | Message-id: 20210430132740.10391-3-peter.maydell@linaro.org | 17 | Message-id: 20220404154658.565020-6-peter.maydell@linaro.org |
16 | --- | 18 | --- |
17 | target/arm/translate-a64.h | 2 -- | 19 | include/hw/arm/exynos4210.h | 8 ++------ |
18 | target/arm/translate.h | 3 +++ | 20 | hw/arm/exynos4210.c | 6 +----- |
19 | target/arm/translate-a64.c | 15 --------------- | 21 | hw/intc/exynos4210_gic.c | 32 ++++++++------------------------ |
20 | target/arm/translate.c | 14 +++++++++----- | 22 | 3 files changed, 11 insertions(+), 35 deletions(-) |
21 | 4 files changed, 12 insertions(+), 22 deletions(-) | ||
22 | 23 | ||
23 | diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h | 24 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h |
24 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/target/arm/translate-a64.h | 26 | --- a/include/hw/arm/exynos4210.h |
26 | +++ b/target/arm/translate-a64.h | 27 | +++ b/include/hw/arm/exynos4210.h |
27 | @@ -XXX,XX +XXX,XX @@ | 28 | @@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq { |
28 | #ifndef TARGET_ARM_TRANSLATE_A64_H | 29 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; |
29 | #define TARGET_ARM_TRANSLATE_A64_H | 30 | qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; |
30 | 31 | qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ]; | |
31 | -void unallocated_encoding(DisasContext *s); | 32 | - qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; |
33 | } Exynos4210Irq; | ||
34 | |||
35 | struct Exynos4210State { | ||
36 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { | ||
37 | /*< public >*/ | ||
38 | ARMCPU *cpu[EXYNOS4210_NCPUS]; | ||
39 | Exynos4210Irq irqs; | ||
40 | - qemu_irq *irq_table; | ||
41 | + qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
42 | |||
43 | MemoryRegion chipid_mem; | ||
44 | MemoryRegion iram_mem; | ||
45 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC) | ||
46 | void exynos4210_write_secondary(ARMCPU *cpu, | ||
47 | const struct arm_boot_info *info); | ||
48 | |||
49 | -/* Initialize exynos4210 IRQ subsystem stub */ | ||
50 | -qemu_irq *exynos4210_init_irq(Exynos4210Irq *env); | ||
32 | - | 51 | - |
33 | #define unsupported_encoding(s, insn) \ | 52 | /* Initialize board IRQs. |
34 | do { \ | 53 | * These IRQs contain splitted Int/External Combiner and External Gic IRQs */ |
35 | qemu_log_mask(LOG_UNIMP, \ | 54 | -void exynos4210_init_board_irqs(Exynos4210Irq *s); |
36 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 55 | +void exynos4210_init_board_irqs(Exynos4210State *s); |
56 | |||
57 | /* Get IRQ number from exynos4210 IRQ subsystem stub. | ||
58 | * To identify IRQ source use internal combiner group and bit number | ||
59 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | 60 | index XXXXXXX..XXXXXXX 100644 |
38 | --- a/target/arm/translate.h | 61 | --- a/hw/arm/exynos4210.c |
39 | +++ b/target/arm/translate.h | 62 | +++ b/hw/arm/exynos4210.c |
40 | @@ -XXX,XX +XXX,XX @@ void arm_free_cc(DisasCompare *cmp); | 63 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) |
41 | void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); | 64 | qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); |
42 | void arm_gen_test_cc(int cc, TCGLabel *label); | 65 | } |
43 | MemOp pow2_align(unsigned i); | 66 | |
44 | +void unallocated_encoding(DisasContext *s); | 67 | - /*** IRQs ***/ |
45 | +void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, | 68 | - |
46 | + uint32_t syn, uint32_t target_el); | 69 | - s->irq_table = exynos4210_init_irq(&s->irqs); |
47 | 70 | - | |
48 | /* Return state of Alternate Half-precision flag, caller frees result */ | 71 | /* IRQ Gate */ |
49 | static inline TCGv_i32 get_ahp_flag(void) | 72 | for (i = 0; i < EXYNOS4210_NCPUS; i++) { |
50 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 73 | DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]); |
74 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
75 | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); | ||
76 | |||
77 | /* Initialize board IRQs. */ | ||
78 | - exynos4210_init_board_irqs(&s->irqs); | ||
79 | + exynos4210_init_board_irqs(s); | ||
80 | |||
81 | /*** Memory ***/ | ||
82 | |||
83 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | ||
51 | index XXXXXXX..XXXXXXX 100644 | 84 | index XXXXXXX..XXXXXXX 100644 |
52 | --- a/target/arm/translate-a64.c | 85 | --- a/hw/intc/exynos4210_gic.c |
53 | +++ b/target/arm/translate-a64.c | 86 | +++ b/hw/intc/exynos4210_gic.c |
54 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp) | 87 | @@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { |
55 | s->base.is_jmp = DISAS_NORETURN; | 88 | #define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100 |
56 | } | 89 | #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000 |
57 | 90 | ||
58 | -static void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, | 91 | -static void exynos4210_irq_handler(void *opaque, int irq, int level) |
59 | - uint32_t syndrome, uint32_t target_el) | ||
60 | -{ | 92 | -{ |
61 | - gen_a64_set_pc_im(pc); | 93 | - Exynos4210Irq *s = (Exynos4210Irq *)opaque; |
62 | - gen_exception(excp, syndrome, target_el); | 94 | - |
63 | - s->base.is_jmp = DISAS_NORETURN; | 95 | - /* Bypass */ |
96 | - qemu_set_irq(s->board_irqs[irq], level); | ||
64 | -} | 97 | -} |
65 | - | 98 | - |
66 | static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome) | 99 | -/* |
100 | - * Initialize exynos4210 IRQ subsystem stub. | ||
101 | - */ | ||
102 | -qemu_irq *exynos4210_init_irq(Exynos4210Irq *s) | ||
103 | -{ | ||
104 | - return qemu_allocate_irqs(exynos4210_irq_handler, s, | ||
105 | - EXYNOS4210_MAX_INT_COMBINER_IN_IRQ); | ||
106 | -} | ||
107 | - | ||
108 | /* | ||
109 | * Initialize board IRQs. | ||
110 | * These IRQs contain splitted Int/External Combiner and External Gic IRQs. | ||
111 | */ | ||
112 | -void exynos4210_init_board_irqs(Exynos4210Irq *s) | ||
113 | +void exynos4210_init_board_irqs(Exynos4210State *s) | ||
67 | { | 114 | { |
68 | TCGv_i32 tcg_syn; | 115 | uint32_t grp, bit, irq_id, n; |
69 | @@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) | 116 | + Exynos4210Irq *is = &s->irqs; |
117 | |||
118 | for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { | ||
119 | irq_id = 0; | ||
120 | @@ -XXX,XX +XXX,XX @@ void exynos4210_init_board_irqs(Exynos4210Irq *s) | ||
121 | irq_id = EXT_GIC_ID_MCT_G1; | ||
122 | } | ||
123 | if (irq_id) { | ||
124 | - s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n], | ||
125 | - s->ext_gic_irq[irq_id-32]); | ||
126 | + s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
127 | + is->ext_gic_irq[irq_id - 32]); | ||
128 | } else { | ||
129 | - s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n], | ||
130 | - s->ext_combiner_irq[n]); | ||
131 | + s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
132 | + is->ext_combiner_irq[n]); | ||
133 | } | ||
134 | } | ||
135 | for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { | ||
136 | @@ -XXX,XX +XXX,XX @@ void exynos4210_init_board_irqs(Exynos4210Irq *s) | ||
137 | EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; | ||
138 | |||
139 | if (irq_id) { | ||
140 | - s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n], | ||
141 | - s->ext_gic_irq[irq_id-32]); | ||
142 | + s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
143 | + is->ext_gic_irq[irq_id - 32]); | ||
144 | } | ||
70 | } | 145 | } |
71 | } | 146 | } |
72 | |||
73 | -void unallocated_encoding(DisasContext *s) | ||
74 | -{ | ||
75 | - /* Unallocated and reserved encodings are uncategorized */ | ||
76 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), | ||
77 | - default_exception_el(s)); | ||
78 | -} | ||
79 | - | ||
80 | static void init_tmp_a64_array(DisasContext *s) | ||
81 | { | ||
82 | #ifdef CONFIG_DEBUG_TCG | ||
83 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
84 | index XXXXXXX..XXXXXXX 100644 | ||
85 | --- a/target/arm/translate.c | ||
86 | +++ b/target/arm/translate.c | ||
87 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp) | ||
88 | s->base.is_jmp = DISAS_NORETURN; | ||
89 | } | ||
90 | |||
91 | -static void gen_exception_insn(DisasContext *s, uint32_t pc, int excp, | ||
92 | - int syn, uint32_t target_el) | ||
93 | +void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, | ||
94 | + uint32_t syn, uint32_t target_el) | ||
95 | { | ||
96 | - gen_set_condexec(s); | ||
97 | - gen_set_pc_im(s, pc); | ||
98 | + if (s->aarch64) { | ||
99 | + gen_a64_set_pc_im(pc); | ||
100 | + } else { | ||
101 | + gen_set_condexec(s); | ||
102 | + gen_set_pc_im(s, pc); | ||
103 | + } | ||
104 | gen_exception(excp, syn, target_el); | ||
105 | s->base.is_jmp = DISAS_NORETURN; | ||
106 | } | ||
107 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) | ||
108 | s->base.is_jmp = DISAS_NORETURN; | ||
109 | } | ||
110 | |||
111 | -static void unallocated_encoding(DisasContext *s) | ||
112 | +void unallocated_encoding(DisasContext *s) | ||
113 | { | ||
114 | /* Unallocated and reserved encodings are uncategorized */ | ||
115 | gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), | ||
116 | -- | 147 | -- |
117 | 2.20.1 | 148 | 2.25.1 |
118 | |||
119 | diff view generated by jsdifflib |
1 | The MPS2 SCC device doesn't have any documentation of its properties; | 1 | Fix a missing set of spaces around '-' in the definition of |
---|---|---|---|
2 | add a "QEMU interface" format comment describing them. | 2 | combiner_grp_to_gic_id[]. We're about to move this code, so |
3 | fix the style issue first to keep checkpatch happy with the | ||
4 | code-motion patch. | ||
3 | 5 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Message-id: 20210504120912.23094-2-peter.maydell@linaro.org | 8 | Message-id: 20220404154658.565020-7-peter.maydell@linaro.org |
7 | --- | 9 | --- |
8 | include/hw/misc/mps2-scc.h | 12 ++++++++++++ | 10 | hw/intc/exynos4210_gic.c | 2 +- |
9 | 1 file changed, 12 insertions(+) | 11 | 1 file changed, 1 insertion(+), 1 deletion(-) |
10 | 12 | ||
11 | diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h | 13 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c |
12 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/include/hw/misc/mps2-scc.h | 15 | --- a/hw/intc/exynos4210_gic.c |
14 | +++ b/include/hw/misc/mps2-scc.h | 16 | +++ b/hw/intc/exynos4210_gic.c |
15 | @@ -XXX,XX +XXX,XX @@ | 17 | @@ -XXX,XX +XXX,XX @@ enum ExtInt { |
16 | * (at your option) any later version. | ||
17 | */ | 18 | */ |
18 | 19 | ||
19 | +/* | 20 | static const uint32_t |
20 | + * This is a model of the Serial Communication Controller (SCC) | 21 | -combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { |
21 | + * block found in most MPS FPGA images. | 22 | +combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { |
22 | + * | 23 | /* int combiner groups 16-19 */ |
23 | + * QEMU interface: | 24 | { }, { }, { }, { }, |
24 | + * + sysbus MMIO region 0: the register bank | 25 | /* int combiner group 20 */ |
25 | + * + QOM property "scc-cfg4": value of the read-only CFG4 register | ||
26 | + * + QOM property "scc-aid": value of the read-only SCC_AID register | ||
27 | + * + QOM property "scc-id": value of the read-only SCC_ID register | ||
28 | + * + QOM property array "oscclk": reset values of the OSCCLK registers | ||
29 | + * (which are accessed via the SYS_CFG channel provided by this device) | ||
30 | + */ | ||
31 | #ifndef MPS2_SCC_H | ||
32 | #define MPS2_SCC_H | ||
33 | |||
34 | -- | 26 | -- |
35 | 2.20.1 | 27 | 2.25.1 |
36 | |||
37 | diff view generated by jsdifflib |
1 | Currently the trans functions for m-nocp.decode all live in | 1 | The function exynos4210_init_board_irqs() currently lives in |
---|---|---|---|
2 | translate-vfp.inc.c; move them out into their own translation unit, | 2 | exynos4210_gic.c, but it isn't really part of the exynos4210.gic |
3 | translate-m-nocp.c. | 3 | device -- it is a function that implements (some of) the wiring up of |
4 | 4 | interrupts between the SoC's GIC and combiner components. This means | |
5 | The trans_* functions here are pure code motion with no changes. | 5 | it fits better in exynos4210.c, which is the SoC-level code. Move it |
6 | there. Similarly, exynos4210_git_irq() is used almost only in the | ||
7 | SoC-level code, so move it too. | ||
6 | 8 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20210430132740.10391-5-peter.maydell@linaro.org | 11 | Message-id: 20220404154658.565020-8-peter.maydell@linaro.org |
10 | --- | 12 | --- |
11 | target/arm/translate-a32.h | 3 + | 13 | include/hw/arm/exynos4210.h | 4 - |
12 | target/arm/translate-m-nocp.c | 221 +++++++++++++++++++++++++++++++++ | 14 | hw/arm/exynos4210.c | 202 +++++++++++++++++++++++++++++++++++ |
13 | target/arm/translate.c | 1 - | 15 | hw/intc/exynos4210_gic.c | 204 ------------------------------------ |
14 | target/arm/translate-vfp.c.inc | 196 ----------------------------- | 16 | 3 files changed, 202 insertions(+), 208 deletions(-) |
15 | target/arm/meson.build | 3 +- | ||
16 | 5 files changed, 226 insertions(+), 198 deletions(-) | ||
17 | create mode 100644 target/arm/translate-m-nocp.c | ||
18 | 17 | ||
19 | diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h | 18 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h |
20 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/target/arm/translate-a32.h | 20 | --- a/include/hw/arm/exynos4210.h |
22 | +++ b/target/arm/translate-a32.h | 21 | +++ b/include/hw/arm/exynos4210.h |
22 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC) | ||
23 | void exynos4210_write_secondary(ARMCPU *cpu, | ||
24 | const struct arm_boot_info *info); | ||
25 | |||
26 | -/* Initialize board IRQs. | ||
27 | - * These IRQs contain splitted Int/External Combiner and External Gic IRQs */ | ||
28 | -void exynos4210_init_board_irqs(Exynos4210State *s); | ||
29 | - | ||
30 | /* Get IRQ number from exynos4210 IRQ subsystem stub. | ||
31 | * To identify IRQ source use internal combiner group and bit number | ||
32 | * grp - group number | ||
33 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/hw/arm/exynos4210.c | ||
36 | +++ b/hw/arm/exynos4210.c | ||
23 | @@ -XXX,XX +XXX,XX @@ | 37 | @@ -XXX,XX +XXX,XX @@ |
24 | #ifndef TARGET_ARM_TRANSLATE_A64_H | 38 | #define EXYNOS4210_PL330_BASE1_ADDR 0x12690000 |
25 | #define TARGET_ARM_TRANSLATE_A64_H | 39 | #define EXYNOS4210_PL330_BASE2_ADDR 0x12850000 |
26 | 40 | ||
27 | +/* Prototypes for autogenerated disassembler functions */ | 41 | +enum ExtGicId { |
28 | +bool disas_m_nocp(DisasContext *dc, uint32_t insn); | 42 | + EXT_GIC_ID_MDMA_LCD0 = 66, |
29 | + | 43 | + EXT_GIC_ID_PDMA0, |
30 | void load_reg_var(DisasContext *s, TCGv_i32 var, int reg); | 44 | + EXT_GIC_ID_PDMA1, |
31 | void arm_gen_condlabel(DisasContext *s); | 45 | + EXT_GIC_ID_TIMER0, |
32 | bool vfp_access_check(DisasContext *s); | 46 | + EXT_GIC_ID_TIMER1, |
33 | diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c | 47 | + EXT_GIC_ID_TIMER2, |
34 | new file mode 100644 | 48 | + EXT_GIC_ID_TIMER3, |
35 | index XXXXXXX..XXXXXXX | 49 | + EXT_GIC_ID_TIMER4, |
36 | --- /dev/null | 50 | + EXT_GIC_ID_MCT_L0, |
37 | +++ b/target/arm/translate-m-nocp.c | 51 | + EXT_GIC_ID_WDT, |
38 | @@ -XXX,XX +XXX,XX @@ | 52 | + EXT_GIC_ID_RTC_ALARM, |
53 | + EXT_GIC_ID_RTC_TIC, | ||
54 | + EXT_GIC_ID_GPIO_XB, | ||
55 | + EXT_GIC_ID_GPIO_XA, | ||
56 | + EXT_GIC_ID_MCT_L1, | ||
57 | + EXT_GIC_ID_IEM_APC, | ||
58 | + EXT_GIC_ID_IEM_IEC, | ||
59 | + EXT_GIC_ID_NFC, | ||
60 | + EXT_GIC_ID_UART0, | ||
61 | + EXT_GIC_ID_UART1, | ||
62 | + EXT_GIC_ID_UART2, | ||
63 | + EXT_GIC_ID_UART3, | ||
64 | + EXT_GIC_ID_UART4, | ||
65 | + EXT_GIC_ID_MCT_G0, | ||
66 | + EXT_GIC_ID_I2C0, | ||
67 | + EXT_GIC_ID_I2C1, | ||
68 | + EXT_GIC_ID_I2C2, | ||
69 | + EXT_GIC_ID_I2C3, | ||
70 | + EXT_GIC_ID_I2C4, | ||
71 | + EXT_GIC_ID_I2C5, | ||
72 | + EXT_GIC_ID_I2C6, | ||
73 | + EXT_GIC_ID_I2C7, | ||
74 | + EXT_GIC_ID_SPI0, | ||
75 | + EXT_GIC_ID_SPI1, | ||
76 | + EXT_GIC_ID_SPI2, | ||
77 | + EXT_GIC_ID_MCT_G1, | ||
78 | + EXT_GIC_ID_USB_HOST, | ||
79 | + EXT_GIC_ID_USB_DEVICE, | ||
80 | + EXT_GIC_ID_MODEMIF, | ||
81 | + EXT_GIC_ID_HSMMC0, | ||
82 | + EXT_GIC_ID_HSMMC1, | ||
83 | + EXT_GIC_ID_HSMMC2, | ||
84 | + EXT_GIC_ID_HSMMC3, | ||
85 | + EXT_GIC_ID_SDMMC, | ||
86 | + EXT_GIC_ID_MIPI_CSI_4LANE, | ||
87 | + EXT_GIC_ID_MIPI_DSI_4LANE, | ||
88 | + EXT_GIC_ID_MIPI_CSI_2LANE, | ||
89 | + EXT_GIC_ID_MIPI_DSI_2LANE, | ||
90 | + EXT_GIC_ID_ONENAND_AUDI, | ||
91 | + EXT_GIC_ID_ROTATOR, | ||
92 | + EXT_GIC_ID_FIMC0, | ||
93 | + EXT_GIC_ID_FIMC1, | ||
94 | + EXT_GIC_ID_FIMC2, | ||
95 | + EXT_GIC_ID_FIMC3, | ||
96 | + EXT_GIC_ID_JPEG, | ||
97 | + EXT_GIC_ID_2D, | ||
98 | + EXT_GIC_ID_PCIe, | ||
99 | + EXT_GIC_ID_MIXER, | ||
100 | + EXT_GIC_ID_HDMI, | ||
101 | + EXT_GIC_ID_HDMI_I2C, | ||
102 | + EXT_GIC_ID_MFC, | ||
103 | + EXT_GIC_ID_TVENC, | ||
104 | +}; | ||
105 | + | ||
106 | +enum ExtInt { | ||
107 | + EXT_GIC_ID_EXTINT0 = 48, | ||
108 | + EXT_GIC_ID_EXTINT1, | ||
109 | + EXT_GIC_ID_EXTINT2, | ||
110 | + EXT_GIC_ID_EXTINT3, | ||
111 | + EXT_GIC_ID_EXTINT4, | ||
112 | + EXT_GIC_ID_EXTINT5, | ||
113 | + EXT_GIC_ID_EXTINT6, | ||
114 | + EXT_GIC_ID_EXTINT7, | ||
115 | + EXT_GIC_ID_EXTINT8, | ||
116 | + EXT_GIC_ID_EXTINT9, | ||
117 | + EXT_GIC_ID_EXTINT10, | ||
118 | + EXT_GIC_ID_EXTINT11, | ||
119 | + EXT_GIC_ID_EXTINT12, | ||
120 | + EXT_GIC_ID_EXTINT13, | ||
121 | + EXT_GIC_ID_EXTINT14, | ||
122 | + EXT_GIC_ID_EXTINT15 | ||
123 | +}; | ||
124 | + | ||
39 | +/* | 125 | +/* |
40 | + * ARM translation: M-profile NOCP special-case instructions | 126 | + * External GIC sources which are not from External Interrupt Combiner or |
41 | + * | 127 | + * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ, |
42 | + * Copyright (c) 2020 Linaro, Ltd. | 128 | + * which is INTG16 in Internal Interrupt Combiner. |
43 | + * | ||
44 | + * This library is free software; you can redistribute it and/or | ||
45 | + * modify it under the terms of the GNU Lesser General Public | ||
46 | + * License as published by the Free Software Foundation; either | ||
47 | + * version 2.1 of the License, or (at your option) any later version. | ||
48 | + * | ||
49 | + * This library is distributed in the hope that it will be useful, | ||
50 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
51 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
52 | + * Lesser General Public License for more details. | ||
53 | + * | ||
54 | + * You should have received a copy of the GNU Lesser General Public | ||
55 | + * License along with this library; if not, see <http://www.gnu.org/licenses/>. | ||
56 | + */ | 129 | + */ |
57 | + | 130 | + |
58 | +#include "qemu/osdep.h" | 131 | +static const uint32_t |
59 | +#include "tcg/tcg-op.h" | 132 | +combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { |
60 | +#include "translate.h" | 133 | + /* int combiner groups 16-19 */ |
61 | +#include "translate-a32.h" | 134 | + { }, { }, { }, { }, |
62 | + | 135 | + /* int combiner group 20 */ |
63 | +#include "decode-m-nocp.c.inc" | 136 | + { 0, EXT_GIC_ID_MDMA_LCD0 }, |
137 | + /* int combiner group 21 */ | ||
138 | + { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 }, | ||
139 | + /* int combiner group 22 */ | ||
140 | + { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2, | ||
141 | + EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 }, | ||
142 | + /* int combiner group 23 */ | ||
143 | + { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC }, | ||
144 | + /* int combiner group 24 */ | ||
145 | + { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA }, | ||
146 | + /* int combiner group 25 */ | ||
147 | + { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC }, | ||
148 | + /* int combiner group 26 */ | ||
149 | + { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3, | ||
150 | + EXT_GIC_ID_UART4 }, | ||
151 | + /* int combiner group 27 */ | ||
152 | + { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3, | ||
153 | + EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6, | ||
154 | + EXT_GIC_ID_I2C7 }, | ||
155 | + /* int combiner group 28 */ | ||
156 | + { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST}, | ||
157 | + /* int combiner group 29 */ | ||
158 | + { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2, | ||
159 | + EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC }, | ||
160 | + /* int combiner group 30 */ | ||
161 | + { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE }, | ||
162 | + /* int combiner group 31 */ | ||
163 | + { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE }, | ||
164 | + /* int combiner group 32 */ | ||
165 | + { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 }, | ||
166 | + /* int combiner group 33 */ | ||
167 | + { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 }, | ||
168 | + /* int combiner group 34 */ | ||
169 | + { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, | ||
170 | + /* int combiner group 35 */ | ||
171 | + { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
172 | + /* int combiner group 36 */ | ||
173 | + { EXT_GIC_ID_MIXER }, | ||
174 | + /* int combiner group 37 */ | ||
175 | + { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6, | ||
176 | + EXT_GIC_ID_EXTINT7 }, | ||
177 | + /* groups 38-50 */ | ||
178 | + { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, | ||
179 | + /* int combiner group 51 */ | ||
180 | + { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
181 | + /* group 52 */ | ||
182 | + { }, | ||
183 | + /* int combiner group 53 */ | ||
184 | + { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
185 | + /* groups 54-63 */ | ||
186 | + { }, { }, { }, { }, { }, { }, { }, { }, { }, { } | ||
187 | +}; | ||
64 | + | 188 | + |
65 | +/* | 189 | +/* |
66 | + * Decode VLLDM and VLSTM are nonstandard because: | 190 | + * Initialize board IRQs. |
67 | + * * if there is no FPU then these insns must NOP in | 191 | + * These IRQs contain splitted Int/External Combiner and External Gic IRQs. |
68 | + * Secure state and UNDEF in Nonsecure state | ||
69 | + * * if there is an FPU then these insns do not have | ||
70 | + * the usual behaviour that vfp_access_check() provides of | ||
71 | + * being controlled by CPACR/NSACR enable bits or the | ||
72 | + * lazy-stacking logic. | ||
73 | + */ | 192 | + */ |
74 | +static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a) | 193 | +static void exynos4210_init_board_irqs(Exynos4210State *s) |
75 | +{ | 194 | +{ |
76 | + TCGv_i32 fptr; | 195 | + uint32_t grp, bit, irq_id, n; |
77 | + | 196 | + Exynos4210Irq *is = &s->irqs; |
78 | + if (!arm_dc_feature(s, ARM_FEATURE_M) || | 197 | + |
79 | + !arm_dc_feature(s, ARM_FEATURE_V8)) { | 198 | + for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { |
80 | + return false; | 199 | + irq_id = 0; |
81 | + } | 200 | + if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) || |
82 | + | 201 | + n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) { |
83 | + if (a->op) { | 202 | + /* MCT_G0 is passed to External GIC */ |
84 | + /* | 203 | + irq_id = EXT_GIC_ID_MCT_G0; |
85 | + * T2 encoding ({D0-D31} reglist): v8.1M and up. We choose not | ||
86 | + * to take the IMPDEF option to make memory accesses to the stack | ||
87 | + * slots that correspond to the D16-D31 registers (discarding | ||
88 | + * read data and writing UNKNOWN values), so for us the T2 | ||
89 | + * encoding behaves identically to the T1 encoding. | ||
90 | + */ | ||
91 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
92 | + return false; | ||
93 | + } | 204 | + } |
94 | + } else { | 205 | + if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) || |
95 | + /* | 206 | + n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) { |
96 | + * T1 encoding ({D0-D15} reglist); undef if we have 32 Dregs. | 207 | + /* MCT_G1 is passed to External and GIC */ |
97 | + * This is currently architecturally impossible, but we add the | 208 | + irq_id = EXT_GIC_ID_MCT_G1; |
98 | + * check to stay in line with the pseudocode. Note that we must | 209 | + } |
99 | + * emit code for the UNDEF so it takes precedence over the NOCP. | 210 | + if (irq_id) { |
100 | + */ | 211 | + s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], |
101 | + if (dc_isar_feature(aa32_simd_r32, s)) { | 212 | + is->ext_gic_irq[irq_id - 32]); |
102 | + unallocated_encoding(s); | 213 | + } else { |
103 | + return true; | 214 | + s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], |
215 | + is->ext_combiner_irq[n]); | ||
104 | + } | 216 | + } |
105 | + } | 217 | + } |
106 | + | 218 | + for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { |
107 | + /* | 219 | + /* these IDs are passed to Internal Combiner and External GIC */ |
108 | + * If not secure, UNDEF. We must emit code for this | 220 | + grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n); |
109 | + * rather than returning false so that this takes | 221 | + bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); |
110 | + * precedence over the m-nocp.decode NOCP fallback. | 222 | + irq_id = combiner_grp_to_gic_id[grp - |
111 | + */ | 223 | + EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; |
112 | + if (!s->v8m_secure) { | 224 | + |
113 | + unallocated_encoding(s); | 225 | + if (irq_id) { |
114 | + return true; | 226 | + s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], |
227 | + is->ext_gic_irq[irq_id - 32]); | ||
228 | + } | ||
115 | + } | 229 | + } |
116 | + /* If no fpu, NOP. */ | ||
117 | + if (!dc_isar_feature(aa32_vfp, s)) { | ||
118 | + return true; | ||
119 | + } | ||
120 | + | ||
121 | + fptr = load_reg(s, a->rn); | ||
122 | + if (a->l) { | ||
123 | + gen_helper_v7m_vlldm(cpu_env, fptr); | ||
124 | + } else { | ||
125 | + gen_helper_v7m_vlstm(cpu_env, fptr); | ||
126 | + } | ||
127 | + tcg_temp_free_i32(fptr); | ||
128 | + | ||
129 | + /* End the TB, because we have updated FP control bits */ | ||
130 | + s->base.is_jmp = DISAS_UPDATE_EXIT; | ||
131 | + return true; | ||
132 | +} | 230 | +} |
133 | + | 231 | + |
134 | +static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) | 232 | +/* |
233 | + * Get IRQ number from exynos4210 IRQ subsystem stub. | ||
234 | + * To identify IRQ source use internal combiner group and bit number | ||
235 | + * grp - group number | ||
236 | + * bit - bit number inside group | ||
237 | + */ | ||
238 | +uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) | ||
135 | +{ | 239 | +{ |
136 | + int btmreg, topreg; | 240 | + return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); |
137 | + TCGv_i64 zero; | ||
138 | + TCGv_i32 aspen, sfpa; | ||
139 | + | ||
140 | + if (!dc_isar_feature(aa32_m_sec_state, s)) { | ||
141 | + /* Before v8.1M, fall through in decode to NOCP check */ | ||
142 | + return false; | ||
143 | + } | ||
144 | + | ||
145 | + /* Explicitly UNDEF because this takes precedence over NOCP */ | ||
146 | + if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) { | ||
147 | + unallocated_encoding(s); | ||
148 | + return true; | ||
149 | + } | ||
150 | + | ||
151 | + if (!dc_isar_feature(aa32_vfp_simd, s)) { | ||
152 | + /* NOP if we have neither FP nor MVE */ | ||
153 | + return true; | ||
154 | + } | ||
155 | + | ||
156 | + /* | ||
157 | + * If FPCCR.ASPEN != 0 && CONTROL_S.SFPA == 0 then there is no | ||
158 | + * active floating point context so we must NOP (without doing | ||
159 | + * any lazy state preservation or the NOCP check). | ||
160 | + */ | ||
161 | + aspen = load_cpu_field(v7m.fpccr[M_REG_S]); | ||
162 | + sfpa = load_cpu_field(v7m.control[M_REG_S]); | ||
163 | + tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); | ||
164 | + tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); | ||
165 | + tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK); | ||
166 | + tcg_gen_or_i32(sfpa, sfpa, aspen); | ||
167 | + arm_gen_condlabel(s); | ||
168 | + tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel); | ||
169 | + | ||
170 | + if (s->fp_excp_el != 0) { | ||
171 | + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
172 | + syn_uncategorized(), s->fp_excp_el); | ||
173 | + return true; | ||
174 | + } | ||
175 | + | ||
176 | + topreg = a->vd + a->imm - 1; | ||
177 | + btmreg = a->vd; | ||
178 | + | ||
179 | + /* Convert to Sreg numbers if the insn specified in Dregs */ | ||
180 | + if (a->size == 3) { | ||
181 | + topreg = topreg * 2 + 1; | ||
182 | + btmreg *= 2; | ||
183 | + } | ||
184 | + | ||
185 | + if (topreg > 63 || (topreg > 31 && !(topreg & 1))) { | ||
186 | + /* UNPREDICTABLE: we choose to undef */ | ||
187 | + unallocated_encoding(s); | ||
188 | + return true; | ||
189 | + } | ||
190 | + | ||
191 | + /* Silently ignore requests to clear D16-D31 if they don't exist */ | ||
192 | + if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) { | ||
193 | + topreg = 31; | ||
194 | + } | ||
195 | + | ||
196 | + if (!vfp_access_check(s)) { | ||
197 | + return true; | ||
198 | + } | ||
199 | + | ||
200 | + /* Zero the Sregs from btmreg to topreg inclusive. */ | ||
201 | + zero = tcg_const_i64(0); | ||
202 | + if (btmreg & 1) { | ||
203 | + write_neon_element64(zero, btmreg >> 1, 1, MO_32); | ||
204 | + btmreg++; | ||
205 | + } | ||
206 | + for (; btmreg + 1 <= topreg; btmreg += 2) { | ||
207 | + write_neon_element64(zero, btmreg >> 1, 0, MO_64); | ||
208 | + } | ||
209 | + if (btmreg == topreg) { | ||
210 | + write_neon_element64(zero, btmreg >> 1, 0, MO_32); | ||
211 | + btmreg++; | ||
212 | + } | ||
213 | + assert(btmreg == topreg + 1); | ||
214 | + /* TODO: when MVE is implemented, zero VPR here */ | ||
215 | + return true; | ||
216 | +} | 241 | +} |
217 | + | 242 | + |
218 | +static bool trans_NOCP(DisasContext *s, arg_nocp *a) | 243 | static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, |
219 | +{ | 244 | 0x09, 0x00, 0x00, 0x00 }; |
220 | + /* | 245 | |
221 | + * Handle M-profile early check for disabled coprocessor: | 246 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c |
222 | + * all we need to do here is emit the NOCP exception if | ||
223 | + * the coprocessor is disabled. Otherwise we return false | ||
224 | + * and the real VFP/etc decode will handle the insn. | ||
225 | + */ | ||
226 | + assert(arm_dc_feature(s, ARM_FEATURE_M)); | ||
227 | + | ||
228 | + if (a->cp == 11) { | ||
229 | + a->cp = 10; | ||
230 | + } | ||
231 | + if (arm_dc_feature(s, ARM_FEATURE_V8_1M) && | ||
232 | + (a->cp == 8 || a->cp == 9 || a->cp == 14 || a->cp == 15)) { | ||
233 | + /* in v8.1M cp 8, 9, 14, 15 also are governed by the cp10 enable */ | ||
234 | + a->cp = 10; | ||
235 | + } | ||
236 | + | ||
237 | + if (a->cp != 10) { | ||
238 | + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
239 | + syn_uncategorized(), default_exception_el(s)); | ||
240 | + return true; | ||
241 | + } | ||
242 | + | ||
243 | + if (s->fp_excp_el != 0) { | ||
244 | + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
245 | + syn_uncategorized(), s->fp_excp_el); | ||
246 | + return true; | ||
247 | + } | ||
248 | + | ||
249 | + return false; | ||
250 | +} | ||
251 | + | ||
252 | +static bool trans_NOCP_8_1(DisasContext *s, arg_nocp *a) | ||
253 | +{ | ||
254 | + /* This range needs a coprocessor check for v8.1M and later only */ | ||
255 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
256 | + return false; | ||
257 | + } | ||
258 | + return trans_NOCP(s, a); | ||
259 | +} | ||
260 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
261 | index XXXXXXX..XXXXXXX 100644 | 247 | index XXXXXXX..XXXXXXX 100644 |
262 | --- a/target/arm/translate.c | 248 | --- a/hw/intc/exynos4210_gic.c |
263 | +++ b/target/arm/translate.c | 249 | +++ b/hw/intc/exynos4210_gic.c |
264 | @@ -XXX,XX +XXX,XX @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg) | 250 | @@ -XXX,XX +XXX,XX @@ |
265 | #define ARM_CP_RW_BIT (1 << 20) | 251 | #include "hw/arm/exynos4210.h" |
266 | 252 | #include "qom/object.h" | |
267 | /* Include the VFP and Neon decoders */ | 253 | |
268 | -#include "decode-m-nocp.c.inc" | 254 | -enum ExtGicId { |
269 | #include "translate-vfp.c.inc" | 255 | - EXT_GIC_ID_MDMA_LCD0 = 66, |
270 | #include "translate-neon.c.inc" | 256 | - EXT_GIC_ID_PDMA0, |
271 | 257 | - EXT_GIC_ID_PDMA1, | |
272 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | 258 | - EXT_GIC_ID_TIMER0, |
273 | index XXXXXXX..XXXXXXX 100644 | 259 | - EXT_GIC_ID_TIMER1, |
274 | --- a/target/arm/translate-vfp.c.inc | 260 | - EXT_GIC_ID_TIMER2, |
275 | +++ b/target/arm/translate-vfp.c.inc | 261 | - EXT_GIC_ID_TIMER3, |
276 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a) | 262 | - EXT_GIC_ID_TIMER4, |
277 | return true; | 263 | - EXT_GIC_ID_MCT_L0, |
278 | } | 264 | - EXT_GIC_ID_WDT, |
279 | 265 | - EXT_GIC_ID_RTC_ALARM, | |
266 | - EXT_GIC_ID_RTC_TIC, | ||
267 | - EXT_GIC_ID_GPIO_XB, | ||
268 | - EXT_GIC_ID_GPIO_XA, | ||
269 | - EXT_GIC_ID_MCT_L1, | ||
270 | - EXT_GIC_ID_IEM_APC, | ||
271 | - EXT_GIC_ID_IEM_IEC, | ||
272 | - EXT_GIC_ID_NFC, | ||
273 | - EXT_GIC_ID_UART0, | ||
274 | - EXT_GIC_ID_UART1, | ||
275 | - EXT_GIC_ID_UART2, | ||
276 | - EXT_GIC_ID_UART3, | ||
277 | - EXT_GIC_ID_UART4, | ||
278 | - EXT_GIC_ID_MCT_G0, | ||
279 | - EXT_GIC_ID_I2C0, | ||
280 | - EXT_GIC_ID_I2C1, | ||
281 | - EXT_GIC_ID_I2C2, | ||
282 | - EXT_GIC_ID_I2C3, | ||
283 | - EXT_GIC_ID_I2C4, | ||
284 | - EXT_GIC_ID_I2C5, | ||
285 | - EXT_GIC_ID_I2C6, | ||
286 | - EXT_GIC_ID_I2C7, | ||
287 | - EXT_GIC_ID_SPI0, | ||
288 | - EXT_GIC_ID_SPI1, | ||
289 | - EXT_GIC_ID_SPI2, | ||
290 | - EXT_GIC_ID_MCT_G1, | ||
291 | - EXT_GIC_ID_USB_HOST, | ||
292 | - EXT_GIC_ID_USB_DEVICE, | ||
293 | - EXT_GIC_ID_MODEMIF, | ||
294 | - EXT_GIC_ID_HSMMC0, | ||
295 | - EXT_GIC_ID_HSMMC1, | ||
296 | - EXT_GIC_ID_HSMMC2, | ||
297 | - EXT_GIC_ID_HSMMC3, | ||
298 | - EXT_GIC_ID_SDMMC, | ||
299 | - EXT_GIC_ID_MIPI_CSI_4LANE, | ||
300 | - EXT_GIC_ID_MIPI_DSI_4LANE, | ||
301 | - EXT_GIC_ID_MIPI_CSI_2LANE, | ||
302 | - EXT_GIC_ID_MIPI_DSI_2LANE, | ||
303 | - EXT_GIC_ID_ONENAND_AUDI, | ||
304 | - EXT_GIC_ID_ROTATOR, | ||
305 | - EXT_GIC_ID_FIMC0, | ||
306 | - EXT_GIC_ID_FIMC1, | ||
307 | - EXT_GIC_ID_FIMC2, | ||
308 | - EXT_GIC_ID_FIMC3, | ||
309 | - EXT_GIC_ID_JPEG, | ||
310 | - EXT_GIC_ID_2D, | ||
311 | - EXT_GIC_ID_PCIe, | ||
312 | - EXT_GIC_ID_MIXER, | ||
313 | - EXT_GIC_ID_HDMI, | ||
314 | - EXT_GIC_ID_HDMI_I2C, | ||
315 | - EXT_GIC_ID_MFC, | ||
316 | - EXT_GIC_ID_TVENC, | ||
317 | -}; | ||
318 | - | ||
319 | -enum ExtInt { | ||
320 | - EXT_GIC_ID_EXTINT0 = 48, | ||
321 | - EXT_GIC_ID_EXTINT1, | ||
322 | - EXT_GIC_ID_EXTINT2, | ||
323 | - EXT_GIC_ID_EXTINT3, | ||
324 | - EXT_GIC_ID_EXTINT4, | ||
325 | - EXT_GIC_ID_EXTINT5, | ||
326 | - EXT_GIC_ID_EXTINT6, | ||
327 | - EXT_GIC_ID_EXTINT7, | ||
328 | - EXT_GIC_ID_EXTINT8, | ||
329 | - EXT_GIC_ID_EXTINT9, | ||
330 | - EXT_GIC_ID_EXTINT10, | ||
331 | - EXT_GIC_ID_EXTINT11, | ||
332 | - EXT_GIC_ID_EXTINT12, | ||
333 | - EXT_GIC_ID_EXTINT13, | ||
334 | - EXT_GIC_ID_EXTINT14, | ||
335 | - EXT_GIC_ID_EXTINT15 | ||
336 | -}; | ||
337 | - | ||
280 | -/* | 338 | -/* |
281 | - * Decode VLLDM and VLSTM are nonstandard because: | 339 | - * External GIC sources which are not from External Interrupt Combiner or |
282 | - * * if there is no FPU then these insns must NOP in | 340 | - * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ, |
283 | - * Secure state and UNDEF in Nonsecure state | 341 | - * which is INTG16 in Internal Interrupt Combiner. |
284 | - * * if there is an FPU then these insns do not have | ||
285 | - * the usual behaviour that vfp_access_check() provides of | ||
286 | - * being controlled by CPACR/NSACR enable bits or the | ||
287 | - * lazy-stacking logic. | ||
288 | - */ | 342 | - */ |
289 | -static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a) | 343 | - |
344 | -static const uint32_t | ||
345 | -combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
346 | - /* int combiner groups 16-19 */ | ||
347 | - { }, { }, { }, { }, | ||
348 | - /* int combiner group 20 */ | ||
349 | - { 0, EXT_GIC_ID_MDMA_LCD0 }, | ||
350 | - /* int combiner group 21 */ | ||
351 | - { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 }, | ||
352 | - /* int combiner group 22 */ | ||
353 | - { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2, | ||
354 | - EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 }, | ||
355 | - /* int combiner group 23 */ | ||
356 | - { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC }, | ||
357 | - /* int combiner group 24 */ | ||
358 | - { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA }, | ||
359 | - /* int combiner group 25 */ | ||
360 | - { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC }, | ||
361 | - /* int combiner group 26 */ | ||
362 | - { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3, | ||
363 | - EXT_GIC_ID_UART4 }, | ||
364 | - /* int combiner group 27 */ | ||
365 | - { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3, | ||
366 | - EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6, | ||
367 | - EXT_GIC_ID_I2C7 }, | ||
368 | - /* int combiner group 28 */ | ||
369 | - { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST}, | ||
370 | - /* int combiner group 29 */ | ||
371 | - { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2, | ||
372 | - EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC }, | ||
373 | - /* int combiner group 30 */ | ||
374 | - { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE }, | ||
375 | - /* int combiner group 31 */ | ||
376 | - { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE }, | ||
377 | - /* int combiner group 32 */ | ||
378 | - { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 }, | ||
379 | - /* int combiner group 33 */ | ||
380 | - { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 }, | ||
381 | - /* int combiner group 34 */ | ||
382 | - { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, | ||
383 | - /* int combiner group 35 */ | ||
384 | - { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
385 | - /* int combiner group 36 */ | ||
386 | - { EXT_GIC_ID_MIXER }, | ||
387 | - /* int combiner group 37 */ | ||
388 | - { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6, | ||
389 | - EXT_GIC_ID_EXTINT7 }, | ||
390 | - /* groups 38-50 */ | ||
391 | - { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, | ||
392 | - /* int combiner group 51 */ | ||
393 | - { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
394 | - /* group 52 */ | ||
395 | - { }, | ||
396 | - /* int combiner group 53 */ | ||
397 | - { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
398 | - /* groups 54-63 */ | ||
399 | - { }, { }, { }, { }, { }, { }, { }, { }, { }, { } | ||
400 | -}; | ||
401 | - | ||
402 | #define EXYNOS4210_GIC_NIRQ 160 | ||
403 | |||
404 | #define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE 0x10000 | ||
405 | @@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
406 | #define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100 | ||
407 | #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000 | ||
408 | |||
409 | -/* | ||
410 | - * Initialize board IRQs. | ||
411 | - * These IRQs contain splitted Int/External Combiner and External Gic IRQs. | ||
412 | - */ | ||
413 | -void exynos4210_init_board_irqs(Exynos4210State *s) | ||
290 | -{ | 414 | -{ |
291 | - TCGv_i32 fptr; | 415 | - uint32_t grp, bit, irq_id, n; |
292 | - | 416 | - Exynos4210Irq *is = &s->irqs; |
293 | - if (!arm_dc_feature(s, ARM_FEATURE_M) || | 417 | - |
294 | - !arm_dc_feature(s, ARM_FEATURE_V8)) { | 418 | - for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { |
295 | - return false; | 419 | - irq_id = 0; |
296 | - } | 420 | - if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) || |
297 | - | 421 | - n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) { |
298 | - if (a->op) { | 422 | - /* MCT_G0 is passed to External GIC */ |
299 | - /* | 423 | - irq_id = EXT_GIC_ID_MCT_G0; |
300 | - * T2 encoding ({D0-D31} reglist): v8.1M and up. We choose not | ||
301 | - * to take the IMPDEF option to make memory accesses to the stack | ||
302 | - * slots that correspond to the D16-D31 registers (discarding | ||
303 | - * read data and writing UNKNOWN values), so for us the T2 | ||
304 | - * encoding behaves identically to the T1 encoding. | ||
305 | - */ | ||
306 | - if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
307 | - return false; | ||
308 | - } | 424 | - } |
309 | - } else { | 425 | - if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) || |
310 | - /* | 426 | - n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) { |
311 | - * T1 encoding ({D0-D15} reglist); undef if we have 32 Dregs. | 427 | - /* MCT_G1 is passed to External and GIC */ |
312 | - * This is currently architecturally impossible, but we add the | 428 | - irq_id = EXT_GIC_ID_MCT_G1; |
313 | - * check to stay in line with the pseudocode. Note that we must | 429 | - } |
314 | - * emit code for the UNDEF so it takes precedence over the NOCP. | 430 | - if (irq_id) { |
315 | - */ | 431 | - s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], |
316 | - if (dc_isar_feature(aa32_simd_r32, s)) { | 432 | - is->ext_gic_irq[irq_id - 32]); |
317 | - unallocated_encoding(s); | 433 | - } else { |
318 | - return true; | 434 | - s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], |
435 | - is->ext_combiner_irq[n]); | ||
319 | - } | 436 | - } |
320 | - } | 437 | - } |
321 | - | 438 | - for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { |
322 | - /* | 439 | - /* these IDs are passed to Internal Combiner and External GIC */ |
323 | - * If not secure, UNDEF. We must emit code for this | 440 | - grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n); |
324 | - * rather than returning false so that this takes | 441 | - bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); |
325 | - * precedence over the m-nocp.decode NOCP fallback. | 442 | - irq_id = combiner_grp_to_gic_id[grp - |
326 | - */ | 443 | - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; |
327 | - if (!s->v8m_secure) { | 444 | - |
328 | - unallocated_encoding(s); | 445 | - if (irq_id) { |
329 | - return true; | 446 | - s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], |
447 | - is->ext_gic_irq[irq_id - 32]); | ||
448 | - } | ||
330 | - } | 449 | - } |
331 | - /* If no fpu, NOP. */ | ||
332 | - if (!dc_isar_feature(aa32_vfp, s)) { | ||
333 | - return true; | ||
334 | - } | ||
335 | - | ||
336 | - fptr = load_reg(s, a->rn); | ||
337 | - if (a->l) { | ||
338 | - gen_helper_v7m_vlldm(cpu_env, fptr); | ||
339 | - } else { | ||
340 | - gen_helper_v7m_vlstm(cpu_env, fptr); | ||
341 | - } | ||
342 | - tcg_temp_free_i32(fptr); | ||
343 | - | ||
344 | - /* End the TB, because we have updated FP control bits */ | ||
345 | - s->base.is_jmp = DISAS_UPDATE_EXIT; | ||
346 | - return true; | ||
347 | -} | 450 | -} |
348 | - | 451 | - |
349 | -static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) | 452 | -/* |
453 | - * Get IRQ number from exynos4210 IRQ subsystem stub. | ||
454 | - * To identify IRQ source use internal combiner group and bit number | ||
455 | - * grp - group number | ||
456 | - * bit - bit number inside group | ||
457 | - */ | ||
458 | -uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) | ||
350 | -{ | 459 | -{ |
351 | - int btmreg, topreg; | 460 | - return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); |
352 | - TCGv_i64 zero; | ||
353 | - TCGv_i32 aspen, sfpa; | ||
354 | - | ||
355 | - if (!dc_isar_feature(aa32_m_sec_state, s)) { | ||
356 | - /* Before v8.1M, fall through in decode to NOCP check */ | ||
357 | - return false; | ||
358 | - } | ||
359 | - | ||
360 | - /* Explicitly UNDEF because this takes precedence over NOCP */ | ||
361 | - if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) { | ||
362 | - unallocated_encoding(s); | ||
363 | - return true; | ||
364 | - } | ||
365 | - | ||
366 | - if (!dc_isar_feature(aa32_vfp_simd, s)) { | ||
367 | - /* NOP if we have neither FP nor MVE */ | ||
368 | - return true; | ||
369 | - } | ||
370 | - | ||
371 | - /* | ||
372 | - * If FPCCR.ASPEN != 0 && CONTROL_S.SFPA == 0 then there is no | ||
373 | - * active floating point context so we must NOP (without doing | ||
374 | - * any lazy state preservation or the NOCP check). | ||
375 | - */ | ||
376 | - aspen = load_cpu_field(v7m.fpccr[M_REG_S]); | ||
377 | - sfpa = load_cpu_field(v7m.control[M_REG_S]); | ||
378 | - tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); | ||
379 | - tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); | ||
380 | - tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK); | ||
381 | - tcg_gen_or_i32(sfpa, sfpa, aspen); | ||
382 | - arm_gen_condlabel(s); | ||
383 | - tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel); | ||
384 | - | ||
385 | - if (s->fp_excp_el != 0) { | ||
386 | - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
387 | - syn_uncategorized(), s->fp_excp_el); | ||
388 | - return true; | ||
389 | - } | ||
390 | - | ||
391 | - topreg = a->vd + a->imm - 1; | ||
392 | - btmreg = a->vd; | ||
393 | - | ||
394 | - /* Convert to Sreg numbers if the insn specified in Dregs */ | ||
395 | - if (a->size == 3) { | ||
396 | - topreg = topreg * 2 + 1; | ||
397 | - btmreg *= 2; | ||
398 | - } | ||
399 | - | ||
400 | - if (topreg > 63 || (topreg > 31 && !(topreg & 1))) { | ||
401 | - /* UNPREDICTABLE: we choose to undef */ | ||
402 | - unallocated_encoding(s); | ||
403 | - return true; | ||
404 | - } | ||
405 | - | ||
406 | - /* Silently ignore requests to clear D16-D31 if they don't exist */ | ||
407 | - if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) { | ||
408 | - topreg = 31; | ||
409 | - } | ||
410 | - | ||
411 | - if (!vfp_access_check(s)) { | ||
412 | - return true; | ||
413 | - } | ||
414 | - | ||
415 | - /* Zero the Sregs from btmreg to topreg inclusive. */ | ||
416 | - zero = tcg_const_i64(0); | ||
417 | - if (btmreg & 1) { | ||
418 | - write_neon_element64(zero, btmreg >> 1, 1, MO_32); | ||
419 | - btmreg++; | ||
420 | - } | ||
421 | - for (; btmreg + 1 <= topreg; btmreg += 2) { | ||
422 | - write_neon_element64(zero, btmreg >> 1, 0, MO_64); | ||
423 | - } | ||
424 | - if (btmreg == topreg) { | ||
425 | - write_neon_element64(zero, btmreg >> 1, 0, MO_32); | ||
426 | - btmreg++; | ||
427 | - } | ||
428 | - assert(btmreg == topreg + 1); | ||
429 | - /* TODO: when MVE is implemented, zero VPR here */ | ||
430 | - return true; | ||
431 | -} | 461 | -} |
432 | - | 462 | - |
433 | -static bool trans_NOCP(DisasContext *s, arg_nocp *a) | 463 | -/********* GIC part *********/ |
434 | -{ | 464 | - |
435 | - /* | 465 | #define TYPE_EXYNOS4210_GIC "exynos4210.gic" |
436 | - * Handle M-profile early check for disabled coprocessor: | 466 | OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC) |
437 | - * all we need to do here is emit the NOCP exception if | 467 | |
438 | - * the coprocessor is disabled. Otherwise we return false | ||
439 | - * and the real VFP/etc decode will handle the insn. | ||
440 | - */ | ||
441 | - assert(arm_dc_feature(s, ARM_FEATURE_M)); | ||
442 | - | ||
443 | - if (a->cp == 11) { | ||
444 | - a->cp = 10; | ||
445 | - } | ||
446 | - if (arm_dc_feature(s, ARM_FEATURE_V8_1M) && | ||
447 | - (a->cp == 8 || a->cp == 9 || a->cp == 14 || a->cp == 15)) { | ||
448 | - /* in v8.1M cp 8, 9, 14, 15 also are governed by the cp10 enable */ | ||
449 | - a->cp = 10; | ||
450 | - } | ||
451 | - | ||
452 | - if (a->cp != 10) { | ||
453 | - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
454 | - syn_uncategorized(), default_exception_el(s)); | ||
455 | - return true; | ||
456 | - } | ||
457 | - | ||
458 | - if (s->fp_excp_el != 0) { | ||
459 | - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
460 | - syn_uncategorized(), s->fp_excp_el); | ||
461 | - return true; | ||
462 | - } | ||
463 | - | ||
464 | - return false; | ||
465 | -} | ||
466 | - | ||
467 | -static bool trans_NOCP_8_1(DisasContext *s, arg_nocp *a) | ||
468 | -{ | ||
469 | - /* This range needs a coprocessor check for v8.1M and later only */ | ||
470 | - if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
471 | - return false; | ||
472 | - } | ||
473 | - return trans_NOCP(s, a); | ||
474 | -} | ||
475 | - | ||
476 | static bool trans_VINS(DisasContext *s, arg_VINS *a) | ||
477 | { | ||
478 | TCGv_i32 rd, rm; | ||
479 | diff --git a/target/arm/meson.build b/target/arm/meson.build | ||
480 | index XXXXXXX..XXXXXXX 100644 | ||
481 | --- a/target/arm/meson.build | ||
482 | +++ b/target/arm/meson.build | ||
483 | @@ -XXX,XX +XXX,XX @@ gen = [ | ||
484 | decodetree.process('neon-ls.decode', extra_args: '--static-decode=disas_neon_ls'), | ||
485 | decodetree.process('vfp.decode', extra_args: '--static-decode=disas_vfp'), | ||
486 | decodetree.process('vfp-uncond.decode', extra_args: '--static-decode=disas_vfp_uncond'), | ||
487 | - decodetree.process('m-nocp.decode', extra_args: '--static-decode=disas_m_nocp'), | ||
488 | + decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp'), | ||
489 | decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'), | ||
490 | decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'), | ||
491 | decodetree.process('t32.decode', extra_args: '--static-decode=disas_t32'), | ||
492 | @@ -XXX,XX +XXX,XX @@ arm_ss.add(files( | ||
493 | 'op_helper.c', | ||
494 | 'tlb_helper.c', | ||
495 | 'translate.c', | ||
496 | + 'translate-m-nocp.c', | ||
497 | 'vec_helper.c', | ||
498 | 'vfp_helper.c', | ||
499 | 'cpu_tcg.c', | ||
500 | -- | 468 | -- |
501 | 2.20.1 | 469 | 2.25.1 |
502 | |||
503 | diff view generated by jsdifflib |
1 | Make dis-asm.h handle being included outside an 'extern "C"' block; | 1 | Switch the creation of the external GIC to the new-style "embedded in |
---|---|---|---|
2 | this allows us to remove the 'extern "C"' blocks that our two C++ | 2 | state struct" approach, so we can easily refer to the object |
3 | files that include it are using. | 3 | elsewhere during realize. |
4 | 4 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20220404154658.565020-9-peter.maydell@linaro.org | ||
7 | --- | 8 | --- |
8 | include/disas/dis-asm.h | 12 ++++++++++-- | 9 | include/hw/arm/exynos4210.h | 2 ++ |
9 | disas/arm-a64.cc | 2 -- | 10 | include/hw/intc/exynos4210_gic.h | 43 ++++++++++++++++++++++++++++++++ |
10 | disas/nanomips.cpp | 2 -- | 11 | hw/arm/exynos4210.c | 10 ++++---- |
11 | 3 files changed, 10 insertions(+), 6 deletions(-) | 12 | hw/intc/exynos4210_gic.c | 17 ++----------- |
13 | MAINTAINERS | 2 +- | ||
14 | 5 files changed, 53 insertions(+), 21 deletions(-) | ||
15 | create mode 100644 include/hw/intc/exynos4210_gic.h | ||
12 | 16 | ||
13 | diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h | 17 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h |
14 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/include/disas/dis-asm.h | 19 | --- a/include/hw/arm/exynos4210.h |
16 | +++ b/include/disas/dis-asm.h | 20 | +++ b/include/hw/arm/exynos4210.h |
17 | @@ -XXX,XX +XXX,XX @@ | 21 | @@ -XXX,XX +XXX,XX @@ |
18 | #ifndef DISAS_DIS_ASM_H | 22 | #include "hw/or-irq.h" |
19 | #define DISAS_DIS_ASM_H | 23 | #include "hw/sysbus.h" |
20 | 24 | #include "hw/cpu/a9mpcore.h" | |
21 | +#include "qemu/bswap.h" | 25 | +#include "hw/intc/exynos4210_gic.h" |
26 | #include "target/arm/cpu-qom.h" | ||
27 | #include "qom/object.h" | ||
28 | |||
29 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { | ||
30 | qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; | ||
31 | qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; | ||
32 | A9MPPrivState a9mpcore; | ||
33 | + Exynos4210GicState ext_gic; | ||
34 | }; | ||
35 | |||
36 | #define TYPE_EXYNOS4210_SOC "exynos4210" | ||
37 | diff --git a/include/hw/intc/exynos4210_gic.h b/include/hw/intc/exynos4210_gic.h | ||
38 | new file mode 100644 | ||
39 | index XXXXXXX..XXXXXXX | ||
40 | --- /dev/null | ||
41 | +++ b/include/hw/intc/exynos4210_gic.h | ||
42 | @@ -XXX,XX +XXX,XX @@ | ||
43 | +/* | ||
44 | + * Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c | ||
45 | + * | ||
46 | + * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. | ||
47 | + * All rights reserved. | ||
48 | + * | ||
49 | + * Evgeny Voevodin <e.voevodin@samsung.com> | ||
50 | + * | ||
51 | + * This program is free software; you can redistribute it and/or modify it | ||
52 | + * under the terms of the GNU General Public License as published by the | ||
53 | + * Free Software Foundation; either version 2 of the License, or (at your | ||
54 | + * option) any later version. | ||
55 | + * | ||
56 | + * This program is distributed in the hope that it will be useful, | ||
57 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
58 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | ||
59 | + * See the GNU General Public License for more details. | ||
60 | + * | ||
61 | + * You should have received a copy of the GNU General Public License along | ||
62 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
63 | + */ | ||
64 | +#ifndef HW_INTC_EXYNOS4210_GIC_H | ||
65 | +#define HW_INTC_EXYNOS4210_GIC_H | ||
22 | + | 66 | + |
23 | +#ifdef __cplusplus | 67 | +#include "hw/sysbus.h" |
24 | +extern "C" { | 68 | + |
69 | +#define TYPE_EXYNOS4210_GIC "exynos4210.gic" | ||
70 | +OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC) | ||
71 | + | ||
72 | +#define EXYNOS4210_GIC_NCPUS 2 | ||
73 | + | ||
74 | +struct Exynos4210GicState { | ||
75 | + SysBusDevice parent_obj; | ||
76 | + | ||
77 | + MemoryRegion cpu_container; | ||
78 | + MemoryRegion dist_container; | ||
79 | + MemoryRegion cpu_alias[EXYNOS4210_GIC_NCPUS]; | ||
80 | + MemoryRegion dist_alias[EXYNOS4210_GIC_NCPUS]; | ||
81 | + uint32_t num_cpu; | ||
82 | + DeviceState *gic; | ||
83 | +}; | ||
84 | + | ||
25 | +#endif | 85 | +#endif |
26 | + | 86 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c |
27 | typedef void *PTR; | 87 | index XXXXXXX..XXXXXXX 100644 |
28 | typedef uint64_t bfd_vma; | 88 | --- a/hw/arm/exynos4210.c |
29 | typedef int64_t bfd_signed_vma; | 89 | +++ b/hw/arm/exynos4210.c |
30 | @@ -XXX,XX +XXX,XX @@ bool cap_disas_plugin(disassemble_info *info, uint64_t pc, size_t size); | 90 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) |
31 | 91 | sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); | |
32 | /* from libbfd */ | 92 | |
33 | 93 | /* External GIC */ | |
34 | -#include "qemu/bswap.h" | 94 | - dev = qdev_new("exynos4210.gic"); |
95 | - qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); | ||
96 | - busdev = SYS_BUS_DEVICE(dev); | ||
97 | - sysbus_realize_and_unref(busdev, &error_fatal); | ||
98 | + qdev_prop_set_uint32(DEVICE(&s->ext_gic), "num-cpu", EXYNOS4210_NCPUS); | ||
99 | + busdev = SYS_BUS_DEVICE(&s->ext_gic); | ||
100 | + sysbus_realize(busdev, &error_fatal); | ||
101 | /* Map CPU interface */ | ||
102 | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); | ||
103 | /* Map Distributer interface */ | ||
104 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
105 | qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1)); | ||
106 | } | ||
107 | for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { | ||
108 | - s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n); | ||
109 | + s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->ext_gic), n); | ||
110 | } | ||
111 | |||
112 | /* Internal Interrupt Combiner */ | ||
113 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj) | ||
114 | } | ||
115 | |||
116 | object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); | ||
117 | + object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC); | ||
118 | } | ||
119 | |||
120 | static void exynos4210_class_init(ObjectClass *klass, void *data) | ||
121 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | ||
122 | index XXXXXXX..XXXXXXX 100644 | ||
123 | --- a/hw/intc/exynos4210_gic.c | ||
124 | +++ b/hw/intc/exynos4210_gic.c | ||
125 | @@ -XXX,XX +XXX,XX @@ | ||
126 | #include "qemu/module.h" | ||
127 | #include "hw/irq.h" | ||
128 | #include "hw/qdev-properties.h" | ||
129 | +#include "hw/intc/exynos4210_gic.h" | ||
130 | #include "hw/arm/exynos4210.h" | ||
131 | #include "qom/object.h" | ||
132 | |||
133 | @@ -XXX,XX +XXX,XX @@ | ||
134 | #define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100 | ||
135 | #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000 | ||
136 | |||
137 | -#define TYPE_EXYNOS4210_GIC "exynos4210.gic" | ||
138 | -OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC) | ||
35 | - | 139 | - |
36 | static inline bfd_vma bfd_getl64(const bfd_byte *addr) | 140 | -struct Exynos4210GicState { |
141 | - SysBusDevice parent_obj; | ||
142 | - | ||
143 | - MemoryRegion cpu_container; | ||
144 | - MemoryRegion dist_container; | ||
145 | - MemoryRegion cpu_alias[EXYNOS4210_NCPUS]; | ||
146 | - MemoryRegion dist_alias[EXYNOS4210_NCPUS]; | ||
147 | - uint32_t num_cpu; | ||
148 | - DeviceState *gic; | ||
149 | -}; | ||
150 | - | ||
151 | static void exynos4210_gic_set_irq(void *opaque, int irq, int level) | ||
37 | { | 152 | { |
38 | return ldq_le_p(addr); | 153 | Exynos4210GicState *s = (Exynos4210GicState *)opaque; |
39 | @@ -XXX,XX +XXX,XX @@ static inline bfd_vma bfd_getb16(const bfd_byte *addr) | 154 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_realize(DeviceState *dev, Error **errp) |
40 | 155 | * enough room for the cpu numbers. gcc 9.2.1 on 32-bit x86 | |
41 | typedef bool bfd_boolean; | 156 | * doesn't figure this out, otherwise and gives spurious warnings. |
42 | 157 | */ | |
43 | +#ifdef __cplusplus | 158 | - assert(n <= EXYNOS4210_NCPUS); |
44 | +} | 159 | + assert(n <= EXYNOS4210_GIC_NCPUS); |
45 | +#endif | 160 | for (i = 0; i < n; i++) { |
46 | + | 161 | /* Map CPU interface per SMP Core */ |
47 | #endif /* DISAS_DIS_ASM_H */ | 162 | sprintf(cpu_alias_name, "%s%x", cpu_prefix, i); |
48 | diff --git a/disas/arm-a64.cc b/disas/arm-a64.cc | 163 | diff --git a/MAINTAINERS b/MAINTAINERS |
49 | index XXXXXXX..XXXXXXX 100644 | 164 | index XXXXXXX..XXXXXXX 100644 |
50 | --- a/disas/arm-a64.cc | 165 | --- a/MAINTAINERS |
51 | +++ b/disas/arm-a64.cc | 166 | +++ b/MAINTAINERS |
52 | @@ -XXX,XX +XXX,XX @@ | 167 | @@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org> |
53 | */ | 168 | L: qemu-arm@nongnu.org |
54 | 169 | S: Odd Fixes | |
55 | #include "qemu/osdep.h" | 170 | F: hw/*/exynos* |
56 | -extern "C" { | 171 | -F: include/hw/arm/exynos4210.h |
57 | #include "disas/dis-asm.h" | 172 | +F: include/hw/*/exynos* |
58 | -} | 173 | |
59 | 174 | Calxeda Highbank | |
60 | #include "vixl/a64/disasm-a64.h" | 175 | M: Rob Herring <robh@kernel.org> |
61 | |||
62 | diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp | ||
63 | index XXXXXXX..XXXXXXX 100644 | ||
64 | --- a/disas/nanomips.cpp | ||
65 | +++ b/disas/nanomips.cpp | ||
66 | @@ -XXX,XX +XXX,XX @@ | ||
67 | */ | ||
68 | |||
69 | #include "qemu/osdep.h" | ||
70 | -extern "C" { | ||
71 | #include "disas/dis-asm.h" | ||
72 | -} | ||
73 | |||
74 | #include <cstring> | ||
75 | #include <stdexcept> | ||
76 | -- | 176 | -- |
77 | 2.20.1 | 177 | 2.25.1 |
78 | |||
79 | diff view generated by jsdifflib |
1 | Make the remaining functions which are needed by translate-vfp.c.inc | 1 | The only time we use the ext_gic_irq[] array in the Exynos4210Irq |
---|---|---|---|
2 | global. | 2 | struct is during realize of the SoC -- we initialize it with the |
3 | input IRQs of the external GIC device, and then connect those to | ||
4 | outputs of other devices further on in realize (including in the | ||
5 | exynos4210_init_board_irqs() function). Now that the ext_gic object | ||
6 | is easily accessible as s->ext_gic we can make the connections | ||
7 | directly from one device to the other without going via this array. | ||
3 | 8 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20210430132740.10391-8-peter.maydell@linaro.org | 11 | Message-id: 20220404154658.565020-10-peter.maydell@linaro.org |
8 | --- | 12 | --- |
9 | target/arm/translate-a32.h | 18 ++++++++++++++++++ | 13 | include/hw/arm/exynos4210.h | 1 - |
10 | target/arm/translate.c | 25 ++++++++----------------- | 14 | hw/arm/exynos4210.c | 12 ++++++------ |
11 | 2 files changed, 26 insertions(+), 17 deletions(-) | 15 | 2 files changed, 6 insertions(+), 7 deletions(-) |
12 | 16 | ||
13 | diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h | 17 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h |
14 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/translate-a32.h | 19 | --- a/include/hw/arm/exynos4210.h |
16 | +++ b/target/arm/translate-a32.h | 20 | +++ b/include/hw/arm/exynos4210.h |
17 | @@ -XXX,XX +XXX,XX @@ void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop); | 21 | @@ -XXX,XX +XXX,XX @@ |
18 | void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop); | 22 | typedef struct Exynos4210Irq { |
19 | void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop); | 23 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; |
20 | void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop); | 24 | qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; |
21 | +TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs); | 25 | - qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ]; |
22 | +void gen_set_cpsr(TCGv_i32 var, uint32_t mask); | 26 | } Exynos4210Irq; |
23 | +void gen_set_condexec(DisasContext *s); | 27 | |
24 | +void gen_set_pc_im(DisasContext *s, target_ulong val); | 28 | struct Exynos4210State { |
25 | +void gen_lookup_tb(DisasContext *s); | 29 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c |
26 | +long vfp_reg_offset(bool dp, unsigned reg); | 30 | index XXXXXXX..XXXXXXX 100644 |
27 | +long neon_full_reg_offset(unsigned reg); | 31 | --- a/hw/arm/exynos4210.c |
28 | 32 | +++ b/hw/arm/exynos4210.c | |
29 | static inline TCGv_i32 load_cpu_offset(int offset) | 33 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) |
30 | { | 34 | { |
31 | @@ -XXX,XX +XXX,XX @@ static inline TCGv_i32 load_reg(DisasContext *s, int reg) | 35 | uint32_t grp, bit, irq_id, n; |
32 | return tmp; | 36 | Exynos4210Irq *is = &s->irqs; |
33 | } | 37 | + DeviceState *extgicdev = DEVICE(&s->ext_gic); |
34 | 38 | ||
35 | +void store_reg(DisasContext *s, int reg, TCGv_i32 var); | 39 | for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { |
36 | + | 40 | irq_id = 0; |
37 | void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, | 41 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) |
38 | TCGv_i32 a32, int index, MemOp opc); | 42 | } |
39 | void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, | 43 | if (irq_id) { |
40 | @@ -XXX,XX +XXX,XX @@ DO_GEN_ST(32, MO_UL) | 44 | s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], |
41 | #undef DO_GEN_LD | 45 | - is->ext_gic_irq[irq_id - 32]); |
42 | #undef DO_GEN_ST | 46 | + qdev_get_gpio_in(extgicdev, |
43 | 47 | + irq_id - 32)); | |
44 | +#if defined(CONFIG_USER_ONLY) | 48 | } else { |
45 | +#define IS_USER(s) 1 | 49 | s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], |
46 | +#else | 50 | is->ext_combiner_irq[n]); |
47 | +#define IS_USER(s) (s->user) | 51 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) |
48 | +#endif | 52 | |
49 | + | 53 | if (irq_id) { |
50 | +/* Set NZCV flags from the high 4 bits of var. */ | 54 | s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], |
51 | +#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV) | 55 | - is->ext_gic_irq[irq_id - 32]); |
52 | + | 56 | + qdev_get_gpio_in(extgicdev, |
53 | #endif | 57 | + irq_id - 32)); |
54 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 58 | } |
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/target/arm/translate.c | ||
57 | +++ b/target/arm/translate.c | ||
58 | @@ -XXX,XX +XXX,XX @@ | ||
59 | #include "translate.h" | ||
60 | #include "translate-a32.h" | ||
61 | |||
62 | -#if defined(CONFIG_USER_ONLY) | ||
63 | -#define IS_USER(s) 1 | ||
64 | -#else | ||
65 | -#define IS_USER(s) (s->user) | ||
66 | -#endif | ||
67 | - | ||
68 | /* These are TCG temporaries used only by the legacy iwMMXt decoder */ | ||
69 | static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; | ||
70 | /* These are TCG globals which alias CPUARMState fields */ | ||
71 | @@ -XXX,XX +XXX,XX @@ void load_reg_var(DisasContext *s, TCGv_i32 var, int reg) | ||
72 | * This is used for load/store for which use of PC implies (literal), | ||
73 | * or ADD that implies ADR. | ||
74 | */ | ||
75 | -static TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs) | ||
76 | +TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs) | ||
77 | { | ||
78 | TCGv_i32 tmp = tcg_temp_new_i32(); | ||
79 | |||
80 | @@ -XXX,XX +XXX,XX @@ static TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs) | ||
81 | |||
82 | /* Set a CPU register. The source must be a temporary and will be | ||
83 | marked as dead. */ | ||
84 | -static void store_reg(DisasContext *s, int reg, TCGv_i32 var) | ||
85 | +void store_reg(DisasContext *s, int reg, TCGv_i32 var) | ||
86 | { | ||
87 | if (reg == 15) { | ||
88 | /* In Thumb mode, we must ignore bit 0. | ||
89 | @@ -XXX,XX +XXX,XX @@ static void store_sp_checked(DisasContext *s, TCGv_i32 var) | ||
90 | #define gen_sxtb16(var) gen_helper_sxtb16(var, var) | ||
91 | #define gen_uxtb16(var) gen_helper_uxtb16(var, var) | ||
92 | |||
93 | - | ||
94 | -static inline void gen_set_cpsr(TCGv_i32 var, uint32_t mask) | ||
95 | +void gen_set_cpsr(TCGv_i32 var, uint32_t mask) | ||
96 | { | ||
97 | TCGv_i32 tmp_mask = tcg_const_i32(mask); | ||
98 | gen_helper_cpsr_write(cpu_env, var, tmp_mask); | ||
99 | tcg_temp_free_i32(tmp_mask); | ||
100 | } | ||
101 | -/* Set NZCV flags from the high 4 bits of var. */ | ||
102 | -#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV) | ||
103 | |||
104 | static void gen_exception_internal(int excp) | ||
105 | { | ||
106 | @@ -XXX,XX +XXX,XX @@ void arm_gen_test_cc(int cc, TCGLabel *label) | ||
107 | arm_free_cc(&cmp); | ||
108 | } | ||
109 | |||
110 | -static inline void gen_set_condexec(DisasContext *s) | ||
111 | +void gen_set_condexec(DisasContext *s) | ||
112 | { | ||
113 | if (s->condexec_mask) { | ||
114 | uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1); | ||
115 | @@ -XXX,XX +XXX,XX @@ static inline void gen_set_condexec(DisasContext *s) | ||
116 | } | 59 | } |
117 | } | 60 | } |
118 | 61 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | |
119 | -static inline void gen_set_pc_im(DisasContext *s, target_ulong val) | 62 | sysbus_connect_irq(busdev, n, |
120 | +void gen_set_pc_im(DisasContext *s, target_ulong val) | 63 | qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1)); |
121 | { | 64 | } |
122 | tcg_gen_movi_i32(cpu_R[15], val); | 65 | - for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { |
123 | } | 66 | - s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->ext_gic), n); |
124 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_el(DisasContext *s, int excp, uint32_t syn, | 67 | - } |
125 | } | 68 | |
126 | 69 | /* Internal Interrupt Combiner */ | |
127 | /* Force a TB lookup after an instruction that changes the CPU state. */ | 70 | dev = qdev_new("exynos4210.combiner"); |
128 | -static inline void gen_lookup_tb(DisasContext *s) | 71 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) |
129 | +void gen_lookup_tb(DisasContext *s) | 72 | busdev = SYS_BUS_DEVICE(dev); |
130 | { | 73 | sysbus_realize_and_unref(busdev, &error_fatal); |
131 | tcg_gen_movi_i32(cpu_R[15], s->base.pc_next); | 74 | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { |
132 | s->base.is_jmp = DISAS_EXIT; | 75 | - sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]); |
133 | @@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm) | 76 | + sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n)); |
134 | /* | 77 | } |
135 | * Return the offset of a "full" NEON Dreg. | 78 | exynos4210_combiner_get_gpioin(&s->irqs, dev, 1); |
136 | */ | 79 | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); |
137 | -static long neon_full_reg_offset(unsigned reg) | ||
138 | +long neon_full_reg_offset(unsigned reg) | ||
139 | { | ||
140 | return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]); | ||
141 | } | ||
142 | @@ -XXX,XX +XXX,XX @@ static long neon_element_offset(int reg, int element, MemOp memop) | ||
143 | } | ||
144 | |||
145 | /* Return the offset of a VFP Dreg (dp = true) or VFP Sreg (dp = false). */ | ||
146 | -static long vfp_reg_offset(bool dp, unsigned reg) | ||
147 | +long vfp_reg_offset(bool dp, unsigned reg) | ||
148 | { | ||
149 | if (dp) { | ||
150 | return neon_element_offset(reg, 0, MO_64); | ||
151 | -- | 80 | -- |
152 | 2.20.1 | 81 | 2.25.1 |
153 | |||
154 | diff view generated by jsdifflib |
1 | Switch translate-neon.c.inc from being #included into translate.c | 1 | The function exynos4210_combiner_get_gpioin() currently lives in |
---|---|---|---|
2 | to being its own compilation unit. | 2 | exynos4210_combiner.c, but it isn't really part of the combiner |
3 | device itself -- it is a function that implements the wiring up of | ||
4 | some interrupt sources to multiple combiner inputs. Move it to live | ||
5 | with the other SoC-level code in exynos4210.c, along with a few | ||
6 | macros previously defined in exynos4210.h which are now used only | ||
7 | in exynos4210.c. | ||
3 | 8 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20210430132740.10391-14-peter.maydell@linaro.org | 11 | Message-id: 20220404154658.565020-11-peter.maydell@linaro.org |
8 | --- | 12 | --- |
9 | target/arm/translate-a32.h | 3 +++ | 13 | include/hw/arm/exynos4210.h | 11 ----- |
10 | .../arm/{translate-neon.c.inc => translate-neon.c} | 12 +++++++----- | 14 | hw/arm/exynos4210.c | 82 +++++++++++++++++++++++++++++++++++ |
11 | target/arm/translate.c | 3 --- | 15 | hw/intc/exynos4210_combiner.c | 77 -------------------------------- |
12 | target/arm/meson.build | 7 ++++--- | 16 | 3 files changed, 82 insertions(+), 88 deletions(-) |
13 | 4 files changed, 14 insertions(+), 11 deletions(-) | ||
14 | rename target/arm/{translate-neon.c.inc => translate-neon.c} (99%) | ||
15 | 17 | ||
16 | diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h | 18 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h |
17 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/translate-a32.h | 20 | --- a/include/hw/arm/exynos4210.h |
19 | +++ b/target/arm/translate-a32.h | 21 | +++ b/include/hw/arm/exynos4210.h |
20 | @@ -XXX,XX +XXX,XX @@ | 22 | @@ -XXX,XX +XXX,XX @@ |
21 | bool disas_m_nocp(DisasContext *dc, uint32_t insn); | 23 | #define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \ |
22 | bool disas_vfp(DisasContext *s, uint32_t insn); | 24 | (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8) |
23 | bool disas_vfp_uncond(DisasContext *s, uint32_t insn); | 25 | |
24 | +bool disas_neon_dp(DisasContext *s, uint32_t insn); | 26 | -#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp)*8 + (bit)) |
25 | +bool disas_neon_ls(DisasContext *s, uint32_t insn); | 27 | -#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8) |
26 | +bool disas_neon_shared(DisasContext *s, uint32_t insn); | 28 | -#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ |
27 | 29 | - ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) | |
28 | void load_reg_var(DisasContext *s, TCGv_i32 var, int reg); | 30 | - |
29 | void arm_gen_condlabel(DisasContext *s); | 31 | /* IRQs number for external and internal GIC */ |
30 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c | 32 | #define EXYNOS4210_EXT_GIC_NIRQ (160-32) |
31 | similarity index 99% | 33 | #define EXYNOS4210_INT_GIC_NIRQ 64 |
32 | rename from target/arm/translate-neon.c.inc | 34 | @@ -XXX,XX +XXX,XX @@ void exynos4210_write_secondary(ARMCPU *cpu, |
33 | rename to target/arm/translate-neon.c | 35 | * bit - bit number inside group */ |
36 | uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit); | ||
37 | |||
38 | -/* | ||
39 | - * Get Combiner input GPIO into irqs structure | ||
40 | - */ | ||
41 | -void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev, | ||
42 | - int ext); | ||
43 | - | ||
44 | /* | ||
45 | * exynos4210 UART | ||
46 | */ | ||
47 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | 48 | index XXXXXXX..XXXXXXX 100644 |
35 | --- a/target/arm/translate-neon.c.inc | 49 | --- a/hw/arm/exynos4210.c |
36 | +++ b/target/arm/translate-neon.c | 50 | +++ b/hw/arm/exynos4210.c |
37 | @@ -XXX,XX +XXX,XX @@ | 51 | @@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { |
38 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | 52 | { }, { }, { }, { }, { }, { }, { }, { }, { }, { } |
39 | */ | 53 | }; |
54 | |||
55 | +#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp) * 8 + (bit)) | ||
56 | +#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8) | ||
57 | +#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ | ||
58 | + ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) | ||
59 | + | ||
60 | /* | ||
61 | * Initialize board IRQs. | ||
62 | * These IRQs contain splitted Int/External Combiner and External Gic IRQs. | ||
63 | @@ -XXX,XX +XXX,XX @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) | ||
64 | return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); | ||
65 | } | ||
66 | |||
67 | +/* | ||
68 | + * Get Combiner input GPIO into irqs structure | ||
69 | + */ | ||
70 | +static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, | ||
71 | + DeviceState *dev, int ext) | ||
72 | +{ | ||
73 | + int n; | ||
74 | + int bit; | ||
75 | + int max; | ||
76 | + qemu_irq *irq; | ||
77 | + | ||
78 | + max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ : | ||
79 | + EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; | ||
80 | + irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq; | ||
81 | + | ||
82 | + /* | ||
83 | + * Some IRQs of Int/External Combiner are going to two Combiners groups, | ||
84 | + * so let split them. | ||
85 | + */ | ||
86 | + for (n = 0; n < max; n++) { | ||
87 | + | ||
88 | + bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); | ||
89 | + | ||
90 | + switch (n) { | ||
91 | + /* MDNIE_LCD1 INTG1 */ | ||
92 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ... | ||
93 | + EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3): | ||
94 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
95 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]); | ||
96 | + continue; | ||
97 | + | ||
98 | + /* TMU INTG3 */ | ||
99 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4): | ||
100 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
101 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]); | ||
102 | + continue; | ||
103 | + | ||
104 | + /* LCD1 INTG12 */ | ||
105 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ... | ||
106 | + EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3): | ||
107 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
108 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]); | ||
109 | + continue; | ||
110 | + | ||
111 | + /* Multi-Core Timer INTG12 */ | ||
112 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ... | ||
113 | + EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8): | ||
114 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
115 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
116 | + continue; | ||
117 | + | ||
118 | + /* Multi-Core Timer INTG35 */ | ||
119 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ... | ||
120 | + EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8): | ||
121 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
122 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
123 | + continue; | ||
124 | + | ||
125 | + /* Multi-Core Timer INTG51 */ | ||
126 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ... | ||
127 | + EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8): | ||
128 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
129 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
130 | + continue; | ||
131 | + | ||
132 | + /* Multi-Core Timer INTG53 */ | ||
133 | + case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ... | ||
134 | + EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8): | ||
135 | + irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
136 | + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
137 | + continue; | ||
138 | + } | ||
139 | + | ||
140 | + irq[n] = qdev_get_gpio_in(dev, n); | ||
141 | + } | ||
142 | +} | ||
143 | + | ||
144 | static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, | ||
145 | 0x09, 0x00, 0x00, 0x00 }; | ||
146 | |||
147 | diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c | ||
148 | index XXXXXXX..XXXXXXX 100644 | ||
149 | --- a/hw/intc/exynos4210_combiner.c | ||
150 | +++ b/hw/intc/exynos4210_combiner.c | ||
151 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_exynos4210_combiner = { | ||
152 | } | ||
153 | }; | ||
40 | 154 | ||
41 | -/* | 155 | -/* |
42 | - * This file is intended to be included from translate.c; it uses | 156 | - * Get Combiner input GPIO into irqs structure |
43 | - * some macros and definitions provided by that file. | ||
44 | - * It might be possible to convert it to a standalone .c file eventually. | ||
45 | - */ | 157 | - */ |
46 | +#include "qemu/osdep.h" | 158 | -void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev, |
47 | +#include "tcg/tcg-op.h" | 159 | - int ext) |
48 | +#include "tcg/tcg-op-gvec.h" | 160 | -{ |
49 | +#include "exec/exec-all.h" | 161 | - int n; |
50 | +#include "exec/gen-icount.h" | 162 | - int bit; |
51 | +#include "translate.h" | 163 | - int max; |
52 | +#include "translate-a32.h" | 164 | - qemu_irq *irq; |
53 | 165 | - | |
54 | static inline int plus1(DisasContext *s, int x) | 166 | - max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ : |
167 | - EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; | ||
168 | - irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq; | ||
169 | - | ||
170 | - /* | ||
171 | - * Some IRQs of Int/External Combiner are going to two Combiners groups, | ||
172 | - * so let split them. | ||
173 | - */ | ||
174 | - for (n = 0; n < max; n++) { | ||
175 | - | ||
176 | - bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); | ||
177 | - | ||
178 | - switch (n) { | ||
179 | - /* MDNIE_LCD1 INTG1 */ | ||
180 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ... | ||
181 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3): | ||
182 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
183 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]); | ||
184 | - continue; | ||
185 | - | ||
186 | - /* TMU INTG3 */ | ||
187 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4): | ||
188 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
189 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]); | ||
190 | - continue; | ||
191 | - | ||
192 | - /* LCD1 INTG12 */ | ||
193 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ... | ||
194 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3): | ||
195 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
196 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]); | ||
197 | - continue; | ||
198 | - | ||
199 | - /* Multi-Core Timer INTG12 */ | ||
200 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ... | ||
201 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8): | ||
202 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
203 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
204 | - continue; | ||
205 | - | ||
206 | - /* Multi-Core Timer INTG35 */ | ||
207 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ... | ||
208 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8): | ||
209 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
210 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
211 | - continue; | ||
212 | - | ||
213 | - /* Multi-Core Timer INTG51 */ | ||
214 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ... | ||
215 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8): | ||
216 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
217 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
218 | - continue; | ||
219 | - | ||
220 | - /* Multi-Core Timer INTG53 */ | ||
221 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ... | ||
222 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8): | ||
223 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
224 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
225 | - continue; | ||
226 | - } | ||
227 | - | ||
228 | - irq[n] = qdev_get_gpio_in(dev, n); | ||
229 | - } | ||
230 | -} | ||
231 | - | ||
232 | static uint64_t | ||
233 | exynos4210_combiner_read(void *opaque, hwaddr offset, unsigned size) | ||
55 | { | 234 | { |
56 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/target/arm/translate.c | ||
59 | +++ b/target/arm/translate.c | ||
60 | @@ -XXX,XX +XXX,XX @@ void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop) | ||
61 | |||
62 | #define ARM_CP_RW_BIT (1 << 20) | ||
63 | |||
64 | -/* Include the Neon decoder */ | ||
65 | -#include "translate-neon.c.inc" | ||
66 | - | ||
67 | static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) | ||
68 | { | ||
69 | tcg_gen_ld_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg])); | ||
70 | diff --git a/target/arm/meson.build b/target/arm/meson.build | ||
71 | index XXXXXXX..XXXXXXX 100644 | ||
72 | --- a/target/arm/meson.build | ||
73 | +++ b/target/arm/meson.build | ||
74 | @@ -XXX,XX +XXX,XX @@ | ||
75 | gen = [ | ||
76 | decodetree.process('sve.decode', extra_args: '--decode=disas_sve'), | ||
77 | - decodetree.process('neon-shared.decode', extra_args: '--static-decode=disas_neon_shared'), | ||
78 | - decodetree.process('neon-dp.decode', extra_args: '--static-decode=disas_neon_dp'), | ||
79 | - decodetree.process('neon-ls.decode', extra_args: '--static-decode=disas_neon_ls'), | ||
80 | + decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'), | ||
81 | + decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'), | ||
82 | + decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'), | ||
83 | decodetree.process('vfp.decode', extra_args: '--decode=disas_vfp'), | ||
84 | decodetree.process('vfp-uncond.decode', extra_args: '--decode=disas_vfp_uncond'), | ||
85 | decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp'), | ||
86 | @@ -XXX,XX +XXX,XX @@ arm_ss.add(files( | ||
87 | 'tlb_helper.c', | ||
88 | 'translate.c', | ||
89 | 'translate-m-nocp.c', | ||
90 | + 'translate-neon.c', | ||
91 | 'translate-vfp.c', | ||
92 | 'vec_helper.c', | ||
93 | 'vfp_helper.c', | ||
94 | -- | 235 | -- |
95 | 2.20.1 | 236 | 2.25.1 |
96 | |||
97 | diff view generated by jsdifflib |
1 | Make bswap.h handle being included outside an 'extern "C"' block: | 1 | Delete a couple of #defines which are never used. |
---|---|---|---|
2 | all system headers are included first, then all declarations are | ||
3 | put inside an 'extern "C"' block. | ||
4 | |||
5 | This requires a little rearrangement as currently we have an ifdef | ||
6 | ladder that has some system includes and some local declarations | ||
7 | or definitions, and we need to separate those out. | ||
8 | |||
9 | We want to do this because dis-asm.h includes bswap.h, dis-asm.h | ||
10 | may need to be included from C++ files, and system headers should | ||
11 | not be included within 'extern "C"' blocks. | ||
12 | 2 | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20220404154658.565020-12-peter.maydell@linaro.org | ||
15 | --- | 6 | --- |
16 | include/qemu/bswap.h | 26 ++++++++++++++++++++++---- | 7 | include/hw/arm/exynos4210.h | 4 ---- |
17 | 1 file changed, 22 insertions(+), 4 deletions(-) | 8 | 1 file changed, 4 deletions(-) |
18 | 9 | ||
19 | diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h | 10 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h |
20 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/include/qemu/bswap.h | 12 | --- a/include/hw/arm/exynos4210.h |
22 | +++ b/include/qemu/bswap.h | 13 | +++ b/include/hw/arm/exynos4210.h |
23 | @@ -XXX,XX +XXX,XX @@ | 14 | @@ -XXX,XX +XXX,XX @@ |
24 | #ifndef BSWAP_H | 15 | #define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \ |
25 | #define BSWAP_H | 16 | (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8) |
26 | 17 | ||
27 | -#include "fpu/softfloat-types.h" | 18 | -/* IRQs number for external and internal GIC */ |
19 | -#define EXYNOS4210_EXT_GIC_NIRQ (160-32) | ||
20 | -#define EXYNOS4210_INT_GIC_NIRQ 64 | ||
28 | - | 21 | - |
29 | #ifdef CONFIG_MACHINE_BSWAP_H | 22 | #define EXYNOS4210_I2C_NUMBER 9 |
30 | # include <sys/endian.h> | 23 | |
31 | # include <machine/bswap.h> | 24 | #define EXYNOS4210_NUM_DMA 3 |
32 | @@ -XXX,XX +XXX,XX @@ | ||
33 | # include <endian.h> | ||
34 | #elif defined(CONFIG_BYTESWAP_H) | ||
35 | # include <byteswap.h> | ||
36 | +#define BSWAP_FROM_BYTESWAP | ||
37 | +# else | ||
38 | +#define BSWAP_FROM_FALLBACKS | ||
39 | +#endif /* ! CONFIG_MACHINE_BSWAP_H */ | ||
40 | |||
41 | +#ifdef __cplusplus | ||
42 | +extern "C" { | ||
43 | +#endif | ||
44 | + | ||
45 | +#include "fpu/softfloat-types.h" | ||
46 | + | ||
47 | +#ifdef BSWAP_FROM_BYTESWAP | ||
48 | static inline uint16_t bswap16(uint16_t x) | ||
49 | { | ||
50 | return bswap_16(x); | ||
51 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t bswap64(uint64_t x) | ||
52 | { | ||
53 | return bswap_64(x); | ||
54 | } | ||
55 | -# else | ||
56 | +#endif | ||
57 | + | ||
58 | +#ifdef BSWAP_FROM_FALLBACKS | ||
59 | static inline uint16_t bswap16(uint16_t x) | ||
60 | { | ||
61 | return (((x & 0x00ff) << 8) | | ||
62 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t bswap64(uint64_t x) | ||
63 | ((x & 0x00ff000000000000ULL) >> 40) | | ||
64 | ((x & 0xff00000000000000ULL) >> 56)); | ||
65 | } | ||
66 | -#endif /* ! CONFIG_MACHINE_BSWAP_H */ | ||
67 | +#endif | ||
68 | + | ||
69 | +#undef BSWAP_FROM_BYTESWAP | ||
70 | +#undef BSWAP_FROM_FALLBACKS | ||
71 | |||
72 | static inline void bswap16s(uint16_t *s) | ||
73 | { | ||
74 | @@ -XXX,XX +XXX,XX @@ DO_STN_LDN_P(be) | ||
75 | #undef le_bswaps | ||
76 | #undef be_bswaps | ||
77 | |||
78 | +#ifdef __cplusplus | ||
79 | +} | ||
80 | +#endif | ||
81 | + | ||
82 | #endif /* BSWAP_H */ | ||
83 | -- | 25 | -- |
84 | 2.20.1 | 26 | 2.25.1 |
85 | |||
86 | diff view generated by jsdifflib |
1 | On some boards, SCC config register CFG0 bit 0 controls whether | 1 | In exynos4210_init_board_irqs(), use the TYPE_SPLIT_IRQ device |
---|---|---|---|
2 | parts of the board memory map are remapped. Support this with: | 2 | instead of qemu_irq_split(). |
3 | * a device property scc-cfg0 so the board can specify the | ||
4 | initial value of the CFG0 register | ||
5 | * an outbound GPIO line which tracks bit 0 and which the board | ||
6 | can wire up to provide the remapping | ||
7 | 3 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 6 | Message-id: 20220404154658.565020-13-peter.maydell@linaro.org |
11 | Message-id: 20210504120912.23094-3-peter.maydell@linaro.org | ||
12 | --- | 7 | --- |
13 | include/hw/misc/mps2-scc.h | 9 +++++++++ | 8 | include/hw/arm/exynos4210.h | 9 ++++++++ |
14 | hw/misc/mps2-scc.c | 13 ++++++++++--- | 9 | hw/arm/exynos4210.c | 41 +++++++++++++++++++++++++++++-------- |
15 | 2 files changed, 19 insertions(+), 3 deletions(-) | 10 | 2 files changed, 42 insertions(+), 8 deletions(-) |
16 | 11 | ||
17 | diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h | 12 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h |
18 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/include/hw/misc/mps2-scc.h | 14 | --- a/include/hw/arm/exynos4210.h |
20 | +++ b/include/hw/misc/mps2-scc.h | 15 | +++ b/include/hw/arm/exynos4210.h |
21 | @@ -XXX,XX +XXX,XX @@ | 16 | @@ -XXX,XX +XXX,XX @@ |
22 | * + QOM property "scc-cfg4": value of the read-only CFG4 register | 17 | #include "hw/sysbus.h" |
23 | * + QOM property "scc-aid": value of the read-only SCC_AID register | 18 | #include "hw/cpu/a9mpcore.h" |
24 | * + QOM property "scc-id": value of the read-only SCC_ID register | 19 | #include "hw/intc/exynos4210_gic.h" |
25 | + * + QOM property "scc-cfg0": reset value of the CFG0 register | 20 | +#include "hw/core/split-irq.h" |
26 | * + QOM property array "oscclk": reset values of the OSCCLK registers | 21 | #include "target/arm/cpu-qom.h" |
27 | * (which are accessed via the SYS_CFG channel provided by this device) | 22 | #include "qom/object.h" |
28 | + * + named GPIO output "remap": this tracks the value of CFG0 register | 23 | |
29 | + * bit 0. Boards where this bit controls memory remapping should | 24 | @@ -XXX,XX +XXX,XX @@ |
30 | + * connect this GPIO line to a function performing that mapping. | 25 | |
31 | + * Boards where bit 0 has no special function should leave the GPIO | 26 | #define EXYNOS4210_NUM_DMA 3 |
32 | + * output disconnected. | 27 | |
33 | */ | 28 | +/* |
34 | #ifndef MPS2_SCC_H | 29 | + * We need one splitter for every external combiner input, plus |
35 | #define MPS2_SCC_H | 30 | + * one for every non-zero entry in combiner_grp_to_gic_id[]. |
36 | @@ -XXX,XX +XXX,XX @@ struct MPS2SCC { | 31 | + * We'll assert in exynos4210_init_board_irqs() if this is wrong. |
37 | uint32_t num_oscclk; | 32 | + */ |
38 | uint32_t *oscclk; | 33 | +#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 60) |
39 | uint32_t *oscclk_reset; | ||
40 | + uint32_t cfg0_reset; | ||
41 | + | 34 | + |
42 | + qemu_irq remap; | 35 | typedef struct Exynos4210Irq { |
36 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
37 | qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; | ||
38 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { | ||
39 | qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; | ||
40 | A9MPPrivState a9mpcore; | ||
41 | Exynos4210GicState ext_gic; | ||
42 | + SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS]; | ||
43 | }; | 43 | }; |
44 | 44 | ||
45 | #endif | 45 | #define TYPE_EXYNOS4210_SOC "exynos4210" |
46 | diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c | 46 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c |
47 | index XXXXXXX..XXXXXXX 100644 | 47 | index XXXXXXX..XXXXXXX 100644 |
48 | --- a/hw/misc/mps2-scc.c | 48 | --- a/hw/arm/exynos4210.c |
49 | +++ b/hw/misc/mps2-scc.c | 49 | +++ b/hw/arm/exynos4210.c |
50 | @@ -XXX,XX +XXX,XX @@ | 50 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) |
51 | #include "qemu/bitops.h" | 51 | uint32_t grp, bit, irq_id, n; |
52 | #include "trace.h" | 52 | Exynos4210Irq *is = &s->irqs; |
53 | #include "hw/sysbus.h" | 53 | DeviceState *extgicdev = DEVICE(&s->ext_gic); |
54 | +#include "hw/irq.h" | 54 | + int splitcount = 0; |
55 | #include "migration/vmstate.h" | 55 | + DeviceState *splitter; |
56 | #include "hw/registerfields.h" | 56 | |
57 | #include "hw/misc/mps2-scc.h" | 57 | for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { |
58 | @@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value, | 58 | irq_id = 0; |
59 | switch (offset) { | 59 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) |
60 | case A_CFG0: | 60 | /* MCT_G1 is passed to External and GIC */ |
61 | /* | 61 | irq_id = EXT_GIC_ID_MCT_G1; |
62 | - * TODO on some boards bit 0 controls RAM remapping; | 62 | } |
63 | - * on others bit 1 is CPU_WAIT. | 63 | + |
64 | + * On some boards bit 0 controls board-specific remapping; | 64 | + assert(splitcount < EXYNOS4210_NUM_SPLITTERS); |
65 | + * we always reflect bit 0 in the 'remap' GPIO output line, | 65 | + splitter = DEVICE(&s->splitter[splitcount]); |
66 | + * and let the board wire it up or not as it chooses. | 66 | + qdev_prop_set_uint16(splitter, "num-lines", 2); |
67 | + * TODO on some boards bit 1 is CPU_WAIT. | 67 | + qdev_realize(splitter, NULL, &error_abort); |
68 | */ | 68 | + splitcount++; |
69 | s->cfg0 = value; | 69 | + s->irq_table[n] = qdev_get_gpio_in(splitter, 0); |
70 | + qemu_set_irq(s->remap, s->cfg0 & 1); | 70 | + qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); |
71 | break; | 71 | if (irq_id) { |
72 | case A_CFG1: | 72 | - s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], |
73 | s->cfg1 = value; | 73 | - qdev_get_gpio_in(extgicdev, |
74 | @@ -XXX,XX +XXX,XX @@ static void mps2_scc_reset(DeviceState *dev) | 74 | - irq_id - 32)); |
75 | int i; | 75 | + qdev_connect_gpio_out(splitter, 1, |
76 | 76 | + qdev_get_gpio_in(extgicdev, irq_id - 32)); | |
77 | trace_mps2_scc_reset(); | 77 | } else { |
78 | - s->cfg0 = 0; | 78 | - s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], |
79 | + s->cfg0 = s->cfg0_reset; | 79 | - is->ext_combiner_irq[n]); |
80 | s->cfg1 = 0; | 80 | + qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]); |
81 | s->cfg2 = 0; | 81 | } |
82 | s->cfg5 = 0; | 82 | } |
83 | @@ -XXX,XX +XXX,XX @@ static void mps2_scc_init(Object *obj) | 83 | for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { |
84 | 84 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | |
85 | memory_region_init_io(&s->iomem, obj, &mps2_scc_ops, s, "mps2-scc", 0x1000); | 85 | EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; |
86 | sysbus_init_mmio(sbd, &s->iomem); | 86 | |
87 | + qdev_init_gpio_out_named(DEVICE(obj), &s->remap, "remap", 1); | 87 | if (irq_id) { |
88 | - s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n], | ||
89 | - qdev_get_gpio_in(extgicdev, | ||
90 | - irq_id - 32)); | ||
91 | + assert(splitcount < EXYNOS4210_NUM_SPLITTERS); | ||
92 | + splitter = DEVICE(&s->splitter[splitcount]); | ||
93 | + qdev_prop_set_uint16(splitter, "num-lines", 2); | ||
94 | + qdev_realize(splitter, NULL, &error_abort); | ||
95 | + splitcount++; | ||
96 | + s->irq_table[n] = qdev_get_gpio_in(splitter, 0); | ||
97 | + qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); | ||
98 | + qdev_connect_gpio_out(splitter, 1, | ||
99 | + qdev_get_gpio_in(extgicdev, irq_id - 32)); | ||
100 | } | ||
101 | } | ||
102 | + /* | ||
103 | + * We check this here to avoid a more obscure assert later when | ||
104 | + * qdev_assert_realized_properly() checks that we realized every | ||
105 | + * child object we initialized. | ||
106 | + */ | ||
107 | + assert(splitcount == EXYNOS4210_NUM_SPLITTERS); | ||
88 | } | 108 | } |
89 | 109 | ||
90 | static void mps2_scc_realize(DeviceState *dev, Error **errp) | 110 | /* |
91 | @@ -XXX,XX +XXX,XX @@ static Property mps2_scc_properties[] = { | 111 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj) |
92 | DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0), | 112 | object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ); |
93 | DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0), | 113 | } |
94 | DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0), | 114 | |
95 | + /* Reset value for CFG0 register */ | 115 | + for (i = 0; i < ARRAY_SIZE(s->splitter); i++) { |
96 | + DEFINE_PROP_UINT32("scc-cfg0", MPS2SCC, cfg0_reset, 0), | 116 | + g_autofree char *name = g_strdup_printf("irq-splitter%d", i); |
97 | /* | 117 | + object_initialize_child(obj, name, &s->splitter[i], TYPE_SPLIT_IRQ); |
98 | * These are the initial settings for the source clocks on the board. | 118 | + } |
99 | * In hardware they can be configured via a config file read by the | 119 | + |
120 | object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); | ||
121 | object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC); | ||
122 | } | ||
100 | -- | 123 | -- |
101 | 2.20.1 | 124 | 2.25.1 |
102 | |||
103 | diff view generated by jsdifflib |
1 | Switch translate-vfp.c.inc from being #included into translate.c | 1 | In exynos4210_init_board_irqs(), the loop that handles IRQ lines that |
---|---|---|---|
2 | to being its own compilation unit. | 2 | are in a range that applies to the internal combiner only creates a |
3 | splitter for those interrupts which go to both the internal combiner | ||
4 | and to the external GIC, but it does nothing at all for the | ||
5 | interrupts which don't go to the external GIC, leaving the | ||
6 | irq_table[] array element empty for those. (This will result in | ||
7 | those interrupts simply being lost, not in a QEMU crash.) | ||
8 | |||
9 | I don't have a reliable datasheet for this SoC, but since we do wire | ||
10 | up one interrupt line in this category (the HDMI I2C device on | ||
11 | interrupt 16,1), this seems like it must be a bug in the existing | ||
12 | QEMU code. Fill in the irq_table[] entries where we're not splitting | ||
13 | the IRQ to both the internal combiner and the external GIC with the | ||
14 | IRQ line of the internal combiner. (That is, these IRQ lines go to | ||
15 | just one device, not multiple.) | ||
16 | |||
17 | This bug didn't have any visible guest effects because the only | ||
18 | implemented device that was affected was the HDMI I2C controller, | ||
19 | and we never connect any I2C devices to that bus. | ||
3 | 20 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 22 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20210430132740.10391-9-peter.maydell@linaro.org | 23 | Message-id: 20220404154658.565020-14-peter.maydell@linaro.org |
8 | --- | 24 | --- |
9 | target/arm/translate-a32.h | 2 ++ | 25 | hw/arm/exynos4210.c | 2 ++ |
10 | target/arm/{translate-vfp.c.inc => translate-vfp.c} | 12 +++++++----- | 26 | 1 file changed, 2 insertions(+) |
11 | target/arm/translate.c | 3 +-- | ||
12 | target/arm/meson.build | 5 +++-- | ||
13 | 4 files changed, 13 insertions(+), 9 deletions(-) | ||
14 | rename target/arm/{translate-vfp.c.inc => translate-vfp.c} (99%) | ||
15 | 27 | ||
16 | diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h | 28 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c |
17 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/translate-a32.h | 30 | --- a/hw/arm/exynos4210.c |
19 | +++ b/target/arm/translate-a32.h | 31 | +++ b/hw/arm/exynos4210.c |
20 | @@ -XXX,XX +XXX,XX @@ | 32 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) |
21 | 33 | qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); | |
22 | /* Prototypes for autogenerated disassembler functions */ | 34 | qdev_connect_gpio_out(splitter, 1, |
23 | bool disas_m_nocp(DisasContext *dc, uint32_t insn); | 35 | qdev_get_gpio_in(extgicdev, irq_id - 32)); |
24 | +bool disas_vfp(DisasContext *s, uint32_t insn); | 36 | + } else { |
25 | +bool disas_vfp_uncond(DisasContext *s, uint32_t insn); | 37 | + s->irq_table[n] = is->int_combiner_irq[n]; |
26 | 38 | } | |
27 | void load_reg_var(DisasContext *s, TCGv_i32 var, int reg); | 39 | } |
28 | void arm_gen_condlabel(DisasContext *s); | 40 | /* |
29 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c | ||
30 | similarity index 99% | ||
31 | rename from target/arm/translate-vfp.c.inc | ||
32 | rename to target/arm/translate-vfp.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/target/arm/translate-vfp.c.inc | ||
35 | +++ b/target/arm/translate-vfp.c | ||
36 | @@ -XXX,XX +XXX,XX @@ | ||
37 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | ||
38 | */ | ||
39 | |||
40 | -/* | ||
41 | - * This file is intended to be included from translate.c; it uses | ||
42 | - * some macros and definitions provided by that file. | ||
43 | - * It might be possible to convert it to a standalone .c file eventually. | ||
44 | - */ | ||
45 | +#include "qemu/osdep.h" | ||
46 | +#include "tcg/tcg-op.h" | ||
47 | +#include "tcg/tcg-op-gvec.h" | ||
48 | +#include "exec/exec-all.h" | ||
49 | +#include "exec/gen-icount.h" | ||
50 | +#include "translate.h" | ||
51 | +#include "translate-a32.h" | ||
52 | |||
53 | /* Include the generated VFP decoder */ | ||
54 | #include "decode-vfp.c.inc" | ||
55 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
56 | index XXXXXXX..XXXXXXX 100644 | ||
57 | --- a/target/arm/translate.c | ||
58 | +++ b/target/arm/translate.c | ||
59 | @@ -XXX,XX +XXX,XX @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg) | ||
60 | |||
61 | #define ARM_CP_RW_BIT (1 << 20) | ||
62 | |||
63 | -/* Include the VFP and Neon decoders */ | ||
64 | -#include "translate-vfp.c.inc" | ||
65 | +/* Include the Neon decoder */ | ||
66 | #include "translate-neon.c.inc" | ||
67 | |||
68 | static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) | ||
69 | diff --git a/target/arm/meson.build b/target/arm/meson.build | ||
70 | index XXXXXXX..XXXXXXX 100644 | ||
71 | --- a/target/arm/meson.build | ||
72 | +++ b/target/arm/meson.build | ||
73 | @@ -XXX,XX +XXX,XX @@ gen = [ | ||
74 | decodetree.process('neon-shared.decode', extra_args: '--static-decode=disas_neon_shared'), | ||
75 | decodetree.process('neon-dp.decode', extra_args: '--static-decode=disas_neon_dp'), | ||
76 | decodetree.process('neon-ls.decode', extra_args: '--static-decode=disas_neon_ls'), | ||
77 | - decodetree.process('vfp.decode', extra_args: '--static-decode=disas_vfp'), | ||
78 | - decodetree.process('vfp-uncond.decode', extra_args: '--static-decode=disas_vfp_uncond'), | ||
79 | + decodetree.process('vfp.decode', extra_args: '--decode=disas_vfp'), | ||
80 | + decodetree.process('vfp-uncond.decode', extra_args: '--decode=disas_vfp_uncond'), | ||
81 | decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp'), | ||
82 | decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'), | ||
83 | decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'), | ||
84 | @@ -XXX,XX +XXX,XX @@ arm_ss.add(files( | ||
85 | 'tlb_helper.c', | ||
86 | 'translate.c', | ||
87 | 'translate-m-nocp.c', | ||
88 | + 'translate-vfp.c', | ||
89 | 'vec_helper.c', | ||
90 | 'vfp_helper.c', | ||
91 | 'cpu_tcg.c', | ||
92 | -- | 41 | -- |
93 | 2.20.1 | 42 | 2.25.1 |
94 | |||
95 | diff view generated by jsdifflib |
1 | Move the NeonGenThreeOpEnvFn typedef to translate.h together | 1 | Currently for the interrupts MCT_G0 and MCT_G1 which are |
---|---|---|---|
2 | with the other similar typedefs. | 2 | the only ones in the input range of the external combiner |
3 | and which are also wired to the external GIC, we connect | ||
4 | them only to the internal combiner and the external GIC. | ||
5 | This seems likely to be a bug, as all other interrupts | ||
6 | which are in the input range of both combiners are | ||
7 | connected to both combiners. (The fact that the code in | ||
8 | exynos4210_combiner_get_gpioin() is also trying to wire | ||
9 | up these inputs on both combiners also suggests this.) | ||
10 | |||
11 | Wire these interrupts up to both combiners, like the rest. | ||
3 | 12 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 15 | Message-id: 20220404154658.565020-15-peter.maydell@linaro.org |
7 | Message-id: 20210430132740.10391-12-peter.maydell@linaro.org | ||
8 | --- | 16 | --- |
9 | target/arm/translate.h | 2 ++ | 17 | hw/arm/exynos4210.c | 7 +++---- |
10 | target/arm/translate.c | 3 --- | 18 | 1 file changed, 3 insertions(+), 4 deletions(-) |
11 | 2 files changed, 2 insertions(+), 3 deletions(-) | ||
12 | 19 | ||
13 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 20 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c |
14 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/translate.h | 22 | --- a/hw/arm/exynos4210.c |
16 | +++ b/target/arm/translate.h | 23 | +++ b/hw/arm/exynos4210.c |
17 | @@ -XXX,XX +XXX,XX @@ typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32); | 24 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) |
18 | typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32); | 25 | |
19 | typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32); | 26 | assert(splitcount < EXYNOS4210_NUM_SPLITTERS); |
20 | typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); | 27 | splitter = DEVICE(&s->splitter[splitcount]); |
21 | +typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, | 28 | - qdev_prop_set_uint16(splitter, "num-lines", 2); |
22 | + TCGv_i32, TCGv_i32); | 29 | + qdev_prop_set_uint16(splitter, "num-lines", irq_id ? 3 : 2); |
23 | typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64); | 30 | qdev_realize(splitter, NULL, &error_abort); |
24 | typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64); | 31 | splitcount++; |
25 | typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); | 32 | s->irq_table[n] = qdev_get_gpio_in(splitter, 0); |
26 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 33 | qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); |
27 | index XXXXXXX..XXXXXXX 100644 | 34 | + qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]); |
28 | --- a/target/arm/translate.c | 35 | if (irq_id) { |
29 | +++ b/target/arm/translate.c | 36 | - qdev_connect_gpio_out(splitter, 1, |
30 | @@ -XXX,XX +XXX,XX @@ static const char * const regnames[] = | 37 | + qdev_connect_gpio_out(splitter, 2, |
31 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | 38 | qdev_get_gpio_in(extgicdev, irq_id - 32)); |
32 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" }; | 39 | - } else { |
33 | 40 | - qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]); | |
34 | -/* Function prototypes for gen_ functions calling Neon helpers. */ | 41 | } |
35 | -typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, | 42 | } |
36 | - TCGv_i32, TCGv_i32); | 43 | for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { |
37 | |||
38 | /* initialize TCG globals. */ | ||
39 | void arm_translate_init(void) | ||
40 | -- | 44 | -- |
41 | 2.20.1 | 45 | 2.25.1 |
42 | |||
43 | diff view generated by jsdifflib |
1 | The VFPGenFixPointFn typedef is unused; delete it. | 1 | The combiner_grp_to_gic_id[] array includes the EXT_GIC_ID_MCT_G0 |
---|---|---|---|
2 | and EXT_GIC_ID_MCT_G1 multiple times. This means that we will | ||
3 | connect multiple IRQs up to the same external GIC input, which | ||
4 | is not permitted. We do the same thing in the code in | ||
5 | exynos4210_init_board_irqs() because the conditionals selecting | ||
6 | an irq_id in the first loop match multiple interrupt IDs. | ||
7 | |||
8 | Overall we do this for interrupt IDs | ||
9 | (1, 4), (12, 4), (35, 4), (51, 4), (53, 4) for EXT_GIC_ID_MCT_G0 | ||
10 | and | ||
11 | (1, 5), (12, 5), (35, 5), (51, 5), (53, 5) for EXT_GIC_ID_MCT_G1 | ||
12 | |||
13 | These correspond to the cases for the multi-core timer that we are | ||
14 | wiring up to multiple inputs on the combiner in | ||
15 | exynos4210_combiner_get_gpioin(). That code already deals with all | ||
16 | these interrupt IDs being the same input source, so we don't need to | ||
17 | connect the external GIC interrupt for any of them except the first | ||
18 | (1, 4) and (1, 5). Remove the array entries and conditionals which | ||
19 | were incorrectly causing us to wire up extra lines. | ||
20 | |||
21 | This bug didn't cause any visible effects, because we only connect | ||
22 | up a device to the "primary" ID values (1, 4) and (1, 5), so the | ||
23 | extra lines would never be set to a level. | ||
2 | 24 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 26 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 27 | Message-id: 20220404154658.565020-16-peter.maydell@linaro.org |
6 | Message-id: 20210430132740.10391-11-peter.maydell@linaro.org | ||
7 | --- | 28 | --- |
8 | target/arm/translate.c | 2 -- | 29 | include/hw/arm/exynos4210.h | 2 +- |
9 | 1 file changed, 2 deletions(-) | 30 | hw/arm/exynos4210.c | 12 +++++------- |
31 | 2 files changed, 6 insertions(+), 8 deletions(-) | ||
10 | 32 | ||
11 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 33 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h |
12 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/translate.c | 35 | --- a/include/hw/arm/exynos4210.h |
14 | +++ b/target/arm/translate.c | 36 | +++ b/include/hw/arm/exynos4210.h |
15 | @@ -XXX,XX +XXX,XX @@ static const char * const regnames[] = | 37 | @@ -XXX,XX +XXX,XX @@ |
16 | /* Function prototypes for gen_ functions calling Neon helpers. */ | 38 | * one for every non-zero entry in combiner_grp_to_gic_id[]. |
17 | typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, | 39 | * We'll assert in exynos4210_init_board_irqs() if this is wrong. |
18 | TCGv_i32, TCGv_i32); | 40 | */ |
19 | -/* Function prototypes for gen_ functions for fix point conversions */ | 41 | -#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 60) |
20 | -typedef void VFPGenFixPointFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); | 42 | +#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 54) |
21 | 43 | ||
22 | /* initialize TCG globals. */ | 44 | typedef struct Exynos4210Irq { |
23 | void arm_translate_init(void) | 45 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; |
46 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/hw/arm/exynos4210.c | ||
49 | +++ b/hw/arm/exynos4210.c | ||
50 | @@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
51 | /* int combiner group 34 */ | ||
52 | { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, | ||
53 | /* int combiner group 35 */ | ||
54 | - { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
55 | + { 0, 0, 0, EXT_GIC_ID_MCT_L1 }, | ||
56 | /* int combiner group 36 */ | ||
57 | { EXT_GIC_ID_MIXER }, | ||
58 | /* int combiner group 37 */ | ||
59 | @@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { | ||
60 | /* groups 38-50 */ | ||
61 | { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, | ||
62 | /* int combiner group 51 */ | ||
63 | - { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
64 | + { EXT_GIC_ID_MCT_L0 }, | ||
65 | /* group 52 */ | ||
66 | { }, | ||
67 | /* int combiner group 53 */ | ||
68 | - { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, | ||
69 | + { EXT_GIC_ID_WDT }, | ||
70 | /* groups 54-63 */ | ||
71 | { }, { }, { }, { }, { }, { }, { }, { }, { }, { } | ||
72 | }; | ||
73 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
74 | |||
75 | for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { | ||
76 | irq_id = 0; | ||
77 | - if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) || | ||
78 | - n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) { | ||
79 | + if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4)) { | ||
80 | /* MCT_G0 is passed to External GIC */ | ||
81 | irq_id = EXT_GIC_ID_MCT_G0; | ||
82 | } | ||
83 | - if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) || | ||
84 | - n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) { | ||
85 | + if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5)) { | ||
86 | /* MCT_G1 is passed to External and GIC */ | ||
87 | irq_id = EXT_GIC_ID_MCT_G1; | ||
88 | } | ||
24 | -- | 89 | -- |
25 | 2.20.1 | 90 | 2.25.1 |
26 | |||
27 | diff view generated by jsdifflib |
1 | The AN524 FPGA image supports two memory maps, which differ in where | 1 | At this point, the function exynos4210_init_board_irqs() splits input |
---|---|---|---|
2 | the QSPI and BRAM are. In the default map, the BRAM is at | 2 | IRQ lines to connect them to the input combiner, output combiner and |
3 | 0x0000_0000, and the QSPI at 0x2800_0000. In the second map, they | 3 | external GIC. The function exynos4210_combiner_get_gpioin() splits |
4 | are the other way around. | 4 | some of the combiner input lines further to connect them to multiple |
5 | 5 | different inputs on the combiner. | |
6 | In hardware, the initial mapping can be selected by the user by | 6 | |
7 | writing either "REMAP: BRAM" (the default) or "REMAP: QSPI" in the | 7 | Because (unlike qemu_irq_split()) the TYPE_SPLIT_IRQ device has a |
8 | board configuration file. The board config file is acted on by the | 8 | configurable number of outputs, we can do all this in one place, by |
9 | "Motherboard Configuration Controller", which is an entirely separate | 9 | making exynos4210_init_board_irqs() add extra outputs to the splitter |
10 | microcontroller on the dev board but outside the FPGA. | 10 | device when it must be connected to more than one input on each |
11 | 11 | combiner. | |
12 | The guest can also dynamically change the mapping via the SCC | 12 | |
13 | CFG_REG0 register. | 13 | We do this with a new data structure, the combinermap, which is an |
14 | 14 | array each of whose elements is a list of the interrupt IDs on the | |
15 | Implement this functionality for QEMU, using a machine property | 15 | combiner which must be tied together. As we loop through each |
16 | "remap" with valid values "BRAM" and "QSPI" to allow the user to set | 16 | interrupt ID, if we find that it is the first one in one of these |
17 | the initial mapping, in the same way they can on the FPGA, and | 17 | lists, we configure the splitter device with eonugh extra outputs and |
18 | wiring up the bit from the SCC register to also switch the mapping. | 18 | wire them up to the other interrupt IDs in the list. |
19 | |||
20 | Conveniently, for all the cases where this is necessary, the | ||
21 | lowest-numbered interrupt ID in each group is in the range of the | ||
22 | external combiner, so we only need to code for this in the first of | ||
23 | the two loops in exynos4210_init_board_irqs(). | ||
24 | |||
25 | The old code in exynos4210_combiner_get_gpioin() which is being | ||
26 | deleted here had several problems which don't exist in the new code | ||
27 | in its handling of the multi-core timer interrupts: | ||
28 | (1) the case labels specified bits 4 ... 8, but bit '8' doesn't | ||
29 | exist; these should have been 4 ... 7 | ||
30 | (2) it used the input irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)] | ||
31 | multiple times as the input of several different splitters, | ||
32 | which isn't allowed | ||
33 | (3) in an apparent cut-and-paste error, the cases for all the | ||
34 | multi-core timer inputs used "bit + 4" even though the | ||
35 | bit range for the case was (intended to be) 4 ... 7, which | ||
36 | meant it was looking at non-existent bits 8 ... 11. | ||
37 | None of these exist in the new code. | ||
19 | 38 | ||
20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 39 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
21 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 40 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
22 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 41 | Message-id: 20220404154658.565020-17-peter.maydell@linaro.org |
23 | Message-id: 20210504120912.23094-4-peter.maydell@linaro.org | ||
24 | --- | 42 | --- |
25 | docs/system/arm/mps2.rst | 10 ++++ | 43 | include/hw/arm/exynos4210.h | 6 +- |
26 | hw/arm/mps2-tz.c | 108 ++++++++++++++++++++++++++++++++++++++- | 44 | hw/arm/exynos4210.c | 178 +++++++++++++++++++++++------------- |
27 | 2 files changed, 117 insertions(+), 1 deletion(-) | 45 | 2 files changed, 119 insertions(+), 65 deletions(-) |
28 | 46 | ||
29 | diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst | 47 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h |
30 | index XXXXXXX..XXXXXXX 100644 | 48 | index XXXXXXX..XXXXXXX 100644 |
31 | --- a/docs/system/arm/mps2.rst | 49 | --- a/include/hw/arm/exynos4210.h |
32 | +++ b/docs/system/arm/mps2.rst | 50 | +++ b/include/hw/arm/exynos4210.h |
33 | @@ -XXX,XX +XXX,XX @@ Differences between QEMU and real hardware: | 51 | @@ -XXX,XX +XXX,XX @@ |
34 | flash, but only as simple ROM, so attempting to rewrite the flash | 52 | |
35 | from the guest will fail | 53 | /* |
36 | - QEMU does not model the USB controller in MPS3 boards | 54 | * We need one splitter for every external combiner input, plus |
37 | + | 55 | - * one for every non-zero entry in combiner_grp_to_gic_id[]. |
38 | +Machine-specific options | 56 | + * one for every non-zero entry in combiner_grp_to_gic_id[], |
39 | +"""""""""""""""""""""""" | 57 | + * minus one for every external combiner ID in second or later |
40 | + | 58 | + * places in a combinermap[] line. |
41 | +The following machine-specific options are supported: | 59 | * We'll assert in exynos4210_init_board_irqs() if this is wrong. |
42 | + | 60 | */ |
43 | +remap | 61 | -#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 54) |
44 | + Supported for ``mps3-an524`` only. | 62 | +#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38) |
45 | + Set ``BRAM``/``QSPI`` to select the initial memory mapping. The | 63 | |
46 | + default is ``BRAM``. | 64 | typedef struct Exynos4210Irq { |
47 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c | 65 | qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; |
66 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | 67 | index XXXXXXX..XXXXXXX 100644 |
49 | --- a/hw/arm/mps2-tz.c | 68 | --- a/hw/arm/exynos4210.c |
50 | +++ b/hw/arm/mps2-tz.c | 69 | +++ b/hw/arm/exynos4210.c |
51 | @@ -XXX,XX +XXX,XX @@ | 70 | @@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { |
52 | #include "hw/boards.h" | 71 | #define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ |
53 | #include "exec/address-spaces.h" | 72 | ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) |
54 | #include "sysemu/sysemu.h" | ||
55 | +#include "sysemu/reset.h" | ||
56 | #include "hw/misc/unimp.h" | ||
57 | #include "hw/char/cmsdk-apb-uart.h" | ||
58 | #include "hw/timer/cmsdk-apb-timer.h" | ||
59 | @@ -XXX,XX +XXX,XX @@ | ||
60 | #include "hw/core/split-irq.h" | ||
61 | #include "hw/qdev-clock.h" | ||
62 | #include "qom/object.h" | ||
63 | +#include "hw/irq.h" | ||
64 | |||
65 | #define MPS2TZ_NUMIRQ_MAX 96 | ||
66 | #define MPS2TZ_RAM_MAX 5 | ||
67 | @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState { | ||
68 | SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX]; | ||
69 | Clock *sysclk; | ||
70 | Clock *s32kclk; | ||
71 | + | ||
72 | + bool remap; | ||
73 | + qemu_irq remap_irq; | ||
74 | }; | ||
75 | |||
76 | #define TYPE_MPS2TZ_MACHINE "mps2tz" | ||
77 | @@ -XXX,XX +XXX,XX @@ static const RAMInfo an505_raminfo[] = { { | ||
78 | }, | ||
79 | }; | ||
80 | 73 | ||
81 | +/* | 74 | +/* |
82 | + * Note that the addresses and MPC numbering here should match up | 75 | + * Some interrupt lines go to multiple combiner inputs. |
83 | + * with those used in remap_memory(), which can swap the BRAM and QSPI. | 76 | + * This data structure defines those: each array element is |
77 | + * a list of combiner inputs which are connected together; | ||
78 | + * the one with the smallest interrupt ID value must be first. | ||
79 | + * As with combiner_grp_to_gic_id[], we rely on (0, 0) not being | ||
80 | + * wired to anything so we can use 0 as a terminator. | ||
84 | + */ | 81 | + */ |
85 | static const RAMInfo an524_raminfo[] = { { | 82 | +#define IRQNO(G, B) EXYNOS4210_COMBINER_GET_IRQ_NUM(G, B) |
86 | .name = "bram", | 83 | +#define IRQNONE 0 |
87 | .base = 0x00000000, | 84 | + |
88 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, | 85 | +#define COMBINERMAP_SIZE 16 |
89 | 86 | + | |
90 | object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC); | 87 | +static const int combinermap[COMBINERMAP_SIZE][6] = { |
91 | sccdev = DEVICE(scc); | 88 | + /* MDNIE_LCD1 */ |
92 | + qdev_prop_set_uint32(sccdev, "scc-cfg0", mms->remap ? 1 : 0); | 89 | + { IRQNO(0, 4), IRQNO(1, 0), IRQNONE }, |
93 | qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); | 90 | + { IRQNO(0, 5), IRQNO(1, 1), IRQNONE }, |
94 | qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); | 91 | + { IRQNO(0, 6), IRQNO(1, 2), IRQNONE }, |
95 | qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); | 92 | + { IRQNO(0, 7), IRQNO(1, 3), IRQNONE }, |
96 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, | 93 | + /* TMU */ |
97 | return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); | 94 | + { IRQNO(2, 4), IRQNO(3, 4), IRQNONE }, |
98 | } | 95 | + { IRQNO(2, 5), IRQNO(3, 5), IRQNONE }, |
99 | 96 | + { IRQNO(2, 6), IRQNO(3, 6), IRQNONE }, | |
100 | +static hwaddr boot_mem_base(MPS2TZMachineState *mms) | 97 | + { IRQNO(2, 7), IRQNO(3, 7), IRQNONE }, |
98 | + /* LCD1 */ | ||
99 | + { IRQNO(11, 4), IRQNO(12, 0), IRQNONE }, | ||
100 | + { IRQNO(11, 5), IRQNO(12, 1), IRQNONE }, | ||
101 | + { IRQNO(11, 6), IRQNO(12, 2), IRQNONE }, | ||
102 | + { IRQNO(11, 7), IRQNO(12, 3), IRQNONE }, | ||
103 | + /* Multi-core timer */ | ||
104 | + { IRQNO(1, 4), IRQNO(12, 4), IRQNO(35, 4), IRQNO(51, 4), IRQNO(53, 4), IRQNONE }, | ||
105 | + { IRQNO(1, 5), IRQNO(12, 5), IRQNO(35, 5), IRQNO(51, 5), IRQNO(53, 5), IRQNONE }, | ||
106 | + { IRQNO(1, 6), IRQNO(12, 6), IRQNO(35, 6), IRQNO(51, 6), IRQNO(53, 6), IRQNONE }, | ||
107 | + { IRQNO(1, 7), IRQNO(12, 7), IRQNO(35, 7), IRQNO(51, 7), IRQNO(53, 7), IRQNONE }, | ||
108 | +}; | ||
109 | + | ||
110 | +#undef IRQNO | ||
111 | + | ||
112 | +static const int *combinermap_entry(int irq) | ||
101 | +{ | 113 | +{ |
102 | + /* | 114 | + /* |
103 | + * Return the canonical address of the block which will be mapped | 115 | + * If the interrupt number passed in is the first entry in some |
104 | + * at address 0x0 (i.e. where the vector table is). | 116 | + * line of the combinermap, return a pointer to that line; |
105 | + * This is usually 0, but if the AN524 alternate memory map is | 117 | + * otherwise return NULL. |
106 | + * enabled it will be the base address of the QSPI block. | ||
107 | + */ | 118 | + */ |
108 | + return mms->remap ? 0x28000000 : 0; | 119 | + int i; |
120 | + for (i = 0; i < COMBINERMAP_SIZE; i++) { | ||
121 | + if (combinermap[i][0] == irq) { | ||
122 | + return combinermap[i]; | ||
123 | + } | ||
124 | + } | ||
125 | + return NULL; | ||
109 | +} | 126 | +} |
110 | + | 127 | + |
111 | +static void remap_memory(MPS2TZMachineState *mms, int map) | 128 | +static int mapline_size(const int *mapline) |
112 | +{ | 129 | +{ |
113 | + /* | 130 | + /* Return number of entries in this mapline in total */ |
114 | + * Remap the memory for the AN524. 'map' is the value of | 131 | + int i = 0; |
115 | + * SCC CFG_REG0 bit 0, i.e. 0 for the default map and 1 | 132 | + |
116 | + * for the "option 1" mapping where QSPI is at address 0. | 133 | + if (!mapline) { |
117 | + * | 134 | + /* Not in the map? IRQ goes to exactly one combiner input */ |
118 | + * Effectively we need to swap around the "upstream" ends of | 135 | + return 1; |
119 | + * MPC 0 and MPC 1. | ||
120 | + */ | ||
121 | + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); | ||
122 | + int i; | ||
123 | + | ||
124 | + if (mmc->fpga_type != FPGA_AN524) { | ||
125 | + return; | ||
126 | + } | 136 | + } |
127 | + | 137 | + while (*mapline != IRQNONE) { |
128 | + memory_region_transaction_begin(); | 138 | + mapline++; |
129 | + for (i = 0; i < 2; i++) { | 139 | + i++; |
130 | + TZMPC *mpc = &mms->mpc[i]; | ||
131 | + MemoryRegion *upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); | ||
132 | + hwaddr addr = (i ^ map) ? 0x28000000 : 0; | ||
133 | + | ||
134 | + memory_region_set_address(upstream, addr); | ||
135 | + } | 140 | + } |
136 | + memory_region_transaction_commit(); | 141 | + return i; |
137 | +} | 142 | +} |
138 | + | 143 | + |
139 | +static void remap_irq_fn(void *opaque, int n, int level) | 144 | /* |
140 | +{ | 145 | * Initialize board IRQs. |
141 | + MPS2TZMachineState *mms = opaque; | 146 | * These IRQs contain splitted Int/External Combiner and External Gic IRQs. |
142 | + | 147 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) |
143 | + remap_memory(mms, level); | 148 | DeviceState *extgicdev = DEVICE(&s->ext_gic); |
144 | +} | 149 | int splitcount = 0; |
145 | + | 150 | DeviceState *splitter; |
146 | static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, | 151 | + const int *mapline; |
147 | const char *name, hwaddr size, | 152 | + int numlines, splitin, in; |
148 | const int *irqs) | 153 | |
149 | @@ -XXX,XX +XXX,XX @@ static uint32_t boot_ram_size(MPS2TZMachineState *mms) | 154 | for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { |
150 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); | 155 | irq_id = 0; |
151 | 156 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | |
152 | for (p = mmc->raminfo; p->name; p++) { | 157 | irq_id = EXT_GIC_ID_MCT_G1; |
153 | - if (p->base == 0) { | 158 | } |
154 | + if (p->base == boot_mem_base(mms)) { | 159 | |
155 | return p->size; | 160 | + if (s->irq_table[n]) { |
161 | + /* | ||
162 | + * This must be some non-first entry in a combinermap line, | ||
163 | + * and we've already filled it in. | ||
164 | + */ | ||
165 | + continue; | ||
166 | + } | ||
167 | + mapline = combinermap_entry(n); | ||
168 | + /* | ||
169 | + * We need to connect the IRQ to multiple inputs on both combiners | ||
170 | + * and possibly also to the external GIC. | ||
171 | + */ | ||
172 | + numlines = 2 * mapline_size(mapline); | ||
173 | + if (irq_id) { | ||
174 | + numlines++; | ||
175 | + } | ||
176 | assert(splitcount < EXYNOS4210_NUM_SPLITTERS); | ||
177 | splitter = DEVICE(&s->splitter[splitcount]); | ||
178 | - qdev_prop_set_uint16(splitter, "num-lines", irq_id ? 3 : 2); | ||
179 | + qdev_prop_set_uint16(splitter, "num-lines", numlines); | ||
180 | qdev_realize(splitter, NULL, &error_abort); | ||
181 | splitcount++; | ||
182 | - s->irq_table[n] = qdev_get_gpio_in(splitter, 0); | ||
183 | - qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); | ||
184 | - qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]); | ||
185 | + | ||
186 | + in = n; | ||
187 | + splitin = 0; | ||
188 | + for (;;) { | ||
189 | + s->irq_table[in] = qdev_get_gpio_in(splitter, 0); | ||
190 | + qdev_connect_gpio_out(splitter, splitin, is->int_combiner_irq[in]); | ||
191 | + qdev_connect_gpio_out(splitter, splitin + 1, is->ext_combiner_irq[in]); | ||
192 | + splitin += 2; | ||
193 | + if (!mapline) { | ||
194 | + break; | ||
195 | + } | ||
196 | + mapline++; | ||
197 | + in = *mapline; | ||
198 | + if (in == IRQNONE) { | ||
199 | + break; | ||
200 | + } | ||
201 | + } | ||
202 | if (irq_id) { | ||
203 | - qdev_connect_gpio_out(splitter, 2, | ||
204 | + qdev_connect_gpio_out(splitter, splitin, | ||
205 | qdev_get_gpio_in(extgicdev, irq_id - 32)); | ||
156 | } | 206 | } |
157 | } | 207 | } |
158 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) | 208 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) |
159 | 209 | irq_id = combiner_grp_to_gic_id[grp - | |
160 | create_non_mpc_ram(mms); | 210 | EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; |
161 | 211 | ||
162 | + if (mmc->fpga_type == FPGA_AN524) { | 212 | + if (s->irq_table[n]) { |
163 | + /* | 213 | + /* |
164 | + * Connect the line from the SCC so that we can remap when the | 214 | + * This must be some non-first entry in a combinermap line, |
165 | + * guest updates that register. | 215 | + * and we've already filled it in. |
166 | + */ | 216 | + */ |
167 | + mms->remap_irq = qemu_allocate_irq(remap_irq_fn, mms, 0); | 217 | + continue; |
168 | + qdev_connect_gpio_out_named(DEVICE(&mms->scc), "remap", 0, | 218 | + } |
169 | + mms->remap_irq); | 219 | + |
170 | + } | 220 | if (irq_id) { |
171 | + | 221 | assert(splitcount < EXYNOS4210_NUM_SPLITTERS); |
172 | armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, | 222 | splitter = DEVICE(&s->splitter[splitcount]); |
173 | boot_ram_size(mms)); | 223 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, |
224 | DeviceState *dev, int ext) | ||
225 | { | ||
226 | int n; | ||
227 | - int bit; | ||
228 | int max; | ||
229 | qemu_irq *irq; | ||
230 | |||
231 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, | ||
232 | EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; | ||
233 | irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq; | ||
234 | |||
235 | - /* | ||
236 | - * Some IRQs of Int/External Combiner are going to two Combiners groups, | ||
237 | - * so let split them. | ||
238 | - */ | ||
239 | for (n = 0; n < max; n++) { | ||
240 | - | ||
241 | - bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); | ||
242 | - | ||
243 | - switch (n) { | ||
244 | - /* MDNIE_LCD1 INTG1 */ | ||
245 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ... | ||
246 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3): | ||
247 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
248 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]); | ||
249 | - continue; | ||
250 | - | ||
251 | - /* TMU INTG3 */ | ||
252 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4): | ||
253 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
254 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]); | ||
255 | - continue; | ||
256 | - | ||
257 | - /* LCD1 INTG12 */ | ||
258 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ... | ||
259 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3): | ||
260 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
261 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]); | ||
262 | - continue; | ||
263 | - | ||
264 | - /* Multi-Core Timer INTG12 */ | ||
265 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ... | ||
266 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8): | ||
267 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
268 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
269 | - continue; | ||
270 | - | ||
271 | - /* Multi-Core Timer INTG35 */ | ||
272 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ... | ||
273 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8): | ||
274 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
275 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
276 | - continue; | ||
277 | - | ||
278 | - /* Multi-Core Timer INTG51 */ | ||
279 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ... | ||
280 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8): | ||
281 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
282 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
283 | - continue; | ||
284 | - | ||
285 | - /* Multi-Core Timer INTG53 */ | ||
286 | - case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ... | ||
287 | - EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8): | ||
288 | - irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n), | ||
289 | - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); | ||
290 | - continue; | ||
291 | - } | ||
292 | - | ||
293 | irq[n] = qdev_get_gpio_in(dev, n); | ||
294 | } | ||
174 | } | 295 | } |
175 | @@ -XXX,XX +XXX,XX @@ static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, | ||
176 | *iregion = region; | ||
177 | } | ||
178 | |||
179 | +static char *mps2_get_remap(Object *obj, Error **errp) | ||
180 | +{ | ||
181 | + MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj); | ||
182 | + const char *val = mms->remap ? "QSPI" : "BRAM"; | ||
183 | + return g_strdup(val); | ||
184 | +} | ||
185 | + | ||
186 | +static void mps2_set_remap(Object *obj, const char *value, Error **errp) | ||
187 | +{ | ||
188 | + MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj); | ||
189 | + | ||
190 | + if (!strcmp(value, "BRAM")) { | ||
191 | + mms->remap = false; | ||
192 | + } else if (!strcmp(value, "QSPI")) { | ||
193 | + mms->remap = true; | ||
194 | + } else { | ||
195 | + error_setg(errp, "Invalid remap value"); | ||
196 | + error_append_hint(errp, "Valid values are BRAM and QSPI.\n"); | ||
197 | + } | ||
198 | +} | ||
199 | + | ||
200 | +static void mps2_machine_reset(MachineState *machine) | ||
201 | +{ | ||
202 | + MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); | ||
203 | + | ||
204 | + /* | ||
205 | + * Set the initial memory mapping before triggering the reset of | ||
206 | + * the rest of the system, so that the guest image loader and CPU | ||
207 | + * reset see the correct mapping. | ||
208 | + */ | ||
209 | + remap_memory(mms, mms->remap); | ||
210 | + qemu_devices_reset(); | ||
211 | +} | ||
212 | + | ||
213 | static void mps2tz_class_init(ObjectClass *oc, void *data) | ||
214 | { | ||
215 | MachineClass *mc = MACHINE_CLASS(oc); | ||
216 | IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc); | ||
217 | |||
218 | mc->init = mps2tz_common_init; | ||
219 | + mc->reset = mps2_machine_reset; | ||
220 | iic->check = mps2_tz_idau_check; | ||
221 | } | ||
222 | |||
223 | @@ -XXX,XX +XXX,XX @@ static void mps3tz_an524_class_init(ObjectClass *oc, void *data) | ||
224 | mmc->raminfo = an524_raminfo; | ||
225 | mmc->armsse_type = TYPE_SSE200; | ||
226 | mps2tz_set_default_ram_info(mmc); | ||
227 | + | ||
228 | + object_class_property_add_str(oc, "remap", mps2_get_remap, mps2_set_remap); | ||
229 | + object_class_property_set_description(oc, "remap", | ||
230 | + "Set memory mapping. Valid values " | ||
231 | + "are BRAM (default) and QSPI."); | ||
232 | } | ||
233 | |||
234 | static void mps3tz_an547_class_init(ObjectClass *oc, void *data) | ||
235 | -- | 296 | -- |
236 | 2.20.1 | 297 | 2.25.1 |
237 | |||
238 | diff view generated by jsdifflib |
1 | We want to split out the .c.inc files which are currently included | 1 | Switch the creation of the combiner devices to the new-style |
---|---|---|---|
2 | into translate.c so they are separate compilation units. To do this | 2 | "embedded in state struct" approach, so we can easily refer |
3 | we need to make some functions which are currently file-local to | 3 | to the object elsewhere during realize. |
4 | translate.c have global scope; create a translate-a32.h paralleling | ||
5 | the existing translate-a64.h as a place for these declarations to | ||
6 | live, so that code moved into the new compilation units can call | ||
7 | them. | ||
8 | |||
9 | The functions made global here are those required by the | ||
10 | m-nocp.decode functions, except that I have converted the whole | ||
11 | family of {read,write}_neon_element* and also both the load_cpu and | ||
12 | store_cpu functions for consistency, even though m-nocp only wants a | ||
13 | few functions from each. | ||
14 | 4 | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
17 | Message-id: 20210430132740.10391-4-peter.maydell@linaro.org | 7 | Message-id: 20220404154658.565020-18-peter.maydell@linaro.org |
18 | --- | 8 | --- |
19 | target/arm/translate-a32.h | 57 ++++++++++++++++++++++++++++++++++ | 9 | include/hw/arm/exynos4210.h | 3 ++ |
20 | target/arm/translate.c | 39 +++++------------------ | 10 | include/hw/intc/exynos4210_combiner.h | 57 +++++++++++++++++++++++++++ |
21 | target/arm/translate-vfp.c.inc | 2 +- | 11 | hw/arm/exynos4210.c | 20 +++++----- |
22 | 3 files changed, 65 insertions(+), 33 deletions(-) | 12 | hw/intc/exynos4210_combiner.c | 31 +-------------- |
23 | create mode 100644 target/arm/translate-a32.h | 13 | 4 files changed, 72 insertions(+), 39 deletions(-) |
14 | create mode 100644 include/hw/intc/exynos4210_combiner.h | ||
24 | 15 | ||
25 | diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h | 16 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h |
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/include/hw/arm/exynos4210.h | ||
19 | +++ b/include/hw/arm/exynos4210.h | ||
20 | @@ -XXX,XX +XXX,XX @@ | ||
21 | #include "hw/sysbus.h" | ||
22 | #include "hw/cpu/a9mpcore.h" | ||
23 | #include "hw/intc/exynos4210_gic.h" | ||
24 | +#include "hw/intc/exynos4210_combiner.h" | ||
25 | #include "hw/core/split-irq.h" | ||
26 | #include "target/arm/cpu-qom.h" | ||
27 | #include "qom/object.h" | ||
28 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { | ||
29 | qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; | ||
30 | A9MPPrivState a9mpcore; | ||
31 | Exynos4210GicState ext_gic; | ||
32 | + Exynos4210CombinerState int_combiner; | ||
33 | + Exynos4210CombinerState ext_combiner; | ||
34 | SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS]; | ||
35 | }; | ||
36 | |||
37 | diff --git a/include/hw/intc/exynos4210_combiner.h b/include/hw/intc/exynos4210_combiner.h | ||
26 | new file mode 100644 | 38 | new file mode 100644 |
27 | index XXXXXXX..XXXXXXX | 39 | index XXXXXXX..XXXXXXX |
28 | --- /dev/null | 40 | --- /dev/null |
29 | +++ b/target/arm/translate-a32.h | 41 | +++ b/include/hw/intc/exynos4210_combiner.h |
30 | @@ -XXX,XX +XXX,XX @@ | 42 | @@ -XXX,XX +XXX,XX @@ |
31 | +/* | 43 | +/* |
32 | + * AArch32 translation, common definitions. | 44 | + * Samsung exynos4210 Interrupt Combiner |
33 | + * | 45 | + * |
34 | + * Copyright (c) 2021 Linaro, Ltd. | 46 | + * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. |
47 | + * All rights reserved. | ||
35 | + * | 48 | + * |
36 | + * This library is free software; you can redistribute it and/or | 49 | + * Evgeny Voevodin <e.voevodin@samsung.com> |
37 | + * modify it under the terms of the GNU Lesser General Public | ||
38 | + * License as published by the Free Software Foundation; either | ||
39 | + * version 2.1 of the License, or (at your option) any later version. | ||
40 | + * | 50 | + * |
41 | + * This library is distributed in the hope that it will be useful, | 51 | + * This program is free software; you can redistribute it and/or modify it |
52 | + * under the terms of the GNU General Public License as published by the | ||
53 | + * Free Software Foundation; either version 2 of the License, or (at your | ||
54 | + * option) any later version. | ||
55 | + * | ||
56 | + * This program is distributed in the hope that it will be useful, | ||
42 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | 57 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
43 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | 58 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
44 | + * Lesser General Public License for more details. | 59 | + * See the GNU General Public License for more details. |
45 | + * | 60 | + * |
46 | + * You should have received a copy of the GNU Lesser General Public | 61 | + * You should have received a copy of the GNU General Public License along |
47 | + * License along with this library; if not, see <http://www.gnu.org/licenses/>. | 62 | + * with this program; if not, see <http://www.gnu.org/licenses/>. |
48 | + */ | 63 | + */ |
49 | + | 64 | + |
50 | +#ifndef TARGET_ARM_TRANSLATE_A64_H | 65 | +#ifndef HW_INTC_EXYNOS4210_COMBINER |
51 | +#define TARGET_ARM_TRANSLATE_A64_H | 66 | +#define HW_INTC_EXYNOS4210_COMBINER |
52 | + | 67 | + |
53 | +void load_reg_var(DisasContext *s, TCGv_i32 var, int reg); | 68 | +#include "hw/sysbus.h" |
54 | +void arm_gen_condlabel(DisasContext *s); | ||
55 | +bool vfp_access_check(DisasContext *s); | ||
56 | +void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop); | ||
57 | +void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop); | ||
58 | +void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop); | ||
59 | +void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop); | ||
60 | + | 69 | + |
61 | +static inline TCGv_i32 load_cpu_offset(int offset) | 70 | +/* |
62 | +{ | 71 | + * State for each output signal of internal combiner |
63 | + TCGv_i32 tmp = tcg_temp_new_i32(); | 72 | + */ |
64 | + tcg_gen_ld_i32(tmp, cpu_env, offset); | 73 | +typedef struct CombinerGroupState { |
65 | + return tmp; | 74 | + uint8_t src_mask; /* 1 - source enabled, 0 - disabled */ |
66 | +} | 75 | + uint8_t src_pending; /* Pending source interrupts before masking */ |
76 | +} CombinerGroupState; | ||
67 | + | 77 | + |
68 | +#define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name)) | 78 | +#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner" |
79 | +OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210CombinerState, EXYNOS4210_COMBINER) | ||
69 | + | 80 | + |
70 | +static inline void store_cpu_offset(TCGv_i32 var, int offset) | 81 | +/* Number of groups and total number of interrupts for the internal combiner */ |
71 | +{ | 82 | +#define IIC_NGRP 64 |
72 | + tcg_gen_st_i32(var, cpu_env, offset); | 83 | +#define IIC_NIRQ (IIC_NGRP * 8) |
73 | + tcg_temp_free_i32(var); | 84 | +#define IIC_REGSET_SIZE 0x41 |
74 | +} | ||
75 | + | 85 | + |
76 | +#define store_cpu_field(var, name) \ | 86 | +struct Exynos4210CombinerState { |
77 | + store_cpu_offset(var, offsetof(CPUARMState, name)) | 87 | + SysBusDevice parent_obj; |
78 | + | 88 | + |
79 | +/* Create a new temporary and set it to the value of a CPU register. */ | 89 | + MemoryRegion iomem; |
80 | +static inline TCGv_i32 load_reg(DisasContext *s, int reg) | 90 | + |
81 | +{ | 91 | + struct CombinerGroupState group[IIC_NGRP]; |
82 | + TCGv_i32 tmp = tcg_temp_new_i32(); | 92 | + uint32_t reg_set[IIC_REGSET_SIZE]; |
83 | + load_reg_var(s, tmp, reg); | 93 | + uint32_t icipsr[2]; |
84 | + return tmp; | 94 | + uint32_t external; /* 1 means that this combiner is external */ |
85 | +} | 95 | + |
96 | + qemu_irq output_irq[IIC_NGRP]; | ||
97 | +}; | ||
86 | + | 98 | + |
87 | +#endif | 99 | +#endif |
88 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 100 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c |
89 | index XXXXXXX..XXXXXXX 100644 | 101 | index XXXXXXX..XXXXXXX 100644 |
90 | --- a/target/arm/translate.c | 102 | --- a/hw/arm/exynos4210.c |
91 | +++ b/target/arm/translate.c | 103 | +++ b/hw/arm/exynos4210.c |
104 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
105 | } | ||
106 | |||
107 | /* Internal Interrupt Combiner */ | ||
108 | - dev = qdev_new("exynos4210.combiner"); | ||
109 | - busdev = SYS_BUS_DEVICE(dev); | ||
110 | - sysbus_realize_and_unref(busdev, &error_fatal); | ||
111 | + busdev = SYS_BUS_DEVICE(&s->int_combiner); | ||
112 | + sysbus_realize(busdev, &error_fatal); | ||
113 | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { | ||
114 | sysbus_connect_irq(busdev, n, | ||
115 | qdev_get_gpio_in(DEVICE(&s->a9mpcore), n)); | ||
116 | } | ||
117 | - exynos4210_combiner_get_gpioin(&s->irqs, dev, 0); | ||
118 | + exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->int_combiner), 0); | ||
119 | sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); | ||
120 | |||
121 | /* External Interrupt Combiner */ | ||
122 | - dev = qdev_new("exynos4210.combiner"); | ||
123 | - qdev_prop_set_uint32(dev, "external", 1); | ||
124 | - busdev = SYS_BUS_DEVICE(dev); | ||
125 | - sysbus_realize_and_unref(busdev, &error_fatal); | ||
126 | + qdev_prop_set_uint32(DEVICE(&s->ext_combiner), "external", 1); | ||
127 | + busdev = SYS_BUS_DEVICE(&s->ext_combiner); | ||
128 | + sysbus_realize(busdev, &error_fatal); | ||
129 | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { | ||
130 | sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n)); | ||
131 | } | ||
132 | - exynos4210_combiner_get_gpioin(&s->irqs, dev, 1); | ||
133 | + exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->ext_combiner), 1); | ||
134 | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); | ||
135 | |||
136 | /* Initialize board IRQs. */ | ||
137 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj) | ||
138 | |||
139 | object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); | ||
140 | object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC); | ||
141 | + object_initialize_child(obj, "int-combiner", &s->int_combiner, | ||
142 | + TYPE_EXYNOS4210_COMBINER); | ||
143 | + object_initialize_child(obj, "ext-combiner", &s->ext_combiner, | ||
144 | + TYPE_EXYNOS4210_COMBINER); | ||
145 | } | ||
146 | |||
147 | static void exynos4210_class_init(ObjectClass *klass, void *data) | ||
148 | diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c | ||
149 | index XXXXXXX..XXXXXXX 100644 | ||
150 | --- a/hw/intc/exynos4210_combiner.c | ||
151 | +++ b/hw/intc/exynos4210_combiner.c | ||
92 | @@ -XXX,XX +XXX,XX @@ | 152 | @@ -XXX,XX +XXX,XX @@ |
93 | #define ENABLE_ARCH_8 arm_dc_feature(s, ARM_FEATURE_V8) | 153 | #include "hw/sysbus.h" |
94 | 154 | #include "migration/vmstate.h" | |
95 | #include "translate.h" | 155 | #include "qemu/module.h" |
96 | +#include "translate-a32.h" | ||
97 | |||
98 | #if defined(CONFIG_USER_ONLY) | ||
99 | #define IS_USER(s) 1 | ||
100 | @@ -XXX,XX +XXX,XX @@ void arm_translate_init(void) | ||
101 | } | ||
102 | |||
103 | /* Generate a label used for skipping this instruction */ | ||
104 | -static void arm_gen_condlabel(DisasContext *s) | ||
105 | +void arm_gen_condlabel(DisasContext *s) | ||
106 | { | ||
107 | if (!s->condjmp) { | ||
108 | s->condlabel = gen_new_label(); | ||
109 | @@ -XXX,XX +XXX,XX @@ static inline int get_a32_user_mem_index(DisasContext *s) | ||
110 | } | ||
111 | } | ||
112 | |||
113 | -static inline TCGv_i32 load_cpu_offset(int offset) | ||
114 | -{ | ||
115 | - TCGv_i32 tmp = tcg_temp_new_i32(); | ||
116 | - tcg_gen_ld_i32(tmp, cpu_env, offset); | ||
117 | - return tmp; | ||
118 | -} | ||
119 | - | 156 | - |
120 | -#define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name)) | 157 | +#include "hw/intc/exynos4210_combiner.h" |
158 | #include "hw/arm/exynos4210.h" | ||
159 | #include "hw/hw.h" | ||
160 | #include "hw/irq.h" | ||
161 | @@ -XXX,XX +XXX,XX @@ | ||
162 | #define DPRINTF(fmt, ...) do {} while (0) | ||
163 | #endif | ||
164 | |||
165 | -#define IIC_NGRP 64 /* Internal Interrupt Combiner | ||
166 | - Groups number */ | ||
167 | -#define IIC_NIRQ (IIC_NGRP * 8)/* Internal Interrupt Combiner | ||
168 | - Interrupts number */ | ||
169 | #define IIC_REGION_SIZE 0x108 /* Size of memory mapped region */ | ||
170 | -#define IIC_REGSET_SIZE 0x41 | ||
121 | - | 171 | - |
122 | -static inline void store_cpu_offset(TCGv_i32 var, int offset) | 172 | -/* |
123 | -{ | 173 | - * State for each output signal of internal combiner |
124 | - tcg_gen_st_i32(var, cpu_env, offset); | 174 | - */ |
125 | - tcg_temp_free_i32(var); | 175 | -typedef struct CombinerGroupState { |
126 | -} | 176 | - uint8_t src_mask; /* 1 - source enabled, 0 - disabled */ |
177 | - uint8_t src_pending; /* Pending source interrupts before masking */ | ||
178 | -} CombinerGroupState; | ||
127 | - | 179 | - |
128 | -#define store_cpu_field(var, name) \ | 180 | -#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner" |
129 | - store_cpu_offset(var, offsetof(CPUARMState, name)) | 181 | -OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210CombinerState, EXYNOS4210_COMBINER) |
130 | - | 182 | - |
131 | /* The architectural value of PC. */ | 183 | -struct Exynos4210CombinerState { |
132 | static uint32_t read_pc(DisasContext *s) | 184 | - SysBusDevice parent_obj; |
133 | { | ||
134 | @@ -XXX,XX +XXX,XX @@ static uint32_t read_pc(DisasContext *s) | ||
135 | } | ||
136 | |||
137 | /* Set a variable to the value of a CPU register. */ | ||
138 | -static void load_reg_var(DisasContext *s, TCGv_i32 var, int reg) | ||
139 | +void load_reg_var(DisasContext *s, TCGv_i32 var, int reg) | ||
140 | { | ||
141 | if (reg == 15) { | ||
142 | tcg_gen_movi_i32(var, read_pc(s)); | ||
143 | @@ -XXX,XX +XXX,XX @@ static void load_reg_var(DisasContext *s, TCGv_i32 var, int reg) | ||
144 | } | ||
145 | } | ||
146 | |||
147 | -/* Create a new temporary and set it to the value of a CPU register. */ | ||
148 | -static inline TCGv_i32 load_reg(DisasContext *s, int reg) | ||
149 | -{ | ||
150 | - TCGv_i32 tmp = tcg_temp_new_i32(); | ||
151 | - load_reg_var(s, tmp, reg); | ||
152 | - return tmp; | ||
153 | -} | ||
154 | - | 185 | - |
155 | /* | 186 | - MemoryRegion iomem; |
156 | * Create a new temp, REG + OFS, except PC is ALIGN(PC, 4). | 187 | - |
157 | * This is used for load/store for which use of PC implies (literal), | 188 | - struct CombinerGroupState group[IIC_NGRP]; |
158 | @@ -XXX,XX +XXX,XX @@ static inline void vfp_store_reg32(TCGv_i32 var, int reg) | 189 | - uint32_t reg_set[IIC_REGSET_SIZE]; |
159 | tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); | 190 | - uint32_t icipsr[2]; |
160 | } | 191 | - uint32_t external; /* 1 means that this combiner is external */ |
161 | 192 | - | |
162 | -static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop) | 193 | - qemu_irq output_irq[IIC_NGRP]; |
163 | +void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop) | 194 | -}; |
164 | { | 195 | |
165 | long off = neon_element_offset(reg, ele, memop); | 196 | static const VMStateDescription vmstate_exynos4210_combiner_group_state = { |
166 | 197 | .name = "exynos4210.combiner.groupstate", | |
167 | @@ -XXX,XX +XXX,XX @@ static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop) | ||
168 | } | ||
169 | } | ||
170 | |||
171 | -static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop) | ||
172 | +void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop) | ||
173 | { | ||
174 | long off = neon_element_offset(reg, ele, memop); | ||
175 | |||
176 | @@ -XXX,XX +XXX,XX @@ static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop) | ||
177 | } | ||
178 | } | ||
179 | |||
180 | -static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop) | ||
181 | +void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop) | ||
182 | { | ||
183 | long off = neon_element_offset(reg, ele, memop); | ||
184 | |||
185 | @@ -XXX,XX +XXX,XX @@ static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop) | ||
186 | } | ||
187 | } | ||
188 | |||
189 | -static void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop) | ||
190 | +void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop) | ||
191 | { | ||
192 | long off = neon_element_offset(reg, ele, memop); | ||
193 | |||
194 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
195 | index XXXXXXX..XXXXXXX 100644 | ||
196 | --- a/target/arm/translate-vfp.c.inc | ||
197 | +++ b/target/arm/translate-vfp.c.inc | ||
198 | @@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) | ||
199 | * The most usual kind of VFP access check, for everything except | ||
200 | * FMXR/FMRX to the always-available special registers. | ||
201 | */ | ||
202 | -static bool vfp_access_check(DisasContext *s) | ||
203 | +bool vfp_access_check(DisasContext *s) | ||
204 | { | ||
205 | return full_vfp_access_check(s, false); | ||
206 | } | ||
207 | -- | 198 | -- |
208 | 2.20.1 | 199 | 2.25.1 |
209 | |||
210 | diff view generated by jsdifflib |
1 | The function vfp_reg_ptr() is used only in translate-neon.c.inc; | 1 | The only time we use the int_combiner_irq[] and ext_combiner_irq[] |
---|---|---|---|
2 | move it there. | 2 | arrays in the Exynos4210Irq struct is during realize of the SoC -- we |
3 | initialize them with the input IRQs of the combiner devices, and then | ||
4 | connect those to outputs of other devices in | ||
5 | exynos4210_init_board_irqs(). Now that the combiner objects are | ||
6 | easily accessible as s->int_combiner and s->ext_combiner we can make | ||
7 | the connections directly from one device to the other without going | ||
8 | via these arrays. | ||
9 | |||
10 | Since these are the only two remaining elements of Exynos4210Irq, | ||
11 | we can remove that struct entirely. | ||
3 | 12 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20210430132740.10391-10-peter.maydell@linaro.org | 15 | Message-id: 20220404154658.565020-19-peter.maydell@linaro.org |
8 | --- | 16 | --- |
9 | target/arm/translate.c | 7 ------- | 17 | include/hw/arm/exynos4210.h | 6 ------ |
10 | target/arm/translate-neon.c.inc | 7 +++++++ | 18 | hw/arm/exynos4210.c | 34 ++++++++-------------------------- |
11 | 2 files changed, 7 insertions(+), 7 deletions(-) | 19 | 2 files changed, 8 insertions(+), 32 deletions(-) |
12 | 20 | ||
13 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 21 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h |
14 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/translate.c | 23 | --- a/include/hw/arm/exynos4210.h |
16 | +++ b/target/arm/translate.c | 24 | +++ b/include/hw/arm/exynos4210.h |
17 | @@ -XXX,XX +XXX,XX @@ void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop) | 25 | @@ -XXX,XX +XXX,XX @@ |
26 | */ | ||
27 | #define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38) | ||
28 | |||
29 | -typedef struct Exynos4210Irq { | ||
30 | - qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
31 | - qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; | ||
32 | -} Exynos4210Irq; | ||
33 | - | ||
34 | struct Exynos4210State { | ||
35 | /*< private >*/ | ||
36 | SysBusDevice parent_obj; | ||
37 | /*< public >*/ | ||
38 | ARMCPU *cpu[EXYNOS4210_NCPUS]; | ||
39 | - Exynos4210Irq irqs; | ||
40 | qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; | ||
41 | |||
42 | MemoryRegion chipid_mem; | ||
43 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/hw/arm/exynos4210.c | ||
46 | +++ b/hw/arm/exynos4210.c | ||
47 | @@ -XXX,XX +XXX,XX @@ static int mapline_size(const int *mapline) | ||
48 | static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
49 | { | ||
50 | uint32_t grp, bit, irq_id, n; | ||
51 | - Exynos4210Irq *is = &s->irqs; | ||
52 | DeviceState *extgicdev = DEVICE(&s->ext_gic); | ||
53 | + DeviceState *intcdev = DEVICE(&s->int_combiner); | ||
54 | + DeviceState *extcdev = DEVICE(&s->ext_combiner); | ||
55 | int splitcount = 0; | ||
56 | DeviceState *splitter; | ||
57 | const int *mapline; | ||
58 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
59 | splitin = 0; | ||
60 | for (;;) { | ||
61 | s->irq_table[in] = qdev_get_gpio_in(splitter, 0); | ||
62 | - qdev_connect_gpio_out(splitter, splitin, is->int_combiner_irq[in]); | ||
63 | - qdev_connect_gpio_out(splitter, splitin + 1, is->ext_combiner_irq[in]); | ||
64 | + qdev_connect_gpio_out(splitter, splitin, | ||
65 | + qdev_get_gpio_in(intcdev, in)); | ||
66 | + qdev_connect_gpio_out(splitter, splitin + 1, | ||
67 | + qdev_get_gpio_in(extcdev, in)); | ||
68 | splitin += 2; | ||
69 | if (!mapline) { | ||
70 | break; | ||
71 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s) | ||
72 | qdev_realize(splitter, NULL, &error_abort); | ||
73 | splitcount++; | ||
74 | s->irq_table[n] = qdev_get_gpio_in(splitter, 0); | ||
75 | - qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); | ||
76 | + qdev_connect_gpio_out(splitter, 0, qdev_get_gpio_in(intcdev, n)); | ||
77 | qdev_connect_gpio_out(splitter, 1, | ||
78 | qdev_get_gpio_in(extgicdev, irq_id - 32)); | ||
79 | } else { | ||
80 | - s->irq_table[n] = is->int_combiner_irq[n]; | ||
81 | + s->irq_table[n] = qdev_get_gpio_in(intcdev, n); | ||
82 | } | ||
18 | } | 83 | } |
84 | /* | ||
85 | @@ -XXX,XX +XXX,XX @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) | ||
86 | return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); | ||
19 | } | 87 | } |
20 | 88 | ||
21 | -static TCGv_ptr vfp_reg_ptr(bool dp, int reg) | 89 | -/* |
90 | - * Get Combiner input GPIO into irqs structure | ||
91 | - */ | ||
92 | -static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, | ||
93 | - DeviceState *dev, int ext) | ||
22 | -{ | 94 | -{ |
23 | - TCGv_ptr ret = tcg_temp_new_ptr(); | 95 | - int n; |
24 | - tcg_gen_addi_ptr(ret, cpu_env, vfp_reg_offset(dp, reg)); | 96 | - int max; |
25 | - return ret; | 97 | - qemu_irq *irq; |
98 | - | ||
99 | - max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ : | ||
100 | - EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; | ||
101 | - irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq; | ||
102 | - | ||
103 | - for (n = 0; n < max; n++) { | ||
104 | - irq[n] = qdev_get_gpio_in(dev, n); | ||
105 | - } | ||
26 | -} | 106 | -} |
27 | - | 107 | - |
28 | #define ARM_CP_RW_BIT (1 << 20) | 108 | static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, |
29 | 109 | 0x09, 0x00, 0x00, 0x00 }; | |
30 | /* Include the Neon decoder */ | 110 | |
31 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc | 111 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) |
32 | index XXXXXXX..XXXXXXX 100644 | 112 | sysbus_connect_irq(busdev, n, |
33 | --- a/target/arm/translate-neon.c.inc | 113 | qdev_get_gpio_in(DEVICE(&s->a9mpcore), n)); |
34 | +++ b/target/arm/translate-neon.c.inc | 114 | } |
35 | @@ -XXX,XX +XXX,XX @@ static inline int neon_3same_fp_size(DisasContext *s, int x) | 115 | - exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->int_combiner), 0); |
36 | #include "decode-neon-ls.c.inc" | 116 | sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); |
37 | #include "decode-neon-shared.c.inc" | 117 | |
38 | 118 | /* External Interrupt Combiner */ | |
39 | +static TCGv_ptr vfp_reg_ptr(bool dp, int reg) | 119 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) |
40 | +{ | 120 | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { |
41 | + TCGv_ptr ret = tcg_temp_new_ptr(); | 121 | sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n)); |
42 | + tcg_gen_addi_ptr(ret, cpu_env, vfp_reg_offset(dp, reg)); | 122 | } |
43 | + return ret; | 123 | - exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->ext_combiner), 1); |
44 | +} | 124 | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); |
45 | + | 125 | |
46 | static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop) | 126 | /* Initialize board IRQs. */ |
47 | { | ||
48 | long offset = neon_element_offset(reg, ele, mop & MO_SIZE); | ||
49 | -- | 127 | -- |
50 | 2.20.1 | 128 | 2.25.1 |
51 | |||
52 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Zongyuan Li <zongyuan.li@smartx.com> |
---|---|---|---|
2 | 2 | ||
3 | These three features are already enabled by TCG, but are missing | 3 | Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com> |
4 | their hwcap bits. Update HWCAP2 from linux v5.12. | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
5 | 5 | Message-id: 20220324181557.203805-2-zongyuan.li@smartx.com | |
6 | Cc: qemu-stable@nongnu.org (for 6.0.1) | ||
7 | Buglink: https://bugs.launchpad.net/bugs/1926044 | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20210427214108.88503-1-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 7 | --- |
12 | linux-user/elfload.c | 13 +++++++++++++ | 8 | hw/arm/realview.c | 33 ++++++++++++++++++++++++--------- |
13 | 1 file changed, 13 insertions(+) | 9 | 1 file changed, 24 insertions(+), 9 deletions(-) |
14 | 10 | ||
15 | diff --git a/linux-user/elfload.c b/linux-user/elfload.c | 11 | diff --git a/hw/arm/realview.c b/hw/arm/realview.c |
16 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/linux-user/elfload.c | 13 | --- a/hw/arm/realview.c |
18 | +++ b/linux-user/elfload.c | 14 | +++ b/hw/arm/realview.c |
19 | @@ -XXX,XX +XXX,XX @@ enum { | 15 | @@ -XXX,XX +XXX,XX @@ |
20 | ARM_HWCAP2_A64_SVESM4 = 1 << 6, | 16 | #include "hw/sysbus.h" |
21 | ARM_HWCAP2_A64_FLAGM2 = 1 << 7, | 17 | #include "hw/arm/boot.h" |
22 | ARM_HWCAP2_A64_FRINT = 1 << 8, | 18 | #include "hw/arm/primecell.h" |
23 | + ARM_HWCAP2_A64_SVEI8MM = 1 << 9, | 19 | +#include "hw/core/split-irq.h" |
24 | + ARM_HWCAP2_A64_SVEF32MM = 1 << 10, | 20 | #include "hw/net/lan9118.h" |
25 | + ARM_HWCAP2_A64_SVEF64MM = 1 << 11, | 21 | #include "hw/net/smc91c111.h" |
26 | + ARM_HWCAP2_A64_SVEBF16 = 1 << 12, | 22 | #include "hw/pci/pci.h" |
27 | + ARM_HWCAP2_A64_I8MM = 1 << 13, | 23 | +#include "hw/qdev-core.h" |
28 | + ARM_HWCAP2_A64_BF16 = 1 << 14, | 24 | #include "net/net.h" |
29 | + ARM_HWCAP2_A64_DGH = 1 << 15, | 25 | #include "sysemu/sysemu.h" |
30 | + ARM_HWCAP2_A64_RNG = 1 << 16, | 26 | #include "hw/boards.h" |
31 | + ARM_HWCAP2_A64_BTI = 1 << 17, | 27 | @@ -XXX,XX +XXX,XX @@ static const int realview_board_id[] = { |
32 | + ARM_HWCAP2_A64_MTE = 1 << 18, | 28 | 0x76d |
33 | }; | 29 | }; |
34 | 30 | ||
35 | #define ELF_HWCAP get_elf_hwcap() | 31 | +static void split_irq_from_named(DeviceState *src, const char* outname, |
36 | @@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap2(void) | 32 | + qemu_irq out1, qemu_irq out2) { |
37 | GET_FEATURE_ID(aa64_dcpodp, ARM_HWCAP2_A64_DCPODP); | 33 | + DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ); |
38 | GET_FEATURE_ID(aa64_condm_5, ARM_HWCAP2_A64_FLAGM2); | 34 | + |
39 | GET_FEATURE_ID(aa64_frint, ARM_HWCAP2_A64_FRINT); | 35 | + qdev_prop_set_uint32(splitter, "num-lines", 2); |
40 | + GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG); | 36 | + |
41 | + GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI); | 37 | + qdev_realize_and_unref(splitter, NULL, &error_fatal); |
42 | + GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE); | 38 | + |
43 | 39 | + qdev_connect_gpio_out(splitter, 0, out1); | |
44 | return hwcaps; | 40 | + qdev_connect_gpio_out(splitter, 1, out2); |
45 | } | 41 | + qdev_connect_gpio_out_named(src, outname, 0, |
42 | + qdev_get_gpio_in(splitter, 0)); | ||
43 | +} | ||
44 | + | ||
45 | static void realview_init(MachineState *machine, | ||
46 | enum realview_board_type board_type) | ||
47 | { | ||
48 | @@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine, | ||
49 | DeviceState *dev, *sysctl, *gpio2, *pl041; | ||
50 | SysBusDevice *busdev; | ||
51 | qemu_irq pic[64]; | ||
52 | - qemu_irq mmc_irq[2]; | ||
53 | PCIBus *pci_bus = NULL; | ||
54 | NICInfo *nd; | ||
55 | DriveInfo *dinfo; | ||
56 | @@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine, | ||
57 | * and the PL061 has them the other way about. Also the card | ||
58 | * detect line is inverted. | ||
59 | */ | ||
60 | - mmc_irq[0] = qemu_irq_split( | ||
61 | - qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), | ||
62 | - qdev_get_gpio_in(gpio2, 1)); | ||
63 | - mmc_irq[1] = qemu_irq_split( | ||
64 | - qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), | ||
65 | - qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); | ||
66 | - qdev_connect_gpio_out_named(dev, "card-read-only", 0, mmc_irq[0]); | ||
67 | - qdev_connect_gpio_out_named(dev, "card-inserted", 0, mmc_irq[1]); | ||
68 | + split_irq_from_named(dev, "card-read-only", | ||
69 | + qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), | ||
70 | + qdev_get_gpio_in(gpio2, 1)); | ||
71 | + | ||
72 | + split_irq_from_named(dev, "card-inserted", | ||
73 | + qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), | ||
74 | + qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); | ||
75 | + | ||
76 | dinfo = drive_get(IF_SD, 0, 0); | ||
77 | if (dinfo) { | ||
78 | DeviceState *card; | ||
46 | -- | 79 | -- |
47 | 2.20.1 | 80 | 2.25.1 |
48 | |||
49 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Zongyuan Li <zongyuan.li@smartx.com> | ||
1 | 2 | ||
3 | Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220324181557.203805-3-zongyuan.li@smartx.com | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | hw/arm/stellaris.c | 15 +++++++++++++-- | ||
9 | 1 file changed, 13 insertions(+), 2 deletions(-) | ||
10 | |||
11 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/hw/arm/stellaris.c | ||
14 | +++ b/hw/arm/stellaris.c | ||
15 | @@ -XXX,XX +XXX,XX @@ | ||
16 | |||
17 | #include "qemu/osdep.h" | ||
18 | #include "qapi/error.h" | ||
19 | +#include "hw/core/split-irq.h" | ||
20 | #include "hw/sysbus.h" | ||
21 | #include "hw/sd/sd.h" | ||
22 | #include "hw/ssi/ssi.h" | ||
23 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) | ||
24 | DeviceState *ssddev; | ||
25 | DriveInfo *dinfo; | ||
26 | DeviceState *carddev; | ||
27 | + DeviceState *gpio_d_splitter; | ||
28 | BlockBackend *blk; | ||
29 | |||
30 | /* | ||
31 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) | ||
32 | &error_fatal); | ||
33 | |||
34 | ssddev = ssi_create_peripheral(bus, "ssd0323"); | ||
35 | - gpio_out[GPIO_D][0] = qemu_irq_split( | ||
36 | - qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0), | ||
37 | + | ||
38 | + gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ); | ||
39 | + qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2); | ||
40 | + qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal); | ||
41 | + qdev_connect_gpio_out( | ||
42 | + gpio_d_splitter, 0, | ||
43 | + qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0)); | ||
44 | + qdev_connect_gpio_out( | ||
45 | + gpio_d_splitter, 1, | ||
46 | qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); | ||
47 | + gpio_out[GPIO_D][0] = qdev_get_gpio_in(gpio_d_splitter, 0); | ||
48 | + | ||
49 | gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); | ||
50 | |||
51 | /* Make sure the select pin is high. */ | ||
52 | -- | ||
53 | 2.25.1 | diff view generated by jsdifflib |
1 | The functions vfp_load_reg32(), vfp_load_reg64(), vfp_store_reg32() | 1 | From: Zongyuan Li <zongyuan.li@smartx.com> |
---|---|---|---|
2 | and vfp_store_reg64() are used only in translate-vfp.c.inc. Move | ||
3 | them to that file. | ||
4 | 2 | ||
3 | Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Message-id: 20220324181557.203805-5-zongyuan.li@smartx.com | ||
6 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/811 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20210430132740.10391-7-peter.maydell@linaro.org | ||
9 | --- | 8 | --- |
10 | target/arm/translate.c | 20 -------------------- | 9 | include/hw/irq.h | 5 ----- |
11 | target/arm/translate-vfp.c.inc | 20 ++++++++++++++++++++ | 10 | hw/core/irq.c | 15 --------------- |
12 | 2 files changed, 20 insertions(+), 20 deletions(-) | 11 | 2 files changed, 20 deletions(-) |
13 | 12 | ||
14 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 13 | diff --git a/include/hw/irq.h b/include/hw/irq.h |
15 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/translate.c | 15 | --- a/include/hw/irq.h |
17 | +++ b/target/arm/translate.c | 16 | +++ b/include/hw/irq.h |
18 | @@ -XXX,XX +XXX,XX @@ static long vfp_reg_offset(bool dp, unsigned reg) | 17 | @@ -XXX,XX +XXX,XX @@ void qemu_free_irq(qemu_irq irq); |
19 | } | 18 | /* Returns a new IRQ with opposite polarity. */ |
19 | qemu_irq qemu_irq_invert(qemu_irq irq); | ||
20 | |||
21 | -/* Returns a new IRQ which feeds into both the passed IRQs. | ||
22 | - * It's probably better to use the TYPE_SPLIT_IRQ device instead. | ||
23 | - */ | ||
24 | -qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2); | ||
25 | - | ||
26 | /* For internal use in qtest. Similar to qemu_irq_split, but operating | ||
27 | on an existing vector of qemu_irq. */ | ||
28 | void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n); | ||
29 | diff --git a/hw/core/irq.c b/hw/core/irq.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/hw/core/irq.c | ||
32 | +++ b/hw/core/irq.c | ||
33 | @@ -XXX,XX +XXX,XX @@ qemu_irq qemu_irq_invert(qemu_irq irq) | ||
34 | return qemu_allocate_irq(qemu_notirq, irq, 0); | ||
20 | } | 35 | } |
21 | 36 | ||
22 | -static inline void vfp_load_reg64(TCGv_i64 var, int reg) | 37 | -static void qemu_splitirq(void *opaque, int line, int level) |
23 | -{ | 38 | -{ |
24 | - tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg)); | 39 | - struct IRQState **irq = opaque; |
40 | - irq[0]->handler(irq[0]->opaque, irq[0]->n, level); | ||
41 | - irq[1]->handler(irq[1]->opaque, irq[1]->n, level); | ||
25 | -} | 42 | -} |
26 | - | 43 | - |
27 | -static inline void vfp_store_reg64(TCGv_i64 var, int reg) | 44 | -qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2) |
28 | -{ | 45 | -{ |
29 | - tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg)); | 46 | - qemu_irq *s = g_new0(qemu_irq, 2); |
47 | - s[0] = irq1; | ||
48 | - s[1] = irq2; | ||
49 | - return qemu_allocate_irq(qemu_splitirq, s, 0); | ||
30 | -} | 50 | -} |
31 | - | 51 | - |
32 | -static inline void vfp_load_reg32(TCGv_i32 var, int reg) | 52 | void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n) |
33 | -{ | ||
34 | - tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg)); | ||
35 | -} | ||
36 | - | ||
37 | -static inline void vfp_store_reg32(TCGv_i32 var, int reg) | ||
38 | -{ | ||
39 | - tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); | ||
40 | -} | ||
41 | - | ||
42 | void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop) | ||
43 | { | 53 | { |
44 | long off = neon_element_offset(reg, ele, memop); | 54 | int i; |
45 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
46 | index XXXXXXX..XXXXXXX 100644 | ||
47 | --- a/target/arm/translate-vfp.c.inc | ||
48 | +++ b/target/arm/translate-vfp.c.inc | ||
49 | @@ -XXX,XX +XXX,XX @@ | ||
50 | #include "decode-vfp.c.inc" | ||
51 | #include "decode-vfp-uncond.c.inc" | ||
52 | |||
53 | +static inline void vfp_load_reg64(TCGv_i64 var, int reg) | ||
54 | +{ | ||
55 | + tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg)); | ||
56 | +} | ||
57 | + | ||
58 | +static inline void vfp_store_reg64(TCGv_i64 var, int reg) | ||
59 | +{ | ||
60 | + tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg)); | ||
61 | +} | ||
62 | + | ||
63 | +static inline void vfp_load_reg32(TCGv_i32 var, int reg) | ||
64 | +{ | ||
65 | + tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg)); | ||
66 | +} | ||
67 | + | ||
68 | +static inline void vfp_store_reg32(TCGv_i32 var, int reg) | ||
69 | +{ | ||
70 | + tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); | ||
71 | +} | ||
72 | + | ||
73 | /* | ||
74 | * The imm8 encodes the sign bit, enough bits to represent an exponent in | ||
75 | * the range 01....1xx to 10....0xx, and the most significant 4 bits of | ||
76 | -- | 55 | -- |
77 | 2.20.1 | 56 | 2.25.1 |
78 | |||
79 | diff view generated by jsdifflib |
1 | From: Guenter Roeck <linux@roeck-us.net> | 1 | From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> |
---|---|---|---|
2 | 2 | ||
3 | Commit dfc388797cc4 ("hw/arm: xlnx: Set all boards' GEM 'phy-addr' | 3 | Describe that the gic-version influences the maximum number of CPUs. |
4 | property value to 23") configured the PHY address for xilinx-zynq-a9 | ||
5 | to 23. When trying to boot xilinx-zynq-a9 with zynq-zc702.dtb or | ||
6 | zynq-zc706.dtb, this results in the following error message when | ||
7 | trying to use the Ethernet interface. | ||
8 | 4 | ||
9 | macb e000b000.ethernet eth0: Could not attach PHY (-19) | 5 | Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> |
10 | 6 | Message-id: 20220413231456.35811-1-heinrich.schuchardt@canonical.com | |
11 | The devicetree files for ZC702 and ZC706 configure PHY address 7. The | 7 | [PMM: minor punctuation tweaks] |
12 | documentation for the ZC702 and ZC706 evaluation boards suggest that the | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
13 | PHY address is 7, not 23. Other boards use PHY address 0, 1, 3, or 7. | ||
14 | I was unable to find a documentation or a devicetree file suggesting | ||
15 | or using PHY address 23. The Ethernet interface starts working with | ||
16 | zynq-zc702.dtb and zynq-zc706.dtb when setting the PHY address to 7, | ||
17 | so let's use it. | ||
18 | |||
19 | Cc: Bin Meng <bin.meng@windriver.com> | ||
20 | Signed-off-by: Guenter Roeck <linux@roeck-us.net> | ||
21 | Reviewed-by: Bin Meng <bmeng.cn@gmail.com> | ||
22 | Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
23 | Message-id: 20210504124140.1100346-1-linux@roeck-us.net | ||
24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
25 | --- | 10 | --- |
26 | hw/arm/xilinx_zynq.c | 2 +- | 11 | docs/system/arm/virt.rst | 4 ++-- |
27 | 1 file changed, 1 insertion(+), 1 deletion(-) | 12 | 1 file changed, 2 insertions(+), 2 deletions(-) |
28 | 13 | ||
29 | diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c | 14 | diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst |
30 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
31 | --- a/hw/arm/xilinx_zynq.c | 16 | --- a/docs/system/arm/virt.rst |
32 | +++ b/hw/arm/xilinx_zynq.c | 17 | +++ b/docs/system/arm/virt.rst |
33 | @@ -XXX,XX +XXX,XX @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) | 18 | @@ -XXX,XX +XXX,XX @@ gic-version |
34 | qemu_check_nic_model(nd, TYPE_CADENCE_GEM); | 19 | Valid values are: |
35 | qdev_set_nic_properties(dev, nd); | 20 | |
36 | } | 21 | ``2`` |
37 | - object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort); | 22 | - GICv2 |
38 | + object_property_set_int(OBJECT(dev), "phy-addr", 7, &error_abort); | 23 | + GICv2. Note that this limits the number of CPUs to 8. |
39 | s = SYS_BUS_DEVICE(dev); | 24 | ``3`` |
40 | sysbus_realize_and_unref(s, &error_fatal); | 25 | - GICv3 |
41 | sysbus_mmio_map(s, 0, base); | 26 | + GICv3. This allows up to 512 CPUs. |
27 | ``host`` | ||
28 | Use the same GIC version the host provides, when using KVM | ||
29 | ``max`` | ||
42 | -- | 30 | -- |
43 | 2.20.1 | 31 | 2.25.1 |
44 | |||
45 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Hao Wu <wuhaotsh@google.com> |
---|---|---|---|
2 | 2 | ||
3 | The i.MX25 PDK board has 2 banks for SDRAM, each can | 3 | Similar to the Aspeed code in include/misc/aspeed_scu.h, we define |
4 | address up to 256 MiB. So the total RAM usable for this | 4 | the PWRON STRAP fields in their corresponding module for NPCM7XX. |
5 | board is 512M. When we ask for more we get a misleading | ||
6 | error message: | ||
7 | 5 | ||
8 | $ qemu-system-arm -M imx25-pdk -m 513M | 6 | Signed-off-by: Hao Wu <wuhaotsh@google.com> |
9 | qemu-system-arm: Invalid RAM size, should be 128 MiB | 7 | Reviewed-by: Patrick Venture <venture@google.com> |
10 | 8 | Message-id: 20220411165842.3912945-2-wuhaotsh@google.com | |
11 | Update the error message to better match the reality: | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
12 | |||
13 | $ qemu-system-arm -M imx25-pdk -m 513M | ||
14 | qemu-system-arm: RAM size more than 512 MiB is not supported | ||
15 | |||
16 | Fixes: bf350daae02 ("arm/imx25_pdk: drop RAM size fixup") | ||
17 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
19 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | ||
20 | Message-id: 20210407225608.1882855-1-f4bug@amsat.org | ||
21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
22 | --- | 11 | --- |
23 | hw/arm/imx25_pdk.c | 5 ++--- | 12 | include/hw/misc/npcm7xx_gcr.h | 30 ++++++++++++++++++++++++++++++ |
24 | 1 file changed, 2 insertions(+), 3 deletions(-) | 13 | 1 file changed, 30 insertions(+) |
25 | 14 | ||
26 | diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c | 15 | diff --git a/include/hw/misc/npcm7xx_gcr.h b/include/hw/misc/npcm7xx_gcr.h |
27 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
28 | --- a/hw/arm/imx25_pdk.c | 17 | --- a/include/hw/misc/npcm7xx_gcr.h |
29 | +++ b/hw/arm/imx25_pdk.c | 18 | +++ b/include/hw/misc/npcm7xx_gcr.h |
30 | @@ -XXX,XX +XXX,XX @@ static struct arm_boot_info imx25_pdk_binfo; | 19 | @@ -XXX,XX +XXX,XX @@ |
31 | 20 | #include "exec/memory.h" | |
32 | static void imx25_pdk_init(MachineState *machine) | 21 | #include "hw/sysbus.h" |
33 | { | 22 | |
34 | - MachineClass *mc = MACHINE_GET_CLASS(machine); | 23 | +/* |
35 | IMX25PDK *s = g_new0(IMX25PDK, 1); | 24 | + * NPCM7XX PWRON STRAP bit fields |
36 | unsigned int ram_size; | 25 | + * 12: SPI0 powered by VSBV3 at 1.8V |
37 | unsigned int alias_offset; | 26 | + * 11: System flash attached to BMC |
38 | @@ -XXX,XX +XXX,XX @@ static void imx25_pdk_init(MachineState *machine) | 27 | + * 10: BSP alternative pins. |
39 | 28 | + * 9:8: Flash UART command route enabled. | |
40 | /* We need to initialize our memory */ | 29 | + * 7: Security enabled. |
41 | if (machine->ram_size > (FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE)) { | 30 | + * 6: HI-Z state control. |
42 | - char *sz = size_to_str(mc->default_ram_size); | 31 | + * 5: ECC disabled. |
43 | - error_report("Invalid RAM size, should be %s", sz); | 32 | + * 4: Reserved |
44 | + char *sz = size_to_str(FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE); | 33 | + * 3: JTAG2 enabled. |
45 | + error_report("RAM size more than %s is not supported", sz); | 34 | + * 2:0: CPU and DRAM clock frequency. |
46 | g_free(sz); | 35 | + */ |
47 | exit(EXIT_FAILURE); | 36 | +#define NPCM7XX_PWRON_STRAP_SPI0F18 BIT(12) |
48 | } | 37 | +#define NPCM7XX_PWRON_STRAP_SFAB BIT(11) |
38 | +#define NPCM7XX_PWRON_STRAP_BSPA BIT(10) | ||
39 | +#define NPCM7XX_PWRON_STRAP_FUP(x) ((x) << 8) | ||
40 | +#define FUP_NORM_UART2 3 | ||
41 | +#define FUP_PROG_UART3 2 | ||
42 | +#define FUP_PROG_UART2 1 | ||
43 | +#define FUP_NORM_UART3 0 | ||
44 | +#define NPCM7XX_PWRON_STRAP_SECEN BIT(7) | ||
45 | +#define NPCM7XX_PWRON_STRAP_HIZ BIT(6) | ||
46 | +#define NPCM7XX_PWRON_STRAP_ECC BIT(5) | ||
47 | +#define NPCM7XX_PWRON_STRAP_RESERVE1 BIT(4) | ||
48 | +#define NPCM7XX_PWRON_STRAP_J2EN BIT(3) | ||
49 | +#define NPCM7XX_PWRON_STRAP_CKFRQ(x) (x) | ||
50 | +#define CKFRQ_SKIPINIT 0x000 | ||
51 | +#define CKFRQ_DEFAULT 0x111 | ||
52 | + | ||
53 | /* | ||
54 | * Number of registers in our device state structure. Don't change this without | ||
55 | * incrementing the version_id in the vmstate. | ||
49 | -- | 56 | -- |
50 | 2.20.1 | 57 | 2.25.1 |
51 | |||
52 | diff view generated by jsdifflib |
1 | From: Alex Bennée <alex.bennee@linaro.org> | 1 | From: Hao Wu <wuhaotsh@google.com> |
---|---|---|---|
2 | 2 | ||
3 | A trailing _ makes all the difference to the rendered link. | 3 | This patch uses the defined fields to describe PWRON STRAPs for |
4 | better readability. | ||
4 | 5 | ||
5 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | 6 | Signed-off-by: Hao Wu <wuhaotsh@google.com> |
6 | Message-id: 20210428131316.31390-1-alex.bennee@linaro.org | 7 | Reviewed-by: Patrick Venture <venture@google.com> |
8 | Message-id: 20220411165842.3912945-3-wuhaotsh@google.com | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 11 | --- |
10 | docs/system/arm/sbsa.rst | 2 +- | 12 | hw/arm/npcm7xx_boards.c | 24 +++++++++++++++++++----- |
11 | 1 file changed, 1 insertion(+), 1 deletion(-) | 13 | 1 file changed, 19 insertions(+), 5 deletions(-) |
12 | 14 | ||
13 | diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst | 15 | diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c |
14 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/docs/system/arm/sbsa.rst | 17 | --- a/hw/arm/npcm7xx_boards.c |
16 | +++ b/docs/system/arm/sbsa.rst | 18 | +++ b/hw/arm/npcm7xx_boards.c |
17 | @@ -XXX,XX +XXX,XX @@ Arm Server Base System Architecture Reference board (``sbsa-ref``) | 19 | @@ -XXX,XX +XXX,XX @@ |
18 | While the `virt` board is a generic board platform that doesn't match | 20 | #include "sysemu/sysemu.h" |
19 | any real hardware the `sbsa-ref` board intends to look like real | 21 | #include "sysemu/block-backend.h" |
20 | hardware. The `Server Base System Architecture | 22 | |
21 | -<https://developer.arm.com/documentation/den0029/latest>` defines a | 23 | -#define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7 |
22 | +<https://developer.arm.com/documentation/den0029/latest>`_ defines a | 24 | -#define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff |
23 | minimum base line of hardware support and importantly how the firmware | 25 | -#define QUANTA_GBS_POWER_ON_STRAPS 0x000017ff |
24 | reports that to any operating system. It is a static system that | 26 | -#define KUDO_BMC_POWER_ON_STRAPS 0x00001fff |
25 | reports a very minimal DT to the firmware for non-discoverable | 27 | -#define MORI_BMC_POWER_ON_STRAPS 0x00001fff |
28 | +#define NPCM7XX_POWER_ON_STRAPS_DEFAULT ( \ | ||
29 | + NPCM7XX_PWRON_STRAP_SPI0F18 | \ | ||
30 | + NPCM7XX_PWRON_STRAP_SFAB | \ | ||
31 | + NPCM7XX_PWRON_STRAP_BSPA | \ | ||
32 | + NPCM7XX_PWRON_STRAP_FUP(FUP_NORM_UART2) | \ | ||
33 | + NPCM7XX_PWRON_STRAP_SECEN | \ | ||
34 | + NPCM7XX_PWRON_STRAP_HIZ | \ | ||
35 | + NPCM7XX_PWRON_STRAP_ECC | \ | ||
36 | + NPCM7XX_PWRON_STRAP_RESERVE1 | \ | ||
37 | + NPCM7XX_PWRON_STRAP_J2EN | \ | ||
38 | + NPCM7XX_PWRON_STRAP_CKFRQ(CKFRQ_DEFAULT)) | ||
39 | + | ||
40 | +#define NPCM750_EVB_POWER_ON_STRAPS ( \ | ||
41 | + NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_J2EN) | ||
42 | +#define QUANTA_GSJ_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT | ||
43 | +#define QUANTA_GBS_POWER_ON_STRAPS ( \ | ||
44 | + NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_SFAB) | ||
45 | +#define KUDO_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT | ||
46 | +#define MORI_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT | ||
47 | |||
48 | static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin"; | ||
49 | |||
26 | -- | 50 | -- |
27 | 2.20.1 | 51 | 2.25.1 |
28 | |||
29 | diff view generated by jsdifflib |