aarch64: add support for FEAT_TLBIRANGE and FEAT_TLBIOS

[PATCH v8 0/4] aarch64: add support for FEAT_TLBIRANGE and FEAT_TLBIOS

Rebecca Cran posted 4 patches 2 years, 11 months ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20210505030443.25310-1-rebecca@nuviainc.com

Maintainers: Peter Maydell <peter.maydell@linaro.org>, Paolo Bonzini <pbonzini@redhat.com>, Richard Henderson <richard.henderson@linaro.org>

accel/tcg/cputlb.c      | 128 ++++++-
include/exec/exec-all.h |  46 +++
target/arm/cpu.h        |  10 +
target/arm/cpu64.c      |   1 +
target/arm/helper.c     | 371 ++++++++++++++++++++
5 files changed, 553 insertions(+), 3 deletions(-)

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[PATCH v8 0/4] aarch64: add support for FEAT_TLBIRANGE and FEAT_TLBIOS

Posted by Rebecca Cran 2 years, 11 months ago

Improved readability and fixed a bug in
tlb_flush_page_range_bits_by_mmuidx_async_0.

Rebecca Cran (4):
  accel/tcg: Add TLB invalidation support for ranges of addresses
  target/arm: Add support for FEAT_TLBIRANGE
  target/arm: Add support for FEAT_TLBIOS
  target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type

 accel/tcg/cputlb.c      | 128 ++++++-
 include/exec/exec-all.h |  46 +++
 target/arm/cpu.h        |  10 +
 target/arm/cpu64.c      |   1 +
 target/arm/helper.c     | 371 ++++++++++++++++++++
 5 files changed, 553 insertions(+), 3 deletions(-)

-- 
2.26.2