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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id a63sm12270550qkf.132.2021.05.04.20.05.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 May 2021 20:05:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=btMaGj7ccU0HCYX4NRJ6hUY5JOpjFZjbz479ppWGpb4=; b=COjG2xbTiCbqE5q9t8lNX6MiFZgcmFD/CdZcNJDrCeJdMXfKMnrt6pnJpuzBpL1+OR 158crcgWsWR8MK5DslG55/Gv9+vYyOjL3JL1YMHU4l3ShYAnYVDiUHedYsUG6Xr3uEgy zcLGZ2vL3SILl+tHSz5npM2P2x+tZqOnaECCNlKZRAo193K5RyupZGeixbOg5JzhoyGP xWpYO2LMK/Wt2OKrzPlsgq+7m2ns6uLfEId/UWrRqUxUtJfkkEK5mkZO07K/WRxl/jsV hxCcCvdOMayZzk0PKjDxG6jWwJKzp7fFhRsV4wfrAjYTdbek+2C9e8gHr8+ujwjarGlL gv9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=btMaGj7ccU0HCYX4NRJ6hUY5JOpjFZjbz479ppWGpb4=; b=Rx3++u4sD+CRLxmK5AtKw4dTU8tZgpUV//r0Ygkxumd9jPHDKcfJenR0+OwDqDgqTT RLjVEGxtFR48xIdWDSNbh+qlgZQuacOpGPzWHUGQKP44XKYGlQ5Irl9J10AWKHiEQWSn Y2QVRkEbe/iJB+cWg58vJmfD++FUsgA/s8cCbsJfc9l00lLwaNOHEgYBhL+gGEEwuIcF jMJDowA3MaZOxRT67hIKLtO70BBVH7+IhVFJMPUyUadPms7c1nxWRpyeU5PTFHmnPN90 jthLzwLFkbTHI9p0U0ElES2k+m0tzKAXxlXXruYq88Z8H2xLB5L9ctbIUT1DnT3IhkgM lPpw== X-Gm-Message-State: AOAM531am0+fTfI3Nu5IVPIQwAq4QzqrRhigphyOkDLDHSmbYIdE8q3O 35MX520QTFAIFVXQfszsacNnLg== X-Google-Smtp-Source: ABdhPJwGiH5AYwN+lHKJsKswAyj/5XGLetW1t/AOBK21a72zM9WKRY1FSQQyXXaeCqaGRugYFLjJtg== X-Received: by 2002:a05:620a:4a:: with SMTP id t10mr28484318qkt.249.1620183904647; Tue, 04 May 2021 20:05:04 -0700 (PDT) From: Rebecca Cran To: Richard Henderson , Peter Maydell Subject: [PATCH v8 1/4] accel/tcg: Add TLB invalidation support for ranges of addresses Date: Tue, 4 May 2021 21:04:40 -0600 Message-Id: <20210505030443.25310-2-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210505030443.25310-1-rebecca@nuviainc.com> References: <20210505030443.25310-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72b; envelope-from=rebecca@nuviainc.com; helo=mail-qk1-x72b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , qemu-devel@nongnu.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @nuviainc-com.20150623.gappssmtp.com) Content-Type: text/plain; charset="utf-8" Add functions to support the FEAT_TLBIRANGE ARMv8.4 feature that adds TLB invalidation instructions to invalidate ranges of addresses. Signed-off-by: Rebecca Cran --- accel/tcg/cputlb.c | 128 +++++++++++++++++++- include/exec/exec-all.h | 46 +++++++ 2 files changed, 171 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 8a7b779270a4..9381745f2528 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -709,7 +709,7 @@ void tlb_flush_page_all_cpus_synced(CPUState *src, targ= et_ulong addr) tlb_flush_page_by_mmuidx_all_cpus_synced(src, addr, ALL_MMUIDX_BITS); } =20 -static void tlb_flush_page_bits_locked(CPUArchState *env, int midx, +static bool tlb_flush_page_bits_locked(CPUArchState *env, int midx, target_ulong page, unsigned bits) { CPUTLBDesc *d =3D &env_tlb(env)->d[midx]; @@ -729,7 +729,7 @@ static void tlb_flush_page_bits_locked(CPUArchState *en= v, int midx, TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", midx, page, mask); tlb_flush_one_mmuidx_locked(env, midx, get_clock_realtime()); - return; + return true; } =20 /* Check if we need to flush due to large pages. */ @@ -738,13 +738,14 @@ static void tlb_flush_page_bits_locked(CPUArchState *= env, int midx, TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", midx, d->large_page_addr, d->large_page_mask); tlb_flush_one_mmuidx_locked(env, midx, get_clock_realtime()); - return; + return true; } =20 if (tlb_flush_entry_mask_locked(tlb_entry(env, midx, page), page, mask= )) { tlb_n_used_entries_dec(env, midx); } tlb_flush_vtlb_page_mask_locked(env, midx, page, mask); + return false; } =20 typedef struct { @@ -943,6 +944,127 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CP= UState *src_cpu, } } =20 +typedef struct { + target_ulong addr; + target_ulong length; + uint16_t idxmap; + uint16_t bits; +} TLBFlushPageRangeBitsByMMUIdxData; + +static void +tlb_flush_page_range_bits_by_mmuidx_async_0(CPUState *cpu, + target_ulong addr, + target_ulong length, + uint16_t idxmap, + unsigned bits) +{ + CPUArchState *env =3D cpu->env_ptr; + bool full_flush; + int mmu_idx; + target_ulong page; + + assert_cpu_is_self(cpu); + + tlb_debug("page addr:" TARGET_FMT_lx "/%u len: " TARGET_FMT_lx + " mmu_map:0x%x\n", + addr, bits, length, idxmap); + + qemu_spin_lock(&env_tlb(env)->c.lock); + for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { + if ((idxmap >> mmu_idx) & 1) { + for (page =3D addr; page < (addr + length); page +=3D TARGET_P= AGE_SIZE) { + full_flush =3D tlb_flush_page_bits_locked(env, mmu_idx, + page, bits); + if (full_flush) { + break; + } + } + } + } + qemu_spin_unlock(&env_tlb(env)->c.lock); + + for (page =3D addr; page < (addr + length); page +=3D TARGET_PAGE_SIZE= ) { + tb_flush_jmp_cache(cpu, page); + } +} + +static void +tlb_flush_page_range_bits_by_mmuidx_async_1(CPUState *cpu, + run_on_cpu_data data) +{ + TLBFlushPageRangeBitsByMMUIdxData *d =3D data.host_ptr; + + tlb_flush_page_range_bits_by_mmuidx_async_0(cpu, d->addr, d->length, + d->idxmap, d->bits); + + g_free(d); +} + +void tlb_flush_page_range_bits_by_mmuidx(CPUState *cpu, + target_ulong addr, + target_ulong length, + uint16_t idxmap, + unsigned bits) +{ + TLBFlushPageRangeBitsByMMUIdxData d; + TLBFlushPageRangeBitsByMMUIdxData *p; + + /* This should already be page aligned */ + addr &=3D TARGET_PAGE_BITS; + + d.addr =3D addr & TARGET_PAGE_MASK; + d.idxmap =3D idxmap; + d.bits =3D bits; + d.length =3D length; + + if (qemu_cpu_is_self(cpu)) { + tlb_flush_page_range_bits_by_mmuidx_async_0(cpu, addr, length, + idxmap, bits); + } else { + p =3D g_new(TLBFlushPageRangeBitsByMMUIdxData, 1); + + /* Allocate a structure, freed by the worker. */ + *p =3D d; + async_run_on_cpu(cpu, tlb_flush_page_range_bits_by_mmuidx_async_1, + RUN_ON_CPU_HOST_PTR(p)); + } +} + +void tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, + target_ulong addr, + target_ulong leng= th, + uint16_t idxmap, + unsigned bits) +{ + TLBFlushPageRangeBitsByMMUIdxData d; + TLBFlushPageRangeBitsByMMUIdxData *p; + CPUState *dst_cpu; + + /* This should already be page aligned */ + addr &=3D TARGET_PAGE_BITS; + + d.addr =3D addr; + d.idxmap =3D idxmap; + d.bits =3D bits; + d.length =3D length; + + /* Allocate a separate data block for each destination cpu. */ + CPU_FOREACH(dst_cpu) { + if (dst_cpu !=3D src_cpu) { + p =3D g_new(TLBFlushPageRangeBitsByMMUIdxData, 1); + *p =3D d; + async_run_on_cpu(dst_cpu, + tlb_flush_page_range_bits_by_mmuidx_async_1, + RUN_ON_CPU_HOST_PTR(p)); + } + } + + p =3D g_new(TLBFlushPageRangeBitsByMMUIdxData, 1); + *p =3D d; + async_safe_run_on_cpu(src_cpu, tlb_flush_page_range_bits_by_mmuidx_asy= nc_1, + RUN_ON_CPU_HOST_PTR(p)); +} + /* update the TLBs so that writes to code in the virtual page 'addr' can be detected */ void tlb_protect_code(ram_addr_t ram_addr) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 6b036cae8f65..a7ff35efb865 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -212,6 +212,37 @@ void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, = target_ulong addr, */ void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong = addr, uint16_t idxmap); +/** + * tlb_flush_page_range_by_mmuidx: + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of start of page range to be flushed + * @length: the number of bytes to be flushed + * @idxmap: bitmap of MMU indexes to flush + * + * Flush a range of pages from the TLB of the specified CPU, for the speci= fied + * MMU indexes. + */ +void tlb_flush_page_range_bits_by_mmuidx(CPUState *cpu, target_ulong addr, + target_ulong length, uint16_t idx= map, + unsigned bits); +/** + * tlb_flush_page_range_by_mmuidx_all_cpus_synced: + * @cpu: Originating CPU of the flush + * @addr: virtual address of start of page range to be flushed + * @length: the number of bytes to be flushed + * @idxmap: bitmap of MMU indexes to flush + * + * Flush a range of pages from the TLB of all CPUs, for the specified MMU + * indexes like tlb_flush_page_by_mmuidx_all_cpus except the source + * vCPUs work is scheduled as safe work meaning all flushes will be + * complete once the source vCPUs safe work is complete. This will + * depend on when the guests translation ends the TB. + */ +void tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, + target_ulong addr, + target_ulong leng= th, + uint16_t idxmap, + unsigned bits); /** * tlb_flush_by_mmuidx: * @cpu: CPU whose TLB should be flushed @@ -313,6 +344,21 @@ static inline void tlb_flush_page_all_cpus_synced(CPUS= tate *src, target_ulong addr) { } +static inline void tlb_flush_page_range_bits_by_mmuidx(CPUState *cpu, + target_ulong addr, + target_ulong length, + uint16_t idxmap, + unsigned bits) +{ +} +static inline void +tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, + target_ulong addr, + target_ulong length, + uint16_t idxmap, + unsigned bits) +{ +} static inline void tlb_flush(CPUState *cpu) { } --=20 2.26.2 From nobody Sat May 4 23:35:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1620184069; cv=none; d=zohomail.com; s=zohoarc; b=oL+JAAzOkGYg20YihKqcbVl/0zMSD6gZfcjLWu/tpCr2R/j9yqHAuL6Mrz6CINv/6dMUjx8A1xO0MJkpZOPCmz9p+kP7fC14ZPALDo/29YB/ALgRsSkMK2PDJrEfDyCDT41mUceYfW8w8zS/8gNdKshiIVmH+ETco2kJdHDr+7A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620184069; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jlgETGbZuRzHBHvHlcUoL6xtFf9QKaaxdVGn5r8yTJA=; b=k+ocPyr2/Tk5Y33NoF117B3oBMOztHEEEFpWRkxiJAYHDJaQs1KKR/I5uLzcF9PjPsNFQCwaYqFNMxIH4+Y62mqF5P+aCclKXqXju30PBg5/gghkfoTsYt9VKNhET7hxSXGTuI4yi6287UID3zG2z7hhU0qq7lYhtSDHIsQ4eI8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162018406961451.30158968819842; Tue, 4 May 2021 20:07:49 -0700 (PDT) Received: from localhost ([::1]:50562 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1le7t6-0001Vn-4u for importer@patchew.org; Tue, 04 May 2021 23:07:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39048) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1le7qb-0008CD-Hf for qemu-devel@nongnu.org; Tue, 04 May 2021 23:05:13 -0400 Received: from mail-qv1-xf35.google.com ([2607:f8b0:4864:20::f35]:44788) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1le7qV-00032h-1e for qemu-devel@nongnu.org; Tue, 04 May 2021 23:05:13 -0400 Received: by mail-qv1-xf35.google.com with SMTP id u1so550484qvg.11 for ; Tue, 04 May 2021 20:05:06 -0700 (PDT) Received: from cube.int.bluestop.org (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id a63sm12270550qkf.132.2021.05.04.20.05.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 May 2021 20:05:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jlgETGbZuRzHBHvHlcUoL6xtFf9QKaaxdVGn5r8yTJA=; b=Gka7U2VPWD7XS/ZTppMHp81DH3AVgFEmnJCSPQkWFJCKmxh9Vsh69KLMcI25e3alRW MSe9PP2ACvY5t+1SPF/6ihyzK+wrmacoa3Cj1upylzQjaESfFe5Rm1fWY6yEgw42UyC0 /7W/OuM6vr3GC4KPa+C/ZGHstGQhPgeeMY5YoJ8cb6XbLWsSldgSwx91aHcBReEHiVxt copkclDr260xff6T2HsdjhC2VZFncKqlCilbPB3wlTuJJ8dH+gIFPrObSv/efE/D1fBa yzmEPH4qB1qnlX3zFGp3SGEOia14R+E2pNtjVzXJn3nbZfb51iISFnnSj9kS3DZmxs7V oxxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jlgETGbZuRzHBHvHlcUoL6xtFf9QKaaxdVGn5r8yTJA=; b=TZSX29EmvkSA+Ii6X2faqYoujwfXJUthSMAxYoHi0e5ycnstQB0XAe1Wf3nzSOZUJQ vMq3P+dbGVxlMIT3cU7t1axvKoN/h/QCenIQKBzGVGmDufR0dYebK/5n4iaKNXsGB4N/ vtpJDZl3M0VI4Cm8eh1lr9sK8kxxi6ceu6BkgFHxsdGmt2rV1A0zERIJdURXlielbQJ8 VUdHJ+6MjVYlJqrPnTjRsWbBOmkcatadFbHqXu7jFgNP8o0x4x2DBMB+dgFtMkYJvhHF ZLEmX9zmzlsn+ZkUALcZI4oD2iFz1xhuWoVnSNvuzGrBcacFkOgCCLfcGiVJKHo9Stis hncw== X-Gm-Message-State: AOAM533dehjLf09Vai/1pVhcTpNCNYEncE6H6TgjHi0DhmTEsPw9Bu2y aw3ue+wbS+r408vWZk01IncoBw== X-Google-Smtp-Source: ABdhPJzCWqD6tc2CSmRF7TepIODm8BL0oIFfd5GgZG8jCkXy0LGjNVy5ru3Xb7nQVf0nFYP5KsYQIg== X-Received: by 2002:a0c:ca8c:: with SMTP id a12mr28588897qvk.14.1620183905802; Tue, 04 May 2021 20:05:05 -0700 (PDT) From: Rebecca Cran To: Richard Henderson , Peter Maydell Subject: [PATCH v8 2/4] target/arm: Add support for FEAT_TLBIRANGE Date: Tue, 4 May 2021 21:04:41 -0600 Message-Id: <20210505030443.25310-3-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210505030443.25310-1-rebecca@nuviainc.com> References: <20210505030443.25310-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f35; envelope-from=rebecca@nuviainc.com; helo=mail-qv1-xf35.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , qemu-devel@nongnu.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @nuviainc-com.20150623.gappssmtp.com) Content-Type: text/plain; charset="utf-8" ARMv8.4 adds the mandatory FEAT_TLBIRANGE. It provides TLBI maintenance instructions that apply to a range of input addresses. Signed-off-by: Rebecca Cran --- target/arm/cpu.h | 5 + target/arm/helper.c | 296 ++++++++++++++++++++ 2 files changed, 301 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 616b39325347..5802798c3069 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4071,6 +4071,11 @@ static inline bool isar_feature_aa64_pauth_arch(cons= t ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) !=3D 0; } =20 +static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) =3D=3D 2; +} + static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 9b1b98705f91..cb10851efda8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4759,6 +4759,219 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env= , const ARMCPRegInfo *ri, ARMMMUIdxBit_SE3, bits); } =20 +#ifdef TARGET_AARCH64 +static uint64_t tlbi_aa64_range_get_length(CPUARMState *env, + uint64_t value) +{ + unsigned int page_shift; + unsigned int page_size_granule; + uint64_t num; + uint64_t scale; + uint64_t exponent; + uint64_t length; + + num =3D extract64(value, 39, 4); + scale =3D extract64(value, 44, 2); + page_size_granule =3D extract64(value, 46, 2); + + page_shift =3D page_size_granule * 2 + 10; + + if (page_size_granule =3D=3D 0) { + qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n", + page_size_granule); + return 0; + } + + exponent =3D (5 * scale) + 1; + length =3D (num + 1) << (exponent + page_shift); + + return length; +} + +static void tlbi_aa64_rvae1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL1&0. + * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1, + * since we don't support flush-for-specific-ASID-only or + * flush-last-level-only. + */ + ARMMMUIdx mmu_idx; + int mask; + int bits; + uint64_t pageaddr; + uint64_t length; + + CPUState *cs =3D env_cpu(env); + mask =3D vae1_tlbmask(env); + mmu_idx =3D ARM_MMU_IDX_A | ctz32(mask); + if (regime_has_2_ranges(mmu_idx)) { + pageaddr =3D sextract64(value, 0, 37) << TARGET_PAGE_BITS; + } else { + pageaddr =3D extract64(value, 0, 37) << TARGET_PAGE_BITS; + } + length =3D tlbi_aa64_range_get_length(env, value); + bits =3D tlbbits_for_regime(env, mmu_idx, pageaddr); + + if (tlb_force_broadcast(env)) { + tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + length, mask, + bits); + } else { + tlb_flush_page_range_bits_by_mmuidx(cs, pageaddr, length, mask, + bits); + } +} + +static void tlbi_aa64_rvae1is_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + /* + * Invalidate by VA range, Inner/Outer Shareable EL1&0. + * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS, + * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support + * flush-for-specific-ASID-only, flush-last-level-only or inner/outer + * shareable specific flushes. + */ + ARMMMUIdx mmu_idx; + int mask; + int bits; + uint64_t pageaddr; + uint64_t length; + + CPUState *cs =3D env_cpu(env); + mask =3D vae1_tlbmask(env); + mmu_idx =3D ARM_MMU_IDX_A | ctz32(mask); + if (regime_has_2_ranges(mmu_idx)) { + pageaddr =3D sextract64(value, 0, 37) << TARGET_PAGE_BITS; + } else { + pageaddr =3D extract64(value, 0, 37) << TARGET_PAGE_BITS; + } + length =3D tlbi_aa64_range_get_length(env, value); + bits =3D tlbbits_for_regime(env, mmu_idx, pageaddr); + + tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + length, mask, + bits); +} + +static void tlbi_aa64_rvae2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL2. + * Currently handles all of RVAE2 and RVALE2, + * since we don't support flush-for-specific-ASID-only or + * flush-last-level-only. + */ + bool secure; + int mask; + int bits; + uint64_t pageaddr; + uint64_t length; + + CPUState *cs =3D env_cpu(env); + secure =3D arm_is_secure_below_el3(env); + pageaddr =3D extract64(value, 0, 37) << TARGET_PAGE_BITS; + length =3D tlbi_aa64_range_get_length(env, value); + mask =3D secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; + bits =3D tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2, + pageaddr); + + if (tlb_force_broadcast(env)) { + tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + length, mask, + bits); + } else { + tlb_flush_page_range_bits_by_mmuidx(cs, pageaddr, length, mask, + bits); + } +} + +static void tlbi_aa64_rvae2is_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + /* + * Invalidate by VA range, Inner/Outer Shareable, EL2. + * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS, + * since we don't support flush-for-specific-ASID-only, + * flush-last-level-only or inner/outer shareable specific flushes. + */ + bool secure; + int mask; + int bits; + uint64_t pageaddr; + uint64_t length; + + CPUState *cs =3D env_cpu(env); + secure =3D arm_is_secure_below_el3(env); + pageaddr =3D extract64(value, 0, 37) << TARGET_PAGE_BITS; + length =3D tlbi_aa64_range_get_length(env, value); + mask =3D secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; + bits =3D tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2, + pageaddr); + + tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + length, mask, + bits); +} + +static void tlbi_aa64_rvae3_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL3. + * Currently handles all of RVAE3 and RVALE3, + * since we don't support flush-for-specific-ASID-only or + * flush-last-level-only. + */ + int bits; + uint64_t pageaddr; + uint64_t length; + + CPUState *cs =3D env_cpu(env); + pageaddr =3D extract64(value, 0, 37) << TARGET_PAGE_BITS; + length =3D tlbi_aa64_range_get_length(env, value); + bits =3D tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr); + + if (tlb_force_broadcast(env)) { + tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + length, + ARMMMUIdxBit_S= E3, + bits); + } else { + tlb_flush_page_range_bits_by_mmuidx(cs, pageaddr, length, + ARMMMUIdxBit_SE3, + bits); + } +} + +static void tlbi_aa64_rvae3is_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL3, Inner/Outer Shareable. + * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS, + * since we don't support flush-for-specific-ASID-only, + * flush-last-level-only or inner/outer specific flushes. + */ + int bits; + uint64_t pageaddr; + uint64_t length; + + CPUState *cs =3D env_cpu(env); + pageaddr =3D extract64(value, 0, 37) << TARGET_PAGE_BITS; + length =3D tlbi_aa64_range_get_length(env, value); + bits =3D tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr); + + tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + length, + ARMMMUIdxBit_SE3, + bits); +} +#endif + static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo= *ri, bool isread) { @@ -6920,6 +7133,86 @@ static const ARMCPRegInfo pauth_reginfo[] =3D { REGINFO_SENTINEL }; =20 +static const ARMCPRegInfo tlbirange_reginfo[] =3D { + { .name =3D "TLBI_RVAE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAAE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 3, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVALE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAALE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 7, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1_write }, + { .name =3D "TLBI_RVAAE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 3, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1_write }, + { .name =3D "TLBI_RVALE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1_write }, + { .name =3D "TLBI_RVAALE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 7, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1_write }, + { .name =3D "TLBI_RIPAS2E1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 2, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2LE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RVAE2IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2is_write }, + { .name =3D "TLBI_RVALE2IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2is_write }, + { .name =3D "TLBI_RIPAS2E1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 2, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2LE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RVAE2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2_write }, + { .name =3D "TLBI_RVALE2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2_write }, + { .name =3D "TLBI_RVAE3IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3is_write }, + { .name =3D "TLBI_RVALE3IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3is_write }, + { .name =3D "TLBI_RVAE3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3_write }, + { .name =3D "TLBI_RVALE3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3_write }, + REGINFO_SENTINEL +}; + static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) { Error *err =3D NULL; @@ -8289,6 +8582,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_rndr, cpu)) { define_arm_cp_regs(cpu, rndr_reginfo); } + if (cpu_isar_feature(aa64_tlbirange, cpu)) { + define_arm_cp_regs(cpu, tlbirange_reginfo); + } #ifndef CONFIG_USER_ONLY /* Data Cache clean instructions up to PoP */ if (cpu_isar_feature(aa64_dcpop, cpu)) { --=20 2.26.2 From nobody Sat May 4 23:35:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1620184264; cv=none; d=zohomail.com; s=zohoarc; b=VM1YVcolIJ221ezpQDA75gKMXF9jqsDUSzzIOes3RFgr7wQFZZl3Pi5aGxHknq8FpjGe+uDoR4N4P6L+Cf6CWoyFtN6I47SyR8yloYexC4UBeTHTWgNxrPZMmXAriiBbAyuIYAEBNmfzoQjSklNTmErfDRk+s13NcHfuB3hd/Lw= ARC-Message-Signature: i=1; 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id a63sm12270550qkf.132.2021.05.04.20.05.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 May 2021 20:05:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gehSBgjnjQRNmV009q75lCL2iDxHBnM112fEwKMS6aA=; b=1u0HBwjOeX8loV5l2xCF4uOZm9BYfKIt56h3Zj5ceAI9wvVFpPfyUJ+kPzxYsAYYqO yemDn4h8p+KfIhnUiHQ1Vrqw9j5ZJGyx36hEipNwwVFPk8iptLx87AgHt1wwF6SFAxUy 5AFxzf++NIqhcYggNmz2DUh0xnymatg0Uj1x2DOLjz7O8+b5GgywVeXBYUpNTNEW23x+ EbqkdV6UDMRW+nwUHXaHGGDRpguLBINPubs8t52dg2yKEzb3eXJUBSShT8ckprVdklBS xLc/R8Nr48ummOgGEGhKgVhfTdqIjeoVKju7/tHZQ2HPKPaUIPk40yX8twrVIbj21UM5 s1sQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gehSBgjnjQRNmV009q75lCL2iDxHBnM112fEwKMS6aA=; b=lO5LqU2oKNdnChyFaG1a3+AOoWSukg3gOyx+gdoRq6MPYj3TZomy9nn9AwEOIeXwPT FtIVzLtpMoujIIPdChXxQR9+0xsFog1oS9yz1fmAKbV/dz4cUfQM5r9kGU52PVWesEDk jOD1aPuNprzMHJafycO9Ticx9L/0+Rn4oqrGlK+WKE1LaZS3A9f/HvLBCaGMuApm+5bk YAnqgBRr4cZ1rwnRCAzD6YxsvFCRPivo9W/2V3sC1o2dzP925wxv0K/3wWXkwG7w2rk2 Kl/EN5e4HNJECCCFtdGuT+94ihBjG0I6zHTO6rIu4Ugwm81OSi8irHw1lhm/Fy8bR3zs 1emw== X-Gm-Message-State: AOAM530StSnbDWUx1apRwNvsQ2lSwiT/Z0+b1DoLjRWHG3bxHDgYZoCT p9nDO4MHvws9FTA5MUi4PKk9Zw== X-Google-Smtp-Source: ABdhPJygbS5PjUK2rI09IAF0KR5hIwgWgOaWrxSV2nkq0vrzvvYyD96tWhA1ygHJcgZmt6eQc+fnxw== X-Received: by 2002:a37:7944:: with SMTP id u65mr27714555qkc.29.1620183906930; Tue, 04 May 2021 20:05:06 -0700 (PDT) From: Rebecca Cran To: Richard Henderson , Peter Maydell Subject: [PATCH v8 3/4] target/arm: Add support for FEAT_TLBIOS Date: Tue, 4 May 2021 21:04:42 -0600 Message-Id: <20210505030443.25310-4-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210505030443.25310-1-rebecca@nuviainc.com> References: <20210505030443.25310-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::729; envelope-from=rebecca@nuviainc.com; helo=mail-qk1-x729.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , qemu-devel@nongnu.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @nuviainc-com.20150623.gappssmtp.com) Content-Type: text/plain; charset="utf-8" ARMv8.4 adds the mandatory FEAT_TLBIOS. It provides TLBI maintenance instructions that extend to the Outer Shareable domain. Signed-off-by: Rebecca Cran --- target/arm/cpu.h | 5 ++ target/arm/helper.c | 75 ++++++++++++++++++++ 2 files changed, 80 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5802798c3069..7986a217acdd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4076,6 +4076,11 @@ static inline bool isar_feature_aa64_tlbirange(const= ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) =3D=3D 2; } =20 +static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) !=3D 0; +} + static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index cb10851efda8..04c4d766adb9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7213,6 +7213,78 @@ static const ARMCPRegInfo tlbirange_reginfo[] =3D { REGINFO_SENTINEL }; =20 +static const ARMCPRegInfo tlbios_reginfo[] =3D { + { .name =3D "TLBI_VMALLE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vmalle1is_write }, + { .name =3D "TLBI_ASIDE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 2, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vmalle1is_write }, + { .name =3D "TLBI_RVAE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAAE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 3, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVALE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAALE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 7, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_ALLE2OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle2is_write }, + { .name =3D "TLBI_ALLE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 4, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle1is_write }, + { .name =3D "TLBI_VMALLS12E1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle1is_write }, + { .name =3D "TLBI_IPAS2E1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 0, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2E1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 3, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_IPAS2LE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 4, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2LE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 7, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RVAE2OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2is_write }, + { .name =3D "TLBI_RVALE2OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2is_write }, + { .name =3D "TLBI_ALLE3OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle3is_write }, + { .name =3D "TLBI_RVAE3OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3is_write }, + { .name =3D "TLBI_RVALE3OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3is_write }, + REGINFO_SENTINEL +}; + static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) { Error *err =3D NULL; @@ -8585,6 +8657,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_tlbirange, cpu)) { define_arm_cp_regs(cpu, tlbirange_reginfo); } + if (cpu_isar_feature(aa64_tlbios, cpu)) { + define_arm_cp_regs(cpu, tlbios_reginfo); + } #ifndef CONFIG_USER_ONLY /* Data Cache clean instructions up to PoP */ if (cpu_isar_feature(aa64_dcpop, cpu)) { --=20 2.26.2 From nobody Sat May 4 23:35:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1620184542; cv=none; d=zohomail.com; s=zohoarc; b=NzkbTIOvg9+JuFp0YLdECGYHaNGvek4t5+ah2KFu/EYFDuXbQywQMaPWLx5r5SNEntSyws9jRLZDeYLxQK93SdYbqdvFAS7ZdOQZG3R2r2ZlPpmVslqcaIT/+vPbqFvD/1UpKkiGn1kiagYFQffOqF4mcNhW4M3BcDZVxOY0RRA= ARC-Message-Signature: i=1; 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id a63sm12270550qkf.132.2021.05.04.20.05.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 May 2021 20:05:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uNizM5dd+njefSGglfwPGotA4yVew4h3gSREpFzckEs=; b=05WXkcw2sOlbiq6nu0JNKVFANsscIs2gaD5SDLLLZ56buXsFk0UUyUgHR7GV1gounI XNbucrzS3z+xDT+1buUDiiF/mLuDuao0LcVQnrzwnr9TldqlI2hoRwsl3N6KR25Dfbdv 9n14jqN4ih+adVEXih6Z/fcfcq6ez2sNJXTfm2gROQ4/+4FDh+47YC3xsbXUq84JWIiq i//jIGNHhMibUhrXMHrG9AUAGM6KSXAYw9TWWYq7plQ856QoDAaloSbrfnH/sl+uZpHg zUa3PtTvelX+/Kk7h831r89wJM6nCm51ruTquXX0epcOqlZFRnOoHadBC5zbhUA2OUe0 4BIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uNizM5dd+njefSGglfwPGotA4yVew4h3gSREpFzckEs=; b=GFHOGnENx+LUOnput5Gd2vPxc3xbQzbQ0Jm5/XTEwLAyj0zOytduEuk93Gp79Au+KZ q4+qwAkgEH8CHzTzJ2scvnZfpsukp69JAjxSP4mi23jXfdXRdJso739VH/YBZsBNsBgK e3wTAO+hYeY+UZjBdLIzJwtbotlioN2zYT+9gOuUCNOu2w/rphyX3IQxAw25E5K1lOww RzU2mvqW+Ri8QFAeXUpvmXCTW/DlICL94Wlb1sgS4DGUH/Idp0IKK4gQzED0lAgllGTT 0z/zIDJtcstq0kVXrwMdJbUwF8dduMFAkXiCucM1AyzHcKqpQ8W1bEQzbGiAQHy02f4p /sxw== X-Gm-Message-State: AOAM532jyTG1EAo08cxSNrG6FUKN55Sc0f/B4t4tu07jEGuLmMKgjaGY 5IVJmgnjUUZsRApvasOgFLtDaA== X-Google-Smtp-Source: ABdhPJyIdUDWQsjnx2P468PdQcMp4i03Ar0A20MTFP5/m/JakjuJzGQoguhGFr1zVqlmVV+aOxFhkA== X-Received: by 2002:a37:27cd:: with SMTP id n196mr13036119qkn.420.1620183908054; Tue, 04 May 2021 20:05:08 -0700 (PDT) From: Rebecca Cran To: Richard Henderson , Peter Maydell Subject: [PATCH v8 4/4] target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type Date: Tue, 4 May 2021 21:04:43 -0600 Message-Id: <20210505030443.25310-5-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210505030443.25310-1-rebecca@nuviainc.com> References: <20210505030443.25310-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::735; envelope-from=rebecca@nuviainc.com; helo=mail-qk1-x735.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , qemu-devel@nongnu.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @nuviainc-com.20150623.gappssmtp.com) Content-Type: text/plain; charset="utf-8" Indicate support for FEAT_TLBIOS and FEAT_TLBIRANGE by setting ID_AA64ISAR0.TLB to 2 for the max AARCH64 CPU type. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson --- target/arm/cpu64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f0a9e968c9c1..f42803ecaf1d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -651,6 +651,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); cpu->isar.id_aa64isar0 =3D t; =20 --=20 2.26.2