[PULL 00/36] MIPS patches for 2021-05-02

Philippe Mathieu-Daudé posted 36 patches 3 years ago
Test checkpatch failed
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20210502161538.534038-1-f4bug@amsat.org
Maintainers: Jiaxun Yang <jiaxun.yang@flygoat.com>, "Philippe Mathieu-Daudé" <f4bug@amsat.org>, Aurelien Jarno <aurelien@aurel32.net>, Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
meson.build                                  |    6 +
target/mips/helper.h                         |  183 +--
target/mips/internal.h                       |  105 +-
target/mips/tcg/tcg-internal.h               |   64 +
target/mips/translate.h                      |    7 +-
target/mips/{ => tcg}/msa_helper.h.inc       |    0
target/mips/tcg/sysemu_helper.h.inc          |  185 +++
target/mips/{ => tcg}/mips32r6.decode        |    0
target/mips/{ => tcg}/mips64r6.decode        |    0
target/mips/{ => tcg}/msa32.decode           |    0
target/mips/{ => tcg}/msa64.decode           |    0
target/mips/{ => tcg}/tx79.decode            |    0
hw/isa/piix4.c                               |    5 +-
target/mips/cpu.c                            |  311 ++---
target/mips/fpu.c                            |   25 +
target/mips/msa.c                            |   60 +
target/mips/op_helper.c                      | 1210 ------------------
target/mips/{ => sysemu}/addr.c              |    0
target/mips/sysemu/cp0.c                     |  123 ++
target/mips/{ => sysemu}/cp0_timer.c         |    0
target/mips/{ => sysemu}/machine.c           |   21 +-
target/mips/sysemu/physaddr.c                |  257 ++++
target/mips/{ => tcg}/dsp_helper.c           |    0
target/mips/tcg/exception.c                  |  167 +++
target/mips/{ => tcg}/fpu_helper.c           |    8 -
target/mips/tcg/ldst_helper.c                |  288 +++++
target/mips/{ => tcg}/lmmi_helper.c          |    0
target/mips/{ => tcg}/msa_helper.c           |   36 -
target/mips/{ => tcg}/msa_translate.c        |    0
target/mips/{ => tcg}/mxu_translate.c        |    0
target/mips/tcg/op_helper.c                  |  420 ++++++
target/mips/{ => tcg}/rel6_translate.c       |    0
target/mips/{ => tcg/sysemu}/cp0_helper.c    |    0
target/mips/{ => tcg/sysemu}/mips-semi.c     |    0
target/mips/tcg/sysemu/special_helper.c      |  173 +++
target/mips/{ => tcg/sysemu}/tlb_helper.c    |  623 +++++----
target/mips/{ => tcg}/translate.c            |  115 +-
target/mips/{ => tcg}/translate_addr_const.c |    0
target/mips/{ => tcg}/tx79_translate.c       |    0
target/mips/{ => tcg}/txx9_translate.c       |    0
target/mips/tcg/user/tlb_helper.c            |   64 +
.gitlab-ci.d/crossbuilds.yml                 |    8 +
MAINTAINERS                                  |    3 +-
hw/mips/meson.build                          |   11 +-
target/mips/meson.build                      |   55 +-
target/mips/sysemu/meson.build               |    7 +
target/mips/tcg/meson.build                  |   35 +
target/mips/tcg/sysemu/meson.build           |    6 +
target/mips/tcg/user/meson.build             |    3 +
49 files changed, 2426 insertions(+), 2158 deletions(-)
create mode 100644 target/mips/tcg/tcg-internal.h
rename target/mips/{ => tcg}/msa_helper.h.inc (100%)
create mode 100644 target/mips/tcg/sysemu_helper.h.inc
rename target/mips/{ => tcg}/mips32r6.decode (100%)
rename target/mips/{ => tcg}/mips64r6.decode (100%)
rename target/mips/{ => tcg}/msa32.decode (100%)
rename target/mips/{ => tcg}/msa64.decode (100%)
rename target/mips/{ => tcg}/tx79.decode (100%)
create mode 100644 target/mips/fpu.c
create mode 100644 target/mips/msa.c
delete mode 100644 target/mips/op_helper.c
rename target/mips/{ => sysemu}/addr.c (100%)
create mode 100644 target/mips/sysemu/cp0.c
rename target/mips/{ => sysemu}/cp0_timer.c (100%)
rename target/mips/{ => sysemu}/machine.c (94%)
create mode 100644 target/mips/sysemu/physaddr.c
rename target/mips/{ => tcg}/dsp_helper.c (100%)
create mode 100644 target/mips/tcg/exception.c
rename target/mips/{ => tcg}/fpu_helper.c (99%)
create mode 100644 target/mips/tcg/ldst_helper.c
rename target/mips/{ => tcg}/lmmi_helper.c (100%)
rename target/mips/{ => tcg}/msa_helper.c (99%)
rename target/mips/{ => tcg}/msa_translate.c (100%)
rename target/mips/{ => tcg}/mxu_translate.c (100%)
create mode 100644 target/mips/tcg/op_helper.c
rename target/mips/{ => tcg}/rel6_translate.c (100%)
rename target/mips/{ => tcg/sysemu}/cp0_helper.c (100%)
rename target/mips/{ => tcg/sysemu}/mips-semi.c (100%)
create mode 100644 target/mips/tcg/sysemu/special_helper.c
rename target/mips/{ => tcg/sysemu}/tlb_helper.c (76%)
rename target/mips/{ => tcg}/translate.c (99%)
rename target/mips/{ => tcg}/translate_addr_const.c (100%)
rename target/mips/{ => tcg}/tx79_translate.c (100%)
rename target/mips/{ => tcg}/txx9_translate.c (100%)
create mode 100644 target/mips/tcg/user/tlb_helper.c
create mode 100644 target/mips/sysemu/meson.build
create mode 100644 target/mips/tcg/meson.build
create mode 100644 target/mips/tcg/sysemu/meson.build
create mode 100644 target/mips/tcg/user/meson.build
[PULL 00/36] MIPS patches for 2021-05-02
Posted by Philippe Mathieu-Daudé 3 years ago
The following changes since commit 53c5433e84e8935abed8e91d4a2eb813168a0ecf:

  Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210501' into staging (2021-05-02 12:02:46 +0100)

are available in the Git repository at:

  https://github.com/philmd/qemu.git tags/mips-20210502

for you to fetch changes up to 1c13514449439b5ff1f746ed0bf73b298da39cf0:

  gitlab-ci: Add KVM mips64el cross-build jobs (2021-05-02 16:49:35 +0200)

----------------------------------------------------------------
MIPS patches queue

- Fix CACHEE opcode
- Add missing CP0 checks to nanoMIPS RDPGPR / WRPGPR opcodes
- Remove isa_get_irq() call in PIIX4 south bridge
- Add various missing fields to the MIPS CPU migration vmstate
- Lot of code moved around to allow TCG or KVM only builds
- Restrict non-virtualized machines to TCG
- Add KVM mips64el cross-build jobs to gitlab-ci


scripts/checkpatch.pl false positive in patch 31
"Move TLB management helpers to tcg/sysemu/tlb_helper.c":

4 checkpatch errors:

  ERROR: space prohibited after that '&' (ctx:WxW)
  #414: FILE: target/mips/tcg/sysemu/tlb_helper.c:71:
  +    tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
                                                    ^

  ERROR: space prohibited after that '&' (ctx:WxW)
  #415: FILE: target/mips/tcg/sysemu/tlb_helper.c:72:
  +    tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
                                                    ^

  ERROR: space prohibited after that '&' (ctx:WxW)
  #420: FILE: target/mips/tcg/sysemu/tlb_helper.c:77:
  +    tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
                                                    ^

  ERROR: space prohibited after that '&' (ctx:WxW)
  #421: FILE: target/mips/tcg/sysemu/tlb_helper.c:78:
  +    tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
                                                    ^

  total: 4 errors, 0 warnings, 688 lines checked
----------------------------------------------------------------

Philippe Mathieu-Daudé (36):
  hw/isa/piix4: Use qdev_get_gpio_in_named() to get ISA IRQ
  target/mips: Fix CACHEE opcode (CACHE using EVA addressing)
  target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes
  target/mips: Remove spurious LOG_UNIMP of MTHC0 opcode
  target/mips: Migrate missing CPU fields
  target/mips: Make check_cp0_enabled() return a boolean
  target/mips: Simplify meson TCG rules
  target/mips: Move IEEE rounding mode array to new source file
  target/mips: Move msa_reset() to new source file
  target/mips: Make CPU/FPU regnames[] arrays global
  target/mips: Optimize CPU/FPU regnames[] arrays
  target/mips: Restrict mips_cpu_dump_state() to cpu.c
  target/mips: Turn printfpr() macro into a proper function
  target/mips: Declare mips_env_set_pc() inlined in "internal.h"
  target/mips: Merge do_translate_address into
    cpu_mips_translate_address
  target/mips: Extract load/store helpers to ldst_helper.c
  meson: Introduce meson_user_arch source set for arch-specific
    user-mode
  target/mips: Introduce tcg-internal.h for TCG specific declarations
  target/mips: Add simple user-mode mips_cpu_do_interrupt()
  target/mips: Add simple user-mode mips_cpu_tlb_fill()
  target/mips: Move cpu_signal_handler definition around
  target/mips: Move sysemu specific files under sysemu/ subfolder
  target/mips: Move physical addressing code to sysemu/physaddr.c
  target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG
  target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder
  target/mips: Restrict mmu_init() to TCG
  target/mips: Move tlb_helper.c to tcg/sysemu/
  target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope
  target/mips: Move Special opcodes to tcg/sysemu/special_helper.c
  target/mips: Move helper_cache() to tcg/sysemu/special_helper.c
  target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c
  target/mips: Move exception management code to exception.c
  target/mips: Move CP0 helpers to sysemu/cp0.c
  target/mips: Move TCG source files under tcg/ sub directory
  hw/mips: Restrict non-virtualized machines to TCG
  gitlab-ci: Add KVM mips64el cross-build jobs

 meson.build                                  |    6 +
 target/mips/helper.h                         |  183 +--
 target/mips/internal.h                       |  105 +-
 target/mips/tcg/tcg-internal.h               |   64 +
 target/mips/translate.h                      |    7 +-
 target/mips/{ => tcg}/msa_helper.h.inc       |    0
 target/mips/tcg/sysemu_helper.h.inc          |  185 +++
 target/mips/{ => tcg}/mips32r6.decode        |    0
 target/mips/{ => tcg}/mips64r6.decode        |    0
 target/mips/{ => tcg}/msa32.decode           |    0
 target/mips/{ => tcg}/msa64.decode           |    0
 target/mips/{ => tcg}/tx79.decode            |    0
 hw/isa/piix4.c                               |    5 +-
 target/mips/cpu.c                            |  311 ++---
 target/mips/fpu.c                            |   25 +
 target/mips/msa.c                            |   60 +
 target/mips/op_helper.c                      | 1210 ------------------
 target/mips/{ => sysemu}/addr.c              |    0
 target/mips/sysemu/cp0.c                     |  123 ++
 target/mips/{ => sysemu}/cp0_timer.c         |    0
 target/mips/{ => sysemu}/machine.c           |   21 +-
 target/mips/sysemu/physaddr.c                |  257 ++++
 target/mips/{ => tcg}/dsp_helper.c           |    0
 target/mips/tcg/exception.c                  |  167 +++
 target/mips/{ => tcg}/fpu_helper.c           |    8 -
 target/mips/tcg/ldst_helper.c                |  288 +++++
 target/mips/{ => tcg}/lmmi_helper.c          |    0
 target/mips/{ => tcg}/msa_helper.c           |   36 -
 target/mips/{ => tcg}/msa_translate.c        |    0
 target/mips/{ => tcg}/mxu_translate.c        |    0
 target/mips/tcg/op_helper.c                  |  420 ++++++
 target/mips/{ => tcg}/rel6_translate.c       |    0
 target/mips/{ => tcg/sysemu}/cp0_helper.c    |    0
 target/mips/{ => tcg/sysemu}/mips-semi.c     |    0
 target/mips/tcg/sysemu/special_helper.c      |  173 +++
 target/mips/{ => tcg/sysemu}/tlb_helper.c    |  623 +++++----
 target/mips/{ => tcg}/translate.c            |  115 +-
 target/mips/{ => tcg}/translate_addr_const.c |    0
 target/mips/{ => tcg}/tx79_translate.c       |    0
 target/mips/{ => tcg}/txx9_translate.c       |    0
 target/mips/tcg/user/tlb_helper.c            |   64 +
 .gitlab-ci.d/crossbuilds.yml                 |    8 +
 MAINTAINERS                                  |    3 +-
 hw/mips/meson.build                          |   11 +-
 target/mips/meson.build                      |   55 +-
 target/mips/sysemu/meson.build               |    7 +
 target/mips/tcg/meson.build                  |   35 +
 target/mips/tcg/sysemu/meson.build           |    6 +
 target/mips/tcg/user/meson.build             |    3 +
 49 files changed, 2426 insertions(+), 2158 deletions(-)
 create mode 100644 target/mips/tcg/tcg-internal.h
 rename target/mips/{ => tcg}/msa_helper.h.inc (100%)
 create mode 100644 target/mips/tcg/sysemu_helper.h.inc
 rename target/mips/{ => tcg}/mips32r6.decode (100%)
 rename target/mips/{ => tcg}/mips64r6.decode (100%)
 rename target/mips/{ => tcg}/msa32.decode (100%)
 rename target/mips/{ => tcg}/msa64.decode (100%)
 rename target/mips/{ => tcg}/tx79.decode (100%)
 create mode 100644 target/mips/fpu.c
 create mode 100644 target/mips/msa.c
 delete mode 100644 target/mips/op_helper.c
 rename target/mips/{ => sysemu}/addr.c (100%)
 create mode 100644 target/mips/sysemu/cp0.c
 rename target/mips/{ => sysemu}/cp0_timer.c (100%)
 rename target/mips/{ => sysemu}/machine.c (94%)
 create mode 100644 target/mips/sysemu/physaddr.c
 rename target/mips/{ => tcg}/dsp_helper.c (100%)
 create mode 100644 target/mips/tcg/exception.c
 rename target/mips/{ => tcg}/fpu_helper.c (99%)
 create mode 100644 target/mips/tcg/ldst_helper.c
 rename target/mips/{ => tcg}/lmmi_helper.c (100%)
 rename target/mips/{ => tcg}/msa_helper.c (99%)
 rename target/mips/{ => tcg}/msa_translate.c (100%)
 rename target/mips/{ => tcg}/mxu_translate.c (100%)
 create mode 100644 target/mips/tcg/op_helper.c
 rename target/mips/{ => tcg}/rel6_translate.c (100%)
 rename target/mips/{ => tcg/sysemu}/cp0_helper.c (100%)
 rename target/mips/{ => tcg/sysemu}/mips-semi.c (100%)
 create mode 100644 target/mips/tcg/sysemu/special_helper.c
 rename target/mips/{ => tcg/sysemu}/tlb_helper.c (76%)
 rename target/mips/{ => tcg}/translate.c (99%)
 rename target/mips/{ => tcg}/translate_addr_const.c (100%)
 rename target/mips/{ => tcg}/tx79_translate.c (100%)
 rename target/mips/{ => tcg}/txx9_translate.c (100%)
 create mode 100644 target/mips/tcg/user/tlb_helper.c
 create mode 100644 target/mips/sysemu/meson.build
 create mode 100644 target/mips/tcg/meson.build
 create mode 100644 target/mips/tcg/sysemu/meson.build
 create mode 100644 target/mips/tcg/user/meson.build

-- 
2.26.3

Re: [PULL 00/36] MIPS patches for 2021-05-02
Posted by no-reply@patchew.org 3 years ago
Patchew URL: https://patchew.org/QEMU/20210502161538.534038-1-f4bug@amsat.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20210502161538.534038-1-f4bug@amsat.org
Subject: [PULL 00/36] MIPS patches for 2021-05-02

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/20210502160326.1196252-1-linux@roeck-us.net -> patchew/20210502160326.1196252-1-linux@roeck-us.net
 * [new tag]         patchew/20210502161538.534038-1-f4bug@amsat.org -> patchew/20210502161538.534038-1-f4bug@amsat.org
Switched to a new branch 'test'
153fae2 gitlab-ci: Add KVM mips64el cross-build jobs
0a555e6 hw/mips: Restrict non-virtualized machines to TCG
a8a91c9 target/mips: Move TCG source files under tcg/ sub directory
5807053 target/mips: Move CP0 helpers to sysemu/cp0.c
46d44ac target/mips: Move exception management code to exception.c
4fc84f2 target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c
4efe8dc target/mips: Move helper_cache() to tcg/sysemu/special_helper.c
b0da237 target/mips: Move Special opcodes to tcg/sysemu/special_helper.c
d53f2a0 target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope
f13b3b0 target/mips: Move tlb_helper.c to tcg/sysemu/
0584792 target/mips: Restrict mmu_init() to TCG
249d351 target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder
e43ecf4 target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG
220dc20 target/mips: Move physical addressing code to sysemu/physaddr.c
6f7158f target/mips: Move sysemu specific files under sysemu/ subfolder
da27055 target/mips: Move cpu_signal_handler definition around
1b9571f target/mips: Add simple user-mode mips_cpu_tlb_fill()
7ba1be7 target/mips: Add simple user-mode mips_cpu_do_interrupt()
6176008 target/mips: Introduce tcg-internal.h for TCG specific declarations
fe7a887 meson: Introduce meson_user_arch source set for arch-specific user-mode
671a7a3 target/mips: Extract load/store helpers to ldst_helper.c
dcf190f target/mips: Merge do_translate_address into cpu_mips_translate_address
c7bee2a target/mips: Declare mips_env_set_pc() inlined in "internal.h"
314c65c target/mips: Turn printfpr() macro into a proper function
6daca61 target/mips: Restrict mips_cpu_dump_state() to cpu.c
4f7d374 target/mips: Optimize CPU/FPU regnames[] arrays
6604fa5 target/mips: Make CPU/FPU regnames[] arrays global
c8c1839 target/mips: Move msa_reset() to new source file
3ecd205 target/mips: Move IEEE rounding mode array to new source file
eb9ab4e target/mips: Simplify meson TCG rules
38235a2 target/mips: Make check_cp0_enabled() return a boolean
c0aa51a target/mips: Migrate missing CPU fields
e5939a3 target/mips: Remove spurious LOG_UNIMP of MTHC0 opcode
f0cf233 target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes
e8283b3 target/mips: Fix CACHEE opcode (CACHE using EVA addressing)
07ade0a hw/isa/piix4: Use qdev_get_gpio_in_named() to get ISA IRQ

=== OUTPUT BEGIN ===
1/36 Checking commit 07ade0a92cae (hw/isa/piix4: Use qdev_get_gpio_in_named() to get ISA IRQ)
2/36 Checking commit e8283b3b2b28 (target/mips: Fix CACHEE opcode (CACHE using EVA addressing))
3/36 Checking commit f0cf233e449f (target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes)
4/36 Checking commit e5939a36e3e9 (target/mips: Remove spurious LOG_UNIMP of MTHC0 opcode)
5/36 Checking commit c0aa51a12edc (target/mips: Migrate missing CPU fields)
6/36 Checking commit 38235a22d857 (target/mips: Make check_cp0_enabled() return a boolean)
7/36 Checking commit eb9ab4e4d7b6 (target/mips: Simplify meson TCG rules)
8/36 Checking commit 3ecd205a58ca (target/mips: Move IEEE rounding mode array to new source file)
Use of uninitialized value $acpi_testexpected in string eq at ./scripts/checkpatch.pl line 1529.
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31: 
new file mode 100644

total: 0 errors, 1 warnings, 39 lines checked

Patch 8/36 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/36 Checking commit c8c183917a34 (target/mips: Move msa_reset() to new source file)
Use of uninitialized value $acpi_testexpected in string eq at ./scripts/checkpatch.pl line 1529.
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#37: 
new file mode 100644

total: 0 errors, 1 warnings, 70 lines checked

Patch 9/36 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/36 Checking commit 6604fa5e6bd1 (target/mips: Make CPU/FPU regnames[] arrays global)
11/36 Checking commit 4f7d37453de6 (target/mips: Optimize CPU/FPU regnames[] arrays)
12/36 Checking commit 6daca61b9815 (target/mips: Restrict mips_cpu_dump_state() to cpu.c)
13/36 Checking commit 314c65c2a075 (target/mips: Turn printfpr() macro into a proper function)
14/36 Checking commit c7bee2a13367 (target/mips: Declare mips_env_set_pc() inlined in "internal.h")
15/36 Checking commit dcf190f75f5a (target/mips: Merge do_translate_address into cpu_mips_translate_address)
16/36 Checking commit 671a7a373cfb (target/mips: Extract load/store helpers to ldst_helper.c)
Use of uninitialized value $acpi_testexpected in string eq at ./scripts/checkpatch.pl line 1529.
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#18: 
new file mode 100644

total: 0 errors, 1 warnings, 560 lines checked

Patch 16/36 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/36 Checking commit fe7a887c1fc2 (meson: Introduce meson_user_arch source set for arch-specific user-mode)
18/36 Checking commit 6176008134b4 (target/mips: Introduce tcg-internal.h for TCG specific declarations)
Use of uninitialized value $acpi_testexpected in string eq at ./scripts/checkpatch.pl line 1529.
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54: 
new file mode 100644

total: 0 errors, 1 warnings, 45 lines checked

Patch 18/36 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
19/36 Checking commit 7ba1be7dc69b (target/mips: Add simple user-mode mips_cpu_do_interrupt())
Use of uninitialized value $acpi_testexpected in string eq at ./scripts/checkpatch.pl line 1529.
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 19/36 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
20/36 Checking commit 1b9571f49d0b (target/mips: Add simple user-mode mips_cpu_tlb_fill())
21/36 Checking commit da27055e390e (target/mips: Move cpu_signal_handler definition around)
22/36 Checking commit 6f7158fb5b79 (target/mips: Move sysemu specific files under sysemu/ subfolder)
23/36 Checking commit 220dc20d0cb5 (target/mips: Move physical addressing code to sysemu/physaddr.c)
Use of uninitialized value $acpi_testexpected in string eq at ./scripts/checkpatch.pl line 1529.
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#76: 
new file mode 100644

total: 0 errors, 1 warnings, 573 lines checked

Patch 23/36 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
24/36 Checking commit e43ecf43e80e (target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG)
25/36 Checking commit 249d35118313 (target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#20: 
 target/mips/{ => tcg/sysemu}/cp0_helper.c |   0

total: 0 errors, 1 warnings, 371 lines checked

Patch 25/36 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/36 Checking commit 0584792b0566 (target/mips: Restrict mmu_init() to TCG)
27/36 Checking commit f13b3b009608 (target/mips: Move tlb_helper.c to tcg/sysemu/)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#24: 
 target/mips/{ => tcg/sysemu}/tlb_helper.c | 3 ---

total: 0 errors, 1 warnings, 59 lines checked

Patch 27/36 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
28/36 Checking commit d53f2a0f8eca (target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope)
29/36 Checking commit b0da23728fcb (target/mips: Move Special opcodes to tcg/sysemu/special_helper.c)
Use of uninitialized value $acpi_testexpected in string eq at ./scripts/checkpatch.pl line 1529.
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#194: 
new file mode 100644

total: 0 errors, 1 warnings, 311 lines checked

Patch 29/36 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
30/36 Checking commit 4efe8dc3e58e (target/mips: Move helper_cache() to tcg/sysemu/special_helper.c)
31/36 Checking commit 4fc84f299625 (target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c)
ERROR: space prohibited after that '&' (ctx:WxW)
#456: FILE: target/mips/tcg/sysemu/tlb_helper.c:71:
+    tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
                                                  ^

ERROR: space prohibited after that '&' (ctx:WxW)
#457: FILE: target/mips/tcg/sysemu/tlb_helper.c:72:
+    tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
                                                  ^

ERROR: space prohibited after that '&' (ctx:WxW)
#462: FILE: target/mips/tcg/sysemu/tlb_helper.c:77:
+    tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
                                                  ^

ERROR: space prohibited after that '&' (ctx:WxW)
#463: FILE: target/mips/tcg/sysemu/tlb_helper.c:78:
+    tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
                                                  ^

total: 4 errors, 0 warnings, 720 lines checked

Patch 31/36 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

32/36 Checking commit 46d44acd812d (target/mips: Move exception management code to exception.c)
Use of uninitialized value $acpi_testexpected in string eq at ./scripts/checkpatch.pl line 1529.
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#158: 
new file mode 100644

total: 0 errors, 1 warnings, 402 lines checked

Patch 32/36 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
33/36 Checking commit 5807053b9689 (target/mips: Move CP0 helpers to sysemu/cp0.c)
Use of uninitialized value $acpi_testexpected in string eq at ./scripts/checkpatch.pl line 1529.
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#161: 
new file mode 100644

ERROR: space prohibited after that '&' (ctx:WxW)
#205: FILE: target/mips/sysemu/cp0.c:40:
+    cu = (v >> CP0St_CU0) & 0xf;
                           ^

ERROR: space prohibited after that '&' (ctx:WxW)
#206: FILE: target/mips/sysemu/cp0.c:41:
+    mx = (v >> CP0St_MX) & 0x1;
                          ^

ERROR: space prohibited after that '&' (ctx:WxW)
#207: FILE: target/mips/sysemu/cp0.c:42:
+    ksu = (v >> CP0St_KSU) & 0x3;
                            ^

ERROR: space prohibited after that '&' (ctx:WxW)
#234: FILE: target/mips/sysemu/cp0.c:69:
+        uint32_t ksux = (1 << CP0St_KX) & val;
                                         ^

ERROR: space prohibited after that '&' (ctx:WxW)
#242: FILE: target/mips/sysemu/cp0.c:77:
+        mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
                                                        ^

ERROR: space prohibited after that '&' (ctx:WxW)
#269: FILE: target/mips/sysemu/cp0.c:104:
+        mask &= ~((1 << CP0Ca_WP) & val);
                                   ^

ERROR: space prohibited after that '&' (ctx:WxW)
#274: FILE: target/mips/sysemu/cp0.c:109:
+    if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
                                ^

ERROR: space prohibited after that '&' (ctx:WxW)
#284: FILE: target/mips/sysemu/cp0.c:119:
+        if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
                                    ^

total: 8 errors, 1 warnings, 257 lines checked

Patch 33/36 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

34/36 Checking commit a8a91c9b2ed9 (target/mips: Move TCG source files under tcg/ sub directory)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#24: 
 target/mips/{ => tcg}/dsp_helper.c           |  0

total: 0 errors, 1 warnings, 144 lines checked

Patch 34/36 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
35/36 Checking commit 0a555e66b02e (hw/mips: Restrict non-virtualized machines to TCG)
36/36 Checking commit 153fae25b40a (gitlab-ci: Add KVM mips64el cross-build jobs)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20210502161538.534038-1-f4bug@amsat.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
Re: [PULL 00/36] MIPS patches for 2021-05-02
Posted by Peter Maydell 2 years, 12 months ago
On Sun, 2 May 2021 at 17:20, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> The following changes since commit 53c5433e84e8935abed8e91d4a2eb813168a0ecf:
>
>   Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210501' into staging (2021-05-02 12:02:46 +0100)
>
> are available in the Git repository at:
>
>   https://github.com/philmd/qemu.git tags/mips-20210502
>
> for you to fetch changes up to 1c13514449439b5ff1f746ed0bf73b298da39cf0:
>
>   gitlab-ci: Add KVM mips64el cross-build jobs (2021-05-02 16:49:35 +0200)
>
> ----------------------------------------------------------------
> MIPS patches queue
>
> - Fix CACHEE opcode
> - Add missing CP0 checks to nanoMIPS RDPGPR / WRPGPR opcodes
> - Remove isa_get_irq() call in PIIX4 south bridge
> - Add various missing fields to the MIPS CPU migration vmstate
> - Lot of code moved around to allow TCG or KVM only builds
> - Restrict non-virtualized machines to TCG
> - Add KVM mips64el cross-build jobs to gitlab-ci
>
>
> scripts/checkpatch.pl false positive in patch 31
> "Move TLB management helpers to tcg/sysemu/tlb_helper.c":
>
> 4 checkpatch errors:
>
>   ERROR: space prohibited after that '&' (ctx:WxW)
>   #414: FILE: target/mips/tcg/sysemu/tlb_helper.c:71:
>   +    tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
>                                                     ^
>
>   ERROR: space prohibited after that '&' (ctx:WxW)
>   #415: FILE: target/mips/tcg/sysemu/tlb_helper.c:72:
>   +    tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
>                                                     ^
>
>   ERROR: space prohibited after that '&' (ctx:WxW)
>   #420: FILE: target/mips/tcg/sysemu/tlb_helper.c:77:
>   +    tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
>                                                     ^
>
>   ERROR: space prohibited after that '&' (ctx:WxW)
>   #421: FILE: target/mips/tcg/sysemu/tlb_helper.c:78:
>   +    tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
>                                                     ^
>
>   total: 4 errors, 0 warnings, 688 lines checked

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.1
for any user-visible changes.

-- PMM