From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) client-ip=209.85.128.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619972148; cv=none; d=zohomail.com; s=zohoarc; b=RC0DdYR6wq9biDXd/aicOI1v/P+1vCgCtN1KSQYJejLVzSL12wXQ7alYp0xb++oLB3G21zR/T63g6LDLq7q0QT5vZ0Tx0EpcTIktPjPlyHiMo9HxCIKdSgoKCstmKlwbNzbQY40kXUQBHgNsf95nzac1t/CgC5G5UEfdgrOJkdM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972148; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Ea5zmyJlxs7XTwwtJD6w8UxqiI46mAH5yHMSAEvlRDk=; b=V0+I590E7RhgsAuKlIi46d0+6cenQvcpFoDORLhKJk2EUP6XD0LFIOKsBHHUIUZGAEd2hNTYzyjLW5Oeaq8ngFRKd6LxE+IsNaiSR57ICEa1ctqoRnl8tY7wT4CUEaoC9aoUVZwWrZFnq0oyWnABD6WCfd3lCqQ9KNXKdF2rIRk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) by mx.zohomail.com with SMTPS id 1619972148264469.28362333095845; Sun, 2 May 2021 09:15:48 -0700 (PDT) Received: by mail-wm1-f44.google.com with SMTP id b19-20020a05600c06d3b029014258a636e8so2116715wmn.2 for ; Sun, 02 May 2021 09:15:47 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (anancy-651-1-208-144.w109-217.abo.wanadoo.fr. [109.217.237.144]) by smtp.gmail.com with ESMTPSA id l14sm9466032wrv.94.2021.05.02.09.15.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:15:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ea5zmyJlxs7XTwwtJD6w8UxqiI46mAH5yHMSAEvlRDk=; b=ht5k1QUxNyFxCU5RH6mBSnZql5VIl+hgc+112QBjuEYF+kjuSCB5eiA9QCw5CLBiep drTwzkyvM1zEiha/SbCTv1icpItZJUEBN8ufUkCQr4VuOhrnjTodIvmqL2AufWhzK4E1 u8ldpFvepMmeHjxhoExXjiuVUcxts3aNzUWawSPhX4QkQ05L2jH121vlMY7iE7tccyOo WEXDIhEmJ4wuGcWlHnR/OBqZxp+HKxajJHOWDlIIuz3BqZHyWwkd+t50hKYHruTonFsY MOuuAq6QId1AjaU9cZOS9JtxpyBr3K4WflgMW8hNFRH3GT7FBCj4KcJIHJZESwhcJoqy IAQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Ea5zmyJlxs7XTwwtJD6w8UxqiI46mAH5yHMSAEvlRDk=; b=i2leA9KNlZZDKa8Jt2s9FmT+cTHtPXm4oUZ35k7ny9Y5o3SaVD2dUenW0cFYp7DcoL sKO2HNo3ljYGHB0uTA7ea90LC3F3zoLqY7uT4uh/x//Y3roICuAmHEh5q5paQVHnPKTY yWP4uXHZ3KhIsyeRLI0Tjc85IRpLrHCwYk0AC7cIfkqNzEBof2l0poyj1+CIZtQcrrNX t96R2OBV1ozwPWq7ZGEBd11/gVtCqyTC9vem1Lhql0ULrs6R3lkuB3gE6hqREc7JdnRa VIIBfsLhEqZLowT8Zk/fHPFAUEU7Ezs6SJq4ERAkBk1ecbulT3JQgpJ1/WUII/mE0da1 VrdQ== X-Gm-Message-State: AOAM530pz0b1Sj/otLqOHEhxD7m1bAeVPog/UQTKVbpcm7L/OhhxD1hl V0Oddx7GEXGR57c+OdBVXy4= X-Google-Smtp-Source: ABdhPJzHuYqQQK/4jkf4sya0mMKrZ9pryU2xNMY56EyyyNbeumFdZWQEkjj6Kk9s5h2ZBu4orkDSNg== X-Received: by 2002:a1c:65c2:: with SMTP id z185mr28152433wmb.2.1619972146514; Sun, 02 May 2021 09:15:46 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Herv=C3=A9=20Poussineau?= Subject: [PULL 01/36] hw/isa/piix4: Use qdev_get_gpio_in_named() to get ISA IRQ Date: Sun, 2 May 2021 18:15:03 +0200 Message-Id: <20210502161538.534038-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Since commit 078778c5a55 ("piix4: Add an i8259 Interrupt Controller") the TYPE_PIIX4_PCI_DEVICE exposes the ISA input IRQs as "isa" alias. Use this alias to get IRQ for the power management PCI function. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210324182902.692419-1-f4bug@amsat.org> --- hw/isa/piix4.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index b3b6a4378a3..5ae3b4984d2 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -268,8 +268,9 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa= _bus, I2CBus **smbus) pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci"); if (smbus) { *smbus =3D piix4_pm_init(pci_bus, devfn + 3, 0x1100, - isa_get_irq(NULL, 9), NULL, 0, NULL); - } + qdev_get_gpio_in_named(dev, "isa", 9), + NULL, 0, NULL); + } =20 return dev; } --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) client-ip=209.85.128.47; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f47.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619972153; cv=none; d=zohomail.com; s=zohoarc; b=fLwV84csie2aJpa3M3PHYzRubkRVUU/mXt08NkBS6Myd8HHxH5aQq8UeOnN1oXL/VPExbMbc4iz3E3ccI3zl3CGArENqedsTZ2xP2Quzq+OSm5HcNF4lesD6AxFfLkkC/2k8mei/PnTLo//p7mp2KF8D1Ewc5HS8MiC1f2gdZXI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972153; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=P4j2gbE04oS0h94Kjd7cj3338C2131+7etp/nt6YQrQ=; b=ahfepJ/jQsY780QjJe/6ztvOsjYszD5Ew1QjR5hJ2Eu1CToe9Rp2u6ufIWe9wMiagSR/3d6V1evR7kiEF7KGfyvQSofzRmrWZoplP+6IJMOesvoU6ZSlaLWoaLxtnWCWkuUipvS8RHx4Sa2ZYcnVDOwdsUBFO/tpDQqPTwzdKcw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) by mx.zohomail.com with SMTPS id 1619972153545372.79229332777857; Sun, 2 May 2021 09:15:53 -0700 (PDT) Received: by mail-wm1-f47.google.com with SMTP id s5-20020a7bc0c50000b0290147d0c21c51so2114519wmh.4 for ; Sun, 02 May 2021 09:15:52 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (anancy-651-1-208-144.w109-217.abo.wanadoo.fr. [109.217.237.144]) by smtp.gmail.com with ESMTPSA id l5sm8959057wmh.0.2021.05.02.09.15.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:15:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P4j2gbE04oS0h94Kjd7cj3338C2131+7etp/nt6YQrQ=; b=c6reylfW4gomBRCjmTwnA8+dxcYEh/M6L+TJ40aIa9SWwhdhRchsBqGARcfKfPGvP1 kyFks3kUm4AKrnJxqJua8LcmeyNsEnnfQJH5xNIPgbNObx0iDZbmzr1lfwg+ly8Bnqar sGBoo9ts5fSv4KMzReRhQFDVesU9nnC+sYcUnqC0y9tnsz6Bs4SbXlSKHS1YXm0zMNcX 2Q8gpJpcm0u12rUV2T15/dJaQIdTnuwO8mNI4vyT4hB8KJjX7y4FyQdXaiaeXnwjy0Ef m2h8Ig6mPohoTnzcX1WZHdKYD5uQlzzAVdaKqFFBBq7/pYsPXDw/n/rNU88md660LtSz r22A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=P4j2gbE04oS0h94Kjd7cj3338C2131+7etp/nt6YQrQ=; b=h5oRzCVPm0XtVxR+bWkmHCJr0rUSS9OBPtib3zCUh87mcqKa5Sghb1FrPhROD89hqd QVyyTgKjI3R1buo18yO9C884He215HxroXXmfEJk7KtLlXbNHI31iMgPZiXJ3Imf/wx0 jUwJEg5bc3etT7msTUhsOJyfxmu97/6gh/fwB3Se/f1iPD0GutqxEng2HTqUH5Q1KVZe J897a7eNnzcmeIPRY9pkI2TsOdoY0ZCSkNyzEnqY6rVnL3ywXapsz2aKxmy+y/PO/4tC OAPQm2vZbPOwDYgQ0OdP9kpGT7TrYKcqu115e6Rbr70GeZQtokncMx0C5pcinaCgVqrI XkuQ== X-Gm-Message-State: AOAM530wWB/FzcgzbJaDOHgSSRL3zGLOa/rI73YcUgCxdjR2IuV0SHl9 b4ZBZ6jRCV7NTn3gB0EM4c2pCpKoihDPL+ur X-Google-Smtp-Source: ABdhPJwiNs9jXlEaXqfMC4+nvvay3Oi/sGUmkTriPiraFqLBkq7Cg+UKielvdRa81zHVtL6JM0omYw== X-Received: by 2002:a1c:7419:: with SMTP id p25mr8923380wmc.79.1619972151830; Sun, 02 May 2021 09:15:51 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 02/36] target/mips: Fix CACHEE opcode (CACHE using EVA addressing) Date: Sun, 2 May 2021 18:15:04 +0200 Message-Id: <20210502161538.534038-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The CACHEE opcode "requires CP0 privilege". The pseudocode checks in the ISA manual is: if is_eva and not C0.Config5.EVA: raise exception('RI') if not IsCoprocessor0Enabled(): raise coprocessor_exception(0) Add the missing checks. Inspired-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210420175426.1875746-1-f4bug@amsat.org> --- target/mips/translate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 71fa5ec1973..5dad75cdf37 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20957,6 +20957,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) gen_ld(ctx, OPC_LHUE, rt, rs, s); break; case NM_CACHEE: + check_eva(ctx); + check_cp0_enabled(ctx); check_nms_dl_il_sl_tl_l2c(ctx); gen_cache_operation(ctx, rt, rs, s); break; @@ -24530,11 +24532,11 @@ static void decode_opc_special3(CPUMIPSState *env= , DisasContext *ctx) gen_st_cond(ctx, rt, rs, imm, MO_TESL, true); return; case OPC_CACHEE: + check_eva(ctx); check_cp0_enabled(ctx); if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { gen_cache_operation(ctx, rt, rs, imm); } - /* Treat as NOP. */ return; case OPC_PREFE: check_cp0_enabled(ctx); --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) client-ip=209.85.221.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619972158; cv=none; d=zohomail.com; s=zohoarc; b=czW8nfienY0F4KB1n3mkREM+5zl0wDetLoDsJ7lK3NAqSezJLXgaFH3TA2mveEyIVot5bAYuq4fUsYDfquOgxqdA3ya9j8HnK+NJT3yid+nyoKlct9VRkEwtTRzGVUXFoKEpXMnmCTouuz/KaxI7+t7vv8PA2zJvi8RJdv3xC9E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972158; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dvzaE+vmEj53OsiqB294gBuJPIp1EJ/XIul7LLbiwhk=; b=IWzIefw83hz/0JR5SWrj18yCO9OjQBkBlSiu/mVGmY3zVjbG9uNqF60yv/pnHovtOqUl3sgml9EmkrZC4dCkq4Ld5GkBbWGdBkwDqjC1EMCAJLRyxs48iDEu1xlyoEI/THC02aareWTyEFDSgrVNEupkmDE8X2IJFHiJPqn9jok= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) by mx.zohomail.com with SMTPS id 1619972158413295.42511964948665; Sun, 2 May 2021 09:15:58 -0700 (PDT) Received: by mail-wr1-f53.google.com with SMTP id a4so3109036wrr.2 for ; Sun, 02 May 2021 09:15:57 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (anancy-651-1-208-144.w109-217.abo.wanadoo.fr. [109.217.237.144]) by smtp.gmail.com with ESMTPSA id o18sm10347944wmq.20.2021.05.02.09.15.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:15:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dvzaE+vmEj53OsiqB294gBuJPIp1EJ/XIul7LLbiwhk=; b=lJa5GjW/x+WJ8kxmGoCJZ75Yp5rsNfN4NqD0T9QPoa6/+pQcIOF6CPdixFGDEZ2Vj/ 7E4uM/sfmpyYFDi0vMKIiRspas1UO3aGXIlVcE4dIJHkYmm7xrDGLEXnsIK3mVWT2RQI sZHbypRL2/Z3KrITJO5l6K4rbIVhSqNVkBbrXyAP1BPFI35ypXlzkPCuql95Fp8Gnvhf pGuCHcd4SLN8RGba+ambXWCduKKAR9hVRyLrZrWIcamaq+p8i5+dytYu1q3IF/ba6GTT vyABBTV3rwbsY4YjSzV1ght/MSETIlxL7D0C3UCcFcywqG+8Mypl1835+/9ZcY/AkEw+ qEkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=dvzaE+vmEj53OsiqB294gBuJPIp1EJ/XIul7LLbiwhk=; b=m7MtKHNxLkg+e63+iYISjP2hb6gZodrsExwsimwwWmVvZuWNobH8E+a6s0BlztZUpL v8/7XjXY2gtHB1RJJe/uV7Rm+EfKRygtJ0cG4XXAKIUCSbFHJzSg5iUO3yT3rcVwB3fV LsPZhG3oVyXRFbAp8G89FHxdePaZHdHZKNxS8f4i2sXNZv1meMfYaALpFUP2ECqaAuGl N3NJua6fNzoxZ2tFMWjuF7rBRVVl7Q+3hlGN5SQy9p2e9lcqlbaGSATpc6PSe/LIy5js ZuyW8XqKpuc2h4k4psdu6+0fZ1kExzpaFC1IYSmUW740eUz1kBLHoO46uNbG49+f21nr I0Dw== X-Gm-Message-State: AOAM532TTMiqnBx0qkiqS4qKlV95htJbyDdNGSsRXVlNt0RNt75dXWKE HQvcRRb98hSlRvWYRqq3tt4NXaoEy1wQlqze X-Google-Smtp-Source: ABdhPJxIjCSKNmL1i+TfinhA59mJgC31NGvSwimoqJ9uXE0qCBzK3IkeBe11NDCzm0gFQ8XgpVuQMQ== X-Received: by 2002:adf:f152:: with SMTP id y18mr19951431wro.77.1619972156737; Sun, 02 May 2021 09:15:56 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 03/36] target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes Date: Sun, 2 May 2021 18:15:05 +0200 Message-Id: <20210502161538.534038-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Per the nanoMIPS32 Instruction Set Technical Reference Manual, Revision 01.01, Chapter 3. "Instruction Definitions": The Read/Write Previous GPR opcodes "require CP0 privilege". Add the missing CP0 checks. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210421185007.2231855-1-f4bug@amsat.org> --- target/mips/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 5dad75cdf37..8a0a2197426 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -18969,9 +18969,11 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSSta= te *env, DisasContext *ctx) } break; case NM_RDPGPR: + check_cp0_enabled(ctx); gen_load_srsgpr(rs, rt); break; case NM_WRPGPR: + check_cp0_enabled(ctx); gen_store_srsgpr(rs, rt); break; case NM_WAIT: --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) client-ip=209.85.221.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619972163; cv=none; d=zohomail.com; s=zohoarc; b=nxhBChz9guK4l6l5zEiibYLrPkfQm2Kk2E5i33i3XGUBteZn3a5juj42tobpKcODfOYPTgzwLiYnz6pv3lCZ9sB4i8JMT1bMPmPwV65GHpM5f67rcWmNTMrAOL2f12zey2wi1JF2TpyDXRE5R+xWVKr1aCEoCtso3ZHOeWHUVVQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972163; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PGJF5dKqSB+KKQYLEJgSlRUAv3AoaIgySDoRGS9mRQ8=; b=bcCQsbquN5ltgiWfE/PYf/TX2UcE75lUhDCAiWkIQSQUkfe3SmkeCL8YoB9hff52fJxa4pU1o2lkurE1W1RKtqhLt0rRYFVRLfkazaZzaYqbmlym1uRdDQrf7R4OgDc78JF88zUwin6o8mFBGlLkZhr5OD57gOE05kGJ/69vCJs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) by mx.zohomail.com with SMTPS id 1619972163303922.0119199367128; Sun, 2 May 2021 09:16:03 -0700 (PDT) Received: by mail-wr1-f53.google.com with SMTP id v12so3090947wrq.6 for ; Sun, 02 May 2021 09:16:02 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (anancy-651-1-208-144.w109-217.abo.wanadoo.fr. [109.217.237.144]) by smtp.gmail.com with ESMTPSA id z7sm9508056wrl.11.2021.05.02.09.16.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:16:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PGJF5dKqSB+KKQYLEJgSlRUAv3AoaIgySDoRGS9mRQ8=; b=ZBhkZ3avbPBD+unZdLOSvLrunbCtylkj/8CXloDNx5unBLjNGsgSKbKrdb53V9H4I/ nzHfHhCa5cuF8GloXGnq+iYKxqJCh+YvP7nJsJTrKUoPTNB11Li/JNQWXfNkWg7Ife1i JcH6Rh+DUckjOUoBsYPO7c/pF4cACgGAMx69Ri+csGNgqFGGTdzAQo4Wuv0lvFrY+kMM 9eQuno/uAs66f/0aailBzEbqrj+JF9Rq8bf/EksakdQ9tGD3dpQr8e5hqLNm/pH6saxe 9q6RJC0Xw/bYAoE96vSu6D+rgezy+TAr3blArAhugmeMXS6n/YJIIgep2d5bI9rufWMh VovQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=PGJF5dKqSB+KKQYLEJgSlRUAv3AoaIgySDoRGS9mRQ8=; b=uNZPcQKalQMNFsAlwWeN2l88F+Y9dJfOntTRoymTROwGrRnj5ZWD9ZYjTOJxFg5nti WbhONU04kvH+9lCLeV4GsYOwXX7sBZdViz/EvhyrBHSLpKRXnLjuxZqt7+b0Ma0kCo8z rksQ3YBnD0WuvIP/YzouDpcX9SeopyKksyLV+9HBxjozJDXVXM8MRdZjH14KGNzSHwHO 5fnOWcyDb+6lTk+1teFffnyhE4gfpYw+ywDuQkwohOlBiiT07cnMMMD1BxZR+wPSawGZ aouuFiuOYhFRLaUlpCNHR2g+kDPB2IP4n/RTxTBQmGQszdsk+zCW3xPUteKtx+sDhJ8V kEaQ== X-Gm-Message-State: AOAM533DKpHmM+CtQIIt8JshlGbj9Oux3htpV2ccH1NDW7WFkQ7QYjEY RRow4tzQGYRbXm7C+ELUOSE= X-Google-Smtp-Source: ABdhPJyiTY1NbMlgVwF4AhvRe47z8Ilms3XXJUnsGuJKHpPfOMUHectDG2xVDtWJknlySV1Vpt56Lg== X-Received: by 2002:a05:6000:180a:: with SMTP id m10mr19852327wrh.215.1619972161600; Sun, 02 May 2021 09:16:01 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 04/36] target/mips: Remove spurious LOG_UNIMP of MTHC0 opcode Date: Sun, 2 May 2021 18:15:06 +0200 Message-Id: <20210502161538.534038-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) When running with '-d unimp' all MTHC0 opcode executed are logged as unimplemented... Add the proper 'return' statement missed from commit 5204ea79ea7. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210422081055.2349216-1-f4bug@amsat.org> --- target/mips/translate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 8a0a2197426..3230b2bca3b 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -5945,6 +5945,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; } trace_mips_translate_c0("mthc0", register_name, reg, sel); + return; =20 cp0_unimplemented: qemu_log_mask(LOG_UNIMP, "mthc0 %s (reg %d sel %d)\n", --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) client-ip=209.85.128.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619972168; cv=none; d=zohomail.com; s=zohoarc; b=j/7TRhMxALb5QqgtpWdIV33JfuUXKUFE7lBTtXMb6zZTt49mlCI6sQ3c8vQYXFkiO/3SafgITWTiTyjp3HEm0sjGcChSMw2o9bEqqeCQhJSciUnEQiMSmn6LiCruOg/3ABBCWd/t02SjISLaJq/FZz9EieF1uk6Vn/0RI81cx+o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972168; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0RPwNXgnYoOFEB/Syw7iOsyR0ocLEZVRgNHH2ttrTpk=; b=deYIRGFr6IwwErvBbs0wpnRnEoTB/U1ZPhAfgwStLRjB6ezzZ+bMymOKunOSiviuPbTgES5ZBuoGPxi5ErCzf3lO6DqLxR32Vt5/2UFKQc1Pwgup28oMGE9uyR1DkqiU0Gnk0YETBR9AQJiPnFEG7wrkih1LeT6j9iWsziphegk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) by mx.zohomail.com with SMTPS id 1619972168278418.0362498275672; Sun, 2 May 2021 09:16:08 -0700 (PDT) Received: by mail-wm1-f51.google.com with SMTP id k128so1915720wmk.4 for ; Sun, 02 May 2021 09:16:07 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (anancy-651-1-208-144.w109-217.abo.wanadoo.fr. [109.217.237.144]) by smtp.gmail.com with ESMTPSA id v18sm10898604wro.18.2021.05.02.09.16.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:16:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0RPwNXgnYoOFEB/Syw7iOsyR0ocLEZVRgNHH2ttrTpk=; b=NEinPNeqgvyvdCVcS0of2RnYaQeOxPBrUYQW796BCL4diI+aWNWjltWc/AzIZkJjkx 9tI6T+VheF5A1vXyuOqPKr/8HtgRR0fhjl+IybLYW8tJsBq7KxJL18pLf6ao6DWQN34/ HloPtp9R1m5ODqwGWGjEimXileUgff+a9blZXsVY0heiyM6ziDFY5CEb6SONtL0V9zAa Qv1RO1+Xfn9HB7jXLP6S4bG80ZxkMvAozG3IqViVtDF/8Mb4QL/6lnZPr1Cv+GP44GiR z6eEjsA+sNs08e97A5kTTubCLrPEH74yKRIZrBcXYmOdLhdQM/3FjVVppaUkhur1W4Ej ta5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=0RPwNXgnYoOFEB/Syw7iOsyR0ocLEZVRgNHH2ttrTpk=; b=hhABMdK/pX3snUxfXSLlSkYDj/l1vqwULQup/ZE6IVTG0ruCwKF49yHmY8fup79W8S C8JV60pw5gxQJrpocBPxyyR/EzJuslASTYPtjoG9p+ZASYDAxVl10MzVWXhFISl22jAm PWrhENq93lxaD5jZFUm8qg8YZOb+aji8X0lAWIuLZ3xTytu4Dok6Vgyf5mOzOd8dbDH8 ctrLemNcDaXiS9qdPSvoWLl1dZgCChhuw5miO9rYwC2AwK/gdY6I+QOTLzkX+qi66wzk 3FZuCkvRfhlMD57gMsAXLzLA8yWN8vGMY7zPPlXLoWTkW79MdxaN4M6G+ajyClstxTAC 9zlQ== X-Gm-Message-State: AOAM533DJ3GKLyrXTIHyDxCS3cTq43LHFLTqUlxPuxjDyBRfR+pygWcb QnJx7PZr9FAT+dhzS6VbMG4= X-Google-Smtp-Source: ABdhPJytgoSdM47nI4MO9m9nIqmPLznZyPLFBwW6iRg+X8RytBK9alAb/EmSUj+POML1x9bCKAHmsw== X-Received: by 2002:a1c:9897:: with SMTP id a145mr19387038wme.9.1619972166576; Sun, 02 May 2021 09:16:06 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 05/36] target/mips: Migrate missing CPU fields Date: Sun, 2 May 2021 18:15:07 +0200 Message-Id: <20210502161538.534038-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Add various missing fields to the CPU migration vmstate: - CP0_VPControl & CP0_GlobalNumber (01bc435b44b 2016-02-03) - CMGCRBase (c870e3f52ca 2016-03-15) - CP0_ErrCtl (0d74a222c27 2016-03-25) - MXU GPR[] & CR (eb5559f67dc 2018-10-18) - R5900 128-bit upper half (a168a796e1c 2019-01-17) This is a migration break. Fixes: 01bc435b44b ("target-mips: implement R6 multi-threading") Fixes: c870e3f52ca ("target-mips: add CMGCRBase register") Fixes: 0d74a222c27 ("target-mips: make ITC Configuration Tags accessible to= the CPU") Fixes: eb5559f67dc ("target/mips: Introduce MXU registers") Fixes: a168a796e1c ("target/mips: Introduce 32 R5900 multimedia registers") Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Richard Henderson Message-Id: <20210423220044.3004195-1-f4bug@amsat.org> --- target/mips/machine.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/target/mips/machine.c b/target/mips/machine.c index b5fda6a2786..80d37f9c2fc 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -81,6 +81,9 @@ const VMStateDescription vmstate_inactive_fpu =3D { =20 static VMStateField vmstate_tc_fields[] =3D { VMSTATE_UINTTL_ARRAY(gpr, TCState, 32), +#if defined(TARGET_MIPS64) + VMSTATE_UINT64_ARRAY(gpr_hi, TCState, 32), +#endif /* TARGET_MIPS64 */ VMSTATE_UINTTL(PC, TCState), VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC), VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC), @@ -95,20 +98,22 @@ static VMStateField vmstate_tc_fields[] =3D { VMSTATE_INT32(CP0_Debug_tcstatus, TCState), VMSTATE_UINTTL(CP0_UserLocal, TCState), VMSTATE_INT32(msacsr, TCState), + VMSTATE_UINTTL_ARRAY(mxu_gpr, TCState, NUMBER_OF_MXU_REGISTERS - 1), + VMSTATE_UINTTL(mxu_cr, TCState), VMSTATE_END_OF_LIST() }; =20 const VMStateDescription vmstate_tc =3D { .name =3D "cpu/tc", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .fields =3D vmstate_tc_fields }; =20 const VMStateDescription vmstate_inactive_tc =3D { .name =3D "cpu/inactive_tc", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .fields =3D vmstate_tc_fields }; =20 @@ -213,8 +218,8 @@ const VMStateDescription vmstate_tlb =3D { =20 const VMStateDescription vmstate_mips_cpu =3D { .name =3D "cpu", - .version_id =3D 20, - .minimum_version_id =3D 20, + .version_id =3D 21, + .minimum_version_id =3D 21, .post_load =3D cpu_post_load, .fields =3D (VMStateField[]) { /* Active TC */ @@ -241,6 +246,7 @@ const VMStateDescription vmstate_mips_cpu =3D { =20 /* Remaining CP0 registers */ VMSTATE_INT32(env.CP0_Index, MIPSCPU), + VMSTATE_INT32(env.CP0_VPControl, MIPSCPU), VMSTATE_INT32(env.CP0_Random, MIPSCPU), VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU), VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU), @@ -251,6 +257,7 @@ const VMStateDescription vmstate_mips_cpu =3D { VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU), VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU), VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU), + VMSTATE_INT32(env.CP0_GlobalNumber, MIPSCPU), VMSTATE_UINTTL(env.CP0_Context, MIPSCPU), VMSTATE_INT32(env.CP0_MemoryMapID, MIPSCPU), VMSTATE_INT32(env.CP0_PageMask, MIPSCPU), @@ -286,6 +293,7 @@ const VMStateDescription vmstate_mips_cpu =3D { VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU), VMSTATE_INT32(env.CP0_PRid, MIPSCPU), VMSTATE_UINTTL(env.CP0_EBase, MIPSCPU), + VMSTATE_UINTTL(env.CP0_CMGCRBase, MIPSCPU), VMSTATE_INT32(env.CP0_Config0, MIPSCPU), VMSTATE_INT32(env.CP0_Config1, MIPSCPU), VMSTATE_INT32(env.CP0_Config2, MIPSCPU), @@ -305,6 +313,7 @@ const VMStateDescription vmstate_mips_cpu =3D { VMSTATE_INT32(env.CP0_Debug, MIPSCPU), VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU), VMSTATE_INT32(env.CP0_Performance0, MIPSCPU), + VMSTATE_INT32(env.CP0_ErrCtl, MIPSCPU), VMSTATE_UINT64(env.CP0_TagLo, MIPSCPU), VMSTATE_INT32(env.CP0_DataLo, MIPSCPU), VMSTATE_INT32(env.CP0_TagHi, MIPSCPU), --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) client-ip=209.85.221.42; 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[109.217.237.144]) by smtp.gmail.com with ESMTPSA id z15sm9176134wrv.39.2021.05.02.09.16.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:16:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6i1WU64wR8pkFjcHjE2+dlBuW0U+Z2Gby3NQK6F4B3o=; b=pgtl+R/YycldNgLVkoGUllDsvpg1cCILyYRyQe/VAZWHlptNA/eDHBQCi68FpcJXtH pNu9cd8jhXJDN4iNMLuIU3wo/htNLjN8EFVIc7ts8PH7tclQswHTMyFx+LlrNQ4VFVA/ czxCRJaupuMa75ftmWuPDkDrlvb/kd0w+fXttqjVKXsrEec0BxGG/hJGx8vnuIuLu7Oy 5a+dDwVv6gHHyJDWICf4xHJr1X9+ydEyYmxnCzydhhukUS0BCLb3Sty4Cnm+PjiGjgl/ 5Azms1zlZ7bWKI2/o8JA7hiSVFjEOoyjbbj7r7r0DdElFsGCwmxu00ytBs2ygelKE2lT fo8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=6i1WU64wR8pkFjcHjE2+dlBuW0U+Z2Gby3NQK6F4B3o=; b=es/F+Dzmf7m1MICBYtjpwu+yD3yfv2RWk0gWBOhcW5Y00LZYp6ZR9Eh8qarDtGCmSn USXMKZOd2p+Sw7u0HaNMAHik+zGZAB854GGZmf3tG50Rml3WapQBU4FLN12IwaVLbdpu xl4w9EPyIBdoqfDHZ0PLbKDGzg2AFXBrDeAV4PTGpYy9ify6TR2sIcwzsOV9m7HjQYoE aHEqx5JZUdeX9lHUUtDo9GHDvTk5xolwESOysnhpNvIkB6Rkatp4YVS825jXQy6o/gW1 fPTxE5fGXltt/3nM/xjRqVMNnyJTkRq0q8KL5f3XiNKKF96t65Isb+tMAruAZOLZGsY+ RncQ== X-Gm-Message-State: AOAM530//Sh/y6ZqreXwrKaFMK7A8/XbcFRAkYtgmOwuRR4sLOelQ6I4 NAmi8a9aG/40p8KcztU2mSw= X-Google-Smtp-Source: ABdhPJzWwkz+hd7uEh9zbZCablUH3Dun8zcmdKBJNW9dPx+3kmpAaZBsqd8Kpjx7OCeASK34jDckLw== X-Received: by 2002:adf:a119:: with SMTP id o25mr20234031wro.61.1619972171607; Sun, 02 May 2021 09:16:11 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 06/36] target/mips: Make check_cp0_enabled() return a boolean Date: Sun, 2 May 2021 18:15:08 +0200 Message-Id: <20210502161538.534038-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) To avoid callers to emit dead code if check_cp0_enabled() raise an exception, let it return a boolean value, whether CP0 is enabled or not. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210420193453.1913810-4-f4bug@amsat.org> --- target/mips/translate.h | 7 ++++++- target/mips/translate.c | 4 +++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index 2b3c7a69ec6..61442590340 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -120,7 +120,12 @@ void gen_reserved_instruction(DisasContext *ctx); =20 void check_insn(DisasContext *ctx, uint64_t flags); void check_mips_64(DisasContext *ctx); -void check_cp0_enabled(DisasContext *ctx); +/** + * check_cp0_enabled: + * Return %true if CP0 is enabled, otherwise return %false + * and emit a 'coprocessor unusable' exception. + */ +bool check_cp0_enabled(DisasContext *ctx); void check_cp1_enabled(DisasContext *ctx); void check_cp1_64bitmode(DisasContext *ctx); void check_cp1_registers(DisasContext *ctx, int regs); diff --git a/target/mips/translate.c b/target/mips/translate.c index 3230b2bca3b..0e90d8cace6 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1572,11 +1572,13 @@ void gen_move_high32(TCGv ret, TCGv_i64 arg) #endif } =20 -void check_cp0_enabled(DisasContext *ctx) +bool check_cp0_enabled(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { generate_exception_end(ctx, EXCP_CpU); + return false; } + return true; } =20 void check_cp1_enabled(DisasContext *ctx) --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.48 as permitted sender) client-ip=209.85.128.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619972178; cv=none; d=zohomail.com; s=zohoarc; b=lEFyQqaJTf3OmLT4tpvzasAoAiVODHjtgzStaqIV8CZaL76GHFc5ESAZVYEIiCKPZdEoj30ltaxStdOJ2wOh/UA1wXFIdSjlMLBKofYkSsZgJ7KA7OYA9tY9sFj0u7zgVjDqsj4TUet0VVlIpViuw2vwcuzDCDrzzx/b8y1AxT4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972178; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pGVpj51cW5V28vRCX7GintOUgmx2bc45xybHGDvB0WI=; b=ljmFEvtutYgLe5Cf/N2wz/wwfj1jSne9Qr+JesYGdu9BCirdV0WUNVylXrFj0vJqFoAwU5mPkzcjbMiDEk5wyyhowHaXMGUPcoZSbkxtp3NpFi7vT8TPMRD9HXWPcHem34yyWZuQfaNcDDmC6Bs845vAKpEq6v9spp3TZ0D0B38= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) by mx.zohomail.com with SMTPS id 1619972178504866.6977705717524; Sun, 2 May 2021 09:16:18 -0700 (PDT) Received: by mail-wm1-f48.google.com with SMTP id j3-20020a05600c4843b02901484662c4ebso2726884wmo.0 for ; Sun, 02 May 2021 09:16:17 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (anancy-651-1-208-144.w109-217.abo.wanadoo.fr. [109.217.237.144]) by smtp.gmail.com with ESMTPSA id l5sm8960057wmh.0.2021.05.02.09.16.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:16:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pGVpj51cW5V28vRCX7GintOUgmx2bc45xybHGDvB0WI=; b=LW3cXiFIoM7DuVzxWouIwiHV78U1YdhWOWrxx6r0VpPrkPHe7c/TA1RjQPxwOZEwnr Vp80CFNqgIaSBMByLiG+kFH8iFmI207UNmfw84gFSaQXs1E/Liqse6dt7QKaOocYry7i pykQ0AT64GvKySABbRweYY9fdvc4zBMieHJiqwN6WEnloUKMqEOzUCuKZKlbx+OlmwL4 Qsy3anMrc0fVKSdf032zno81BKBR9FcC3kxy7eA6d8kmuuUA1a1/1pGFEXV+FqRH9y/O Z4KLoQCF5H7fuh6RQqw7n8ikbftMNpL3aL82KXw0k5zIWGRmJ1XcV3pksRHrulCt28z9 z12Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=pGVpj51cW5V28vRCX7GintOUgmx2bc45xybHGDvB0WI=; b=ZPg+ZNQb450kI7TVKhe9Sd5ic3XrMGJ533QvBhEdGNLJWr3bnYLHZ+GBr5JGy+FhC7 e+FFTKAQr1L42mxYsKk8Zfx62xcHQfk+ibtvjl51xTNRUw75b78oqqGapvOkfFKre6zN A/6e//AUQrRsmT9iBaSOr/ojvI+FbCvHirzmQCsyFHhSbK6ripWTatgcE+uCWJdBV9A3 XTYOzsX5IbRIAuAU7Z6gjlGFXiTjWeP+ENQ5kEQn1YHVIhyGZF0KwmzUODmXNWnAD7eE x8CIFQsrCnh5g9nxZluB+c64ff40RTo3njpDHNTLSC4K2RGrzEnClMTIMz+YV+rZl5CS QqfA== X-Gm-Message-State: AOAM532EUD4uBeVqfKPe1049ItB/AWGI6wPBQ1dZqwrEsB15jvwDhpNX /UsMUpV4EE9Ccw7JIW8YHQ4= X-Google-Smtp-Source: ABdhPJwdCUyFzssT0wgZqAc/+5ErYa0h/aBwhvxdk7c32XRksKHUxhGqmoR46XizeLOpr1OaKzm2BQ== X-Received: by 2002:a7b:c846:: with SMTP id c6mr26999235wml.75.1619972176866; Sun, 02 May 2021 09:16:16 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 07/36] target/mips: Simplify meson TCG rules Date: Sun, 2 May 2021 18:15:09 +0200 Message-Id: <20210502161538.534038-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We already have the mips_tcg_ss source set for TCG-specific files, use it for mxu_translate.c and tx79_translate.c to simplify a bit. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-2-f4bug@amsat.org> --- target/mips/meson.build | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/mips/meson.build b/target/mips/meson.build index 3b131c4a7f6..3733d1200f7 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -26,10 +26,9 @@ 'translate_addr_const.c', 'txx9_translate.c', )) -mips_ss.add(when: ['CONFIG_TCG', 'TARGET_MIPS64'], if_true: files( +mips_tcg_ss.add(when: 'TARGET_MIPS64', if_true: files( 'tx79_translate.c', -)) -mips_tcg_ss.add(when: 'TARGET_MIPS64', if_false: files( +), if_false: files( 'mxu_translate.c', )) =20 --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) client-ip=209.85.221.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619972183; cv=none; d=zohomail.com; s=zohoarc; b=YcxH2Mcy67dTbU6c8LeNj/uHDM7XCOF/fcPbe/sCFE9HbPsUTJjmO3bjInrrDkXMcjE3uagY6UOr54bCpIRq4STQOsdeC43tET8/LTavrHNmTbVS8H5cqjvigM+YeHxyk9jvk+PIZVewEI/+ob79dnIl5V9fCAjn9esdltTkJE0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972183; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9aHYgYzT6J1wA0FMMiXBOV8u8PmBNE5bOUtIZLsRchM=; b=assDpr1VCQxvSJPn206Op7ZG15CHK7xR5vfTGyPilGGX8iO49r3mT/sjI7k+kscA7I5hlEyyv2YYKtYQ3As81SRsuXO1LmOR/VGsZsCgGFfpBRTIYSTnfenmcNZm/Qkhie+t+a9npkm+ihruaxCzdre2Y3+72I9bHpWLaxHMuN8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) by mx.zohomail.com with SMTPS id 1619972183596400.1515615415175; Sun, 2 May 2021 09:16:23 -0700 (PDT) Received: by mail-wr1-f42.google.com with SMTP id t18so3108899wry.1 for ; Sun, 02 May 2021 09:16:23 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (anancy-651-1-208-144.w109-217.abo.wanadoo.fr. [109.217.237.144]) by smtp.gmail.com with ESMTPSA id u2sm10619688wmm.5.2021.05.02.09.16.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:16:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9aHYgYzT6J1wA0FMMiXBOV8u8PmBNE5bOUtIZLsRchM=; b=kQapcxIqYtind6MGaR4gjiFhcyuv/QdHntQfJ+xt3GxP36i1qqHN07KZhgPfrRhvUU rdenA5LFxMPPkqxg9el+FeWWux6BNeyumikpcfhithvdyGCcPufZI63k4tnYrfyZKJYf qqyBJhDX5zzpa0uYrI/ogiv4W8F5y0rzrRTYdoJAf/jG3pfvpwmR2FYKxlFR1QDyReMX nrVDy31jZ8JAVOZDMO2bUXFPgfDS6Jw1BZBJoTF2YqHopO1JwxBrlelZxoW8eBJ7GR3A J3IlkDmtD3XEwausKrpKMfg8Qp+PPbz5O76SJrWT4pv/4N66tnthxG37UJHYV89AOQXu W5Yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=9aHYgYzT6J1wA0FMMiXBOV8u8PmBNE5bOUtIZLsRchM=; b=gHR2f/vUHysF86NB73t98hkqlHJ0RkbWBtzihYyFMtDpQByMJCTTvDl/9sK74jUeLt XQVdeTVo31wAvLO2DPAyxnTnATcb1boX7YO6LAJLOqYIzyNp9YrixdobnWxygSaOa83c eNG/zpQXWHpbOzv3TVdu79h8A8n+DNh9Mb71SasgcWBi2cYRCQhKXeuKkBHn2hPodUmD +u1wmYV890FPfq4dbsWix3EB5ZbNyTw21RNMzO+ojxs0gVnXqyhafW31hHeLrVSvl/KZ tKlmkCIt2idw9JGKtE1U981ydpnka7v5iEV5oAtcFFUHlfDs/j+T0LgU034Fp3QHwv7o sBpw== X-Gm-Message-State: AOAM532VonaUblharQJTFX3wVqL6ahQeTkcRKNjUbTpAUvQXYrunba1c WQEHeNlrqam3zLr5QC4mOH0= X-Google-Smtp-Source: ABdhPJxTzP7+oM3S4uMjRRtq01ifxA8JZSJ80beccg4IPh/ufe4zUEVdVWByq++CC9zQvNg7JSqrsQ== X-Received: by 2002:a5d:5741:: with SMTP id q1mr19819781wrw.212.1619972181918; Sun, 02 May 2021 09:16:21 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 08/36] target/mips: Move IEEE rounding mode array to new source file Date: Sun, 2 May 2021 18:15:10 +0200 Message-Id: <20210502161538.534038-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) restore_msa_fp_status() is declared inlined in fpu_helper.h, and uses the ieee_rm[] array. Therefore any code calling restore_msa_fp_status() must have access to this ieee_rm[] array. kvm_mips_get_fpu_registers(), which is in target/mips/kvm.c, calls restore_msa_fp_status. Except this tiny array, the rest of fpu_helper.c is only useful for the TCG accelerator. To be able to restrict fpu_helper.c to TCG, we need to move the ieee_rm[] array to a new source file. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-3-f4bug@amsat.org> --- target/mips/fpu.c | 18 ++++++++++++++++++ target/mips/fpu_helper.c | 8 -------- target/mips/meson.build | 1 + 3 files changed, 19 insertions(+), 8 deletions(-) create mode 100644 target/mips/fpu.c diff --git a/target/mips/fpu.c b/target/mips/fpu.c new file mode 100644 index 00000000000..39a2f7fd22e --- /dev/null +++ b/target/mips/fpu.c @@ -0,0 +1,18 @@ +/* + * Helpers for emulation of FPU-related MIPS instructions. + * + * Copyright (C) 2004-2005 Jocelyn Mayer + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#include "qemu/osdep.h" +#include "fpu/softfloat-helpers.h" +#include "fpu_helper.h" + +/* convert MIPS rounding mode in FCR31 to IEEE library */ +const FloatRoundMode ieee_rm[4] =3D { + float_round_nearest_even, + float_round_to_zero, + float_round_up, + float_round_down +}; diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index 6dd853259e2..8ce56ed7c81 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -38,14 +38,6 @@ #define FP_TO_INT32_OVERFLOW 0x7fffffff #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL =20 -/* convert MIPS rounding mode in FCR31 to IEEE library */ -const FloatRoundMode ieee_rm[4] =3D { - float_round_nearest_even, - float_round_to_zero, - float_round_up, - float_round_down -}; - target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg) { target_ulong arg1 =3D 0; diff --git a/target/mips/meson.build b/target/mips/meson.build index 3733d1200f7..5fcb211ca9a 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -9,6 +9,7 @@ mips_ss =3D ss.source_set() mips_ss.add(files( 'cpu.c', + 'fpu.c', 'gdbstub.c', )) mips_tcg_ss =3D ss.source_set() --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) client-ip=209.85.128.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619972188; cv=none; d=zohomail.com; s=zohoarc; b=JjFz5JK46u06osoATS6KHmDVhOFo9SwS0HxGofkV84kbP/lPgInlcjyPA49CFV0wi4BKXGEVZQ40Cm26OeZCMj0yL51d6cyasbjM/nSJLNgS7mIYA5fPgacXSEp/W6kLDdvPpSQNlRbemV8KWs0sQA95Q/43HzoKgDUyXSFIKfk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972188; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8Aj0mupBuNQzvSz3rnDg5UisWaq3YfANzo69Tpa9DXM=; b=c4H846gaUIxh5yMTeOtmMO7Ep9tDbA5beM68EOSw7lwoWBBVHPWsz+9a8R8FwEak+UQ+xW89uq291i5AC/RvRyNzDQEdo3UztJcP8dZ4eF4vc+VmZ8OXcQTCRWmvp4pUTiMC/Jh9VQT/WDYzPcWW5OT8TL7O8aIBYD1/so71UlM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.zohomail.com with SMTPS id 1619972188984594.4007633687296; Sun, 2 May 2021 09:16:28 -0700 (PDT) Received: by mail-wm1-f49.google.com with SMTP id b19-20020a05600c06d3b029014258a636e8so2117410wmn.2 for ; Sun, 02 May 2021 09:16:28 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (anancy-651-1-208-144.w109-217.abo.wanadoo.fr. [109.217.237.144]) by smtp.gmail.com with ESMTPSA id z18sm9288724wrh.16.2021.05.02.09.16.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:16:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8Aj0mupBuNQzvSz3rnDg5UisWaq3YfANzo69Tpa9DXM=; b=b5Xre1WozQ+TNTBfwJKBkXqAlVq//DyfmygEBQVCoRILuKpw7k6CRH3ZNdTJvuKXoU R8Ua5WLGd/Fli2QZqMAGjHZQ7bl5Cq5Bx3x9gCtlcjblMO+cqVz+eg4Oc9F7s0P5phff 1mbO6ye1tee/1h5I2/TrnIZanlf9HYv3E4YxYM1ncEvgRrZuilksvPYZY1aa2u8RR2t+ TOiSJsEMN+I7ilF5TgolpKcnEhOBHitRvJru0U3Kxdb+PyeOJos+C1LsmaFTgSAgXGi3 xJ14MiaHd9jeOR7YaGmOesGADWt3WC7ciidRvAHg6dIhYuhHOdLtKcQFHdNkn8l8GdtI aBXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=8Aj0mupBuNQzvSz3rnDg5UisWaq3YfANzo69Tpa9DXM=; b=pXZZSwMSyKqeauGlMyVEUbKSEbsoM2RZjhiE6hwGsbyexQfLl+Hja3wUUiiUUYivZA XsTeKSu/RPwtwDSvGU8MwbAFmeXNYuRtJJKqvnk4T8JeiNG5ygPa9Dx2HTks99Z9T+nn oSVyPU3uu4zYxW0rYAHH5r9p9ElyX6QvoRzGNTPSHAqDcvx7vj1Z+kGyhYRQrOEpRJih VO+4z9TC4ZOLIxHoYML6hBzdQWAnnIcJTFQ1XYesdhKkstocreLdMZ0MbEbO/A1i6jOi 59XgkYhuh9d8cTzYctNb8J58g3PB6vF/vJJk9XVKF1cXmdTHeHmXfQSMQdcOPmslZtfx jfxw== X-Gm-Message-State: AOAM531afTf2abuxgbsFSU6kG6CZ/CnbLCCpMebyXI5oJ+fpqYjODB88 06SefC7shFF0/TmXrRkZabY= X-Google-Smtp-Source: ABdhPJwdDuVGVkkXbVmeqnFsAhRumwwD+K1YCtWYJYFXifz+5qsb1O4BkifyjxHKFhOn4sNSPQadVQ== X-Received: by 2002:a1c:1d17:: with SMTP id d23mr17265336wmd.110.1619972187081; Sun, 02 May 2021 09:16:27 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 09/36] target/mips: Move msa_reset() to new source file Date: Sun, 2 May 2021 18:15:11 +0200 Message-Id: <20210502161538.534038-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) mips_cpu_reset() is used by all accelerators, and calls msa_reset(), which is defined in msa_helper.c. Beside msa_reset(), the rest of msa_helper.c is only useful to the TCG accelerator. To be able to restrict this helper file to TCG, we need to move msa_reset() out of it. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-4-f4bug@amsat.org> --- target/mips/msa.c | 60 ++++++++++++++++++++++++++++++++++++++++ target/mips/msa_helper.c | 36 ------------------------ target/mips/meson.build | 1 + 3 files changed, 61 insertions(+), 36 deletions(-) create mode 100644 target/mips/msa.c diff --git a/target/mips/msa.c b/target/mips/msa.c new file mode 100644 index 00000000000..61f1a9a5936 --- /dev/null +++ b/target/mips/msa.c @@ -0,0 +1,60 @@ +/* + * MIPS SIMD Architecture Module Instruction emulation helpers for QEMU. + * + * Copyright (c) 2014 Imagination Technologies + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internal.h" +#include "fpu/softfloat.h" +#include "fpu_helper.h" + +void msa_reset(CPUMIPSState *env) +{ + if (!ase_msa_available(env)) { + return; + } + +#ifdef CONFIG_USER_ONLY + /* MSA access enabled */ + env->CP0_Config5 |=3D 1 << CP0C5_MSAEn; + env->CP0_Status |=3D (1 << CP0St_CU1) | (1 << CP0St_FR); +#endif + + /* + * MSA CSR: + * - non-signaling floating point exception mode off (NX bit is 0) + * - Cause, Enables, and Flags are all 0 + * - round to nearest / ties to even (RM bits are 0) + */ + env->active_tc.msacsr =3D 0; + + restore_msa_fp_status(env); + + /* tininess detected after rounding.*/ + set_float_detect_tininess(float_tininess_after_rounding, + &env->active_tc.msa_fp_status); + + /* clear float_status exception flags */ + set_float_exception_flags(0, &env->active_tc.msa_fp_status); + + /* clear float_status nan mode */ + set_default_nan_mode(0, &env->active_tc.msa_fp_status); + + /* set proper signanling bit meaning ("1" means "quiet") */ + set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); +} diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 4caefe29ad7..04af54f66d1 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -8595,39 +8595,3 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]); #endif } - -void msa_reset(CPUMIPSState *env) -{ - if (!ase_msa_available(env)) { - return; - } - -#ifdef CONFIG_USER_ONLY - /* MSA access enabled */ - env->CP0_Config5 |=3D 1 << CP0C5_MSAEn; - env->CP0_Status |=3D (1 << CP0St_CU1) | (1 << CP0St_FR); -#endif - - /* - * MSA CSR: - * - non-signaling floating point exception mode off (NX bit is 0) - * - Cause, Enables, and Flags are all 0 - * - round to nearest / ties to even (RM bits are 0) - */ - env->active_tc.msacsr =3D 0; - - restore_msa_fp_status(env); - - /* tininess detected after rounding.*/ - set_float_detect_tininess(float_tininess_after_rounding, - &env->active_tc.msa_fp_status); - - /* clear float_status exception flags */ - set_float_exception_flags(0, &env->active_tc.msa_fp_status); - - /* clear float_status nan mode */ - set_default_nan_mode(0, &env->active_tc.msa_fp_status); - - /* set proper signanling bit meaning ("1" means "quiet") */ - set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); -} diff --git a/target/mips/meson.build b/target/mips/meson.build index 5fcb211ca9a..daf5f1d55bc 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -11,6 +11,7 @@ 'cpu.c', 'fpu.c', 'gdbstub.c', + 'msa.c', )) mips_tcg_ss =3D ss.source_set() mips_tcg_ss.add(gen) --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) client-ip=209.85.221.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619972194; cv=none; d=zohomail.com; s=zohoarc; b=LD6INs+lZZMF3yTQG4UPu+Jq1GURCpJ4ziVzQ2tPaZhd7F2EWMo/xMWoIuCkZu46CiUFMUeJc/WPx9Nx7igNbLJQx/0V7AZk9rs1xXrzS11bt9Qzs//d4/er/7Lqqb00VdELRlaF8+pQ4SGbZMLDvFL5boqP8oP01hadMzqm354= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972194; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=U33GaZGmKc4FXCL1JvbSdQZh866O1wwcqJkiYK14iVg=; b=ALx92mKTmEIpm2D6sKK8QQx4ZJyDZOmZu4Qrbr74O3+ZYkJR2wTlsdAcFv6BgVIAS8iymZ1y3soV9ib60wdMd4xc9YWANlsnT5ycCDgTy1e5ZU5KcXGb/E3I+TOjyV2+Lwh6UXiYBfw8evk0Ca8BUh+ojnlfcFhccf1/Tt7/V5g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) by mx.zohomail.com with SMTPS id 1619972194069507.76411846276267; Sun, 2 May 2021 09:16:34 -0700 (PDT) Received: by mail-wr1-f52.google.com with SMTP id v12so3092157wrq.6 for ; Sun, 02 May 2021 09:16:33 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (anancy-651-1-208-144.w109-217.abo.wanadoo.fr. [109.217.237.144]) by smtp.gmail.com with ESMTPSA id m11sm9463723wri.44.2021.05.02.09.16.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:16:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U33GaZGmKc4FXCL1JvbSdQZh866O1wwcqJkiYK14iVg=; b=Le7YhhrPWUwgaAYXTqhR9PfkgWkK9VtyCQlDyfvTcFYSBRGjCZekgjfz4XgcQZ0YoD dONKBUaOhX5xrb4ebD68UfPQlCQyjMvoZxUXnHUp58dElWE+WX2aCJyv4wxYP93PLoUS Cyo/ZGlnvug0fMhDyEoVteddXaXlAs65uLh2+OZbxhB+FCB8BPs7R6rYzjgSHhjCeHz3 Z+qtZUmiqx3FMMlAqYAUr/7vO+csDBCeiMQWs0Ts3cLEtmsR7xVUSZQ8gqWi8fV1RPl9 aN4+ob1Xoxr3JoN9NReIBHVPNq6Dr7IgMd4j+v4yjCx9k7KoQnliPWdiybsfB9Gt0R1h 4bTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=U33GaZGmKc4FXCL1JvbSdQZh866O1wwcqJkiYK14iVg=; b=m7RPUQgk/Al6lV+cpn3RKwWP2a2tPrrHFtXSbvpFGyCdi0xpGwGg9xsYxdW//QhfGy GX18B6KgJPZFrwESAeOEXruSYI8ovNYUSrcsFRd1ts/Jro+M6G5poYmM8Le2RXuKGTBm qpCWTRBWE28rNu/IS/NJASjBYx1cfwqNb+at9MC0x1gdmHSSzZuqTx8hxZ9giCTUMhl7 J8cD3V1UJ5jhdldxI6X3DIeS5bDd9lYt2neG2NMKF1QCqBecoyuv20aj41M1gyl4Sp56 TdBjRb6SQApty7c5l1JpP4Y/Lr0tX/AAXBV1QhaSI9bqB/rzmTd23Xx3AVjlXXiBZM5/ 8C0Q== X-Gm-Message-State: AOAM533fWO48qWCft8YNdnrc13J34C6QzFeWCkBGiZZgcRhZZYQS68/9 pZm7VEh4dLRY2moeYl5di2TRt7VbNyxWXj0E X-Google-Smtp-Source: ABdhPJw64wLkDmF8aCNK25kVFdMHmoY/+6BGDxBc78j0X0HRB/pqdjT/3hsU9lPBVpHTBtFcMdhdvA== X-Received: by 2002:adf:dfcd:: with SMTP id q13mr20212854wrn.363.1619972192106; Sun, 02 May 2021 09:16:32 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 10/36] target/mips: Make CPU/FPU regnames[] arrays global Date: Sun, 2 May 2021 18:15:12 +0200 Message-Id: <20210502161538.534038-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The CPU/FPU regnames[] arrays is used in mips_tcg_init() and mips_cpu_dump_state(), which while being in translate.c is not specific to TCG. To be able to move mips_cpu_dump_state() to cpu.c, which is compiled for all accelerator, we need to make the regnames[] arrays global to target/mips/ by declaring them in "internal.h". Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-5-f4bug@amsat.org> --- target/mips/internal.h | 3 +++ target/mips/cpu.c | 7 +++++++ target/mips/fpu.c | 7 +++++++ target/mips/translate.c | 14 -------------- 4 files changed, 17 insertions(+), 14 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 99264b8bf6a..a8644f754a6 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -71,6 +71,9 @@ struct mips_def_t { int32_t SAARP; }; =20 +extern const char * const regnames[32]; +extern const char * const fregnames[32]; + extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; =20 diff --git a/target/mips/cpu.c b/target/mips/cpu.c index dce1e166bde..f354d18aec4 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -35,6 +35,13 @@ #include "qapi/qapi-commands-machine-target.h" #include "fpu_helper.h" =20 +const char * const regnames[32] =3D { + "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", + "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", + "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", +}; + #if !defined(CONFIG_USER_ONLY) =20 /* Called for updates to CP0_Status. */ diff --git a/target/mips/fpu.c b/target/mips/fpu.c index 39a2f7fd22e..1447dba3fa3 100644 --- a/target/mips/fpu.c +++ b/target/mips/fpu.c @@ -16,3 +16,10 @@ const FloatRoundMode ieee_rm[4] =3D { float_round_up, float_round_down }; + +const char * const fregnames[32] =3D { + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", +}; diff --git a/target/mips/translate.c b/target/mips/translate.c index 0e90d8cace6..8d686e90954 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1267,13 +1267,6 @@ TCGv_i64 fpu_f64[32]; #define DISAS_STOP DISAS_TARGET_0 #define DISAS_EXIT DISAS_TARGET_1 =20 -static const char * const regnames[] =3D { - "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", - "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", - "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", - "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", -}; - static const char * const regnames_HI[] =3D { "HI0", "HI1", "HI2", "HI3", }; @@ -1282,13 +1275,6 @@ static const char * const regnames_LO[] =3D { "LO0", "LO1", "LO2", "LO3", }; =20 -static const char * const fregnames[] =3D { - "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", - "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", - "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", - "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", -}; - /* General purpose registers moves. */ void gen_load_gpr(TCGv t, int reg) { --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) client-ip=209.85.221.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619972198; cv=none; d=zohomail.com; s=zohoarc; b=N6YWT21TopBG5ov9+2V6WN4k/fYYeHlUk04xi+IXF4mbBjUCSZxL+cyt/hsAYLuQzA79ktWdz8ypvSDEdpysnRsQ2fFFieaxtJTI1jX7mfmgVv1XVaLcC0CU4HsQo9CGIalAtE9bhQSuA7q1dP0kbLJDEV3q3D6paTbjriw+baE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972198; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=otaOdF2+QjBw7vCs6eJeEN+7XfrkFSt9cRlnVyMFAT8=; b=g1Svb/r/s8OiH18nVimgs5LTI5srMlw553RuJIxee8Ex/g1FHVYFinHheKzXPC0wa3lMO8TzZ+3IUD4s+egTKoAFfimnz8bNCoAMOxLy+RfJ++FQgH3EAJvBJqHQK89nX/q4Hlo2q0/PrUNz5s+E7yLibpD/byT/9aWlnTu7g4c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) by mx.zohomail.com with SMTPS id 1619972198877107.4803575584059; Sun, 2 May 2021 09:16:38 -0700 (PDT) Received: by mail-wr1-f42.google.com with SMTP id d4so3091203wru.7 for ; Sun, 02 May 2021 09:16:38 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (anancy-651-1-208-144.w109-217.abo.wanadoo.fr. [109.217.237.144]) by smtp.gmail.com with ESMTPSA id s6sm21201888wms.0.2021.05.02.09.16.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:16:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=otaOdF2+QjBw7vCs6eJeEN+7XfrkFSt9cRlnVyMFAT8=; b=YzqwfsBxeZ643NXMZN6yrtEFs37/3BnfS98ZFXzsjsAJ7BGFSbbUQC72ZutQ25swS/ HGDGfytE/dH2taG2npjICB9yhLHLkGpd4fx3KzAeLzgbfYVd0scb26qr6AqF2iAnaGBc fjH8ew4cbKGtKf3Gp6Eg+qtA3PX+ZF+90EkKssh3Xb+PPqW5HTx7aR9Ate60wSrUPoZw c73rFN7fpl9S9h/K+fb0Ac9i32I7S0QSJR0l/29hckG2+t9rzeNaTAMzmv+VIfhkOvqr qwnf8GS3/tZUFGUuu9GSCfuPf/H1PNVrAeWJdR/v6LpEnqVD5DWS11O5+9WiqxFTYFQ7 HrkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=otaOdF2+QjBw7vCs6eJeEN+7XfrkFSt9cRlnVyMFAT8=; b=pn1zEHkMD1ojleDaBW6lh2zpLAtxSm9jS+L9fVc/ELPG5Y3lGT+JUiNWaD30R4ZNVA 2DO4NCn3AxEXqTTooWNWTMeMG7XPled6CHl8B3MTMWi3Lx3GNWW0HJqVi0wFJyDLj+ZX DfKL6/uTUN2K2fE0X/QfzocDk6dyg0EDWU/sQuKq7IL/3zEFHgZWuTNdTuOUJc0wZtdY yyhRmd/KaVO57cfgyMfi9955KFB6OH6zOrvKo2erL45q9YDWDuUFj0hcYI2uU7ncxHf7 ggNODCbl0SPfBB0qRpYlPrcNxNNnYfAFFmKozF8JDQ7fIrF2GYg5Z93e89brDgxIlW5k JQ0g== X-Gm-Message-State: AOAM533B/WM0OkFjKBhLCS9CRQaadgP4O+g7P3oYpAnbZixNBcDQ2oK1 ZxwJcpGw0h1eupRmC8wn+HI= X-Google-Smtp-Source: ABdhPJzOy91Rge+I9QbC6z1HsSI2Ja21veqhliFdHuaxqdufJ2JvBOw+2yiQMJf2G6zjnK4wWR3pYA== X-Received: by 2002:adf:fe8e:: with SMTP id l14mr19439702wrr.305.1619972197154; Sun, 02 May 2021 09:16:37 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 11/36] target/mips: Optimize CPU/FPU regnames[] arrays Date: Sun, 2 May 2021 18:15:13 +0200 Message-Id: <20210502161538.534038-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Since all entries are no more than 4 bytes (including nul terminator), can save space and pie runtime relocations by declaring regnames[] as array of 4 const char. Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-6-f4bug@amsat.org> --- target/mips/internal.h | 4 ++-- target/mips/cpu.c | 2 +- target/mips/fpu.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index a8644f754a6..37f54a8b3fc 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -71,8 +71,8 @@ struct mips_def_t { int32_t SAARP; }; =20 -extern const char * const regnames[32]; -extern const char * const fregnames[32]; +extern const char regnames[32][4]; +extern const char fregnames[32][4]; =20 extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index f354d18aec4..ed9552ebeb7 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -35,7 +35,7 @@ #include "qapi/qapi-commands-machine-target.h" #include "fpu_helper.h" =20 -const char * const regnames[32] =3D { +const char regnames[32][4] =3D { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", diff --git a/target/mips/fpu.c b/target/mips/fpu.c index 1447dba3fa3..c7c487c1f9f 100644 --- a/target/mips/fpu.c +++ b/target/mips/fpu.c @@ -17,7 +17,7 @@ const FloatRoundMode ieee_rm[4] =3D { float_round_down }; =20 -const char * const fregnames[32] =3D { +const char fregnames[32][4] =3D { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) client-ip=209.85.221.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1619972204; cv=none; d=zohomail.com; s=zohoarc; b=RgYNrnS1yIeW0FVgoUgwTwoTh/9XiFwlpd8AqiuTX0uPDk2ydlN6CzMaaQ39yEuWM/Oamz/Xl///GT1XfKoprMCf1XJHSifX4Byz3i4/n5K/7laduvlpjDgRRniIgqUmoD1gZ/EVD3t3m/aGGnmKQwmMwUyEJ/TckQhCjqHKll0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972204; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=q9wnhp0A3R7EoBRYlMJ/eiPyIrdG3fRM7mBr849A7fc=; b=aogh2gek2x3rD7JTLA7kCwbA3hFDIAKpiLnkGvwgxMWq+/UbqtqCycwOtcWOm0aa2jmAwoUicYT59iRfa04pdsUCy7AIpp2dwybijW4aOrrhxJrJws0DzhXh0KdXOF8yWIHExkxktBSCdIewzIGI4+0wFh+Ds1uzmZFlbA7I0yE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) by mx.zohomail.com with SMTPS id 1619972204040666.736072130786; Sun, 2 May 2021 09:16:44 -0700 (PDT) Received: by mail-wr1-f50.google.com with SMTP id l13so1488842wru.11 for ; Sun, 02 May 2021 09:16:43 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (anancy-651-1-208-144.w109-217.abo.wanadoo.fr. [109.217.237.144]) by smtp.gmail.com with ESMTPSA id m67sm22132157wme.27.2021.05.02.09.16.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:16:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=q9wnhp0A3R7EoBRYlMJ/eiPyIrdG3fRM7mBr849A7fc=; b=omJ3CBORaWBn6d3tt88wKL+2rQFnMIxlPfLl29nVxXeFDnwBYf0u28D6dGbeK4XcNJ pus0QC+u6ZDQMQqqlF9xrzQ1S16Skq+cFwlxwMnjbJTOx59ZyPD/5kEMYeGur2H4QqUu C5s1X7K1LBLqWuZyj01RhFLiCIeLk/wsLKje/YKKF0m28kfg9OgXB4fWmDVLFgzshX3V WFuGDgy7PxJGCYQDmjoi70bbHH8GHrshjHx7QRCT+dZadR1JETlcleFcVtvprjMtFEXu YwdxcHmTAslV1qwjPQ9PG5j4PXZmGrY5vuYdB6dlSpJR/Ioj45tEMPXrcO4SS1LT16oC n2gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=q9wnhp0A3R7EoBRYlMJ/eiPyIrdG3fRM7mBr849A7fc=; b=oIGRRIuUuaXbB/4aaki5E0d+49pYitfh+WEotNYGJBQCDsCkFIeledeszdDJDKUuNN rVq5OmWEYo+PEp+cTkGBt4dPiFvEdE4Ol+h5Q7BSkDh5I4uKtwwS3JPT/X+dhvmKVexY 9UsKTkQVP8o2xidCCATBNyYjO5ccyn89HXx+5PmygGfRVuy9Pp8WYUda2UC78NEr9bd0 qK0E4p2HXnN/+kObKja1s7Vrm6dPLD7umLykilJsOAhZBeHlSQqFgoXHmzdW7sqvfA2t Eda4Tr/f7D0MiIdOeTto0EzNydO06sVBScq0NUWSX0F8Aj3EyjtYoL0ouRUl7nWVEjie S/hg== X-Gm-Message-State: AOAM531oG5Dzhe2/wqxDD6ifBujwlyzhj5r1iayko4UfJhZVN/ZFJ5Qt kEnY9n0sCIqf226ks5sAdXw= X-Google-Smtp-Source: ABdhPJzwzGTnFhBj2ZWjJ+fqTjw6mtVkdq52MJub06zDrNFLOI1eCL/X0bqAUm6V6bFGzznBvAScKg== X-Received: by 2002:a5d:4386:: with SMTP id i6mr14558919wrq.207.1619972202297; Sun, 02 May 2021 09:16:42 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 12/36] target/mips: Restrict mips_cpu_dump_state() to cpu.c Date: Sun, 2 May 2021 18:15:14 +0200 Message-Id: <20210502161538.534038-13-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) As mips_cpu_dump_state() is only used once to initialize the CPUClass::dump_state handler, we can move it to cpu.c to keep it symbol local. Beside, this handler is used by all accelerators, while the translate.c file targets TCG. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-7-f4bug@amsat.org> --- target/mips/internal.h | 1 - target/mips/cpu.c | 77 +++++++++++++++++++++++++++++++++++++++++ target/mips/translate.c | 77 ----------------------------------------- 3 files changed, 77 insertions(+), 78 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 37f54a8b3fc..57072a941e7 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -79,7 +79,6 @@ extern const int mips_defs_number; =20 void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); -void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index ed9552ebeb7..232f701b836 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -145,6 +145,83 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ul= ong val) =20 #endif /* !CONFIG_USER_ONLY */ =20 +static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) +{ + int i; + int is_fpu64 =3D !!(env->hflags & MIPS_HFLAG_F64); + +#define printfpr(fp) \ + do { \ + if (is_fpu64) \ + qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ + " fd:%13g fs:%13g psu: %13g\n", \ + (fp)->w[FP_ENDIAN_IDX], (fp)->d, \ + (double)(fp)->fd, \ + (double)(fp)->fs[FP_ENDIAN_IDX], \ + (double)(fp)->fs[!FP_ENDIAN_IDX]); \ + else { \ + fpr_t tmp; \ + tmp.w[FP_ENDIAN_IDX] =3D (fp)->w[FP_ENDIAN_IDX]; \ + tmp.w[!FP_ENDIAN_IDX] =3D ((fp) + 1)->w[FP_ENDIAN_IDX]; \ + qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ + " fd:%13g fs:%13g psu:%13g\n", \ + tmp.w[FP_ENDIAN_IDX], tmp.d, \ + (double)tmp.fd, \ + (double)tmp.fs[FP_ENDIAN_IDX], \ + (double)tmp.fs[!FP_ENDIAN_IDX]); \ + } \ + } while (0) + + + qemu_fprintf(f, + "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02= x\n", + env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, + get_float_exception_flags(&env->active_fpu.fp_status)); + for (i =3D 0; i < 32; (is_fpu64) ? i++ : (i +=3D 2)) { + qemu_fprintf(f, "%3s: ", fregnames[i]); + printfpr(&env->active_fpu.fpr[i]); + } + +#undef printfpr +} + +static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + int i; + + qemu_fprintf(f, "pc=3D0x" TARGET_FMT_lx " HI=3D0x" TARGET_FMT_lx + " LO=3D0x" TARGET_FMT_lx " ds %04x " + TARGET_FMT_lx " " TARGET_FMT_ld "\n", + env->active_tc.PC, env->active_tc.HI[0], env->active_tc.L= O[0], + env->hflags, env->btarget, env->bcond); + for (i =3D 0; i < 32; i++) { + if ((i & 3) =3D=3D 0) { + qemu_fprintf(f, "GPR%02d:", i); + } + qemu_fprintf(f, " %s " TARGET_FMT_lx, + regnames[i], env->active_tc.gpr[i]); + if ((i & 3) =3D=3D 3) { + qemu_fprintf(f, "\n"); + } + } + + qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" + TARGET_FMT_lx "\n", + env->CP0_Status, env->CP0_Cause, env->CP0_EPC); + qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" + PRIx64 "\n", + env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); + qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", + env->CP0_Config2, env->CP0_Config3); + qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", + env->CP0_Config4, env->CP0_Config5); + if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) { + fpu_dump_state(env, f, flags); + } +} + static const char * const excp_names[EXCP_LAST + 1] =3D { [EXCP_RESET] =3D "reset", [EXCP_SRESET] =3D "soft reset", diff --git a/target/mips/translate.c b/target/mips/translate.c index 8d686e90954..f0ae3716022 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -25586,83 +25586,6 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb, int max_insns) translator_loop(&mips_tr_ops, &ctx.base, cs, tb, max_insns); } =20 -static void fpu_dump_state(CPUMIPSState *env, FILE * f, int flags) -{ - int i; - int is_fpu64 =3D !!(env->hflags & MIPS_HFLAG_F64); - -#define printfpr(fp) \ - do { \ - if (is_fpu64) \ - qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ - " fd:%13g fs:%13g psu: %13g\n", \ - (fp)->w[FP_ENDIAN_IDX], (fp)->d, \ - (double)(fp)->fd, \ - (double)(fp)->fs[FP_ENDIAN_IDX], \ - (double)(fp)->fs[!FP_ENDIAN_IDX]); \ - else { \ - fpr_t tmp; \ - tmp.w[FP_ENDIAN_IDX] =3D (fp)->w[FP_ENDIAN_IDX]; \ - tmp.w[!FP_ENDIAN_IDX] =3D ((fp) + 1)->w[FP_ENDIAN_IDX]; \ - qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ - " fd:%13g fs:%13g psu:%13g\n", \ - tmp.w[FP_ENDIAN_IDX], tmp.d, \ - (double)tmp.fd, \ - (double)tmp.fs[FP_ENDIAN_IDX], \ - (double)tmp.fs[!FP_ENDIAN_IDX]); \ - } \ - } while (0) - - - qemu_fprintf(f, - "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02= x\n", - env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, - get_float_exception_flags(&env->active_fpu.fp_status)); - for (i =3D 0; i < 32; (is_fpu64) ? i++ : (i +=3D 2)) { - qemu_fprintf(f, "%3s: ", fregnames[i]); - printfpr(&env->active_fpu.fpr[i]); - } - -#undef printfpr -} - -void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) -{ - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - int i; - - qemu_fprintf(f, "pc=3D0x" TARGET_FMT_lx " HI=3D0x" TARGET_FMT_lx - " LO=3D0x" TARGET_FMT_lx " ds %04x " - TARGET_FMT_lx " " TARGET_FMT_ld "\n", - env->active_tc.PC, env->active_tc.HI[0], env->active_tc.L= O[0], - env->hflags, env->btarget, env->bcond); - for (i =3D 0; i < 32; i++) { - if ((i & 3) =3D=3D 0) { - qemu_fprintf(f, "GPR%02d:", i); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx, - regnames[i], env->active_tc.gpr[i]); - if ((i & 3) =3D=3D 3) { - qemu_fprintf(f, "\n"); - } - } - - qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" - TARGET_FMT_lx "\n", - env->CP0_Status, env->CP0_Cause, env->CP0_EPC); - qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" - PRIx64 "\n", - env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); - qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", - env->CP0_Config2, env->CP0_Config3); - qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", - env->CP0_Config4, env->CP0_Config5); - if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) { - fpu_dump_state(env, f, flags); - } -} - void mips_tcg_init(void) { int i; --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) client-ip=209.85.221.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1619972209; cv=none; d=zohomail.com; s=zohoarc; b=SaeD9uubADoyDZN9cX+CiANx+3GxfavIKfy9FNQes5QZuegpW5+5pa8PJ7NjIMRUxnDeulEvJ71d4ttIwDPKALmB6OuEkGKGy1/ne7q7twX0DvZj5kFms3ricZup4leTjZLkmh7SBrStaZIvWrbYV8/aybfWcIqEgVHZnCtw+J8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972209; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vEgBRw3bS0UqwDQNEnkoqhfr+jxoj1xXZeQLuQmGs0c=; b=JIEUGRZnnuzYjLRJTQ3pcaaWSOxiRI5AMgpIFFvgxMNIwCjbzZQkRAFhQe0cpnGBzDfwwHJDVGMUAlB46np9kVX8Ml7GGi/HB+0DbK6ccjhdHcL5JHwr2QvJMDJOyi7PRD0e0pG7uUNesAicC/Ka2WsATGl9FUQC/55EWLaPTL8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) by mx.zohomail.com with SMTPS id 1619972209907851.9688784099037; Sun, 2 May 2021 09:16:49 -0700 (PDT) Received: by mail-wr1-f42.google.com with SMTP id v12so3092765wrq.6 for ; Sun, 02 May 2021 09:16:49 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (anancy-651-1-208-144.w109-217.abo.wanadoo.fr. [109.217.237.144]) by smtp.gmail.com with ESMTPSA id u9sm8759441wmc.38.2021.05.02.09.16.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:16:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vEgBRw3bS0UqwDQNEnkoqhfr+jxoj1xXZeQLuQmGs0c=; b=iDaNjdJg72Z2bctorpKU/LM3WXl3AzPXJlYq2lmGZ5QPgS8+m+TPCGcX3gCUcmXuqg OVJlyXT71fXBZQTrJ3GIAimpugbLccVFGo0CAgcrtgOcSUCcBzBKVp2nTiSOtOzXqAk1 yLl31QHKekjBv2zLI9uVFb5o7ZL5lzfS6gxP4YqlN3AI8SGrUr8h5WtHmqrpIyqT43Ru a8RNfCcY6kVZI5ehYg7E3XQCO6e0JNE6SD+00dez2wsglL3vJ/3juVybr6aNetfQ2eNo 3J5ZdUIXPD9FVX+DYTC4ccYfybnsLQPJUMo/al9or1WXXeC/vFxgwRfJCl05GhoBKfnY k6qA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=vEgBRw3bS0UqwDQNEnkoqhfr+jxoj1xXZeQLuQmGs0c=; b=RnrO/0rJKomaYphQA0AkLHiIKqKd2gny/ney4xuFq6dQSaWO1wJudN67oaLW5yEG/d YAuJ7WTXbn+DT2szr1t5tIYM+vYwdKd7gFCyeozEDkAHxnNVRAr2XUpynXPt6Ricj4J0 JPhq2Th8emM0dD7NPhKYJetmyF1fikVwlC7eRcfBR1uBdL2Vh9bI/puAcn/o+ZCo0L5L c1HgHClgaigHhEKV+bTLPuBtDc20MNpAyr4wbt8wXv6pzP6I8qJ1MdFoTI98+0bqVcFt dRGOyidy4b3erhXGznvxeusLObXLKiwNkctPmc+GCNEZVrl28lCaGEdxyO0QjuJDyzYQ RE3g== X-Gm-Message-State: AOAM531Zb8tsRH3mybEmMjczfStY1kfgPxxcxQGSZgtgL2jhdCPJti3N r5Iuo4TOsH/m2cdea13jfwI= X-Google-Smtp-Source: ABdhPJy0ozRtVnQkWEijqE0clAm1KTUz6rztSjqKvhtTwHjFh0hURz3cGu9kyj+PSRXxfGG0F4n1Sg== X-Received: by 2002:a5d:4d09:: with SMTP id z9mr11462265wrt.131.1619972208227; Sun, 02 May 2021 09:16:48 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 13/36] target/mips: Turn printfpr() macro into a proper function Date: Sun, 2 May 2021 18:15:15 +0200 Message-Id: <20210502161538.534038-14-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Turn printfpr() macro into a proper function: fpu_dump_fpr(). Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-8-f4bug@amsat.org> --- target/mips/cpu.c | 50 ++++++++++++++++++++++------------------------- 1 file changed, 23 insertions(+), 27 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 232f701b836..8f76f4576f4 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -145,33 +145,31 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_u= long val) =20 #endif /* !CONFIG_USER_ONLY */ =20 +static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64) +{ + if (is_fpu64) { + qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu: %13g= \n", + fpr->w[FP_ENDIAN_IDX], fpr->d, + (double)fpr->fd, + (double)fpr->fs[FP_ENDIAN_IDX], + (double)fpr->fs[!FP_ENDIAN_IDX]); + } else { + fpr_t tmp; + + tmp.w[FP_ENDIAN_IDX] =3D fpr->w[FP_ENDIAN_IDX]; + tmp.w[!FP_ENDIAN_IDX] =3D (fpr + 1)->w[FP_ENDIAN_IDX]; + qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu:%13g\= n", + tmp.w[FP_ENDIAN_IDX], tmp.d, + (double)tmp.fd, + (double)tmp.fs[FP_ENDIAN_IDX], + (double)tmp.fs[!FP_ENDIAN_IDX]); + } +} + static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) { int i; - int is_fpu64 =3D !!(env->hflags & MIPS_HFLAG_F64); - -#define printfpr(fp) \ - do { \ - if (is_fpu64) \ - qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ - " fd:%13g fs:%13g psu: %13g\n", \ - (fp)->w[FP_ENDIAN_IDX], (fp)->d, \ - (double)(fp)->fd, \ - (double)(fp)->fs[FP_ENDIAN_IDX], \ - (double)(fp)->fs[!FP_ENDIAN_IDX]); \ - else { \ - fpr_t tmp; \ - tmp.w[FP_ENDIAN_IDX] =3D (fp)->w[FP_ENDIAN_IDX]; \ - tmp.w[!FP_ENDIAN_IDX] =3D ((fp) + 1)->w[FP_ENDIAN_IDX]; \ - qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ - " fd:%13g fs:%13g psu:%13g\n", \ - tmp.w[FP_ENDIAN_IDX], tmp.d, \ - (double)tmp.fd, \ - (double)tmp.fs[FP_ENDIAN_IDX], \ - (double)tmp.fs[!FP_ENDIAN_IDX]); \ - } \ - } while (0) - + bool is_fpu64 =3D !!(env->hflags & MIPS_HFLAG_F64); =20 qemu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02= x\n", @@ -179,10 +177,8 @@ static void fpu_dump_state(CPUMIPSState *env, FILE *f,= int flags) get_float_exception_flags(&env->active_fpu.fp_status)); for (i =3D 0; i < 32; (is_fpu64) ? i++ : (i +=3D 2)) { qemu_fprintf(f, "%3s: ", fregnames[i]); - printfpr(&env->active_fpu.fpr[i]); + fpu_dump_fpr(&env->active_fpu.fpr[i], f, is_fpu64); } - -#undef printfpr } =20 static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) client-ip=209.85.221.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619972216; cv=none; d=zohomail.com; s=zohoarc; b=kWHa0h4F3pt8O9LYzfAElyFjEXedHze/vVoMRRnVyXMlJotbJTA8PVdUMU485PdIgpnFk0mgeNM9KG2sOAhV9D8PLZMjNulUUk9bnKkCFU2Qqk7PZD6CAhg7f1JiVQAuH3WHm19+CVftWBCntqqetU0Itx/2oH0Bv/KJe58nW3M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972216; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SAjsdRT6m+/gb9YjtjeiORJfX3lsELt6a2iqeSZGiwI=; b=d8r4ShTtzVNsOYKBcPXT26m+VGXI4jCsMq7Qn10nEAhgpt3V+slnDADXzzMVXJ8e//cMfehL2qOmKfu8FLG+T9E9DkyrsIMMv4O9zDKz9fBoRppSwAEZPRXczBgfhRITI56LopNzHaKXA04x3uy5rXNKNdBR0U45tfWNwMbbK1g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) by mx.zohomail.com with SMTPS id 1619972216606421.9891902064629; Sun, 2 May 2021 09:16:56 -0700 (PDT) Received: by mail-wr1-f54.google.com with SMTP id v12so3092926wrq.6 for ; Sun, 02 May 2021 09:16:55 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (anancy-651-1-208-144.w109-217.abo.wanadoo.fr. [109.217.237.144]) by smtp.gmail.com with ESMTPSA id a2sm9894505wrt.82.2021.05.02.09.16.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:16:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SAjsdRT6m+/gb9YjtjeiORJfX3lsELt6a2iqeSZGiwI=; b=XjipVA66tmQ4OSa+3+g8g2YFcbKzAbSD74lHtglef11Z9zIgeZoZnbAN0rzGjK+tkL +JpLtFrwryWu3QuLsVcVP5aejivVYF51wC7B91Ty2iV9xcuPsX2X0e3Tv+hW/FtP49aY mNwbT6/fYSEy4BurpcpaM9/FPsBHlPEbxCF6wq+YEUnq1DDy1A8cFP83+UomODEV87GT m2wFDIFvWcgRfKw7oTIE8pu2+8SN4mXK8o734kpmlNS21rgFEW3GtbWA2KjQKZNTsMEr 2qk8ejPmxACdXIQDq9m/QHV5HT/e+fU/pYwRLg+AR5R7PJuTwZbjczBLgyFQ6s9Z6pHK An7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=SAjsdRT6m+/gb9YjtjeiORJfX3lsELt6a2iqeSZGiwI=; b=nMWF732zcf56zfnet0jRYx2mlIoJqsUdX3PP+3+9KYA4+6oxpav9K1Yq2kfQzYhtnC IAvpXmN4M4E5VXy/jS6UgKO12lUAFWUQr/1a1TXpP9ej/dYSxhVUP4XsRO5YpOVLHu7z 2myikIR4Sr2YD9Z/agfdHafpT0eJlveis18DlTuUi7qlNGWsjsiy8rsF0HiQU0+mgFPP k92d+2Qz6ZqI1x2TSIw+AFTgqmbz9uQxATRR4iyR7A2FfqgsVbr6RR3zhbZkBFOZNPZt kkDzgs0fccpxtU2oHgGYrsvOUzz6hLoBSsm4RM2uhKZ4w+9lKmARvPAvfJ6W5HDq/4n6 bv8g== X-Gm-Message-State: AOAM530FeaQVQ09JUVDAHQYWHGGJ0C4K57SFAK2YddWqGp7c5WIJgUI8 McSAvduT+wJRGopva78Eqks= X-Google-Smtp-Source: ABdhPJy1Bnip6k0IG0lqwjbDm2tKdLNZQo1eYNBri2pONhyFIZSjvD9B+L2OnNEP+UM/uDFrkQbkOA== X-Received: by 2002:adf:f205:: with SMTP id p5mr10671095wro.170.1619972213935; Sun, 02 May 2021 09:16:53 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 14/36] target/mips: Declare mips_env_set_pc() inlined in "internal.h" Date: Sun, 2 May 2021 18:15:16 +0200 Message-Id: <20210502161538.534038-15-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Rename set_pc() as mips_env_set_pc(), declare it inlined and use it in cpu.c and op_helper.c. Reported-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210428170410.479308-9-f4bug@amsat.org> --- target/mips/internal.h | 10 ++++++++++ target/mips/cpu.c | 8 +------- target/mips/op_helper.c | 16 +++------------- 3 files changed, 14 insertions(+), 20 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 57072a941e7..04f4b3d6614 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -219,6 +219,16 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, /* op_helper.c */ void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); =20 +static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value) +{ + env->active_tc.PC =3D value & ~(target_ulong)1; + if (value & 1) { + env->hflags |=3D MIPS_HFLAG_M16; + } else { + env->hflags &=3D ~(MIPS_HFLAG_M16); + } +} + static inline void restore_pamask(CPUMIPSState *env) { if (env->hflags & MIPS_HFLAG_ELPA) { diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 8f76f4576f4..a751c958329 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -327,14 +327,8 @@ void QEMU_NORETURN do_raise_exception_err(CPUMIPSState= *env, static void mips_cpu_set_pc(CPUState *cs, vaddr value) { MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; =20 - env->active_tc.PC =3D value & ~(target_ulong)1; - if (value & 1) { - env->hflags |=3D MIPS_HFLAG_M16; - } else { - env->hflags &=3D ~(MIPS_HFLAG_M16); - } + mips_env_set_pc(&cpu->env, value); } =20 #ifdef CONFIG_TCG diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index b80e8f75401..222a0d7c7b3 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -993,24 +993,14 @@ static void debug_post_eret(CPUMIPSState *env) } } =20 -static void set_pc(CPUMIPSState *env, target_ulong error_pc) -{ - env->active_tc.PC =3D error_pc & ~(target_ulong)1; - if (error_pc & 1) { - env->hflags |=3D MIPS_HFLAG_M16; - } else { - env->hflags &=3D ~(MIPS_HFLAG_M16); - } -} - static inline void exception_return(CPUMIPSState *env) { debug_pre_eret(env); if (env->CP0_Status & (1 << CP0St_ERL)) { - set_pc(env, env->CP0_ErrorEPC); + mips_env_set_pc(env, env->CP0_ErrorEPC); env->CP0_Status &=3D ~(1 << CP0St_ERL); } else { - set_pc(env, env->CP0_EPC); + mips_env_set_pc(env, env->CP0_EPC); env->CP0_Status &=3D ~(1 << CP0St_EXL); } compute_hflags(env); @@ -1036,7 +1026,7 @@ void helper_deret(CPUMIPSState *env) env->hflags &=3D ~MIPS_HFLAG_DM; compute_hflags(env); =20 - set_pc(env, env->CP0_DEPC); + mips_env_set_pc(env, env->CP0_DEPC); =20 debug_post_eret(env); } --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) client-ip=209.85.128.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1619972221; cv=none; d=zohomail.com; s=zohoarc; b=Xic4fFXMajleP9wcBSjbwpIOmobQuaJV/r9yK8qVpuUIiScb2Gwh7z6QQu8z9VFCIkOdGTCtVNSL3CXJdbEqelKCU1/pa2H4prZtzgR+eF8ZyaEfsKq6UZsrS9YWXr0vYAjdKJeNfsleNhUeaFAYUMKAPZqD2LE7baw5P06v9TY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972221; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=99Oig4N3wkTuBjvWFCoLaUR2inByyDBBLID8cJTmWr0=; b=LyaMSf/1K4FxkiqUyF4Z9fwJJa5aMu8ZPVl7qaxNs2TLdrxaBMQP8S2bbrrhjwG1s/ua5Wf/X3aKkEb1f16Ojbr2tBU33it2av4vxIfQmWIyxO6S5rqpYoY4MJ+n3OyOUsxMVZJBxFbiLhjN9srMWNiYJ4DwnjGqXrlVZ62i4Y8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) by mx.zohomail.com with SMTPS id 1619972221762277.44647796596394; Sun, 2 May 2021 09:17:01 -0700 (PDT) Received: by mail-wm1-f54.google.com with SMTP id k4-20020a7bc4040000b02901331d89fb83so2110040wmi.5 for ; Sun, 02 May 2021 09:17:01 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (anancy-651-1-208-144.w109-217.abo.wanadoo.fr. [109.217.237.144]) by smtp.gmail.com with ESMTPSA id c15sm9583182wrr.3.2021.05.02.09.16.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:16:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=99Oig4N3wkTuBjvWFCoLaUR2inByyDBBLID8cJTmWr0=; b=KM+vYxHpdY3V+kBbCdX891uOCkYBAvaTz+3+Sv/Vq37Z/gYuZHgR39BERWGhW+urYK QnaUXpaT4dnLXPcVoGeEIB3G6cBidj4V/zfdMz8grBOzRFmI9DElYCTeke1wbnGRPASt xTRlv0D5S+ei/F09dK49eeGooIjJxxvnRXHReuon4eXFRiRuKOXVTzLO5f49X+UivMgX FXLytGaPuWc8bnSqHh5FZLAn1mgZc2D0y4boW5KnMeYNjWiA0jxE2pXZa3CQE/ak8Asx LYgqdx+5j7OQ3WlSKcLVO576G9z6WdmOThkaxYC55G8zt9mlQDTOoN6o0akNz8oW73/w /Urw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=99Oig4N3wkTuBjvWFCoLaUR2inByyDBBLID8cJTmWr0=; b=nMDpw6p/VyWsntEg9BJ7SuZPNg2g6FSk8fUMFjo0xta7jfAYsqCk4IXPgPIS8khHfS A4YMLWGADBCImi1jj8Utaixk0FLU1Vk/wrPKJJutvxW3AaKlE2eR0EAv3vT82SKTQld0 RrhIWeWcwrxoD84A4Cy2ZUE8tOTF2ZC7GaM2wUahyXBGb2aTnKzH8NT44/6pYkkQ7InM 9b0g0LvnPKtYjguthHnEzVsAIpDp8Up1xTkPxP4ArmMApAuHKv44NmosoOVOd8aZRwZq JlKTpu446qhWb6HcrEBCTMrQFr/6AY8MejSgBXktotyahMa7xZ70Zz3IgHjOVw9b8BP9 ZD+g== X-Gm-Message-State: AOAM5334Ff0YI17g7pCL4IJdxxhIyoea1tDP6fg2qDWgjo2uHpnMcX5U AvlX/xLQ2Rkqz4W8U3XPdtI= X-Google-Smtp-Source: ABdhPJwMgDTAz8R9rGUss6ESPy/fXchZSH5oZgX2UhwKx2d5cRIDSYUDkxtod6jSzGFE6uU7qaz9Ow== X-Received: by 2002:a05:600c:4fd0:: with SMTP id o16mr4533101wmq.137.1619972220025; Sun, 02 May 2021 09:17:00 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 15/36] target/mips: Merge do_translate_address into cpu_mips_translate_address Date: Sun, 2 May 2021 18:15:17 +0200 Message-Id: <20210502161538.534038-16-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Currently cpu_mips_translate_address() calls raise_mmu_exception(), and do_translate_address() calls cpu_loop_exit_restore(). This API split is dangerous, we could call cpu_mips_translate_address without returning to the main loop. As there is only one caller, it is trivial (and safer) to merge do_translate_address() back to cpu_mips_translate_address(). Reported-by: Richard Henderson Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-10-f4bug@amsat.org> --- target/mips/internal.h | 2 +- target/mips/op_helper.c | 20 ++------------------ target/mips/tlb_helper.c | 11 ++++++----- 3 files changed, 9 insertions(+), 24 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 04f4b3d6614..e93e057bece 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -148,7 +148,7 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwadd= r physaddr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retadd= r); hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, - MMUAccessType access_type); + MMUAccessType access_type, uintptr_t ret= addr); #endif =20 #define cpu_signal_handler cpu_mips_signal_handler diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 222a0d7c7b3..61e68cc8bed 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -287,23 +287,6 @@ target_ulong helper_rotx(target_ulong rs, uint32_t shi= ft, uint32_t shiftx, =20 #ifndef CONFIG_USER_ONLY =20 -static inline hwaddr do_translate_address(CPUMIPSState *env, - target_ulong address, - MMUAccessType access_type, - uintptr_t retaddr) -{ - hwaddr paddr; - CPUState *cs =3D env_cpu(env); - - paddr =3D cpu_mips_translate_address(env, address, access_type); - - if (paddr =3D=3D -1LL) { - cpu_loop_exit_restore(cs, retaddr); - } else { - return paddr; - } -} - #define HELPER_LD_ATOMIC(name, insn, almask, do_cast) = \ target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_id= x) \ { = \ @@ -313,7 +296,8 @@ target_ulong helper_##name(CPUMIPSState *env, target_ul= ong arg, int mem_idx) \ } = \ do_raise_exception(env, EXCP_AdEL, GETPC()); = \ } = \ - env->CP0_LLAddr =3D do_translate_address(env, arg, MMU_DATA_LOAD, GETP= C()); \ + env->CP0_LLAddr =3D cpu_mips_translate_address(env, arg, MMU_DATA_LOAD= , \ + GETPC()); = \ env->lladdr =3D arg; = \ env->llval =3D do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC= ()); \ return env->llval; = \ diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index 8d3ea497803..1ffdc1f8304 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -904,21 +904,22 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, =20 #ifndef CONFIG_USER_ONLY hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, - MMUAccessType access_type) + MMUAccessType access_type, uintptr_t ret= addr) { hwaddr physical; int prot; int ret =3D 0; + CPUState *cs =3D env_cpu(env); =20 /* data access */ ret =3D get_physical_address(env, &physical, &prot, address, access_ty= pe, cpu_mmu_index(env, false)); - if (ret !=3D TLBRET_MATCH) { - raise_mmu_exception(env, address, access_type, ret); - return -1LL; - } else { + if (ret =3D=3D TLBRET_MATCH) { return physical; } + + raise_mmu_exception(env, address, access_type, ret); + cpu_loop_exit_restore(cs, retaddr); } =20 static void set_hflags_for_handler(CPUMIPSState *env) --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) client-ip=209.85.128.46; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f46.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; 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[109.217.237.144]) by smtp.gmail.com with ESMTPSA id g13sm5109544wrd.41.2021.05.02.09.17.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:17:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+BSxAg+QNnno53jdugbRrYx5ZtfO8FYfElFGGEXHpVo=; b=nHjbmXwnFuM0TJI9JQaEsfBmCq05Pt1CystoBmiXCm1Qp8v9E67a0RhrMeKIA+3a4a MtsP+kaby4Ks80+xex/+7ibjlu8HF8wAK1R8oNZ30YjFEyCIZzvNAyhQBR8yE7btivQI sthiK7KmqW2WNWL8mNIzBCawBaAV9SAbiqFVfIM5xUzOS2l/IXLh1l7GzIJGGcVvPEue +0B0lY7gmHv5WqZi1O0siMIlYeS7dGcp4eCA8rO0OYxz+9XUQ6cGBtq/caDPCW2qIQv4 886+B4c2BemF0Jy2X09DOCBCaUk1tcTMTjSUnyuKtOCpglViiqPTsCT8u64Vs20EqMHX 4RKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=+BSxAg+QNnno53jdugbRrYx5ZtfO8FYfElFGGEXHpVo=; b=EE6dYy+gNEI5NBrxb5h0L/LE2HmMUZm8mvLFyYOVTvmp/QHtvtajbFX278C9pX528s Bg0CI32H5yyXGKnmyGgJ0cZm7XXaoK2WNA5NTuHMAJKXi/A9OXhBzv5w00yyod/Sis3r lNapQzmaAZ5f7q1TuzBttP3A0+hvKJG7cvVkoC31b1REBEaJokAUL181B/7eOeiAr3WO AE6Avc8vGuQ85QKo0AvjVVJZRkud1rSE176bQv0kAvVuA2Ne4wpD4uIsR5z2HP6/WC64 UXrRkZUGpcKhkUC8TjCFGElPv7ssQzl+dPMXtj1ARvYCHS0UfQbEoq7nZsA5dShZYvWe pJnQ== X-Gm-Message-State: AOAM5325AgOB9al5PwvvctRShheQwBOC8rViDdNaaplKK5ap0l1Wd1rN 3wpaZySIzy7ijuZuQ8PSl/I= X-Google-Smtp-Source: ABdhPJxhKYtucNvJ10Vww9cx8+Z/lgGq5rqLSOusplwPrERLF5J/Oouk+77Kq8emVvXlhsnhDPgJ4Q== X-Received: by 2002:a1c:4302:: with SMTP id q2mr12145798wma.1.1619972225295; Sun, 02 May 2021 09:17:05 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 16/36] target/mips: Extract load/store helpers to ldst_helper.c Date: Sun, 2 May 2021 18:15:18 +0200 Message-Id: <20210502161538.534038-17-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-11-f4bug@amsat.org> --- target/mips/ldst_helper.c | 288 ++++++++++++++++++++++++++++++++++++++ target/mips/op_helper.c | 259 ---------------------------------- target/mips/meson.build | 1 + 3 files changed, 289 insertions(+), 259 deletions(-) create mode 100644 target/mips/ldst_helper.c diff --git a/target/mips/ldst_helper.c b/target/mips/ldst_helper.c new file mode 100644 index 00000000000..d42812b8a6a --- /dev/null +++ b/target/mips/ldst_helper.c @@ -0,0 +1,288 @@ +/* + * MIPS emulation load/store helpers for QEMU. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * SPDX-License-Identifier: LGPL-2.1-or-later + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "exec/exec-all.h" +#include "exec/memop.h" +#include "internal.h" + +#ifndef CONFIG_USER_ONLY + +#define HELPER_LD_ATOMIC(name, insn, almask, do_cast) = \ +target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_id= x) \ +{ = \ + if (arg & almask) { = \ + if (!(env->hflags & MIPS_HFLAG_DM)) { = \ + env->CP0_BadVAddr =3D arg; = \ + } = \ + do_raise_exception(env, EXCP_AdEL, GETPC()); = \ + } = \ + env->CP0_LLAddr =3D cpu_mips_translate_address(env, arg, MMU_DATA_LOAD= , \ + GETPC()); = \ + env->lladdr =3D arg; = \ + env->llval =3D do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC= ()); \ + return env->llval; = \ +} +HELPER_LD_ATOMIC(ll, ldl, 0x3, (target_long)(int32_t)) +#ifdef TARGET_MIPS64 +HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong)) +#endif +#undef HELPER_LD_ATOMIC + +#endif /* !CONFIG_USER_ONLY */ + +#ifdef TARGET_WORDS_BIGENDIAN +#define GET_LMASK(v) ((v) & 3) +#define GET_OFFSET(addr, offset) (addr + (offset)) +#else +#define GET_LMASK(v) (((v) & 3) ^ 3) +#define GET_OFFSET(addr, offset) (addr - (offset)) +#endif + +void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) +{ + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC()); + + if (GET_LMASK(arg2) <=3D 2) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), + mem_idx, GETPC()); + } + + if (GET_LMASK(arg2) <=3D 1) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), + mem_idx, GETPC()); + } + + if (GET_LMASK(arg2) =3D=3D 0) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, + mem_idx, GETPC()); + } +} + +void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) +{ + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); + + if (GET_LMASK(arg2) >=3D 1) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), + mem_idx, GETPC()); + } + + if (GET_LMASK(arg2) >=3D 2) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), + mem_idx, GETPC()); + } + + if (GET_LMASK(arg2) =3D=3D 3) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), + mem_idx, GETPC()); + } +} + +#if defined(TARGET_MIPS64) +/* + * "half" load and stores. We must do the memory access inline, + * or fault handling won't work. + */ +#ifdef TARGET_WORDS_BIGENDIAN +#define GET_LMASK64(v) ((v) & 7) +#else +#define GET_LMASK64(v) (((v) & 7) ^ 7) +#endif + +void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) +{ + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC()); + + if (GET_LMASK64(arg2) <=3D 6) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <=3D 5) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <=3D 4) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <=3D 3) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <=3D 2) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <=3D 1) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <=3D 0) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, + mem_idx, GETPC()); + } +} + +void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) +{ + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); + + if (GET_LMASK64(arg2) >=3D 1) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >=3D 2) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >=3D 3) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >=3D 4) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >=3D 5) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >=3D 6) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) =3D=3D 7) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), + mem_idx, GETPC()); + } +} +#endif /* TARGET_MIPS64 */ + +static const int multiple_regs[] =3D { 16, 17, 18, 19, 20, 21, 22, 23, 30 = }; + +void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) +{ + target_ulong base_reglist =3D reglist & 0xf; + target_ulong do_r31 =3D reglist & 0x10; + + if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { + target_ulong i; + + for (i =3D 0; i < base_reglist; i++) { + env->active_tc.gpr[multiple_regs[i]] =3D + (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()= ); + addr +=3D 4; + } + } + + if (do_r31) { + env->active_tc.gpr[31] =3D + (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()); + } +} + +void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) +{ + target_ulong base_reglist =3D reglist & 0xf; + target_ulong do_r31 =3D reglist & 0x10; + + if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { + target_ulong i; + + for (i =3D 0; i < base_reglist; i++) { + cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[= i]], + mem_idx, GETPC()); + addr +=3D 4; + } + } + + if (do_r31) { + cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETP= C()); + } +} + +#if defined(TARGET_MIPS64) +void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) +{ + target_ulong base_reglist =3D reglist & 0xf; + target_ulong do_r31 =3D reglist & 0x10; + + if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { + target_ulong i; + + for (i =3D 0; i < base_reglist; i++) { + env->active_tc.gpr[multiple_regs[i]] =3D + cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC()); + addr +=3D 8; + } + } + + if (do_r31) { + env->active_tc.gpr[31] =3D + cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC()); + } +} + +void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) +{ + target_ulong base_reglist =3D reglist & 0xf; + target_ulong do_r31 =3D reglist & 0x10; + + if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { + target_ulong i; + + for (i =3D 0; i < base_reglist; i++) { + cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[= i]], + mem_idx, GETPC()); + addr +=3D 8; + } + } + + if (do_r31) { + cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETP= C()); + } +} + +#endif /* TARGET_MIPS64 */ diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 61e68cc8bed..7a7369bc8a6 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -285,265 +285,6 @@ target_ulong helper_rotx(target_ulong rs, uint32_t sh= ift, uint32_t shiftx, return (int64_t)(int32_t)(uint32_t)tmp5; } =20 -#ifndef CONFIG_USER_ONLY - -#define HELPER_LD_ATOMIC(name, insn, almask, do_cast) = \ -target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_id= x) \ -{ = \ - if (arg & almask) { = \ - if (!(env->hflags & MIPS_HFLAG_DM)) { = \ - env->CP0_BadVAddr =3D arg; = \ - } = \ - do_raise_exception(env, EXCP_AdEL, GETPC()); = \ - } = \ - env->CP0_LLAddr =3D cpu_mips_translate_address(env, arg, MMU_DATA_LOAD= , \ - GETPC()); = \ - env->lladdr =3D arg; = \ - env->llval =3D do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC= ()); \ - return env->llval; = \ -} -HELPER_LD_ATOMIC(ll, ldl, 0x3, (target_long)(int32_t)) -#ifdef TARGET_MIPS64 -HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong)) -#endif -#undef HELPER_LD_ATOMIC -#endif - -#ifdef TARGET_WORDS_BIGENDIAN -#define GET_LMASK(v) ((v) & 3) -#define GET_OFFSET(addr, offset) (addr + (offset)) -#else -#define GET_LMASK(v) (((v) & 3) ^ 3) -#define GET_OFFSET(addr, offset) (addr - (offset)) -#endif - -void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, - int mem_idx) -{ - cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC()); - - if (GET_LMASK(arg2) <=3D 2) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), - mem_idx, GETPC()); - } - - if (GET_LMASK(arg2) <=3D 1) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), - mem_idx, GETPC()); - } - - if (GET_LMASK(arg2) =3D=3D 0) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, - mem_idx, GETPC()); - } -} - -void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, - int mem_idx) -{ - cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); - - if (GET_LMASK(arg2) >=3D 1) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), - mem_idx, GETPC()); - } - - if (GET_LMASK(arg2) >=3D 2) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), - mem_idx, GETPC()); - } - - if (GET_LMASK(arg2) =3D=3D 3) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), - mem_idx, GETPC()); - } -} - -#if defined(TARGET_MIPS64) -/* - * "half" load and stores. We must do the memory access inline, - * or fault handling won't work. - */ -#ifdef TARGET_WORDS_BIGENDIAN -#define GET_LMASK64(v) ((v) & 7) -#else -#define GET_LMASK64(v) (((v) & 7) ^ 7) -#endif - -void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, - int mem_idx) -{ - cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC()); - - if (GET_LMASK64(arg2) <=3D 6) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <=3D 5) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <=3D 4) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <=3D 3) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <=3D 2) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <=3D 1) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <=3D 0) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, - mem_idx, GETPC()); - } -} - -void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, - int mem_idx) -{ - cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); - - if (GET_LMASK64(arg2) >=3D 1) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >=3D 2) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >=3D 3) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >=3D 4) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >=3D 5) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >=3D 6) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) =3D=3D 7) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), - mem_idx, GETPC()); - } -} -#endif /* TARGET_MIPS64 */ - -static const int multiple_regs[] =3D { 16, 17, 18, 19, 20, 21, 22, 23, 30 = }; - -void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, - uint32_t mem_idx) -{ - target_ulong base_reglist =3D reglist & 0xf; - target_ulong do_r31 =3D reglist & 0x10; - - if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { - target_ulong i; - - for (i =3D 0; i < base_reglist; i++) { - env->active_tc.gpr[multiple_regs[i]] =3D - (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()= ); - addr +=3D 4; - } - } - - if (do_r31) { - env->active_tc.gpr[31] =3D - (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()); - } -} - -void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, - uint32_t mem_idx) -{ - target_ulong base_reglist =3D reglist & 0xf; - target_ulong do_r31 =3D reglist & 0x10; - - if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { - target_ulong i; - - for (i =3D 0; i < base_reglist; i++) { - cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[= i]], - mem_idx, GETPC()); - addr +=3D 4; - } - } - - if (do_r31) { - cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETP= C()); - } -} - -#if defined(TARGET_MIPS64) -void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, - uint32_t mem_idx) -{ - target_ulong base_reglist =3D reglist & 0xf; - target_ulong do_r31 =3D reglist & 0x10; - - if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { - target_ulong i; - - for (i =3D 0; i < base_reglist; i++) { - env->active_tc.gpr[multiple_regs[i]] =3D - cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC()); - addr +=3D 8; - } - } - - if (do_r31) { - env->active_tc.gpr[31] =3D - cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC()); - } -} - -void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, - uint32_t mem_idx) -{ - target_ulong base_reglist =3D reglist & 0xf; - target_ulong do_r31 =3D reglist & 0x10; - - if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { - target_ulong i; - - for (i =3D 0; i < base_reglist; i++) { - cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[= i]], - mem_idx, GETPC()); - addr +=3D 8; - } - } - - if (do_r31) { - cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETP= C()); - } -} -#endif - - void helper_fork(target_ulong arg1, target_ulong arg2) { /* diff --git a/target/mips/meson.build b/target/mips/meson.build index daf5f1d55bc..15c2f835c68 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -18,6 +18,7 @@ mips_tcg_ss.add(files( 'dsp_helper.c', 'fpu_helper.c', + 'ldst_helper.c', 'lmmi_helper.c', 'msa_helper.c', 'msa_translate.c', --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) client-ip=209.85.128.46; envelope-from=philippe.mathieu.daude@gmail.com; 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[109.217.237.144]) by smtp.gmail.com with ESMTPSA id m13sm8825049wrw.86.2021.05.02.09.17.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:17:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=J/y1ixRwBU6yKoocpZNA8qfYNVL0ZltPQY4AVdwAq4I=; b=noUWPLgKsVjTTgmEy8LgLDNOM1xdGOCzVGH8yThHmdZIIRLC5Ay1hL0m0aMytyGobE qPAgsgbZsAFacM4t5LgUdl9EbkVrsoSvciTii17Lq/bWps8sZPJ9wgK5NCssMcr/VglP CyPky/DlXB4lbDBNyn/Akx/E/0nMbeNEmWYhjSY+sZ2Vgn/LqSkR73bMBt2DZv55kgx1 sMjs46lEVYm4MRx3e7nwcXtvosDSafxiDpEGwz3+5dLGSXKU3tExkgI+cqzpDoQJ9AFD 8CRDsuVErzbmRpwLEwMmU+kKqMsYIQcK5at+oJFkz8A0LW7LJCPDM2QDp+MMggsgnEKA 5RVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=J/y1ixRwBU6yKoocpZNA8qfYNVL0ZltPQY4AVdwAq4I=; b=E/hkHneJODN5QeNBlZUBps5gl8WA85VrnGdV+WdUto/gvTV/oO7u6gj2owe9notHW4 sV8RSyYB1LOh4Re9rVMBvjbMjJadXi4tlY1+bDU2febvF4wgKdKGyoKoJRlXgVilwVSs kxhxwyXiaoFBwt4ZsScwNZ6wptCKvNc3OpXiWboadsDQSbyoh5ZHa5Ji5q1SMHdah2n0 Ea3nmokZ95tWwjcac8fkUR5p3TyqMD8c2/+B/dwhj7Xl9SzoelBDEjgGa4SLHiQqQIqF Fn0jmxpA02kE6HYhcaEm+DkAaEsX00V0hDoWxwU4PbWHr69KSrTXH9/w6uB6waJkLiEy 9qlg== X-Gm-Message-State: AOAM530cfyImwNEcVW/jV5Bi/js/yw63zdPFPnb5YwpB82Q/d/8rx01y F5F8cyr03+oSpNgH/QPHFyU= X-Google-Smtp-Source: ABdhPJzTD3jA62IrOJjyg97VIgSkW25mLucuZExZdOfY8Mg1nNsaJaYNYsmYdCY4FeLzIilh+oD3rA== X-Received: by 2002:a7b:c047:: with SMTP id u7mr27849375wmc.98.1619972230294; Sun, 02 May 2021 09:17:10 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 17/36] meson: Introduce meson_user_arch source set for arch-specific user-mode Date: Sun, 2 May 2021 18:15:19 +0200 Message-Id: <20210502161538.534038-18-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Similarly to the 'target_softmmu_arch' source set which allows to restrict target-specific sources to system emulation, add the equivalent 'target_user_arch' set for user emulation. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-12-f4bug@amsat.org> --- meson.build | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/meson.build b/meson.build index d8bb1ec5aa9..1ffdc9e6c4e 100644 --- a/meson.build +++ b/meson.build @@ -1751,6 +1751,7 @@ hw_arch =3D {} target_arch =3D {} target_softmmu_arch =3D {} +target_user_arch =3D {} =20 ############### # Trace files # @@ -2168,6 +2169,11 @@ abi =3D config_target['TARGET_ABI_DIR'] target_type=3D'user' qemu_target_name =3D 'qemu-' + target_name + if arch in target_user_arch + t =3D target_user_arch[arch].apply(config_target, strict: false) + arch_srcs +=3D t.sources() + arch_deps +=3D t.dependencies() + endif if 'CONFIG_LINUX_USER' in config_target base_dir =3D 'linux-user' target_inc +=3D include_directories('linux-user/host/' / config_host= ['ARCH']) --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) client-ip=209.85.221.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619972236; cv=none; d=zohomail.com; s=zohoarc; b=HOapNZ7gAxTxL4OQNwkQU/Czd7gpQs/r7rcHhvW4Ts+c6rIN8vJcjvm1zIOGfa5/5sudgDB/H2Db4G1faMvS0m+gxHfAPec9d4VE/yguFXtwiDXBs+BOl8r2tpbuYmPFsKST2y0xAziQa3Bep8PU3eYa8FY6n1Fxo8lW09BdJ30= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972236; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HO4kVKQpXVHCbWKcXA+wAgV5vQ4RCJonvqTRm6Lg8wM=; b=nS1slmBgpiLgOboeuBNdJOVh4UvDviUXLcgPr0v0TXFKienFYi7qVVUG0zOHDaKypuGgH2Xg6HTEdRbejsqWcCj5brE4A37e8OnlmqtXJtoTzC8bEGk05ac2wwLdyFYwj4/omCcrYY9BxHM62OMWaFcGewalR4bWLUUXbTT6NTg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) by mx.zohomail.com with SMTPS id 1619972236920802.5070980101001; Sun, 2 May 2021 09:17:16 -0700 (PDT) Received: by mail-wr1-f43.google.com with SMTP id l2so3087550wrm.9 for ; Sun, 02 May 2021 09:17:16 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (anancy-651-1-208-144.w109-217.abo.wanadoo.fr. [109.217.237.144]) by smtp.gmail.com with ESMTPSA id x4sm2745743wmj.17.2021.05.02.09.17.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:17:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HO4kVKQpXVHCbWKcXA+wAgV5vQ4RCJonvqTRm6Lg8wM=; b=ssBT5LTihEouAFiOZoveFfJ3qnTLdE8cC175rvFZIx1q2/FgUDONIZOxiAeCJs6ZjM YUexbvLKG3gCJlqiyzoOrn8OBMv6F/5mNajCdYs9bJxAMPmG3AxdFffKpelOfMVLV7Ce 0hNXFyAvflP94dZhgFWeaGTeaXVcJdBkdnlYqMgFkHM76sibwBiP04CRxFPul3cUErJy rH8hA0HmXbFaeVhR5yz0faR59Usjk+ONpoF3EZOhHhixcOmXA9o3X4Y/54ZvNhHgJ99j 0ZuS//KMY0uSJmhK6WGC/fyHyXW/CzlpGw6YpkfwYfLw9ItqGUD8iF7Apc+dc3Cs77Iz kCQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=HO4kVKQpXVHCbWKcXA+wAgV5vQ4RCJonvqTRm6Lg8wM=; b=rbkROet/cbSBldaP/ME0JYtqgtcGqn5tMs29mF6c3VR1ccxkbpTI3GqLlRuJr/uUfX SoVwGHeVLcrMj1evhPS6idUXP9Im4Tv0dFhPYQrEdvayrIVHfTKk6UHCCg9/p8g2MruK bBnrIIdA0mTEBWlFeLAml1HTDdlYGx9zmcnYDHzP05CWYefBjC8k+emql8jhyebeQJ1p S70VYVo5mDBGQKmwY+hpm4/G3Mxf0DoDJcsfQ0SzV6oUCH9R0lmllexaRv/RiAVbXHnF RIQ98tUqCKvzMZ4aOBidi7cgg/ZMwdE2J2LqGfgz68KeyZsrCDqWpDCDABNIyPs1u/K9 Pq3A== X-Gm-Message-State: AOAM530w0KIYmufanFH5QkcgnU7QleM10mdCxdX7U+qtjR5dXYspgkR9 aUGNhBEBxVQK2R6u44r/cSk= X-Google-Smtp-Source: ABdhPJyIcUI9jO+QrbAP8GcH4E4U+ZaFXcLi2Gwog3jhi5Ld1Z/1gDnlpIl5AxUbAN5vZ342AbShYA== X-Received: by 2002:a05:6000:50d:: with SMTP id a13mr3045326wrf.130.1619972235225; Sun, 02 May 2021 09:17:15 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 18/36] target/mips: Introduce tcg-internal.h for TCG specific declarations Date: Sun, 2 May 2021 18:15:20 +0200 Message-Id: <20210502161538.534038-19-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We will gradually move TCG-specific declarations to a new local header: "tcg-internal.h". To keep review simple, first add this header with 2 TCG prototypes, which we are going to move in the next 2 commits. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-13-f4bug@amsat.org> --- target/mips/internal.h | 7 +++---- target/mips/tcg/tcg-internal.h | 20 ++++++++++++++++++++ 2 files changed, 23 insertions(+), 4 deletions(-) create mode 100644 target/mips/tcg/tcg-internal.h diff --git a/target/mips/internal.h b/target/mips/internal.h index e93e057bece..754135c1421 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -9,6 +9,9 @@ #define MIPS_INTERNAL_H =20 #include "exec/memattrs.h" +#ifdef CONFIG_TCG +#include "tcg/tcg-internal.h" +#endif =20 /* * MMU types, the first four entries have the same layout as the @@ -77,7 +80,6 @@ extern const char fregnames[32][4]; extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; =20 -void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); @@ -212,9 +214,6 @@ void cpu_mips_stop_count(CPUMIPSState *env); =20 /* helper.c */ void mmu_init(CPUMIPSState *env, const mips_def_t *def); -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); =20 /* op_helper.c */ void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h new file mode 100644 index 00000000000..24438667f47 --- /dev/null +++ b/target/mips/tcg/tcg-internal.h @@ -0,0 +1,20 @@ +/* + * MIPS internal definitions and helpers (TCG accelerator) + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef MIPS_TCG_INTERNAL_H +#define MIPS_TCG_INTERNAL_H + +#include "hw/core/cpu.h" + +void mips_cpu_do_interrupt(CPUState *cpu); +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + +#endif --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) client-ip=209.85.128.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619972241; cv=none; d=zohomail.com; s=zohoarc; b=M/BHyBcTnvGbAujI+/bbm2BFCJmdPqDAtNEv55yd5saxd1DoQindB+XT74+S1R/7qL/R6P24HQ65DIV3z57m+TE1RQW2uqKgrs4VzJp8SkpF6A7hzO6Kw/42xvGauBw2caRA6TkdtoKWW9GtPZuenPUCGKkH3/JsjEfJhNEYxys= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972241; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fPxVO8YxYE573bf/ors7hmJKmVbhQk08qkmo13FNuuU=; b=caM9aUYSCp1In4fA+blyHCnM4Sg0D14tId/gCKlVRXyAMEZFyBPTzMtwbMqXlEcAbTJfKXZeu4LTIFrJJXeFNIrqzoaeOJpKrPXuMaW/tnFmQRWR0nwDa2hxv9MuYoTYu2hz9oiJN6R52SVb1yXx1pun4VN06P+yWp4Zlxec69g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) by mx.zohomail.com with SMTPS id 1619972241925956.0823307992654; Sun, 2 May 2021 09:17:21 -0700 (PDT) Received: by mail-wm1-f51.google.com with SMTP id n205so1036528wmf.1 for ; Sun, 02 May 2021 09:17:21 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (anancy-651-1-208-144.w109-217.abo.wanadoo.fr. [109.217.237.144]) by smtp.gmail.com with ESMTPSA id v15sm12078430wmj.39.2021.05.02.09.17.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:17:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fPxVO8YxYE573bf/ors7hmJKmVbhQk08qkmo13FNuuU=; b=XPfz2xjfb9fjMJUYM/M1q7UkoqPUzVRJpzvnjbUQAvIHWdIzw1fWzsNxbgGWGon08c uz3Ebsw4UuSMCAqYsJ52CCrOGLB/CtgdgEVdlMHgpncidOiYMlYiNIHY0deJnBnZneRD vEmqDTQ1C+GloHurT4sm1ROzg4SFa56V29S+mmx5AkZV/XUCk/jjQWUFf/4LWcinavPg nIZQV+pj1QWwLW50yuceMHlf6c9v+EE04vYHuDXhgdsBu46Io9vC8xsikUd1Tqw3nuMT wD+dcPDhNprBoyFSXfIx1KOlcaYQ/qL3YDZi9RPeWJsT77s8wgmuoctOPxVsn1ncfeKz HQAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=fPxVO8YxYE573bf/ors7hmJKmVbhQk08qkmo13FNuuU=; b=cgBdaVcX4dcOrOX1Wt73TgVQX3H4Nv633gmzVb/RLtQHLZ7z/Sf9s2thdqSu53qMh2 mNaz9aKQ66XXyY0emCbwvArpmDekp5jvP9GtGX/hBURtCcHZEhfjTSfwEH7Z94bvl4V4 4AEKRUEF31qmDtr1On/ktTdMIhZIS73h7UYcynG2RNSoybCHyFirhMOcDAkF5cADH7jW Q7acP9DdfdvOHIz7DaK/vumJf02TzcsbN5i/wgVVFRVPn/VF+beGh+8qb+r6xzOMo6wT lcZNxQkMX79zLC1ZTqCpntwS9cBfzGV8xBsCMo4onQmXewC6yTdoicVL1XQQfsg5zXmt Kdhw== X-Gm-Message-State: AOAM530QhiYR1fbb9K8sY11j5ll7hn5MHmKV+u3X2kmvpslzQ+VmD3X6 fnJxPbhIabCGATsXQUcceM8= X-Google-Smtp-Source: ABdhPJwowWiVf+cd1CrcreLlsGFIaq45pT0EffdZkMXG1eYZt9VnAZVuXj9WQME09XUX3x7DzfYvWQ== X-Received: by 2002:a1c:f715:: with SMTP id v21mr17381384wmh.187.1619972240179; Sun, 02 May 2021 09:17:20 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 19/36] target/mips: Add simple user-mode mips_cpu_do_interrupt() Date: Sun, 2 May 2021 18:15:21 +0200 Message-Id: <20210502161538.534038-20-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The #ifdef'ry hides that the user-mode implementation of mips_cpu_do_interrupt() simply sets exception_index =3D EXCP_NONE. Add this simple implementation to tcg/user/tlb_helper.c, and the corresponding Meson machinery to build this file when user emulation is configured. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-14-f4bug@amsat.org> --- target/mips/tcg/user/tlb_helper.c | 28 ++++++++++++++++++++++++++++ target/mips/tlb_helper.c | 5 ----- target/mips/meson.build | 5 +++++ target/mips/tcg/meson.build | 3 +++ target/mips/tcg/user/meson.build | 3 +++ 5 files changed, 39 insertions(+), 5 deletions(-) create mode 100644 target/mips/tcg/user/tlb_helper.c create mode 100644 target/mips/tcg/meson.build create mode 100644 target/mips/tcg/user/meson.build diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_h= elper.c new file mode 100644 index 00000000000..453b9e9b930 --- /dev/null +++ b/target/mips/tcg/user/tlb_helper.c @@ -0,0 +1,28 @@ +/* + * MIPS TLB (Translation lookaside buffer) helpers. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ +#include "qemu/osdep.h" + +#include "cpu.h" +#include "exec/exec-all.h" +#include "internal.h" + +void mips_cpu_do_interrupt(CPUState *cs) +{ + cs->exception_index =3D EXCP_NONE; +} diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index 1ffdc1f8304..78720c4d20a 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -965,11 +965,8 @@ static inline void set_badinstr_registers(CPUMIPSState= *env) } } =20 -#endif /* !CONFIG_USER_ONLY */ - void mips_cpu_do_interrupt(CPUState *cs) { -#if !defined(CONFIG_USER_ONLY) MIPSCPU *cpu =3D MIPS_CPU(cs); CPUMIPSState *env =3D &cpu->env; bool update_badinstr =3D 0; @@ -1272,11 +1269,9 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, env->CP0_DEPC); } -#endif cs->exception_index =3D EXCP_NONE; } =20 -#if !defined(CONFIG_USER_ONLY) void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) { CPUState *cs =3D env_cpu(env); diff --git a/target/mips/meson.build b/target/mips/meson.build index 15c2f835c68..ca3cc62cf7a 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -6,6 +6,7 @@ decodetree.process('tx79.decode', extra_args: '--static-decode=3Ddecode_= tx79'), ] =20 +mips_user_ss =3D ss.source_set() mips_ss =3D ss.source_set() mips_ss.add(files( 'cpu.c', @@ -34,6 +35,9 @@ ), if_false: files( 'mxu_translate.c', )) +if 'CONFIG_TCG' in config_all + subdir('tcg') +endif =20 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 @@ -52,3 +56,4 @@ =20 target_arch +=3D {'mips': mips_ss} target_softmmu_arch +=3D {'mips': mips_softmmu_ss} +target_user_arch +=3D {'mips': mips_user_ss} diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build new file mode 100644 index 00000000000..b74fa04303e --- /dev/null +++ b/target/mips/tcg/meson.build @@ -0,0 +1,3 @@ +if have_user + subdir('user') +endif diff --git a/target/mips/tcg/user/meson.build b/target/mips/tcg/user/meson.= build new file mode 100644 index 00000000000..79badcd3217 --- /dev/null +++ b/target/mips/tcg/user/meson.build @@ -0,0 +1,3 @@ +mips_user_ss.add(files( + 'tlb_helper.c', +)) --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.45 as permitted sender) client-ip=209.85.128.45; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f45.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619972247; cv=none; d=zohomail.com; s=zohoarc; b=ebElwc56DuF049932mpgjDs6/cVJe3sSed26duvG86c5xzAMspiCH+24JJGUW4+TsRWhlsaWgFY87SbEE6RLvJ72pG0qRzT+4no6yPvH2++CAxlRQqnTAa3E1IOg2N2xow9YE7T/q5boddTK0iW8XzuBC3tUax4D8Pbf/c6b5hY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972247; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/fMkH6Q98B3JkGJr/ySJUTql2HNV5/mMZqqV/6nG+Ag=; b=ELlPu9Fj1b3teresj7m9WkDfLC3CYlxsU+ipvAqn+EjsrT02uxCGMZhfkLMp5qH1E3nRQ+DdIjawIzDz0Kjh1ejvxTDGX+EZxnkKChdHjTjseBwO1g8AieUHz8ZNsSn+om1yvobkirGv1srIif5AAnzGp0tLaKjRP7QfMKe4Lu8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) by mx.zohomail.com with SMTPS id 1619972246872504.5235406336508; Sun, 2 May 2021 09:17:26 -0700 (PDT) Received: by mail-wm1-f45.google.com with SMTP id j3-20020a05600c4843b02901484662c4ebso2728640wmo.0 for ; Sun, 02 May 2021 09:17:26 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (anancy-651-1-208-144.w109-217.abo.wanadoo.fr. [109.217.237.144]) by smtp.gmail.com with ESMTPSA id 61sm9880095wrm.52.2021.05.02.09.17.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:17:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/fMkH6Q98B3JkGJr/ySJUTql2HNV5/mMZqqV/6nG+Ag=; b=CPS1nV3CNHVwuG1Br3ug1CYOtSfQ1JkVvaNt7Mc+Pazkd/pJQn/t3PqiwyMj5uM5Ot nVRS6qhfeWpejwT56I/Dr0Jn51yWh7UUzPnKLPA/AfNPoxyva5ief5kZvd5qNkX2Ir3C oqIbXGyNTcACUn/zCU8rXknnL2xQ4oNBSawMJlf6H9BCCPS+dKJm+2PbJSNzrglI9/dm 4WAEvxwzfNlS53Dur1x0hDDxuBRCeZMd1HEHvY/QoEW5YTWsT3gV4vRBPHRqja5Zl1W+ 3pyKFBYXu1jU/VSIWHVxc5t2TRoY4/fGNiGZmV4njummbS/eokY+bvjdzq3K9hjiWCdw K1Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=/fMkH6Q98B3JkGJr/ySJUTql2HNV5/mMZqqV/6nG+Ag=; b=ijlM2iY4TwxNz6wxjFSPgRLU7tZpY7APE0MzPBWsF44tmP5jA5/wmG/IqA4udEhOPD o4+zmhKpCoUIWe9ZF56SGiJNQQmj86yq09qQmIpWl8nKYK5M/ohEMoKr4osovTo9SbTT C1VxO4EKivZRLPuIkUTNXsXM9ydRBKX/8790OfpT8OrJOkXHaa98BVEDGUuDXYk/W69u v56S3YPzUGoL9g7xzj5ChXutMco6B8DUzSokZwJmrmgOxJ5FYbHdzpaNa8TksxonStHq RsJYnRm9M/sUsx8qetMaiadxFQ3ix5luMfjI5+WmjYXmNwwu+xynn0D+3ixU3/WU80Gl rMHA== X-Gm-Message-State: AOAM5321CrC9saeXDQAhbnYlnLR4SlFYkPT0KjDZwPhC4ZED6SJEkqAe qwA7TU0UROR/wuNOzFRPP5Q= X-Google-Smtp-Source: ABdhPJymbjOlwS51uImZYhTyzujVaJflRv7l0kfzh4iHMM8eO/7RCoGgJ6I8x4VaNQcRCA4UVX1oPA== X-Received: by 2002:a1c:4382:: with SMTP id q124mr16900765wma.63.1619972245140; Sun, 02 May 2021 09:17:25 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 20/36] target/mips: Add simple user-mode mips_cpu_tlb_fill() Date: Sun, 2 May 2021 18:15:22 +0200 Message-Id: <20210502161538.534038-21-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) tlb_helper.c's #ifdef'ry hides a quite simple user-mode implementation of mips_cpu_tlb_fill(). Copy the user-mode implementation (without #ifdef'ry) to tcg/user/helper.c and simplify tlb_helper.c's #ifdef'ry. This will allow us to restrict tlb_helper.c to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-15-f4bug@amsat.org> --- target/mips/tcg/user/tlb_helper.c | 36 +++++++++++++++++++++++++++++++ target/mips/tlb_helper.c | 10 --------- 2 files changed, 36 insertions(+), 10 deletions(-) diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_h= elper.c index 453b9e9b930..b835144b820 100644 --- a/target/mips/tcg/user/tlb_helper.c +++ b/target/mips/tcg/user/tlb_helper.c @@ -22,6 +22,42 @@ #include "exec/exec-all.h" #include "internal.h" =20 +static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, + MMUAccessType access_type) +{ + CPUState *cs =3D env_cpu(env); + + env->error_code =3D 0; + if (access_type =3D=3D MMU_INST_FETCH) { + env->error_code |=3D EXCP_INST_NOTAVAIL; + } + + /* Reference to kernel address from user mode or supervisor mode */ + /* Reference to supervisor address from user mode */ + if (access_type =3D=3D MMU_DATA_STORE) { + cs->exception_index =3D EXCP_AdES; + } else { + cs->exception_index =3D EXCP_AdEL; + } + + /* Raise exception */ + if (!(env->hflags & MIPS_HFLAG_DM)) { + env->CP0_BadVAddr =3D address; + } +} + +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + /* data access */ + raise_mmu_exception(env, address, access_type); + do_raise_exception_err(env, cs->exception_index, env->error_code, reta= ddr); +} + void mips_cpu_do_interrupt(CPUState *cs) { cs->exception_index =3D EXCP_NONE; diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index 78720c4d20a..afc019c80dd 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -403,8 +403,6 @@ void cpu_mips_tlb_flush(CPUMIPSState *env) env->tlb->tlb_in_use =3D env->tlb->nb_tlb; } =20 -#endif /* !CONFIG_USER_ONLY */ - static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, MMUAccessType access_type, int tlb_error) { @@ -484,8 +482,6 @@ static void raise_mmu_exception(CPUMIPSState *env, targ= et_ulong address, env->error_code =3D error_code; } =20 -#if !defined(CONFIG_USER_ONLY) - hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { MIPSCPU *cpu =3D MIPS_CPU(cs); @@ -833,7 +829,6 @@ refill: return true; } #endif -#endif /* !CONFIG_USER_ONLY */ =20 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, @@ -841,14 +836,11 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, { MIPSCPU *cpu =3D MIPS_CPU(cs); CPUMIPSState *env =3D &cpu->env; -#if !defined(CONFIG_USER_ONLY) hwaddr physical; int prot; -#endif int ret =3D TLBRET_BADADDR; =20 /* data access */ -#if !defined(CONFIG_USER_ONLY) /* XXX: put correct access by using cpu_restore_state() correctly */ ret =3D get_physical_address(env, &physical, &prot, address, access_type, mmu_idx); @@ -896,13 +888,11 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, if (probe) { return false; } -#endif =20 raise_mmu_exception(env, address, access_type, ret); do_raise_exception_err(env, cs->exception_index, env->error_code, reta= ddr); } =20 -#ifndef CONFIG_USER_ONLY hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, MMUAccessType access_type, uintptr_t ret= addr) { --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) client-ip=209.85.221.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619972251; cv=none; d=zohomail.com; s=zohoarc; b=npv+GWh1A2L3W3z4c6Fy/e7RPlfchrhbd89Q/VyvwKFRgHAa+PnCd3q0AGMHqXtcjcibyxmC2Gqf+Ba8IgYCLuKms24qLaoqu1igz68Xbw2aRY1dq/Gk2muEvwSJLGnHl5WEqjfPmP4vkW1cDCrJS0AQMcjOm7uroFUMaUUZ01Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972251; 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[109.217.237.144]) by smtp.gmail.com with ESMTPSA id q7sm9264544wrr.62.2021.05.02.09.17.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:17:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aRwpX/8Cx1qFim5Lxwv/XxTDijvHeV79c3pumAeSJhI=; b=U5XJDP0Wsdzm30fty0bgu43F9f5TBt/amse2frvrDh5laGODTZEFCFFV2eTaNy4IBV koa5pB+YWTKwAr/JZlNP4sX+IW9yL9qEz20w3tfCDJ9Xs9QBwkZRkrueRiFptSVKAmgj RQcY4U/5mfUNqDGFp5ekPvPPbVAo03bDV9mjPfdUxGiA4TThSkO2OGKJTL3HNtVC64Z2 CfjGdqxqhdFvuawxGmgLEuqjn+VymqaTlfeL+8M+2GKeYCfc9kBTia18HSTccZ2qksWH J+Wro/t03wH9qKt8+0xJEE2sAT32nGg1dWcErGWric/Mm2EeRJIVPhC8YuIHjyB4IS/B wYzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=aRwpX/8Cx1qFim5Lxwv/XxTDijvHeV79c3pumAeSJhI=; b=J8jq7MTwkkI7A7RtJOOQ9q9Lh1Vp4HYtJpSGPjaWFI2gUMlmxZLVkkSGt6exb4fFH8 Pd5I8lZq4m2MQX9YyxPQ5UDYGbayJmrJbuWxLliTHFu2ZL+SBpW0w1J7Tt84lhL495UT v3vzm5JPQbZy4WWAcipUyx5wqIPHKB7kWdTKjfKdB5Zd124t9VC4/Is3C7oyrByY42QH 3azRU9s3CT1L2UPWZv6garfzigQuc7qZxhACTNHsb2uJlNYYnv/iiCmkyuHm/TsFBZw0 62PvutZ+D+PQSgApZESuX79jG3k+eUUcV6SUWdfvWjDF7RnW1B9Nt9OvFekVH1HE+a0P ZaGA== X-Gm-Message-State: AOAM530o7z4h8WslZ2CYkk66C0xNC6gIOf9in0feepAPOlrgURML9RHj hqnhtgGxuv5Mx/j79hkS40g= X-Google-Smtp-Source: ABdhPJyyMo5UUEPEqiyVU7gYLEKjuYDeYvBCWZUbIPIUtIbztVI5Sts8K7oWd4+CzfNxhZAIsW3BSQ== X-Received: by 2002:a5d:698f:: with SMTP id g15mr16134549wru.316.1619972250014; Sun, 02 May 2021 09:17:30 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 21/36] target/mips: Move cpu_signal_handler definition around Date: Sun, 2 May 2021 18:15:23 +0200 Message-Id: <20210502161538.534038-22-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We have 2 blocks guarded with #ifdef for sysemu, which are simply separated by the cpu_signal_handler definition. To simplify the following commits which involve various changes in internal.h, first join the sysemu-guarded blocks. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-16-f4bug@amsat.org> --- target/mips/internal.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 754135c1421..3c8ccfbe929 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -151,14 +151,13 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwa= ddr physaddr, MemTxResult response, uintptr_t retadd= r); hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, MMUAccessType access_type, uintptr_t ret= addr); -#endif + +extern const VMStateDescription vmstate_mips_cpu; + +#endif /* !CONFIG_USER_ONLY */ =20 #define cpu_signal_handler cpu_mips_signal_handler =20 -#ifndef CONFIG_USER_ONLY -extern const VMStateDescription vmstate_mips_cpu; -#endif - static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) { return (env->CP0_Status & (1 << CP0St_IE)) && --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) client-ip=209.85.128.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619972256; cv=none; d=zohomail.com; s=zohoarc; b=DHzQbLdr+Lh8ug9xELyhZaoIfj8lr2mlZejh+mwQUZsnZOiZXaIIzIGE43WsZdhWV4NQckNch2cngW0Ck+1KrPLV5LqjuyEn0cn5biHrcLFhCWWNtKPzTK/M7vlARyuGJYnZZoRfQVqRmzoSttUvXqxp3Hm6zPy+I+wr2Ewj7gI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972256; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WVwQyksNWdrjcIF4p/5zEaubeV4UBzzGXqsE5aq1wp8=; b=JT8J//Intd+1Vb9MhSl0S83zkj9+yXoAAZrMlvFfZXLFBPw7eeI0hRJaEQD2rvpoofBaDy+EU6d6fh0o+oBs8Dy5LqPvdAC3DcGBWhub0roreh7WEIn2KRjOXxZkPKapVPMEBrE7RaLF1g8+HHUIulzb0lFOYn9l95kn1R/udjk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) by mx.zohomail.com with SMTPS id 1619972256667208.0187562878125; Sun, 2 May 2021 09:17:36 -0700 (PDT) Received: by mail-wm1-f42.google.com with SMTP id s82so1921477wmf.3 for ; Sun, 02 May 2021 09:17:36 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (anancy-651-1-208-144.w109-217.abo.wanadoo.fr. [109.217.237.144]) by smtp.gmail.com with ESMTPSA id x64sm8813903wmg.46.2021.05.02.09.17.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:17:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WVwQyksNWdrjcIF4p/5zEaubeV4UBzzGXqsE5aq1wp8=; b=cA2MVBQRllmo5GnPyUjN4Rrw/hLsoJPmJ9xJKtavWGnuN+/gi8g2Qrav3At1L8WxUt QUyw5dmnJiElMhza0VnSjcl1blw2ZM3lMZUloY5cWPfMHX5LP4Mgqml8AEcQHpMnVPGb ksNJUAL2xFvbO8P5Jp9JQ3C5+UFNzrnIuDoVVLEBGji144iVIEXYDHZ91pC+V5Ay4A60 h9Z6NkM8RWLvTMqwFDmYE6ajjw1fazNyWj4zatQNmg3wPyWfhjiv4aSB3Cy3KY9aayc/ U7jJ/+ChiTKyl0gzivq/UkaLGRJBSJM8oWtzm8nPMh5R15wELGJ8qTHCSVB9TvChxPO6 S5Uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=WVwQyksNWdrjcIF4p/5zEaubeV4UBzzGXqsE5aq1wp8=; b=OY2RnDje6yGt1k9ylMb3s0O/Qn+WSV7fOOzJKPwVxsFAgijU19jiKmpiLRH1v+O5UR VN5s4xOL44yNskFito0jzhE3PHNcF2dT2GVbJUj2hz+nsgYpNZz36wP+WGQKm7kf3FxW 7ryshRyYYg/sGGgh7PmFQFQg9T2FK5/p7AksbC4CSjFEULc3xJNjdYZgbIdAL7526e6R 65SaTWffF9+DHJiCoZgsBgNLE3QlzISMDZGZt1v++pp0bvJIFPbE5/fX8sIFI7tM/vlV m+T4c0GukKiPZILGFdQOiUtmwJ6+fkHhiyTHwQVrSPsatP9krvKUYoD3gpKHAXw64w5c HSWw== X-Gm-Message-State: AOAM5312Ri4e0pzd6rQIhjAjzbSPRhgdJnjN3Al9NNKAIF9AvDzJ4z9q r1cHqc4kJFQFB34dgZYBlSg= X-Google-Smtp-Source: ABdhPJwoLdQBKsbqRVvY5uzW2cWlOTCQsV+BbvKx77L21dtdXqKCeTrQ1d9hNwJ4Lvy6+locdqg1Ew== X-Received: by 2002:a05:600c:4ec9:: with SMTP id g9mr27135746wmq.145.1619972254959; Sun, 02 May 2021 09:17:34 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 22/36] target/mips: Move sysemu specific files under sysemu/ subfolder Date: Sun, 2 May 2021 18:15:24 +0200 Message-Id: <20210502161538.534038-23-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move sysemu-specific files under the new sysemu/ subfolder and adapt the Meson machinery. Update the KVM MIPS entry in MAINTAINERS. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-17-f4bug@amsat.org> --- target/mips/{ =3D> sysemu}/addr.c | 0 target/mips/{ =3D> sysemu}/cp0_timer.c | 0 target/mips/{ =3D> sysemu}/machine.c | 0 MAINTAINERS | 3 ++- target/mips/meson.build | 12 ++++++------ target/mips/sysemu/meson.build | 5 +++++ 6 files changed, 13 insertions(+), 7 deletions(-) rename target/mips/{ =3D> sysemu}/addr.c (100%) rename target/mips/{ =3D> sysemu}/cp0_timer.c (100%) rename target/mips/{ =3D> sysemu}/machine.c (100%) create mode 100644 target/mips/sysemu/meson.build diff --git a/target/mips/addr.c b/target/mips/sysemu/addr.c similarity index 100% rename from target/mips/addr.c rename to target/mips/sysemu/addr.c diff --git a/target/mips/cp0_timer.c b/target/mips/sysemu/cp0_timer.c similarity index 100% rename from target/mips/cp0_timer.c rename to target/mips/sysemu/cp0_timer.c diff --git a/target/mips/machine.c b/target/mips/sysemu/machine.c similarity index 100% rename from target/mips/machine.c rename to target/mips/sysemu/machine.c diff --git a/MAINTAINERS b/MAINTAINERS index 4c05ff8bbab..8e4e3298104 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -404,7 +404,8 @@ F: target/arm/kvm.c MIPS KVM CPUs M: Huacai Chen S: Odd Fixes -F: target/mips/kvm.c +F: target/mips/kvm* +F: target/mips/sysemu/ =20 PPC KVM CPUs M: David Gibson diff --git a/target/mips/meson.build b/target/mips/meson.build index ca3cc62cf7a..9a507937ece 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -7,6 +7,7 @@ ] =20 mips_user_ss =3D ss.source_set() +mips_softmmu_ss =3D ss.source_set() mips_ss =3D ss.source_set() mips_ss.add(files( 'cpu.c', @@ -14,6 +15,11 @@ 'gdbstub.c', 'msa.c', )) + +if have_system + subdir('sysemu') +endif + mips_tcg_ss =3D ss.source_set() mips_tcg_ss.add(gen) mips_tcg_ss.add(files( @@ -41,12 +47,6 @@ =20 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 -mips_softmmu_ss =3D ss.source_set() -mips_softmmu_ss.add(files( - 'addr.c', - 'cp0_timer.c', - 'machine.c', -)) mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( 'cp0_helper.c', 'mips-semi.c', diff --git a/target/mips/sysemu/meson.build b/target/mips/sysemu/meson.build new file mode 100644 index 00000000000..f2a1ff46081 --- /dev/null +++ b/target/mips/sysemu/meson.build @@ -0,0 +1,5 @@ +mips_softmmu_ss.add(files( + 'addr.c', + 'cp0_timer.c', + 'machine.c', +)) --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) client-ip=209.85.221.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619972262; cv=none; d=zohomail.com; s=zohoarc; b=VT0IZuwFV0dWM3xS4TS3rZB5t7FRwQkL4bVv4DnzOVEn1MfbsAMA2RTrS8IPcwu76DTwEDP2xM9zGthv2VemELZDe1BTZMg5bFY9o4jR3B2Brr+FAywZ1/vHwMhch3ejQ9s8r1YQXIQNFINgtcsaAhPWDkHCBb9r7gcCVaFpxrE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972262; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ygSc2uYfVXyGCGpvMRk3QGhfV5AHhPWVzoqCEpRfH1o=; b=a+6ygjw2dXBt0z6uP3/Tu6Fw32J/sksYwKeBk53vqACu/EJO6rTmGFKAZ5e7wtFiQadClEcmUE/grwnlseKjoZSSBz0bUwROfrPYXMwv1HQxyrguhrOo9dozGCtQCAuykdR6ZIbzpXbc8Wyy6rgg3ovM2ZMIft6K5oxtdJExxf8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) by mx.zohomail.com with SMTPS id 1619972262457534.3592824134618; Sun, 2 May 2021 09:17:42 -0700 (PDT) Received: by mail-wr1-f48.google.com with SMTP id n2so3132242wrm.0 for ; Sun, 02 May 2021 09:17:41 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (anancy-651-1-208-144.w109-217.abo.wanadoo.fr. [109.217.237.144]) by smtp.gmail.com with ESMTPSA id l5sm8963419wmh.0.2021.05.02.09.17.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:17:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ygSc2uYfVXyGCGpvMRk3QGhfV5AHhPWVzoqCEpRfH1o=; b=CRv0+5ZDiK0DomOkCjGvOl5Ck8+ajCYh4X6fuOJsBQqaoa+mpCnjk8w1u8VbnTj9Cs SD8p9e8oZI30WLgSqbxALf1CUtnSEQ0WwyjJVpf/+TXc9EIPyqYqJhnjKPo/WjnDMPjF UXTBjHPOdD7vqO+XMZmgPT//P/0Mho6noukaGzDgXJJPerRhg9IJX3it2dV0cM20X6TZ y42JFa7kSOU/GZBKr6Nn/iADhBcTJhv80/2ts9MUm+OsjMemC3Esvfgjq/efDAo4hVup yiGu+F/hbsLrIunzirqotbdkY+BeNzwRwpxuzfs4rFhNo0b1cQh5Jda4xsS5nbPycxhp X1SQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ygSc2uYfVXyGCGpvMRk3QGhfV5AHhPWVzoqCEpRfH1o=; b=rFStrayEVZp+ylYKGVsTyYaWkS7ajd6rmdaqZgoyl7diKprOG5v282BipQoQFfh+x6 gphcFkJ5lsCaugKSJ4F0DPxsl/j3VCkIA0OhOsRlsjznt5fitrwT+obYmZvFHiHFHf31 KdVLYuF2sjmbg94TUBzp5aBk6Bg4dalyZgewPmXLfNb/UJp27lM0u+FZqVEZyOFBcTmn OOV1hKFBaKsL03wSACGpPBWiINLaGiD0MglDlzAXd2/sJ7L71msvj58dYz66AErjX7jK uTf+hxq++VVoEHJbo+oFZCOLG5TqeOih97yE/UUth1o85WFm1gUH2yn3b6CvWGzqlk53 +04Q== X-Gm-Message-State: AOAM530Vij1+dSWAnjm4IAG+/Q1d7xkkjWVR2EYtqEJWEGhSgkqHrHSC OBdcoiEJxlcP3Y7n/BtGs/M= X-Google-Smtp-Source: ABdhPJxcFd9db1WkG+T8zlX+Yaa6JEpV1h+bpqRExNllZ6LEb3AyQ7fF6OOiZmJ7MrzRzIw6TQ4Psg== X-Received: by 2002:a5d:6352:: with SMTP id b18mr20121914wrw.76.1619972260564; Sun, 02 May 2021 09:17:40 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 23/36] target/mips: Move physical addressing code to sysemu/physaddr.c Date: Sun, 2 May 2021 18:15:25 +0200 Message-Id: <20210502161538.534038-24-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Declare get_physical_address() with local scope and move it along with mips_cpu_get_phys_page_debug() to sysemu/physaddr.c new file. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-18-f4bug@amsat.org> --- target/mips/internal.h | 25 +++- target/mips/sysemu/physaddr.c | 257 +++++++++++++++++++++++++++++++++ target/mips/tlb_helper.c | 254 -------------------------------- target/mips/sysemu/meson.build | 1 + 4 files changed, 282 insertions(+), 255 deletions(-) create mode 100644 target/mips/sysemu/physaddr.c diff --git a/target/mips/internal.h b/target/mips/internal.h index 3c8ccfbe929..be32102a2ac 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -81,15 +81,38 @@ extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; =20 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); -hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); =20 +#define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL) +#define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL) +#define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL) +#define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL) +#define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL) + +#define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL) +#define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL) + #if !defined(CONFIG_USER_ONLY) =20 +enum { + TLBRET_XI =3D -6, + TLBRET_RI =3D -5, + TLBRET_DIRTY =3D -4, + TLBRET_INVALID =3D -3, + TLBRET_NOMATCH =3D -2, + TLBRET_BADADDR =3D -1, + TLBRET_MATCH =3D 0 +}; + +int get_physical_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong real_address, + MMUAccessType access_type, int mmu_idx); +hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); + typedef struct r4k_tlb_t r4k_tlb_t; struct r4k_tlb_t { target_ulong VPN; diff --git a/target/mips/sysemu/physaddr.c b/target/mips/sysemu/physaddr.c new file mode 100644 index 00000000000..1918633aa1c --- /dev/null +++ b/target/mips/sysemu/physaddr.c @@ -0,0 +1,257 @@ +/* + * MIPS TLB (Translation lookaside buffer) helpers. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "../internal.h" + +static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) +{ + /* + * Interpret access control mode and mmu_idx. + * AdE? TLB? + * AM K S U E K S U E + * UK 0 0 1 1 0 0 - - 0 + * MK 1 0 1 1 0 1 - - !eu + * MSK 2 0 0 1 0 1 1 - !eu + * MUSK 3 0 0 0 0 1 1 1 !eu + * MUSUK 4 0 0 0 0 0 1 1 0 + * USK 5 0 0 1 0 0 0 - 0 + * - 6 - - - - - - - - + * UUSK 7 0 0 0 0 0 0 0 0 + */ + int32_t adetlb_mask; + + switch (mmu_idx) { + case 3: /* ERL */ + /* If EU is set, always unmapped */ + if (eu) { + return 0; + } + /* fall through */ + case MIPS_HFLAG_KM: + /* Never AdE, TLB mapped if AM=3D{1,2,3} */ + adetlb_mask =3D 0x70000000; + goto check_tlb; + + case MIPS_HFLAG_SM: + /* AdE if AM=3D{0,1}, TLB mapped if AM=3D{2,3,4} */ + adetlb_mask =3D 0xc0380000; + goto check_ade; + + case MIPS_HFLAG_UM: + /* AdE if AM=3D{0,1,2,5}, TLB mapped if AM=3D{3,4} */ + adetlb_mask =3D 0xe4180000; + /* fall through */ + check_ade: + /* does this AM cause AdE in current execution mode */ + if ((adetlb_mask << am) < 0) { + return TLBRET_BADADDR; + } + adetlb_mask <<=3D 8; + /* fall through */ + check_tlb: + /* is this AM mapped in current execution mode */ + return ((adetlb_mask << am) < 0); + default: + assert(0); + return TLBRET_BADADDR; + }; +} + +static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong real_address, + MMUAccessType access_type, int mmu_idx, + unsigned int am, bool eu, + target_ulong segmask, + hwaddr physical_base) +{ + int mapped =3D is_seg_am_mapped(am, eu, mmu_idx); + + if (mapped < 0) { + /* is_seg_am_mapped can report TLBRET_BADADDR */ + return mapped; + } else if (mapped) { + /* The segment is TLB mapped */ + return env->tlb->map_address(env, physical, prot, real_address, + access_type); + } else { + /* The segment is unmapped */ + *physical =3D physical_base | (real_address & segmask); + *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return TLBRET_MATCH; + } +} + +static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong real_addres= s, + MMUAccessType access_type, int mmu_= idx, + uint16_t segctl, target_ulong segma= sk) +{ + unsigned int am =3D (segctl & CP0SC_AM_MASK) >> CP0SC_AM; + bool eu =3D (segctl >> CP0SC_EU) & 1; + hwaddr pa =3D ((hwaddr)segctl & CP0SC_PA_MASK) << 20; + + return get_seg_physical_address(env, physical, prot, real_address, + access_type, mmu_idx, am, eu, segmask, + pa & ~(hwaddr)segmask); +} + +int get_physical_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong real_address, + MMUAccessType access_type, int mmu_idx) +{ + /* User mode can only access useg/xuseg */ +#if defined(TARGET_MIPS64) + int user_mode =3D mmu_idx =3D=3D MIPS_HFLAG_UM; + int supervisor_mode =3D mmu_idx =3D=3D MIPS_HFLAG_SM; + int kernel_mode =3D !user_mode && !supervisor_mode; + int UX =3D (env->CP0_Status & (1 << CP0St_UX)) !=3D 0; + int SX =3D (env->CP0_Status & (1 << CP0St_SX)) !=3D 0; + int KX =3D (env->CP0_Status & (1 << CP0St_KX)) !=3D 0; +#endif + int ret =3D TLBRET_MATCH; + /* effective address (modified for KVM T&E kernel segments) */ + target_ulong address =3D real_address; + + if (mips_um_ksegs_enabled()) { + /* KVM T&E adds guest kernel segments in useg */ + if (real_address >=3D KVM_KSEG0_BASE) { + if (real_address < KVM_KSEG2_BASE) { + /* kseg0 */ + address +=3D KSEG0_BASE - KVM_KSEG0_BASE; + } else if (real_address <=3D USEG_LIMIT) { + /* kseg2/3 */ + address +=3D KSEG2_BASE - KVM_KSEG2_BASE; + } + } + } + + if (address <=3D USEG_LIMIT) { + /* useg */ + uint16_t segctl; + + if (address >=3D 0x40000000UL) { + segctl =3D env->CP0_SegCtl2; + } else { + segctl =3D env->CP0_SegCtl2 >> 16; + } + ret =3D get_segctl_physical_address(env, physical, prot, + real_address, access_type, + mmu_idx, segctl, 0x3FFFFFFF); +#if defined(TARGET_MIPS64) + } else if (address < 0x4000000000000000ULL) { + /* xuseg */ + if (UX && address <=3D (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { + ret =3D env->tlb->map_address(env, physical, prot, + real_address, access_type); + } else { + ret =3D TLBRET_BADADDR; + } + } else if (address < 0x8000000000000000ULL) { + /* xsseg */ + if ((supervisor_mode || kernel_mode) && + SX && address <=3D (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { + ret =3D env->tlb->map_address(env, physical, prot, + real_address, access_type); + } else { + ret =3D TLBRET_BADADDR; + } + } else if (address < 0xC000000000000000ULL) { + /* xkphys */ + if ((address & 0x07FFFFFFFFFFFFFFULL) <=3D env->PAMask) { + /* KX/SX/UX bit to check for each xkphys EVA access mode */ + static const uint8_t am_ksux[8] =3D { + [CP0SC_AM_UK] =3D (1u << CP0St_KX), + [CP0SC_AM_MK] =3D (1u << CP0St_KX), + [CP0SC_AM_MSK] =3D (1u << CP0St_SX), + [CP0SC_AM_MUSK] =3D (1u << CP0St_UX), + [CP0SC_AM_MUSUK] =3D (1u << CP0St_UX), + [CP0SC_AM_USK] =3D (1u << CP0St_SX), + [6] =3D (1u << CP0St_KX), + [CP0SC_AM_UUSK] =3D (1u << CP0St_UX), + }; + unsigned int am =3D CP0SC_AM_UK; + unsigned int xr =3D (env->CP0_SegCtl2 & CP0SC2_XR_MASK) >> CP0= SC2_XR; + + if (xr & (1 << ((address >> 59) & 0x7))) { + am =3D (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM; + } + /* Does CP0_Status.KX/SX/UX permit the access mode (am) */ + if (env->CP0_Status & am_ksux[am]) { + ret =3D get_seg_physical_address(env, physical, prot, + real_address, access_type, + mmu_idx, am, false, env->PA= Mask, + 0); + } else { + ret =3D TLBRET_BADADDR; + } + } else { + ret =3D TLBRET_BADADDR; + } + } else if (address < 0xFFFFFFFF80000000ULL) { + /* xkseg */ + if (kernel_mode && KX && + address <=3D (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { + ret =3D env->tlb->map_address(env, physical, prot, + real_address, access_type); + } else { + ret =3D TLBRET_BADADDR; + } +#endif + } else if (address < KSEG1_BASE) { + /* kseg0 */ + ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, + access_type, mmu_idx, + env->CP0_SegCtl1 >> 16, 0x1FFFFF= FF); + } else if (address < KSEG2_BASE) { + /* kseg1 */ + ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, + access_type, mmu_idx, + env->CP0_SegCtl1, 0x1FFFFFFF); + } else if (address < KSEG3_BASE) { + /* sseg (kseg2) */ + ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, + access_type, mmu_idx, + env->CP0_SegCtl0 >> 16, 0x1FFFFF= FF); + } else { + /* + * kseg3 + * XXX: debug segment is not emulated + */ + ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, + access_type, mmu_idx, + env->CP0_SegCtl0, 0x1FFFFFFF); + } + return ret; +} + +hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + hwaddr phys_addr; + int prot; + + if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD, + cpu_mmu_index(env, false)) !=3D 0) { + return -1; + } + return phys_addr; +} diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index afc019c80dd..bfb08eaf506 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -25,16 +25,6 @@ #include "exec/log.h" #include "hw/mips/cpudevs.h" =20 -enum { - TLBRET_XI =3D -6, - TLBRET_RI =3D -5, - TLBRET_DIRTY =3D -4, - TLBRET_INVALID =3D -3, - TLBRET_NOMATCH =3D -2, - TLBRET_BADADDR =3D -1, - TLBRET_MATCH =3D 0 -}; - #if !defined(CONFIG_USER_ONLY) =20 /* no MMU emulation */ @@ -166,236 +156,6 @@ void mmu_init(CPUMIPSState *env, const mips_def_t *de= f) } } =20 -static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) -{ - /* - * Interpret access control mode and mmu_idx. - * AdE? TLB? - * AM K S U E K S U E - * UK 0 0 1 1 0 0 - - 0 - * MK 1 0 1 1 0 1 - - !eu - * MSK 2 0 0 1 0 1 1 - !eu - * MUSK 3 0 0 0 0 1 1 1 !eu - * MUSUK 4 0 0 0 0 0 1 1 0 - * USK 5 0 0 1 0 0 0 - 0 - * - 6 - - - - - - - - - * UUSK 7 0 0 0 0 0 0 0 0 - */ - int32_t adetlb_mask; - - switch (mmu_idx) { - case 3: /* ERL */ - /* If EU is set, always unmapped */ - if (eu) { - return 0; - } - /* fall through */ - case MIPS_HFLAG_KM: - /* Never AdE, TLB mapped if AM=3D{1,2,3} */ - adetlb_mask =3D 0x70000000; - goto check_tlb; - - case MIPS_HFLAG_SM: - /* AdE if AM=3D{0,1}, TLB mapped if AM=3D{2,3,4} */ - adetlb_mask =3D 0xc0380000; - goto check_ade; - - case MIPS_HFLAG_UM: - /* AdE if AM=3D{0,1,2,5}, TLB mapped if AM=3D{3,4} */ - adetlb_mask =3D 0xe4180000; - /* fall through */ - check_ade: - /* does this AM cause AdE in current execution mode */ - if ((adetlb_mask << am) < 0) { - return TLBRET_BADADDR; - } - adetlb_mask <<=3D 8; - /* fall through */ - check_tlb: - /* is this AM mapped in current execution mode */ - return ((adetlb_mask << am) < 0); - default: - assert(0); - return TLBRET_BADADDR; - }; -} - -static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical, - int *prot, target_ulong real_address, - MMUAccessType access_type, int mmu_idx, - unsigned int am, bool eu, - target_ulong segmask, - hwaddr physical_base) -{ - int mapped =3D is_seg_am_mapped(am, eu, mmu_idx); - - if (mapped < 0) { - /* is_seg_am_mapped can report TLBRET_BADADDR */ - return mapped; - } else if (mapped) { - /* The segment is TLB mapped */ - return env->tlb->map_address(env, physical, prot, real_address, - access_type); - } else { - /* The segment is unmapped */ - *physical =3D physical_base | (real_address & segmask); - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return TLBRET_MATCH; - } -} - -static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical, - int *prot, target_ulong real_addres= s, - MMUAccessType access_type, int mmu_= idx, - uint16_t segctl, target_ulong segma= sk) -{ - unsigned int am =3D (segctl & CP0SC_AM_MASK) >> CP0SC_AM; - bool eu =3D (segctl >> CP0SC_EU) & 1; - hwaddr pa =3D ((hwaddr)segctl & CP0SC_PA_MASK) << 20; - - return get_seg_physical_address(env, physical, prot, real_address, - access_type, mmu_idx, am, eu, segmask, - pa & ~(hwaddr)segmask); -} - -static int get_physical_address(CPUMIPSState *env, hwaddr *physical, - int *prot, target_ulong real_address, - MMUAccessType access_type, int mmu_idx) -{ - /* User mode can only access useg/xuseg */ -#if defined(TARGET_MIPS64) - int user_mode =3D mmu_idx =3D=3D MIPS_HFLAG_UM; - int supervisor_mode =3D mmu_idx =3D=3D MIPS_HFLAG_SM; - int kernel_mode =3D !user_mode && !supervisor_mode; - int UX =3D (env->CP0_Status & (1 << CP0St_UX)) !=3D 0; - int SX =3D (env->CP0_Status & (1 << CP0St_SX)) !=3D 0; - int KX =3D (env->CP0_Status & (1 << CP0St_KX)) !=3D 0; -#endif - int ret =3D TLBRET_MATCH; - /* effective address (modified for KVM T&E kernel segments) */ - target_ulong address =3D real_address; - -#define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL) -#define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL) -#define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL) -#define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL) -#define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL) - -#define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL) -#define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL) - - if (mips_um_ksegs_enabled()) { - /* KVM T&E adds guest kernel segments in useg */ - if (real_address >=3D KVM_KSEG0_BASE) { - if (real_address < KVM_KSEG2_BASE) { - /* kseg0 */ - address +=3D KSEG0_BASE - KVM_KSEG0_BASE; - } else if (real_address <=3D USEG_LIMIT) { - /* kseg2/3 */ - address +=3D KSEG2_BASE - KVM_KSEG2_BASE; - } - } - } - - if (address <=3D USEG_LIMIT) { - /* useg */ - uint16_t segctl; - - if (address >=3D 0x40000000UL) { - segctl =3D env->CP0_SegCtl2; - } else { - segctl =3D env->CP0_SegCtl2 >> 16; - } - ret =3D get_segctl_physical_address(env, physical, prot, - real_address, access_type, - mmu_idx, segctl, 0x3FFFFFFF); -#if defined(TARGET_MIPS64) - } else if (address < 0x4000000000000000ULL) { - /* xuseg */ - if (UX && address <=3D (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { - ret =3D env->tlb->map_address(env, physical, prot, - real_address, access_type); - } else { - ret =3D TLBRET_BADADDR; - } - } else if (address < 0x8000000000000000ULL) { - /* xsseg */ - if ((supervisor_mode || kernel_mode) && - SX && address <=3D (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { - ret =3D env->tlb->map_address(env, physical, prot, - real_address, access_type); - } else { - ret =3D TLBRET_BADADDR; - } - } else if (address < 0xC000000000000000ULL) { - /* xkphys */ - if ((address & 0x07FFFFFFFFFFFFFFULL) <=3D env->PAMask) { - /* KX/SX/UX bit to check for each xkphys EVA access mode */ - static const uint8_t am_ksux[8] =3D { - [CP0SC_AM_UK] =3D (1u << CP0St_KX), - [CP0SC_AM_MK] =3D (1u << CP0St_KX), - [CP0SC_AM_MSK] =3D (1u << CP0St_SX), - [CP0SC_AM_MUSK] =3D (1u << CP0St_UX), - [CP0SC_AM_MUSUK] =3D (1u << CP0St_UX), - [CP0SC_AM_USK] =3D (1u << CP0St_SX), - [6] =3D (1u << CP0St_KX), - [CP0SC_AM_UUSK] =3D (1u << CP0St_UX), - }; - unsigned int am =3D CP0SC_AM_UK; - unsigned int xr =3D (env->CP0_SegCtl2 & CP0SC2_XR_MASK) >> CP0= SC2_XR; - - if (xr & (1 << ((address >> 59) & 0x7))) { - am =3D (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM; - } - /* Does CP0_Status.KX/SX/UX permit the access mode (am) */ - if (env->CP0_Status & am_ksux[am]) { - ret =3D get_seg_physical_address(env, physical, prot, - real_address, access_type, - mmu_idx, am, false, env->PA= Mask, - 0); - } else { - ret =3D TLBRET_BADADDR; - } - } else { - ret =3D TLBRET_BADADDR; - } - } else if (address < 0xFFFFFFFF80000000ULL) { - /* xkseg */ - if (kernel_mode && KX && - address <=3D (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { - ret =3D env->tlb->map_address(env, physical, prot, - real_address, access_type); - } else { - ret =3D TLBRET_BADADDR; - } -#endif - } else if (address < KSEG1_BASE) { - /* kseg0 */ - ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, - access_type, mmu_idx, - env->CP0_SegCtl1 >> 16, 0x1FFFFF= FF); - } else if (address < KSEG2_BASE) { - /* kseg1 */ - ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, - access_type, mmu_idx, - env->CP0_SegCtl1, 0x1FFFFFFF); - } else if (address < KSEG3_BASE) { - /* sseg (kseg2) */ - ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, - access_type, mmu_idx, - env->CP0_SegCtl0 >> 16, 0x1FFFFF= FF); - } else { - /* - * kseg3 - * XXX: debug segment is not emulated - */ - ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, - access_type, mmu_idx, - env->CP0_SegCtl0, 0x1FFFFFFF); - } - return ret; -} - void cpu_mips_tlb_flush(CPUMIPSState *env) { /* Flush qemu's TLB and discard all shadowed entries. */ @@ -482,20 +242,6 @@ static void raise_mmu_exception(CPUMIPSState *env, tar= get_ulong address, env->error_code =3D error_code; } =20 -hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) -{ - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - hwaddr phys_addr; - int prot; - - if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)) !=3D 0) { - return -1; - } - return phys_addr; -} - #if !defined(TARGET_MIPS64) =20 /* diff --git a/target/mips/sysemu/meson.build b/target/mips/sysemu/meson.build index f2a1ff46081..925ceeaa449 100644 --- a/target/mips/sysemu/meson.build +++ b/target/mips/sysemu/meson.build @@ -2,4 +2,5 @@ 'addr.c', 'cp0_timer.c', 'machine.c', + 'physaddr.c', )) --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) client-ip=209.85.128.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619972267; cv=none; d=zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-19-f4bug@amsat.org> --- target/mips/internal.h | 4 ---- target/mips/tcg/tcg-internal.h | 9 +++++++++ 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index be32102a2ac..6bac8ef704a 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -165,7 +165,6 @@ void r4k_helper_tlbr(CPUMIPSState *env); void r4k_helper_tlbinv(CPUMIPSState *env); void r4k_helper_tlbinvf(CPUMIPSState *env); void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); -uint32_t cpu_mips_get_random(CPUMIPSState *env); =20 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, @@ -237,9 +236,6 @@ void cpu_mips_stop_count(CPUMIPSState *env); /* helper.c */ void mmu_init(CPUMIPSState *env, const mips_def_t *def); =20 -/* op_helper.c */ -void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); - static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value) { env->active_tc.PC =3D value & ~(target_ulong)1; diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 24438667f47..b65580af211 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -11,10 +11,19 @@ #define MIPS_TCG_INTERNAL_H =20 #include "hw/core/cpu.h" +#include "cpu.h" =20 void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 +#if !defined(CONFIG_USER_ONLY) + +void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); + +uint32_t cpu_mips_get_random(CPUMIPSState *env); + +#endif /* !CONFIG_USER_ONLY */ + #endif --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) client-ip=209.85.128.42; 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[109.217.237.144]) by smtp.gmail.com with ESMTPSA id v13sm9456987wrt.65.2021.05.02.09.17.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:17:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5CBh0GK72R05sRHyTjxIRuL5NbyJxrVcGBiXhIvAsEY=; b=tcRDfnachZu3Kd+AyMT4Z4vUkHs6dOdAdcbTHG4BnzV5JsMb0I1oMSpAgdwbgX8zun 7aPhsPHZgwuI2ZK0SYm4ARg9cG4vvGDKO55e5EmVQH2D4+A9sj6wrbAEN7k0JpALt+p3 aay7Eh0ssUUJm2UoyrSNObh3shu0oXi6OWGCCZ+WG5GrYlxEiNopPLeYsZ4tKwLie3uz SMF1oTntFLrwefD0eJri8ej5xSI1YJ4vG9qaIXBtA+CmliJTF72MHNVhgY68xrXcnwP3 K6ODYVDRBsS+u/Zyz6dOtuE1PJDWCBs9DLMqPMG/ZO93FQclmEAN/rvCuGrM+a9pdglC RR/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=5CBh0GK72R05sRHyTjxIRuL5NbyJxrVcGBiXhIvAsEY=; b=BO6qJ6/0A7mg59KtqF73SgX9SYA7UWTNhOnummFmAvWT5D6WQsU+kkuYtmIR/5tb4r +cMtAgnG96P3w2GKCrOJwcGJYwA6jMrdleKJteyHMcwULWvblKGy3M2qh0lE1JCsdfP9 W4e9n/u3L3v6/2YefpXayXse8YJwF+jQTt8EY8kVjGMHkEURRdRyZ1IhB1k8O91mB8mU WuJR1CA9lJzA4FnaV/eg5bt8Fk2+m+4HFL78ja+XEGt2H5O9U+2olHEELfp2B8vFvIbF 8SzXIj/+kQrV1ZBxcT8LXjwxU42++GY+q3xrm7C75xH0K7hKZsvgxkej5HA+dX+QWnTB Mvkg== X-Gm-Message-State: AOAM5316BUdKc4SbLLC5QeO5WvHtCFXy4wV9D8Ck/ffjK7Y5PHwwXmt2 UzZoZ69hTZwmkfGFb68Wc9/WYn+j0m/hyvUg X-Google-Smtp-Source: ABdhPJw8zU+ceIevEga8lQD+MqLpXYsHPho2JlMX1m7rLIlxJqQLuYhM9iArO8iYaxgyX+4L2iPaBg== X-Received: by 2002:a7b:c7d0:: with SMTP id z16mr3759491wmk.22.1619972270646; Sun, 02 May 2021 09:17:50 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 25/36] target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder Date: Sun, 2 May 2021 18:15:27 +0200 Message-Id: <20210502161538.534038-26-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move cp0_helper.c and mips-semi.c to the new tcg/sysemu/ folder, adapting the Meson machinery. Move the opcode definitions to tcg/sysemu_helper.h.inc. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-20-f4bug@amsat.org> --- target/mips/helper.h | 166 +-------------------- target/mips/tcg/sysemu_helper.h.inc | 168 ++++++++++++++++++++++ target/mips/{ =3D> tcg/sysemu}/cp0_helper.c | 0 target/mips/{ =3D> tcg/sysemu}/mips-semi.c | 0 target/mips/meson.build | 5 - target/mips/tcg/meson.build | 3 + target/mips/tcg/sysemu/meson.build | 4 + 7 files changed, 179 insertions(+), 167 deletions(-) create mode 100644 target/mips/tcg/sysemu_helper.h.inc rename target/mips/{ =3D> tcg/sysemu}/cp0_helper.c (100%) rename target/mips/{ =3D> tcg/sysemu}/mips-semi.c (100%) create mode 100644 target/mips/tcg/sysemu/meson.build diff --git a/target/mips/helper.h b/target/mips/helper.h index 709494445dd..bc308e5db13 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -2,10 +2,6 @@ DEF_HELPER_3(raise_exception_err, noreturn, env, i32, int) DEF_HELPER_2(raise_exception, noreturn, env, i32) DEF_HELPER_1(raise_exception_debug, noreturn, env) =20 -#ifndef CONFIG_USER_ONLY -DEF_HELPER_1(do_semihosting, void, env) -#endif - #ifdef TARGET_MIPS64 DEF_HELPER_4(sdl, void, env, tl, tl, int) DEF_HELPER_4(sdr, void, env, tl, tl, int) @@ -42,164 +38,6 @@ DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl) =20 DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32) =20 -#ifndef CONFIG_USER_ONLY -/* CP0 helpers */ -DEF_HELPER_1(mfc0_mvpcontrol, tl, env) -DEF_HELPER_1(mfc0_mvpconf0, tl, env) -DEF_HELPER_1(mfc0_mvpconf1, tl, env) -DEF_HELPER_1(mftc0_vpecontrol, tl, env) -DEF_HELPER_1(mftc0_vpeconf0, tl, env) -DEF_HELPER_1(mfc0_random, tl, env) -DEF_HELPER_1(mfc0_tcstatus, tl, env) -DEF_HELPER_1(mftc0_tcstatus, tl, env) -DEF_HELPER_1(mfc0_tcbind, tl, env) -DEF_HELPER_1(mftc0_tcbind, tl, env) -DEF_HELPER_1(mfc0_tcrestart, tl, env) -DEF_HELPER_1(mftc0_tcrestart, tl, env) -DEF_HELPER_1(mfc0_tchalt, tl, env) -DEF_HELPER_1(mftc0_tchalt, tl, env) -DEF_HELPER_1(mfc0_tccontext, tl, env) -DEF_HELPER_1(mftc0_tccontext, tl, env) -DEF_HELPER_1(mfc0_tcschedule, tl, env) -DEF_HELPER_1(mftc0_tcschedule, tl, env) -DEF_HELPER_1(mfc0_tcschefback, tl, env) -DEF_HELPER_1(mftc0_tcschefback, tl, env) -DEF_HELPER_1(mfc0_count, tl, env) -DEF_HELPER_1(mfc0_saar, tl, env) -DEF_HELPER_1(mfhc0_saar, tl, env) -DEF_HELPER_1(mftc0_entryhi, tl, env) -DEF_HELPER_1(mftc0_status, tl, env) -DEF_HELPER_1(mftc0_cause, tl, env) -DEF_HELPER_1(mftc0_epc, tl, env) -DEF_HELPER_1(mftc0_ebase, tl, env) -DEF_HELPER_2(mftc0_configx, tl, env, tl) -DEF_HELPER_1(mfc0_lladdr, tl, env) -DEF_HELPER_1(mfc0_maar, tl, env) -DEF_HELPER_1(mfhc0_maar, tl, env) -DEF_HELPER_2(mfc0_watchlo, tl, env, i32) -DEF_HELPER_2(mfc0_watchhi, tl, env, i32) -DEF_HELPER_2(mfhc0_watchhi, tl, env, i32) -DEF_HELPER_1(mfc0_debug, tl, env) -DEF_HELPER_1(mftc0_debug, tl, env) -#ifdef TARGET_MIPS64 -DEF_HELPER_1(dmfc0_tcrestart, tl, env) -DEF_HELPER_1(dmfc0_tchalt, tl, env) -DEF_HELPER_1(dmfc0_tccontext, tl, env) -DEF_HELPER_1(dmfc0_tcschedule, tl, env) -DEF_HELPER_1(dmfc0_tcschefback, tl, env) -DEF_HELPER_1(dmfc0_lladdr, tl, env) -DEF_HELPER_1(dmfc0_maar, tl, env) -DEF_HELPER_2(dmfc0_watchlo, tl, env, i32) -DEF_HELPER_2(dmfc0_watchhi, tl, env, i32) -DEF_HELPER_1(dmfc0_saar, tl, env) -#endif /* TARGET_MIPS64 */ - -DEF_HELPER_2(mtc0_index, void, env, tl) -DEF_HELPER_2(mtc0_mvpcontrol, void, env, tl) -DEF_HELPER_2(mtc0_vpecontrol, void, env, tl) -DEF_HELPER_2(mttc0_vpecontrol, void, env, tl) -DEF_HELPER_2(mtc0_vpeconf0, void, env, tl) -DEF_HELPER_2(mttc0_vpeconf0, void, env, tl) -DEF_HELPER_2(mtc0_vpeconf1, void, env, tl) -DEF_HELPER_2(mtc0_yqmask, void, env, tl) -DEF_HELPER_2(mtc0_vpeopt, void, env, tl) -DEF_HELPER_2(mtc0_entrylo0, void, env, tl) -DEF_HELPER_2(mtc0_tcstatus, void, env, tl) -DEF_HELPER_2(mttc0_tcstatus, void, env, tl) -DEF_HELPER_2(mtc0_tcbind, void, env, tl) -DEF_HELPER_2(mttc0_tcbind, void, env, tl) -DEF_HELPER_2(mtc0_tcrestart, void, env, tl) -DEF_HELPER_2(mttc0_tcrestart, void, env, tl) -DEF_HELPER_2(mtc0_tchalt, void, env, tl) -DEF_HELPER_2(mttc0_tchalt, void, env, tl) -DEF_HELPER_2(mtc0_tccontext, void, env, tl) -DEF_HELPER_2(mttc0_tccontext, void, env, tl) -DEF_HELPER_2(mtc0_tcschedule, void, env, tl) -DEF_HELPER_2(mttc0_tcschedule, void, env, tl) -DEF_HELPER_2(mtc0_tcschefback, void, env, tl) -DEF_HELPER_2(mttc0_tcschefback, void, env, tl) -DEF_HELPER_2(mtc0_entrylo1, void, env, tl) -DEF_HELPER_2(mtc0_context, void, env, tl) -DEF_HELPER_2(mtc0_memorymapid, void, env, tl) -DEF_HELPER_2(mtc0_pagemask, void, env, tl) -DEF_HELPER_2(mtc0_pagegrain, void, env, tl) -DEF_HELPER_2(mtc0_segctl0, void, env, tl) -DEF_HELPER_2(mtc0_segctl1, void, env, tl) -DEF_HELPER_2(mtc0_segctl2, void, env, tl) -DEF_HELPER_2(mtc0_pwfield, void, env, tl) -DEF_HELPER_2(mtc0_pwsize, void, env, tl) -DEF_HELPER_2(mtc0_wired, void, env, tl) -DEF_HELPER_2(mtc0_srsconf0, void, env, tl) -DEF_HELPER_2(mtc0_srsconf1, void, env, tl) -DEF_HELPER_2(mtc0_srsconf2, void, env, tl) -DEF_HELPER_2(mtc0_srsconf3, void, env, tl) -DEF_HELPER_2(mtc0_srsconf4, void, env, tl) -DEF_HELPER_2(mtc0_hwrena, void, env, tl) -DEF_HELPER_2(mtc0_pwctl, void, env, tl) -DEF_HELPER_2(mtc0_count, void, env, tl) -DEF_HELPER_2(mtc0_saari, void, env, tl) -DEF_HELPER_2(mtc0_saar, void, env, tl) -DEF_HELPER_2(mthc0_saar, void, env, tl) -DEF_HELPER_2(mtc0_entryhi, void, env, tl) -DEF_HELPER_2(mttc0_entryhi, void, env, tl) -DEF_HELPER_2(mtc0_compare, void, env, tl) -DEF_HELPER_2(mtc0_status, void, env, tl) -DEF_HELPER_2(mttc0_status, void, env, tl) -DEF_HELPER_2(mtc0_intctl, void, env, tl) -DEF_HELPER_2(mtc0_srsctl, void, env, tl) -DEF_HELPER_2(mtc0_cause, void, env, tl) -DEF_HELPER_2(mttc0_cause, void, env, tl) -DEF_HELPER_2(mtc0_ebase, void, env, tl) -DEF_HELPER_2(mttc0_ebase, void, env, tl) -DEF_HELPER_2(mtc0_config0, void, env, tl) -DEF_HELPER_2(mtc0_config2, void, env, tl) -DEF_HELPER_2(mtc0_config3, void, env, tl) -DEF_HELPER_2(mtc0_config4, void, env, tl) -DEF_HELPER_2(mtc0_config5, void, env, tl) -DEF_HELPER_2(mtc0_lladdr, void, env, tl) -DEF_HELPER_2(mtc0_maar, void, env, tl) -DEF_HELPER_2(mthc0_maar, void, env, tl) -DEF_HELPER_2(mtc0_maari, void, env, tl) -DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32) -DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32) -DEF_HELPER_3(mthc0_watchhi, void, env, tl, i32) -DEF_HELPER_2(mtc0_xcontext, void, env, tl) -DEF_HELPER_2(mtc0_framemask, void, env, tl) -DEF_HELPER_2(mtc0_debug, void, env, tl) -DEF_HELPER_2(mttc0_debug, void, env, tl) -DEF_HELPER_2(mtc0_performance0, void, env, tl) -DEF_HELPER_2(mtc0_errctl, void, env, tl) -DEF_HELPER_2(mtc0_taglo, void, env, tl) -DEF_HELPER_2(mtc0_datalo, void, env, tl) -DEF_HELPER_2(mtc0_taghi, void, env, tl) -DEF_HELPER_2(mtc0_datahi, void, env, tl) - -#if defined(TARGET_MIPS64) -DEF_HELPER_2(dmtc0_entrylo0, void, env, i64) -DEF_HELPER_2(dmtc0_entrylo1, void, env, i64) -#endif - -/* MIPS MT functions */ -DEF_HELPER_2(mftgpr, tl, env, i32) -DEF_HELPER_2(mftlo, tl, env, i32) -DEF_HELPER_2(mfthi, tl, env, i32) -DEF_HELPER_2(mftacx, tl, env, i32) -DEF_HELPER_1(mftdsp, tl, env) -DEF_HELPER_3(mttgpr, void, env, tl, i32) -DEF_HELPER_3(mttlo, void, env, tl, i32) -DEF_HELPER_3(mtthi, void, env, tl, i32) -DEF_HELPER_3(mttacx, void, env, tl, i32) -DEF_HELPER_2(mttdsp, void, env, tl) -DEF_HELPER_0(dmt, tl) -DEF_HELPER_0(emt, tl) -DEF_HELPER_1(dvpe, tl, env) -DEF_HELPER_1(evpe, tl, env) - -/* R6 Multi-threading */ -DEF_HELPER_1(dvp, tl, env) -DEF_HELPER_1(evp, tl, env) -#endif /* !CONFIG_USER_ONLY */ - /* microMIPS functions */ DEF_HELPER_4(lwm, void, env, tl, tl, i32) DEF_HELPER_4(swm, void, env, tl, tl, i32) @@ -783,4 +621,8 @@ DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) =20 DEF_HELPER_3(cache, void, env, tl, i32) =20 +#ifndef CONFIG_USER_ONLY +#include "tcg/sysemu_helper.h.inc" +#endif /* !CONFIG_USER_ONLY */ + #include "msa_helper.h.inc" diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_h= elper.h.inc new file mode 100644 index 00000000000..d136c4160a7 --- /dev/null +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -0,0 +1,168 @@ +/* + * QEMU MIPS sysemu helpers + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +DEF_HELPER_1(do_semihosting, void, env) + +/* CP0 helpers */ +DEF_HELPER_1(mfc0_mvpcontrol, tl, env) +DEF_HELPER_1(mfc0_mvpconf0, tl, env) +DEF_HELPER_1(mfc0_mvpconf1, tl, env) +DEF_HELPER_1(mftc0_vpecontrol, tl, env) +DEF_HELPER_1(mftc0_vpeconf0, tl, env) +DEF_HELPER_1(mfc0_random, tl, env) +DEF_HELPER_1(mfc0_tcstatus, tl, env) +DEF_HELPER_1(mftc0_tcstatus, tl, env) +DEF_HELPER_1(mfc0_tcbind, tl, env) +DEF_HELPER_1(mftc0_tcbind, tl, env) +DEF_HELPER_1(mfc0_tcrestart, tl, env) +DEF_HELPER_1(mftc0_tcrestart, tl, env) +DEF_HELPER_1(mfc0_tchalt, tl, env) +DEF_HELPER_1(mftc0_tchalt, tl, env) +DEF_HELPER_1(mfc0_tccontext, tl, env) +DEF_HELPER_1(mftc0_tccontext, tl, env) +DEF_HELPER_1(mfc0_tcschedule, tl, env) +DEF_HELPER_1(mftc0_tcschedule, tl, env) +DEF_HELPER_1(mfc0_tcschefback, tl, env) +DEF_HELPER_1(mftc0_tcschefback, tl, env) +DEF_HELPER_1(mfc0_count, tl, env) +DEF_HELPER_1(mfc0_saar, tl, env) +DEF_HELPER_1(mfhc0_saar, tl, env) +DEF_HELPER_1(mftc0_entryhi, tl, env) +DEF_HELPER_1(mftc0_status, tl, env) +DEF_HELPER_1(mftc0_cause, tl, env) +DEF_HELPER_1(mftc0_epc, tl, env) +DEF_HELPER_1(mftc0_ebase, tl, env) +DEF_HELPER_2(mftc0_configx, tl, env, tl) +DEF_HELPER_1(mfc0_lladdr, tl, env) +DEF_HELPER_1(mfc0_maar, tl, env) +DEF_HELPER_1(mfhc0_maar, tl, env) +DEF_HELPER_2(mfc0_watchlo, tl, env, i32) +DEF_HELPER_2(mfc0_watchhi, tl, env, i32) +DEF_HELPER_2(mfhc0_watchhi, tl, env, i32) +DEF_HELPER_1(mfc0_debug, tl, env) +DEF_HELPER_1(mftc0_debug, tl, env) +#ifdef TARGET_MIPS64 +DEF_HELPER_1(dmfc0_tcrestart, tl, env) +DEF_HELPER_1(dmfc0_tchalt, tl, env) +DEF_HELPER_1(dmfc0_tccontext, tl, env) +DEF_HELPER_1(dmfc0_tcschedule, tl, env) +DEF_HELPER_1(dmfc0_tcschefback, tl, env) +DEF_HELPER_1(dmfc0_lladdr, tl, env) +DEF_HELPER_1(dmfc0_maar, tl, env) +DEF_HELPER_2(dmfc0_watchlo, tl, env, i32) +DEF_HELPER_2(dmfc0_watchhi, tl, env, i32) +DEF_HELPER_1(dmfc0_saar, tl, env) +#endif /* TARGET_MIPS64 */ + +DEF_HELPER_2(mtc0_index, void, env, tl) +DEF_HELPER_2(mtc0_mvpcontrol, void, env, tl) +DEF_HELPER_2(mtc0_vpecontrol, void, env, tl) +DEF_HELPER_2(mttc0_vpecontrol, void, env, tl) +DEF_HELPER_2(mtc0_vpeconf0, void, env, tl) +DEF_HELPER_2(mttc0_vpeconf0, void, env, tl) +DEF_HELPER_2(mtc0_vpeconf1, void, env, tl) +DEF_HELPER_2(mtc0_yqmask, void, env, tl) +DEF_HELPER_2(mtc0_vpeopt, void, env, tl) +DEF_HELPER_2(mtc0_entrylo0, void, env, tl) +DEF_HELPER_2(mtc0_tcstatus, void, env, tl) +DEF_HELPER_2(mttc0_tcstatus, void, env, tl) +DEF_HELPER_2(mtc0_tcbind, void, env, tl) +DEF_HELPER_2(mttc0_tcbind, void, env, tl) +DEF_HELPER_2(mtc0_tcrestart, void, env, tl) +DEF_HELPER_2(mttc0_tcrestart, void, env, tl) +DEF_HELPER_2(mtc0_tchalt, void, env, tl) +DEF_HELPER_2(mttc0_tchalt, void, env, tl) +DEF_HELPER_2(mtc0_tccontext, void, env, tl) +DEF_HELPER_2(mttc0_tccontext, void, env, tl) +DEF_HELPER_2(mtc0_tcschedule, void, env, tl) +DEF_HELPER_2(mttc0_tcschedule, void, env, tl) +DEF_HELPER_2(mtc0_tcschefback, void, env, tl) +DEF_HELPER_2(mttc0_tcschefback, void, env, tl) +DEF_HELPER_2(mtc0_entrylo1, void, env, tl) +DEF_HELPER_2(mtc0_context, void, env, tl) +DEF_HELPER_2(mtc0_memorymapid, void, env, tl) +DEF_HELPER_2(mtc0_pagemask, void, env, tl) +DEF_HELPER_2(mtc0_pagegrain, void, env, tl) +DEF_HELPER_2(mtc0_segctl0, void, env, tl) +DEF_HELPER_2(mtc0_segctl1, void, env, tl) +DEF_HELPER_2(mtc0_segctl2, void, env, tl) +DEF_HELPER_2(mtc0_pwfield, void, env, tl) +DEF_HELPER_2(mtc0_pwsize, void, env, tl) +DEF_HELPER_2(mtc0_wired, void, env, tl) +DEF_HELPER_2(mtc0_srsconf0, void, env, tl) +DEF_HELPER_2(mtc0_srsconf1, void, env, tl) +DEF_HELPER_2(mtc0_srsconf2, void, env, tl) +DEF_HELPER_2(mtc0_srsconf3, void, env, tl) +DEF_HELPER_2(mtc0_srsconf4, void, env, tl) +DEF_HELPER_2(mtc0_hwrena, void, env, tl) +DEF_HELPER_2(mtc0_pwctl, void, env, tl) +DEF_HELPER_2(mtc0_count, void, env, tl) +DEF_HELPER_2(mtc0_saari, void, env, tl) +DEF_HELPER_2(mtc0_saar, void, env, tl) +DEF_HELPER_2(mthc0_saar, void, env, tl) +DEF_HELPER_2(mtc0_entryhi, void, env, tl) +DEF_HELPER_2(mttc0_entryhi, void, env, tl) +DEF_HELPER_2(mtc0_compare, void, env, tl) +DEF_HELPER_2(mtc0_status, void, env, tl) +DEF_HELPER_2(mttc0_status, void, env, tl) +DEF_HELPER_2(mtc0_intctl, void, env, tl) +DEF_HELPER_2(mtc0_srsctl, void, env, tl) +DEF_HELPER_2(mtc0_cause, void, env, tl) +DEF_HELPER_2(mttc0_cause, void, env, tl) +DEF_HELPER_2(mtc0_ebase, void, env, tl) +DEF_HELPER_2(mttc0_ebase, void, env, tl) +DEF_HELPER_2(mtc0_config0, void, env, tl) +DEF_HELPER_2(mtc0_config2, void, env, tl) +DEF_HELPER_2(mtc0_config3, void, env, tl) +DEF_HELPER_2(mtc0_config4, void, env, tl) +DEF_HELPER_2(mtc0_config5, void, env, tl) +DEF_HELPER_2(mtc0_lladdr, void, env, tl) +DEF_HELPER_2(mtc0_maar, void, env, tl) +DEF_HELPER_2(mthc0_maar, void, env, tl) +DEF_HELPER_2(mtc0_maari, void, env, tl) +DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32) +DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32) +DEF_HELPER_3(mthc0_watchhi, void, env, tl, i32) +DEF_HELPER_2(mtc0_xcontext, void, env, tl) +DEF_HELPER_2(mtc0_framemask, void, env, tl) +DEF_HELPER_2(mtc0_debug, void, env, tl) +DEF_HELPER_2(mttc0_debug, void, env, tl) +DEF_HELPER_2(mtc0_performance0, void, env, tl) +DEF_HELPER_2(mtc0_errctl, void, env, tl) +DEF_HELPER_2(mtc0_taglo, void, env, tl) +DEF_HELPER_2(mtc0_datalo, void, env, tl) +DEF_HELPER_2(mtc0_taghi, void, env, tl) +DEF_HELPER_2(mtc0_datahi, void, env, tl) + +#if defined(TARGET_MIPS64) +DEF_HELPER_2(dmtc0_entrylo0, void, env, i64) +DEF_HELPER_2(dmtc0_entrylo1, void, env, i64) +#endif + +/* MIPS MT functions */ +DEF_HELPER_2(mftgpr, tl, env, i32) +DEF_HELPER_2(mftlo, tl, env, i32) +DEF_HELPER_2(mfthi, tl, env, i32) +DEF_HELPER_2(mftacx, tl, env, i32) +DEF_HELPER_1(mftdsp, tl, env) +DEF_HELPER_3(mttgpr, void, env, tl, i32) +DEF_HELPER_3(mttlo, void, env, tl, i32) +DEF_HELPER_3(mtthi, void, env, tl, i32) +DEF_HELPER_3(mttacx, void, env, tl, i32) +DEF_HELPER_2(mttdsp, void, env, tl) +DEF_HELPER_0(dmt, tl) +DEF_HELPER_0(emt, tl) +DEF_HELPER_1(dvpe, tl, env) +DEF_HELPER_1(evpe, tl, env) + +/* R6 Multi-threading */ +DEF_HELPER_1(dvp, tl, env) +DEF_HELPER_1(evp, tl, env) diff --git a/target/mips/cp0_helper.c b/target/mips/tcg/sysemu/cp0_helper.c similarity index 100% rename from target/mips/cp0_helper.c rename to target/mips/tcg/sysemu/cp0_helper.c diff --git a/target/mips/mips-semi.c b/target/mips/tcg/sysemu/mips-semi.c similarity index 100% rename from target/mips/mips-semi.c rename to target/mips/tcg/sysemu/mips-semi.c diff --git a/target/mips/meson.build b/target/mips/meson.build index 9a507937ece..a55af1cd6cf 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -47,11 +47,6 @@ =20 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 -mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( - 'cp0_helper.c', - 'mips-semi.c', -)) - mips_ss.add_all(when: 'CONFIG_TCG', if_true: [mips_tcg_ss]) =20 target_arch +=3D {'mips': mips_ss} diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index b74fa04303e..2cffc5a5ac6 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -1,3 +1,6 @@ if have_user subdir('user') endif +if have_system + subdir('sysemu') +endif diff --git a/target/mips/tcg/sysemu/meson.build b/target/mips/tcg/sysemu/me= son.build new file mode 100644 index 00000000000..5c3024e7760 --- /dev/null +++ b/target/mips/tcg/sysemu/meson.build @@ -0,0 +1,4 @@ +mips_softmmu_ss.add(files( + 'cp0_helper.c', + 'mips-semi.c', +)) --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: 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[109.217.237.144]) by smtp.gmail.com with ESMTPSA id a142sm19403862wmd.7.2021.05.02.09.17.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:17:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8raeOnbaaLR0eMWkBaEAhhPOlsDJQegVcWQXqveM4CA=; b=Bgc2RmU7u1IHufQTOWtu+Od43Tjy33IXPJOIulK2o1FgpJWYNljoOdOOyXxoIK6pEq k6gsKq7MGiFc1+LZjfRIyAQIc3CMiNQ+dAY5F8xkdGrrF6fj7gHKOYL+kyy1kjsuhtS0 HzWo8hCZ8WPGlBo31bdE1gTHmcqSen2+WPWlVx9gDSvOP9H0OlOLK5ZVhdKMzoIJz8DJ ccE9+yyJE1w24d5E+KRptOJMzrA0rVzjamXZVKOYfeLAV7gO6DCF7DIPuKnmq+3pfSaH 6eW9T+thrnCf3lf5NZJJE1PfDAHj6qUHei5Q/R6Iy+B+3U82uwp7nUuZa4wJHf9WiM3H nw1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=8raeOnbaaLR0eMWkBaEAhhPOlsDJQegVcWQXqveM4CA=; b=MqBJpNXD9ycscEBFLfTE7Oxm98BO90IRBbMgSPJdt+aZ9WeiNn27msxQfBGOfxF5z4 v/PPxZgX1A6SKL7RoqJVNkAD3nzmmBcTBZjTjMsIeHrJmDisMoB2EP9c9xYQgwLUlCWs Mfpkt/1cK0pVW1XBK6yPyWDGMXaRbYp0qeBkUrEGeevYGMJ/EEUuS0bIxs4nFCmwU5wU lNl8m2+NLTvk5OaFhvGOGM4nUl+l7LFqtK4LxUkSPKBpFRzfDeb60zrwYiEQ0OIwgpFH gX/6LoPFuUJfGKarFxRVB2jKCwUqYVG9zrQnSdORQME8g1x9WLw3Xak8eWWfG50iZkYl E4pQ== X-Gm-Message-State: AOAM530Rey4+DpbOxLji0H1u1qJxaJWqj2KQHQ+0hdQToHbRH9/krOsU NoKrqQkZycaefF7iQj6OKSc= X-Google-Smtp-Source: ABdhPJx7XXC7qpiUVeb4pzWHZgAwG58R+7jJPHf4GwG58kPekd1KIj4Ql9DXzew3uCCTaCCHjGuHoQ== X-Received: by 2002:a5d:654c:: with SMTP id z12mr19957786wrv.12.1619972275751; Sun, 02 May 2021 09:17:55 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 26/36] target/mips: Restrict mmu_init() to TCG Date: Sun, 2 May 2021 18:15:28 +0200 Message-Id: <20210502161538.534038-27-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) mmu_init() is only required by TCG accelerator. Restrict its declaration and call to TCG. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-21-f4bug@amsat.org> --- target/mips/internal.h | 3 --- target/mips/tcg/tcg-internal.h | 2 ++ target/mips/cpu.c | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 6bac8ef704a..2c9666905df 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -233,9 +233,6 @@ void cpu_mips_store_compare(CPUMIPSState *env, uint32_t= value); void cpu_mips_start_count(CPUMIPSState *env); void cpu_mips_stop_count(CPUMIPSState *env); =20 -/* helper.c */ -void mmu_init(CPUMIPSState *env, const mips_def_t *def); - static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value) { env->active_tc.PC =3D value & ~(target_ulong)1; diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index b65580af211..70655bab45c 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -20,6 +20,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize, =20 #if !defined(CONFIG_USER_ONLY) =20 +void mmu_init(CPUMIPSState *env, const mips_def_t *def); + void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); =20 uint32_t cpu_mips_get_random(CPUMIPSState *env); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index a751c958329..c3159e3d7f3 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -708,7 +708,7 @@ static void mips_cpu_realizefn(DeviceState *dev, Error = **errp) =20 env->exception_base =3D (int32_t)0xBFC00000; =20 -#ifndef CONFIG_USER_ONLY +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) mmu_init(env, env->cpu_model); #endif fpu_init(env, env->cpu_model); --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) client-ip=209.85.221.41; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f41.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619972282; cv=none; d=zohomail.com; s=zohoarc; b=UTRcOSCAzRlLZUlP/c9/bB5RoF5dHBlZ1E+A4AILRqJk4Igq6ilfThJ/SQ5x6O8a+qWEwQNcrLa9NPTjmIaLgLwyX0s7AuQnYeVHTFCHiKbmO95kdhTMHC8UpURqL7hkA14b7NhA0i/6xamMVJw0QvoPh1EKTSzauVR7x56IjB4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972282; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZETGpx4nbZfkaug+OflFl89N3mWc3Om9YqwBm01M7wo=; b=AKWq9L742g6l1hlrVqELHlqxXwFHw9PQ6KvWtrwEYRwR/dr/LWcGR7BcXSNra97Cd/s5LPaMZpKa1EzO2lB8PIG6Va79LMBRS0Xb6yGRHxlcEi1/yzOwyEXbhdFMCmAoGxYTMh5Pxgi2YA6ansMptjF8CR6fkUCJE+ozXANi4p0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) by mx.zohomail.com with SMTPS id 1619972282468411.77125088904756; Sun, 2 May 2021 09:18:02 -0700 (PDT) Received: by mail-wr1-f41.google.com with SMTP id v12so3094492wrq.6 for ; Sun, 02 May 2021 09:18:01 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (anancy-651-1-208-144.w109-217.abo.wanadoo.fr. [109.217.237.144]) by smtp.gmail.com with ESMTPSA id b6sm17735676wmj.2.2021.05.02.09.17.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:18:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZETGpx4nbZfkaug+OflFl89N3mWc3Om9YqwBm01M7wo=; b=kaEi/DPSsdIDlQQdGBQDEHlHP28upTUjCWZE2JCjjRRvaZkxK8ErFtsHElkiv1plKm xUyuJz4qrYOBXlaXjRlyoiOrLKm88yERmcIR7NlYtvCYp8cTtsUe7Xn1LWXbSa72Cz/a XFxfvG5CGYV+Gs8u90FZrdfD87LtLtMUKQvyfl7Zw9Gf27xfuvY2M03yPmHbdkduEoZh mNIdwMKpDuvOmWk7JpRuZb1qYY1jJ2Y6LqgczIEp1EZQ7ShQGzd1lwov4w5Epz3zoG5H ng1SUrk3+S0sB4bp2yjMT213iB8sKbasga/HhxY6qQc5X+Yxdy26iOAvoJKljnd/qDd1 LmsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ZETGpx4nbZfkaug+OflFl89N3mWc3Om9YqwBm01M7wo=; b=MvXw79SKnWmQnoubdcJNpkzP5CpMDCYB9ZFotHfyGN1biF6TbgVG6YRTMU9YeuKqKB ac+OWNdQQC7rqiuEniEx96joM42zT/G78qzGAwziaDsNSWvI77tDlyvfYRC996fw5w3h PsLkMw4aqRK8fmTAsuOILATBVs1hGxM2/p5j4sojyaZEhjw1hkdKvCUIJLMMiqk4kAhy e0VRdlrJBN6P/njA1BUnvwbVyZWR4+y2LECPrUotlR26IMvMWZOT6sQpYGqnLzTe5uyI 33MCIA88DpKlKeTinHmS4d5cTGmPHhnrgQXwhNnFmbsbspmqQVkIXw+TMsjF5hyeAcCe sz6A== X-Gm-Message-State: AOAM531TU1qezMcZKb7miwGKtqbT1QDL3g4NqlM1LIbtSc9eAsp6zud7 yZkDqasu3ksDjHwXyeZbDZw= X-Google-Smtp-Source: ABdhPJwulmc+QzUi061YtUWveAy93AK4kEHrf45Vlm2IgKs5W8kcyrDlexGRfkGzdigloJvFAL62Mw== X-Received: by 2002:adf:f502:: with SMTP id q2mr20100401wro.171.1619972280737; Sun, 02 May 2021 09:18:00 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 27/36] target/mips: Move tlb_helper.c to tcg/sysemu/ Date: Sun, 2 May 2021 18:15:29 +0200 Message-Id: <20210502161538.534038-28-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move tlb_helper.c to the tcg/sysemu/ subdir, along with the following 3 declarations to tcg-internal.h: - cpu_mips_tlb_flush() - cpu_mips_translate_address() - r4k_invalidate_tlb() Simplify tlb_helper.c #ifdef'ry because files in tcg/sysemu/ are only build when sysemu mode is configured. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-22-f4bug@amsat.org> --- target/mips/internal.h | 5 ----- target/mips/tcg/tcg-internal.h | 5 +++++ target/mips/{ =3D> tcg/sysemu}/tlb_helper.c | 3 --- target/mips/meson.build | 1 - target/mips/tcg/sysemu/meson.build | 1 + 5 files changed, 6 insertions(+), 9 deletions(-) rename target/mips/{ =3D> tcg/sysemu}/tlb_helper.c (99%) diff --git a/target/mips/internal.h b/target/mips/internal.h index 2c9666905df..558cdca4e84 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -164,16 +164,12 @@ void r4k_helper_tlbp(CPUMIPSState *env); void r4k_helper_tlbr(CPUMIPSState *env); void r4k_helper_tlbinv(CPUMIPSState *env); void r4k_helper_tlbinvf(CPUMIPSState *env); -void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); =20 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retadd= r); -hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, - MMUAccessType access_type, uintptr_t ret= addr); - extern const VMStateDescription vmstate_mips_cpu; =20 #endif /* !CONFIG_USER_ONLY */ @@ -423,7 +419,6 @@ static inline void compute_hflags(CPUMIPSState *env) } } =20 -void cpu_mips_tlb_flush(CPUMIPSState *env); void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 70655bab45c..a39ff45d58f 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -24,8 +24,13 @@ void mmu_init(CPUMIPSState *env, const mips_def_t *def); =20 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); =20 +void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); uint32_t cpu_mips_get_random(CPUMIPSState *env); =20 +hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, + MMUAccessType access_type, uintptr_t ret= addr); +void cpu_mips_tlb_flush(CPUMIPSState *env); + #endif /* !CONFIG_USER_ONLY */ =20 #endif diff --git a/target/mips/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c similarity index 99% rename from target/mips/tlb_helper.c rename to target/mips/tcg/sysemu/tlb_helper.c index bfb08eaf506..bf242f5e65a 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -25,8 +25,6 @@ #include "exec/log.h" #include "hw/mips/cpudevs.h" =20 -#if !defined(CONFIG_USER_ONLY) - /* no MMU emulation */ int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, MMUAccessType access_type) @@ -1072,4 +1070,3 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, i= nt use_extra) } } } -#endif /* !CONFIG_USER_ONLY */ diff --git a/target/mips/meson.build b/target/mips/meson.build index a55af1cd6cf..ff5eb210dfd 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -31,7 +31,6 @@ 'msa_translate.c', 'op_helper.c', 'rel6_translate.c', - 'tlb_helper.c', 'translate.c', 'translate_addr_const.c', 'txx9_translate.c', diff --git a/target/mips/tcg/sysemu/meson.build b/target/mips/tcg/sysemu/me= son.build index 5c3024e7760..73ab9571ba6 100644 --- a/target/mips/tcg/sysemu/meson.build +++ b/target/mips/tcg/sysemu/meson.build @@ -1,4 +1,5 @@ mips_softmmu_ss.add(files( 'cp0_helper.c', 'mips-semi.c', + 'tlb_helper.c', )) --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.45 as permitted sender) client-ip=209.85.128.45; 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[109.217.237.144]) by smtp.gmail.com with ESMTPSA id v15sm12080084wmj.39.2021.05.02.09.18.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:18:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8Q+raHQIs2wulUOjH/a7oHvrT+XycjGTmZz6SqSk5mc=; b=E2DF2nkUs6uteuMxtb98eFPf8P9erq8hWAQmMX2Tft7uDoPxF3TgbcIpnz3IoZnaPr NXDVHO98Nz5RGah9UGL4guTomUYTAi1F3Te5iX7xLbQFCtIeSTm++NIAobH6SnH813P6 xv88bAd2jKP7SBtYhZB/Tum9pLefmI/xKt/wMFfqPwGttyRcsOUpiP/2QkLxWppXhIm+ SFnYm9qt6Gn8rQoUU7Ju++qr9uMcasn+aLMdFL4HTPxoShQ7QVfLIJoUl53eo35jRZuB 0jiBmgi/JbdAu+pgJVcPNpzpcs95Q6RNt6L8X66YEAaqZdqaYJYbmz0GZC3jiwjCiSc7 CW+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=8Q+raHQIs2wulUOjH/a7oHvrT+XycjGTmZz6SqSk5mc=; b=MPdwdLZ585MgML7LCA9OZso1CmV5oFNb4/ZvE0VMrGsEpTGRgw+3+2e4WuT44SKBmq Q0DNUt+AJupqy019G3JmR9XhXcid1FN6TAqxzY3o5a6w6efkC2e57J/XelWMquQNb9HH Fcnf305RBl10jncZdYfMSJOtnAhVlon0g5eG8uY2zjjawnWtU5mAJv+gVyyiyJzTGbPV wrL7wipLc2byI4r8C3mAPAjL+aOm6qEn1SAlLtkNDdJ234Z2geFp1pvI/rYbY5TDpxmR 9g6LgkKFEGyebD1zH+tuAlEL8O4DcLHN0HWskZKsMb+MSKQuum8w8JQh+1uYkOv3uKfa KUJw== X-Gm-Message-State: AOAM530xsJp2dNp+dE0RYS77FDizlCJqo6kBBOuysSmvgSVzDONSrThM aQkCpZymFmMceWVqwq9FNz0= X-Google-Smtp-Source: ABdhPJyllZyy74XvsUEauqP0ikYhe1w/hstBcKQW8Be4dITfAgbMLpBhqSdlHHeoePQkh5QN9qwWGw== X-Received: by 2002:a05:600c:4f44:: with SMTP id m4mr17257677wmq.50.1619972285754; Sun, 02 May 2021 09:18:05 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 28/36] target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope Date: Sun, 2 May 2021 18:15:30 +0200 Message-Id: <20210502161538.534038-29-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The 3 map_address() handlers are local to tlb_helper.c, no need to have their prototype declared publically. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-23-f4bug@amsat.org> --- target/mips/internal.h | 6 ------ target/mips/tcg/sysemu/tlb_helper.c | 13 +++++++------ 2 files changed, 7 insertions(+), 12 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 558cdca4e84..c1751700731 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -152,12 +152,6 @@ struct CPUMIPSTLBContext { } mmu; }; =20 -int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type); -int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type); -int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type); void r4k_helper_tlbwi(CPUMIPSState *env); void r4k_helper_tlbwr(CPUMIPSState *env); void r4k_helper_tlbp(CPUMIPSState *env); diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/t= lb_helper.c index bf242f5e65a..a45146a2b21 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -26,8 +26,8 @@ #include "hw/mips/cpudevs.h" =20 /* no MMU emulation */ -int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type) +static int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *pr= ot, + target_ulong address, MMUAccessType access_t= ype) { *physical =3D address; *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -35,8 +35,9 @@ int no_mmu_map_address(CPUMIPSState *env, hwaddr *physica= l, int *prot, } =20 /* fixed mapping MMU emulation */ -int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type) +static int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong address, + MMUAccessType access_type) { if (address <=3D (int32_t)0x7FFFFFFFUL) { if (!(env->CP0_Status & (1 << CP0St_ERL))) { @@ -55,8 +56,8 @@ int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *phys= ical, int *prot, } =20 /* MIPS32/MIPS64 R4000-style MMU emulation */ -int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type) +static int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, + target_ulong address, MMUAccessType access_type) { uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; uint32_t MMID =3D env->CP0_MemoryMapID; --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) client-ip=209.85.221.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619972293; cv=none; d=zohomail.com; s=zohoarc; b=ngJ0GswauDwEWkCJqH9sk8cEBUbc3+4IM6zI3HwjQz/n/+/t9jNPDJMe5Q/uug6QECKcap/35VnsyTNl39OlkBGg/pPXQJrUPqPPux6sM23hwBpm6hmICmmYS1RHqDYMW9737ZlERj5FSiSK5G46ffeyzM74b/Z8evpWHt0C6s4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972293; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=x19cjSTQwIq79xCZBtZq0kMD0w0hQS1PLNYgzSi3WfA=; b=GIhbrs+tnPsS6BVAQ34dxrbTW4NnefS7moBuP2VSjJhH8PeIQJ4P3ivwTDxXq4vvYDrFYkckyDCnxdmTV18ntE/wD/O3A7OOU6lNe4hjxl3c8+89bb8fFJ15yhrPgA7P2AEgK5KOTNJkC39wJ8XBIwBGSvHrfie9rceh9XSddLQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) by mx.zohomail.com with SMTPS id 1619972293086236.6396288528781; Sun, 2 May 2021 09:18:13 -0700 (PDT) Received: by mail-wr1-f48.google.com with SMTP id x5so3070320wrv.13 for ; Sun, 02 May 2021 09:18:12 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (anancy-651-1-208-144.w109-217.abo.wanadoo.fr. [109.217.237.144]) by smtp.gmail.com with ESMTPSA id i14sm19973067wmq.1.2021.05.02.09.18.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:18:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=x19cjSTQwIq79xCZBtZq0kMD0w0hQS1PLNYgzSi3WfA=; b=A4ttA+zHp2WsueJxPjCtFWT5UHVmP4jc3UV3g3fFL5an21X4DZflQ4F76PDYnmVG8T XmdZxEhARPCihriOsAP2Kzc2Zom8npIcePCIV5sLF7zWhnjIfkUWvkYH6zyD82D9BYCy tHchhNbnN/aTbtZBs7lFyEqvSAe9SyW3AF8yBP/ZEzkE9Uo5Vd5UVcs3yULGYvpOTSuw UVydqkuX6zIFdwnOwOc7wInXMkPJK6xIfctARC5uwoZClGgJd114ZFbJH9IxvBmJ3C8P UjSIQKIUf4byEQVDELeXuFMi1Tav/PvmqF0QqnSxO1ThWCjQrpVZCbv74qGGsJRnGv2F 3PUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=x19cjSTQwIq79xCZBtZq0kMD0w0hQS1PLNYgzSi3WfA=; b=uleIR+rX0maJsS7i+1gDiXRMXTlbRUcjTZrfWidlUiU50+xaqtdm2Gd9/zJb/ciMFz VBDxT+vFjUfrjEVOKW5p0OQzVBfHiHm6yj1aJBXFAmVJ0BERT8ad7r1mD+ntooYvavub diC6s8+B5a62Ikv303lOs6tEyY9u/wkByKTwsdJKxFIgTu63Ub+aezayzN9gpV9rxTsF I5LeLfZXalQf/sML7rOYyZaDmYu7oQaiWrfGHmudMX8lWKCr/sJeMqXX+lKCQTKImHtb VFWyQT8uXjJBIobuDqnJqxRd5ck2JgPJdCmFVZYVFRjIQghRVgVYglzAGmns6F3siwHx gdCA== X-Gm-Message-State: AOAM5301+ScmrdzYS+0dwOds2u7nfxlLsOrBdSzErL1n0mMPFAdKT344 CyLTWX2sozgKDPockR22eWU= X-Google-Smtp-Source: ABdhPJxRcyAKZZLkHM4YGYD8RxiYjSDkFA6wiDQW6loOS1BsPKyAolVX/XjLWmUhRMZ7pA+LapdweA== X-Received: by 2002:a5d:4707:: with SMTP id y7mr20149320wrq.137.1619972291271; Sun, 02 May 2021 09:18:11 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 29/36] target/mips: Move Special opcodes to tcg/sysemu/special_helper.c Date: Sun, 2 May 2021 18:15:31 +0200 Message-Id: <20210502161538.534038-30-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move the Special opcodes helpers to tcg/sysemu/special_helper.c. Since mips_io_recompile_replay_branch() is set as CPUClass::io_recompile_replay_branch handler in cpu.c, we need to declare its prototype in "tcg-internal.h". Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-24-f4bug@amsat.org> --- target/mips/helper.h | 5 - target/mips/tcg/tcg-internal.h | 3 + target/mips/tcg/sysemu_helper.h.inc | 7 ++ target/mips/cpu.c | 17 --- target/mips/op_helper.c | 100 ----------------- target/mips/tcg/sysemu/special_helper.c | 140 ++++++++++++++++++++++++ target/mips/tcg/sysemu/meson.build | 1 + 7 files changed, 151 insertions(+), 122 deletions(-) create mode 100644 target/mips/tcg/sysemu/special_helper.c diff --git a/target/mips/helper.h b/target/mips/helper.h index bc308e5db13..4ee7916d8b2 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -210,11 +210,6 @@ DEF_HELPER_1(tlbp, void, env) DEF_HELPER_1(tlbr, void, env) DEF_HELPER_1(tlbinv, void, env) DEF_HELPER_1(tlbinvf, void, env) -DEF_HELPER_1(di, tl, env) -DEF_HELPER_1(ei, tl, env) -DEF_HELPER_1(eret, void, env) -DEF_HELPER_1(eretnc, void, env) -DEF_HELPER_1(deret, void, env) DEF_HELPER_3(ginvt, void, env, tl, i32) #endif /* !CONFIG_USER_ONLY */ DEF_HELPER_1(rdhwr_cpunum, tl, env) diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index a39ff45d58f..73667b35778 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -10,6 +10,7 @@ #ifndef MIPS_TCG_INTERNAL_H #define MIPS_TCG_INTERNAL_H =20 +#include "tcg/tcg.h" #include "hw/core/cpu.h" #include "cpu.h" =20 @@ -27,6 +28,8 @@ void update_pagemask(CPUMIPSState *env, target_ulong arg1= , int32_t *pagemask); void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); uint32_t cpu_mips_get_random(CPUMIPSState *env); =20 +bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock = *tb); + hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, MMUAccessType access_type, uintptr_t ret= addr); void cpu_mips_tlb_flush(CPUMIPSState *env); diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_h= elper.h.inc index d136c4160a7..38e55cbf118 100644 --- a/target/mips/tcg/sysemu_helper.h.inc +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -166,3 +166,10 @@ DEF_HELPER_1(evpe, tl, env) /* R6 Multi-threading */ DEF_HELPER_1(dvp, tl, env) DEF_HELPER_1(evp, tl, env) + +/* Special */ +DEF_HELPER_1(di, tl, env) +DEF_HELPER_1(ei, tl, env) +DEF_HELPER_1(eret, void, env) +DEF_HELPER_1(eretnc, void, env) +DEF_HELPER_1(deret, void, env) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index c3159e3d7f3..a33e3b6c202 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -342,23 +342,6 @@ static void mips_cpu_synchronize_from_tb(CPUState *cs, env->hflags &=3D ~MIPS_HFLAG_BMASK; env->hflags |=3D tb->flags & MIPS_HFLAG_BMASK; } - -# ifndef CONFIG_USER_ONLY -static bool mips_io_recompile_replay_branch(CPUState *cs, - const TranslationBlock *tb) -{ - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - - if ((env->hflags & MIPS_HFLAG_BMASK) !=3D 0 - && env->active_tc.PC !=3D tb->pc) { - env->active_tc.PC -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); - env->hflags &=3D ~MIPS_HFLAG_BMASK; - return true; - } - return false; -} -# endif /* !CONFIG_USER_ONLY */ #endif /* CONFIG_TCG */ =20 static bool mips_cpu_has_work(CPUState *cs) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 7a7369bc8a6..a077535194b 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -655,106 +655,6 @@ void helper_ginvt(CPUMIPSState *env, target_ulong arg= , uint32_t type) } } =20 -/* Specials */ -target_ulong helper_di(CPUMIPSState *env) -{ - target_ulong t0 =3D env->CP0_Status; - - env->CP0_Status =3D t0 & ~(1 << CP0St_IE); - return t0; -} - -target_ulong helper_ei(CPUMIPSState *env) -{ - target_ulong t0 =3D env->CP0_Status; - - env->CP0_Status =3D t0 | (1 << CP0St_IE); - return t0; -} - -static void debug_pre_eret(CPUMIPSState *env) -{ - if (qemu_loglevel_mask(CPU_LOG_EXEC)) { - qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, - env->active_tc.PC, env->CP0_EPC); - if (env->CP0_Status & (1 << CP0St_ERL)) { - qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); - } - if (env->hflags & MIPS_HFLAG_DM) { - qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); - } - qemu_log("\n"); - } -} - -static void debug_post_eret(CPUMIPSState *env) -{ - if (qemu_loglevel_mask(CPU_LOG_EXEC)) { - qemu_log(" =3D> PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, - env->active_tc.PC, env->CP0_EPC); - if (env->CP0_Status & (1 << CP0St_ERL)) { - qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); - } - if (env->hflags & MIPS_HFLAG_DM) { - qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); - } - switch (cpu_mmu_index(env, false)) { - case 3: - qemu_log(", ERL\n"); - break; - case MIPS_HFLAG_UM: - qemu_log(", UM\n"); - break; - case MIPS_HFLAG_SM: - qemu_log(", SM\n"); - break; - case MIPS_HFLAG_KM: - qemu_log("\n"); - break; - default: - cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); - break; - } - } -} - -static inline void exception_return(CPUMIPSState *env) -{ - debug_pre_eret(env); - if (env->CP0_Status & (1 << CP0St_ERL)) { - mips_env_set_pc(env, env->CP0_ErrorEPC); - env->CP0_Status &=3D ~(1 << CP0St_ERL); - } else { - mips_env_set_pc(env, env->CP0_EPC); - env->CP0_Status &=3D ~(1 << CP0St_EXL); - } - compute_hflags(env); - debug_post_eret(env); -} - -void helper_eret(CPUMIPSState *env) -{ - exception_return(env); - env->CP0_LLAddr =3D 1; - env->lladdr =3D 1; -} - -void helper_eretnc(CPUMIPSState *env) -{ - exception_return(env); -} - -void helper_deret(CPUMIPSState *env) -{ - debug_pre_eret(env); - - env->hflags &=3D ~MIPS_HFLAG_DM; - compute_hflags(env); - - mips_env_set_pc(env, env->CP0_DEPC); - - debug_post_eret(env); -} #endif /* !CONFIG_USER_ONLY */ =20 static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc) diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/syse= mu/special_helper.c new file mode 100644 index 00000000000..971883fa385 --- /dev/null +++ b/target/mips/tcg/sysemu/special_helper.c @@ -0,0 +1,140 @@ +/* + * QEMU MIPS emulation: Special opcode helpers + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "exec/exec-all.h" +#include "internal.h" + +/* Specials */ +target_ulong helper_di(CPUMIPSState *env) +{ + target_ulong t0 =3D env->CP0_Status; + + env->CP0_Status =3D t0 & ~(1 << CP0St_IE); + return t0; +} + +target_ulong helper_ei(CPUMIPSState *env) +{ + target_ulong t0 =3D env->CP0_Status; + + env->CP0_Status =3D t0 | (1 << CP0St_IE); + return t0; +} + +static void debug_pre_eret(CPUMIPSState *env) +{ + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { + qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, + env->active_tc.PC, env->CP0_EPC); + if (env->CP0_Status & (1 << CP0St_ERL)) { + qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); + } + if (env->hflags & MIPS_HFLAG_DM) { + qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); + } + qemu_log("\n"); + } +} + +static void debug_post_eret(CPUMIPSState *env) +{ + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { + qemu_log(" =3D> PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, + env->active_tc.PC, env->CP0_EPC); + if (env->CP0_Status & (1 << CP0St_ERL)) { + qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); + } + if (env->hflags & MIPS_HFLAG_DM) { + qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); + } + switch (cpu_mmu_index(env, false)) { + case 3: + qemu_log(", ERL\n"); + break; + case MIPS_HFLAG_UM: + qemu_log(", UM\n"); + break; + case MIPS_HFLAG_SM: + qemu_log(", SM\n"); + break; + case MIPS_HFLAG_KM: + qemu_log("\n"); + break; + default: + cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); + break; + } + } +} + +bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock = *tb) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + if ((env->hflags & MIPS_HFLAG_BMASK) !=3D 0 + && env->active_tc.PC !=3D tb->pc) { + env->active_tc.PC -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); + env->hflags &=3D ~MIPS_HFLAG_BMASK; + return true; + } + return false; +} + +static inline void exception_return(CPUMIPSState *env) +{ + debug_pre_eret(env); + if (env->CP0_Status & (1 << CP0St_ERL)) { + mips_env_set_pc(env, env->CP0_ErrorEPC); + env->CP0_Status &=3D ~(1 << CP0St_ERL); + } else { + mips_env_set_pc(env, env->CP0_EPC); + env->CP0_Status &=3D ~(1 << CP0St_EXL); + } + compute_hflags(env); + debug_post_eret(env); +} + +void helper_eret(CPUMIPSState *env) +{ + exception_return(env); + env->CP0_LLAddr =3D 1; + env->lladdr =3D 1; +} + +void helper_eretnc(CPUMIPSState *env) +{ + exception_return(env); +} + +void helper_deret(CPUMIPSState *env) +{ + debug_pre_eret(env); + + env->hflags &=3D ~MIPS_HFLAG_DM; + compute_hflags(env); + + mips_env_set_pc(env, env->CP0_DEPC); + + debug_post_eret(env); +} diff --git a/target/mips/tcg/sysemu/meson.build b/target/mips/tcg/sysemu/me= son.build index 73ab9571ba6..4da2c577b20 100644 --- a/target/mips/tcg/sysemu/meson.build +++ b/target/mips/tcg/sysemu/meson.build @@ -1,5 +1,6 @@ mips_softmmu_ss.add(files( 'cp0_helper.c', 'mips-semi.c', + 'special_helper.c', 'tlb_helper.c', )) --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) client-ip=209.85.221.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619972299; cv=none; d=zohomail.com; s=zohoarc; b=FEWQuEjYNgZtILIM1zApejlH+TAlFloJSRqaRXdzdcMJ72h3Xt2unS1zpcX1g4bM7+qS/388ESoL6+4TqcIJVnrhWAJEZuHVy+syDd/S4G84M7rUdbImU295XxKkMcMZaMk0rM29YBh50Ep4d1Yz0TOBGD3v35BUu8R8V61ZNIs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972299; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xccbGy6b98qgbGQkHPDUbNVvkJNRN81dhxs2umRUhSw=; b=CH4m88PuSZ2aUERSRBAp4SzMCJesYKZoXzc5VCPGB6/jk1ulmPkcnMYmzGh+DripVihtrRQeU8AEcU53u/IKQKg1vM+juyouTHQABc6Ye+2W1eoFkUSrLX7o90nhGx0auW4mVEO227dwQlRyEN1vyATjkbWRw/QX7vt2npSiJDg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) by mx.zohomail.com with SMTPS id 1619972299042467.7169653135486; Sun, 2 May 2021 09:18:19 -0700 (PDT) Received: by mail-wr1-f52.google.com with SMTP id d11so3098993wrw.8 for ; Sun, 02 May 2021 09:18:18 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (anancy-651-1-208-144.w109-217.abo.wanadoo.fr. [109.217.237.144]) by smtp.gmail.com with ESMTPSA id y11sm9957508wmi.41.2021.05.02.09.18.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:18:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xccbGy6b98qgbGQkHPDUbNVvkJNRN81dhxs2umRUhSw=; b=ecF/9lr+hie3NweRrMMK1MAdXXNnz5upv43OAVFoBENmA5viYY/O/41RgjfdbDWqQP 0rm6xf3TnGHiF24PbIMcGGVwqEp0Kwq0/UjZnnvoNUPiJENWNZDiLrQAdu2N/elSjJEQ bH/i5sFeaBoLgNsor3wYa++vj0QLMocaAmZw5Y99pO7r79O1I6sjH+26HyKw5k+151Tj IGhwdvls1Nnzls+M6awYC2yhGt1u+jJOyuEUmfRn3TyB+WGCh4qH6W8AnyBQu/Hx+rah 9H5nJl5DCwxtZotfFbgbxT3jflI7ho2A6JOYD2hiBUiJqIrs32W30GnBkA1mNikaCebV gsKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=xccbGy6b98qgbGQkHPDUbNVvkJNRN81dhxs2umRUhSw=; b=miYaDg5D9f+djIPTI70k3eNZSpw+uMzaBTNWLipsqvryHedoN6IFTSwvo4U9wXWW4k X61YfR99s8t/Io7PIV1VTNt54NJrXqIJ2xLxeo8MQCeJvsTbpbE8+mhMxsUppluLrIes Xa4u8mf4R18MdyG/uMW2pYTnXqG0JuUCh6wJj/DFS+gRX7xeiFufUftwNigtml6b9VHK njO1Zb0yQF12ouZxQf2T/c1Rz/Qlt5QfR+PLqngyM+ZJCSoGGZE0T4fZ1nmzwzAmJo9x o2KHvTxQTDkUdYyFrs0nbbMMooNbxsWRLg+daAARiwM5Y3sy6dvCvCGQjvA/envJvY0v jsNQ== X-Gm-Message-State: AOAM533iaIB/4nOciYIicwQx1pYzHtPWZHCfTIYSJsHFlCYVoQhlmNr0 mbGEyGiclfy4ioUIor2045ytXsfz31ScOvXN X-Google-Smtp-Source: ABdhPJxVi4cTo+yE0W0+dhrKlvcpyRuI+1eq68wDiKWX6LSaD/5Q1BBlehNbec6Oy4eSxWUHoyqtOw== X-Received: by 2002:adf:fe8e:: with SMTP id l14mr19445161wrr.305.1619972297360; Sun, 02 May 2021 09:18:17 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 30/36] target/mips: Move helper_cache() to tcg/sysemu/special_helper.c Date: Sun, 2 May 2021 18:15:32 +0200 Message-Id: <20210502161538.534038-31-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move helper_cache() to tcg/sysemu/special_helper.c. The CACHE opcode is privileged and is not accessible in user emulation. However we get a link failure when restricting the symbol to sysemu. For now, add a stub helper to satisfy linking, which abort if ever called. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-25-f4bug@amsat.org> --- target/mips/helper.h | 2 -- target/mips/tcg/sysemu_helper.h.inc | 1 + target/mips/op_helper.c | 35 ------------------------- target/mips/tcg/sysemu/special_helper.c | 33 +++++++++++++++++++++++ target/mips/translate.c | 13 +++++++++ 5 files changed, 47 insertions(+), 37 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 4ee7916d8b2..d49620f9282 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -614,8 +614,6 @@ DEF_HELPER_FLAGS_3(dmthlip, 0, void, tl, tl, env) DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env) DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) =20 -DEF_HELPER_3(cache, void, env, tl, i32) - #ifndef CONFIG_USER_ONLY #include "tcg/sysemu_helper.h.inc" #endif /* !CONFIG_USER_ONLY */ diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_h= elper.h.inc index 38e55cbf118..1ccbf687237 100644 --- a/target/mips/tcg/sysemu_helper.h.inc +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -173,3 +173,4 @@ DEF_HELPER_1(ei, tl, env) DEF_HELPER_1(eret, void, env) DEF_HELPER_1(eretnc, void, env) DEF_HELPER_1(deret, void, env) +DEF_HELPER_3(cache, void, env, tl, i32) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index a077535194b..a7fe1de8c42 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -788,38 +788,3 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, } } #endif /* !CONFIG_USER_ONLY */ - -void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op) -{ -#ifndef CONFIG_USER_ONLY - static const char *const type_name[] =3D { - "Primary Instruction", - "Primary Data or Unified Primary", - "Tertiary", - "Secondary" - }; - uint32_t cache_type =3D extract32(op, 0, 2); - uint32_t cache_operation =3D extract32(op, 2, 3); - target_ulong index =3D addr & 0x1fffffff; - - switch (cache_operation) { - case 0b010: /* Index Store Tag */ - memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo, - MO_64, MEMTXATTRS_UNSPECIFIED); - break; - case 0b001: /* Index Load Tag */ - memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo, - MO_64, MEMTXATTRS_UNSPECIFIED); - break; - case 0b000: /* Index Invalidate */ - case 0b100: /* Hit Invalidate */ - case 0b110: /* Hit Writeback */ - /* no-op */ - break; - default: - qemu_log_mask(LOG_UNIMP, "cache operation:%u (type: %s cache)\n", - cache_operation, type_name[cache_type]); - break; - } -#endif -} diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/syse= mu/special_helper.c index 971883fa385..2a2afb49e81 100644 --- a/target/mips/tcg/sysemu/special_helper.c +++ b/target/mips/tcg/sysemu/special_helper.c @@ -138,3 +138,36 @@ void helper_deret(CPUMIPSState *env) =20 debug_post_eret(env); } + +void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op) +{ + static const char *const type_name[] =3D { + "Primary Instruction", + "Primary Data or Unified Primary", + "Tertiary", + "Secondary" + }; + uint32_t cache_type =3D extract32(op, 0, 2); + uint32_t cache_operation =3D extract32(op, 2, 3); + target_ulong index =3D addr & 0x1fffffff; + + switch (cache_operation) { + case 0b010: /* Index Store Tag */ + memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo, + MO_64, MEMTXATTRS_UNSPECIFIED); + break; + case 0b001: /* Index Load Tag */ + memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo, + MO_64, MEMTXATTRS_UNSPECIFIED); + break; + case 0b000: /* Index Invalidate */ + case 0b100: /* Hit Invalidate */ + case 0b110: /* Hit Writeback */ + /* no-op */ + break; + default: + qemu_log_mask(LOG_UNIMP, "cache operation:%u (type: %s cache)\n", + cache_operation, type_name[cache_type]); + break; + } +} diff --git a/target/mips/translate.c b/target/mips/translate.c index f0ae3716022..c03a8ae1fed 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -39,6 +39,19 @@ #include "fpu_helper.h" #include "translate.h" =20 +/* + * Many sysemu-only helpers are not reachable for user-only. + * Define stub generators here, so that we need not either sprinkle + * ifdefs through the translator, nor provide the helper function. + */ +#define STUB_HELPER(NAME, ...) \ + static inline void gen_helper_##NAME(__VA_ARGS__) \ + { g_assert_not_reached(); } + +#ifdef CONFIG_USER_ONLY +STUB_HELPER(cache, TCGv_env env, TCGv val, TCGv_i32 reg) +#endif + enum { /* indirect opcode tables */ OPC_SPECIAL =3D (0x00 << 26), --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) client-ip=209.85.128.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1619972304; cv=none; d=zohomail.com; s=zohoarc; b=VLHMKo+gDbmLZeGQrngVJpY/G1Tyvrf0ci6Md/CeTc/R2O7hKdUjlj6aLUA7eQJz7GWt+UfYEMer6vnR0QlVrsW1ZaZPIZTUaGH0z9ZCk8qJlz5VoTyWu3t6BsPkqZ/nFa8Fd89gEqhMVCC/DWpv1s1PnLh2ZWJjHk7r5HnXtvc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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[109.217.237.144]) by smtp.gmail.com with ESMTPSA id v18sm10905506wro.18.2021.05.02.09.18.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:18:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fOCW3qxGbXTdprDd4pm0/slzthSBWtj0LaXQ5LQYGS4=; b=DaOHrrsXajWQftZOLnUKkkoUl6Uteq/7Yy0Tr+UXc0xV6zwbe2xljdJMSPXnJZDN9N +Xpzfowz/7EJ0fu8Iq3m/1MRtKWRj9TqIR63QHqomk1RRKRrsVQivcH+5H9tvRLipz4p VZ0O6dqkURHkqbY/5w+76Wl0dALASpiS4tAvMGgXrb16vCA0kLOl3KJqH746jQOHq6V9 UfBdCGH9HMyfCLHw1dNnXK2A+3rMp1ndNfTASJhxOktQ6I+32zbPspuZgvS1563qHR61 OxQw5grkInjkznVUp0nIlR9q+CjcSkT7mhwiR0UVI8Yxh81/rmrXQLrdp07CEF+XYpS9 iWvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=fOCW3qxGbXTdprDd4pm0/slzthSBWtj0LaXQ5LQYGS4=; b=DlWRDizAhSfV8WzvvZ9WhMP1ddTDnLP6SULSWJCRpTqoYFv6bN0ll0hy7hFU5pFaSm hUPfE5Afbvg/R0A2SLkyxxSd8hUk1d1FjrHa5NHTTdAnVIXqfNA6gob157+CY43m8Xyc 1iaD5joUNU8xFUImck2uV303jzNyEzSDJQ5rm7WqdhodaEiuLixyKe42kOYkMVPCXUzW BxglyjSxx83YmYHxYJ/kfhTapN/P7/2VHqzNGmh8mr1K7nZelreb1f3lgOhxICvJpgzC WD/4py6pfv//CXTe/heMB6mc1TZYnsA9147ssgeFnFHp392BbRmMX9004RclkbDfh0nM UMPg== X-Gm-Message-State: AOAM533B2BGABQnWPDfGb6auzmBrgKCC/LJAPaKrN70Bkz5U39967S1M k3ccXYbsxg+1wIAofqibn7c= X-Google-Smtp-Source: ABdhPJx+ma4EcM5KZQrOrOg+YKKtymjua/DB9dEjFADsAzN7xNbTLmj72UBHVyWeAdE2DBUacfedrA== X-Received: by 2002:a05:600c:3581:: with SMTP id p1mr26997623wmq.35.1619972302958; Sun, 02 May 2021 09:18:22 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 31/36] target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c Date: Sun, 2 May 2021 18:15:33 +0200 Message-Id: <20210502161538.534038-32-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move TLB management helpers to tcg/sysemu/tlb_helper.c. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-26-f4bug@amsat.org> --- target/mips/helper.h | 10 - target/mips/internal.h | 7 - target/mips/tcg/sysemu_helper.h.inc | 9 + target/mips/op_helper.c | 333 ---------------------------- target/mips/tcg/sysemu/tlb_helper.c | 331 +++++++++++++++++++++++++++ 5 files changed, 340 insertions(+), 350 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index d49620f9282..ba301ae160d 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -202,16 +202,6 @@ FOP_PROTO(sune) FOP_PROTO(sne) #undef FOP_PROTO =20 -/* Special functions */ -#ifndef CONFIG_USER_ONLY -DEF_HELPER_1(tlbwi, void, env) -DEF_HELPER_1(tlbwr, void, env) -DEF_HELPER_1(tlbp, void, env) -DEF_HELPER_1(tlbr, void, env) -DEF_HELPER_1(tlbinv, void, env) -DEF_HELPER_1(tlbinvf, void, env) -DEF_HELPER_3(ginvt, void, env, tl, i32) -#endif /* !CONFIG_USER_ONLY */ DEF_HELPER_1(rdhwr_cpunum, tl, env) DEF_HELPER_1(rdhwr_synci_step, tl, env) DEF_HELPER_1(rdhwr_cc, tl, env) diff --git a/target/mips/internal.h b/target/mips/internal.h index c1751700731..a1c7f658c2b 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -152,13 +152,6 @@ struct CPUMIPSTLBContext { } mmu; }; =20 -void r4k_helper_tlbwi(CPUMIPSState *env); -void r4k_helper_tlbwr(CPUMIPSState *env); -void r4k_helper_tlbp(CPUMIPSState *env); -void r4k_helper_tlbr(CPUMIPSState *env); -void r4k_helper_tlbinv(CPUMIPSState *env); -void r4k_helper_tlbinvf(CPUMIPSState *env); - void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_h= elper.h.inc index 1ccbf687237..4353a966f97 100644 --- a/target/mips/tcg/sysemu_helper.h.inc +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -167,6 +167,15 @@ DEF_HELPER_1(evpe, tl, env) DEF_HELPER_1(dvp, tl, env) DEF_HELPER_1(evp, tl, env) =20 +/* TLB */ +DEF_HELPER_1(tlbwi, void, env) +DEF_HELPER_1(tlbwr, void, env) +DEF_HELPER_1(tlbp, void, env) +DEF_HELPER_1(tlbr, void, env) +DEF_HELPER_1(tlbinv, void, env) +DEF_HELPER_1(tlbinvf, void, env) +DEF_HELPER_3(ginvt, void, env, tl, i32) + /* Special */ DEF_HELPER_1(di, tl, env) DEF_HELPER_1(ei, tl, env) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index a7fe1de8c42..cb2a7e96fc3 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -324,339 +324,6 @@ target_ulong helper_yield(CPUMIPSState *env, target_u= long arg) return env->CP0_YQMask; } =20 -#ifndef CONFIG_USER_ONLY -/* TLB management */ -static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first) -{ - /* Discard entries from env->tlb[first] onwards. */ - while (env->tlb->tlb_in_use > first) { - r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); - } -} - -static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo) -{ -#if defined(TARGET_MIPS64) - return extract64(entrylo, 6, 54); -#else - return extract64(entrylo, 6, 24) | /* PFN */ - (extract64(entrylo, 32, 32) << 24); /* PFNX */ -#endif -} - -static void r4k_fill_tlb(CPUMIPSState *env, int idx) -{ - r4k_tlb_t *tlb; - uint64_t mask =3D env->CP0_PageMask >> (TARGET_PAGE_BITS + 1); - - /* XXX: detect conflicting TLBs and raise a MCHECK exception when need= ed */ - tlb =3D &env->tlb->mmu.r4k.tlb[idx]; - if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) { - tlb->EHINV =3D 1; - return; - } - tlb->EHINV =3D 0; - tlb->VPN =3D env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); -#if defined(TARGET_MIPS64) - tlb->VPN &=3D env->SEGMask; -#endif - tlb->ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - tlb->MMID =3D env->CP0_MemoryMapID; - tlb->PageMask =3D env->CP0_PageMask; - tlb->G =3D env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; - tlb->V0 =3D (env->CP0_EntryLo0 & 2) !=3D 0; - tlb->D0 =3D (env->CP0_EntryLo0 & 4) !=3D 0; - tlb->C0 =3D (env->CP0_EntryLo0 >> 3) & 0x7; - tlb->XI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1; - tlb->RI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1; - tlb->PFN[0] =3D (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) = << 12; - tlb->V1 =3D (env->CP0_EntryLo1 & 2) !=3D 0; - tlb->D1 =3D (env->CP0_EntryLo1 & 4) !=3D 0; - tlb->C1 =3D (env->CP0_EntryLo1 >> 3) & 0x7; - tlb->XI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1; - tlb->RI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1; - tlb->PFN[1] =3D (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) = << 12; -} - -void r4k_helper_tlbinv(CPUMIPSState *env) -{ - bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); - uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - uint32_t MMID =3D env->CP0_MemoryMapID; - uint32_t tlb_mmid; - r4k_tlb_t *tlb; - int idx; - - MMID =3D mi ? MMID : (uint32_t) ASID; - for (idx =3D 0; idx < env->tlb->nb_tlb; idx++) { - tlb =3D &env->tlb->mmu.r4k.tlb[idx]; - tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; - if (!tlb->G && tlb_mmid =3D=3D MMID) { - tlb->EHINV =3D 1; - } - } - cpu_mips_tlb_flush(env); -} - -void r4k_helper_tlbinvf(CPUMIPSState *env) -{ - int idx; - - for (idx =3D 0; idx < env->tlb->nb_tlb; idx++) { - env->tlb->mmu.r4k.tlb[idx].EHINV =3D 1; - } - cpu_mips_tlb_flush(env); -} - -void r4k_helper_tlbwi(CPUMIPSState *env) -{ - bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); - target_ulong VPN; - uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - uint32_t MMID =3D env->CP0_MemoryMapID; - uint32_t tlb_mmid; - bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1; - r4k_tlb_t *tlb; - int idx; - - MMID =3D mi ? MMID : (uint32_t) ASID; - - idx =3D (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; - tlb =3D &env->tlb->mmu.r4k.tlb[idx]; - VPN =3D env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); -#if defined(TARGET_MIPS64) - VPN &=3D env->SEGMask; -#endif - EHINV =3D (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) !=3D 0; - G =3D env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; - V0 =3D (env->CP0_EntryLo0 & 2) !=3D 0; - D0 =3D (env->CP0_EntryLo0 & 4) !=3D 0; - XI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_XI) &1; - RI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_RI) &1; - V1 =3D (env->CP0_EntryLo1 & 2) !=3D 0; - D1 =3D (env->CP0_EntryLo1 & 4) !=3D 0; - XI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_XI) &1; - RI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_RI) &1; - - tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; - /* - * Discard cached TLB entries, unless tlbwi is just upgrading access - * permissions on the current entry. - */ - if (tlb->VPN !=3D VPN || tlb_mmid !=3D MMID || tlb->G !=3D G || - (!tlb->EHINV && EHINV) || - (tlb->V0 && !V0) || (tlb->D0 && !D0) || - (!tlb->XI0 && XI0) || (!tlb->RI0 && RI0) || - (tlb->V1 && !V1) || (tlb->D1 && !D1) || - (!tlb->XI1 && XI1) || (!tlb->RI1 && RI1)) { - r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); - } - - r4k_invalidate_tlb(env, idx, 0); - r4k_fill_tlb(env, idx); -} - -void r4k_helper_tlbwr(CPUMIPSState *env) -{ - int r =3D cpu_mips_get_random(env); - - r4k_invalidate_tlb(env, r, 1); - r4k_fill_tlb(env, r); -} - -void r4k_helper_tlbp(CPUMIPSState *env) -{ - bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); - r4k_tlb_t *tlb; - target_ulong mask; - target_ulong tag; - target_ulong VPN; - uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - uint32_t MMID =3D env->CP0_MemoryMapID; - uint32_t tlb_mmid; - int i; - - MMID =3D mi ? MMID : (uint32_t) ASID; - for (i =3D 0; i < env->tlb->nb_tlb; i++) { - tlb =3D &env->tlb->mmu.r4k.tlb[i]; - /* 1k pages are not supported. */ - mask =3D tlb->PageMask | ~(TARGET_PAGE_MASK << 1); - tag =3D env->CP0_EntryHi & ~mask; - VPN =3D tlb->VPN & ~mask; -#if defined(TARGET_MIPS64) - tag &=3D env->SEGMask; -#endif - tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; - /* Check ASID/MMID, virtual page number & size */ - if ((tlb->G =3D=3D 1 || tlb_mmid =3D=3D MMID) && VPN =3D=3D tag &&= !tlb->EHINV) { - /* TLB match */ - env->CP0_Index =3D i; - break; - } - } - if (i =3D=3D env->tlb->nb_tlb) { - /* No match. Discard any shadow entries, if any of them match. */ - for (i =3D env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) { - tlb =3D &env->tlb->mmu.r4k.tlb[i]; - /* 1k pages are not supported. */ - mask =3D tlb->PageMask | ~(TARGET_PAGE_MASK << 1); - tag =3D env->CP0_EntryHi & ~mask; - VPN =3D tlb->VPN & ~mask; -#if defined(TARGET_MIPS64) - tag &=3D env->SEGMask; -#endif - tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; - /* Check ASID/MMID, virtual page number & size */ - if ((tlb->G =3D=3D 1 || tlb_mmid =3D=3D MMID) && VPN =3D=3D ta= g) { - r4k_mips_tlb_flush_extra(env, i); - break; - } - } - - env->CP0_Index |=3D 0x80000000; - } -} - -static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn) -{ -#if defined(TARGET_MIPS64) - return tlb_pfn << 6; -#else - return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */ - (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */ -#endif -} - -void r4k_helper_tlbr(CPUMIPSState *env) -{ - bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); - uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - uint32_t MMID =3D env->CP0_MemoryMapID; - uint32_t tlb_mmid; - r4k_tlb_t *tlb; - int idx; - - MMID =3D mi ? MMID : (uint32_t) ASID; - idx =3D (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; - tlb =3D &env->tlb->mmu.r4k.tlb[idx]; - - tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; - /* If this will change the current ASID/MMID, flush qemu's TLB. */ - if (MMID !=3D tlb_mmid) { - cpu_mips_tlb_flush(env); - } - - r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); - - if (tlb->EHINV) { - env->CP0_EntryHi =3D 1 << CP0EnHi_EHINV; - env->CP0_PageMask =3D 0; - env->CP0_EntryLo0 =3D 0; - env->CP0_EntryLo1 =3D 0; - } else { - env->CP0_EntryHi =3D mi ? tlb->VPN : tlb->VPN | tlb->ASID; - env->CP0_MemoryMapID =3D tlb->MMID; - env->CP0_PageMask =3D tlb->PageMask; - env->CP0_EntryLo0 =3D tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | - ((uint64_t)tlb->RI0 << CP0EnLo_RI) | - ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3= ) | - get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12); - env->CP0_EntryLo1 =3D tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | - ((uint64_t)tlb->RI1 << CP0EnLo_RI) | - ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3= ) | - get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12); - } -} - -void helper_tlbwi(CPUMIPSState *env) -{ - env->tlb->helper_tlbwi(env); -} - -void helper_tlbwr(CPUMIPSState *env) -{ - env->tlb->helper_tlbwr(env); -} - -void helper_tlbp(CPUMIPSState *env) -{ - env->tlb->helper_tlbp(env); -} - -void helper_tlbr(CPUMIPSState *env) -{ - env->tlb->helper_tlbr(env); -} - -void helper_tlbinv(CPUMIPSState *env) -{ - env->tlb->helper_tlbinv(env); -} - -void helper_tlbinvf(CPUMIPSState *env) -{ - env->tlb->helper_tlbinvf(env); -} - -static void global_invalidate_tlb(CPUMIPSState *env, - uint32_t invMsgVPN2, - uint8_t invMsgR, - uint32_t invMsgMMid, - bool invAll, - bool invVAMMid, - bool invMMid, - bool invVA) -{ - - int idx; - r4k_tlb_t *tlb; - bool VAMatch; - bool MMidMatch; - - for (idx =3D 0; idx < env->tlb->nb_tlb; idx++) { - tlb =3D &env->tlb->mmu.r4k.tlb[idx]; - VAMatch =3D - (((tlb->VPN & ~tlb->PageMask) =3D=3D (invMsgVPN2 & ~tlb->PageM= ask)) -#ifdef TARGET_MIPS64 - && - (extract64(env->CP0_EntryHi, 62, 2) =3D=3D invMsgR) -#endif - ); - MMidMatch =3D tlb->MMID =3D=3D invMsgMMid; - if ((invAll && (idx > env->CP0_Wired)) || - (VAMatch && invVAMMid && (tlb->G || MMidMatch)) || - (VAMatch && invVA) || - (MMidMatch && !(tlb->G) && invMMid)) { - tlb->EHINV =3D 1; - } - } - cpu_mips_tlb_flush(env); -} - -void helper_ginvt(CPUMIPSState *env, target_ulong arg, uint32_t type) -{ - bool invAll =3D type =3D=3D 0; - bool invVA =3D type =3D=3D 1; - bool invMMid =3D type =3D=3D 2; - bool invVAMMid =3D type =3D=3D 3; - uint32_t invMsgVPN2 =3D arg & (TARGET_PAGE_MASK << 1); - uint8_t invMsgR =3D 0; - uint32_t invMsgMMid =3D env->CP0_MemoryMapID; - CPUState *other_cs =3D first_cpu; - -#ifdef TARGET_MIPS64 - invMsgR =3D extract64(arg, 62, 2); -#endif - - CPU_FOREACH(other_cs) { - MIPSCPU *other_cpu =3D MIPS_CPU(other_cs); - global_invalidate_tlb(&other_cpu->env, invMsgVPN2, invMsgR, invMsg= MMid, - invAll, invVAMMid, invMMid, invVA); - } -} - -#endif /* !CONFIG_USER_ONLY */ - static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc) { if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) { diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/t= lb_helper.c index a45146a2b21..259f780d19f 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -24,6 +24,337 @@ #include "exec/cpu_ldst.h" #include "exec/log.h" #include "hw/mips/cpudevs.h" +#include "exec/helper-proto.h" + +/* TLB management */ +static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first) +{ + /* Discard entries from env->tlb[first] onwards. */ + while (env->tlb->tlb_in_use > first) { + r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); + } +} + +static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo) +{ +#if defined(TARGET_MIPS64) + return extract64(entrylo, 6, 54); +#else + return extract64(entrylo, 6, 24) | /* PFN */ + (extract64(entrylo, 32, 32) << 24); /* PFNX */ +#endif +} + +static void r4k_fill_tlb(CPUMIPSState *env, int idx) +{ + r4k_tlb_t *tlb; + uint64_t mask =3D env->CP0_PageMask >> (TARGET_PAGE_BITS + 1); + + /* XXX: detect conflicting TLBs and raise a MCHECK exception when need= ed */ + tlb =3D &env->tlb->mmu.r4k.tlb[idx]; + if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) { + tlb->EHINV =3D 1; + return; + } + tlb->EHINV =3D 0; + tlb->VPN =3D env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); +#if defined(TARGET_MIPS64) + tlb->VPN &=3D env->SEGMask; +#endif + tlb->ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + tlb->MMID =3D env->CP0_MemoryMapID; + tlb->PageMask =3D env->CP0_PageMask; + tlb->G =3D env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; + tlb->V0 =3D (env->CP0_EntryLo0 & 2) !=3D 0; + tlb->D0 =3D (env->CP0_EntryLo0 & 4) !=3D 0; + tlb->C0 =3D (env->CP0_EntryLo0 >> 3) & 0x7; + tlb->XI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1; + tlb->RI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1; + tlb->PFN[0] =3D (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) = << 12; + tlb->V1 =3D (env->CP0_EntryLo1 & 2) !=3D 0; + tlb->D1 =3D (env->CP0_EntryLo1 & 4) !=3D 0; + tlb->C1 =3D (env->CP0_EntryLo1 >> 3) & 0x7; + tlb->XI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1; + tlb->RI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1; + tlb->PFN[1] =3D (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) = << 12; +} + +static void r4k_helper_tlbinv(CPUMIPSState *env) +{ + bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); + uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint32_t MMID =3D env->CP0_MemoryMapID; + uint32_t tlb_mmid; + r4k_tlb_t *tlb; + int idx; + + MMID =3D mi ? MMID : (uint32_t) ASID; + for (idx =3D 0; idx < env->tlb->nb_tlb; idx++) { + tlb =3D &env->tlb->mmu.r4k.tlb[idx]; + tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; + if (!tlb->G && tlb_mmid =3D=3D MMID) { + tlb->EHINV =3D 1; + } + } + cpu_mips_tlb_flush(env); +} + +static void r4k_helper_tlbinvf(CPUMIPSState *env) +{ + int idx; + + for (idx =3D 0; idx < env->tlb->nb_tlb; idx++) { + env->tlb->mmu.r4k.tlb[idx].EHINV =3D 1; + } + cpu_mips_tlb_flush(env); +} + +static void r4k_helper_tlbwi(CPUMIPSState *env) +{ + bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); + target_ulong VPN; + uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint32_t MMID =3D env->CP0_MemoryMapID; + uint32_t tlb_mmid; + bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1; + r4k_tlb_t *tlb; + int idx; + + MMID =3D mi ? MMID : (uint32_t) ASID; + + idx =3D (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; + tlb =3D &env->tlb->mmu.r4k.tlb[idx]; + VPN =3D env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); +#if defined(TARGET_MIPS64) + VPN &=3D env->SEGMask; +#endif + EHINV =3D (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) !=3D 0; + G =3D env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; + V0 =3D (env->CP0_EntryLo0 & 2) !=3D 0; + D0 =3D (env->CP0_EntryLo0 & 4) !=3D 0; + XI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_XI) &1; + RI0 =3D (env->CP0_EntryLo0 >> CP0EnLo_RI) &1; + V1 =3D (env->CP0_EntryLo1 & 2) !=3D 0; + D1 =3D (env->CP0_EntryLo1 & 4) !=3D 0; + XI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_XI) &1; + RI1 =3D (env->CP0_EntryLo1 >> CP0EnLo_RI) &1; + + tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; + /* + * Discard cached TLB entries, unless tlbwi is just upgrading access + * permissions on the current entry. + */ + if (tlb->VPN !=3D VPN || tlb_mmid !=3D MMID || tlb->G !=3D G || + (!tlb->EHINV && EHINV) || + (tlb->V0 && !V0) || (tlb->D0 && !D0) || + (!tlb->XI0 && XI0) || (!tlb->RI0 && RI0) || + (tlb->V1 && !V1) || (tlb->D1 && !D1) || + (!tlb->XI1 && XI1) || (!tlb->RI1 && RI1)) { + r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); + } + + r4k_invalidate_tlb(env, idx, 0); + r4k_fill_tlb(env, idx); +} + +static void r4k_helper_tlbwr(CPUMIPSState *env) +{ + int r =3D cpu_mips_get_random(env); + + r4k_invalidate_tlb(env, r, 1); + r4k_fill_tlb(env, r); +} + +static void r4k_helper_tlbp(CPUMIPSState *env) +{ + bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); + r4k_tlb_t *tlb; + target_ulong mask; + target_ulong tag; + target_ulong VPN; + uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint32_t MMID =3D env->CP0_MemoryMapID; + uint32_t tlb_mmid; + int i; + + MMID =3D mi ? MMID : (uint32_t) ASID; + for (i =3D 0; i < env->tlb->nb_tlb; i++) { + tlb =3D &env->tlb->mmu.r4k.tlb[i]; + /* 1k pages are not supported. */ + mask =3D tlb->PageMask | ~(TARGET_PAGE_MASK << 1); + tag =3D env->CP0_EntryHi & ~mask; + VPN =3D tlb->VPN & ~mask; +#if defined(TARGET_MIPS64) + tag &=3D env->SEGMask; +#endif + tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; + /* Check ASID/MMID, virtual page number & size */ + if ((tlb->G =3D=3D 1 || tlb_mmid =3D=3D MMID) && VPN =3D=3D tag &&= !tlb->EHINV) { + /* TLB match */ + env->CP0_Index =3D i; + break; + } + } + if (i =3D=3D env->tlb->nb_tlb) { + /* No match. Discard any shadow entries, if any of them match. */ + for (i =3D env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) { + tlb =3D &env->tlb->mmu.r4k.tlb[i]; + /* 1k pages are not supported. */ + mask =3D tlb->PageMask | ~(TARGET_PAGE_MASK << 1); + tag =3D env->CP0_EntryHi & ~mask; + VPN =3D tlb->VPN & ~mask; +#if defined(TARGET_MIPS64) + tag &=3D env->SEGMask; +#endif + tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; + /* Check ASID/MMID, virtual page number & size */ + if ((tlb->G =3D=3D 1 || tlb_mmid =3D=3D MMID) && VPN =3D=3D ta= g) { + r4k_mips_tlb_flush_extra(env, i); + break; + } + } + + env->CP0_Index |=3D 0x80000000; + } +} + +static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn) +{ +#if defined(TARGET_MIPS64) + return tlb_pfn << 6; +#else + return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */ + (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */ +#endif +} + +static void r4k_helper_tlbr(CPUMIPSState *env) +{ + bool mi =3D !!((env->CP0_Config5 >> CP0C5_MI) & 1); + uint16_t ASID =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint32_t MMID =3D env->CP0_MemoryMapID; + uint32_t tlb_mmid; + r4k_tlb_t *tlb; + int idx; + + MMID =3D mi ? MMID : (uint32_t) ASID; + idx =3D (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; + tlb =3D &env->tlb->mmu.r4k.tlb[idx]; + + tlb_mmid =3D mi ? tlb->MMID : (uint32_t) tlb->ASID; + /* If this will change the current ASID/MMID, flush qemu's TLB. */ + if (MMID !=3D tlb_mmid) { + cpu_mips_tlb_flush(env); + } + + r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); + + if (tlb->EHINV) { + env->CP0_EntryHi =3D 1 << CP0EnHi_EHINV; + env->CP0_PageMask =3D 0; + env->CP0_EntryLo0 =3D 0; + env->CP0_EntryLo1 =3D 0; + } else { + env->CP0_EntryHi =3D mi ? tlb->VPN : tlb->VPN | tlb->ASID; + env->CP0_MemoryMapID =3D tlb->MMID; + env->CP0_PageMask =3D tlb->PageMask; + env->CP0_EntryLo0 =3D tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | + ((uint64_t)tlb->RI0 << CP0EnLo_RI) | + ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3= ) | + get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12); + env->CP0_EntryLo1 =3D tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | + ((uint64_t)tlb->RI1 << CP0EnLo_RI) | + ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3= ) | + get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12); + } +} + +void helper_tlbwi(CPUMIPSState *env) +{ + env->tlb->helper_tlbwi(env); +} + +void helper_tlbwr(CPUMIPSState *env) +{ + env->tlb->helper_tlbwr(env); +} + +void helper_tlbp(CPUMIPSState *env) +{ + env->tlb->helper_tlbp(env); +} + +void helper_tlbr(CPUMIPSState *env) +{ + env->tlb->helper_tlbr(env); +} + +void helper_tlbinv(CPUMIPSState *env) +{ + env->tlb->helper_tlbinv(env); +} + +void helper_tlbinvf(CPUMIPSState *env) +{ + env->tlb->helper_tlbinvf(env); +} + +static void global_invalidate_tlb(CPUMIPSState *env, + uint32_t invMsgVPN2, + uint8_t invMsgR, + uint32_t invMsgMMid, + bool invAll, + bool invVAMMid, + bool invMMid, + bool invVA) +{ + + int idx; + r4k_tlb_t *tlb; + bool VAMatch; + bool MMidMatch; + + for (idx =3D 0; idx < env->tlb->nb_tlb; idx++) { + tlb =3D &env->tlb->mmu.r4k.tlb[idx]; + VAMatch =3D + (((tlb->VPN & ~tlb->PageMask) =3D=3D (invMsgVPN2 & ~tlb->PageM= ask)) +#ifdef TARGET_MIPS64 + && + (extract64(env->CP0_EntryHi, 62, 2) =3D=3D invMsgR) +#endif + ); + MMidMatch =3D tlb->MMID =3D=3D invMsgMMid; + if ((invAll && (idx > env->CP0_Wired)) || + (VAMatch && invVAMMid && (tlb->G || MMidMatch)) || + (VAMatch && invVA) || + (MMidMatch && !(tlb->G) && invMMid)) { + tlb->EHINV =3D 1; + } + } + cpu_mips_tlb_flush(env); +} + +void helper_ginvt(CPUMIPSState *env, target_ulong arg, uint32_t type) +{ + bool invAll =3D type =3D=3D 0; + bool invVA =3D type =3D=3D 1; + bool invMMid =3D type =3D=3D 2; + bool invVAMMid =3D type =3D=3D 3; + uint32_t invMsgVPN2 =3D arg & (TARGET_PAGE_MASK << 1); + uint8_t invMsgR =3D 0; + uint32_t invMsgMMid =3D env->CP0_MemoryMapID; + CPUState *other_cs =3D first_cpu; + +#ifdef TARGET_MIPS64 + invMsgR =3D extract64(arg, 62, 2); +#endif + + CPU_FOREACH(other_cs) { + MIPSCPU *other_cpu =3D MIPS_CPU(other_cs); + global_invalidate_tlb(&other_cpu->env, invMsgVPN2, invMsgR, invMsg= MMid, + invAll, invVAMMid, invMMid, invVA); + } +} =20 /* no MMU emulation */ static int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *pr= ot, --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) client-ip=209.85.221.45; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f45.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619972310; cv=none; d=zohomail.com; s=zohoarc; b=Cy2W+Yk68S6E+d+NFesql+JK3yCPSz9WYkM1BlnFlnIig9itHeHIkxu/cLD8+JvkQ1zoHAFdLyvcGBR4Mw3mJPa/SCDg0xe748cLMAXWjug+R9dj5J5Dq6iup2HykRxURBjr39HzUeuCAlBzxI5UO094oRzLWe8SJ1pGV9NoAEk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972310; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=R7Bq8USqHmm9lxGhv71RrJ0ZCU2Ifg7e8e/JZpV8dXo=; b=dsG5WYe0EPsxUppuEH1uyikePafSRbqK0RReQ6XTY37pV1iBNb980bErNRi1FgRXRLmquhzdA/zNt092KEwMLMGazjOxJfx6C0vYghlE+9zGixrh/GPnBJYCqdbxqEaehtZetf2PkwduCbwu0IV00zUUCqBMo1RiS9oQLE2spSw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) by mx.zohomail.com with SMTPS id 1619972310202848.5905435061919; Sun, 2 May 2021 09:18:30 -0700 (PDT) Received: by mail-wr1-f45.google.com with SMTP id t18so3112565wry.1 for ; Sun, 02 May 2021 09:18:29 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (anancy-651-1-208-144.w109-217.abo.wanadoo.fr. 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b=jcKQDKZNcHxcZMiRvYRF5ETaKY3AwpLoxKYBdrho28fydnjAfISDtEFveO3PBElXg2 C+StxVO5Zo91E2h2PxB4tdP8L2YyG/qm0TEOd/f3yRSDskuGW377IuHbJACqhWG3dvpn CTrdjgF9lVo1hGQm+tBo3bEd958t9J3ZKLXFWqq1ZW46Ptq1kNaPWWQAqr65RDWOoOYC iaSyEQxn4WbLT7PabbTVYbd+WHostBqVo/BufHn/b4HcR8yxElDKh1kn4pXGAl3xiG/U H8ZOqzVjFmH9qNo3W465FaZ3Bn3I2FJUVmQta8pRtEjnEg70ev0HG0JmoFA1cHe4K32/ mt1A== X-Gm-Message-State: AOAM532vWywLcHHpgJhTSRY9jhBxfQWMIVaaawonw4yuh2+Z3bLotxtl ohUlHcNZp1z/WQNRhpslQNI= X-Google-Smtp-Source: ABdhPJyg5FARYYJYY2R7vdrhLZZBteiXOKa5tf3pVwhXDosIZ0EFLLakcKtLkv+/pGeAmc8ckpJWuQ== X-Received: by 2002:a5d:4c8a:: with SMTP id z10mr20171510wrs.395.1619972308333; Sun, 02 May 2021 09:18:28 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 32/36] target/mips: Move exception management code to exception.c Date: Sun, 2 May 2021 18:15:34 +0200 Message-Id: <20210502161538.534038-33-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-27-f4bug@amsat.org> --- target/mips/internal.h | 13 --- target/mips/tcg/tcg-internal.h | 14 +++ target/mips/cpu.c | 113 ---------------------- target/mips/exception.c | 167 +++++++++++++++++++++++++++++++++ target/mips/op_helper.c | 37 -------- target/mips/meson.build | 1 + 6 files changed, 182 insertions(+), 163 deletions(-) create mode 100644 target/mips/exception.c diff --git a/target/mips/internal.h b/target/mips/internal.h index a1c7f658c2b..07573c3e38f 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -80,7 +80,6 @@ extern const char fregnames[32][4]; extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; =20 -bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, @@ -410,16 +409,4 @@ void sync_c0_status(CPUMIPSState *env, CPUMIPSState *c= pu, int tc); void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); =20 -const char *mips_exception_name(int32_t exception); - -void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exce= ption, - int error_code, uintptr_t pc); - -static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, - uint32_t exception, - uintptr_t pc) -{ - do_raise_exception_err(env, exception, 0, pc); -} - #endif diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 73667b35778..75aa3ef98ed 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -14,11 +14,25 @@ #include "hw/core/cpu.h" #include "cpu.h" =20 +void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb= ); void mips_cpu_do_interrupt(CPUState *cpu); +bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 +const char *mips_exception_name(int32_t exception); + +void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exce= ption, + int error_code, uintptr_t pc); + +static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, + uint32_t exception, + uintptr_t pc) +{ + do_raise_exception_err(env, exception, 0, pc); +} + #if !defined(CONFIG_USER_ONLY) =20 void mmu_init(CPUMIPSState *env, const mips_def_t *def); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index a33e3b6c202..daa9a4791ee 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -218,112 +218,12 @@ static void mips_cpu_dump_state(CPUState *cs, FILE *= f, int flags) } } =20 -static const char * const excp_names[EXCP_LAST + 1] =3D { - [EXCP_RESET] =3D "reset", - [EXCP_SRESET] =3D "soft reset", - [EXCP_DSS] =3D "debug single step", - [EXCP_DINT] =3D "debug interrupt", - [EXCP_NMI] =3D "non-maskable interrupt", - [EXCP_MCHECK] =3D "machine check", - [EXCP_EXT_INTERRUPT] =3D "interrupt", - [EXCP_DFWATCH] =3D "deferred watchpoint", - [EXCP_DIB] =3D "debug instruction breakpoint", - [EXCP_IWATCH] =3D "instruction fetch watchpoint", - [EXCP_AdEL] =3D "address error load", - [EXCP_AdES] =3D "address error store", - [EXCP_TLBF] =3D "TLB refill", - [EXCP_IBE] =3D "instruction bus error", - [EXCP_DBp] =3D "debug breakpoint", - [EXCP_SYSCALL] =3D "syscall", - [EXCP_BREAK] =3D "break", - [EXCP_CpU] =3D "coprocessor unusable", - [EXCP_RI] =3D "reserved instruction", - [EXCP_OVERFLOW] =3D "arithmetic overflow", - [EXCP_TRAP] =3D "trap", - [EXCP_FPE] =3D "floating point", - [EXCP_DDBS] =3D "debug data break store", - [EXCP_DWATCH] =3D "data watchpoint", - [EXCP_LTLBL] =3D "TLB modify", - [EXCP_TLBL] =3D "TLB load", - [EXCP_TLBS] =3D "TLB store", - [EXCP_DBE] =3D "data bus error", - [EXCP_DDBL] =3D "debug data break load", - [EXCP_THREAD] =3D "thread", - [EXCP_MDMX] =3D "MDMX", - [EXCP_C2E] =3D "precise coprocessor 2", - [EXCP_CACHE] =3D "cache error", - [EXCP_TLBXI] =3D "TLB execute-inhibit", - [EXCP_TLBRI] =3D "TLB read-inhibit", - [EXCP_MSADIS] =3D "MSA disabled", - [EXCP_MSAFPE] =3D "MSA floating point", -}; - -const char *mips_exception_name(int32_t exception) -{ - if (exception < 0 || exception > EXCP_LAST) { - return "unknown"; - } - return excp_names[exception]; -} - void cpu_set_exception_base(int vp_index, target_ulong address) { MIPSCPU *vp =3D MIPS_CPU(qemu_get_cpu(vp_index)); vp->env.exception_base =3D address; } =20 -target_ulong exception_resume_pc(CPUMIPSState *env) -{ - target_ulong bad_pc; - target_ulong isa_mode; - - isa_mode =3D !!(env->hflags & MIPS_HFLAG_M16); - bad_pc =3D env->active_tc.PC | isa_mode; - if (env->hflags & MIPS_HFLAG_BMASK) { - /* - * If the exception was raised from a delay slot, come back to - * the jump. - */ - bad_pc -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); - } - - return bad_pc; -} - -bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - if (interrupt_request & CPU_INTERRUPT_HARD) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - - if (cpu_mips_hw_interrupts_enabled(env) && - cpu_mips_hw_interrupts_pending(env)) { - /* Raise it */ - cs->exception_index =3D EXCP_EXT_INTERRUPT; - env->error_code =3D 0; - mips_cpu_do_interrupt(cs); - return true; - } - } - return false; -} - -void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, - uint32_t exception, - int error_code, - uintptr_t pc) -{ - CPUState *cs =3D env_cpu(env); - - qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n", - __func__, exception, mips_exception_name(exception), - error_code); - cs->exception_index =3D exception; - env->error_code =3D error_code; - - cpu_loop_exit_restore(cs, pc); -} - static void mips_cpu_set_pc(CPUState *cs, vaddr value) { MIPSCPU *cpu =3D MIPS_CPU(cs); @@ -331,19 +231,6 @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value) mips_env_set_pc(&cpu->env, value); } =20 -#ifdef CONFIG_TCG -static void mips_cpu_synchronize_from_tb(CPUState *cs, - const TranslationBlock *tb) -{ - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - - env->active_tc.PC =3D tb->pc; - env->hflags &=3D ~MIPS_HFLAG_BMASK; - env->hflags |=3D tb->flags & MIPS_HFLAG_BMASK; -} -#endif /* CONFIG_TCG */ - static bool mips_cpu_has_work(CPUState *cs) { MIPSCPU *cpu =3D MIPS_CPU(cs); diff --git a/target/mips/exception.c b/target/mips/exception.c new file mode 100644 index 00000000000..4fb8b00711d --- /dev/null +++ b/target/mips/exception.c @@ -0,0 +1,167 @@ +/* + * MIPS Exceptions processing helpers for QEMU. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internal.h" +#include "exec/helper-proto.h" +#include "exec/exec-all.h" + +target_ulong exception_resume_pc(CPUMIPSState *env) +{ + target_ulong bad_pc; + target_ulong isa_mode; + + isa_mode =3D !!(env->hflags & MIPS_HFLAG_M16); + bad_pc =3D env->active_tc.PC | isa_mode; + if (env->hflags & MIPS_HFLAG_BMASK) { + /* + * If the exception was raised from a delay slot, come back to + * the jump. + */ + bad_pc -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); + } + + return bad_pc; +} + +void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception, + int error_code) +{ + do_raise_exception_err(env, exception, error_code, 0); +} + +void helper_raise_exception(CPUMIPSState *env, uint32_t exception) +{ + do_raise_exception(env, exception, GETPC()); +} + +void helper_raise_exception_debug(CPUMIPSState *env) +{ + do_raise_exception(env, EXCP_DEBUG, 0); +} + +static void raise_exception(CPUMIPSState *env, uint32_t exception) +{ + do_raise_exception(env, exception, 0); +} + +void helper_wait(CPUMIPSState *env) +{ + CPUState *cs =3D env_cpu(env); + + cs->halted =3D 1; + cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); + /* + * Last instruction in the block, PC was updated before + * - no need to recover PC and icount. + */ + raise_exception(env, EXCP_HLT); +} + +void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) +{ + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + env->active_tc.PC =3D tb->pc; + env->hflags &=3D ~MIPS_HFLAG_BMASK; + env->hflags |=3D tb->flags & MIPS_HFLAG_BMASK; +} + +bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_HARD) { + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + if (cpu_mips_hw_interrupts_enabled(env) && + cpu_mips_hw_interrupts_pending(env)) { + /* Raise it */ + cs->exception_index =3D EXCP_EXT_INTERRUPT; + env->error_code =3D 0; + mips_cpu_do_interrupt(cs); + return true; + } + } + return false; +} + +static const char * const excp_names[EXCP_LAST + 1] =3D { + [EXCP_RESET] =3D "reset", + [EXCP_SRESET] =3D "soft reset", + [EXCP_DSS] =3D "debug single step", + [EXCP_DINT] =3D "debug interrupt", + [EXCP_NMI] =3D "non-maskable interrupt", + [EXCP_MCHECK] =3D "machine check", + [EXCP_EXT_INTERRUPT] =3D "interrupt", + [EXCP_DFWATCH] =3D "deferred watchpoint", + [EXCP_DIB] =3D "debug instruction breakpoint", + [EXCP_IWATCH] =3D "instruction fetch watchpoint", + [EXCP_AdEL] =3D "address error load", + [EXCP_AdES] =3D "address error store", + [EXCP_TLBF] =3D "TLB refill", + [EXCP_IBE] =3D "instruction bus error", + [EXCP_DBp] =3D "debug breakpoint", + [EXCP_SYSCALL] =3D "syscall", + [EXCP_BREAK] =3D "break", + [EXCP_CpU] =3D "coprocessor unusable", + [EXCP_RI] =3D "reserved instruction", + [EXCP_OVERFLOW] =3D "arithmetic overflow", + [EXCP_TRAP] =3D "trap", + [EXCP_FPE] =3D "floating point", + [EXCP_DDBS] =3D "debug data break store", + [EXCP_DWATCH] =3D "data watchpoint", + [EXCP_LTLBL] =3D "TLB modify", + [EXCP_TLBL] =3D "TLB load", + [EXCP_TLBS] =3D "TLB store", + [EXCP_DBE] =3D "data bus error", + [EXCP_DDBL] =3D "debug data break load", + [EXCP_THREAD] =3D "thread", + [EXCP_MDMX] =3D "MDMX", + [EXCP_C2E] =3D "precise coprocessor 2", + [EXCP_CACHE] =3D "cache error", + [EXCP_TLBXI] =3D "TLB execute-inhibit", + [EXCP_TLBRI] =3D "TLB read-inhibit", + [EXCP_MSADIS] =3D "MSA disabled", + [EXCP_MSAFPE] =3D "MSA floating point", +}; + +const char *mips_exception_name(int32_t exception) +{ + if (exception < 0 || exception > EXCP_LAST) { + return "unknown"; + } + return excp_names[exception]; +} + +void do_raise_exception_err(CPUMIPSState *env, uint32_t exception, + int error_code, uintptr_t pc) +{ + CPUState *cs =3D env_cpu(env); + + qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n", + __func__, exception, mips_exception_name(exception), + error_code); + cs->exception_index =3D exception; + env->error_code =3D error_code; + + cpu_loop_exit_restore(cs, pc); +} diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index cb2a7e96fc3..ce1549c9854 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -26,30 +26,6 @@ #include "exec/memop.h" #include "fpu_helper.h" =20 -/*************************************************************************= ****/ -/* Exceptions processing helpers */ - -void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception, - int error_code) -{ - do_raise_exception_err(env, exception, error_code, 0); -} - -void helper_raise_exception(CPUMIPSState *env, uint32_t exception) -{ - do_raise_exception(env, exception, GETPC()); -} - -void helper_raise_exception_debug(CPUMIPSState *env) -{ - do_raise_exception(env, EXCP_DEBUG, 0); -} - -static void raise_exception(CPUMIPSState *env, uint32_t exception) -{ - do_raise_exception(env, exception, 0); -} - /* 64 bits arithmetic for 32 bits hosts */ static inline uint64_t get_HILO(CPUMIPSState *env) { @@ -399,19 +375,6 @@ void helper_pmon(CPUMIPSState *env, int function) } } =20 -void helper_wait(CPUMIPSState *env) -{ - CPUState *cs =3D env_cpu(env); - - cs->halted =3D 1; - cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); - /* - * Last instruction in the block, PC was updated before - * - no need to recover PC and icount. - */ - raise_exception(env, EXCP_HLT); -} - #if !defined(CONFIG_USER_ONLY) =20 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/mips/meson.build b/target/mips/meson.build index ff5eb210dfd..e08077bfc18 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -24,6 +24,7 @@ mips_tcg_ss.add(gen) mips_tcg_ss.add(files( 'dsp_helper.c', + 'exception.c', 'fpu_helper.c', 'ldst_helper.c', 'lmmi_helper.c', --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) client-ip=209.85.128.46; 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[109.217.237.144]) by smtp.gmail.com with ESMTPSA id z14sm10890103wrt.54.2021.05.02.09.18.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:18:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AI6Xo4TmMGfUY040b6yCfWtAncz9V0VwKjuBz7JTA8w=; b=EsX2hEQrlrW2QDHoVe6isjlwUwYip2BOTBm+3dAnhqVUwteH0V2DyVbnjeYkWP8Nqz gumme7RAwSPF0VFpV71w3wJEwQkb9AXU46qyDFmPF3L6D0MEoSSV9FfQJYZ4ZJZ8oDXB HA6/kY5REohFFmd3lWEGtcV/MzaNWzjBz2+IDbefcy09pmraMKr26ahU+Rejr3paFmFZ IfcTVWkpoEPwroQA89xot8ZOMSm/dl4EqTk4GneMqZc5Jt+6Hq+kEp3XE7aYR1+8om55 E8ty8NEyJLOB6Ma/XoGqViuNl+dM+8l/1+Ua9pcTQn9ER+2kfu4Dwyx1v8CHSAMB9IIC WiNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=AI6Xo4TmMGfUY040b6yCfWtAncz9V0VwKjuBz7JTA8w=; b=JuQH7KPBOaD+DR5LV4vnuZ/kMo9DTDd+4D4L+zBXDlxWzbrb8scc/CGg9RLLd9e2Bf EkxHMCb/8i0kP+yAT5Ap0MjUcl1ln/2aVduIQi0YE/WoySp7OO8o4VoUz5J52ngzwdr+ 1mjlFYG5T1yLJrLFUusRCwh+XbTswPFhMeRkDSaz2LKQ8Cxoli0gLDXB9lhzCMyZF9v/ 0doYqQkRUqnoSCRfaSDkZor1oHgHTzTDjLP7icnTBMLTVmNjm0hwHQyA8WjnGTYoWV9k uaM+6+OZHHm59ickZYMoFfgjNhpPwPpLc7y1Gbq1MISyzFXgUS51E7WnfMpTygBH25q3 2stw== X-Gm-Message-State: AOAM531q0lKBqt2jS4fsTaK3piM4FONzqeqppx3Vw8uXD7cqN6qs1hEv z70au4VBxcHodBK5iC7c/0E= X-Google-Smtp-Source: ABdhPJz54iaNygJfV/7IppaLSXTFohHZ6j/i+Jb53Y/TnBIA81yhFn6TreswV1P47QsGrD6Uy/afZQ== X-Received: by 2002:a1c:ed03:: with SMTP id l3mr3302594wmh.130.1619972313524; Sun, 02 May 2021 09:18:33 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 33/36] target/mips: Move CP0 helpers to sysemu/cp0.c Date: Sun, 2 May 2021 18:15:35 +0200 Message-Id: <20210502161538.534038-34-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Opcodes accessing Coprocessor 0 are privileged. Move the CP0 helpers to sysemu/ and simplify the #ifdef'ry. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-28-f4bug@amsat.org> --- target/mips/internal.h | 9 +-- target/mips/cpu.c | 103 --------------------------- target/mips/sysemu/cp0.c | 123 +++++++++++++++++++++++++++++++++ target/mips/sysemu/meson.build | 1 + 4 files changed, 129 insertions(+), 107 deletions(-) create mode 100644 target/mips/sysemu/cp0.c diff --git a/target/mips/internal.h b/target/mips/internal.h index 07573c3e38f..dd332b4dcef 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -156,6 +156,11 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retadd= r); + +void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); +void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); +void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); + extern const VMStateDescription vmstate_mips_cpu; =20 #endif /* !CONFIG_USER_ONLY */ @@ -405,8 +410,4 @@ static inline void compute_hflags(CPUMIPSState *env) } } =20 -void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); -void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); -void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); - #endif diff --git a/target/mips/cpu.c b/target/mips/cpu.c index daa9a4791ee..1ad2fe4aa33 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -42,109 +42,6 @@ const char regnames[32][4] =3D { "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", }; =20 -#if !defined(CONFIG_USER_ONLY) - -/* Called for updates to CP0_Status. */ -void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) -{ - int32_t tcstatus, *tcst; - uint32_t v =3D cpu->CP0_Status; - uint32_t cu, mx, asid, ksu; - uint32_t mask =3D ((1 << CP0TCSt_TCU3) - | (1 << CP0TCSt_TCU2) - | (1 << CP0TCSt_TCU1) - | (1 << CP0TCSt_TCU0) - | (1 << CP0TCSt_TMX) - | (3 << CP0TCSt_TKSU) - | (0xff << CP0TCSt_TASID)); - - cu =3D (v >> CP0St_CU0) & 0xf; - mx =3D (v >> CP0St_MX) & 0x1; - ksu =3D (v >> CP0St_KSU) & 0x3; - asid =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - - tcstatus =3D cu << CP0TCSt_TCU0; - tcstatus |=3D mx << CP0TCSt_TMX; - tcstatus |=3D ksu << CP0TCSt_TKSU; - tcstatus |=3D asid; - - if (tc =3D=3D cpu->current_tc) { - tcst =3D &cpu->active_tc.CP0_TCStatus; - } else { - tcst =3D &cpu->tcs[tc].CP0_TCStatus; - } - - *tcst &=3D ~mask; - *tcst |=3D tcstatus; - compute_hflags(cpu); -} - -void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) -{ - uint32_t mask =3D env->CP0_Status_rw_bitmask; - target_ulong old =3D env->CP0_Status; - - if (env->insn_flags & ISA_MIPS_R6) { - bool has_supervisor =3D extract32(mask, CP0St_KSU, 2) =3D=3D 0x3; -#if defined(TARGET_MIPS64) - uint32_t ksux =3D (1 << CP0St_KX) & val; - ksux |=3D (ksux >> 1) & val; /* KX =3D 0 forces SX to be 0 */ - ksux |=3D (ksux >> 1) & val; /* SX =3D 0 forces UX to be 0 */ - val =3D (val & ~(7 << CP0St_UX)) | ksux; -#endif - if (has_supervisor && extract32(val, CP0St_KSU, 2) =3D=3D 0x3) { - mask &=3D ~(3 << CP0St_KSU); - } - mask &=3D ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); - } - - env->CP0_Status =3D (old & ~mask) | (val & mask); -#if defined(TARGET_MIPS64) - if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { - /* Access to at least one of the 64-bit segments has been disabled= */ - tlb_flush(env_cpu(env)); - } -#endif - if (ase_mt_available(env)) { - sync_c0_status(env, env, env->current_tc); - } else { - compute_hflags(env); - } -} - -void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) -{ - uint32_t mask =3D 0x00C00300; - uint32_t old =3D env->CP0_Cause; - int i; - - if (env->insn_flags & ISA_MIPS_R2) { - mask |=3D 1 << CP0Ca_DC; - } - if (env->insn_flags & ISA_MIPS_R6) { - mask &=3D ~((1 << CP0Ca_WP) & val); - } - - env->CP0_Cause =3D (env->CP0_Cause & ~mask) | (val & mask); - - if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { - if (env->CP0_Cause & (1 << CP0Ca_DC)) { - cpu_mips_stop_count(env); - } else { - cpu_mips_start_count(env); - } - } - - /* Set/reset software interrupts */ - for (i =3D 0 ; i < 2 ; i++) { - if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { - cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i= ))); - } - } -} - -#endif /* !CONFIG_USER_ONLY */ - static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64) { if (is_fpu64) { diff --git a/target/mips/sysemu/cp0.c b/target/mips/sysemu/cp0.c new file mode 100644 index 00000000000..bae37f515bf --- /dev/null +++ b/target/mips/sysemu/cp0.c @@ -0,0 +1,123 @@ +/* + * QEMU MIPS CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internal.h" +#include "exec/exec-all.h" + +/* Called for updates to CP0_Status. */ +void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) +{ + int32_t tcstatus, *tcst; + uint32_t v =3D cpu->CP0_Status; + uint32_t cu, mx, asid, ksu; + uint32_t mask =3D ((1 << CP0TCSt_TCU3) + | (1 << CP0TCSt_TCU2) + | (1 << CP0TCSt_TCU1) + | (1 << CP0TCSt_TCU0) + | (1 << CP0TCSt_TMX) + | (3 << CP0TCSt_TKSU) + | (0xff << CP0TCSt_TASID)); + + cu =3D (v >> CP0St_CU0) & 0xf; + mx =3D (v >> CP0St_MX) & 0x1; + ksu =3D (v >> CP0St_KSU) & 0x3; + asid =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + + tcstatus =3D cu << CP0TCSt_TCU0; + tcstatus |=3D mx << CP0TCSt_TMX; + tcstatus |=3D ksu << CP0TCSt_TKSU; + tcstatus |=3D asid; + + if (tc =3D=3D cpu->current_tc) { + tcst =3D &cpu->active_tc.CP0_TCStatus; + } else { + tcst =3D &cpu->tcs[tc].CP0_TCStatus; + } + + *tcst &=3D ~mask; + *tcst |=3D tcstatus; + compute_hflags(cpu); +} + +void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) +{ + uint32_t mask =3D env->CP0_Status_rw_bitmask; + target_ulong old =3D env->CP0_Status; + + if (env->insn_flags & ISA_MIPS_R6) { + bool has_supervisor =3D extract32(mask, CP0St_KSU, 2) =3D=3D 0x3; +#if defined(TARGET_MIPS64) + uint32_t ksux =3D (1 << CP0St_KX) & val; + ksux |=3D (ksux >> 1) & val; /* KX =3D 0 forces SX to be 0 */ + ksux |=3D (ksux >> 1) & val; /* SX =3D 0 forces UX to be 0 */ + val =3D (val & ~(7 << CP0St_UX)) | ksux; +#endif + if (has_supervisor && extract32(val, CP0St_KSU, 2) =3D=3D 0x3) { + mask &=3D ~(3 << CP0St_KSU); + } + mask &=3D ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); + } + + env->CP0_Status =3D (old & ~mask) | (val & mask); +#if defined(TARGET_MIPS64) + if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { + /* Access to at least one of the 64-bit segments has been disabled= */ + tlb_flush(env_cpu(env)); + } +#endif + if (ase_mt_available(env)) { + sync_c0_status(env, env, env->current_tc); + } else { + compute_hflags(env); + } +} + +void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) +{ + uint32_t mask =3D 0x00C00300; + uint32_t old =3D env->CP0_Cause; + int i; + + if (env->insn_flags & ISA_MIPS_R2) { + mask |=3D 1 << CP0Ca_DC; + } + if (env->insn_flags & ISA_MIPS_R6) { + mask &=3D ~((1 << CP0Ca_WP) & val); + } + + env->CP0_Cause =3D (env->CP0_Cause & ~mask) | (val & mask); + + if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { + if (env->CP0_Cause & (1 << CP0Ca_DC)) { + cpu_mips_stop_count(env); + } else { + cpu_mips_start_count(env); + } + } + + /* Set/reset software interrupts */ + for (i =3D 0 ; i < 2 ; i++) { + if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { + cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i= ))); + } + } +} diff --git a/target/mips/sysemu/meson.build b/target/mips/sysemu/meson.build index 925ceeaa449..cefc2275828 100644 --- a/target/mips/sysemu/meson.build +++ b/target/mips/sysemu/meson.build @@ -1,5 +1,6 @@ mips_softmmu_ss.add(files( 'addr.c', + 'cp0.c', 'cp0_timer.c', 'machine.c', 'physaddr.c', --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) client-ip=209.85.128.54; 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[109.217.237.144]) by smtp.gmail.com with ESMTPSA id d22sm9695219wrc.50.2021.05.02.09.18.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:18:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pnjyKRQ7/9n91PbEJLZsMKQQzRD0g231SYcwKPC7JUI=; b=Gk4b2xWGMepk3oz75HT1fqnXIV74P8y8+21CRO/aBl2sCZDbASo1Wqzf6DkqPF9+0/ T/bdzXOs799NpGTw3kQE4cpthkYYLkMXFoAzRIRrYUyESZ4lCcORM2ARJPlON8eww70o MRx5nXhsJGCEWUPOKioJNQA/RyqnElsVPTkABEt8ALwGJkFxLX08Ud+BaRyxre6O5OgD 3ybfAY1pWLKfSTdG9MvSdSX2W45WUqWm1VWwaW7gkY8ql4Y/VlvO5no8SQkNPkZAHpWl V/a+PfrAQ/423/W7gloXNa1a1XLb5rpuZ18vHQ8dGt3VW6dxuQxOqSpdRrgAGMJvgk+1 OYsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=pnjyKRQ7/9n91PbEJLZsMKQQzRD0g231SYcwKPC7JUI=; b=N5bA5YbnvpoTZitLKe2X0WGv/DWYkwPvOvfFJbhqRb7Dh4O55ISgIhQRGqGECnn67r bqAbbmj1ecf2jUFJv7HZgFuh9JDGhShYX/NXI9mc+uKv/OKzlFAPCn7gMX8JnvJW9hrv ARetpBHfjJssizXhJ65DSzbl96groHm37b6vbcaNq4B5VlCxEXja4U0d5WYxWaRO0j1o vbPsroMLbZXIzkiXro0mnHgN6Jclzv6dQwGU9KLwawSMJGdsmI9RrTyNbJRrowJ2kJdi ZsdEntt9u5/XvYJ4NnnkfSpBBwhqc7Z8xvWs8u2A+KGfv1s2Bk+0svNdgg85czMyEkH+ 4ikA== X-Gm-Message-State: AOAM530Xqd8CKP5TEP/B3aqKHyP641qU8rO0WBsmk3UUTzqMTBclAYc/ Vzt7YF3QHuPm4akOFk/tt9E= X-Google-Smtp-Source: ABdhPJyAwDQphK5OLBprY0/4PN2T1TR/5c3Sx4G+3hKLBKMcXOnfH6E83MFU3WivB3JA7l2UxNTSJw== X-Received: by 2002:a05:600c:3581:: with SMTP id p1mr17164741wmq.76.1619972318722; Sun, 02 May 2021 09:18:38 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 34/36] target/mips: Move TCG source files under tcg/ sub directory Date: Sun, 2 May 2021 18:15:36 +0200 Message-Id: <20210502161538.534038-35-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) To ease maintenance, move all TCG specific files under the tcg/ sub-directory. Adapt the Meson machinery. The following prototypes: - mips_tcg_init() - mips_cpu_do_unaligned_access() - mips_cpu_do_transaction_failed() can now be restricted to the "tcg-internal.h" header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-29-f4bug@amsat.org> --- target/mips/helper.h | 2 +- target/mips/internal.h | 11 ------- target/mips/tcg/tcg-internal.h | 11 +++++++ target/mips/{ =3D> tcg}/msa_helper.h.inc | 0 target/mips/{ =3D> tcg}/mips32r6.decode | 0 target/mips/{ =3D> tcg}/mips64r6.decode | 0 target/mips/{ =3D> tcg}/msa32.decode | 0 target/mips/{ =3D> tcg}/msa64.decode | 0 target/mips/{ =3D> tcg}/tx79.decode | 0 target/mips/{ =3D> tcg}/dsp_helper.c | 0 target/mips/{ =3D> tcg}/exception.c | 0 target/mips/{ =3D> tcg}/fpu_helper.c | 0 target/mips/{ =3D> tcg}/ldst_helper.c | 0 target/mips/{ =3D> tcg}/lmmi_helper.c | 0 target/mips/{ =3D> tcg}/msa_helper.c | 0 target/mips/{ =3D> tcg}/msa_translate.c | 0 target/mips/{ =3D> tcg}/mxu_translate.c | 0 target/mips/{ =3D> tcg}/op_helper.c | 0 target/mips/{ =3D> tcg}/rel6_translate.c | 0 target/mips/{ =3D> tcg}/translate.c | 0 target/mips/{ =3D> tcg}/translate_addr_const.c | 0 target/mips/{ =3D> tcg}/tx79_translate.c | 0 target/mips/{ =3D> tcg}/txx9_translate.c | 0 target/mips/meson.build | 31 -------------------- target/mips/tcg/meson.build | 29 ++++++++++++++++++ 25 files changed, 41 insertions(+), 43 deletions(-) rename target/mips/{ =3D> tcg}/msa_helper.h.inc (100%) rename target/mips/{ =3D> tcg}/mips32r6.decode (100%) rename target/mips/{ =3D> tcg}/mips64r6.decode (100%) rename target/mips/{ =3D> tcg}/msa32.decode (100%) rename target/mips/{ =3D> tcg}/msa64.decode (100%) rename target/mips/{ =3D> tcg}/tx79.decode (100%) rename target/mips/{ =3D> tcg}/dsp_helper.c (100%) rename target/mips/{ =3D> tcg}/exception.c (100%) rename target/mips/{ =3D> tcg}/fpu_helper.c (100%) rename target/mips/{ =3D> tcg}/ldst_helper.c (100%) rename target/mips/{ =3D> tcg}/lmmi_helper.c (100%) rename target/mips/{ =3D> tcg}/msa_helper.c (100%) rename target/mips/{ =3D> tcg}/msa_translate.c (100%) rename target/mips/{ =3D> tcg}/mxu_translate.c (100%) rename target/mips/{ =3D> tcg}/op_helper.c (100%) rename target/mips/{ =3D> tcg}/rel6_translate.c (100%) rename target/mips/{ =3D> tcg}/translate.c (100%) rename target/mips/{ =3D> tcg}/translate_addr_const.c (100%) rename target/mips/{ =3D> tcg}/tx79_translate.c (100%) rename target/mips/{ =3D> tcg}/txx9_translate.c (100%) diff --git a/target/mips/helper.h b/target/mips/helper.h index ba301ae160d..a9c6c7d1a31 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -608,4 +608,4 @@ DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) #include "tcg/sysemu_helper.h.inc" #endif /* !CONFIG_USER_ONLY */ =20 -#include "msa_helper.h.inc" +#include "tcg/msa_helper.h.inc" diff --git a/target/mips/internal.h b/target/mips/internal.h index dd332b4dcef..18d5da64a57 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -82,9 +82,6 @@ extern const int mips_defs_number; =20 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); =20 #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL) #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL) @@ -151,12 +148,6 @@ struct CPUMIPSTLBContext { } mmu; }; =20 -void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, - vaddr addr, unsigned size, - MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, uintptr_t retadd= r); - void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); @@ -209,8 +200,6 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMI= PSState *env) return r; } =20 -void mips_tcg_init(void); - void msa_reset(CPUMIPSState *env); =20 /* cp0_timer.c */ diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 75aa3ef98ed..81b14eb219e 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -11,15 +11,21 @@ #define MIPS_TCG_INTERNAL_H =20 #include "tcg/tcg.h" +#include "exec/memattrs.h" #include "hw/core/cpu.h" #include "cpu.h" =20 +void mips_tcg_init(void); + void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb= ); void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); =20 const char *mips_exception_name(int32_t exception); =20 @@ -46,6 +52,11 @@ bool mips_io_recompile_replay_branch(CPUState *cs, const= TranslationBlock *tb); =20 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, MMUAccessType access_type, uintptr_t ret= addr); +void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retadd= r); void cpu_mips_tlb_flush(CPUMIPSState *env); =20 #endif /* !CONFIG_USER_ONLY */ diff --git a/target/mips/msa_helper.h.inc b/target/mips/tcg/msa_helper.h.inc similarity index 100% rename from target/mips/msa_helper.h.inc rename to target/mips/tcg/msa_helper.h.inc diff --git a/target/mips/mips32r6.decode b/target/mips/tcg/mips32r6.decode similarity index 100% rename from target/mips/mips32r6.decode rename to target/mips/tcg/mips32r6.decode diff --git a/target/mips/mips64r6.decode b/target/mips/tcg/mips64r6.decode similarity index 100% rename from target/mips/mips64r6.decode rename to target/mips/tcg/mips64r6.decode diff --git a/target/mips/msa32.decode b/target/mips/tcg/msa32.decode similarity index 100% rename from target/mips/msa32.decode rename to target/mips/tcg/msa32.decode diff --git a/target/mips/msa64.decode b/target/mips/tcg/msa64.decode similarity index 100% rename from target/mips/msa64.decode rename to target/mips/tcg/msa64.decode diff --git a/target/mips/tx79.decode b/target/mips/tcg/tx79.decode similarity index 100% rename from target/mips/tx79.decode rename to target/mips/tcg/tx79.decode diff --git a/target/mips/dsp_helper.c b/target/mips/tcg/dsp_helper.c similarity index 100% rename from target/mips/dsp_helper.c rename to target/mips/tcg/dsp_helper.c diff --git a/target/mips/exception.c b/target/mips/tcg/exception.c similarity index 100% rename from target/mips/exception.c rename to target/mips/tcg/exception.c diff --git a/target/mips/fpu_helper.c b/target/mips/tcg/fpu_helper.c similarity index 100% rename from target/mips/fpu_helper.c rename to target/mips/tcg/fpu_helper.c diff --git a/target/mips/ldst_helper.c b/target/mips/tcg/ldst_helper.c similarity index 100% rename from target/mips/ldst_helper.c rename to target/mips/tcg/ldst_helper.c diff --git a/target/mips/lmmi_helper.c b/target/mips/tcg/lmmi_helper.c similarity index 100% rename from target/mips/lmmi_helper.c rename to target/mips/tcg/lmmi_helper.c diff --git a/target/mips/msa_helper.c b/target/mips/tcg/msa_helper.c similarity index 100% rename from target/mips/msa_helper.c rename to target/mips/tcg/msa_helper.c diff --git a/target/mips/msa_translate.c b/target/mips/tcg/msa_translate.c similarity index 100% rename from target/mips/msa_translate.c rename to target/mips/tcg/msa_translate.c diff --git a/target/mips/mxu_translate.c b/target/mips/tcg/mxu_translate.c similarity index 100% rename from target/mips/mxu_translate.c rename to target/mips/tcg/mxu_translate.c diff --git a/target/mips/op_helper.c b/target/mips/tcg/op_helper.c similarity index 100% rename from target/mips/op_helper.c rename to target/mips/tcg/op_helper.c diff --git a/target/mips/rel6_translate.c b/target/mips/tcg/rel6_translate.c similarity index 100% rename from target/mips/rel6_translate.c rename to target/mips/tcg/rel6_translate.c diff --git a/target/mips/translate.c b/target/mips/tcg/translate.c similarity index 100% rename from target/mips/translate.c rename to target/mips/tcg/translate.c diff --git a/target/mips/translate_addr_const.c b/target/mips/tcg/translate= _addr_const.c similarity index 100% rename from target/mips/translate_addr_const.c rename to target/mips/tcg/translate_addr_const.c diff --git a/target/mips/tx79_translate.c b/target/mips/tcg/tx79_translate.c similarity index 100% rename from target/mips/tx79_translate.c rename to target/mips/tcg/tx79_translate.c diff --git a/target/mips/txx9_translate.c b/target/mips/tcg/txx9_translate.c similarity index 100% rename from target/mips/txx9_translate.c rename to target/mips/tcg/txx9_translate.c diff --git a/target/mips/meson.build b/target/mips/meson.build index e08077bfc18..2407a05d4c0 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -1,11 +1,3 @@ -gen =3D [ - decodetree.process('mips32r6.decode', extra_args: '--static-decode=3Ddec= ode_mips32r6'), - decodetree.process('mips64r6.decode', extra_args: '--static-decode=3Ddec= ode_mips64r6'), - decodetree.process('msa32.decode', extra_args: '--static-decode=3Ddecode= _msa32'), - decodetree.process('msa64.decode', extra_args: '--static-decode=3Ddecode= _msa64'), - decodetree.process('tx79.decode', extra_args: '--static-decode=3Ddecode_= tx79'), -] - mips_user_ss =3D ss.source_set() mips_softmmu_ss =3D ss.source_set() mips_ss =3D ss.source_set() @@ -20,35 +12,12 @@ subdir('sysemu') endif =20 -mips_tcg_ss =3D ss.source_set() -mips_tcg_ss.add(gen) -mips_tcg_ss.add(files( - 'dsp_helper.c', - 'exception.c', - 'fpu_helper.c', - 'ldst_helper.c', - 'lmmi_helper.c', - 'msa_helper.c', - 'msa_translate.c', - 'op_helper.c', - 'rel6_translate.c', - 'translate.c', - 'translate_addr_const.c', - 'txx9_translate.c', -)) -mips_tcg_ss.add(when: 'TARGET_MIPS64', if_true: files( - 'tx79_translate.c', -), if_false: files( - 'mxu_translate.c', -)) if 'CONFIG_TCG' in config_all subdir('tcg') endif =20 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 -mips_ss.add_all(when: 'CONFIG_TCG', if_true: [mips_tcg_ss]) - target_arch +=3D {'mips': mips_ss} target_softmmu_arch +=3D {'mips': mips_softmmu_ss} target_user_arch +=3D {'mips': mips_user_ss} diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 2cffc5a5ac6..5d8acbaf0d3 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -1,3 +1,32 @@ +gen =3D [ + decodetree.process('mips32r6.decode', extra_args: '--static-decode=3Ddec= ode_mips32r6'), + decodetree.process('mips64r6.decode', extra_args: '--static-decode=3Ddec= ode_mips64r6'), + decodetree.process('msa32.decode', extra_args: '--static-decode=3Ddecode= _msa32'), + decodetree.process('msa64.decode', extra_args: '--static-decode=3Ddecode= _msa64'), + decodetree.process('tx79.decode', extra_args: '--static-decode=3Ddecode_= tx79'), +] + +mips_ss.add(gen) +mips_ss.add(files( + 'dsp_helper.c', + 'exception.c', + 'fpu_helper.c', + 'ldst_helper.c', + 'lmmi_helper.c', + 'msa_helper.c', + 'msa_translate.c', + 'op_helper.c', + 'rel6_translate.c', + 'translate.c', + 'translate_addr_const.c', + 'txx9_translate.c', +)) +mips_ss.add(when: 'TARGET_MIPS64', if_true: files( + 'tx79_translate.c', +), if_false: files( + 'mxu_translate.c', +)) + if have_user subdir('user') endif --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) client-ip=209.85.128.47; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f47.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as 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[109.217.237.144]) by smtp.gmail.com with ESMTPSA id e10sm9391752wrw.20.2021.05.02.09.18.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:18:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=y5rUAff0XwGga948kJnZP8LhVBDdCm+qDgTkGYYKq9k=; b=VxfEiX/VdyWIyItBTwT0TvGXJ7iBuBjf3nTN+BB1mvg2upyGYRpquAQPviEBVZGrzZ Q9AS1Zc0nnp/+Xu1x6sEVw5BQzn4rORuLmHcR7fRKxY71qeDO7XG/72qbL7lGAzU7P/X tJt2d6Fr+BOtpZ55jCiMhDZ3STaMz+x/0weFb3xmfkIAtgh7h4TyrHY4YEt35T9dXDoX vR0Pz5AdzrHTAht/1LHhlXQ1x/zoYmOYPtpGaNua6V5aTXp/LDfbCWq3sHdBq9Kyeqjj aFURrqNW1uInpTsrws6mOh8fOfhSZLHeEY46rOj5g/1bpjwgnS2pRZ3jcDyKMu3MiWFT snDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=y5rUAff0XwGga948kJnZP8LhVBDdCm+qDgTkGYYKq9k=; b=E4HSfrgbdcyFB5FVtSnXWvlHeut43Ll2jPzlBnpLjWHChtD/k2recdnMU6Vqr785kk z/G4676qZAXMEZX3+9xP25nP59L//HVw++qCQLXzMqToCge1O/Jr/cuwp8sioBH7iZKn mLrYxQuTBl0R4k3pJkskIBUO4NVnEOqRZsGg8AGOiWoFUc64XXMjQYLt0IFKs6Iba2Xi uuk4wwR6Se0AUfTquYcsTds/otpMJjBecNwh8qkWaOzGkAT803WhMQI4WKynA/45vaAI VtyRpSmxk3gOlcIFyJfYKZKZ4bE3HyijtB6k87GasFaLw//GRl0k5crauCz9gs3yKcUn XNeg== X-Gm-Message-State: AOAM533cQ5M1m8UumCRWtZdjIRiJJvD/l8h5c4tPjIZTZCr+ikSjCsUM 9zrptuXt2MoIEDhwMUaEvwY= X-Google-Smtp-Source: ABdhPJzHr+8TGy+/iFNctq6REYAIx3fBXLJWhNfOVcDMuptZYEAm4zEN+hd3mrKHaAmeZ0V4+06DOQ== X-Received: by 2002:a7b:c8ca:: with SMTP id f10mr17381427wml.118.1619972323998; Sun, 02 May 2021 09:18:43 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 35/36] hw/mips: Restrict non-virtualized machines to TCG Date: Sun, 2 May 2021 18:15:37 +0200 Message-Id: <20210502161538.534038-36-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Only the malta and loongson3-virt machines support KVM. Restrict the other machines to TCG: - mipssim - magnum - pica61 - fuloong2e - boston Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-30-f4bug@amsat.org> --- hw/mips/meson.build | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/hw/mips/meson.build b/hw/mips/meson.build index 1195716dc73..dd0101ad4d8 100644 --- a/hw/mips/meson.build +++ b/hw/mips/meson.build @@ -1,12 +1,15 @@ mips_ss =3D ss.source_set() mips_ss.add(files('bootloader.c', 'mips_int.c')) mips_ss.add(when: 'CONFIG_FW_CFG_MIPS', if_true: files('fw_cfg.c')) -mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c')) mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c',= 'loongson3_virt.c')) -mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c')) mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c= ')) -mips_ss.add(when: 'CONFIG_MIPSSIM', if_true: files('mipssim.c')) -mips_ss.add(when: 'CONFIG_MIPS_BOSTON', if_true: [files('boston.c'), fdt]) mips_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('cps.c')) =20 +if 'CONFIG_TCG' in config_all +mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c')) +mips_ss.add(when: 'CONFIG_MIPSSIM', if_true: files('mipssim.c')) +mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c')) +mips_ss.add(when: 'CONFIG_MIPS_BOSTON', if_true: [files('boston.c'), fdt]) +endif + hw_arch +=3D {'mips': mips_ss} --=20 2.26.3 From nobody Mon Feb 9 19:59:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) client-ip=209.85.221.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1619972330; cv=none; d=zohomail.com; s=zohoarc; b=CxxUYJtDyo6Mmi+QXOLOgPLeWXGMBBJU8O/fRYt0Krgo8mxVvsnPFKKdpM5TyJhShIhVdwLIGZ9gNSelDNKODu6MS1U4QcEYbA1SKiN25rJzhv7DUyxYh5aJ2RjoqnqtHP7wPiV9V96b2RQItCm/sAzbXXlssYLrWGCQZdCskrI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619972330; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SviDw4K5XBOoGF63LViAqHxpPlYyDc4wVbmHH+f6eTQ=; b=B4qMl70fXm27qboij2qpN/01Qn12mD8sSaWbJ8zEQigsCwvye7hsR/32EuuR3R2wVsFU4dPX0gLmjMh7I4EMWcxcxieu8fsnIQeZ0ryXHiNvUzcEOK84y28aKFveVy3FY3eEpsWf8obU05hJqmKdSwHuOLZQPn5gDTvl+CvvOiU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) by mx.zohomail.com with SMTPS id 1619972330864476.5243807752553; Sun, 2 May 2021 09:18:50 -0700 (PDT) Received: by mail-wr1-f42.google.com with SMTP id n2so3133773wrm.0 for ; Sun, 02 May 2021 09:18:50 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (anancy-651-1-208-144.w109-217.abo.wanadoo.fr. [109.217.237.144]) by smtp.gmail.com with ESMTPSA id m11sm1916641wmq.33.2021.05.02.09.18.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 May 2021 09:18:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SviDw4K5XBOoGF63LViAqHxpPlYyDc4wVbmHH+f6eTQ=; b=iwUxN9p4qyIE3m0xWc2ZfMOQKZfXWbwyE0I/GbesUi1u0wckzXdYyvJl0By+V8uMRi dqDTICAxb6dFLXX5j6Y4xg98thPrig844LtMQCshJROZbM2Z5iyoVuPx4ltOyd2Pi6oJ dZ+4fcJybNAbTEUu1zOZjA9qMt+n/F6BPTXOjQxxjGWigOz5j7BU8nbLSY58S6oc8iet rhNrOEuHe2MRnEE5WsGu0EIog6KYVE78/pUOTzIEpWi24cn1xbTCD1k/VYYog4h7WFku KANR4BkxHWnIH0y+hY/+ciU5mlRonJi/qPnhGcJNFCiAHOFKoVMqxlno68+/VveAE2Je xUoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=SviDw4K5XBOoGF63LViAqHxpPlYyDc4wVbmHH+f6eTQ=; b=XfaQpX+knWB2vk99Jo35yt4vxcFvtYwpMGy34ts4NXNR3eGEA56mQorX9FaNVAoSY7 DshjDovG+HSkWxYussOWKgFn5gRA9QbLWYvLj8JHFSW02U1+OCvQBDJYPOP6xlk23Z0F swluHgBNCBWvFTvJ01A9Dhjzb7rU+Qm3IqBviOyry0cZ5rkydI5KDE7TYpdD4pNrD7Yg CzcZF9ozRZzJou4Ka8+1Xy4xJ2//H0ciCOTQHxBMByf3g54sN/w/Fkpci40z4wegGi4g eaNDTRFjVLwsXYEPEilc5FXlhDMqqv6LjHV7aZkJ0U3Mflc38A6EkC/T6eymWsxF7HOp mChA== X-Gm-Message-State: AOAM531JD4YzYUqpZd31gaMVk7JrLtMA2xCR0GgHTvaPmpXwRjF+aRqg 7HRTcQSDNFpv0MZHomDSbGU= X-Google-Smtp-Source: ABdhPJyHLVlnVubonhG5IGpU7e50aQREXdihDEIdGsEJDhBvN/Rb6pTEK7TujcKufJ84iuVBzDofFg== X-Received: by 2002:a5d:4810:: with SMTP id l16mr883533wrq.44.1619972329102; Sun, 02 May 2021 09:18:49 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Thomas Huth , Willian Rampazzo , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Wainer dos Santos Moschetta Subject: [PULL 36/36] gitlab-ci: Add KVM mips64el cross-build jobs Date: Sun, 2 May 2021 18:15:38 +0200 Message-Id: <20210502161538.534038-37-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org> References: <20210502161538.534038-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Add a new job to cross-build the mips64el target without the TCG accelerator (IOW: only KVM accelerator enabled). Only build the mips64el target which is known to work and has users. Reviewed-by: Richard Henderson Acked-by: Thomas Huth Reviewed-by: Willian Rampazzo Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210428170410.479308-31-f4bug@amsat.org> --- .gitlab-ci.d/crossbuilds.yml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml index 2d95784ed51..e44e4b49a25 100644 --- a/.gitlab-ci.d/crossbuilds.yml +++ b/.gitlab-ci.d/crossbuilds.yml @@ -176,6 +176,14 @@ cross-s390x-kvm-only: IMAGE: debian-s390x-cross ACCEL_CONFIGURE_OPTS: --disable-tcg =20 +cross-mips64el-kvm-only: + extends: .cross_accel_build_job + needs: + job: mips64el-debian-cross-container + variables: + IMAGE: debian-mips64el-cross + ACCEL_CONFIGURE_OPTS: --disable-tcg --target-list=3Dmips64el-softmmu + cross-win32-system: extends: .cross_system_build_job needs: --=20 2.26.3