From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32-64.decode | 4 +++
target/riscv/insn32.decode | 7 +++-
target/riscv/insn_trans/trans_rvb.c.inc | 47 +++++++++++++++++++++++++
target/riscv/translate.c | 42 ++++++++++++++++++++++
4 files changed, 99 insertions(+), 1 deletion(-)
create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 8157dee8b7c..f4c42720fc7 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -86,3 +86,7 @@ fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
+
+# *** RV64B Standard Extension (in addition to RV32B) ***
+clzw 0110000 00000 ..... 001 ..... 0011011 @r2
+ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 3823b3ea800..8fe838cf0d0 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -40,6 +40,7 @@
&i imm rs1 rd
&j imm rd
&r rd rs1 rs2
+&r2 rd rs1
&s imm rs1 rs2
&u imm rd
&shift shamt rs1 rd
@@ -67,7 +68,7 @@
@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
-@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
+@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
@r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
@r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd
@@ -592,3 +593,7 @@ vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
+
+# *** RV32B Standard Extension ***
+clz 011000 000000 ..... 001 ..... 0010011 @r2
+ctz 011000 000001 ..... 001 ..... 0010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
new file mode 100644
index 00000000000..76788c2f353
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -0,0 +1,47 @@
+/*
+ * RISC-V translation routines for the RVB Standard Extension.
+ *
+ * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
+ * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_clz(DisasContext *ctx, arg_clz *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, gen_clz);
+}
+
+static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, gen_ctz);
+}
+
+/* RV64-only instructions */
+#ifdef TARGET_RISCV64
+
+static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, gen_clzw);
+}
+
+static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, gen_ctzw);
+}
+
+#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 2f9f5ccc621..4648c422f42 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -536,6 +536,23 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
#endif
+#ifdef TARGET_RISCV64
+
+static void gen_ctzw(TCGv ret, TCGv arg1)
+{
+ tcg_gen_ori_i64(ret, arg1, MAKE_64BIT_MASK(32, 32));
+ tcg_gen_ctzi_i64(ret, ret, 64);
+}
+
+static void gen_clzw(TCGv ret, TCGv arg1)
+{
+ tcg_gen_ext32u_i64(ret, arg1);
+ tcg_gen_clzi_i64(ret, ret, 64);
+ tcg_gen_subi_i64(ret, ret, 32);
+}
+
+#endif
+
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
@@ -581,6 +598,30 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
return cpu_ldl_code(env, pc);
}
+static void gen_ctz(TCGv ret, TCGv arg1)
+{
+ tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
+}
+
+static void gen_clz(TCGv ret, TCGv arg1)
+{
+ tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
+}
+
+static bool gen_unary(DisasContext *ctx, arg_r2 *a,
+ void(*func)(TCGv, TCGv))
+{
+ TCGv source = tcg_temp_new();
+
+ gen_get_gpr(source, a->rs1);
+
+ (*func)(source, source);
+
+ gen_set_gpr(a->rd, source);
+ tcg_temp_free(source);
+ return true;
+}
+
/* Include insn module translation function */
#include "insn_trans/trans_rvi.c.inc"
#include "insn_trans/trans_rvm.c.inc"
@@ -589,6 +630,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
#include "insn_trans/trans_rvd.c.inc"
#include "insn_trans/trans_rvh.c.inc"
#include "insn_trans/trans_rvv.c.inc"
+#include "insn_trans/trans_rvb.c.inc"
#include "insn_trans/trans_privileged.c.inc"
/* Include the auto-generated decoder for 16 bit insn */
--
2.17.1
On Wed, Apr 21, 2021 at 2:14 PM <frank.chang@sifive.com> wrote:
>
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/riscv/insn32-64.decode | 4 +++
> target/riscv/insn32.decode | 7 +++-
> target/riscv/insn_trans/trans_rvb.c.inc | 47 +++++++++++++++++++++++++
> target/riscv/translate.c | 42 ++++++++++++++++++++++
> 4 files changed, 99 insertions(+), 1 deletion(-)
> create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
>
> diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
> index 8157dee8b7c..f4c42720fc7 100644
> --- a/target/riscv/insn32-64.decode
> +++ b/target/riscv/insn32-64.decode
> @@ -86,3 +86,7 @@ fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
> hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
> hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
> hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
> +
> +# *** RV64B Standard Extension (in addition to RV32B) ***
> +clzw 0110000 00000 ..... 001 ..... 0011011 @r2
> +ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 3823b3ea800..8fe838cf0d0 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -40,6 +40,7 @@
> &i imm rs1 rd
> &j imm rd
> &r rd rs1 rs2
> +&r2 rd rs1
> &s imm rs1 rs2
> &u imm rd
> &shift shamt rs1 rd
> @@ -67,7 +68,7 @@
> @r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
> @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
> @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
> -@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
> +@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
> @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
> @r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
> @r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd
> @@ -592,3 +593,7 @@ vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
>
> vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
> vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
> +
> +# *** RV32B Standard Extension ***
> +clz 011000 000000 ..... 001 ..... 0010011 @r2
> +ctz 011000 000001 ..... 001 ..... 0010011 @r2
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
> new file mode 100644
> index 00000000000..76788c2f353
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -0,0 +1,47 @@
> +/*
> + * RISC-V translation routines for the RVB Standard Extension.
> + *
> + * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
> + * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +static bool trans_clz(DisasContext *ctx, arg_clz *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_unary(ctx, a, gen_clz);
> +}
> +
> +static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_unary(ctx, a, gen_ctz);
> +}
> +
> +/* RV64-only instructions */
> +#ifdef TARGET_RISCV64
> +
> +static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_unary(ctx, a, gen_clzw);
> +}
> +
> +static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_unary(ctx, a, gen_ctzw);
> +}
> +
> +#endif
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 2f9f5ccc621..4648c422f42 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -536,6 +536,23 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
>
> #endif
>
> +#ifdef TARGET_RISCV64
Thanks for the patches!
Unfortunately this will need to be rebased and updated. We don't want
any more #ifdef's on the RISC-V xlen. The idea is to make the XLEN not
just a compile time constant.
The latest riscv-to-apply.next tree has changes to allow you to do
this. See this commit for what this will look like:
https://github.com/alistair23/qemu/commit/4965ae3f6f3838e651d1a33050b15b4ca3d822a0
The changes should be in master after the 6.0 release.
Alistair
> +
> +static void gen_ctzw(TCGv ret, TCGv arg1)
> +{
> + tcg_gen_ori_i64(ret, arg1, MAKE_64BIT_MASK(32, 32));
> + tcg_gen_ctzi_i64(ret, ret, 64);
> +}
> +
> +static void gen_clzw(TCGv ret, TCGv arg1)
> +{
> + tcg_gen_ext32u_i64(ret, arg1);
> + tcg_gen_clzi_i64(ret, ret, 64);
> + tcg_gen_subi_i64(ret, ret, 32);
> +}
> +
> +#endif
> +
> static bool gen_arith(DisasContext *ctx, arg_r *a,
> void(*func)(TCGv, TCGv, TCGv))
> {
> @@ -581,6 +598,30 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
> return cpu_ldl_code(env, pc);
> }
>
> +static void gen_ctz(TCGv ret, TCGv arg1)
> +{
> + tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
> +}
> +
> +static void gen_clz(TCGv ret, TCGv arg1)
> +{
> + tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
> +}
> +
> +static bool gen_unary(DisasContext *ctx, arg_r2 *a,
> + void(*func)(TCGv, TCGv))
> +{
> + TCGv source = tcg_temp_new();
> +
> + gen_get_gpr(source, a->rs1);
> +
> + (*func)(source, source);
> +
> + gen_set_gpr(a->rd, source);
> + tcg_temp_free(source);
> + return true;
> +}
> +
> /* Include insn module translation function */
> #include "insn_trans/trans_rvi.c.inc"
> #include "insn_trans/trans_rvm.c.inc"
> @@ -589,6 +630,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
> #include "insn_trans/trans_rvd.c.inc"
> #include "insn_trans/trans_rvh.c.inc"
> #include "insn_trans/trans_rvv.c.inc"
> +#include "insn_trans/trans_rvb.c.inc"
> #include "insn_trans/trans_privileged.c.inc"
>
> /* Include the auto-generated decoder for 16 bit insn */
> --
> 2.17.1
>
>
Alistair Francis <alistair23@gmail.com> 於 2021年4月27日 週二 下午2:05寫道：
> On Wed, Apr 21, 2021 at 2:14 PM <frank.chang@sifive.com> wrote:
> >
> > From: Kito Cheng <kito.cheng@sifive.com>
> >
> > Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> > ---
> > target/riscv/insn32-64.decode | 4 +++
> > target/riscv/insn32.decode | 7 +++-
> > target/riscv/insn_trans/trans_rvb.c.inc | 47 +++++++++++++++++++++++++
> > target/riscv/translate.c | 42 ++++++++++++++++++++++
> > 4 files changed, 99 insertions(+), 1 deletion(-)
> > create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
> >
> > diff --git a/target/riscv/insn32-64.decode
> b/target/riscv/insn32-64.decode
> > index 8157dee8b7c..f4c42720fc7 100644
> > --- a/target/riscv/insn32-64.decode
> > +++ b/target/riscv/insn32-64.decode
> > @@ -86,3 +86,7 @@ fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
> > hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
> > hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
> > hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
> > +
> > +# *** RV64B Standard Extension (in addition to RV32B) ***
> > +clzw 0110000 00000 ..... 001 ..... 0011011 @r2
> > +ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
> > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> > index 3823b3ea800..8fe838cf0d0 100644
> > --- a/target/riscv/insn32.decode
> > +++ b/target/riscv/insn32.decode
> > @@ -40,6 +40,7 @@
> > &i imm rs1 rd
> > &j imm rd
> > &r rd rs1 rs2
> > +&r2 rd rs1
> > &s imm rs1 rs2
> > &u imm rd
> > &shift shamt rs1 rd
> > @@ -67,7 +68,7 @@
> > @r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
> > @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
> > @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
> > -@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
> > +@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
> > @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
> > @r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
> > @r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd
> > @@ -592,3 +593,7 @@ vcompress_vm 010111 - ..... ..... 010 .....
> 1010111 @r
> >
> > vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
> > vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
> > +
> > +# *** RV32B Standard Extension ***
> > +clz 011000 000000 ..... 001 ..... 0010011 @r2
> > +ctz 011000 000001 ..... 001 ..... 0010011 @r2
> > diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
> b/target/riscv/insn_trans/trans_rvb.c.inc
> > new file mode 100644
> > index 00000000000..76788c2f353
> > --- /dev/null
> > +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> > @@ -0,0 +1,47 @@
> > +/*
> > + * RISC-V translation routines for the RVB Standard Extension.
> > + *
> > + * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
> > + * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> it
> > + * under the terms and conditions of the GNU General Public License,
> > + * version 2 or later, as published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope it will be useful, but
> WITHOUT
> > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
> License for
> > + * more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> along with
> > + * this program. If not, see <http://www.gnu.org/licenses/>.
> > + */
> > +
> > +static bool trans_clz(DisasContext *ctx, arg_clz *a)
> > +{
> > + REQUIRE_EXT(ctx, RVB);
> > + return gen_unary(ctx, a, gen_clz);
> > +}
> > +
> > +static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
> > +{
> > + REQUIRE_EXT(ctx, RVB);
> > + return gen_unary(ctx, a, gen_ctz);
> > +}
> > +
> > +/* RV64-only instructions */
> > +#ifdef TARGET_RISCV64
> > +
> > +static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
> > +{
> > + REQUIRE_EXT(ctx, RVB);
> > + return gen_unary(ctx, a, gen_clzw);
> > +}
> > +
> > +static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
> > +{
> > + REQUIRE_EXT(ctx, RVB);
> > + return gen_unary(ctx, a, gen_ctzw);
> > +}
> > +
> > +#endif
> > diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> > index 2f9f5ccc621..4648c422f42 100644
> > --- a/target/riscv/translate.c
> > +++ b/target/riscv/translate.c
> > @@ -536,6 +536,23 @@ static bool gen_arith_div_uw(DisasContext *ctx,
> arg_r *a,
> >
> > #endif
> >
> > +#ifdef TARGET_RISCV64
>
> Thanks for the patches!
>
> Unfortunately this will need to be rebased and updated. We don't want
> any more #ifdef's on the RISC-V xlen. The idea is to make the XLEN not
> just a compile time constant.
>
> The latest riscv-to-apply.next tree has changes to allow you to do
> this. See this commit for what this will look like:
>
> https://github.com/alistair23/qemu/commit/4965ae3f6f3838e651d1a33050b15b4ca3d822a0
>
> The changes should be in master after the 6.0 release.
>
> Alistair
>
Thanks, I will rebase my patchset.
Frank Chang
>
> > +
> > +static void gen_ctzw(TCGv ret, TCGv arg1)
> > +{
> > + tcg_gen_ori_i64(ret, arg1, MAKE_64BIT_MASK(32, 32));
> > + tcg_gen_ctzi_i64(ret, ret, 64);
> > +}
> > +
> > +static void gen_clzw(TCGv ret, TCGv arg1)
> > +{
> > + tcg_gen_ext32u_i64(ret, arg1);
> > + tcg_gen_clzi_i64(ret, ret, 64);
> > + tcg_gen_subi_i64(ret, ret, 32);
> > +}
> > +
> > +#endif
> > +
> > static bool gen_arith(DisasContext *ctx, arg_r *a,
> > void(*func)(TCGv, TCGv, TCGv))
> > {
> > @@ -581,6 +598,30 @@ static uint32_t opcode_at(DisasContextBase *dcbase,
> target_ulong pc)
> > return cpu_ldl_code(env, pc);
> > }
> >
> > +static void gen_ctz(TCGv ret, TCGv arg1)
> > +{
> > + tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
> > +}
> > +
> > +static void gen_clz(TCGv ret, TCGv arg1)
> > +{
> > + tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
> > +}
> > +
> > +static bool gen_unary(DisasContext *ctx, arg_r2 *a,
> > + void(*func)(TCGv, TCGv))
> > +{
> > + TCGv source = tcg_temp_new();
> > +
> > + gen_get_gpr(source, a->rs1);
> > +
> > + (*func)(source, source);
> > +
> > + gen_set_gpr(a->rd, source);
> > + tcg_temp_free(source);
> > + return true;
> > +}
> > +
> > /* Include insn module translation function */
> > #include "insn_trans/trans_rvi.c.inc"
> > #include "insn_trans/trans_rvm.c.inc"
> > @@ -589,6 +630,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase,
> target_ulong pc)
> > #include "insn_trans/trans_rvd.c.inc"
> > #include "insn_trans/trans_rvh.c.inc"
> > #include "insn_trans/trans_rvv.c.inc"
> > +#include "insn_trans/trans_rvb.c.inc"
> > #include "insn_trans/trans_privileged.c.inc"
> >
> > /* Include the auto-generated decoder for 16 bit insn */
> > --
> > 2.17.1
> >
> >
>
>
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