[PULL 0/5] target-arm queue
[PULL v2 00/32] target-arm queue
1
Handful of arm fixes for the rc.
1
For some reason the xilinx can bus patches built in my local config
2
but not in the merge-test ones; dropped those.
2
3
3
The following changes since commit 555249a59e9cdd6b58da103aba5cf3a2d45c899f:
4
-- PMM
4
5
5
Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-04-10 16:58:56 +0100)
6
The following changes since commit a68694cd1f3e5448cca814ff39b871f9ebd71ed5:
7
8
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/edk2-next-20200914' into staging (2020-09-14 12:18:58 +0100)
6
9
7
are available in the Git repository at:
10
are available in the Git repository at:
8
11
9
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210412
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200914-1
10
13
11
for you to fetch changes up to 52c01ada86611136e3122dd139788dbcbc292d86:
14
for you to fetch changes up to 4fe986dd4480308ecf07200cfbd3c3d494a0f639:
12
15
13
exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1 (2021-04-12 11:06:24 +0100)
16
tests/acceptance: console boot tests for quanta-gsj (2020-09-14 14:24:59 +0100)
14
17
15
----------------------------------------------------------------
18
----------------------------------------------------------------
16
target-arm queue:
19
* hw/misc/a9scu: Do not allow invalid CPU count
17
* hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts
20
* hw/misc/a9scu: Minor cleanups
18
* hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs
21
* hw/timer/armv7m_systick: assert that board code set system_clock_scale
19
* accel/tcg: Preserve PAGE_ANON when changing page permissions
22
* decodetree: Improve identifier matching
20
* target/arm: Check PAGE_WRITE_ORG for MTE writeability
23
* target/arm: Clean up neon fp insn size field decode
21
* exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1
24
* target/arm: Remove KVM support for 32-bit Arm hosts
25
* hw/arm/mps2: New board models mps2-an386, mps2-an500
26
* Deprecate Unicore32 port
27
* Deprecate lm32 port
28
* target/arm: Count PMU events when MDCR.SPME is set
29
* hw/arm: versal-virt: Correct the tx/rx GEM clocks
30
* New Nuvoton iBMC board models npcm750-evb, quanta-gsj
22
31
23
----------------------------------------------------------------
32
----------------------------------------------------------------
24
Richard Henderson (3):
33
Aaron Lindsay (1):
25
accel/tcg: Preserve PAGE_ANON when changing page permissions
34
target/arm: Count PMU events when MDCR.SPME is set
26
target/arm: Check PAGE_WRITE_ORG for MTE writeability
27
exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1
28
35
29
Zenghui Yu (2):
36
Edgar E. Iglesias (1):
30
hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts
37
hw/arm: versal-virt: Correct the tx/rx GEM clocks
31
hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs
32
38
33
include/exec/cpu-all.h | 4 ++--
39
Havard Skinnemoen (14):
34
tests/tcg/aarch64/mte.h | 3 ++-
40
hw/misc: Add NPCM7xx System Global Control Registers device model
35
accel/tcg/translate-all.c | 9 ++++++--
41
hw/misc: Add NPCM7xx Clock Controller device model
36
hw/arm/smmuv3.c | 12 +++++++----
42
hw/timer: Add NPCM7xx Timer device model
37
hw/arm/virt-acpi-build.c | 4 ++--
43
hw/arm: Add NPCM730 and NPCM750 SoC models
38
target/arm/mte_helper.c | 2 +-
44
hw/arm: Add two NPCM7xx-based machines
39
tests/tcg/aarch64/mte-6.c | 43 +++++++++++++++++++++++++++++++++++++++
45
roms: Add virtual Boot ROM for NPCM7xx SoCs
40
tests/tcg/aarch64/Makefile.target | 2 +-
46
hw/arm: Load -bios image as a boot ROM for npcm7xx
41
8 files changed, 66 insertions(+), 13 deletions(-)
47
hw/nvram: NPCM7xx OTP device model
42
create mode 100644 tests/tcg/aarch64/mte-6.c
48
hw/mem: Stubbed out NPCM7xx Memory Controller model
49
hw/ssi: NPCM7xx Flash Interface Unit device model
50
hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj
51
hw/arm/npcm7xx: add board setup stub for CPU and UART clocks
52
docs/system: Add Nuvoton machine documentation
53
tests/acceptance: console boot tests for quanta-gsj
43
54
55
Peter Maydell (11):
56
hw/timer/armv7m_systick: assert that board code set system_clock_scale
57
target/arm: Convert Neon 3-same-fp size field to MO_* in decode
58
target/arm: Convert Neon VCVT fp size field to MO_* in decode
59
target/arm: Convert VCMLA, VCADD size field to MO_* in decode
60
target/arm: Remove KVM support for 32-bit Arm hosts
61
target/arm: Remove no-longer-reachable 32-bit KVM code
62
hw/arm/mps2: New board model mps2-an386
63
hw/arm/mps2: New board model mps2-an500
64
docs/system/arm/mps2.rst: Make board list consistent
65
Deprecate Unicore32 port
66
Deprecate lm32 port
67
68
Philippe Mathieu-Daudé (4):
69
hw/misc/a9scu: Do not allow invalid CPU count
70
hw/misc/a9scu: Simplify setting MemoryRegionOps::valid fields
71
hw/misc/a9scu: Simplify setting MemoryRegionOps::impl fields
72
hw/misc/a9scu: Report unimplemented accesses with qemu_log_mask(UNIMP)
73
74
Richard Henderson (1):
75
decodetree: Improve identifier matching
76
77
docs/system/arm/mps2.rst | 20 +-
78
docs/system/arm/nuvoton.rst | 92 +++++
79
docs/system/deprecated.rst | 32 +-
80
docs/system/target-arm.rst | 1 +
81
configure | 2 +-
82
default-configs/arm-softmmu.mak | 1 +
83
include/hw/arm/npcm7xx.h | 112 +++++++
84
include/hw/mem/npcm7xx_mc.h | 36 ++
85
include/hw/misc/npcm7xx_clk.h | 48 +++
86
include/hw/misc/npcm7xx_gcr.h | 43 +++
87
include/hw/nvram/npcm7xx_otp.h | 79 +++++
88
include/hw/ssi/npcm7xx_fiu.h | 73 ++++
89
include/hw/timer/npcm7xx_timer.h | 78 +++++
90
target/arm/kvm-consts.h | 7 -
91
target/arm/kvm_arm.h | 6 -
92
target/arm/neon-dp.decode | 18 +-
93
target/arm/neon-shared.decode | 18 +-
94
tests/decode/succ_ident1.decode | 7 +
95
hw/arm/mps2.c | 97 +++++-
96
hw/arm/npcm7xx.c | 532 +++++++++++++++++++++++++++++
97
hw/arm/npcm7xx_boards.c | 197 +++++++++++
98
hw/arm/xlnx-versal-virt.c | 2 +-
99
hw/mem/npcm7xx_mc.c | 84 +++++
100
hw/misc/a9scu.c | 59 ++--
101
hw/misc/npcm7xx_clk.c | 266 +++++++++++++++
102
hw/misc/npcm7xx_gcr.c | 269 +++++++++++++++
103
hw/nvram/npcm7xx_otp.c | 440 ++++++++++++++++++++++++
104
hw/ssi/npcm7xx_fiu.c | 572 +++++++++++++++++++++++++++++++
105
hw/timer/armv7m_systick.c | 8 +
106
hw/timer/npcm7xx_timer.c | 543 ++++++++++++++++++++++++++++++
107
target/arm/cpu.c | 101 +++---
108
target/arm/helper.c | 2 +-
109
target/arm/kvm.c | 7 -
110
target/arm/kvm32.c | 595 ---------------------------------
111
.gitmodules | 3 +
112
MAINTAINERS | 10 +
113
hw/arm/Kconfig | 9 +
114
hw/arm/meson.build | 1 +
115
hw/mem/meson.build | 1 +
116
hw/misc/meson.build | 4 +
117
hw/misc/trace-events | 8 +
118
hw/nvram/meson.build | 1 +
119
hw/ssi/meson.build | 1 +
120
hw/ssi/trace-events | 11 +
121
hw/timer/meson.build | 1 +
122
hw/timer/trace-events | 5 +
123
pc-bios/README | 6 +
124
pc-bios/meson.build | 1 +
125
pc-bios/npcm7xx_bootrom.bin | Bin 0 -> 768 bytes
126
roms/Makefile | 7 +
127
roms/vbootrom | 1 +
128
scripts/decodetree.py | 46 ++-
129
target/arm/meson.build | 5 +-
130
target/arm/translate-neon.c.inc | 42 ++-
131
tests/acceptance/boot_linux_console.py | 83 +++++
132
55 files changed, 3910 insertions(+), 783 deletions(-)
133
create mode 100644 docs/system/arm/nuvoton.rst
134
create mode 100644 include/hw/arm/npcm7xx.h
135
create mode 100644 include/hw/mem/npcm7xx_mc.h
136
create mode 100644 include/hw/misc/npcm7xx_clk.h
137
create mode 100644 include/hw/misc/npcm7xx_gcr.h
138
create mode 100644 include/hw/nvram/npcm7xx_otp.h
139
create mode 100644 include/hw/ssi/npcm7xx_fiu.h
140
create mode 100644 include/hw/timer/npcm7xx_timer.h
141
create mode 100644 tests/decode/succ_ident1.decode
142
create mode 100644 hw/arm/npcm7xx.c
143
create mode 100644 hw/arm/npcm7xx_boards.c
144
create mode 100644 hw/mem/npcm7xx_mc.c
145
create mode 100644 hw/misc/npcm7xx_clk.c
146
create mode 100644 hw/misc/npcm7xx_gcr.c
147
create mode 100644 hw/nvram/npcm7xx_otp.c
148
create mode 100644 hw/ssi/npcm7xx_fiu.c
149
create mode 100644 hw/timer/npcm7xx_timer.c
150
delete mode 100644 target/arm/kvm32.c
151
create mode 100644 pc-bios/npcm7xx_bootrom.bin
152
create mode 160000 roms/vbootrom
153
diff view generated by jsdifflib
[PULL 1/5] hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts
Deleted patch
1
From: Zenghui Yu <yuzenghui@huawei.com>
2
1
3
The GSIV values in SMMUv3 IORT node are not correct as they don't match
4
the SMMUIrq enumeration, which describes the IRQ<->PIN mapping used by
5
our emulated vSMMU.
6
7
Fixes: a703b4f6c1ee ("hw/arm/virt-acpi-build: Add smmuv3 node in IORT table")
8
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
9
Acked-by: Eric Auger <eric.auger@redhat.com>
10
Message-id: 20210402084731.93-1-yuzenghui@huawei.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/virt-acpi-build.c | 4 ++--
14
1 file changed, 2 insertions(+), 2 deletions(-)
15
16
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/virt-acpi-build.c
19
+++ b/hw/arm/virt-acpi-build.c
20
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
21
smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE);
22
smmu->event_gsiv = cpu_to_le32(irq);
23
smmu->pri_gsiv = cpu_to_le32(irq + 1);
24
- smmu->gerr_gsiv = cpu_to_le32(irq + 2);
25
- smmu->sync_gsiv = cpu_to_le32(irq + 3);
26
+ smmu->sync_gsiv = cpu_to_le32(irq + 2);
27
+ smmu->gerr_gsiv = cpu_to_le32(irq + 3);
28
29
/* Identity RID mapping covering the whole input RID range */
30
idmap = &smmu->id_mapping_array[0];
31
--
32
2.20.1
33
34
diff view generated by jsdifflib
[PULL 2/5] hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs
Deleted patch
1
From: Zenghui Yu <yuzenghui@huawei.com>
2
1
3
In emulation of the CFGI_STE_RANGE command, we now take StreamID as the
4
start of the invalidation range, regardless of whatever the Range is,
5
whilst the spec clearly states that
6
7
- "Invalidation is performed for an *aligned* range of 2^(Range+1)
8
StreamIDs."
9
10
- "The bottom Range+1 bits of the StreamID parameter are IGNORED,
11
aligning the range to its size."
12
13
Take CFGI_ALL (where Range == 31) as an example, if there are some random
14
bits in the StreamID field, we'll fail to perform the full invalidation but
15
get a strange range (e.g., SMMUSIDRange={.start=1, .end=0}) instead. Rework
16
the emulation a bit to get rid of the discrepancy with the spec.
17
18
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
19
Acked-by: Eric Auger <eric.auger@redhat.com>
20
Message-id: 20210402100449.528-1-yuzenghui@huawei.com
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
23
hw/arm/smmuv3.c | 12 ++++++++----
24
1 file changed, 8 insertions(+), 4 deletions(-)
25
26
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/arm/smmuv3.c
29
+++ b/hw/arm/smmuv3.c
30
@@ -XXX,XX +XXX,XX @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
31
}
32
case SMMU_CMD_CFGI_STE_RANGE: /* same as SMMU_CMD_CFGI_ALL */
33
{
34
- uint32_t start = CMD_SID(&cmd);
35
+ uint32_t sid = CMD_SID(&cmd), mask;
36
uint8_t range = CMD_STE_RANGE(&cmd);
37
- uint64_t end = start + (1ULL << (range + 1)) - 1;
38
- SMMUSIDRange sid_range = {start, end};
39
+ SMMUSIDRange sid_range;
40
41
if (CMD_SSEC(&cmd)) {
42
cmd_error = SMMU_CERROR_ILL;
43
break;
44
}
45
- trace_smmuv3_cmdq_cfgi_ste_range(start, end);
46
+
47
+ mask = (1ULL << (range + 1)) - 1;
48
+ sid_range.start = sid & ~mask;
49
+ sid_range.end = sid_range.start + mask;
50
+
51
+ trace_smmuv3_cmdq_cfgi_ste_range(sid_range.start, sid_range.end);
52
g_hash_table_foreach_remove(bs->configs, smmuv3_invalidate_ste,
53
&sid_range);
54
break;
55
--
56
2.20.1
57
58
diff view generated by jsdifflib
[PULL 3/5] accel/tcg: Preserve PAGE_ANON when changing page permissions
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Using mprotect() to change PROT_* does not change the MAP_ANON
4
previously set with mmap(). Our linux-user version of MTE only
5
works with MAP_ANON pages, so losing PAGE_ANON caused MTE to
6
stop working.
7
8
Reported-by: Stephen Long <steplong@quicinc.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Tested-by: Alex Bennée <alex.bennee@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
tests/tcg/aarch64/mte.h | 3 ++-
15
accel/tcg/translate-all.c | 9 +++++--
16
tests/tcg/aarch64/mte-6.c | 43 +++++++++++++++++++++++++++++++
17
tests/tcg/aarch64/Makefile.target | 2 +-
18
4 files changed, 53 insertions(+), 4 deletions(-)
19
create mode 100644 tests/tcg/aarch64/mte-6.c
20
21
diff --git a/tests/tcg/aarch64/mte.h b/tests/tcg/aarch64/mte.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/tests/tcg/aarch64/mte.h
24
+++ b/tests/tcg/aarch64/mte.h
25
@@ -XXX,XX +XXX,XX @@ static void enable_mte(int tcf)
26
}
27
}
28
29
-static void *alloc_mte_mem(size_t size)
30
+static void * alloc_mte_mem(size_t size) __attribute__((unused));
31
+static void * alloc_mte_mem(size_t size)
32
{
33
void *p = mmap(NULL, size, PROT_READ | PROT_WRITE | PROT_MTE,
34
MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
35
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/accel/tcg/translate-all.c
38
+++ b/accel/tcg/translate-all.c
39
@@ -XXX,XX +XXX,XX @@ void page_set_flags(target_ulong start, target_ulong end, int flags)
40
a missing call to h2g_valid. */
41
assert(end - 1 <= GUEST_ADDR_MAX);
42
assert(start < end);
43
+ /* Only set PAGE_ANON with new mappings. */
44
+ assert(!(flags & PAGE_ANON) || (flags & PAGE_RESET));
45
assert_memory_lock();
46
47
start = start & TARGET_PAGE_MASK;
48
@@ -XXX,XX +XXX,XX @@ void page_set_flags(target_ulong start, target_ulong end, int flags)
49
p->first_tb) {
50
tb_invalidate_phys_page(addr, 0);
51
}
52
- if (reset_target_data && p->target_data) {
53
+ if (reset_target_data) {
54
g_free(p->target_data);
55
p->target_data = NULL;
56
+ p->flags = flags;
57
+ } else {
58
+ /* Using mprotect on a page does not change MAP_ANON. */
59
+ p->flags = (p->flags & PAGE_ANON) | flags;
60
}
61
- p->flags = flags;
62
}
63
}
64
65
diff --git a/tests/tcg/aarch64/mte-6.c b/tests/tcg/aarch64/mte-6.c
66
new file mode 100644
67
index XXXXXXX..XXXXXXX
68
--- /dev/null
69
+++ b/tests/tcg/aarch64/mte-6.c
70
@@ -XXX,XX +XXX,XX @@
71
+#include "mte.h"
72
+
73
+void pass(int sig, siginfo_t *info, void *uc)
74
+{
75
+ assert(info->si_code == SEGV_MTESERR);
76
+ exit(0);
77
+}
78
+
79
+int main(void)
80
+{
81
+ enable_mte(PR_MTE_TCF_SYNC);
82
+
83
+ void *brk = sbrk(16);
84
+ if (brk == (void *)-1) {
85
+ perror("sbrk");
86
+ return 2;
87
+ }
88
+
89
+ if (mprotect(brk, 16, PROT_READ | PROT_WRITE | PROT_MTE)) {
90
+ perror("mprotect");
91
+ return 2;
92
+ }
93
+
94
+ int *p1, *p2;
95
+ long excl = 1;
96
+
97
+ asm("irg %0,%1,%2" : "=r"(p1) : "r"(brk), "r"(excl));
98
+ asm("gmi %0,%1,%0" : "+r"(excl) : "r"(p1));
99
+ asm("irg %0,%1,%2" : "=r"(p2) : "r"(brk), "r"(excl));
100
+ asm("stg %0,[%0]" : : "r"(p1));
101
+
102
+ *p1 = 0;
103
+
104
+ struct sigaction sa;
105
+ memset(&sa, 0, sizeof(sa));
106
+ sa.sa_sigaction = pass;
107
+ sa.sa_flags = SA_SIGINFO;
108
+ sigaction(SIGSEGV, &sa, NULL);
109
+
110
+ *p2 = 0;
111
+
112
+ abort();
113
+}
114
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
115
index XXXXXXX..XXXXXXX 100644
116
--- a/tests/tcg/aarch64/Makefile.target
117
+++ b/tests/tcg/aarch64/Makefile.target
118
@@ -XXX,XX +XXX,XX @@ AARCH64_TESTS += bti-2
119
120
# MTE Tests
121
ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_MTE),)
122
-AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4
123
+AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-6
124
mte-%: CFLAGS += -march=armv8.5-a+memtag
125
endif
126
127
--
128
2.20.1
129
130
diff view generated by jsdifflib
[PULL 4/5] target/arm: Check PAGE_WRITE_ORG for MTE writeability
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
We can remove PAGE_WRITE when (internally) marking a page
4
read-only because it contains translated code.
5
6
This can be triggered by tests/tcg/aarch64/bti-2, after
7
having serviced SIGILL trampolines on the stack.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/mte_helper.c | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/mte_helper.c
19
+++ b/target/arm/mte_helper.c
20
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
21
uint8_t *tags;
22
uintptr_t index;
23
24
- if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE : PAGE_READ))) {
25
+ if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE_ORG : PAGE_READ))) {
26
/* SIGSEGV */
27
arm_cpu_tlb_fill(env_cpu(env), ptr, ptr_size, ptr_access,
28
ptr_mmu_idx, false, ra);
29
--
30
2.20.1
31
32
diff view generated by jsdifflib
[PULL 5/5] exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Unfortuately, the elements of PAGE_* were not in numerical
4
order and so PAGE_ANON was added to an "unused" bit.
5
As an arbitrary choice, move PAGE_TARGET_{1,2} together.
6
7
Cc: Laurent Vivier <laurent@vivier.eu>
8
Fixes: 26bab757d41b ("linux-user: Introduce PAGE_ANON")
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Buglink: https://bugs.launchpad.net/bugs/1922617
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
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Reviewed-by: Laurent Vivier <laurent@vivier.eu>
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Tested-by: Laurent Vivier <laurent@vivier.eu>
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Tested-by: Nathan Chancellor <nathan@kernel.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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include/exec/cpu-all.h | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
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index XXXXXXX..XXXXXXX 100644
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--- a/include/exec/cpu-all.h
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+++ b/include/exec/cpu-all.h
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@@ -XXX,XX +XXX,XX @@ extern intptr_t qemu_host_page_mask;
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#define PAGE_RESERVED 0x0100
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#endif
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/* Target-specific bits that will be used via page_get_flags(). */
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-#define PAGE_TARGET_1 0x0080
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-#define PAGE_TARGET_2 0x0200
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+#define PAGE_TARGET_1 0x0200
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+#define PAGE_TARGET_2 0x0400
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#if defined(CONFIG_USER_ONLY)
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void page_dump(FILE *f);
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--
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2.20.1
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Patchew 2.1-devel-b67e4c2

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