| 1 | The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a: | 1 | The following changes since commit 7774e403f2ac58b3e87bfe8d2f77676501ba893e: |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into staging (2021-03-22 14:26:13 +0000) | 3 | Merge remote-tracking branch 'remotes/kraxel/tags/fixes-20200825-pull-request' into staging (2020-08-25 10:54:51 +0100) |
| 4 | 4 | ||
| 5 | are available in the Git repository at: | 5 | are available in the Git repository at: |
| 6 | 6 | ||
| 7 | git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2 | 7 | git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200825 |
| 8 | 8 | ||
| 9 | for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5: | 9 | for you to fetch changes up to e39a8320b088dd5efc9ebaafe387e52b3d962665: |
| 10 | 10 | ||
| 11 | target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 21:54:40 -0400) | 11 | target/riscv: Support the Virtual Instruction fault (2020-08-25 09:11:36 -0700) |
| 12 | 12 | ||
| 13 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
| 14 | RISC-V PR for 6.0 | 14 | This pull request first adds support for multi-socket NUMA RISC-V |
| 15 | machines. The Spike and Virt machines both support NUMA sockets. | ||
| 15 | 16 | ||
| 16 | This PR includes: | 17 | This PR also updates the current experimental Hypervisor support to the |
| 17 | - Fix for vector CSR access | 18 | v0.6.1 spec. |
| 18 | - Improvements to the Ibex UART device | ||
| 19 | - PMP improvements and bug fixes | ||
| 20 | - Hypervisor extension bug fixes | ||
| 21 | - ramfb support for the virt machine | ||
| 22 | - Fast read support for SST flash | ||
| 23 | - Improvements to the microchip_pfsoc machine | ||
| 24 | 19 | ||
| 25 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
| 26 | Alexander Wagner (1): | 21 | Alistair Francis (13): |
| 27 | hw/char: disable ibex uart receive if the buffer is full | 22 | target/riscv: Allow setting a two-stage lookup in the virt status |
| 23 | target/riscv: Allow generating hlv/hlvx/hsv instructions | ||
| 24 | target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions | ||
| 25 | target/riscv: Don't allow guest to write to htinst | ||
| 26 | target/riscv: Convert MSTATUS MTL to GVA | ||
| 27 | target/riscv: Fix the interrupt cause code | ||
| 28 | target/riscv: Update the Hypervisor trap return/entry | ||
| 29 | target/riscv: Update the CSRs to the v0.6 Hyp extension | ||
| 30 | target/riscv: Only support a single VSXL length | ||
| 31 | target/riscv: Only support little endian guests | ||
| 32 | target/riscv: Support the v0.6 Hypervisor extension CRSs | ||
| 33 | target/riscv: Return the exception from invalid CSR accesses | ||
| 34 | target/riscv: Support the Virtual Instruction fault | ||
| 28 | 35 | ||
| 29 | Asherah Connor (2): | 36 | Anup Patel (5): |
| 30 | hw/riscv: Add fw_cfg support to virt | 37 | hw/riscv: Allow creating multiple instances of CLINT |
| 31 | hw/riscv: allow ramfb on virt | 38 | hw/riscv: Allow creating multiple instances of PLIC |
| 39 | hw/riscv: Add helpers for RISC-V multi-socket NUMA machines | ||
| 40 | hw/riscv: spike: Allow creating multiple NUMA sockets | ||
| 41 | hw/riscv: virt: Allow creating multiple NUMA sockets | ||
| 32 | 42 | ||
| 33 | Bin Meng (3): | 43 | include/hw/riscv/numa.h | 113 +++++++ |
| 34 | hw/block: m25p80: Support fast read for SST flashes | 44 | include/hw/riscv/sifive_clint.h | 7 +- |
| 35 | hw/riscv: microchip_pfsoc: Map EMMC/SD mux register | 45 | include/hw/riscv/sifive_plic.h | 12 +- |
| 36 | docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine | 46 | include/hw/riscv/spike.h | 11 +- |
| 47 | include/hw/riscv/virt.h | 9 +- | ||
| 48 | target/riscv/cpu.h | 2 + | ||
| 49 | target/riscv/cpu_bits.h | 25 +- | ||
| 50 | target/riscv/helper.h | 4 + | ||
| 51 | target/riscv/insn32-64.decode | 5 + | ||
| 52 | target/riscv/insn32.decode | 11 + | ||
| 53 | hw/riscv/numa.c | 242 +++++++++++++++ | ||
| 54 | hw/riscv/sifive_clint.c | 20 +- | ||
| 55 | hw/riscv/sifive_e.c | 4 +- | ||
| 56 | hw/riscv/sifive_plic.c | 24 +- | ||
| 57 | hw/riscv/sifive_u.c | 4 +- | ||
| 58 | hw/riscv/spike.c | 232 +++++++++----- | ||
| 59 | hw/riscv/virt.c | 526 ++++++++++++++++++-------------- | ||
| 60 | target/riscv/cpu_helper.c | 123 ++++---- | ||
| 61 | target/riscv/csr.c | 171 +++++++++-- | ||
| 62 | target/riscv/op_helper.c | 176 ++++++++++- | ||
| 63 | target/riscv/translate.c | 10 - | ||
| 64 | hw/riscv/meson.build | 1 + | ||
| 65 | target/riscv/insn_trans/trans_rvh.c.inc | 342 ++++++++++++++++++++- | ||
| 66 | 23 files changed, 1630 insertions(+), 444 deletions(-) | ||
| 67 | create mode 100644 include/hw/riscv/numa.h | ||
| 68 | create mode 100644 hw/riscv/numa.c | ||
| 37 | 69 | ||
| 38 | Frank Chang (1): | ||
| 39 | target/riscv: fix vs() to return proper error code | ||
| 40 | |||
| 41 | Georg Kotheimer (6): | ||
| 42 | target/riscv: Adjust privilege level for HLV(X)/HSV instructions | ||
| 43 | target/riscv: Make VSTIP and VSEIP read-only in hip | ||
| 44 | target/riscv: Use background registers also for MSTATUS_MPV | ||
| 45 | target/riscv: Fix read and write accesses to vsip and vsie | ||
| 46 | target/riscv: Add proper two-stage lookup exception detection | ||
| 47 | target/riscv: Prevent lost illegal instruction exceptions | ||
| 48 | |||
| 49 | Jim Shu (3): | ||
| 50 | target/riscv: propagate PMP permission to TLB page | ||
| 51 | target/riscv: add log of PMP permission checking | ||
| 52 | target/riscv: flush TLB pages if PMP permission has been changed | ||
| 53 | |||
| 54 | docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++ | ||
| 55 | docs/system/target-riscv.rst | 1 + | ||
| 56 | include/hw/char/ibex_uart.h | 4 + | ||
| 57 | include/hw/riscv/microchip_pfsoc.h | 1 + | ||
| 58 | include/hw/riscv/virt.h | 2 + | ||
| 59 | target/riscv/cpu.h | 4 + | ||
| 60 | target/riscv/pmp.h | 4 +- | ||
| 61 | hw/block/m25p80.c | 3 + | ||
| 62 | hw/char/ibex_uart.c | 23 +++- | ||
| 63 | hw/riscv/microchip_pfsoc.c | 6 + | ||
| 64 | hw/riscv/virt.c | 33 ++++++ | ||
| 65 | target/riscv/cpu.c | 1 + | ||
| 66 | target/riscv/cpu_helper.c | 144 +++++++++++++++-------- | ||
| 67 | target/riscv/csr.c | 77 +++++++------ | ||
| 68 | target/riscv/pmp.c | 84 ++++++++++---- | ||
| 69 | target/riscv/translate.c | 179 +---------------------------- | ||
| 70 | hw/riscv/Kconfig | 1 + | ||
| 71 | 17 files changed, 367 insertions(+), 289 deletions(-) | ||
| 72 | create mode 100644 docs/system/riscv/microchip-icicle-kit.rst | ||
| 73 | diff view generated by jsdifflib |
| 1 | From: Alexander Wagner <alexander.wagner@ulal.de> | 1 | From: Anup Patel <anup.patel@wdc.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Not disabling the UART leads to QEMU overwriting the UART receive buffer with | 3 | We extend CLINT emulation to allow multiple instances of CLINT in |
| 4 | the newest received byte. The rx_level variable is added to allow the use of | 4 | a QEMU RISC-V machine. To achieve this, we remove first HART id |
| 5 | the existing OpenTitan driver libraries. | 5 | zero assumption from CLINT emulation. |
| 6 | 6 | ||
| 7 | Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de> | 7 | Signed-off-by: Anup Patel <anup.patel@wdc.com> |
| 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 9 | Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de | 9 | Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> |
| 10 | Message-Id: <20200616032229.766089-2-anup.patel@wdc.com> | ||
| 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 11 | --- | 12 | --- |
| 12 | include/hw/char/ibex_uart.h | 4 ++++ | 13 | include/hw/riscv/sifive_clint.h | 7 ++++--- |
| 13 | hw/char/ibex_uart.c | 23 ++++++++++++++++++----- | 14 | hw/riscv/sifive_clint.c | 20 ++++++++++++-------- |
| 14 | 2 files changed, 22 insertions(+), 5 deletions(-) | 15 | hw/riscv/sifive_e.c | 2 +- |
| 16 | hw/riscv/sifive_u.c | 2 +- | ||
| 17 | hw/riscv/spike.c | 2 +- | ||
| 18 | hw/riscv/virt.c | 2 +- | ||
| 19 | 6 files changed, 20 insertions(+), 15 deletions(-) | ||
| 15 | 20 | ||
| 16 | diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h | 21 | diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/riscv/sifive_clint.h |
| 17 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/include/hw/char/ibex_uart.h | 23 | --- a/include/hw/riscv/sifive_clint.h |
| 19 | +++ b/include/hw/char/ibex_uart.h | 24 | +++ b/include/hw/riscv/sifive_clint.h |
| 20 | @@ -XXX,XX +XXX,XX @@ REG32(FIFO_CTRL, 0x1c) | 25 | @@ -XXX,XX +XXX,XX @@ typedef struct SiFiveCLINTState { |
| 21 | FIELD(FIFO_CTRL, RXILVL, 2, 3) | 26 | |
| 22 | FIELD(FIFO_CTRL, TXILVL, 5, 2) | 27 | /*< public >*/ |
| 23 | REG32(FIFO_STATUS, 0x20) | 28 | MemoryRegion mmio; |
| 24 | + FIELD(FIFO_STATUS, TXLVL, 0, 5) | 29 | + uint32_t hartid_base; |
| 25 | + FIELD(FIFO_STATUS, RXLVL, 16, 5) | 30 | uint32_t num_harts; |
| 26 | REG32(OVRD, 0x24) | 31 | uint32_t sip_base; |
| 27 | REG32(VAL, 0x28) | 32 | uint32_t timecmp_base; |
| 28 | REG32(TIMEOUT_CTRL, 0x2c) | 33 | @@ -XXX,XX +XXX,XX @@ typedef struct SiFiveCLINTState { |
| 29 | @@ -XXX,XX +XXX,XX @@ struct IbexUartState { | 34 | uint32_t aperture_size; |
| 30 | uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE]; | 35 | } SiFiveCLINTState; |
| 31 | uint32_t tx_level; | 36 | |
| 32 | 37 | -DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts, | |
| 33 | + uint32_t rx_level; | 38 | - uint32_t sip_base, uint32_t timecmp_base, uint32_t time_base, |
| 34 | + | 39 | - bool provide_rdtime); |
| 35 | QEMUTimer *fifo_trigger_handle; | 40 | +DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, |
| 36 | uint64_t char_tx_time; | 41 | + uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base, |
| 37 | 42 | + uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime); | |
| 38 | diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c | 43 | |
| 44 | enum { | ||
| 45 | SIFIVE_SIP_BASE = 0x0, | ||
| 46 | diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c | ||
| 39 | index XXXXXXX..XXXXXXX 100644 | 47 | index XXXXXXX..XXXXXXX 100644 |
| 40 | --- a/hw/char/ibex_uart.c | 48 | --- a/hw/riscv/sifive_clint.c |
| 41 | +++ b/hw/char/ibex_uart.c | 49 | +++ b/hw/riscv/sifive_clint.c |
| 42 | @@ -XXX,XX +XXX,XX @@ static int ibex_uart_can_receive(void *opaque) | 50 | @@ -XXX,XX +XXX,XX @@ static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size) |
| 51 | SiFiveCLINTState *clint = opaque; | ||
| 52 | if (addr >= clint->sip_base && | ||
| 53 | addr < clint->sip_base + (clint->num_harts << 2)) { | ||
| 54 | - size_t hartid = (addr - clint->sip_base) >> 2; | ||
| 55 | + size_t hartid = clint->hartid_base + ((addr - clint->sip_base) >> 2); | ||
| 56 | CPUState *cpu = qemu_get_cpu(hartid); | ||
| 57 | CPURISCVState *env = cpu ? cpu->env_ptr : NULL; | ||
| 58 | if (!env) { | ||
| 59 | @@ -XXX,XX +XXX,XX @@ static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size) | ||
| 60 | } | ||
| 61 | } else if (addr >= clint->timecmp_base && | ||
| 62 | addr < clint->timecmp_base + (clint->num_harts << 3)) { | ||
| 63 | - size_t hartid = (addr - clint->timecmp_base) >> 3; | ||
| 64 | + size_t hartid = clint->hartid_base + | ||
| 65 | + ((addr - clint->timecmp_base) >> 3); | ||
| 66 | CPUState *cpu = qemu_get_cpu(hartid); | ||
| 67 | CPURISCVState *env = cpu ? cpu->env_ptr : NULL; | ||
| 68 | if (!env) { | ||
| 69 | @@ -XXX,XX +XXX,XX @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value, | ||
| 70 | |||
| 71 | if (addr >= clint->sip_base && | ||
| 72 | addr < clint->sip_base + (clint->num_harts << 2)) { | ||
| 73 | - size_t hartid = (addr - clint->sip_base) >> 2; | ||
| 74 | + size_t hartid = clint->hartid_base + ((addr - clint->sip_base) >> 2); | ||
| 75 | CPUState *cpu = qemu_get_cpu(hartid); | ||
| 76 | CPURISCVState *env = cpu ? cpu->env_ptr : NULL; | ||
| 77 | if (!env) { | ||
| 78 | @@ -XXX,XX +XXX,XX @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value, | ||
| 79 | return; | ||
| 80 | } else if (addr >= clint->timecmp_base && | ||
| 81 | addr < clint->timecmp_base + (clint->num_harts << 3)) { | ||
| 82 | - size_t hartid = (addr - clint->timecmp_base) >> 3; | ||
| 83 | + size_t hartid = clint->hartid_base + | ||
| 84 | + ((addr - clint->timecmp_base) >> 3); | ||
| 85 | CPUState *cpu = qemu_get_cpu(hartid); | ||
| 86 | CPURISCVState *env = cpu ? cpu->env_ptr : NULL; | ||
| 87 | if (!env) { | ||
| 88 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps sifive_clint_ops = { | ||
| 89 | }; | ||
| 90 | |||
| 91 | static Property sifive_clint_properties[] = { | ||
| 92 | + DEFINE_PROP_UINT32("hartid-base", SiFiveCLINTState, hartid_base, 0), | ||
| 93 | DEFINE_PROP_UINT32("num-harts", SiFiveCLINTState, num_harts, 0), | ||
| 94 | DEFINE_PROP_UINT32("sip-base", SiFiveCLINTState, sip_base, 0), | ||
| 95 | DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0), | ||
| 96 | @@ -XXX,XX +XXX,XX @@ type_init(sifive_clint_register_types) | ||
| 97 | /* | ||
| 98 | * Create CLINT device. | ||
| 99 | */ | ||
| 100 | -DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts, | ||
| 101 | - uint32_t sip_base, uint32_t timecmp_base, uint32_t time_base, | ||
| 102 | - bool provide_rdtime) | ||
| 103 | +DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, | ||
| 104 | + uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base, | ||
| 105 | + uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime) | ||
| 43 | { | 106 | { |
| 44 | IbexUartState *s = opaque; | 107 | int i; |
| 45 | 108 | for (i = 0; i < num_harts; i++) { | |
| 46 | - if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) { | 109 | - CPUState *cpu = qemu_get_cpu(i); |
| 47 | + if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) | 110 | + CPUState *cpu = qemu_get_cpu(hartid_base + i); |
| 48 | + && !(s->uart_status & R_STATUS_RXFULL_MASK)) { | 111 | CPURISCVState *env = cpu ? cpu->env_ptr : NULL; |
| 49 | return 1; | 112 | if (!env) { |
| 113 | continue; | ||
| 114 | @@ -XXX,XX +XXX,XX @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts, | ||
| 50 | } | 115 | } |
| 51 | 116 | ||
| 52 | @@ -XXX,XX +XXX,XX @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size) | 117 | DeviceState *dev = qdev_new(TYPE_SIFIVE_CLINT); |
| 53 | 118 | + qdev_prop_set_uint32(dev, "hartid-base", hartid_base); | |
| 54 | s->uart_status &= ~R_STATUS_RXIDLE_MASK; | 119 | qdev_prop_set_uint32(dev, "num-harts", num_harts); |
| 55 | s->uart_status &= ~R_STATUS_RXEMPTY_MASK; | 120 | qdev_prop_set_uint32(dev, "sip-base", sip_base); |
| 56 | + /* The RXFULL is set after receiving a single byte | 121 | qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base); |
| 57 | + * as the FIFO buffers are not yet implemented. | 122 | diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c |
| 58 | + */ | 123 | index XXXXXXX..XXXXXXX 100644 |
| 59 | + s->uart_status |= R_STATUS_RXFULL_MASK; | 124 | --- a/hw/riscv/sifive_e.c |
| 60 | + s->rx_level += 1; | 125 | +++ b/hw/riscv/sifive_e.c |
| 61 | 126 | @@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp) | |
| 62 | if (size > rx_fifo_level) { | 127 | SIFIVE_E_PLIC_CONTEXT_STRIDE, |
| 63 | s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK; | 128 | memmap[SIFIVE_E_PLIC].size); |
| 64 | @@ -XXX,XX +XXX,XX @@ static void ibex_uart_reset(DeviceState *dev) | 129 | sifive_clint_create(memmap[SIFIVE_E_CLINT].base, |
| 65 | s->uart_timeout_ctrl = 0x00000000; | 130 | - memmap[SIFIVE_E_CLINT].size, ms->smp.cpus, |
| 66 | 131 | + memmap[SIFIVE_E_CLINT].size, 0, ms->smp.cpus, | |
| 67 | s->tx_level = 0; | 132 | SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); |
| 68 | + s->rx_level = 0; | 133 | create_unimplemented_device("riscv.sifive.e.aon", |
| 69 | 134 | memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size); | |
| 70 | s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10; | 135 | diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c |
| 71 | 136 | index XXXXXXX..XXXXXXX 100644 | |
| 72 | @@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr, | 137 | --- a/hw/riscv/sifive_u.c |
| 73 | 138 | +++ b/hw/riscv/sifive_u.c | |
| 74 | case R_RDATA: | 139 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) |
| 75 | retvalue = s->uart_rdata; | 140 | sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, |
| 76 | - if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) { | 141 | serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); |
| 77 | + if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) { | 142 | sifive_clint_create(memmap[SIFIVE_U_CLINT].base, |
| 78 | qemu_chr_fe_accept_input(&s->chr); | 143 | - memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, |
| 79 | 144 | + memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus, | |
| 80 | - s->uart_status |= R_STATUS_RXIDLE_MASK; | 145 | SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); |
| 81 | - s->uart_status |= R_STATUS_RXEMPTY_MASK; | 146 | |
| 82 | + s->rx_level -= 1; | 147 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { |
| 83 | + s->uart_status &= ~R_STATUS_RXFULL_MASK; | 148 | diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c |
| 84 | + if (s->rx_level == 0) { | 149 | index XXXXXXX..XXXXXXX 100644 |
| 85 | + s->uart_status |= R_STATUS_RXIDLE_MASK; | 150 | --- a/hw/riscv/spike.c |
| 86 | + s->uart_status |= R_STATUS_RXEMPTY_MASK; | 151 | +++ b/hw/riscv/spike.c |
| 87 | + } | 152 | @@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine) |
| 88 | } | 153 | |
| 89 | break; | 154 | /* Core Local Interruptor (timer and IPI) */ |
| 90 | case R_WDATA: | 155 | sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, |
| 91 | @@ -XXX,XX +XXX,XX @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr, | 156 | - smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, |
| 92 | case R_FIFO_STATUS: | 157 | + 0, smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, |
| 93 | retvalue = s->uart_fifo_status; | 158 | false); |
| 94 | 159 | } | |
| 95 | - retvalue |= s->tx_level & 0x1F; | 160 | |
| 96 | + retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT; | 161 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c |
| 97 | + retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT; | 162 | index XXXXXXX..XXXXXXX 100644 |
| 98 | 163 | --- a/hw/riscv/virt.c | |
| 99 | qemu_log_mask(LOG_UNIMP, | 164 | +++ b/hw/riscv/virt.c |
| 100 | "%s: RX fifos are not supported\n", __func__); | 165 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine) |
| 101 | @@ -XXX,XX +XXX,XX @@ static void ibex_uart_write(void *opaque, hwaddr addr, | 166 | VIRT_PLIC_CONTEXT_STRIDE, |
| 102 | s->uart_fifo_ctrl = value; | 167 | memmap[VIRT_PLIC].size); |
| 103 | 168 | sifive_clint_create(memmap[VIRT_CLINT].base, | |
| 104 | if (value & R_FIFO_CTRL_RXRST_MASK) { | 169 | - memmap[VIRT_CLINT].size, smp_cpus, |
| 105 | + s->rx_level = 0; | 170 | + memmap[VIRT_CLINT].size, 0, smp_cpus, |
| 106 | qemu_log_mask(LOG_UNIMP, | 171 | SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true); |
| 107 | "%s: RX fifos are not supported\n", __func__); | 172 | sifive_test_create(memmap[VIRT_TEST].base); |
| 108 | } | 173 | |
| 109 | -- | 174 | -- |
| 110 | 2.30.1 | 175 | 2.28.0 |
| 111 | 176 | ||
| 112 | 177 | diff view generated by jsdifflib |
| 1 | From: Asherah Connor <ashe@kivikakk.ee> | 1 | From: Anup Patel <anup.patel@wdc.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Allow ramfb on virt. This lets `-device ramfb' work. | 3 | We extend PLIC emulation to allow multiple instances of PLIC in |
| 4 | a QEMU RISC-V machine. To achieve this, we remove first HART id | ||
| 5 | zero assumption from PLIC emulation. | ||
| 4 | 6 | ||
| 5 | Signed-off-by: Asherah Connor <ashe@kivikakk.ee> | 7 | Signed-off-by: Anup Patel <anup.patel@wdc.com> |
| 6 | Reviewed-by: Bin Meng <bmeng.cn@gmail.com> | 8 | Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> |
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 8 | Message-id: 20210318235041.17175-3-ashe@kivikakk.ee | 10 | Message-Id: <20200616032229.766089-3-anup.patel@wdc.com> |
| 9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 10 | --- | 12 | --- |
| 11 | hw/riscv/virt.c | 3 +++ | 13 | include/hw/riscv/sifive_plic.h | 12 +++++++----- |
| 12 | 1 file changed, 3 insertions(+) | 14 | hw/riscv/sifive_e.c | 2 +- |
| 15 | hw/riscv/sifive_plic.c | 24 +++++++++++++----------- | ||
| 16 | hw/riscv/sifive_u.c | 2 +- | ||
| 17 | hw/riscv/virt.c | 2 +- | ||
| 18 | 5 files changed, 23 insertions(+), 19 deletions(-) | ||
| 13 | 19 | ||
| 20 | diff --git a/include/hw/riscv/sifive_plic.h b/include/hw/riscv/sifive_plic.h | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | ||
| 22 | --- a/include/hw/riscv/sifive_plic.h | ||
| 23 | +++ b/include/hw/riscv/sifive_plic.h | ||
| 24 | @@ -XXX,XX +XXX,XX @@ typedef struct SiFivePLICState { | ||
| 25 | /*< public >*/ | ||
| 26 | MemoryRegion mmio; | ||
| 27 | uint32_t num_addrs; | ||
| 28 | + uint32_t num_harts; | ||
| 29 | uint32_t bitfield_words; | ||
| 30 | PLICAddr *addr_config; | ||
| 31 | uint32_t *source_priority; | ||
| 32 | @@ -XXX,XX +XXX,XX @@ typedef struct SiFivePLICState { | ||
| 33 | |||
| 34 | /* config */ | ||
| 35 | char *hart_config; | ||
| 36 | + uint32_t hartid_base; | ||
| 37 | uint32_t num_sources; | ||
| 38 | uint32_t num_priorities; | ||
| 39 | uint32_t priority_base; | ||
| 40 | @@ -XXX,XX +XXX,XX @@ typedef struct SiFivePLICState { | ||
| 41 | } SiFivePLICState; | ||
| 42 | |||
| 43 | DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, | ||
| 44 | - uint32_t num_sources, uint32_t num_priorities, | ||
| 45 | - uint32_t priority_base, uint32_t pending_base, | ||
| 46 | - uint32_t enable_base, uint32_t enable_stride, | ||
| 47 | - uint32_t context_base, uint32_t context_stride, | ||
| 48 | - uint32_t aperture_size); | ||
| 49 | + uint32_t hartid_base, uint32_t num_sources, | ||
| 50 | + uint32_t num_priorities, uint32_t priority_base, | ||
| 51 | + uint32_t pending_base, uint32_t enable_base, | ||
| 52 | + uint32_t enable_stride, uint32_t context_base, | ||
| 53 | + uint32_t context_stride, uint32_t aperture_size); | ||
| 54 | |||
| 55 | #endif | ||
| 56 | diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c | ||
| 57 | index XXXXXXX..XXXXXXX 100644 | ||
| 58 | --- a/hw/riscv/sifive_e.c | ||
| 59 | +++ b/hw/riscv/sifive_e.c | ||
| 60 | @@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp) | ||
| 61 | |||
| 62 | /* MMIO */ | ||
| 63 | s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base, | ||
| 64 | - (char *)SIFIVE_E_PLIC_HART_CONFIG, | ||
| 65 | + (char *)SIFIVE_E_PLIC_HART_CONFIG, 0, | ||
| 66 | SIFIVE_E_PLIC_NUM_SOURCES, | ||
| 67 | SIFIVE_E_PLIC_NUM_PRIORITIES, | ||
| 68 | SIFIVE_E_PLIC_PRIORITY_BASE, | ||
| 69 | diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c | ||
| 70 | index XXXXXXX..XXXXXXX 100644 | ||
| 71 | --- a/hw/riscv/sifive_plic.c | ||
| 72 | +++ b/hw/riscv/sifive_plic.c | ||
| 73 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps sifive_plic_ops = { | ||
| 74 | |||
| 75 | static Property sifive_plic_properties[] = { | ||
| 76 | DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config), | ||
| 77 | + DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0), | ||
| 78 | DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0), | ||
| 79 | DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0), | ||
| 80 | DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0), | ||
| 81 | @@ -XXX,XX +XXX,XX @@ static void parse_hart_config(SiFivePLICState *plic) | ||
| 82 | } | ||
| 83 | hartid++; | ||
| 84 | |||
| 85 | - /* store hart/mode combinations */ | ||
| 86 | plic->num_addrs = addrid; | ||
| 87 | + plic->num_harts = hartid; | ||
| 88 | + | ||
| 89 | + /* store hart/mode combinations */ | ||
| 90 | plic->addr_config = g_new(PLICAddr, plic->num_addrs); | ||
| 91 | - addrid = 0, hartid = 0; | ||
| 92 | + addrid = 0, hartid = plic->hartid_base; | ||
| 93 | p = plic->hart_config; | ||
| 94 | while ((c = *p++)) { | ||
| 95 | if (c == ',') { | ||
| 96 | @@ -XXX,XX +XXX,XX @@ static void sifive_plic_irq_request(void *opaque, int irq, int level) | ||
| 97 | |||
| 98 | static void sifive_plic_realize(DeviceState *dev, Error **errp) | ||
| 99 | { | ||
| 100 | - MachineState *ms = MACHINE(qdev_get_machine()); | ||
| 101 | - unsigned int smp_cpus = ms->smp.cpus; | ||
| 102 | SiFivePLICState *plic = SIFIVE_PLIC(dev); | ||
| 103 | int i; | ||
| 104 | |||
| 105 | @@ -XXX,XX +XXX,XX @@ static void sifive_plic_realize(DeviceState *dev, Error **errp) | ||
| 106 | * lost a interrupt in the case a PLIC is attached. The SEIP bit must be | ||
| 107 | * hardware controlled when a PLIC is attached. | ||
| 108 | */ | ||
| 109 | - for (i = 0; i < smp_cpus; i++) { | ||
| 110 | - RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i)); | ||
| 111 | + for (i = 0; i < plic->num_harts; i++) { | ||
| 112 | + RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(plic->hartid_base + i)); | ||
| 113 | if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) { | ||
| 114 | error_report("SEIP already claimed"); | ||
| 115 | exit(1); | ||
| 116 | @@ -XXX,XX +XXX,XX @@ type_init(sifive_plic_register_types) | ||
| 117 | * Create PLIC device. | ||
| 118 | */ | ||
| 119 | DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, | ||
| 120 | - uint32_t num_sources, uint32_t num_priorities, | ||
| 121 | - uint32_t priority_base, uint32_t pending_base, | ||
| 122 | - uint32_t enable_base, uint32_t enable_stride, | ||
| 123 | - uint32_t context_base, uint32_t context_stride, | ||
| 124 | - uint32_t aperture_size) | ||
| 125 | + uint32_t hartid_base, uint32_t num_sources, | ||
| 126 | + uint32_t num_priorities, uint32_t priority_base, | ||
| 127 | + uint32_t pending_base, uint32_t enable_base, | ||
| 128 | + uint32_t enable_stride, uint32_t context_base, | ||
| 129 | + uint32_t context_stride, uint32_t aperture_size) | ||
| 130 | { | ||
| 131 | DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC); | ||
| 132 | assert(enable_stride == (enable_stride & -enable_stride)); | ||
| 133 | assert(context_stride == (context_stride & -context_stride)); | ||
| 134 | qdev_prop_set_string(dev, "hart-config", hart_config); | ||
| 135 | + qdev_prop_set_uint32(dev, "hartid-base", hartid_base); | ||
| 136 | qdev_prop_set_uint32(dev, "num-sources", num_sources); | ||
| 137 | qdev_prop_set_uint32(dev, "num-priorities", num_priorities); | ||
| 138 | qdev_prop_set_uint32(dev, "priority-base", priority_base); | ||
| 139 | diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c | ||
| 140 | index XXXXXXX..XXXXXXX 100644 | ||
| 141 | --- a/hw/riscv/sifive_u.c | ||
| 142 | +++ b/hw/riscv/sifive_u.c | ||
| 143 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) | ||
| 144 | |||
| 145 | /* MMIO */ | ||
| 146 | s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base, | ||
| 147 | - plic_hart_config, | ||
| 148 | + plic_hart_config, 0, | ||
| 149 | SIFIVE_U_PLIC_NUM_SOURCES, | ||
| 150 | SIFIVE_U_PLIC_NUM_PRIORITIES, | ||
| 151 | SIFIVE_U_PLIC_PRIORITY_BASE, | ||
| 14 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c | 152 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c |
| 15 | index XXXXXXX..XXXXXXX 100644 | 153 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/hw/riscv/virt.c | 154 | --- a/hw/riscv/virt.c |
| 17 | +++ b/hw/riscv/virt.c | 155 | +++ b/hw/riscv/virt.c |
| 18 | @@ -XXX,XX +XXX,XX @@ | 156 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine) |
| 19 | #include "sysemu/sysemu.h" | 157 | |
| 20 | #include "hw/pci/pci.h" | 158 | /* MMIO */ |
| 21 | #include "hw/pci-host/gpex.h" | 159 | s->plic = sifive_plic_create(memmap[VIRT_PLIC].base, |
| 22 | +#include "hw/display/ramfb.h" | 160 | - plic_hart_config, |
| 23 | 161 | + plic_hart_config, 0, | |
| 24 | static const MemMapEntry virt_memmap[] = { | 162 | VIRT_PLIC_NUM_SOURCES, |
| 25 | [VIRT_DEBUG] = { 0x0, 0x100 }, | 163 | VIRT_PLIC_NUM_PRIORITIES, |
| 26 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data) | 164 | VIRT_PLIC_PRIORITY_BASE, |
| 27 | mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; | ||
| 28 | mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; | ||
| 29 | mc->numa_mem_supported = true; | ||
| 30 | + | ||
| 31 | + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); | ||
| 32 | } | ||
| 33 | |||
| 34 | static const TypeInfo virt_machine_typeinfo = { | ||
| 35 | -- | 165 | -- |
| 36 | 2.30.1 | 166 | 2.28.0 |
| 37 | 167 | ||
| 38 | 168 | diff view generated by jsdifflib |
| 1 | From: Bin Meng <bin.meng@windriver.com> | 1 | From: Anup Patel <anup.patel@wdc.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | This adds the documentation to describe what is supported for the | 3 | We add common helper routines which can be shared by RISC-V |
| 4 | 'microchip-icicle-kit' machine, and how to boot the machine in QEMU. | 4 | multi-socket NUMA machines. |
| 5 | 5 | ||
| 6 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | 6 | We have two types of helpers: |
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 7 | 1. riscv_socket_xyz() - These helper assist managing multiple |
| 8 | Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com | 8 | sockets irrespective whether QEMU NUMA is enabled/disabled |
| 9 | 2. riscv_numa_xyz() - These helpers assist in providing | ||
| 10 | necessary QEMU machine callbacks for QEMU NUMA emulation | ||
| 11 | |||
| 12 | Signed-off-by: Anup Patel <anup.patel@wdc.com> | ||
| 13 | Reviewed-by: Atish Patra <atish.patra@wdc.com> | ||
| 14 | Message-Id: <20200616032229.766089-4-anup.patel@wdc.com> | ||
| 9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 15 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 10 | --- | 16 | --- |
| 11 | docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++++++++++ | 17 | include/hw/riscv/numa.h | 113 +++++++++++++++++++ |
| 12 | docs/system/target-riscv.rst | 1 + | 18 | hw/riscv/numa.c | 242 ++++++++++++++++++++++++++++++++++++++++ |
| 13 | 2 files changed, 90 insertions(+) | 19 | hw/riscv/meson.build | 1 + |
| 14 | create mode 100644 docs/system/riscv/microchip-icicle-kit.rst | 20 | 3 files changed, 356 insertions(+) |
| 15 | 21 | create mode 100644 include/hw/riscv/numa.h | |
| 16 | diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst | 22 | create mode 100644 hw/riscv/numa.c |
| 23 | |||
| 24 | diff --git a/include/hw/riscv/numa.h b/include/hw/riscv/numa.h | ||
| 17 | new file mode 100644 | 25 | new file mode 100644 |
| 18 | index XXXXXXX..XXXXXXX | 26 | index XXXXXXX..XXXXXXX |
| 19 | --- /dev/null | 27 | --- /dev/null |
| 20 | +++ b/docs/system/riscv/microchip-icicle-kit.rst | 28 | +++ b/include/hw/riscv/numa.h |
| 21 | @@ -XXX,XX +XXX,XX @@ | 29 | @@ -XXX,XX +XXX,XX @@ |
| 22 | +Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``) | 30 | +/* |
| 23 | +============================================================= | 31 | + * QEMU RISC-V NUMA Helper |
| 24 | + | 32 | + * |
| 25 | +Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one | 33 | + * Copyright (c) 2020 Western Digital Corporation or its affiliates. |
| 26 | +SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA. | 34 | + * |
| 27 | + | 35 | + * This program is free software; you can redistribute it and/or modify it |
| 28 | +For more details about Microchip PolarFire SoC, please see: | 36 | + * under the terms and conditions of the GNU General Public License, |
| 29 | +https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga | 37 | + * version 2 or later, as published by the Free Software Foundation. |
| 30 | + | 38 | + * |
| 31 | +The Icicle Kit board information can be found here: | 39 | + * This program is distributed in the hope it will be useful, but WITHOUT |
| 32 | +https://www.microsemi.com/existing-parts/parts/152514 | 40 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 33 | + | 41 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 34 | +Supported devices | 42 | + * more details. |
| 35 | +----------------- | 43 | + * |
| 36 | + | 44 | + * You should have received a copy of the GNU General Public License along with |
| 37 | +The ``microchip-icicle-kit`` machine supports the following devices: | 45 | + * this program. If not, see <http://www.gnu.org/licenses/>. |
| 38 | + | 46 | + */ |
| 39 | + * 1 E51 core | 47 | + |
| 40 | + * 4 U54 cores | 48 | +#ifndef RISCV_NUMA_H |
| 41 | + * Core Level Interruptor (CLINT) | 49 | +#define RISCV_NUMA_H |
| 42 | + * Platform-Level Interrupt Controller (PLIC) | 50 | + |
| 43 | + * L2 Loosely Integrated Memory (L2-LIM) | 51 | +#include "hw/sysbus.h" |
| 44 | + * DDR memory controller | 52 | +#include "sysemu/numa.h" |
| 45 | + * 5 MMUARTs | 53 | + |
| 46 | + * 1 DMA controller | 54 | +/** |
| 47 | + * 2 GEM Ethernet controllers | 55 | + * riscv_socket_count: |
| 48 | + * 1 SDHC storage controller | 56 | + * @ms: pointer to machine state |
| 49 | + | 57 | + * |
| 50 | +Boot options | 58 | + * Returns: number of sockets for a numa system and 1 for a non-numa system |
| 51 | +------------ | 59 | + */ |
| 52 | + | 60 | +int riscv_socket_count(const MachineState *ms); |
| 53 | +The ``microchip-icicle-kit`` machine can start using the standard -bios | 61 | + |
| 54 | +functionality for loading its BIOS image, aka Hart Software Services (HSS_). | 62 | +/** |
| 55 | +HSS loads the second stage bootloader U-Boot from an SD card. It does not | 63 | + * riscv_socket_first_hartid: |
| 56 | +support direct kernel loading via the -kernel option. One has to load kernel | 64 | + * @ms: pointer to machine state |
| 57 | +from U-Boot. | 65 | + * @socket_id: socket index |
| 58 | + | 66 | + * |
| 59 | +The memory is set to 1537 MiB by default which is the minimum required high | 67 | + * Returns: first hartid for a valid socket and -1 for an invalid socket |
| 60 | +memory size by HSS. A sanity check on ram size is performed in the machine | 68 | + */ |
| 61 | +init routine to prompt user to increase the RAM size to > 1537 MiB when less | 69 | +int riscv_socket_first_hartid(const MachineState *ms, int socket_id); |
| 62 | +than 1537 MiB ram is detected. | 70 | + |
| 63 | + | 71 | +/** |
| 64 | +Boot the machine | 72 | + * riscv_socket_last_hartid: |
| 65 | +---------------- | 73 | + * @ms: pointer to machine state |
| 66 | + | 74 | + * @socket_id: socket index |
| 67 | +HSS 2020.12 release is tested at the time of writing. To build an HSS image | 75 | + * |
| 68 | +that can be booted by the ``microchip-icicle-kit`` machine, type the following | 76 | + * Returns: last hartid for a valid socket and -1 for an invalid socket |
| 69 | +in the HSS source tree: | 77 | + */ |
| 70 | + | 78 | +int riscv_socket_last_hartid(const MachineState *ms, int socket_id); |
| 71 | +.. code-block:: bash | 79 | + |
| 72 | + | 80 | +/** |
| 73 | + $ export CROSS_COMPILE=riscv64-linux- | 81 | + * riscv_socket_hart_count: |
| 74 | + $ cp boards/mpfs-icicle-kit-es/def_config .config | 82 | + * @ms: pointer to machine state |
| 75 | + $ make BOARD=mpfs-icicle-kit-es | 83 | + * @socket_id: socket index |
| 76 | + | 84 | + * |
| 77 | +Download the official SD card image released by Microchip and prepare it for | 85 | + * Returns: number of harts for a valid socket and -1 for an invalid socket |
| 78 | +QEMU usage: | 86 | + */ |
| 79 | + | 87 | +int riscv_socket_hart_count(const MachineState *ms, int socket_id); |
| 80 | +.. code-block:: bash | 88 | + |
| 81 | + | 89 | +/** |
| 82 | + $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz | 90 | + * riscv_socket_mem_offset: |
| 83 | + $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz | 91 | + * @ms: pointer to machine state |
| 84 | + $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G | 92 | + * @socket_id: socket index |
| 85 | + | 93 | + * |
| 86 | +Then we can boot the machine by: | 94 | + * Returns: offset of ram belonging to given socket |
| 87 | + | 95 | + */ |
| 88 | +.. code-block:: bash | 96 | +uint64_t riscv_socket_mem_offset(const MachineState *ms, int socket_id); |
| 89 | + | 97 | + |
| 90 | + $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \ | 98 | +/** |
| 91 | + -bios path/to/hss.bin -sd path/to/sdcard.img \ | 99 | + * riscv_socket_mem_size: |
| 92 | + -nic user,model=cadence_gem \ | 100 | + * @ms: pointer to machine state |
| 93 | + -nic tap,ifname=tap,model=cadence_gem,script=no \ | 101 | + * @socket_id: socket index |
| 94 | + -display none -serial stdio \ | 102 | + * |
| 95 | + -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \ | 103 | + * Returns: size of ram belonging to given socket |
| 96 | + -serial chardev:serial1 | 104 | + */ |
| 97 | + | 105 | +uint64_t riscv_socket_mem_size(const MachineState *ms, int socket_id); |
| 98 | +With above command line, current terminal session will be used for the first | 106 | + |
| 99 | +serial port. Open another terminal window, and use `minicom` to connect the | 107 | +/** |
| 100 | +second serial port. | 108 | + * riscv_socket_check_hartids: |
| 101 | + | 109 | + * @ms: pointer to machine state |
| 102 | +.. code-block:: bash | 110 | + * @socket_id: socket index |
| 103 | + | 111 | + * |
| 104 | + $ minicom -D unix\#serial1.sock | 112 | + * Returns: true if hardids belonging to given socket are contiguous else false |
| 105 | + | 113 | + */ |
| 106 | +HSS output is on the first serial port (stdio) and U-Boot outputs on the | 114 | +bool riscv_socket_check_hartids(const MachineState *ms, int socket_id); |
| 107 | +second serial port. U-Boot will automatically load the Linux kernel from | 115 | + |
| 108 | +the SD card image. | 116 | +/** |
| 109 | + | 117 | + * riscv_socket_fdt_write_id: |
| 110 | +.. _HSS: https://github.com/polarfire-soc/hart-software-services | 118 | + * @ms: pointer to machine state |
| 111 | diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst | 119 | + * @socket_id: socket index |
| 120 | + * | ||
| 121 | + * Write NUMA node-id FDT property for given FDT node | ||
| 122 | + */ | ||
| 123 | +void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt, | ||
| 124 | + const char *node_name, int socket_id); | ||
| 125 | + | ||
| 126 | +/** | ||
| 127 | + * riscv_socket_fdt_write_distance_matrix: | ||
| 128 | + * @ms: pointer to machine state | ||
| 129 | + * @socket_id: socket index | ||
| 130 | + * | ||
| 131 | + * Write NUMA distance matrix in FDT for given machine | ||
| 132 | + */ | ||
| 133 | +void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt); | ||
| 134 | + | ||
| 135 | +CpuInstanceProperties | ||
| 136 | +riscv_numa_cpu_index_to_props(MachineState *ms, unsigned cpu_index); | ||
| 137 | + | ||
| 138 | +int64_t riscv_numa_get_default_cpu_node_id(const MachineState *ms, int idx); | ||
| 139 | + | ||
| 140 | +const CPUArchIdList *riscv_numa_possible_cpu_arch_ids(MachineState *ms); | ||
| 141 | + | ||
| 142 | +#endif /* RISCV_NUMA_H */ | ||
| 143 | diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c | ||
| 144 | new file mode 100644 | ||
| 145 | index XXXXXXX..XXXXXXX | ||
| 146 | --- /dev/null | ||
| 147 | +++ b/hw/riscv/numa.c | ||
| 148 | @@ -XXX,XX +XXX,XX @@ | ||
| 149 | +/* | ||
| 150 | + * QEMU RISC-V NUMA Helper | ||
| 151 | + * | ||
| 152 | + * Copyright (c) 2020 Western Digital Corporation or its affiliates. | ||
| 153 | + * | ||
| 154 | + * This program is free software; you can redistribute it and/or modify it | ||
| 155 | + * under the terms and conditions of the GNU General Public License, | ||
| 156 | + * version 2 or later, as published by the Free Software Foundation. | ||
| 157 | + * | ||
| 158 | + * This program is distributed in the hope it will be useful, but WITHOUT | ||
| 159 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 160 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 161 | + * more details. | ||
| 162 | + * | ||
| 163 | + * You should have received a copy of the GNU General Public License along with | ||
| 164 | + * this program. If not, see <http://www.gnu.org/licenses/>. | ||
| 165 | + */ | ||
| 166 | + | ||
| 167 | +#include "qemu/osdep.h" | ||
| 168 | +#include "qemu/units.h" | ||
| 169 | +#include "qemu/log.h" | ||
| 170 | +#include "qemu/error-report.h" | ||
| 171 | +#include "qapi/error.h" | ||
| 172 | +#include "hw/boards.h" | ||
| 173 | +#include "hw/qdev-properties.h" | ||
| 174 | +#include "hw/riscv/numa.h" | ||
| 175 | +#include "sysemu/device_tree.h" | ||
| 176 | + | ||
| 177 | +static bool numa_enabled(const MachineState *ms) | ||
| 178 | +{ | ||
| 179 | + return (ms->numa_state && ms->numa_state->num_nodes) ? true : false; | ||
| 180 | +} | ||
| 181 | + | ||
| 182 | +int riscv_socket_count(const MachineState *ms) | ||
| 183 | +{ | ||
| 184 | + return (numa_enabled(ms)) ? ms->numa_state->num_nodes : 1; | ||
| 185 | +} | ||
| 186 | + | ||
| 187 | +int riscv_socket_first_hartid(const MachineState *ms, int socket_id) | ||
| 188 | +{ | ||
| 189 | + int i, first_hartid = ms->smp.cpus; | ||
| 190 | + | ||
| 191 | + if (!numa_enabled(ms)) { | ||
| 192 | + return (!socket_id) ? 0 : -1; | ||
| 193 | + } | ||
| 194 | + | ||
| 195 | + for (i = 0; i < ms->smp.cpus; i++) { | ||
| 196 | + if (ms->possible_cpus->cpus[i].props.node_id != socket_id) { | ||
| 197 | + continue; | ||
| 198 | + } | ||
| 199 | + if (i < first_hartid) { | ||
| 200 | + first_hartid = i; | ||
| 201 | + } | ||
| 202 | + } | ||
| 203 | + | ||
| 204 | + return (first_hartid < ms->smp.cpus) ? first_hartid : -1; | ||
| 205 | +} | ||
| 206 | + | ||
| 207 | +int riscv_socket_last_hartid(const MachineState *ms, int socket_id) | ||
| 208 | +{ | ||
| 209 | + int i, last_hartid = -1; | ||
| 210 | + | ||
| 211 | + if (!numa_enabled(ms)) { | ||
| 212 | + return (!socket_id) ? ms->smp.cpus - 1 : -1; | ||
| 213 | + } | ||
| 214 | + | ||
| 215 | + for (i = 0; i < ms->smp.cpus; i++) { | ||
| 216 | + if (ms->possible_cpus->cpus[i].props.node_id != socket_id) { | ||
| 217 | + continue; | ||
| 218 | + } | ||
| 219 | + if (i > last_hartid) { | ||
| 220 | + last_hartid = i; | ||
| 221 | + } | ||
| 222 | + } | ||
| 223 | + | ||
| 224 | + return (last_hartid < ms->smp.cpus) ? last_hartid : -1; | ||
| 225 | +} | ||
| 226 | + | ||
| 227 | +int riscv_socket_hart_count(const MachineState *ms, int socket_id) | ||
| 228 | +{ | ||
| 229 | + int first_hartid, last_hartid; | ||
| 230 | + | ||
| 231 | + if (!numa_enabled(ms)) { | ||
| 232 | + return (!socket_id) ? ms->smp.cpus : -1; | ||
| 233 | + } | ||
| 234 | + | ||
| 235 | + first_hartid = riscv_socket_first_hartid(ms, socket_id); | ||
| 236 | + if (first_hartid < 0) { | ||
| 237 | + return -1; | ||
| 238 | + } | ||
| 239 | + | ||
| 240 | + last_hartid = riscv_socket_last_hartid(ms, socket_id); | ||
| 241 | + if (last_hartid < 0) { | ||
| 242 | + return -1; | ||
| 243 | + } | ||
| 244 | + | ||
| 245 | + if (first_hartid > last_hartid) { | ||
| 246 | + return -1; | ||
| 247 | + } | ||
| 248 | + | ||
| 249 | + return last_hartid - first_hartid + 1; | ||
| 250 | +} | ||
| 251 | + | ||
| 252 | +bool riscv_socket_check_hartids(const MachineState *ms, int socket_id) | ||
| 253 | +{ | ||
| 254 | + int i, first_hartid, last_hartid; | ||
| 255 | + | ||
| 256 | + if (!numa_enabled(ms)) { | ||
| 257 | + return (!socket_id) ? true : false; | ||
| 258 | + } | ||
| 259 | + | ||
| 260 | + first_hartid = riscv_socket_first_hartid(ms, socket_id); | ||
| 261 | + if (first_hartid < 0) { | ||
| 262 | + return false; | ||
| 263 | + } | ||
| 264 | + | ||
| 265 | + last_hartid = riscv_socket_last_hartid(ms, socket_id); | ||
| 266 | + if (last_hartid < 0) { | ||
| 267 | + return false; | ||
| 268 | + } | ||
| 269 | + | ||
| 270 | + for (i = first_hartid; i <= last_hartid; i++) { | ||
| 271 | + if (ms->possible_cpus->cpus[i].props.node_id != socket_id) { | ||
| 272 | + return false; | ||
| 273 | + } | ||
| 274 | + } | ||
| 275 | + | ||
| 276 | + return true; | ||
| 277 | +} | ||
| 278 | + | ||
| 279 | +uint64_t riscv_socket_mem_offset(const MachineState *ms, int socket_id) | ||
| 280 | +{ | ||
| 281 | + int i; | ||
| 282 | + uint64_t mem_offset = 0; | ||
| 283 | + | ||
| 284 | + if (!numa_enabled(ms)) { | ||
| 285 | + return 0; | ||
| 286 | + } | ||
| 287 | + | ||
| 288 | + for (i = 0; i < ms->numa_state->num_nodes; i++) { | ||
| 289 | + if (i == socket_id) { | ||
| 290 | + break; | ||
| 291 | + } | ||
| 292 | + mem_offset += ms->numa_state->nodes[i].node_mem; | ||
| 293 | + } | ||
| 294 | + | ||
| 295 | + return (i == socket_id) ? mem_offset : 0; | ||
| 296 | +} | ||
| 297 | + | ||
| 298 | +uint64_t riscv_socket_mem_size(const MachineState *ms, int socket_id) | ||
| 299 | +{ | ||
| 300 | + if (!numa_enabled(ms)) { | ||
| 301 | + return (!socket_id) ? ms->ram_size : 0; | ||
| 302 | + } | ||
| 303 | + | ||
| 304 | + return (socket_id < ms->numa_state->num_nodes) ? | ||
| 305 | + ms->numa_state->nodes[socket_id].node_mem : 0; | ||
| 306 | +} | ||
| 307 | + | ||
| 308 | +void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt, | ||
| 309 | + const char *node_name, int socket_id) | ||
| 310 | +{ | ||
| 311 | + if (numa_enabled(ms)) { | ||
| 312 | + qemu_fdt_setprop_cell(fdt, node_name, "numa-node-id", socket_id); | ||
| 313 | + } | ||
| 314 | +} | ||
| 315 | + | ||
| 316 | +void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt) | ||
| 317 | +{ | ||
| 318 | + int i, j, idx; | ||
| 319 | + uint32_t *dist_matrix, dist_matrix_size; | ||
| 320 | + | ||
| 321 | + if (numa_enabled(ms) && ms->numa_state->have_numa_distance) { | ||
| 322 | + dist_matrix_size = riscv_socket_count(ms) * riscv_socket_count(ms); | ||
| 323 | + dist_matrix_size *= (3 * sizeof(uint32_t)); | ||
| 324 | + dist_matrix = g_malloc0(dist_matrix_size); | ||
| 325 | + | ||
| 326 | + for (i = 0; i < riscv_socket_count(ms); i++) { | ||
| 327 | + for (j = 0; j < riscv_socket_count(ms); j++) { | ||
| 328 | + idx = (i * riscv_socket_count(ms) + j) * 3; | ||
| 329 | + dist_matrix[idx + 0] = cpu_to_be32(i); | ||
| 330 | + dist_matrix[idx + 1] = cpu_to_be32(j); | ||
| 331 | + dist_matrix[idx + 2] = | ||
| 332 | + cpu_to_be32(ms->numa_state->nodes[i].distance[j]); | ||
| 333 | + } | ||
| 334 | + } | ||
| 335 | + | ||
| 336 | + qemu_fdt_add_subnode(fdt, "/distance-map"); | ||
| 337 | + qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", | ||
| 338 | + "numa-distance-map-v1"); | ||
| 339 | + qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", | ||
| 340 | + dist_matrix, dist_matrix_size); | ||
| 341 | + g_free(dist_matrix); | ||
| 342 | + } | ||
| 343 | +} | ||
| 344 | + | ||
| 345 | +CpuInstanceProperties | ||
| 346 | +riscv_numa_cpu_index_to_props(MachineState *ms, unsigned cpu_index) | ||
| 347 | +{ | ||
| 348 | + MachineClass *mc = MACHINE_GET_CLASS(ms); | ||
| 349 | + const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); | ||
| 350 | + | ||
| 351 | + assert(cpu_index < possible_cpus->len); | ||
| 352 | + return possible_cpus->cpus[cpu_index].props; | ||
| 353 | +} | ||
| 354 | + | ||
| 355 | +int64_t riscv_numa_get_default_cpu_node_id(const MachineState *ms, int idx) | ||
| 356 | +{ | ||
| 357 | + int64_t nidx = 0; | ||
| 358 | + | ||
| 359 | + if (ms->numa_state->num_nodes) { | ||
| 360 | + nidx = idx / (ms->smp.cpus / ms->numa_state->num_nodes); | ||
| 361 | + if (ms->numa_state->num_nodes <= nidx) { | ||
| 362 | + nidx = ms->numa_state->num_nodes - 1; | ||
| 363 | + } | ||
| 364 | + } | ||
| 365 | + | ||
| 366 | + return nidx; | ||
| 367 | +} | ||
| 368 | + | ||
| 369 | +const CPUArchIdList *riscv_numa_possible_cpu_arch_ids(MachineState *ms) | ||
| 370 | +{ | ||
| 371 | + int n; | ||
| 372 | + unsigned int max_cpus = ms->smp.max_cpus; | ||
| 373 | + | ||
| 374 | + if (ms->possible_cpus) { | ||
| 375 | + assert(ms->possible_cpus->len == max_cpus); | ||
| 376 | + return ms->possible_cpus; | ||
| 377 | + } | ||
| 378 | + | ||
| 379 | + ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + | ||
| 380 | + sizeof(CPUArchId) * max_cpus); | ||
| 381 | + ms->possible_cpus->len = max_cpus; | ||
| 382 | + for (n = 0; n < ms->possible_cpus->len; n++) { | ||
| 383 | + ms->possible_cpus->cpus[n].type = ms->cpu_type; | ||
| 384 | + ms->possible_cpus->cpus[n].arch_id = n; | ||
| 385 | + ms->possible_cpus->cpus[n].props.has_core_id = true; | ||
| 386 | + ms->possible_cpus->cpus[n].props.core_id = n; | ||
| 387 | + } | ||
| 388 | + | ||
| 389 | + return ms->possible_cpus; | ||
| 390 | +} | ||
| 391 | diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build | ||
| 112 | index XXXXXXX..XXXXXXX 100644 | 392 | index XXXXXXX..XXXXXXX 100644 |
| 113 | --- a/docs/system/target-riscv.rst | 393 | --- a/hw/riscv/meson.build |
| 114 | +++ b/docs/system/target-riscv.rst | 394 | +++ b/hw/riscv/meson.build |
| 115 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running | 395 | @@ -XXX,XX +XXX,XX @@ |
| 116 | .. toctree:: | 396 | riscv_ss = ss.source_set() |
| 117 | :maxdepth: 1 | 397 | riscv_ss.add(files('boot.c')) |
| 118 | 398 | +riscv_ss.add(files('numa.c')) | |
| 119 | + riscv/microchip-icicle-kit | 399 | riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c')) |
| 120 | riscv/sifive_u | 400 | riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) |
| 121 | 401 | riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) | |
| 122 | RISC-V CPU features | ||
| 123 | -- | 402 | -- |
| 124 | 2.30.1 | 403 | 2.28.0 |
| 125 | 404 | ||
| 126 | 405 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | 1 | From: Anup Patel <anup.patel@wdc.com> | |
| 2 | |||
| 3 | We extend RISC-V spike machine to allow creating a multi-socket | ||
| 4 | machine. Each RISC-V spike machine socket is a NUMA node having | ||
| 5 | a set of HARTs, a memory instance, and a CLINT instance. Other | ||
| 6 | devices are shared between all sockets. We also update the | ||
| 7 | generated device tree accordingly. | ||
| 8 | |||
| 9 | By default, NUMA multi-socket support is disabled for RISC-V spike | ||
| 10 | machine. To enable it, users can use "-numa" command-line options | ||
| 11 | of QEMU. | ||
| 12 | |||
| 13 | Example1: For two NUMA nodes with 2 CPUs each, append following | ||
| 14 | to command-line options: "-smp 4 -numa node -numa node" | ||
| 15 | |||
| 16 | Example2: For two NUMA nodes with 1 and 3 CPUs, append following | ||
| 17 | to command-line options: | ||
| 18 | "-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \ | ||
| 19 | -numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \ | ||
| 20 | -numa cpu,node-id=1,core-id=3" | ||
| 21 | |||
| 22 | The maximum number of sockets in a RISC-V spike machine is 8 | ||
| 23 | but this limit can be changed in future. | ||
| 24 | |||
| 25 | Signed-off-by: Anup Patel <anup.patel@wdc.com> | ||
| 26 | Reviewed-by: Atish Patra <atish.patra@wdc.com> | ||
| 27 | Message-Id: <20200616032229.766089-5-anup.patel@wdc.com> | ||
| 28 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 29 | --- | ||
| 30 | include/hw/riscv/spike.h | 11 +- | ||
| 31 | hw/riscv/spike.c | 232 ++++++++++++++++++++++++++------------- | ||
| 32 | 2 files changed, 167 insertions(+), 76 deletions(-) | ||
| 33 | |||
| 34 | diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h | ||
| 35 | index XXXXXXX..XXXXXXX 100644 | ||
| 36 | --- a/include/hw/riscv/spike.h | ||
| 37 | +++ b/include/hw/riscv/spike.h | ||
| 38 | @@ -XXX,XX +XXX,XX @@ | ||
| 39 | #include "hw/riscv/riscv_hart.h" | ||
| 40 | #include "hw/sysbus.h" | ||
| 41 | |||
| 42 | +#define SPIKE_CPUS_MAX 8 | ||
| 43 | +#define SPIKE_SOCKETS_MAX 8 | ||
| 44 | + | ||
| 45 | +#define TYPE_SPIKE_MACHINE MACHINE_TYPE_NAME("spike") | ||
| 46 | +#define SPIKE_MACHINE(obj) \ | ||
| 47 | + OBJECT_CHECK(SpikeState, (obj), TYPE_SPIKE_MACHINE) | ||
| 48 | + | ||
| 49 | typedef struct { | ||
| 50 | /*< private >*/ | ||
| 51 | - SysBusDevice parent_obj; | ||
| 52 | + MachineState parent; | ||
| 53 | |||
| 54 | /*< public >*/ | ||
| 55 | - RISCVHartArrayState soc; | ||
| 56 | + RISCVHartArrayState soc[SPIKE_SOCKETS_MAX]; | ||
| 57 | void *fdt; | ||
| 58 | int fdt_size; | ||
| 59 | } SpikeState; | ||
| 60 | diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c | ||
| 61 | index XXXXXXX..XXXXXXX 100644 | ||
| 62 | --- a/hw/riscv/spike.c | ||
| 63 | +++ b/hw/riscv/spike.c | ||
| 64 | @@ -XXX,XX +XXX,XX @@ | ||
| 65 | #include "hw/riscv/sifive_clint.h" | ||
| 66 | #include "hw/riscv/spike.h" | ||
| 67 | #include "hw/riscv/boot.h" | ||
| 68 | +#include "hw/riscv/numa.h" | ||
| 69 | #include "chardev/char.h" | ||
| 70 | #include "sysemu/arch_init.h" | ||
| 71 | #include "sysemu/device_tree.h" | ||
| 72 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, | ||
| 73 | uint64_t mem_size, const char *cmdline) | ||
| 74 | { | ||
| 75 | void *fdt; | ||
| 76 | - int cpu; | ||
| 77 | - uint32_t *cells; | ||
| 78 | - char *nodename; | ||
| 79 | + uint64_t addr, size; | ||
| 80 | + unsigned long clint_addr; | ||
| 81 | + int cpu, socket; | ||
| 82 | + MachineState *mc = MACHINE(s); | ||
| 83 | + uint32_t *clint_cells; | ||
| 84 | + uint32_t cpu_phandle, intc_phandle, phandle = 1; | ||
| 85 | + char *name, *mem_name, *clint_name, *clust_name; | ||
| 86 | + char *core_name, *cpu_name, *intc_name; | ||
| 87 | |||
| 88 | fdt = s->fdt = create_device_tree(&s->fdt_size); | ||
| 89 | if (!fdt) { | ||
| 90 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, | ||
| 91 | qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); | ||
| 92 | qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); | ||
| 93 | |||
| 94 | - nodename = g_strdup_printf("/memory@%lx", | ||
| 95 | - (long)memmap[SPIKE_DRAM].base); | ||
| 96 | - qemu_fdt_add_subnode(fdt, nodename); | ||
| 97 | - qemu_fdt_setprop_cells(fdt, nodename, "reg", | ||
| 98 | - memmap[SPIKE_DRAM].base >> 32, memmap[SPIKE_DRAM].base, | ||
| 99 | - mem_size >> 32, mem_size); | ||
| 100 | - qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); | ||
| 101 | - g_free(nodename); | ||
| 102 | - | ||
| 103 | qemu_fdt_add_subnode(fdt, "/cpus"); | ||
| 104 | qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", | ||
| 105 | SIFIVE_CLINT_TIMEBASE_FREQ); | ||
| 106 | qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); | ||
| 107 | qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); | ||
| 108 | + qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); | ||
| 109 | + | ||
| 110 | + for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { | ||
| 111 | + clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); | ||
| 112 | + qemu_fdt_add_subnode(fdt, clust_name); | ||
| 113 | + | ||
| 114 | + clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); | ||
| 115 | |||
| 116 | - for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) { | ||
| 117 | - nodename = g_strdup_printf("/cpus/cpu@%d", cpu); | ||
| 118 | - char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | ||
| 119 | - char *isa = riscv_isa_string(&s->soc.harts[cpu]); | ||
| 120 | - qemu_fdt_add_subnode(fdt, nodename); | ||
| 121 | + for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { | ||
| 122 | + cpu_phandle = phandle++; | ||
| 123 | + | ||
| 124 | + cpu_name = g_strdup_printf("/cpus/cpu@%d", | ||
| 125 | + s->soc[socket].hartid_base + cpu); | ||
| 126 | + qemu_fdt_add_subnode(fdt, cpu_name); | ||
| 127 | #if defined(TARGET_RISCV32) | ||
| 128 | - qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); | ||
| 129 | + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); | ||
| 130 | #else | ||
| 131 | - qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); | ||
| 132 | + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); | ||
| 133 | #endif | ||
| 134 | - qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); | ||
| 135 | - qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); | ||
| 136 | - qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); | ||
| 137 | - qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); | ||
| 138 | - qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); | ||
| 139 | - qemu_fdt_add_subnode(fdt, intc); | ||
| 140 | - qemu_fdt_setprop_cell(fdt, intc, "phandle", 1); | ||
| 141 | - qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); | ||
| 142 | - qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); | ||
| 143 | - qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); | ||
| 144 | - g_free(isa); | ||
| 145 | - g_free(intc); | ||
| 146 | - g_free(nodename); | ||
| 147 | - } | ||
| 148 | + name = riscv_isa_string(&s->soc[socket].harts[cpu]); | ||
| 149 | + qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); | ||
| 150 | + g_free(name); | ||
| 151 | + qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); | ||
| 152 | + qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); | ||
| 153 | + qemu_fdt_setprop_cell(fdt, cpu_name, "reg", | ||
| 154 | + s->soc[socket].hartid_base + cpu); | ||
| 155 | + qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); | ||
| 156 | + riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); | ||
| 157 | + qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); | ||
| 158 | |||
| 159 | - cells = g_new0(uint32_t, s->soc.num_harts * 4); | ||
| 160 | - for (cpu = 0; cpu < s->soc.num_harts; cpu++) { | ||
| 161 | - nodename = | ||
| 162 | - g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | ||
| 163 | - uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); | ||
| 164 | - cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | ||
| 165 | - cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); | ||
| 166 | - cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); | ||
| 167 | - cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); | ||
| 168 | - g_free(nodename); | ||
| 169 | + intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); | ||
| 170 | + qemu_fdt_add_subnode(fdt, intc_name); | ||
| 171 | + intc_phandle = phandle++; | ||
| 172 | + qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle); | ||
| 173 | + qemu_fdt_setprop_string(fdt, intc_name, "compatible", | ||
| 174 | + "riscv,cpu-intc"); | ||
| 175 | + qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); | ||
| 176 | + qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); | ||
| 177 | + | ||
| 178 | + clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | ||
| 179 | + clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); | ||
| 180 | + clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); | ||
| 181 | + clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); | ||
| 182 | + | ||
| 183 | + core_name = g_strdup_printf("%s/core%d", clust_name, cpu); | ||
| 184 | + qemu_fdt_add_subnode(fdt, core_name); | ||
| 185 | + qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); | ||
| 186 | + | ||
| 187 | + g_free(core_name); | ||
| 188 | + g_free(intc_name); | ||
| 189 | + g_free(cpu_name); | ||
| 190 | + } | ||
| 191 | + | ||
| 192 | + addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket); | ||
| 193 | + size = riscv_socket_mem_size(mc, socket); | ||
| 194 | + mem_name = g_strdup_printf("/memory@%lx", (long)addr); | ||
| 195 | + qemu_fdt_add_subnode(fdt, mem_name); | ||
| 196 | + qemu_fdt_setprop_cells(fdt, mem_name, "reg", | ||
| 197 | + addr >> 32, addr, size >> 32, size); | ||
| 198 | + qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); | ||
| 199 | + riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); | ||
| 200 | + g_free(mem_name); | ||
| 201 | + | ||
| 202 | + clint_addr = memmap[SPIKE_CLINT].base + | ||
| 203 | + (memmap[SPIKE_CLINT].size * socket); | ||
| 204 | + clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); | ||
| 205 | + qemu_fdt_add_subnode(fdt, clint_name); | ||
| 206 | + qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0"); | ||
| 207 | + qemu_fdt_setprop_cells(fdt, clint_name, "reg", | ||
| 208 | + 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); | ||
| 209 | + qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", | ||
| 210 | + clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); | ||
| 211 | + riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); | ||
| 212 | + | ||
| 213 | + g_free(clint_name); | ||
| 214 | + g_free(clint_cells); | ||
| 215 | + g_free(clust_name); | ||
| 216 | } | ||
| 217 | - nodename = g_strdup_printf("/soc/clint@%lx", | ||
| 218 | - (long)memmap[SPIKE_CLINT].base); | ||
| 219 | - qemu_fdt_add_subnode(fdt, nodename); | ||
| 220 | - qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); | ||
| 221 | - qemu_fdt_setprop_cells(fdt, nodename, "reg", | ||
| 222 | - 0x0, memmap[SPIKE_CLINT].base, | ||
| 223 | - 0x0, memmap[SPIKE_CLINT].size); | ||
| 224 | - qemu_fdt_setprop(fdt, nodename, "interrupts-extended", | ||
| 225 | - cells, s->soc.num_harts * sizeof(uint32_t) * 4); | ||
| 226 | - g_free(cells); | ||
| 227 | - g_free(nodename); | ||
| 228 | + | ||
| 229 | + riscv_socket_fdt_write_distance_matrix(mc, fdt); | ||
| 230 | |||
| 231 | if (cmdline) { | ||
| 232 | qemu_fdt_add_subnode(fdt, "/chosen"); | ||
| 233 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, | ||
| 234 | static void spike_board_init(MachineState *machine) | ||
| 235 | { | ||
| 236 | const struct MemmapEntry *memmap = spike_memmap; | ||
| 237 | - | ||
| 238 | - SpikeState *s = g_new0(SpikeState, 1); | ||
| 239 | + SpikeState *s = SPIKE_MACHINE(machine); | ||
| 240 | MemoryRegion *system_memory = get_system_memory(); | ||
| 241 | MemoryRegion *main_mem = g_new(MemoryRegion, 1); | ||
| 242 | MemoryRegion *mask_rom = g_new(MemoryRegion, 1); | ||
| 243 | - unsigned int smp_cpus = machine->smp.cpus; | ||
| 244 | uint32_t fdt_load_addr; | ||
| 245 | uint64_t kernel_entry; | ||
| 246 | + char *soc_name; | ||
| 247 | + int i, base_hartid, hart_count; | ||
| 248 | |||
| 249 | - /* Initialize SOC */ | ||
| 250 | - object_initialize_child(OBJECT(machine), "soc", &s->soc, | ||
| 251 | - TYPE_RISCV_HART_ARRAY); | ||
| 252 | - object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, | ||
| 253 | - &error_abort); | ||
| 254 | - object_property_set_int(OBJECT(&s->soc), "num-harts", smp_cpus, | ||
| 255 | - &error_abort); | ||
| 256 | - sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort); | ||
| 257 | + /* Check socket count limit */ | ||
| 258 | + if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) { | ||
| 259 | + error_report("number of sockets/nodes should be less than %d", | ||
| 260 | + SPIKE_SOCKETS_MAX); | ||
| 261 | + exit(1); | ||
| 262 | + } | ||
| 263 | + | ||
| 264 | + /* Initialize sockets */ | ||
| 265 | + for (i = 0; i < riscv_socket_count(machine); i++) { | ||
| 266 | + if (!riscv_socket_check_hartids(machine, i)) { | ||
| 267 | + error_report("discontinuous hartids in socket%d", i); | ||
| 268 | + exit(1); | ||
| 269 | + } | ||
| 270 | + | ||
| 271 | + base_hartid = riscv_socket_first_hartid(machine, i); | ||
| 272 | + if (base_hartid < 0) { | ||
| 273 | + error_report("can't find hartid base for socket%d", i); | ||
| 274 | + exit(1); | ||
| 275 | + } | ||
| 276 | + | ||
| 277 | + hart_count = riscv_socket_hart_count(machine, i); | ||
| 278 | + if (hart_count < 0) { | ||
| 279 | + error_report("can't find hart count for socket%d", i); | ||
| 280 | + exit(1); | ||
| 281 | + } | ||
| 282 | + | ||
| 283 | + soc_name = g_strdup_printf("soc%d", i); | ||
| 284 | + object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], | ||
| 285 | + TYPE_RISCV_HART_ARRAY); | ||
| 286 | + g_free(soc_name); | ||
| 287 | + object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", | ||
| 288 | + machine->cpu_type, &error_abort); | ||
| 289 | + object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", | ||
| 290 | + base_hartid, &error_abort); | ||
| 291 | + object_property_set_int(OBJECT(&s->soc[i]), "num-harts", | ||
| 292 | + hart_count, &error_abort); | ||
| 293 | + sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); | ||
| 294 | + | ||
| 295 | + /* Core Local Interruptor (timer and IPI) for each socket */ | ||
| 296 | + sifive_clint_create( | ||
| 297 | + memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size, | ||
| 298 | + memmap[SPIKE_CLINT].size, base_hartid, hart_count, | ||
| 299 | + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); | ||
| 300 | + } | ||
| 301 | |||
| 302 | /* register system main memory (actual RAM) */ | ||
| 303 | memory_region_init_ram(main_mem, NULL, "riscv.spike.ram", | ||
| 304 | @@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine) | ||
| 305 | fdt_load_addr, s->fdt); | ||
| 306 | |||
| 307 | /* initialize HTIF using symbols found in load_kernel */ | ||
| 308 | - htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0)); | ||
| 309 | + htif_mm_init(system_memory, mask_rom, | ||
| 310 | + &s->soc[0].harts[0].env, serial_hd(0)); | ||
| 311 | +} | ||
| 312 | |||
| 313 | - /* Core Local Interruptor (timer and IPI) */ | ||
| 314 | - sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, | ||
| 315 | - 0, smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, | ||
| 316 | - false); | ||
| 317 | +static void spike_machine_instance_init(Object *obj) | ||
| 318 | +{ | ||
| 319 | } | ||
| 320 | |||
| 321 | -static void spike_machine_init(MachineClass *mc) | ||
| 322 | +static void spike_machine_class_init(ObjectClass *oc, void *data) | ||
| 323 | { | ||
| 324 | - mc->desc = "RISC-V Spike Board"; | ||
| 325 | + MachineClass *mc = MACHINE_CLASS(oc); | ||
| 326 | + | ||
| 327 | + mc->desc = "RISC-V Spike board"; | ||
| 328 | mc->init = spike_board_init; | ||
| 329 | - mc->max_cpus = 8; | ||
| 330 | + mc->max_cpus = SPIKE_CPUS_MAX; | ||
| 331 | mc->is_default = true; | ||
| 332 | mc->default_cpu_type = SPIKE_V1_10_0_CPU; | ||
| 333 | + mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; | ||
| 334 | + mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; | ||
| 335 | + mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; | ||
| 336 | + mc->numa_mem_supported = true; | ||
| 337 | +} | ||
| 338 | + | ||
| 339 | +static const TypeInfo spike_machine_typeinfo = { | ||
| 340 | + .name = MACHINE_TYPE_NAME("spike"), | ||
| 341 | + .parent = TYPE_MACHINE, | ||
| 342 | + .class_init = spike_machine_class_init, | ||
| 343 | + .instance_init = spike_machine_instance_init, | ||
| 344 | + .instance_size = sizeof(SpikeState), | ||
| 345 | +}; | ||
| 346 | + | ||
| 347 | +static void spike_machine_init_register_types(void) | ||
| 348 | +{ | ||
| 349 | + type_register_static(&spike_machine_typeinfo); | ||
| 350 | } | ||
| 351 | |||
| 352 | -DEFINE_MACHINE("spike", spike_machine_init) | ||
| 353 | +type_init(spike_machine_init_register_types) | ||
| 354 | -- | ||
| 355 | 2.28.0 | ||
| 356 | |||
| 357 | diff view generated by jsdifflib |
| 1 | From: Asherah Connor <ashe@kivikakk.ee> | 1 | From: Anup Patel <anup.patel@wdc.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Provides fw_cfg for the virt machine on riscv. This enables | 3 | We extend RISC-V virt machine to allow creating a multi-socket |
| 4 | using e.g. ramfb later. | 4 | machine. Each RISC-V virt machine socket is a NUMA node having |
| 5 | 5 | a set of HARTs, a memory instance, a CLINT instance, and a PLIC | |
| 6 | Signed-off-by: Asherah Connor <ashe@kivikakk.ee> | 6 | instance. Other devices are shared between all sockets. We also |
| 7 | Reviewed-by: Bin Meng <bmeng.cn@gmail.com> | 7 | update the generated device tree accordingly. |
| 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 8 | |
| 9 | Message-id: 20210318235041.17175-2-ashe@kivikakk.ee | 9 | By default, NUMA multi-socket support is disabled for RISC-V virt |
| 10 | machine. To enable it, users can use "-numa" command-line options | ||
| 11 | of QEMU. | ||
| 12 | |||
| 13 | Example1: For two NUMA nodes with 2 CPUs each, append following | ||
| 14 | to command-line options: "-smp 4 -numa node -numa node" | ||
| 15 | |||
| 16 | Example2: For two NUMA nodes with 1 and 3 CPUs, append following | ||
| 17 | to command-line options: | ||
| 18 | "-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \ | ||
| 19 | -numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \ | ||
| 20 | -numa cpu,node-id=1,core-id=3" | ||
| 21 | |||
| 22 | The maximum number of sockets in a RISC-V virt machine is 8 | ||
| 23 | but this limit can be changed in future. | ||
| 24 | |||
| 25 | Signed-off-by: Anup Patel <anup.patel@wdc.com> | ||
| 26 | Reviewed-by: Atish Patra <atish.patra@wdc.com> | ||
| 27 | Message-Id: <20200616032229.766089-6-anup.patel@wdc.com> | ||
| 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 28 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 11 | --- | 29 | --- |
| 12 | include/hw/riscv/virt.h | 2 ++ | 30 | include/hw/riscv/virt.h | 9 +- |
| 13 | hw/riscv/virt.c | 30 ++++++++++++++++++++++++++++++ | 31 | hw/riscv/virt.c | 526 +++++++++++++++++++++++----------------- |
| 14 | hw/riscv/Kconfig | 1 + | 32 | 2 files changed, 306 insertions(+), 229 deletions(-) |
| 15 | 3 files changed, 33 insertions(+) | ||
| 16 | 33 | ||
| 17 | diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h | 34 | diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h |
| 18 | index XXXXXXX..XXXXXXX 100644 | 35 | index XXXXXXX..XXXXXXX 100644 |
| 19 | --- a/include/hw/riscv/virt.h | 36 | --- a/include/hw/riscv/virt.h |
| 20 | +++ b/include/hw/riscv/virt.h | 37 | +++ b/include/hw/riscv/virt.h |
| 21 | @@ -XXX,XX +XXX,XX @@ struct RISCVVirtState { | 38 | @@ -XXX,XX +XXX,XX @@ |
| 22 | RISCVHartArrayState soc[VIRT_SOCKETS_MAX]; | 39 | #include "hw/sysbus.h" |
| 23 | DeviceState *plic[VIRT_SOCKETS_MAX]; | 40 | #include "hw/block/flash.h" |
| 41 | |||
| 42 | +#define VIRT_CPUS_MAX 8 | ||
| 43 | +#define VIRT_SOCKETS_MAX 8 | ||
| 44 | + | ||
| 45 | #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt") | ||
| 46 | #define RISCV_VIRT_MACHINE(obj) \ | ||
| 47 | OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_MACHINE) | ||
| 48 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
| 49 | MachineState parent; | ||
| 50 | |||
| 51 | /*< public >*/ | ||
| 52 | - RISCVHartArrayState soc; | ||
| 53 | - DeviceState *plic; | ||
| 54 | + RISCVHartArrayState soc[VIRT_SOCKETS_MAX]; | ||
| 55 | + DeviceState *plic[VIRT_SOCKETS_MAX]; | ||
| 24 | PFlashCFI01 *flash[2]; | 56 | PFlashCFI01 *flash[2]; |
| 25 | + FWCfgState *fw_cfg; | 57 | |
| 26 | 58 | void *fdt; | |
| 27 | int fdt_size; | ||
| 28 | }; | ||
| 29 | @@ -XXX,XX +XXX,XX @@ enum { | 59 | @@ -XXX,XX +XXX,XX @@ enum { |
| 30 | VIRT_PLIC, | 60 | #define VIRT_PLIC_ENABLE_STRIDE 0x80 |
| 31 | VIRT_UART0, | 61 | #define VIRT_PLIC_CONTEXT_BASE 0x200000 |
| 32 | VIRT_VIRTIO, | 62 | #define VIRT_PLIC_CONTEXT_STRIDE 0x1000 |
| 33 | + VIRT_FW_CFG, | 63 | +#define VIRT_PLIC_SIZE(__num_context) \ |
| 34 | VIRT_FLASH, | 64 | + (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE) |
| 35 | VIRT_DRAM, | 65 | |
| 36 | VIRT_PCIE_MMIO, | 66 | #define FDT_PCI_ADDR_CELLS 3 |
| 67 | #define FDT_PCI_INT_CELLS 1 | ||
| 37 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c | 68 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c |
| 38 | index XXXXXXX..XXXXXXX 100644 | 69 | index XXXXXXX..XXXXXXX 100644 |
| 39 | --- a/hw/riscv/virt.c | 70 | --- a/hw/riscv/virt.c |
| 40 | +++ b/hw/riscv/virt.c | 71 | +++ b/hw/riscv/virt.c |
| 41 | @@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = { | 72 | @@ -XXX,XX +XXX,XX @@ |
| 42 | [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, | 73 | #include "hw/riscv/sifive_test.h" |
| 74 | #include "hw/riscv/virt.h" | ||
| 75 | #include "hw/riscv/boot.h" | ||
| 76 | +#include "hw/riscv/numa.h" | ||
| 77 | #include "chardev/char.h" | ||
| 78 | #include "sysemu/arch_init.h" | ||
| 79 | #include "sysemu/device_tree.h" | ||
| 80 | @@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry { | ||
| 81 | [VIRT_RTC] = { 0x101000, 0x1000 }, | ||
| 82 | [VIRT_CLINT] = { 0x2000000, 0x10000 }, | ||
| 83 | [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, | ||
| 84 | - [VIRT_PLIC] = { 0xc000000, 0x4000000 }, | ||
| 85 | + [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, | ||
| 43 | [VIRT_UART0] = { 0x10000000, 0x100 }, | 86 | [VIRT_UART0] = { 0x10000000, 0x100 }, |
| 44 | [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, | 87 | [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, |
| 45 | + [VIRT_FW_CFG] = { 0x10100000, 0x18 }, | ||
| 46 | [VIRT_FLASH] = { 0x20000000, 0x4000000 }, | 88 | [VIRT_FLASH] = { 0x20000000, 0x4000000 }, |
| 47 | [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, | 89 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, |
| 48 | [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, | 90 | uint64_t mem_size, const char *cmdline) |
| 49 | @@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, | 91 | { |
| 50 | return dev; | 92 | void *fdt; |
| 93 | - int cpu, i; | ||
| 94 | - uint32_t *cells; | ||
| 95 | - char *nodename; | ||
| 96 | - uint32_t plic_phandle, test_phandle, phandle = 1; | ||
| 97 | + int i, cpu, socket; | ||
| 98 | + MachineState *mc = MACHINE(s); | ||
| 99 | + uint64_t addr, size; | ||
| 100 | + uint32_t *clint_cells, *plic_cells; | ||
| 101 | + unsigned long clint_addr, plic_addr; | ||
| 102 | + uint32_t plic_phandle[MAX_NODES]; | ||
| 103 | + uint32_t cpu_phandle, intc_phandle, test_phandle; | ||
| 104 | + uint32_t phandle = 1, plic_mmio_phandle = 1; | ||
| 105 | + uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1; | ||
| 106 | + char *mem_name, *cpu_name, *core_name, *intc_name; | ||
| 107 | + char *name, *clint_name, *plic_name, *clust_name; | ||
| 108 | hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; | ||
| 109 | hwaddr flashbase = virt_memmap[VIRT_FLASH].base; | ||
| 110 | |||
| 111 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, | ||
| 112 | qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); | ||
| 113 | qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); | ||
| 114 | |||
| 115 | - nodename = g_strdup_printf("/memory@%lx", | ||
| 116 | - (long)memmap[VIRT_DRAM].base); | ||
| 117 | - qemu_fdt_add_subnode(fdt, nodename); | ||
| 118 | - qemu_fdt_setprop_cells(fdt, nodename, "reg", | ||
| 119 | - memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base, | ||
| 120 | - mem_size >> 32, mem_size); | ||
| 121 | - qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); | ||
| 122 | - g_free(nodename); | ||
| 123 | - | ||
| 124 | qemu_fdt_add_subnode(fdt, "/cpus"); | ||
| 125 | qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", | ||
| 126 | SIFIVE_CLINT_TIMEBASE_FREQ); | ||
| 127 | qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); | ||
| 128 | qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); | ||
| 129 | + qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); | ||
| 130 | + | ||
| 131 | + for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { | ||
| 132 | + clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); | ||
| 133 | + qemu_fdt_add_subnode(fdt, clust_name); | ||
| 134 | + | ||
| 135 | + plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); | ||
| 136 | + clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); | ||
| 137 | + | ||
| 138 | + for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { | ||
| 139 | + cpu_phandle = phandle++; | ||
| 140 | |||
| 141 | - for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) { | ||
| 142 | - int cpu_phandle = phandle++; | ||
| 143 | - int intc_phandle; | ||
| 144 | - nodename = g_strdup_printf("/cpus/cpu@%d", cpu); | ||
| 145 | - char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | ||
| 146 | - char *isa = riscv_isa_string(&s->soc.harts[cpu]); | ||
| 147 | - qemu_fdt_add_subnode(fdt, nodename); | ||
| 148 | + cpu_name = g_strdup_printf("/cpus/cpu@%d", | ||
| 149 | + s->soc[socket].hartid_base + cpu); | ||
| 150 | + qemu_fdt_add_subnode(fdt, cpu_name); | ||
| 151 | #if defined(TARGET_RISCV32) | ||
| 152 | - qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); | ||
| 153 | + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); | ||
| 154 | #else | ||
| 155 | - qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); | ||
| 156 | + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); | ||
| 157 | #endif | ||
| 158 | - qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); | ||
| 159 | - qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); | ||
| 160 | - qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); | ||
| 161 | - qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); | ||
| 162 | - qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); | ||
| 163 | - qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle); | ||
| 164 | - intc_phandle = phandle++; | ||
| 165 | - qemu_fdt_add_subnode(fdt, intc); | ||
| 166 | - qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle); | ||
| 167 | - qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); | ||
| 168 | - qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); | ||
| 169 | - qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); | ||
| 170 | - g_free(isa); | ||
| 171 | - g_free(intc); | ||
| 172 | - g_free(nodename); | ||
| 173 | - } | ||
| 174 | + name = riscv_isa_string(&s->soc[socket].harts[cpu]); | ||
| 175 | + qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); | ||
| 176 | + g_free(name); | ||
| 177 | + qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); | ||
| 178 | + qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); | ||
| 179 | + qemu_fdt_setprop_cell(fdt, cpu_name, "reg", | ||
| 180 | + s->soc[socket].hartid_base + cpu); | ||
| 181 | + qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); | ||
| 182 | + riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); | ||
| 183 | + qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); | ||
| 184 | + | ||
| 185 | + intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); | ||
| 186 | + qemu_fdt_add_subnode(fdt, intc_name); | ||
| 187 | + intc_phandle = phandle++; | ||
| 188 | + qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle); | ||
| 189 | + qemu_fdt_setprop_string(fdt, intc_name, "compatible", | ||
| 190 | + "riscv,cpu-intc"); | ||
| 191 | + qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); | ||
| 192 | + qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); | ||
| 193 | + | ||
| 194 | + clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | ||
| 195 | + clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); | ||
| 196 | + clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); | ||
| 197 | + clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); | ||
| 198 | + | ||
| 199 | + plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | ||
| 200 | + plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); | ||
| 201 | + plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); | ||
| 202 | + plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); | ||
| 203 | + | ||
| 204 | + core_name = g_strdup_printf("%s/core%d", clust_name, cpu); | ||
| 205 | + qemu_fdt_add_subnode(fdt, core_name); | ||
| 206 | + qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); | ||
| 207 | + | ||
| 208 | + g_free(core_name); | ||
| 209 | + g_free(intc_name); | ||
| 210 | + g_free(cpu_name); | ||
| 211 | + } | ||
| 212 | |||
| 213 | - /* Add cpu-topology node */ | ||
| 214 | - qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); | ||
| 215 | - qemu_fdt_add_subnode(fdt, "/cpus/cpu-map/cluster0"); | ||
| 216 | - for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) { | ||
| 217 | - char *core_nodename = g_strdup_printf("/cpus/cpu-map/cluster0/core%d", | ||
| 218 | - cpu); | ||
| 219 | - char *cpu_nodename = g_strdup_printf("/cpus/cpu@%d", cpu); | ||
| 220 | - uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, cpu_nodename); | ||
| 221 | - qemu_fdt_add_subnode(fdt, core_nodename); | ||
| 222 | - qemu_fdt_setprop_cell(fdt, core_nodename, "cpu", intc_phandle); | ||
| 223 | - g_free(core_nodename); | ||
| 224 | - g_free(cpu_nodename); | ||
| 225 | + addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); | ||
| 226 | + size = riscv_socket_mem_size(mc, socket); | ||
| 227 | + mem_name = g_strdup_printf("/memory@%lx", (long)addr); | ||
| 228 | + qemu_fdt_add_subnode(fdt, mem_name); | ||
| 229 | + qemu_fdt_setprop_cells(fdt, mem_name, "reg", | ||
| 230 | + addr >> 32, addr, size >> 32, size); | ||
| 231 | + qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); | ||
| 232 | + riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); | ||
| 233 | + g_free(mem_name); | ||
| 234 | + | ||
| 235 | + clint_addr = memmap[VIRT_CLINT].base + | ||
| 236 | + (memmap[VIRT_CLINT].size * socket); | ||
| 237 | + clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); | ||
| 238 | + qemu_fdt_add_subnode(fdt, clint_name); | ||
| 239 | + qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0"); | ||
| 240 | + qemu_fdt_setprop_cells(fdt, clint_name, "reg", | ||
| 241 | + 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); | ||
| 242 | + qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", | ||
| 243 | + clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); | ||
| 244 | + riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); | ||
| 245 | + g_free(clint_name); | ||
| 246 | + | ||
| 247 | + plic_phandle[socket] = phandle++; | ||
| 248 | + plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); | ||
| 249 | + plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); | ||
| 250 | + qemu_fdt_add_subnode(fdt, plic_name); | ||
| 251 | + qemu_fdt_setprop_cell(fdt, plic_name, | ||
| 252 | + "#address-cells", FDT_PLIC_ADDR_CELLS); | ||
| 253 | + qemu_fdt_setprop_cell(fdt, plic_name, | ||
| 254 | + "#interrupt-cells", FDT_PLIC_INT_CELLS); | ||
| 255 | + qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0"); | ||
| 256 | + qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0); | ||
| 257 | + qemu_fdt_setprop(fdt, plic_name, "interrupts-extended", | ||
| 258 | + plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); | ||
| 259 | + qemu_fdt_setprop_cells(fdt, plic_name, "reg", | ||
| 260 | + 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); | ||
| 261 | + qemu_fdt_setprop_cell(fdt, plic_name, "riscv,ndev", VIRTIO_NDEV); | ||
| 262 | + riscv_socket_fdt_write_id(mc, fdt, plic_name, socket); | ||
| 263 | + qemu_fdt_setprop_cell(fdt, plic_name, "phandle", plic_phandle[socket]); | ||
| 264 | + g_free(plic_name); | ||
| 265 | + | ||
| 266 | + g_free(clint_cells); | ||
| 267 | + g_free(plic_cells); | ||
| 268 | + g_free(clust_name); | ||
| 269 | } | ||
| 270 | |||
| 271 | - cells = g_new0(uint32_t, s->soc.num_harts * 4); | ||
| 272 | - for (cpu = 0; cpu < s->soc.num_harts; cpu++) { | ||
| 273 | - nodename = | ||
| 274 | - g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | ||
| 275 | - uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); | ||
| 276 | - cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | ||
| 277 | - cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); | ||
| 278 | - cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); | ||
| 279 | - cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); | ||
| 280 | - g_free(nodename); | ||
| 281 | - } | ||
| 282 | - nodename = g_strdup_printf("/soc/clint@%lx", | ||
| 283 | - (long)memmap[VIRT_CLINT].base); | ||
| 284 | - qemu_fdt_add_subnode(fdt, nodename); | ||
| 285 | - qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); | ||
| 286 | - qemu_fdt_setprop_cells(fdt, nodename, "reg", | ||
| 287 | - 0x0, memmap[VIRT_CLINT].base, | ||
| 288 | - 0x0, memmap[VIRT_CLINT].size); | ||
| 289 | - qemu_fdt_setprop(fdt, nodename, "interrupts-extended", | ||
| 290 | - cells, s->soc.num_harts * sizeof(uint32_t) * 4); | ||
| 291 | - g_free(cells); | ||
| 292 | - g_free(nodename); | ||
| 293 | - | ||
| 294 | - plic_phandle = phandle++; | ||
| 295 | - cells = g_new0(uint32_t, s->soc.num_harts * 4); | ||
| 296 | - for (cpu = 0; cpu < s->soc.num_harts; cpu++) { | ||
| 297 | - nodename = | ||
| 298 | - g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | ||
| 299 | - uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); | ||
| 300 | - cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | ||
| 301 | - cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); | ||
| 302 | - cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); | ||
| 303 | - cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); | ||
| 304 | - g_free(nodename); | ||
| 305 | + for (socket = 0; socket < riscv_socket_count(mc); socket++) { | ||
| 306 | + if (socket == 0) { | ||
| 307 | + plic_mmio_phandle = plic_phandle[socket]; | ||
| 308 | + plic_virtio_phandle = plic_phandle[socket]; | ||
| 309 | + plic_pcie_phandle = plic_phandle[socket]; | ||
| 310 | + } | ||
| 311 | + if (socket == 1) { | ||
| 312 | + plic_virtio_phandle = plic_phandle[socket]; | ||
| 313 | + plic_pcie_phandle = plic_phandle[socket]; | ||
| 314 | + } | ||
| 315 | + if (socket == 2) { | ||
| 316 | + plic_pcie_phandle = plic_phandle[socket]; | ||
| 317 | + } | ||
| 318 | } | ||
| 319 | - nodename = g_strdup_printf("/soc/interrupt-controller@%lx", | ||
| 320 | - (long)memmap[VIRT_PLIC].base); | ||
| 321 | - qemu_fdt_add_subnode(fdt, nodename); | ||
| 322 | - qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", | ||
| 323 | - FDT_PLIC_ADDR_CELLS); | ||
| 324 | - qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", | ||
| 325 | - FDT_PLIC_INT_CELLS); | ||
| 326 | - qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); | ||
| 327 | - qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); | ||
| 328 | - qemu_fdt_setprop(fdt, nodename, "interrupts-extended", | ||
| 329 | - cells, s->soc.num_harts * sizeof(uint32_t) * 4); | ||
| 330 | - qemu_fdt_setprop_cells(fdt, nodename, "reg", | ||
| 331 | - 0x0, memmap[VIRT_PLIC].base, | ||
| 332 | - 0x0, memmap[VIRT_PLIC].size); | ||
| 333 | - qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV); | ||
| 334 | - qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); | ||
| 335 | - plic_phandle = qemu_fdt_get_phandle(fdt, nodename); | ||
| 336 | - g_free(cells); | ||
| 337 | - g_free(nodename); | ||
| 338 | + | ||
| 339 | + riscv_socket_fdt_write_distance_matrix(mc, fdt); | ||
| 340 | |||
| 341 | for (i = 0; i < VIRTIO_COUNT; i++) { | ||
| 342 | - nodename = g_strdup_printf("/virtio_mmio@%lx", | ||
| 343 | + name = g_strdup_printf("/soc/virtio_mmio@%lx", | ||
| 344 | (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); | ||
| 345 | - qemu_fdt_add_subnode(fdt, nodename); | ||
| 346 | - qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio"); | ||
| 347 | - qemu_fdt_setprop_cells(fdt, nodename, "reg", | ||
| 348 | + qemu_fdt_add_subnode(fdt, name); | ||
| 349 | + qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio"); | ||
| 350 | + qemu_fdt_setprop_cells(fdt, name, "reg", | ||
| 351 | 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, | ||
| 352 | 0x0, memmap[VIRT_VIRTIO].size); | ||
| 353 | - qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | ||
| 354 | - qemu_fdt_setprop_cell(fdt, nodename, "interrupts", VIRTIO_IRQ + i); | ||
| 355 | - g_free(nodename); | ||
| 356 | + qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", | ||
| 357 | + plic_virtio_phandle); | ||
| 358 | + qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i); | ||
| 359 | + g_free(name); | ||
| 360 | } | ||
| 361 | |||
| 362 | - nodename = g_strdup_printf("/soc/pci@%lx", | ||
| 363 | + name = g_strdup_printf("/soc/pci@%lx", | ||
| 364 | (long) memmap[VIRT_PCIE_ECAM].base); | ||
| 365 | - qemu_fdt_add_subnode(fdt, nodename); | ||
| 366 | - qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", | ||
| 367 | - FDT_PCI_ADDR_CELLS); | ||
| 368 | - qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", | ||
| 369 | - FDT_PCI_INT_CELLS); | ||
| 370 | - qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0x2); | ||
| 371 | - qemu_fdt_setprop_string(fdt, nodename, "compatible", | ||
| 372 | - "pci-host-ecam-generic"); | ||
| 373 | - qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci"); | ||
| 374 | - qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0); | ||
| 375 | - qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0, | ||
| 376 | - memmap[VIRT_PCIE_ECAM].size / | ||
| 377 | - PCIE_MMCFG_SIZE_MIN - 1); | ||
| 378 | - qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0); | ||
| 379 | - qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM].base, | ||
| 380 | - 0, memmap[VIRT_PCIE_ECAM].size); | ||
| 381 | - qemu_fdt_setprop_sized_cells(fdt, nodename, "ranges", | ||
| 382 | + qemu_fdt_add_subnode(fdt, name); | ||
| 383 | + qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); | ||
| 384 | + qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS); | ||
| 385 | + qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2); | ||
| 386 | + qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic"); | ||
| 387 | + qemu_fdt_setprop_string(fdt, name, "device_type", "pci"); | ||
| 388 | + qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0); | ||
| 389 | + qemu_fdt_setprop_cells(fdt, name, "bus-range", 0, | ||
| 390 | + memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); | ||
| 391 | + qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0); | ||
| 392 | + qemu_fdt_setprop_cells(fdt, name, "reg", 0, | ||
| 393 | + memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); | ||
| 394 | + qemu_fdt_setprop_sized_cells(fdt, name, "ranges", | ||
| 395 | 1, FDT_PCI_RANGE_IOPORT, 2, 0, | ||
| 396 | 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, | ||
| 397 | 1, FDT_PCI_RANGE_MMIO, | ||
| 398 | 2, memmap[VIRT_PCIE_MMIO].base, | ||
| 399 | 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size); | ||
| 400 | - create_pcie_irq_map(fdt, nodename, plic_phandle); | ||
| 401 | - g_free(nodename); | ||
| 402 | + create_pcie_irq_map(fdt, name, plic_pcie_phandle); | ||
| 403 | + g_free(name); | ||
| 404 | |||
| 405 | test_phandle = phandle++; | ||
| 406 | - nodename = g_strdup_printf("/test@%lx", | ||
| 407 | + name = g_strdup_printf("/soc/test@%lx", | ||
| 408 | (long)memmap[VIRT_TEST].base); | ||
| 409 | - qemu_fdt_add_subnode(fdt, nodename); | ||
| 410 | + qemu_fdt_add_subnode(fdt, name); | ||
| 411 | { | ||
| 412 | const char compat[] = "sifive,test1\0sifive,test0\0syscon"; | ||
| 413 | - qemu_fdt_setprop(fdt, nodename, "compatible", compat, sizeof(compat)); | ||
| 414 | + qemu_fdt_setprop(fdt, name, "compatible", compat, sizeof(compat)); | ||
| 415 | } | ||
| 416 | - qemu_fdt_setprop_cells(fdt, nodename, "reg", | ||
| 417 | + qemu_fdt_setprop_cells(fdt, name, "reg", | ||
| 418 | 0x0, memmap[VIRT_TEST].base, | ||
| 419 | 0x0, memmap[VIRT_TEST].size); | ||
| 420 | - qemu_fdt_setprop_cell(fdt, nodename, "phandle", test_phandle); | ||
| 421 | - test_phandle = qemu_fdt_get_phandle(fdt, nodename); | ||
| 422 | - g_free(nodename); | ||
| 423 | - | ||
| 424 | - nodename = g_strdup_printf("/reboot"); | ||
| 425 | - qemu_fdt_add_subnode(fdt, nodename); | ||
| 426 | - qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-reboot"); | ||
| 427 | - qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_phandle); | ||
| 428 | - qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0); | ||
| 429 | - qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_RESET); | ||
| 430 | - g_free(nodename); | ||
| 431 | - | ||
| 432 | - nodename = g_strdup_printf("/poweroff"); | ||
| 433 | - qemu_fdt_add_subnode(fdt, nodename); | ||
| 434 | - qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-poweroff"); | ||
| 435 | - qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_phandle); | ||
| 436 | - qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0); | ||
| 437 | - qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_PASS); | ||
| 438 | - g_free(nodename); | ||
| 439 | - | ||
| 440 | - nodename = g_strdup_printf("/uart@%lx", | ||
| 441 | - (long)memmap[VIRT_UART0].base); | ||
| 442 | - qemu_fdt_add_subnode(fdt, nodename); | ||
| 443 | - qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a"); | ||
| 444 | - qemu_fdt_setprop_cells(fdt, nodename, "reg", | ||
| 445 | + qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle); | ||
| 446 | + test_phandle = qemu_fdt_get_phandle(fdt, name); | ||
| 447 | + g_free(name); | ||
| 448 | + | ||
| 449 | + name = g_strdup_printf("/soc/reboot"); | ||
| 450 | + qemu_fdt_add_subnode(fdt, name); | ||
| 451 | + qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot"); | ||
| 452 | + qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); | ||
| 453 | + qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); | ||
| 454 | + qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET); | ||
| 455 | + g_free(name); | ||
| 456 | + | ||
| 457 | + name = g_strdup_printf("/soc/poweroff"); | ||
| 458 | + qemu_fdt_add_subnode(fdt, name); | ||
| 459 | + qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff"); | ||
| 460 | + qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); | ||
| 461 | + qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); | ||
| 462 | + qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS); | ||
| 463 | + g_free(name); | ||
| 464 | + | ||
| 465 | + name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base); | ||
| 466 | + qemu_fdt_add_subnode(fdt, name); | ||
| 467 | + qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a"); | ||
| 468 | + qemu_fdt_setprop_cells(fdt, name, "reg", | ||
| 469 | 0x0, memmap[VIRT_UART0].base, | ||
| 470 | 0x0, memmap[VIRT_UART0].size); | ||
| 471 | - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400); | ||
| 472 | - qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | ||
| 473 | - qemu_fdt_setprop_cell(fdt, nodename, "interrupts", UART0_IRQ); | ||
| 474 | + qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400); | ||
| 475 | + qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle); | ||
| 476 | + qemu_fdt_setprop_cell(fdt, name, "interrupts", UART0_IRQ); | ||
| 477 | |||
| 478 | qemu_fdt_add_subnode(fdt, "/chosen"); | ||
| 479 | - qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); | ||
| 480 | + qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name); | ||
| 481 | if (cmdline) { | ||
| 482 | qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); | ||
| 483 | } | ||
| 484 | - g_free(nodename); | ||
| 485 | - | ||
| 486 | - nodename = g_strdup_printf("/rtc@%lx", | ||
| 487 | - (long)memmap[VIRT_RTC].base); | ||
| 488 | - qemu_fdt_add_subnode(fdt, nodename); | ||
| 489 | - qemu_fdt_setprop_string(fdt, nodename, "compatible", | ||
| 490 | - "google,goldfish-rtc"); | ||
| 491 | - qemu_fdt_setprop_cells(fdt, nodename, "reg", | ||
| 492 | + g_free(name); | ||
| 493 | + | ||
| 494 | + name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); | ||
| 495 | + qemu_fdt_add_subnode(fdt, name); | ||
| 496 | + qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc"); | ||
| 497 | + qemu_fdt_setprop_cells(fdt, name, "reg", | ||
| 498 | 0x0, memmap[VIRT_RTC].base, | ||
| 499 | 0x0, memmap[VIRT_RTC].size); | ||
| 500 | - qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | ||
| 501 | - qemu_fdt_setprop_cell(fdt, nodename, "interrupts", RTC_IRQ); | ||
| 502 | - g_free(nodename); | ||
| 503 | - | ||
| 504 | - nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); | ||
| 505 | - qemu_fdt_add_subnode(s->fdt, nodename); | ||
| 506 | - qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "cfi-flash"); | ||
| 507 | - qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg", | ||
| 508 | + qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle); | ||
| 509 | + qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ); | ||
| 510 | + g_free(name); | ||
| 511 | + | ||
| 512 | + name = g_strdup_printf("/soc/flash@%" PRIx64, flashbase); | ||
| 513 | + qemu_fdt_add_subnode(s->fdt, name); | ||
| 514 | + qemu_fdt_setprop_string(s->fdt, name, "compatible", "cfi-flash"); | ||
| 515 | + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", | ||
| 516 | 2, flashbase, 2, flashsize, | ||
| 517 | 2, flashbase + flashsize, 2, flashsize); | ||
| 518 | - qemu_fdt_setprop_cell(s->fdt, nodename, "bank-width", 4); | ||
| 519 | - g_free(nodename); | ||
| 520 | + qemu_fdt_setprop_cell(s->fdt, name, "bank-width", 4); | ||
| 521 | + g_free(name); | ||
| 51 | } | 522 | } |
| 52 | 523 | ||
| 53 | +static FWCfgState *create_fw_cfg(const MachineState *mc) | 524 | - |
| 54 | +{ | 525 | static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, |
| 55 | + hwaddr base = virt_memmap[VIRT_FW_CFG].base; | 526 | hwaddr ecam_base, hwaddr ecam_size, |
| 56 | + hwaddr size = virt_memmap[VIRT_FW_CFG].size; | 527 | hwaddr mmio_base, hwaddr mmio_size, |
| 57 | + FWCfgState *fw_cfg; | ||
| 58 | + char *nodename; | ||
| 59 | + | ||
| 60 | + fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, | ||
| 61 | + &address_space_memory); | ||
| 62 | + fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); | ||
| 63 | + | ||
| 64 | + nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); | ||
| 65 | + qemu_fdt_add_subnode(mc->fdt, nodename); | ||
| 66 | + qemu_fdt_setprop_string(mc->fdt, nodename, | ||
| 67 | + "compatible", "qemu,fw-cfg-mmio"); | ||
| 68 | + qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", | ||
| 69 | + 2, base, 2, size); | ||
| 70 | + qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); | ||
| 71 | + g_free(nodename); | ||
| 72 | + return fw_cfg; | ||
| 73 | +} | ||
| 74 | + | ||
| 75 | static void virt_machine_init(MachineState *machine) | ||
| 76 | { | ||
| 77 | const MemMapEntry *memmap = virt_memmap; | ||
| 78 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine) | 528 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine) |
| 79 | start_addr = virt_memmap[VIRT_FLASH].base; | 529 | MemoryRegion *system_memory = get_system_memory(); |
| 530 | MemoryRegion *main_mem = g_new(MemoryRegion, 1); | ||
| 531 | MemoryRegion *mask_rom = g_new(MemoryRegion, 1); | ||
| 532 | - char *plic_hart_config; | ||
| 533 | + char *plic_hart_config, *soc_name; | ||
| 534 | size_t plic_hart_config_len; | ||
| 535 | target_ulong start_addr = memmap[VIRT_DRAM].base; | ||
| 536 | uint32_t fdt_load_addr; | ||
| 537 | uint64_t kernel_entry; | ||
| 538 | - int i; | ||
| 539 | - unsigned int smp_cpus = machine->smp.cpus; | ||
| 540 | + DeviceState *mmio_plic, *virtio_plic, *pcie_plic; | ||
| 541 | + int i, j, base_hartid, hart_count; | ||
| 542 | |||
| 543 | - /* Initialize SOC */ | ||
| 544 | - object_initialize_child(OBJECT(machine), "soc", &s->soc, | ||
| 545 | - TYPE_RISCV_HART_ARRAY); | ||
| 546 | - object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, | ||
| 547 | - &error_abort); | ||
| 548 | - object_property_set_int(OBJECT(&s->soc), "num-harts", smp_cpus, | ||
| 549 | - &error_abort); | ||
| 550 | - sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort); | ||
| 551 | + /* Check socket count limit */ | ||
| 552 | + if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { | ||
| 553 | + error_report("number of sockets/nodes should be less than %d", | ||
| 554 | + VIRT_SOCKETS_MAX); | ||
| 555 | + exit(1); | ||
| 556 | + } | ||
| 557 | + | ||
| 558 | + /* Initialize sockets */ | ||
| 559 | + mmio_plic = virtio_plic = pcie_plic = NULL; | ||
| 560 | + for (i = 0; i < riscv_socket_count(machine); i++) { | ||
| 561 | + if (!riscv_socket_check_hartids(machine, i)) { | ||
| 562 | + error_report("discontinuous hartids in socket%d", i); | ||
| 563 | + exit(1); | ||
| 564 | + } | ||
| 565 | + | ||
| 566 | + base_hartid = riscv_socket_first_hartid(machine, i); | ||
| 567 | + if (base_hartid < 0) { | ||
| 568 | + error_report("can't find hartid base for socket%d", i); | ||
| 569 | + exit(1); | ||
| 570 | + } | ||
| 571 | + | ||
| 572 | + hart_count = riscv_socket_hart_count(machine, i); | ||
| 573 | + if (hart_count < 0) { | ||
| 574 | + error_report("can't find hart count for socket%d", i); | ||
| 575 | + exit(1); | ||
| 576 | + } | ||
| 577 | + | ||
| 578 | + soc_name = g_strdup_printf("soc%d", i); | ||
| 579 | + object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], | ||
| 580 | + TYPE_RISCV_HART_ARRAY); | ||
| 581 | + g_free(soc_name); | ||
| 582 | + object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", | ||
| 583 | + machine->cpu_type, &error_abort); | ||
| 584 | + object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", | ||
| 585 | + base_hartid, &error_abort); | ||
| 586 | + object_property_set_int(OBJECT(&s->soc[i]), "num-harts", | ||
| 587 | + hart_count, &error_abort); | ||
| 588 | + sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); | ||
| 589 | + | ||
| 590 | + /* Per-socket CLINT */ | ||
| 591 | + sifive_clint_create( | ||
| 592 | + memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, | ||
| 593 | + memmap[VIRT_CLINT].size, base_hartid, hart_count, | ||
| 594 | + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true); | ||
| 595 | + | ||
| 596 | + /* Per-socket PLIC hart topology configuration string */ | ||
| 597 | + plic_hart_config_len = | ||
| 598 | + (strlen(VIRT_PLIC_HART_CONFIG) + 1) * hart_count; | ||
| 599 | + plic_hart_config = g_malloc0(plic_hart_config_len); | ||
| 600 | + for (j = 0; j < hart_count; j++) { | ||
| 601 | + if (j != 0) { | ||
| 602 | + strncat(plic_hart_config, ",", plic_hart_config_len); | ||
| 603 | + } | ||
| 604 | + strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, | ||
| 605 | + plic_hart_config_len); | ||
| 606 | + plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1); | ||
| 607 | + } | ||
| 608 | + | ||
| 609 | + /* Per-socket PLIC */ | ||
| 610 | + s->plic[i] = sifive_plic_create( | ||
| 611 | + memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size, | ||
| 612 | + plic_hart_config, base_hartid, | ||
| 613 | + VIRT_PLIC_NUM_SOURCES, | ||
| 614 | + VIRT_PLIC_NUM_PRIORITIES, | ||
| 615 | + VIRT_PLIC_PRIORITY_BASE, | ||
| 616 | + VIRT_PLIC_PENDING_BASE, | ||
| 617 | + VIRT_PLIC_ENABLE_BASE, | ||
| 618 | + VIRT_PLIC_ENABLE_STRIDE, | ||
| 619 | + VIRT_PLIC_CONTEXT_BASE, | ||
| 620 | + VIRT_PLIC_CONTEXT_STRIDE, | ||
| 621 | + memmap[VIRT_PLIC].size); | ||
| 622 | + g_free(plic_hart_config); | ||
| 623 | + | ||
| 624 | + /* Try to use different PLIC instance based device type */ | ||
| 625 | + if (i == 0) { | ||
| 626 | + mmio_plic = s->plic[i]; | ||
| 627 | + virtio_plic = s->plic[i]; | ||
| 628 | + pcie_plic = s->plic[i]; | ||
| 629 | + } | ||
| 630 | + if (i == 1) { | ||
| 631 | + virtio_plic = s->plic[i]; | ||
| 632 | + pcie_plic = s->plic[i]; | ||
| 633 | + } | ||
| 634 | + if (i == 2) { | ||
| 635 | + pcie_plic = s->plic[i]; | ||
| 636 | + } | ||
| 637 | + } | ||
| 638 | |||
| 639 | /* register system main memory (actual RAM) */ | ||
| 640 | memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram", | ||
| 641 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine) | ||
| 642 | virt_memmap[VIRT_MROM].size, kernel_entry, | ||
| 643 | fdt_load_addr, s->fdt); | ||
| 644 | |||
| 645 | - /* create PLIC hart topology configuration string */ | ||
| 646 | - plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus; | ||
| 647 | - plic_hart_config = g_malloc0(plic_hart_config_len); | ||
| 648 | - for (i = 0; i < smp_cpus; i++) { | ||
| 649 | - if (i != 0) { | ||
| 650 | - strncat(plic_hart_config, ",", plic_hart_config_len); | ||
| 651 | - } | ||
| 652 | - strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_len); | ||
| 653 | - plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1); | ||
| 654 | - } | ||
| 655 | - | ||
| 656 | - /* MMIO */ | ||
| 657 | - s->plic = sifive_plic_create(memmap[VIRT_PLIC].base, | ||
| 658 | - plic_hart_config, 0, | ||
| 659 | - VIRT_PLIC_NUM_SOURCES, | ||
| 660 | - VIRT_PLIC_NUM_PRIORITIES, | ||
| 661 | - VIRT_PLIC_PRIORITY_BASE, | ||
| 662 | - VIRT_PLIC_PENDING_BASE, | ||
| 663 | - VIRT_PLIC_ENABLE_BASE, | ||
| 664 | - VIRT_PLIC_ENABLE_STRIDE, | ||
| 665 | - VIRT_PLIC_CONTEXT_BASE, | ||
| 666 | - VIRT_PLIC_CONTEXT_STRIDE, | ||
| 667 | - memmap[VIRT_PLIC].size); | ||
| 668 | - sifive_clint_create(memmap[VIRT_CLINT].base, | ||
| 669 | - memmap[VIRT_CLINT].size, 0, smp_cpus, | ||
| 670 | - SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true); | ||
| 671 | + /* SiFive Test MMIO device */ | ||
| 672 | sifive_test_create(memmap[VIRT_TEST].base); | ||
| 673 | |||
| 674 | + /* VirtIO MMIO devices */ | ||
| 675 | for (i = 0; i < VIRTIO_COUNT; i++) { | ||
| 676 | sysbus_create_simple("virtio-mmio", | ||
| 677 | memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, | ||
| 678 | - qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i)); | ||
| 679 | + qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i)); | ||
| 80 | } | 680 | } |
| 81 | 681 | ||
| 82 | + /* | 682 | gpex_pcie_init(system_memory, |
| 83 | + * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device | 683 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine) |
| 84 | + * tree cannot be altered and we get FDT_ERR_NOSPACE. | 684 | memmap[VIRT_PCIE_MMIO].base, |
| 85 | + */ | 685 | memmap[VIRT_PCIE_MMIO].size, |
| 86 | + s->fw_cfg = create_fw_cfg(machine); | 686 | memmap[VIRT_PCIE_PIO].base, |
| 87 | + rom_set_fw(s->fw_cfg); | 687 | - DEVICE(s->plic), true); |
| 88 | + | 688 | + DEVICE(pcie_plic), true); |
| 89 | /* Compute the fdt load address in dram */ | 689 | |
| 90 | fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, | 690 | serial_mm_init(system_memory, memmap[VIRT_UART0].base, |
| 91 | machine->ram_size, machine->fdt); | 691 | - 0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193, |
| 92 | diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig | 692 | + 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193, |
| 93 | index XXXXXXX..XXXXXXX 100644 | 693 | serial_hd(0), DEVICE_LITTLE_ENDIAN); |
| 94 | --- a/hw/riscv/Kconfig | 694 | |
| 95 | +++ b/hw/riscv/Kconfig | 695 | sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, |
| 96 | @@ -XXX,XX +XXX,XX @@ config RISCV_VIRT | 696 | - qdev_get_gpio_in(DEVICE(s->plic), RTC_IRQ)); |
| 97 | select SIFIVE_PLIC | 697 | + qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ)); |
| 98 | select SIFIVE_TEST | 698 | |
| 99 | select VIRTIO_MMIO | 699 | virt_flash_create(s); |
| 100 | + select FW_CFG_DMA | 700 | |
| 101 | 701 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine) | |
| 102 | config SIFIVE_E | 702 | drive_get(IF_PFLASH, 0, i)); |
| 103 | bool | 703 | } |
| 704 | virt_flash_map(s, system_memory); | ||
| 705 | - | ||
| 706 | - g_free(plic_hart_config); | ||
| 707 | } | ||
| 708 | |||
| 709 | static void virt_machine_instance_init(Object *obj) | ||
| 710 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data) | ||
| 711 | |||
| 712 | mc->desc = "RISC-V VirtIO board"; | ||
| 713 | mc->init = virt_machine_init; | ||
| 714 | - mc->max_cpus = 8; | ||
| 715 | + mc->max_cpus = VIRT_CPUS_MAX; | ||
| 716 | mc->default_cpu_type = VIRT_CPU; | ||
| 717 | mc->pci_allow_0_address = true; | ||
| 718 | + mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; | ||
| 719 | + mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; | ||
| 720 | + mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; | ||
| 721 | + mc->numa_mem_supported = true; | ||
| 722 | } | ||
| 723 | |||
| 724 | static const TypeInfo virt_machine_typeinfo = { | ||
| 104 | -- | 725 | -- |
| 105 | 2.30.1 | 726 | 2.28.0 |
| 106 | 727 | ||
| 107 | 728 | diff view generated by jsdifflib |
| 1 | From: Jim Shu <cwshu@andestech.com> | 1 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
|---|---|---|---|
| 2 | Message-id: 08cdefb171b1bdb0c9e3151c509aaadefc3dcd3e.1597259519.git.alistair.francis@wdc.com | ||
| 3 | Message-Id: <08cdefb171b1bdb0c9e3151c509aaadefc3dcd3e.1597259519.git.alistair.francis@wdc.com> | ||
| 4 | --- | ||
| 5 | target/riscv/cpu.h | 2 ++ | ||
| 6 | target/riscv/cpu_bits.h | 1 + | ||
| 7 | target/riscv/cpu_helper.c | 18 ++++++++++++++++++ | ||
| 8 | 3 files changed, 21 insertions(+) | ||
| 2 | 9 | ||
| 3 | Currently, PMP permission checking of TLB page is bypassed if TLB hits | 10 | diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h |
| 4 | Fix it by propagating PMP permission to TLB page permission. | ||
| 5 | |||
| 6 | PMP permission checking also use MMU-style API to change TLB permission | ||
| 7 | and size. | ||
| 8 | |||
| 9 | Signed-off-by: Jim Shu <cwshu@andestech.com> | ||
| 10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 11 | Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com | ||
| 12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 13 | --- | ||
| 14 | target/riscv/pmp.h | 4 +- | ||
| 15 | target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++---------- | ||
| 16 | target/riscv/pmp.c | 80 +++++++++++++++++++++++++++---------- | ||
| 17 | 3 files changed, 125 insertions(+), 43 deletions(-) | ||
| 18 | |||
| 19 | diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h | ||
| 20 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
| 21 | --- a/target/riscv/pmp.h | 12 | --- a/target/riscv/cpu.h |
| 22 | +++ b/target/riscv/pmp.h | 13 | +++ b/target/riscv/cpu.h |
| 23 | @@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, | 14 | @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_virt_enabled(CPURISCVState *env); |
| 24 | target_ulong val); | 15 | void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); |
| 25 | target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index); | 16 | bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); |
| 26 | bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, | 17 | void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); |
| 27 | - target_ulong size, pmp_priv_t priv, target_ulong mode); | 18 | +bool riscv_cpu_two_stage_lookup(CPURISCVState *env); |
| 28 | + target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs, | 19 | +void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable); |
| 29 | + target_ulong mode); | 20 | int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); |
| 30 | bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa, | 21 | hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
| 31 | target_ulong *tlb_size); | 22 | void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, |
| 32 | void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index); | 23 | diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h |
| 33 | void pmp_update_rule_nums(CPURISCVState *env); | 24 | index XXXXXXX..XXXXXXX 100644 |
| 34 | uint32_t pmp_get_num_rules(CPURISCVState *env); | 25 | --- a/target/riscv/cpu_bits.h |
| 35 | +int pmp_priv_to_page_prot(pmp_priv_t pmp_priv); | 26 | +++ b/target/riscv/cpu_bits.h |
| 36 | 27 | @@ -XXX,XX +XXX,XX @@ | |
| 37 | #endif | 28 | * page table fault. |
| 29 | */ | ||
| 30 | #define FORCE_HS_EXCEP 2 | ||
| 31 | +#define HS_TWO_STAGE 4 | ||
| 32 | |||
| 33 | /* RV32 satp CSR field masks */ | ||
| 34 | #define SATP32_MODE 0x80000000 | ||
| 38 | diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c | 35 | diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c |
| 39 | index XXXXXXX..XXXXXXX 100644 | 36 | index XXXXXXX..XXXXXXX 100644 |
| 40 | --- a/target/riscv/cpu_helper.c | 37 | --- a/target/riscv/cpu_helper.c |
| 41 | +++ b/target/riscv/cpu_helper.c | 38 | +++ b/target/riscv/cpu_helper.c |
| 42 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) | 39 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable) |
| 43 | env->load_res = -1; | 40 | env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable); |
| 44 | } | 41 | } |
| 45 | 42 | ||
| 46 | +/* | 43 | +bool riscv_cpu_two_stage_lookup(CPURISCVState *env) |
| 47 | + * get_physical_address_pmp - check PMP permission for this physical address | ||
| 48 | + * | ||
| 49 | + * Match the PMP region and check permission for this physical address and it's | ||
| 50 | + * TLB page. Returns 0 if the permission checking was successful | ||
| 51 | + * | ||
| 52 | + * @env: CPURISCVState | ||
| 53 | + * @prot: The returned protection attributes | ||
| 54 | + * @tlb_size: TLB page size containing addr. It could be modified after PMP | ||
| 55 | + * permission checking. NULL if not set TLB page for addr. | ||
| 56 | + * @addr: The physical address to be checked permission | ||
| 57 | + * @access_type: The type of MMU access | ||
| 58 | + * @mode: Indicates current privilege level. | ||
| 59 | + */ | ||
| 60 | +static int get_physical_address_pmp(CPURISCVState *env, int *prot, | ||
| 61 | + target_ulong *tlb_size, hwaddr addr, | ||
| 62 | + int size, MMUAccessType access_type, | ||
| 63 | + int mode) | ||
| 64 | +{ | 44 | +{ |
| 65 | + pmp_priv_t pmp_priv; | 45 | + if (!riscv_has_ext(env, RVH)) { |
| 66 | + target_ulong tlb_size_pmp = 0; | 46 | + return false; |
| 67 | + | ||
| 68 | + if (!riscv_feature(env, RISCV_FEATURE_PMP)) { | ||
| 69 | + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | ||
| 70 | + return TRANSLATE_SUCCESS; | ||
| 71 | + } | 47 | + } |
| 72 | + | 48 | + |
| 73 | + if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv, | 49 | + return get_field(env->virt, HS_TWO_STAGE); |
| 74 | + mode)) { | 50 | +} |
| 75 | + *prot = 0; | 51 | + |
| 76 | + return TRANSLATE_PMP_FAIL; | 52 | +void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable) |
| 53 | +{ | ||
| 54 | + if (!riscv_has_ext(env, RVH)) { | ||
| 55 | + return; | ||
| 77 | + } | 56 | + } |
| 78 | + | 57 | + |
| 79 | + *prot = pmp_priv_to_page_prot(pmp_priv); | 58 | + env->virt = set_field(env->virt, HS_TWO_STAGE, enable); |
| 80 | + if (tlb_size != NULL) { | ||
| 81 | + if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pmp)) { | ||
| 82 | + *tlb_size = tlb_size_pmp; | ||
| 83 | + } | ||
| 84 | + } | ||
| 85 | + | ||
| 86 | + return TRANSLATE_SUCCESS; | ||
| 87 | +} | 59 | +} |
| 88 | + | 60 | + |
| 89 | /* get_physical_address - get the physical address for this virtual address | 61 | int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) |
| 90 | * | ||
| 91 | * Do a page table walk to obtain the physical address corresponding to a | ||
| 92 | @@ -XXX,XX +XXX,XX @@ restart: | ||
| 93 | pte_addr = base + idx * ptesize; | ||
| 94 | } | ||
| 95 | |||
| 96 | - if (riscv_feature(env, RISCV_FEATURE_PMP) && | ||
| 97 | - !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong), | ||
| 98 | - 1 << MMU_DATA_LOAD, PRV_S)) { | ||
| 99 | + int pmp_prot; | ||
| 100 | + int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr, | ||
| 101 | + sizeof(target_ulong), | ||
| 102 | + MMU_DATA_LOAD, PRV_S); | ||
| 103 | + if (pmp_ret != TRANSLATE_SUCCESS) { | ||
| 104 | return TRANSLATE_PMP_FAIL; | ||
| 105 | } | ||
| 106 | |||
| 107 | @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | ||
| 108 | #ifndef CONFIG_USER_ONLY | ||
| 109 | vaddr im_address; | ||
| 110 | hwaddr pa = 0; | ||
| 111 | - int prot, prot2; | ||
| 112 | + int prot, prot2, prot_pmp; | ||
| 113 | bool pmp_violation = false; | ||
| 114 | bool first_stage_error = true; | ||
| 115 | bool two_stage_lookup = false; | ||
| 116 | int ret = TRANSLATE_FAIL; | ||
| 117 | int mode = mmu_idx; | ||
| 118 | - target_ulong tlb_size = 0; | ||
| 119 | + /* default TLB page size */ | ||
| 120 | + target_ulong tlb_size = TARGET_PAGE_SIZE; | ||
| 121 | |||
| 122 | env->guest_phys_fault_addr = 0; | ||
| 123 | |||
| 124 | @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | ||
| 125 | |||
| 126 | prot &= prot2; | ||
| 127 | |||
| 128 | - if (riscv_feature(env, RISCV_FEATURE_PMP) && | ||
| 129 | - (ret == TRANSLATE_SUCCESS) && | ||
| 130 | - !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) { | ||
| 131 | - ret = TRANSLATE_PMP_FAIL; | ||
| 132 | + if (ret == TRANSLATE_SUCCESS) { | ||
| 133 | + ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, | ||
| 134 | + size, access_type, mode); | ||
| 135 | + prot &= prot_pmp; | ||
| 136 | } | ||
| 137 | |||
| 138 | if (ret != TRANSLATE_SUCCESS) { | ||
| 139 | @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | ||
| 140 | "%s address=%" VADDR_PRIx " ret %d physical " | ||
| 141 | TARGET_FMT_plx " prot %d\n", | ||
| 142 | __func__, address, ret, pa, prot); | ||
| 143 | - } | ||
| 144 | |||
| 145 | - if (riscv_feature(env, RISCV_FEATURE_PMP) && | ||
| 146 | - (ret == TRANSLATE_SUCCESS) && | ||
| 147 | - !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) { | ||
| 148 | - ret = TRANSLATE_PMP_FAIL; | ||
| 149 | + if (ret == TRANSLATE_SUCCESS) { | ||
| 150 | + ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, | ||
| 151 | + size, access_type, mode); | ||
| 152 | + prot &= prot_pmp; | ||
| 153 | + } | ||
| 154 | } | ||
| 155 | + | ||
| 156 | if (ret == TRANSLATE_PMP_FAIL) { | ||
| 157 | pmp_violation = true; | ||
| 158 | } | ||
| 159 | |||
| 160 | if (ret == TRANSLATE_SUCCESS) { | ||
| 161 | - if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) { | ||
| 162 | - tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), | ||
| 163 | - prot, mmu_idx, tlb_size); | ||
| 164 | - } else { | ||
| 165 | - tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, | ||
| 166 | - prot, mmu_idx, TARGET_PAGE_SIZE); | ||
| 167 | - } | ||
| 168 | + tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), | ||
| 169 | + prot, mmu_idx, tlb_size); | ||
| 170 | return true; | ||
| 171 | } else if (probe) { | ||
| 172 | return false; | ||
| 173 | diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c | ||
| 174 | index XXXXXXX..XXXXXXX 100644 | ||
| 175 | --- a/target/riscv/pmp.c | ||
| 176 | +++ b/target/riscv/pmp.c | ||
| 177 | @@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr) | ||
| 178 | return result; | ||
| 179 | } | ||
| 180 | |||
| 181 | +/* | ||
| 182 | + * Check if the address has required RWX privs when no PMP entry is matched. | ||
| 183 | + */ | ||
| 184 | +static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr, | ||
| 185 | + target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs, | ||
| 186 | + target_ulong mode) | ||
| 187 | +{ | ||
| 188 | + bool ret; | ||
| 189 | + | ||
| 190 | + if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) { | ||
| 191 | + /* | ||
| 192 | + * Privileged spec v1.10 states if HW doesn't implement any PMP entry | ||
| 193 | + * or no PMP entry matches an M-Mode access, the access succeeds. | ||
| 194 | + */ | ||
| 195 | + ret = true; | ||
| 196 | + *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC; | ||
| 197 | + } else { | ||
| 198 | + /* | ||
| 199 | + * Other modes are not allowed to succeed if they don't * match a rule, | ||
| 200 | + * but there are rules. We've checked for no rule earlier in this | ||
| 201 | + * function. | ||
| 202 | + */ | ||
| 203 | + ret = false; | ||
| 204 | + *allowed_privs = 0; | ||
| 205 | + } | ||
| 206 | + | ||
| 207 | + return ret; | ||
| 208 | +} | ||
| 209 | + | ||
| 210 | |||
| 211 | /* | ||
| 212 | * Public Interface | ||
| 213 | @@ -XXX,XX +XXX,XX @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr) | ||
| 214 | * Check if the address has required RWX privs to complete desired operation | ||
| 215 | */ | ||
| 216 | bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, | ||
| 217 | - target_ulong size, pmp_priv_t privs, target_ulong mode) | ||
| 218 | + target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs, | ||
| 219 | + target_ulong mode) | ||
| 220 | { | 62 | { |
| 221 | int i = 0; | 63 | CPURISCVState *env = &cpu->env; |
| 222 | int ret = -1; | ||
| 223 | int pmp_size = 0; | ||
| 224 | target_ulong s = 0; | ||
| 225 | target_ulong e = 0; | ||
| 226 | - pmp_priv_t allowed_privs = 0; | ||
| 227 | |||
| 228 | /* Short cut if no rules */ | ||
| 229 | if (0 == pmp_get_num_rules(env)) { | ||
| 230 | - return (env->priv == PRV_M) ? true : false; | ||
| 231 | + return pmp_hart_has_privs_default(env, addr, size, privs, | ||
| 232 | + allowed_privs, mode); | ||
| 233 | } | ||
| 234 | |||
| 235 | if (size == 0) { | ||
| 236 | @@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, | ||
| 237 | * check | ||
| 238 | */ | ||
| 239 | if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) { | ||
| 240 | - allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC; | ||
| 241 | + *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC; | ||
| 242 | if ((mode != PRV_M) || pmp_is_locked(env, i)) { | ||
| 243 | - allowed_privs &= env->pmp_state.pmp[i].cfg_reg; | ||
| 244 | + *allowed_privs &= env->pmp_state.pmp[i].cfg_reg; | ||
| 245 | } | ||
| 246 | |||
| 247 | - if ((privs & allowed_privs) == privs) { | ||
| 248 | - ret = 1; | ||
| 249 | - break; | ||
| 250 | - } else { | ||
| 251 | - ret = 0; | ||
| 252 | - break; | ||
| 253 | - } | ||
| 254 | + ret = ((privs & *allowed_privs) == privs); | ||
| 255 | + break; | ||
| 256 | } | ||
| 257 | } | ||
| 258 | |||
| 259 | /* No rule matched */ | ||
| 260 | if (ret == -1) { | ||
| 261 | - if (mode == PRV_M) { | ||
| 262 | - ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an | ||
| 263 | - * M-Mode access, the access succeeds */ | ||
| 264 | - } else { | ||
| 265 | - ret = 0; /* Other modes are not allowed to succeed if they don't | ||
| 266 | - * match a rule, but there are rules. We've checked for | ||
| 267 | - * no rule earlier in this function. */ | ||
| 268 | - } | ||
| 269 | + return pmp_hart_has_privs_default(env, addr, size, privs, | ||
| 270 | + allowed_privs, mode); | ||
| 271 | } | ||
| 272 | |||
| 273 | return ret == 1 ? true : false; | ||
| 274 | } | ||
| 275 | |||
| 276 | - | ||
| 277 | /* | ||
| 278 | * Handle a write to a pmpcfg CSP | ||
| 279 | */ | ||
| 280 | @@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa, | ||
| 281 | |||
| 282 | return false; | ||
| 283 | } | ||
| 284 | + | ||
| 285 | +/* | ||
| 286 | + * Convert PMP privilege to TLB page privilege. | ||
| 287 | + */ | ||
| 288 | +int pmp_priv_to_page_prot(pmp_priv_t pmp_priv) | ||
| 289 | +{ | ||
| 290 | + int prot = 0; | ||
| 291 | + | ||
| 292 | + if (pmp_priv & PMP_READ) { | ||
| 293 | + prot |= PAGE_READ; | ||
| 294 | + } | ||
| 295 | + if (pmp_priv & PMP_WRITE) { | ||
| 296 | + prot |= PAGE_WRITE; | ||
| 297 | + } | ||
| 298 | + if (pmp_priv & PMP_EXEC) { | ||
| 299 | + prot |= PAGE_EXEC; | ||
| 300 | + } | ||
| 301 | + | ||
| 302 | + return prot; | ||
| 303 | +} | ||
| 304 | -- | 64 | -- |
| 305 | 2.30.1 | 65 | 2.28.0 |
| 306 | 66 | ||
| 307 | 67 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 2 | Message-id: 477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com | ||
| 3 | Message-Id: <477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com> | ||
| 4 | --- | ||
| 5 | target/riscv/cpu_bits.h | 1 + | ||
| 6 | target/riscv/helper.h | 3 + | ||
| 7 | target/riscv/insn32-64.decode | 5 + | ||
| 8 | target/riscv/insn32.decode | 11 + | ||
| 9 | target/riscv/op_helper.c | 114 ++++++++ | ||
| 10 | target/riscv/insn_trans/trans_rvh.c.inc | 340 ++++++++++++++++++++++++ | ||
| 11 | 6 files changed, 474 insertions(+) | ||
| 1 | 12 | ||
| 13 | diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/target/riscv/cpu_bits.h | ||
| 16 | +++ b/target/riscv/cpu_bits.h | ||
| 17 | @@ -XXX,XX +XXX,XX @@ | ||
| 18 | #define HSTATUS_SP2V 0x00000200 | ||
| 19 | #define HSTATUS_VTVM 0x00100000 | ||
| 20 | #define HSTATUS_VTSR 0x00400000 | ||
| 21 | +#define HSTATUS_HU 0x00000200 | ||
| 22 | |||
| 23 | #define HSTATUS32_WPRI 0xFF8FF87E | ||
| 24 | #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL | ||
| 25 | diff --git a/target/riscv/helper.h b/target/riscv/helper.h | ||
| 26 | index XXXXXXX..XXXXXXX 100644 | ||
| 27 | --- a/target/riscv/helper.h | ||
| 28 | +++ b/target/riscv/helper.h | ||
| 29 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(tlb_flush, void, env) | ||
| 30 | /* Hypervisor functions */ | ||
| 31 | #ifndef CONFIG_USER_ONLY | ||
| 32 | DEF_HELPER_1(hyp_tlb_flush, void, env) | ||
| 33 | +DEF_HELPER_4(hyp_load, tl, env, tl, tl, tl) | ||
| 34 | +DEF_HELPER_5(hyp_store, void, env, tl, tl, tl, tl) | ||
| 35 | +DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl) | ||
| 36 | #endif | ||
| 37 | |||
| 38 | /* Vector functions */ | ||
| 39 | diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode | ||
| 40 | index XXXXXXX..XXXXXXX 100644 | ||
| 41 | --- a/target/riscv/insn32-64.decode | ||
| 42 | +++ b/target/riscv/insn32-64.decode | ||
| 43 | @@ -XXX,XX +XXX,XX @@ fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2 | ||
| 44 | fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm | ||
| 45 | fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm | ||
| 46 | fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2 | ||
| 47 | + | ||
| 48 | +# *** RV32H Base Instruction Set *** | ||
| 49 | +hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2 | ||
| 50 | +hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2 | ||
| 51 | +hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s | ||
| 52 | diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode | ||
| 53 | index XXXXXXX..XXXXXXX 100644 | ||
| 54 | --- a/target/riscv/insn32.decode | ||
| 55 | +++ b/target/riscv/insn32.decode | ||
| 56 | @@ -XXX,XX +XXX,XX @@ | ||
| 57 | @r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd | ||
| 58 | @r_wdvm ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd | ||
| 59 | @r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd | ||
| 60 | +@r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 | ||
| 61 | |||
| 62 | @hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1 | ||
| 63 | @hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1 | ||
| 64 | @@ -XXX,XX +XXX,XX @@ fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm | ||
| 65 | fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm | ||
| 66 | |||
| 67 | # *** RV32H Base Instruction Set *** | ||
| 68 | +hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2 | ||
| 69 | +hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2 | ||
| 70 | +hlv_h 0110010 00000 ..... 100 ..... 1110011 @r2 | ||
| 71 | +hlv_hu 0110010 00001 ..... 100 ..... 1110011 @r2 | ||
| 72 | +hlvx_hu 0110010 00011 ..... 100 ..... 1110011 @r2 | ||
| 73 | +hlv_w 0110100 00000 ..... 100 ..... 1110011 @r2 | ||
| 74 | +hlvx_wu 0110100 00011 ..... 100 ..... 1110011 @r2 | ||
| 75 | +hsv_b 0110001 ..... ..... 100 00000 1110011 @r2_s | ||
| 76 | +hsv_h 0110011 ..... ..... 100 00000 1110011 @r2_s | ||
| 77 | +hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s | ||
| 78 | hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma | ||
| 79 | hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma | ||
| 80 | |||
| 81 | diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c | ||
| 82 | index XXXXXXX..XXXXXXX 100644 | ||
| 83 | --- a/target/riscv/op_helper.c | ||
| 84 | +++ b/target/riscv/op_helper.c | ||
| 85 | @@ -XXX,XX +XXX,XX @@ void helper_hyp_tlb_flush(CPURISCVState *env) | ||
| 86 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); | ||
| 87 | } | ||
| 88 | |||
| 89 | +target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address, | ||
| 90 | + target_ulong attrs, target_ulong memop) | ||
| 91 | +{ | ||
| 92 | + if (env->priv == PRV_M || | ||
| 93 | + (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || | ||
| 94 | + (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && | ||
| 95 | + get_field(env->hstatus, HSTATUS_HU))) { | ||
| 96 | + target_ulong pte; | ||
| 97 | + | ||
| 98 | + riscv_cpu_set_two_stage_lookup(env, true); | ||
| 99 | + | ||
| 100 | + switch (memop) { | ||
| 101 | + case MO_SB: | ||
| 102 | + pte = cpu_ldsb_data_ra(env, address, GETPC()); | ||
| 103 | + break; | ||
| 104 | + case MO_UB: | ||
| 105 | + pte = cpu_ldub_data_ra(env, address, GETPC()); | ||
| 106 | + break; | ||
| 107 | + case MO_TESW: | ||
| 108 | + pte = cpu_ldsw_data_ra(env, address, GETPC()); | ||
| 109 | + break; | ||
| 110 | + case MO_TEUW: | ||
| 111 | + pte = cpu_lduw_data_ra(env, address, GETPC()); | ||
| 112 | + break; | ||
| 113 | + case MO_TESL: | ||
| 114 | + pte = cpu_ldl_data_ra(env, address, GETPC()); | ||
| 115 | + break; | ||
| 116 | + case MO_TEUL: | ||
| 117 | + pte = cpu_ldl_data_ra(env, address, GETPC()); | ||
| 118 | + break; | ||
| 119 | + case MO_TEQ: | ||
| 120 | + pte = cpu_ldq_data_ra(env, address, GETPC()); | ||
| 121 | + break; | ||
| 122 | + default: | ||
| 123 | + g_assert_not_reached(); | ||
| 124 | + } | ||
| 125 | + | ||
| 126 | + riscv_cpu_set_two_stage_lookup(env, false); | ||
| 127 | + | ||
| 128 | + return pte; | ||
| 129 | + } | ||
| 130 | + | ||
| 131 | + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); | ||
| 132 | + return 0; | ||
| 133 | +} | ||
| 134 | + | ||
| 135 | +void helper_hyp_store(CPURISCVState *env, target_ulong address, | ||
| 136 | + target_ulong val, target_ulong attrs, target_ulong memop) | ||
| 137 | +{ | ||
| 138 | + if (env->priv == PRV_M || | ||
| 139 | + (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || | ||
| 140 | + (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && | ||
| 141 | + get_field(env->hstatus, HSTATUS_HU))) { | ||
| 142 | + riscv_cpu_set_two_stage_lookup(env, true); | ||
| 143 | + | ||
| 144 | + switch (memop) { | ||
| 145 | + case MO_SB: | ||
| 146 | + case MO_UB: | ||
| 147 | + cpu_stb_data_ra(env, address, val, GETPC()); | ||
| 148 | + break; | ||
| 149 | + case MO_TESW: | ||
| 150 | + case MO_TEUW: | ||
| 151 | + cpu_stw_data_ra(env, address, val, GETPC()); | ||
| 152 | + break; | ||
| 153 | + case MO_TESL: | ||
| 154 | + case MO_TEUL: | ||
| 155 | + cpu_stl_data_ra(env, address, val, GETPC()); | ||
| 156 | + break; | ||
| 157 | + case MO_TEQ: | ||
| 158 | + cpu_stq_data_ra(env, address, val, GETPC()); | ||
| 159 | + break; | ||
| 160 | + default: | ||
| 161 | + g_assert_not_reached(); | ||
| 162 | + } | ||
| 163 | + | ||
| 164 | + riscv_cpu_set_two_stage_lookup(env, false); | ||
| 165 | + | ||
| 166 | + return; | ||
| 167 | + } | ||
| 168 | + | ||
| 169 | + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); | ||
| 170 | +} | ||
| 171 | + | ||
| 172 | +target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address, | ||
| 173 | + target_ulong attrs, target_ulong memop) | ||
| 174 | +{ | ||
| 175 | + if (env->priv == PRV_M || | ||
| 176 | + (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || | ||
| 177 | + (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && | ||
| 178 | + get_field(env->hstatus, HSTATUS_HU))) { | ||
| 179 | + target_ulong pte; | ||
| 180 | + | ||
| 181 | + riscv_cpu_set_two_stage_lookup(env, true); | ||
| 182 | + | ||
| 183 | + switch (memop) { | ||
| 184 | + case MO_TEUL: | ||
| 185 | + pte = cpu_ldub_data_ra(env, address, GETPC()); | ||
| 186 | + break; | ||
| 187 | + case MO_TEUW: | ||
| 188 | + pte = cpu_lduw_data_ra(env, address, GETPC()); | ||
| 189 | + break; | ||
| 190 | + default: | ||
| 191 | + g_assert_not_reached(); | ||
| 192 | + } | ||
| 193 | + | ||
| 194 | + riscv_cpu_set_two_stage_lookup(env, false); | ||
| 195 | + | ||
| 196 | + return pte; | ||
| 197 | + } | ||
| 198 | + | ||
| 199 | + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); | ||
| 200 | + return 0; | ||
| 201 | +} | ||
| 202 | + | ||
| 203 | #endif /* !CONFIG_USER_ONLY */ | ||
| 204 | diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc | ||
| 205 | index XXXXXXX..XXXXXXX 100644 | ||
| 206 | --- a/target/riscv/insn_trans/trans_rvh.c.inc | ||
| 207 | +++ b/target/riscv/insn_trans/trans_rvh.c.inc | ||
| 208 | @@ -XXX,XX +XXX,XX @@ | ||
| 209 | * this program. If not, see <http://www.gnu.org/licenses/>. | ||
| 210 | */ | ||
| 211 | |||
| 212 | +static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a) | ||
| 213 | +{ | ||
| 214 | + REQUIRE_EXT(ctx, RVH); | ||
| 215 | +#ifndef CONFIG_USER_ONLY | ||
| 216 | + TCGv t0 = tcg_temp_new(); | ||
| 217 | + TCGv t1 = tcg_temp_new(); | ||
| 218 | + TCGv mem_idx = tcg_temp_new(); | ||
| 219 | + TCGv memop = tcg_temp_new(); | ||
| 220 | + | ||
| 221 | + gen_get_gpr(t0, a->rs1); | ||
| 222 | + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); | ||
| 223 | + tcg_gen_movi_tl(memop, MO_SB); | ||
| 224 | + | ||
| 225 | + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); | ||
| 226 | + gen_set_gpr(a->rd, t1); | ||
| 227 | + | ||
| 228 | + tcg_temp_free(t0); | ||
| 229 | + tcg_temp_free(t1); | ||
| 230 | + tcg_temp_free(mem_idx); | ||
| 231 | + tcg_temp_free(memop); | ||
| 232 | + return true; | ||
| 233 | +#else | ||
| 234 | + return false; | ||
| 235 | +#endif | ||
| 236 | +} | ||
| 237 | + | ||
| 238 | +static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a) | ||
| 239 | +{ | ||
| 240 | + REQUIRE_EXT(ctx, RVH); | ||
| 241 | +#ifndef CONFIG_USER_ONLY | ||
| 242 | + TCGv t0 = tcg_temp_new(); | ||
| 243 | + TCGv t1 = tcg_temp_new(); | ||
| 244 | + TCGv mem_idx = tcg_temp_new(); | ||
| 245 | + TCGv memop = tcg_temp_new(); | ||
| 246 | + | ||
| 247 | + gen_get_gpr(t0, a->rs1); | ||
| 248 | + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); | ||
| 249 | + tcg_gen_movi_tl(memop, MO_TESW); | ||
| 250 | + | ||
| 251 | + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); | ||
| 252 | + gen_set_gpr(a->rd, t1); | ||
| 253 | + | ||
| 254 | + tcg_temp_free(t0); | ||
| 255 | + tcg_temp_free(t1); | ||
| 256 | + tcg_temp_free(mem_idx); | ||
| 257 | + tcg_temp_free(memop); | ||
| 258 | + return true; | ||
| 259 | +#else | ||
| 260 | + return false; | ||
| 261 | +#endif | ||
| 262 | +} | ||
| 263 | + | ||
| 264 | +static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a) | ||
| 265 | +{ | ||
| 266 | + REQUIRE_EXT(ctx, RVH); | ||
| 267 | +#ifndef CONFIG_USER_ONLY | ||
| 268 | + TCGv t0 = tcg_temp_new(); | ||
| 269 | + TCGv t1 = tcg_temp_new(); | ||
| 270 | + TCGv mem_idx = tcg_temp_new(); | ||
| 271 | + TCGv memop = tcg_temp_new(); | ||
| 272 | + | ||
| 273 | + gen_get_gpr(t0, a->rs1); | ||
| 274 | + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); | ||
| 275 | + tcg_gen_movi_tl(memop, MO_TESL); | ||
| 276 | + | ||
| 277 | + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); | ||
| 278 | + gen_set_gpr(a->rd, t1); | ||
| 279 | + | ||
| 280 | + tcg_temp_free(t0); | ||
| 281 | + tcg_temp_free(t1); | ||
| 282 | + tcg_temp_free(mem_idx); | ||
| 283 | + tcg_temp_free(memop); | ||
| 284 | + return true; | ||
| 285 | +#else | ||
| 286 | + return false; | ||
| 287 | +#endif | ||
| 288 | +} | ||
| 289 | + | ||
| 290 | +static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu *a) | ||
| 291 | +{ | ||
| 292 | + REQUIRE_EXT(ctx, RVH); | ||
| 293 | +#ifndef CONFIG_USER_ONLY | ||
| 294 | + TCGv t0 = tcg_temp_new(); | ||
| 295 | + TCGv t1 = tcg_temp_new(); | ||
| 296 | + TCGv mem_idx = tcg_temp_new(); | ||
| 297 | + TCGv memop = tcg_temp_new(); | ||
| 298 | + | ||
| 299 | + gen_get_gpr(t0, a->rs1); | ||
| 300 | + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); | ||
| 301 | + tcg_gen_movi_tl(memop, MO_UB); | ||
| 302 | + | ||
| 303 | + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); | ||
| 304 | + gen_set_gpr(a->rd, t1); | ||
| 305 | + | ||
| 306 | + tcg_temp_free(t0); | ||
| 307 | + tcg_temp_free(t1); | ||
| 308 | + tcg_temp_free(mem_idx); | ||
| 309 | + tcg_temp_free(memop); | ||
| 310 | + return true; | ||
| 311 | +#else | ||
| 312 | + return false; | ||
| 313 | +#endif | ||
| 314 | +} | ||
| 315 | + | ||
| 316 | +static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu *a) | ||
| 317 | +{ | ||
| 318 | + REQUIRE_EXT(ctx, RVH); | ||
| 319 | +#ifndef CONFIG_USER_ONLY | ||
| 320 | + TCGv t0 = tcg_temp_new(); | ||
| 321 | + TCGv t1 = tcg_temp_new(); | ||
| 322 | + TCGv mem_idx = tcg_temp_new(); | ||
| 323 | + TCGv memop = tcg_temp_new(); | ||
| 324 | + | ||
| 325 | + gen_get_gpr(t0, a->rs1); | ||
| 326 | + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); | ||
| 327 | + tcg_gen_movi_tl(memop, MO_TEUW); | ||
| 328 | + | ||
| 329 | + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); | ||
| 330 | + gen_set_gpr(a->rd, t1); | ||
| 331 | + | ||
| 332 | + tcg_temp_free(t0); | ||
| 333 | + tcg_temp_free(t1); | ||
| 334 | + tcg_temp_free(mem_idx); | ||
| 335 | + tcg_temp_free(memop); | ||
| 336 | + return true; | ||
| 337 | +#else | ||
| 338 | + return false; | ||
| 339 | +#endif | ||
| 340 | +} | ||
| 341 | + | ||
| 342 | +static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a) | ||
| 343 | +{ | ||
| 344 | + REQUIRE_EXT(ctx, RVH); | ||
| 345 | +#ifndef CONFIG_USER_ONLY | ||
| 346 | + TCGv t0 = tcg_temp_new(); | ||
| 347 | + TCGv dat = tcg_temp_new(); | ||
| 348 | + TCGv mem_idx = tcg_temp_new(); | ||
| 349 | + TCGv memop = tcg_temp_new(); | ||
| 350 | + | ||
| 351 | + gen_get_gpr(t0, a->rs1); | ||
| 352 | + gen_get_gpr(dat, a->rs2); | ||
| 353 | + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); | ||
| 354 | + tcg_gen_movi_tl(memop, MO_SB); | ||
| 355 | + | ||
| 356 | + gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); | ||
| 357 | + | ||
| 358 | + tcg_temp_free(t0); | ||
| 359 | + tcg_temp_free(dat); | ||
| 360 | + tcg_temp_free(mem_idx); | ||
| 361 | + tcg_temp_free(memop); | ||
| 362 | + return true; | ||
| 363 | +#else | ||
| 364 | + return false; | ||
| 365 | +#endif | ||
| 366 | +} | ||
| 367 | + | ||
| 368 | +static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a) | ||
| 369 | +{ | ||
| 370 | + REQUIRE_EXT(ctx, RVH); | ||
| 371 | +#ifndef CONFIG_USER_ONLY | ||
| 372 | + TCGv t0 = tcg_temp_new(); | ||
| 373 | + TCGv dat = tcg_temp_new(); | ||
| 374 | + TCGv mem_idx = tcg_temp_new(); | ||
| 375 | + TCGv memop = tcg_temp_new(); | ||
| 376 | + | ||
| 377 | + gen_get_gpr(t0, a->rs1); | ||
| 378 | + gen_get_gpr(dat, a->rs2); | ||
| 379 | + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); | ||
| 380 | + tcg_gen_movi_tl(memop, MO_TESW); | ||
| 381 | + | ||
| 382 | + gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); | ||
| 383 | + | ||
| 384 | + tcg_temp_free(t0); | ||
| 385 | + tcg_temp_free(dat); | ||
| 386 | + tcg_temp_free(mem_idx); | ||
| 387 | + tcg_temp_free(memop); | ||
| 388 | + return true; | ||
| 389 | +#else | ||
| 390 | + return false; | ||
| 391 | +#endif | ||
| 392 | +} | ||
| 393 | + | ||
| 394 | +static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a) | ||
| 395 | +{ | ||
| 396 | + REQUIRE_EXT(ctx, RVH); | ||
| 397 | +#ifndef CONFIG_USER_ONLY | ||
| 398 | + TCGv t0 = tcg_temp_new(); | ||
| 399 | + TCGv dat = tcg_temp_new(); | ||
| 400 | + TCGv mem_idx = tcg_temp_new(); | ||
| 401 | + TCGv memop = tcg_temp_new(); | ||
| 402 | + | ||
| 403 | + gen_get_gpr(t0, a->rs1); | ||
| 404 | + gen_get_gpr(dat, a->rs2); | ||
| 405 | + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); | ||
| 406 | + tcg_gen_movi_tl(memop, MO_TESL); | ||
| 407 | + | ||
| 408 | + gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); | ||
| 409 | + | ||
| 410 | + tcg_temp_free(t0); | ||
| 411 | + tcg_temp_free(dat); | ||
| 412 | + tcg_temp_free(mem_idx); | ||
| 413 | + tcg_temp_free(memop); | ||
| 414 | + return true; | ||
| 415 | +#else | ||
| 416 | + return false; | ||
| 417 | +#endif | ||
| 418 | +} | ||
| 419 | + | ||
| 420 | +#ifdef TARGET_RISCV64 | ||
| 421 | +static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a) | ||
| 422 | +{ | ||
| 423 | + REQUIRE_EXT(ctx, RVH); | ||
| 424 | +#ifndef CONFIG_USER_ONLY | ||
| 425 | + TCGv t0 = tcg_temp_new(); | ||
| 426 | + TCGv t1 = tcg_temp_new(); | ||
| 427 | + TCGv mem_idx = tcg_temp_new(); | ||
| 428 | + TCGv memop = tcg_temp_new(); | ||
| 429 | + | ||
| 430 | + gen_get_gpr(t0, a->rs1); | ||
| 431 | + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); | ||
| 432 | + tcg_gen_movi_tl(memop, MO_TEUL); | ||
| 433 | + | ||
| 434 | + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); | ||
| 435 | + gen_set_gpr(a->rd, t1); | ||
| 436 | + | ||
| 437 | + tcg_temp_free(t0); | ||
| 438 | + tcg_temp_free(t1); | ||
| 439 | + tcg_temp_free(mem_idx); | ||
| 440 | + tcg_temp_free(memop); | ||
| 441 | + return true; | ||
| 442 | +#else | ||
| 443 | + return false; | ||
| 444 | +#endif | ||
| 445 | +} | ||
| 446 | + | ||
| 447 | +static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a) | ||
| 448 | +{ | ||
| 449 | + REQUIRE_EXT(ctx, RVH); | ||
| 450 | +#ifndef CONFIG_USER_ONLY | ||
| 451 | + TCGv t0 = tcg_temp_new(); | ||
| 452 | + TCGv t1 = tcg_temp_new(); | ||
| 453 | + TCGv mem_idx = tcg_temp_new(); | ||
| 454 | + TCGv memop = tcg_temp_new(); | ||
| 455 | + | ||
| 456 | + gen_get_gpr(t0, a->rs1); | ||
| 457 | + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); | ||
| 458 | + tcg_gen_movi_tl(memop, MO_TEQ); | ||
| 459 | + | ||
| 460 | + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); | ||
| 461 | + gen_set_gpr(a->rd, t1); | ||
| 462 | + | ||
| 463 | + tcg_temp_free(t0); | ||
| 464 | + tcg_temp_free(t1); | ||
| 465 | + tcg_temp_free(mem_idx); | ||
| 466 | + tcg_temp_free(memop); | ||
| 467 | + return true; | ||
| 468 | +#else | ||
| 469 | + return false; | ||
| 470 | +#endif | ||
| 471 | +} | ||
| 472 | + | ||
| 473 | +static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a) | ||
| 474 | +{ | ||
| 475 | + REQUIRE_EXT(ctx, RVH); | ||
| 476 | +#ifndef CONFIG_USER_ONLY | ||
| 477 | + TCGv t0 = tcg_temp_new(); | ||
| 478 | + TCGv dat = tcg_temp_new(); | ||
| 479 | + TCGv mem_idx = tcg_temp_new(); | ||
| 480 | + TCGv memop = tcg_temp_new(); | ||
| 481 | + | ||
| 482 | + gen_get_gpr(t0, a->rs1); | ||
| 483 | + gen_get_gpr(dat, a->rs2); | ||
| 484 | + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); | ||
| 485 | + tcg_gen_movi_tl(memop, MO_TEQ); | ||
| 486 | + | ||
| 487 | + gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); | ||
| 488 | + | ||
| 489 | + tcg_temp_free(t0); | ||
| 490 | + tcg_temp_free(dat); | ||
| 491 | + tcg_temp_free(mem_idx); | ||
| 492 | + tcg_temp_free(memop); | ||
| 493 | + return true; | ||
| 494 | +#else | ||
| 495 | + return false; | ||
| 496 | +#endif | ||
| 497 | +} | ||
| 498 | +#endif | ||
| 499 | + | ||
| 500 | +static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a) | ||
| 501 | +{ | ||
| 502 | + REQUIRE_EXT(ctx, RVH); | ||
| 503 | +#ifndef CONFIG_USER_ONLY | ||
| 504 | + TCGv t0 = tcg_temp_new(); | ||
| 505 | + TCGv t1 = tcg_temp_new(); | ||
| 506 | + TCGv mem_idx = tcg_temp_new(); | ||
| 507 | + TCGv memop = tcg_temp_new(); | ||
| 508 | + | ||
| 509 | + gen_get_gpr(t0, a->rs1); | ||
| 510 | + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); | ||
| 511 | + tcg_gen_movi_tl(memop, MO_TEUW); | ||
| 512 | + | ||
| 513 | + gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop); | ||
| 514 | + gen_set_gpr(a->rd, t1); | ||
| 515 | + | ||
| 516 | + tcg_temp_free(t0); | ||
| 517 | + tcg_temp_free(t1); | ||
| 518 | + tcg_temp_free(mem_idx); | ||
| 519 | + tcg_temp_free(memop); | ||
| 520 | + return true; | ||
| 521 | +#else | ||
| 522 | + return false; | ||
| 523 | +#endif | ||
| 524 | +} | ||
| 525 | + | ||
| 526 | +static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx_wu *a) | ||
| 527 | +{ | ||
| 528 | + REQUIRE_EXT(ctx, RVH); | ||
| 529 | +#ifndef CONFIG_USER_ONLY | ||
| 530 | + TCGv t0 = tcg_temp_new(); | ||
| 531 | + TCGv t1 = tcg_temp_new(); | ||
| 532 | + TCGv mem_idx = tcg_temp_new(); | ||
| 533 | + TCGv memop = tcg_temp_new(); | ||
| 534 | + | ||
| 535 | + gen_get_gpr(t0, a->rs1); | ||
| 536 | + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); | ||
| 537 | + tcg_gen_movi_tl(memop, MO_TEUL); | ||
| 538 | + | ||
| 539 | + gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop); | ||
| 540 | + gen_set_gpr(a->rd, t1); | ||
| 541 | + | ||
| 542 | + tcg_temp_free(t0); | ||
| 543 | + tcg_temp_free(t1); | ||
| 544 | + tcg_temp_free(mem_idx); | ||
| 545 | + tcg_temp_free(memop); | ||
| 546 | + return true; | ||
| 547 | +#else | ||
| 548 | + return false; | ||
| 549 | +#endif | ||
| 550 | +} | ||
| 551 | + | ||
| 552 | static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) | ||
| 553 | { | ||
| 554 | REQUIRE_EXT(ctx, RVH); | ||
| 555 | -- | ||
| 556 | 2.28.0 | ||
| 557 | |||
| 558 | diff view generated by jsdifflib |
| 1 | From: Georg Kotheimer <georg.kotheimer@kernkonzept.com> | ||
|---|---|---|---|
| 2 | |||
| 3 | The current condition for the use of background registers only | ||
| 4 | considers the hypervisor load and store instructions, | ||
| 5 | but not accesses from M mode via MSTATUS_MPRV+MPV. | ||
| 6 | |||
| 7 | Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com> | ||
| 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 9 | Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com | ||
| 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 1 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 2 | Message-id: 024ad8a594fb2feaf0950fbfad1508cfa82ce7f0.1597259519.git.alistair.francis@wdc.com | ||
| 3 | Message-Id: <024ad8a594fb2feaf0950fbfad1508cfa82ce7f0.1597259519.git.alistair.francis@wdc.com> | ||
| 11 | --- | 4 | --- |
| 12 | target/riscv/cpu_helper.c | 2 +- | 5 | target/riscv/cpu_helper.c | 60 ++++++++++++++++----------------------- |
| 13 | 1 file changed, 1 insertion(+), 1 deletion(-) | 6 | 1 file changed, 25 insertions(+), 35 deletions(-) |
| 14 | 7 | ||
| 15 | diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c | 8 | diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c |
| 16 | index XXXXXXX..XXXXXXX 100644 | 9 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/target/riscv/cpu_helper.c | 10 | --- a/target/riscv/cpu_helper.c |
| 18 | +++ b/target/riscv/cpu_helper.c | 11 | +++ b/target/riscv/cpu_helper.c |
| 19 | @@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, | 12 | @@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, |
| 20 | * was called. Background registers will be used if the guest has | 13 | * was called. Background registers will be used if the guest has |
| 21 | * forced a two stage translation to be on (in HS or M mode). | 14 | * forced a two stage translation to be on (in HS or M mode). |
| 22 | */ | 15 | */ |
| 23 | - if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) { | 16 | + if (riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH) { |
| 24 | + if (!riscv_cpu_virt_enabled(env) && two_stage) { | 17 | + use_background = true; |
| 25 | use_background = true; | 18 | + } |
| 19 | + | ||
| 20 | if (mode == PRV_M && access_type != MMU_INST_FETCH) { | ||
| 21 | if (get_field(env->mstatus, MSTATUS_MPRV)) { | ||
| 22 | mode = get_field(env->mstatus, MSTATUS_MPP); | ||
| 23 | - | ||
| 24 | - if (riscv_has_ext(env, RVH) && | ||
| 25 | - MSTATUS_MPV_ISSET(env)) { | ||
| 26 | - use_background = true; | ||
| 27 | - } | ||
| 28 | - } | ||
| 29 | - } | ||
| 30 | - | ||
| 31 | - if (mode == PRV_S && access_type != MMU_INST_FETCH && | ||
| 32 | - riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) { | ||
| 33 | - if (get_field(env->hstatus, HSTATUS_SPRV)) { | ||
| 34 | - mode = get_field(env->mstatus, SSTATUS_SPP); | ||
| 35 | - use_background = true; | ||
| 36 | } | ||
| 26 | } | 37 | } |
| 27 | 38 | ||
| 39 | @@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address, | ||
| 40 | } | ||
| 41 | break; | ||
| 42 | case MMU_DATA_LOAD: | ||
| 43 | - if (riscv_cpu_virt_enabled(env) && !first_stage) { | ||
| 44 | + if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env)) && | ||
| 45 | + !first_stage) { | ||
| 46 | cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; | ||
| 47 | } else { | ||
| 48 | cs->exception_index = page_fault_exceptions ? | ||
| 49 | @@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address, | ||
| 50 | } | ||
| 51 | break; | ||
| 52 | case MMU_DATA_STORE: | ||
| 53 | - if (riscv_cpu_virt_enabled(env) && !first_stage) { | ||
| 54 | + if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env)) && | ||
| 55 | + !first_stage) { | ||
| 56 | cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; | ||
| 57 | } else { | ||
| 58 | cs->exception_index = page_fault_exceptions ? | ||
| 59 | @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | ||
| 60 | hwaddr pa = 0; | ||
| 61 | int prot, prot2; | ||
| 62 | bool pmp_violation = false; | ||
| 63 | - bool m_mode_two_stage = false; | ||
| 64 | - bool hs_mode_two_stage = false; | ||
| 65 | bool first_stage_error = true; | ||
| 66 | int ret = TRANSLATE_FAIL; | ||
| 67 | int mode = mmu_idx; | ||
| 68 | @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | ||
| 69 | qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", | ||
| 70 | __func__, address, access_type, mmu_idx); | ||
| 71 | |||
| 72 | - /* | ||
| 73 | - * Determine if we are in M mode and MPRV is set or in HS mode and SPRV is | ||
| 74 | - * set and we want to access a virtulisation address. | ||
| 75 | - */ | ||
| 76 | - if (riscv_has_ext(env, RVH)) { | ||
| 77 | - m_mode_two_stage = env->priv == PRV_M && | ||
| 78 | - access_type != MMU_INST_FETCH && | ||
| 79 | - get_field(env->mstatus, MSTATUS_MPRV) && | ||
| 80 | - MSTATUS_MPV_ISSET(env); | ||
| 81 | - | ||
| 82 | - hs_mode_two_stage = env->priv == PRV_S && | ||
| 83 | - !riscv_cpu_virt_enabled(env) && | ||
| 84 | - access_type != MMU_INST_FETCH && | ||
| 85 | - get_field(env->hstatus, HSTATUS_SPRV) && | ||
| 86 | - get_field(env->hstatus, HSTATUS_SPV); | ||
| 87 | - } | ||
| 88 | - | ||
| 89 | if (mode == PRV_M && access_type != MMU_INST_FETCH) { | ||
| 90 | if (get_field(env->mstatus, MSTATUS_MPRV)) { | ||
| 91 | mode = get_field(env->mstatus, MSTATUS_MPP); | ||
| 92 | } | ||
| 93 | } | ||
| 94 | |||
| 95 | - if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_stage) { | ||
| 96 | + if (riscv_has_ext(env, RVH) && env->priv == PRV_M && | ||
| 97 | + access_type != MMU_INST_FETCH && | ||
| 98 | + get_field(env->mstatus, MSTATUS_MPRV) && | ||
| 99 | + MSTATUS_MPV_ISSET(env)) { | ||
| 100 | + riscv_cpu_set_two_stage_lookup(env, true); | ||
| 101 | + } | ||
| 102 | + | ||
| 103 | + if (riscv_cpu_virt_enabled(env) || | ||
| 104 | + (riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH)) { | ||
| 105 | /* Two stage lookup */ | ||
| 106 | ret = get_physical_address(env, &pa, &prot, address, access_type, | ||
| 107 | mmu_idx, true, true); | ||
| 108 | @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | ||
| 109 | __func__, address, ret, pa, prot); | ||
| 110 | } | ||
| 111 | |||
| 112 | + /* We did the two stage lookup based on MPRV, unset the lookup */ | ||
| 113 | + if (riscv_has_ext(env, RVH) && env->priv == PRV_M && | ||
| 114 | + access_type != MMU_INST_FETCH && | ||
| 115 | + get_field(env->mstatus, MSTATUS_MPRV) && | ||
| 116 | + MSTATUS_MPV_ISSET(env)) { | ||
| 117 | + riscv_cpu_set_two_stage_lookup(env, false); | ||
| 118 | + } | ||
| 119 | + | ||
| 120 | if (riscv_feature(env, RISCV_FEATURE_PMP) && | ||
| 121 | (ret == TRANSLATE_SUCCESS) && | ||
| 122 | !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) { | ||
| 28 | -- | 123 | -- |
| 29 | 2.30.1 | 124 | 2.28.0 |
| 30 | 125 | ||
| 31 | 126 | diff view generated by jsdifflib |
| 1 | From: Georg Kotheimer <georg.kotheimer@kernkonzept.com> | 1 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
|---|---|---|---|
| 2 | Message-id: ca5359fec6b2aff851eef3b3bc4b53cb5d4ad194.1597259519.git.alistair.francis@wdc.com | ||
| 3 | Message-Id: <ca5359fec6b2aff851eef3b3bc4b53cb5d4ad194.1597259519.git.alistair.francis@wdc.com> | ||
| 4 | --- | ||
| 5 | target/riscv/csr.c | 1 - | ||
| 6 | 1 file changed, 1 deletion(-) | ||
| 2 | 7 | ||
| 3 | When decode_insn16() fails, we fall back to decode_RV32_64C() for | 8 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c |
| 4 | further compressed instruction decoding. However, prior to this change, | ||
| 5 | we did not raise an illegal instruction exception, if decode_RV32_64C() | ||
| 6 | fails to decode the instruction. This means that we skipped illegal | ||
| 7 | compressed instructions instead of raising an illegal instruction | ||
| 8 | exception. | ||
| 9 | |||
| 10 | Instead of patching decode_RV32_64C(), we can just remove it, | ||
| 11 | as it is dead code since f330433b363 anyway. | ||
| 12 | |||
| 13 | Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com> | ||
| 14 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 15 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 16 | Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com | ||
| 17 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 18 | --- | ||
| 19 | target/riscv/translate.c | 179 +-------------------------------------- | ||
| 20 | 1 file changed, 1 insertion(+), 178 deletions(-) | ||
| 21 | |||
| 22 | diff --git a/target/riscv/translate.c b/target/riscv/translate.c | ||
| 23 | index XXXXXXX..XXXXXXX 100644 | 9 | index XXXXXXX..XXXXXXX 100644 |
| 24 | --- a/target/riscv/translate.c | 10 | --- a/target/riscv/csr.c |
| 25 | +++ b/target/riscv/translate.c | 11 | +++ b/target/riscv/csr.c |
| 26 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { | 12 | @@ -XXX,XX +XXX,XX @@ static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val) |
| 27 | CPUState *cs; | 13 | |
| 28 | } DisasContext; | 14 | static int write_htinst(CPURISCVState *env, int csrno, target_ulong val) |
| 29 | 15 | { | |
| 30 | -#ifdef TARGET_RISCV64 | 16 | - env->htinst = val; |
| 31 | -/* convert riscv funct3 to qemu memop for load/store */ | 17 | return 0; |
| 32 | -static const int tcg_memop_lookup[8] = { | ||
| 33 | - [0 ... 7] = -1, | ||
| 34 | - [0] = MO_SB, | ||
| 35 | - [1] = MO_TESW, | ||
| 36 | - [2] = MO_TESL, | ||
| 37 | - [3] = MO_TEQ, | ||
| 38 | - [4] = MO_UB, | ||
| 39 | - [5] = MO_TEUW, | ||
| 40 | - [6] = MO_TEUL, | ||
| 41 | -}; | ||
| 42 | -#endif | ||
| 43 | - | ||
| 44 | #ifdef TARGET_RISCV64 | ||
| 45 | #define CASE_OP_32_64(X) case X: case glue(X, W) | ||
| 46 | #else | ||
| 47 | @@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) | ||
| 48 | ctx->base.is_jmp = DISAS_NORETURN; | ||
| 49 | } | 18 | } |
| 50 | 19 | ||
| 51 | -#ifdef TARGET_RISCV64 | ||
| 52 | -static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1, | ||
| 53 | - target_long imm) | ||
| 54 | -{ | ||
| 55 | - TCGv t0 = tcg_temp_new(); | ||
| 56 | - TCGv t1 = tcg_temp_new(); | ||
| 57 | - gen_get_gpr(t0, rs1); | ||
| 58 | - tcg_gen_addi_tl(t0, t0, imm); | ||
| 59 | - int memop = tcg_memop_lookup[(opc >> 12) & 0x7]; | ||
| 60 | - | ||
| 61 | - if (memop < 0) { | ||
| 62 | - gen_exception_illegal(ctx); | ||
| 63 | - return; | ||
| 64 | - } | ||
| 65 | - | ||
| 66 | - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop); | ||
| 67 | - gen_set_gpr(rd, t1); | ||
| 68 | - tcg_temp_free(t0); | ||
| 69 | - tcg_temp_free(t1); | ||
| 70 | -} | ||
| 71 | - | ||
| 72 | -static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2, | ||
| 73 | - target_long imm) | ||
| 74 | -{ | ||
| 75 | - TCGv t0 = tcg_temp_new(); | ||
| 76 | - TCGv dat = tcg_temp_new(); | ||
| 77 | - gen_get_gpr(t0, rs1); | ||
| 78 | - tcg_gen_addi_tl(t0, t0, imm); | ||
| 79 | - gen_get_gpr(dat, rs2); | ||
| 80 | - int memop = tcg_memop_lookup[(opc >> 12) & 0x7]; | ||
| 81 | - | ||
| 82 | - if (memop < 0) { | ||
| 83 | - gen_exception_illegal(ctx); | ||
| 84 | - return; | ||
| 85 | - } | ||
| 86 | - | ||
| 87 | - tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop); | ||
| 88 | - tcg_temp_free(t0); | ||
| 89 | - tcg_temp_free(dat); | ||
| 90 | -} | ||
| 91 | -#endif | ||
| 92 | - | ||
| 93 | #ifndef CONFIG_USER_ONLY | ||
| 94 | /* The states of mstatus_fs are: | ||
| 95 | * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty | ||
| 96 | @@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx) | ||
| 97 | static inline void mark_fs_dirty(DisasContext *ctx) { } | ||
| 98 | #endif | ||
| 99 | |||
| 100 | -#if !defined(TARGET_RISCV64) | ||
| 101 | -static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, | ||
| 102 | - int rs1, target_long imm) | ||
| 103 | -{ | ||
| 104 | - TCGv t0; | ||
| 105 | - | ||
| 106 | - if (ctx->mstatus_fs == 0) { | ||
| 107 | - gen_exception_illegal(ctx); | ||
| 108 | - return; | ||
| 109 | - } | ||
| 110 | - | ||
| 111 | - t0 = tcg_temp_new(); | ||
| 112 | - gen_get_gpr(t0, rs1); | ||
| 113 | - tcg_gen_addi_tl(t0, t0, imm); | ||
| 114 | - | ||
| 115 | - switch (opc) { | ||
| 116 | - case OPC_RISC_FLW: | ||
| 117 | - if (!has_ext(ctx, RVF)) { | ||
| 118 | - goto do_illegal; | ||
| 119 | - } | ||
| 120 | - tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL); | ||
| 121 | - /* RISC-V requires NaN-boxing of narrower width floating point values */ | ||
| 122 | - tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL); | ||
| 123 | - break; | ||
| 124 | - case OPC_RISC_FLD: | ||
| 125 | - if (!has_ext(ctx, RVD)) { | ||
| 126 | - goto do_illegal; | ||
| 127 | - } | ||
| 128 | - tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ); | ||
| 129 | - break; | ||
| 130 | - do_illegal: | ||
| 131 | - default: | ||
| 132 | - gen_exception_illegal(ctx); | ||
| 133 | - break; | ||
| 134 | - } | ||
| 135 | - tcg_temp_free(t0); | ||
| 136 | - | ||
| 137 | - mark_fs_dirty(ctx); | ||
| 138 | -} | ||
| 139 | - | ||
| 140 | -static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1, | ||
| 141 | - int rs2, target_long imm) | ||
| 142 | -{ | ||
| 143 | - TCGv t0; | ||
| 144 | - | ||
| 145 | - if (ctx->mstatus_fs == 0) { | ||
| 146 | - gen_exception_illegal(ctx); | ||
| 147 | - return; | ||
| 148 | - } | ||
| 149 | - | ||
| 150 | - t0 = tcg_temp_new(); | ||
| 151 | - gen_get_gpr(t0, rs1); | ||
| 152 | - tcg_gen_addi_tl(t0, t0, imm); | ||
| 153 | - | ||
| 154 | - switch (opc) { | ||
| 155 | - case OPC_RISC_FSW: | ||
| 156 | - if (!has_ext(ctx, RVF)) { | ||
| 157 | - goto do_illegal; | ||
| 158 | - } | ||
| 159 | - tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL); | ||
| 160 | - break; | ||
| 161 | - case OPC_RISC_FSD: | ||
| 162 | - if (!has_ext(ctx, RVD)) { | ||
| 163 | - goto do_illegal; | ||
| 164 | - } | ||
| 165 | - tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ); | ||
| 166 | - break; | ||
| 167 | - do_illegal: | ||
| 168 | - default: | ||
| 169 | - gen_exception_illegal(ctx); | ||
| 170 | - break; | ||
| 171 | - } | ||
| 172 | - | ||
| 173 | - tcg_temp_free(t0); | ||
| 174 | -} | ||
| 175 | -#endif | ||
| 176 | - | ||
| 177 | static void gen_set_rm(DisasContext *ctx, int rm) | ||
| 178 | { | ||
| 179 | TCGv_i32 t0; | ||
| 180 | @@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm) | ||
| 181 | tcg_temp_free_i32(t0); | ||
| 182 | } | ||
| 183 | |||
| 184 | -static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode) | ||
| 185 | -{ | ||
| 186 | - uint8_t funct3 = extract16(opcode, 13, 3); | ||
| 187 | - uint8_t rd_rs2 = GET_C_RS2S(opcode); | ||
| 188 | - uint8_t rs1s = GET_C_RS1S(opcode); | ||
| 189 | - | ||
| 190 | - switch (funct3) { | ||
| 191 | - case 3: | ||
| 192 | -#if defined(TARGET_RISCV64) | ||
| 193 | - /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/ | ||
| 194 | - gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s, | ||
| 195 | - GET_C_LD_IMM(opcode)); | ||
| 196 | -#else | ||
| 197 | - /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/ | ||
| 198 | - gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s, | ||
| 199 | - GET_C_LW_IMM(opcode)); | ||
| 200 | -#endif | ||
| 201 | - break; | ||
| 202 | - case 7: | ||
| 203 | -#if defined(TARGET_RISCV64) | ||
| 204 | - /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/ | ||
| 205 | - gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2, | ||
| 206 | - GET_C_LD_IMM(opcode)); | ||
| 207 | -#else | ||
| 208 | - /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/ | ||
| 209 | - gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2, | ||
| 210 | - GET_C_LW_IMM(opcode)); | ||
| 211 | -#endif | ||
| 212 | - break; | ||
| 213 | - } | ||
| 214 | -} | ||
| 215 | - | ||
| 216 | -static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode) | ||
| 217 | -{ | ||
| 218 | - uint8_t op = extract16(opcode, 0, 2); | ||
| 219 | - | ||
| 220 | - switch (op) { | ||
| 221 | - case 0: | ||
| 222 | - decode_RV32_64C0(ctx, opcode); | ||
| 223 | - break; | ||
| 224 | - } | ||
| 225 | -} | ||
| 226 | - | ||
| 227 | static int ex_plus_1(DisasContext *ctx, int nf) | ||
| 228 | { | ||
| 229 | return nf + 1; | ||
| 230 | @@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) | ||
| 231 | } else { | ||
| 232 | ctx->pc_succ_insn = ctx->base.pc_next + 2; | ||
| 233 | if (!decode_insn16(ctx, opcode)) { | ||
| 234 | - /* fall back to old decoder */ | ||
| 235 | - decode_RV32_64C(ctx, opcode); | ||
| 236 | + gen_exception_illegal(ctx); | ||
| 237 | } | ||
| 238 | } | ||
| 239 | } else { | ||
| 240 | -- | 20 | -- |
| 241 | 2.30.1 | 21 | 2.28.0 |
| 242 | 22 | ||
| 243 | 23 | diff view generated by jsdifflib |
| 1 | From: Georg Kotheimer <georg.kotheimer@kernkonzept.com> | 1 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
|---|---|---|---|
| 2 | Message-id: 9308432988946de550a68524ed76e4b8683f10e2.1597259519.git.alistair.francis@wdc.com | ||
| 3 | Message-Id: <9308432988946de550a68524ed76e4b8683f10e2.1597259519.git.alistair.francis@wdc.com> | ||
| 4 | --- | ||
| 5 | target/riscv/cpu_bits.h | 5 +++-- | ||
| 6 | target/riscv/cpu_helper.c | 24 ++++++++++++++++++++---- | ||
| 7 | target/riscv/csr.c | 6 +++--- | ||
| 8 | 3 files changed, 26 insertions(+), 9 deletions(-) | ||
| 2 | 9 | ||
| 3 | According to the specification the "field SPVP of hstatus controls the | 10 | diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h |
| 4 | privilege level of the access" for the hypervisor virtual-machine load | 11 | index XXXXXXX..XXXXXXX 100644 |
| 5 | and store instructions HLV, HLVX and HSV. | 12 | --- a/target/riscv/cpu_bits.h |
| 6 | 13 | +++ b/target/riscv/cpu_bits.h | |
| 7 | Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com> | 14 | @@ -XXX,XX +XXX,XX @@ |
| 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 15 | #define MSTATUS_TW 0x20000000 /* since: priv-1.10 */ |
| 9 | Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com | 16 | #define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */ |
| 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 17 | #if defined(TARGET_RISCV64) |
| 11 | --- | 18 | -#define MSTATUS_MTL 0x4000000000ULL |
| 12 | target/riscv/cpu_helper.c | 25 ++++++++++++++----------- | 19 | +#define MSTATUS_GVA 0x4000000000ULL |
| 13 | 1 file changed, 14 insertions(+), 11 deletions(-) | 20 | #define MSTATUS_MPV 0x8000000000ULL |
| 14 | 21 | #elif defined(TARGET_RISCV32) | |
| 22 | -#define MSTATUS_MTL 0x00000040 | ||
| 23 | +#define MSTATUS_GVA 0x00000040 | ||
| 24 | #define MSTATUS_MPV 0x00000080 | ||
| 25 | #endif | ||
| 26 | |||
| 27 | @@ -XXX,XX +XXX,XX @@ | ||
| 28 | #define HSTATUS_VTVM 0x00100000 | ||
| 29 | #define HSTATUS_VTSR 0x00400000 | ||
| 30 | #define HSTATUS_HU 0x00000200 | ||
| 31 | +#define HSTATUS_GVA 0x00000040 | ||
| 32 | |||
| 33 | #define HSTATUS32_WPRI 0xFF8FF87E | ||
| 34 | #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL | ||
| 15 | diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c | 35 | diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c |
| 16 | index XXXXXXX..XXXXXXX 100644 | 36 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/target/riscv/cpu_helper.c | 37 | --- a/target/riscv/cpu_helper.c |
| 18 | +++ b/target/riscv/cpu_helper.c | 38 | +++ b/target/riscv/cpu_helper.c |
| 19 | @@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, | 39 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs) |
| 20 | use_background = true; | 40 | if (riscv_has_ext(env, RVH)) { |
| 41 | target_ulong hdeleg = async ? env->hideleg : env->hedeleg; | ||
| 42 | |||
| 43 | + if ((riscv_cpu_virt_enabled(env) || | ||
| 44 | + riscv_cpu_two_stage_lookup(env)) && tval) { | ||
| 45 | + /* | ||
| 46 | + * If we are writing a guest virtual address to stval, set | ||
| 47 | + * this to 1. If we are trapping to VS we will set this to 0 | ||
| 48 | + * later. | ||
| 49 | + */ | ||
| 50 | + env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 1); | ||
| 51 | + } else { | ||
| 52 | + /* For other HS-mode traps, we set this to 0. */ | ||
| 53 | + env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0); | ||
| 54 | + } | ||
| 55 | + | ||
| 56 | if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && | ||
| 57 | !force_hs_execp) { | ||
| 58 | /* | ||
| 59 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs) | ||
| 60 | cause == IRQ_VS_EXT) | ||
| 61 | cause = cause - 1; | ||
| 62 | /* Trap to VS mode */ | ||
| 63 | + env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0); | ||
| 64 | } else if (riscv_cpu_virt_enabled(env)) { | ||
| 65 | /* Trap into HS mode, from virt */ | ||
| 66 | riscv_cpu_swap_hypervisor_regs(env); | ||
| 67 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs) | ||
| 68 | #ifdef TARGET_RISCV32 | ||
| 69 | env->mstatush = set_field(env->mstatush, MSTATUS_MPV, | ||
| 70 | riscv_cpu_virt_enabled(env)); | ||
| 71 | - env->mstatush = set_field(env->mstatush, MSTATUS_MTL, | ||
| 72 | - riscv_cpu_force_hs_excep_enabled(env)); | ||
| 73 | + if (riscv_cpu_virt_enabled(env) && tval) { | ||
| 74 | + env->mstatush = set_field(env->mstatush, MSTATUS_GVA, 1); | ||
| 75 | + } | ||
| 76 | #else | ||
| 77 | env->mstatus = set_field(env->mstatus, MSTATUS_MPV, | ||
| 78 | riscv_cpu_virt_enabled(env)); | ||
| 79 | - env->mstatus = set_field(env->mstatus, MSTATUS_MTL, | ||
| 80 | - riscv_cpu_force_hs_excep_enabled(env)); | ||
| 81 | + if (riscv_cpu_virt_enabled(env) && tval) { | ||
| 82 | + env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); | ||
| 83 | + } | ||
| 84 | #endif | ||
| 85 | |||
| 86 | mtval2 = env->guest_phys_fault_addr; | ||
| 87 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c | ||
| 88 | index XXXXXXX..XXXXXXX 100644 | ||
| 89 | --- a/target/riscv/csr.c | ||
| 90 | +++ b/target/riscv/csr.c | ||
| 91 | @@ -XXX,XX +XXX,XX @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) | ||
| 92 | MSTATUS_TW; | ||
| 93 | #if defined(TARGET_RISCV64) | ||
| 94 | /* | ||
| 95 | - * RV32: MPV and MTL are not in mstatus. The current plan is to | ||
| 96 | + * RV32: MPV and GVA are not in mstatus. The current plan is to | ||
| 97 | * add them to mstatush. For now, we just don't support it. | ||
| 98 | */ | ||
| 99 | - mask |= MSTATUS_MTL | MSTATUS_MPV; | ||
| 100 | + mask |= MSTATUS_MPV | MSTATUS_GVA; | ||
| 101 | #endif | ||
| 102 | |||
| 103 | mstatus = (mstatus & ~mask) | (val & mask); | ||
| 104 | @@ -XXX,XX +XXX,XX @@ static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val) | ||
| 105 | tlb_flush(env_cpu(env)); | ||
| 21 | } | 106 | } |
| 22 | 107 | ||
| 23 | - if (mode == PRV_M && access_type != MMU_INST_FETCH) { | 108 | - val &= MSTATUS_MPV | MSTATUS_MTL; |
| 24 | + /* MPRV does not affect the virtual-machine load/store | 109 | + val &= MSTATUS_MPV | MSTATUS_GVA; |
| 25 | + instructions, HLV, HLVX, and HSV. */ | 110 | |
| 26 | + if (riscv_cpu_two_stage_lookup(mmu_idx)) { | 111 | env->mstatush = val; |
| 27 | + mode = get_field(env->hstatus, HSTATUS_SPVP); | 112 | |
| 28 | + } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { | ||
| 29 | if (get_field(env->mstatus, MSTATUS_MPRV)) { | ||
| 30 | mode = get_field(env->mstatus, MSTATUS_MPP); | ||
| 31 | } | ||
| 32 | @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | ||
| 33 | qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", | ||
| 34 | __func__, address, access_type, mmu_idx); | ||
| 35 | |||
| 36 | - if (mode == PRV_M && access_type != MMU_INST_FETCH) { | ||
| 37 | - if (get_field(env->mstatus, MSTATUS_MPRV)) { | ||
| 38 | - mode = get_field(env->mstatus, MSTATUS_MPP); | ||
| 39 | + /* MPRV does not affect the virtual-machine load/store | ||
| 40 | + instructions, HLV, HLVX, and HSV. */ | ||
| 41 | + if (riscv_cpu_two_stage_lookup(mmu_idx)) { | ||
| 42 | + mode = get_field(env->hstatus, HSTATUS_SPVP); | ||
| 43 | + } else if (mode == PRV_M && access_type != MMU_INST_FETCH && | ||
| 44 | + get_field(env->mstatus, MSTATUS_MPRV)) { | ||
| 45 | + mode = get_field(env->mstatus, MSTATUS_MPP); | ||
| 46 | + if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) { | ||
| 47 | + two_stage_lookup = true; | ||
| 48 | } | ||
| 49 | } | ||
| 50 | |||
| 51 | - if (riscv_has_ext(env, RVH) && env->priv == PRV_M && | ||
| 52 | - access_type != MMU_INST_FETCH && | ||
| 53 | - get_field(env->mstatus, MSTATUS_MPRV) && | ||
| 54 | - get_field(env->mstatus, MSTATUS_MPV)) { | ||
| 55 | - two_stage_lookup = true; | ||
| 56 | - } | ||
| 57 | - | ||
| 58 | if (riscv_cpu_virt_enabled(env) || | ||
| 59 | ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && | ||
| 60 | access_type != MMU_INST_FETCH)) { | ||
| 61 | -- | 113 | -- |
| 62 | 2.30.1 | 114 | 2.28.0 |
| 63 | 115 | ||
| 64 | 116 | diff view generated by jsdifflib |
| 1 | From: Jim Shu <cwshu@andestech.com> | ||
|---|---|---|---|
| 2 | |||
| 3 | Like MMU translation, add qemu log of PMP permission checking for | ||
| 4 | debugging. | ||
| 5 | |||
| 6 | Signed-off-by: Jim Shu <cwshu@andestech.com> | ||
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 8 | Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com | ||
| 9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 1 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 2 | Message-id: 85b7fdba8abd87adb83275cdc3043ce35a1ed5c3.1597259519.git.alistair.francis@wdc.com | ||
| 3 | Message-Id: <85b7fdba8abd87adb83275cdc3043ce35a1ed5c3.1597259519.git.alistair.francis@wdc.com> | ||
| 10 | --- | 4 | --- |
| 11 | target/riscv/cpu_helper.c | 12 ++++++++++++ | 5 | target/riscv/cpu_helper.c | 5 +++-- |
| 12 | 1 file changed, 12 insertions(+) | 6 | 1 file changed, 3 insertions(+), 2 deletions(-) |
| 13 | 7 | ||
| 14 | diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c | 8 | diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c |
| 15 | index XXXXXXX..XXXXXXX 100644 | 9 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/target/riscv/cpu_helper.c | 10 | --- a/target/riscv/cpu_helper.c |
| 17 | +++ b/target/riscv/cpu_helper.c | 11 | +++ b/target/riscv/cpu_helper.c |
| 18 | @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | 12 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs) |
| 19 | if (ret == TRANSLATE_SUCCESS) { | 13 | |
| 20 | ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, | 14 | if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && |
| 21 | size, access_type, mode); | 15 | !force_hs_execp) { |
| 22 | + | 16 | + /* Trap to VS mode */ |
| 23 | + qemu_log_mask(CPU_LOG_MMU, | 17 | /* |
| 24 | + "%s PMP address=" TARGET_FMT_plx " ret %d prot" | 18 | * See if we need to adjust cause. Yes if its VS mode interrupt |
| 25 | + " %d tlb_size " TARGET_FMT_lu "\n", | 19 | * no if hypervisor has delegated one of hs mode's interrupt |
| 26 | + __func__, pa, ret, prot_pmp, tlb_size); | 20 | */ |
| 27 | + | 21 | if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || |
| 28 | prot &= prot_pmp; | 22 | - cause == IRQ_VS_EXT) |
| 29 | } | 23 | + cause == IRQ_VS_EXT) { |
| 30 | 24 | cause = cause - 1; | |
| 31 | @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | 25 | - /* Trap to VS mode */ |
| 32 | if (ret == TRANSLATE_SUCCESS) { | 26 | + } |
| 33 | ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, | 27 | env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0); |
| 34 | size, access_type, mode); | 28 | } else if (riscv_cpu_virt_enabled(env)) { |
| 35 | + | 29 | /* Trap into HS mode, from virt */ |
| 36 | + qemu_log_mask(CPU_LOG_MMU, | ||
| 37 | + "%s PMP address=" TARGET_FMT_plx " ret %d prot" | ||
| 38 | + " %d tlb_size " TARGET_FMT_lu "\n", | ||
| 39 | + __func__, pa, ret, prot_pmp, tlb_size); | ||
| 40 | + | ||
| 41 | prot &= prot_pmp; | ||
| 42 | } | ||
| 43 | } | ||
| 44 | -- | 30 | -- |
| 45 | 2.30.1 | 31 | 2.28.0 |
| 46 | 32 | ||
| 47 | 33 | diff view generated by jsdifflib |
| 1 | From: Georg Kotheimer <georg.kotheimer@kernkonzept.com> | 1 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
|---|---|---|---|
| 2 | Message-id: e7e4e801234f2934306e734f65860f601a5745bd.1597259519.git.alistair.francis@wdc.com | ||
| 3 | Message-Id: <e7e4e801234f2934306e734f65860f601a5745bd.1597259519.git.alistair.francis@wdc.com> | ||
| 4 | --- | ||
| 5 | target/riscv/cpu_bits.h | 1 + | ||
| 6 | target/riscv/cpu_helper.c | 16 ++++++---------- | ||
| 7 | target/riscv/op_helper.c | 8 ++------ | ||
| 8 | target/riscv/translate.c | 10 ---------- | ||
| 9 | 4 files changed, 9 insertions(+), 26 deletions(-) | ||
| 2 | 10 | ||
| 3 | The current two-stage lookup detection in riscv_cpu_do_interrupt falls | 11 | diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h |
| 4 | short of its purpose, as all it checks is whether two-stage address | ||
| 5 | translation either via the hypervisor-load store instructions or the | ||
| 6 | MPRV feature would be allowed. | ||
| 7 | |||
| 8 | What we really need instead is whether two-stage address translation was | ||
| 9 | active when the exception was raised. However, in riscv_cpu_do_interrupt | ||
| 10 | we do not have the information to reliably detect this. Therefore, when | ||
| 11 | we raise a memory fault exception we have to record whether two-stage | ||
| 12 | address translation is active. | ||
| 13 | |||
| 14 | Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com> | ||
| 15 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 16 | Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com | ||
| 17 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 18 | --- | ||
| 19 | target/riscv/cpu.h | 4 ++++ | ||
| 20 | target/riscv/cpu.c | 1 + | ||
| 21 | target/riscv/cpu_helper.c | 21 ++++++++------------- | ||
| 22 | 3 files changed, 13 insertions(+), 13 deletions(-) | ||
| 23 | |||
| 24 | diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h | ||
| 25 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
| 26 | --- a/target/riscv/cpu.h | 13 | --- a/target/riscv/cpu_bits.h |
| 27 | +++ b/target/riscv/cpu.h | 14 | +++ b/target/riscv/cpu_bits.h |
| 28 | @@ -XXX,XX +XXX,XX @@ struct CPURISCVState { | 15 | @@ -XXX,XX +XXX,XX @@ |
| 29 | target_ulong satp_hs; | 16 | #define HSTATUS_VTSR 0x00400000 |
| 30 | uint64_t mstatus_hs; | 17 | #define HSTATUS_HU 0x00000200 |
| 31 | 18 | #define HSTATUS_GVA 0x00000040 | |
| 32 | + /* Signals whether the current exception occurred with two-stage address | 19 | +#define HSTATUS_SPVP 0x00000100 |
| 33 | + translation active. */ | 20 | |
| 34 | + bool two_stage_lookup; | 21 | #define HSTATUS32_WPRI 0xFF8FF87E |
| 35 | + | 22 | #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL |
| 36 | target_ulong scounteren; | ||
| 37 | target_ulong mcounteren; | ||
| 38 | |||
| 39 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
| 40 | index XXXXXXX..XXXXXXX 100644 | ||
| 41 | --- a/target/riscv/cpu.c | ||
| 42 | +++ b/target/riscv/cpu.c | ||
| 43 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev) | ||
| 44 | env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); | ||
| 45 | env->mcause = 0; | ||
| 46 | env->pc = env->resetvec; | ||
| 47 | + env->two_stage_lookup = false; | ||
| 48 | #endif | ||
| 49 | cs->exception_index = EXCP_NONE; | ||
| 50 | env->load_res = -1; | ||
| 51 | diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c | 23 | diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c |
| 52 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
| 53 | --- a/target/riscv/cpu_helper.c | 25 | --- a/target/riscv/cpu_helper.c |
| 54 | +++ b/target/riscv/cpu_helper.c | 26 | +++ b/target/riscv/cpu_helper.c |
| 55 | @@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address, | ||
| 56 | g_assert_not_reached(); | ||
| 57 | } | ||
| 58 | env->badaddr = address; | ||
| 59 | + env->two_stage_lookup = two_stage; | ||
| 60 | } | ||
| 61 | |||
| 62 | hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) | ||
| 63 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, | ||
| 64 | } | ||
| 65 | |||
| 66 | env->badaddr = addr; | ||
| 67 | + env->two_stage_lookup = riscv_cpu_virt_enabled(env) || | ||
| 68 | + riscv_cpu_two_stage_lookup(mmu_idx); | ||
| 69 | riscv_raise_exception(&cpu->env, cs->exception_index, retaddr); | ||
| 70 | } | ||
| 71 | |||
| 72 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, | ||
| 73 | g_assert_not_reached(); | ||
| 74 | } | ||
| 75 | env->badaddr = addr; | ||
| 76 | + env->two_stage_lookup = riscv_cpu_virt_enabled(env) || | ||
| 77 | + riscv_cpu_two_stage_lookup(mmu_idx); | ||
| 78 | riscv_raise_exception(env, cs->exception_index, retaddr); | ||
| 79 | } | ||
| 80 | #endif /* !CONFIG_USER_ONLY */ | ||
| 81 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs) | 27 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs) |
| 82 | /* handle the trap in S-mode */ | 28 | } else if (riscv_cpu_virt_enabled(env)) { |
| 83 | if (riscv_has_ext(env, RVH)) { | 29 | /* Trap into HS mode, from virt */ |
| 84 | target_ulong hdeleg = async ? env->hideleg : env->hedeleg; | 30 | riscv_cpu_swap_hypervisor_regs(env); |
| 85 | - bool two_stage_lookup = false; | 31 | - env->hstatus = set_field(env->hstatus, HSTATUS_SP2V, |
| 86 | 32 | - get_field(env->hstatus, HSTATUS_SPV)); | |
| 87 | - if (env->priv == PRV_M || | 33 | - env->hstatus = set_field(env->hstatus, HSTATUS_SP2P, |
| 88 | - (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || | 34 | + env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, |
| 89 | - (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && | 35 | get_field(env->mstatus, SSTATUS_SPP)); |
| 90 | - get_field(env->hstatus, HSTATUS_HU))) { | 36 | env->hstatus = set_field(env->hstatus, HSTATUS_SPV, |
| 91 | - two_stage_lookup = true; | 37 | riscv_cpu_virt_enabled(env)); |
| 92 | - } | ||
| 93 | - | ||
| 94 | - if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) { | ||
| 95 | + if (env->two_stage_lookup && write_tval) { | ||
| 96 | /* | ||
| 97 | * If we are writing a guest virtual address to stval, set | ||
| 98 | * this to 1. If we are trapping to VS we will set this to 0 | ||
| 99 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs) | 38 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs) |
| 100 | riscv_cpu_set_force_hs_excep(env, 0); | 39 | riscv_cpu_set_force_hs_excep(env, 0); |
| 101 | } else { | 40 | } else { |
| 102 | /* Trap into HS mode */ | 41 | /* Trap into HS mode */ |
| 103 | - if (!two_stage_lookup) { | 42 | - env->hstatus = set_field(env->hstatus, HSTATUS_SP2V, |
| 104 | - env->hstatus = set_field(env->hstatus, HSTATUS_SPV, | 43 | - get_field(env->hstatus, HSTATUS_SPV)); |
| 105 | - riscv_cpu_virt_enabled(env)); | 44 | - env->hstatus = set_field(env->hstatus, HSTATUS_SP2P, |
| 106 | - } | 45 | - get_field(env->mstatus, SSTATUS_SPP)); |
| 107 | + env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); | 46 | - env->hstatus = set_field(env->hstatus, HSTATUS_SPV, |
| 47 | - riscv_cpu_virt_enabled(env)); | ||
| 48 | - | ||
| 49 | + if (!riscv_cpu_two_stage_lookup(env)) { | ||
| 50 | + env->hstatus = set_field(env->hstatus, HSTATUS_SPV, | ||
| 51 | + riscv_cpu_virt_enabled(env)); | ||
| 52 | + } | ||
| 53 | + riscv_cpu_set_two_stage_lookup(env, false); | ||
| 108 | htval = env->guest_phys_fault_addr; | 54 | htval = env->guest_phys_fault_addr; |
| 109 | } | 55 | } |
| 110 | } | 56 | } |
| 111 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs) | 57 | diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c |
| 112 | * RISC-V ISA Specification. | 58 | index XXXXXXX..XXXXXXX 100644 |
| 113 | */ | 59 | --- a/target/riscv/op_helper.c |
| 114 | 60 | +++ b/target/riscv/op_helper.c | |
| 115 | + env->two_stage_lookup = false; | 61 | @@ -XXX,XX +XXX,XX @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) |
| 116 | #endif | 62 | prev_priv = get_field(mstatus, MSTATUS_SPP); |
| 117 | cs->exception_index = EXCP_NONE; /* mark handled to qemu */ | 63 | prev_virt = get_field(hstatus, HSTATUS_SPV); |
| 118 | } | 64 | |
| 65 | - hstatus = set_field(hstatus, HSTATUS_SPV, | ||
| 66 | - get_field(hstatus, HSTATUS_SP2V)); | ||
| 67 | - mstatus = set_field(mstatus, MSTATUS_SPP, | ||
| 68 | - get_field(hstatus, HSTATUS_SP2P)); | ||
| 69 | - hstatus = set_field(hstatus, HSTATUS_SP2V, 0); | ||
| 70 | - hstatus = set_field(hstatus, HSTATUS_SP2P, 0); | ||
| 71 | + hstatus = set_field(hstatus, HSTATUS_SPV, 0); | ||
| 72 | + mstatus = set_field(mstatus, MSTATUS_SPP, 0); | ||
| 73 | mstatus = set_field(mstatus, SSTATUS_SIE, | ||
| 74 | get_field(mstatus, SSTATUS_SPIE)); | ||
| 75 | mstatus = set_field(mstatus, SSTATUS_SPIE, 1); | ||
| 76 | diff --git a/target/riscv/translate.c b/target/riscv/translate.c | ||
| 77 | index XXXXXXX..XXXXXXX 100644 | ||
| 78 | --- a/target/riscv/translate.c | ||
| 79 | +++ b/target/riscv/translate.c | ||
| 80 | @@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) | ||
| 81 | #if !defined(CONFIG_USER_ONLY) | ||
| 82 | if (riscv_has_ext(env, RVH)) { | ||
| 83 | ctx->virt_enabled = riscv_cpu_virt_enabled(env); | ||
| 84 | - if (env->priv_ver == PRV_M && | ||
| 85 | - get_field(env->mstatus, MSTATUS_MPRV) && | ||
| 86 | - MSTATUS_MPV_ISSET(env)) { | ||
| 87 | - ctx->virt_enabled = true; | ||
| 88 | - } else if (env->priv == PRV_S && | ||
| 89 | - !riscv_cpu_virt_enabled(env) && | ||
| 90 | - get_field(env->hstatus, HSTATUS_SPRV) && | ||
| 91 | - get_field(env->hstatus, HSTATUS_SPV)) { | ||
| 92 | - ctx->virt_enabled = true; | ||
| 93 | - } | ||
| 94 | } else { | ||
| 95 | ctx->virt_enabled = false; | ||
| 96 | } | ||
| 119 | -- | 97 | -- |
| 120 | 2.30.1 | 98 | 2.28.0 |
| 121 | 99 | ||
| 122 | 100 | diff view generated by jsdifflib |
| 1 | From: Bin Meng <bin.meng@windriver.com> | 1 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
|---|---|---|---|
| 2 | Message-id: 4f227b30cb1816795296c0994f1123fab143666a.1597259519.git.alistair.francis@wdc.com | ||
| 3 | Message-Id: <4f227b30cb1816795296c0994f1123fab143666a.1597259519.git.alistair.francis@wdc.com> | ||
| 4 | --- | ||
| 5 | target/riscv/cpu_bits.h | 14 ++++++++------ | ||
| 6 | 1 file changed, 8 insertions(+), 6 deletions(-) | ||
| 2 | 7 | ||
| 3 | Since HSS commit c20a89f8dcac, the Icicle Kit reference design has | 8 | diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h |
| 4 | been updated to use a register mapped at 0x4f000000 instead of a | ||
| 5 | GPIO to control whether eMMC or SD card is to be used. With this | ||
| 6 | support the same HSS image can be used for both eMMC and SD card | ||
| 7 | boot flow, while previously two different board configurations were | ||
| 8 | used. This is undocumented but one can take a look at the HSS code | ||
| 9 | HSS_MMCInit() in services/mmc/mmc_api.c. | ||
| 10 | |||
| 11 | With this commit, HSS image built from 2020.12 release boots again. | ||
| 12 | |||
| 13 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
| 14 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 15 | Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com | ||
| 16 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 17 | --- | ||
| 18 | include/hw/riscv/microchip_pfsoc.h | 1 + | ||
| 19 | hw/riscv/microchip_pfsoc.c | 6 ++++++ | ||
| 20 | 2 files changed, 7 insertions(+) | ||
| 21 | |||
| 22 | diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h | ||
| 23 | index XXXXXXX..XXXXXXX 100644 | 9 | index XXXXXXX..XXXXXXX 100644 |
| 24 | --- a/include/hw/riscv/microchip_pfsoc.h | 10 | --- a/target/riscv/cpu_bits.h |
| 25 | +++ b/include/hw/riscv/microchip_pfsoc.h | 11 | +++ b/target/riscv/cpu_bits.h |
| 26 | @@ -XXX,XX +XXX,XX @@ enum { | 12 | @@ -XXX,XX +XXX,XX @@ |
| 27 | MICROCHIP_PFSOC_ENVM_DATA, | 13 | #endif |
| 28 | MICROCHIP_PFSOC_QSPI_XIP, | 14 | |
| 29 | MICROCHIP_PFSOC_IOSCB, | 15 | /* hstatus CSR bits */ |
| 30 | + MICROCHIP_PFSOC_EMMC_SD_MUX, | 16 | -#define HSTATUS_SPRV 0x00000001 |
| 31 | MICROCHIP_PFSOC_DRAM_LO, | 17 | +#define HSTATUS_VSBE 0x00000020 |
| 32 | MICROCHIP_PFSOC_DRAM_LO_ALIAS, | 18 | +#define HSTATUS_GVA 0x00000040 |
| 33 | MICROCHIP_PFSOC_DRAM_HI, | 19 | #define HSTATUS_SPV 0x00000080 |
| 34 | diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c | 20 | -#define HSTATUS_SP2P 0x00000100 |
| 35 | index XXXXXXX..XXXXXXX 100644 | 21 | -#define HSTATUS_SP2V 0x00000200 |
| 36 | --- a/hw/riscv/microchip_pfsoc.c | 22 | +#define HSTATUS_SPVP 0x00000100 |
| 37 | +++ b/hw/riscv/microchip_pfsoc.c | 23 | +#define HSTATUS_HU 0x00000200 |
| 38 | @@ -XXX,XX +XXX,XX @@ static const MemMapEntry microchip_pfsoc_memmap[] = { | 24 | +#define HSTATUS_VGEIN 0x0003F000 |
| 39 | [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, | 25 | #define HSTATUS_VTVM 0x00100000 |
| 40 | [MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 }, | 26 | #define HSTATUS_VTSR 0x00400000 |
| 41 | [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 }, | 27 | -#define HSTATUS_HU 0x00000200 |
| 42 | + [MICROCHIP_PFSOC_EMMC_SD_MUX] = { 0x4f000000, 0x4 }, | 28 | -#define HSTATUS_GVA 0x00000040 |
| 43 | [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 }, | 29 | -#define HSTATUS_SPVP 0x00000100 |
| 44 | [MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 }, | 30 | +#if defined(TARGET_RISCV64) |
| 45 | [MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 }, | 31 | +#define HSTATUS_VSXL 0x300000000 |
| 46 | @@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) | 32 | +#endif |
| 47 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0, | 33 | |
| 48 | memmap[MICROCHIP_PFSOC_IOSCB].base); | 34 | #define HSTATUS32_WPRI 0xFF8FF87E |
| 49 | 35 | #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL | |
| 50 | + /* eMMC/SD mux */ | ||
| 51 | + create_unimplemented_device("microchip.pfsoc.emmc_sd_mux", | ||
| 52 | + memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base, | ||
| 53 | + memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size); | ||
| 54 | + | ||
| 55 | /* QSPI Flash */ | ||
| 56 | memory_region_init_rom(qspi_xip_mem, OBJECT(dev), | ||
| 57 | "microchip.pfsoc.qspi_xip", | ||
| 58 | -- | 36 | -- |
| 59 | 2.30.1 | 37 | 2.28.0 |
| 60 | 38 | ||
| 61 | 39 | diff view generated by jsdifflib |
| 1 | From: Jim Shu <cwshu@andestech.com> | 1 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
|---|---|---|---|
| 2 | Message-id: f3f4fd2ec22a07cc1d750e96895d6813f131de4d.1597259519.git.alistair.francis@wdc.com | ||
| 3 | Message-Id: <f3f4fd2ec22a07cc1d750e96895d6813f131de4d.1597259519.git.alistair.francis@wdc.com> | ||
| 4 | --- | ||
| 5 | target/riscv/csr.c | 9 +++++++++ | ||
| 6 | 1 file changed, 9 insertions(+) | ||
| 2 | 7 | ||
| 3 | If PMP permission of any address has been changed by updating PMP entry, | 8 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c |
| 4 | flush all TLB pages to prevent from getting old permission. | ||
| 5 | |||
| 6 | Signed-off-by: Jim Shu <cwshu@andestech.com> | ||
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 8 | Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com | ||
| 9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 10 | --- | ||
| 11 | target/riscv/pmp.c | 4 ++++ | ||
| 12 | 1 file changed, 4 insertions(+) | ||
| 13 | |||
| 14 | diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | 9 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/target/riscv/pmp.c | 10 | --- a/target/riscv/csr.c |
| 17 | +++ b/target/riscv/pmp.c | 11 | +++ b/target/riscv/csr.c |
| 18 | @@ -XXX,XX +XXX,XX @@ | 12 | @@ -XXX,XX +XXX,XX @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val) |
| 19 | #include "qapi/error.h" | 13 | static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) |
| 20 | #include "cpu.h" | 14 | { |
| 21 | #include "trace.h" | 15 | *val = env->hstatus; |
| 22 | +#include "exec/exec-all.h" | 16 | +#ifdef TARGET_RISCV64 |
| 23 | 17 | + /* We only support 64-bit VSXL */ | |
| 24 | static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index, | 18 | + *val = set_field(*val, HSTATUS_VSXL, 2); |
| 25 | uint8_t val); | 19 | +#endif |
| 26 | @@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, | 20 | return 0; |
| 27 | cfg_val = (val >> 8 * i) & 0xff; | ||
| 28 | pmp_write_cfg(env, (reg_index * 4) + i, cfg_val); | ||
| 29 | } | ||
| 30 | + | ||
| 31 | + /* If PMP permission of any addr has been changed, flush TLB pages. */ | ||
| 32 | + tlb_flush(env_cpu(env)); | ||
| 33 | } | 21 | } |
| 34 | 22 | ||
| 23 | static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val) | ||
| 24 | { | ||
| 25 | env->hstatus = val; | ||
| 26 | +#ifdef TARGET_RISCV64 | ||
| 27 | + if (get_field(val, HSTATUS_VSXL) != 2) { | ||
| 28 | + qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); | ||
| 29 | + } | ||
| 30 | +#endif | ||
| 31 | return 0; | ||
| 32 | } | ||
| 35 | 33 | ||
| 36 | -- | 34 | -- |
| 37 | 2.30.1 | 35 | 2.28.0 |
| 38 | 36 | ||
| 39 | 37 | diff view generated by jsdifflib |
| 1 | From: Georg Kotheimer <georg.kotheimer@kernkonzept.com> | ||
|---|---|---|---|
| 2 | |||
| 3 | The previous implementation was broken in many ways: | ||
| 4 | - Used mideleg instead of hideleg to mask accesses | ||
| 5 | - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie | ||
| 6 | - Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...) | ||
| 7 | |||
| 8 | Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com> | ||
| 9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 10 | Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com | ||
| 11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 1 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 2 | Message-id: 93e5d4f13eca0d2a588e407187f33c6437aeaaf9.1597259519.git.alistair.francis@wdc.com | ||
| 3 | Message-Id: <93e5d4f13eca0d2a588e407187f33c6437aeaaf9.1597259519.git.alistair.francis@wdc.com> | ||
| 12 | --- | 4 | --- |
| 13 | target/riscv/csr.c | 68 +++++++++++++++++++++++----------------------- | 5 | target/riscv/csr.c | 5 +++++ |
| 14 | 1 file changed, 34 insertions(+), 34 deletions(-) | 6 | 1 file changed, 5 insertions(+) |
| 15 | 7 | ||
| 16 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c | 8 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c |
| 17 | index XXXXXXX..XXXXXXX 100644 | 9 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/target/riscv/csr.c | 10 | --- a/target/riscv/csr.c |
| 19 | +++ b/target/riscv/csr.c | 11 | +++ b/target/riscv/csr.c |
| 20 | @@ -XXX,XX +XXX,XX @@ static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val) | 12 | @@ -XXX,XX +XXX,XX @@ static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) |
| 21 | return write_mstatus(env, CSR_MSTATUS, newval); | 13 | /* We only support 64-bit VSXL */ |
| 22 | } | 14 | *val = set_field(*val, HSTATUS_VSXL, 2); |
| 23 | 15 | #endif | |
| 24 | +static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val) | 16 | + /* We only support little endian */ |
| 25 | +{ | 17 | + *val = set_field(*val, HSTATUS_VSBE, 0); |
| 26 | + /* Shift the VS bits to their S bit location in vsie */ | ||
| 27 | + *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1; | ||
| 28 | + return 0; | ||
| 29 | +} | ||
| 30 | + | ||
| 31 | static int read_sie(CPURISCVState *env, int csrno, target_ulong *val) | ||
| 32 | { | ||
| 33 | if (riscv_cpu_virt_enabled(env)) { | ||
| 34 | - /* Tell the guest the VS bits, shifted to the S bit locations */ | ||
| 35 | - *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1; | ||
| 36 | + read_vsie(env, CSR_VSIE, val); | ||
| 37 | } else { | ||
| 38 | *val = env->mie & env->mideleg; | ||
| 39 | } | ||
| 40 | return 0; | 18 | return 0; |
| 41 | } | 19 | } |
| 42 | 20 | ||
| 43 | -static int write_sie(CPURISCVState *env, int csrno, target_ulong val) | 21 | @@ -XXX,XX +XXX,XX @@ static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val) |
| 44 | +static int write_vsie(CPURISCVState *env, int csrno, target_ulong val) | 22 | qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); |
| 45 | { | ||
| 46 | - target_ulong newval; | ||
| 47 | + /* Shift the S bits to their VS bit location in mie */ | ||
| 48 | + target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | | ||
| 49 | + ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS); | ||
| 50 | + return write_mie(env, CSR_MIE, newval); | ||
| 51 | +} | ||
| 52 | |||
| 53 | +static int write_sie(CPURISCVState *env, int csrno, target_ulong val) | ||
| 54 | +{ | ||
| 55 | if (riscv_cpu_virt_enabled(env)) { | ||
| 56 | - /* Shift the guests S bits to VS */ | ||
| 57 | - newval = (env->mie & ~VS_MODE_INTERRUPTS) | | ||
| 58 | - ((val << 1) & VS_MODE_INTERRUPTS); | ||
| 59 | + write_vsie(env, CSR_VSIE, val); | ||
| 60 | } else { | ||
| 61 | - newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS); | ||
| 62 | + target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) | | ||
| 63 | + (val & S_MODE_INTERRUPTS); | ||
| 64 | + write_mie(env, CSR_MIE, newval); | ||
| 65 | } | 23 | } |
| 66 | 24 | #endif | |
| 67 | - return write_mie(env, CSR_MIE, newval); | 25 | + if (get_field(val, HSTATUS_VSBE) != 0) { |
| 68 | + return 0; | 26 | + qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); |
| 69 | } | 27 | + } |
| 70 | |||
| 71 | static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val) | ||
| 72 | @@ -XXX,XX +XXX,XX @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val) | ||
| 73 | return 0; | 28 | return 0; |
| 74 | } | 29 | } |
| 75 | 30 | ||
| 76 | +static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value, | ||
| 77 | + target_ulong new_value, target_ulong write_mask) | ||
| 78 | +{ | ||
| 79 | + /* Shift the S bits to their VS bit location in mip */ | ||
| 80 | + int ret = rmw_mip(env, 0, ret_value, new_value << 1, | ||
| 81 | + (write_mask << 1) & vsip_writable_mask & env->hideleg); | ||
| 82 | + *ret_value &= VS_MODE_INTERRUPTS; | ||
| 83 | + /* Shift the VS bits to their S bit location in vsip */ | ||
| 84 | + *ret_value >>= 1; | ||
| 85 | + return ret; | ||
| 86 | +} | ||
| 87 | + | ||
| 88 | static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, | ||
| 89 | target_ulong new_value, target_ulong write_mask) | ||
| 90 | { | ||
| 91 | int ret; | ||
| 92 | |||
| 93 | if (riscv_cpu_virt_enabled(env)) { | ||
| 94 | - /* Shift the new values to line up with the VS bits */ | ||
| 95 | - ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1, | ||
| 96 | - (write_mask & sip_writable_mask) << 1 & env->mideleg); | ||
| 97 | - ret &= vsip_writable_mask; | ||
| 98 | - ret >>= 1; | ||
| 99 | + ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); | ||
| 100 | } else { | ||
| 101 | ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, | ||
| 102 | write_mask & env->mideleg & sip_writable_mask); | ||
| 103 | @@ -XXX,XX +XXX,XX @@ static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val) | ||
| 104 | return 0; | ||
| 105 | } | ||
| 106 | |||
| 107 | -static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value, | ||
| 108 | - target_ulong new_value, target_ulong write_mask) | ||
| 109 | -{ | ||
| 110 | - int ret = rmw_mip(env, 0, ret_value, new_value, | ||
| 111 | - write_mask & env->mideleg & vsip_writable_mask); | ||
| 112 | - return ret; | ||
| 113 | -} | ||
| 114 | - | ||
| 115 | -static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val) | ||
| 116 | -{ | ||
| 117 | - *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS; | ||
| 118 | - return 0; | ||
| 119 | -} | ||
| 120 | - | ||
| 121 | -static int write_vsie(CPURISCVState *env, int csrno, target_ulong val) | ||
| 122 | -{ | ||
| 123 | - target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP); | ||
| 124 | - return write_mie(env, CSR_MIE, newval); | ||
| 125 | -} | ||
| 126 | - | ||
| 127 | static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) | ||
| 128 | { | ||
| 129 | *val = env->vstvec; | ||
| 130 | -- | 31 | -- |
| 131 | 2.30.1 | 32 | 2.28.0 |
| 132 | 33 | ||
| 133 | 34 | diff view generated by jsdifflib |
| 1 | From: Georg Kotheimer <georg.kotheimer@kernkonzept.com> | 1 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
|---|---|---|---|
| 2 | Message-id: 644b6c114b1a81adbee0ab8c9c66a8672059ec96.1597259519.git.alistair.francis@wdc.com | ||
| 3 | Message-Id: <644b6c114b1a81adbee0ab8c9c66a8672059ec96.1597259519.git.alistair.francis@wdc.com> | ||
| 4 | --- | ||
| 5 | target/riscv/cpu_bits.h | 3 +++ | ||
| 6 | target/riscv/csr.c | 40 ++++++++++++++++++++++++++++++++++++++++ | ||
| 7 | 2 files changed, 43 insertions(+) | ||
| 2 | 8 | ||
| 3 | Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com> | 9 | diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h |
| 4 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 10 | index XXXXXXX..XXXXXXX 100644 |
| 5 | Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com | 11 | --- a/target/riscv/cpu_bits.h |
| 6 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 12 | +++ b/target/riscv/cpu_bits.h |
| 7 | --- | 13 | @@ -XXX,XX +XXX,XX @@ |
| 8 | target/riscv/csr.c | 7 ++++--- | 14 | #define CSR_HIDELEG 0x603 |
| 9 | 1 file changed, 4 insertions(+), 3 deletions(-) | 15 | #define CSR_HIE 0x604 |
| 10 | 16 | #define CSR_HCOUNTEREN 0x606 | |
| 17 | +#define CSR_HGEIE 0x607 | ||
| 18 | #define CSR_HTVAL 0x643 | ||
| 19 | +#define CSR_HVIP 0x645 | ||
| 20 | #define CSR_HIP 0x644 | ||
| 21 | #define CSR_HTINST 0x64A | ||
| 22 | +#define CSR_HGEIP 0xE12 | ||
| 23 | #define CSR_HGATP 0x680 | ||
| 24 | #define CSR_HTIMEDELTA 0x605 | ||
| 25 | #define CSR_HTIMEDELTAH 0x615 | ||
| 11 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c | 26 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c |
| 12 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
| 13 | --- a/target/riscv/csr.c | 28 | --- a/target/riscv/csr.c |
| 14 | +++ b/target/riscv/csr.c | 29 | +++ b/target/riscv/csr.c |
| 15 | @@ -XXX,XX +XXX,XX @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | | 30 | @@ -XXX,XX +XXX,XX @@ static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val) |
| 16 | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | | 31 | return 0; |
| 17 | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; | 32 | } |
| 18 | static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; | 33 | |
| 19 | -static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; | 34 | +static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value, |
| 20 | +static const target_ulong hip_writable_mask = MIP_VSSIP; | 35 | + target_ulong new_value, target_ulong write_mask) |
| 21 | +static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; | 36 | +{ |
| 22 | static const target_ulong vsip_writable_mask = MIP_VSSIP; | 37 | + int ret = rmw_mip(env, 0, ret_value, new_value, |
| 23 | 38 | + write_mask & hip_writable_mask); | |
| 24 | static const char valid_vm_1_10_32[16] = { | 39 | + |
| 25 | @@ -XXX,XX +XXX,XX @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value, | 40 | + *ret_value &= hip_writable_mask; |
| 41 | + | ||
| 42 | + return ret; | ||
| 43 | +} | ||
| 44 | + | ||
| 45 | static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value, | ||
| 26 | target_ulong new_value, target_ulong write_mask) | 46 | target_ulong new_value, target_ulong write_mask) |
| 27 | { | 47 | { |
| 28 | int ret = rmw_mip(env, 0, ret_value, new_value, | 48 | int ret = rmw_mip(env, 0, ret_value, new_value, |
| 29 | - write_mask & hip_writable_mask); | 49 | write_mask & hip_writable_mask); |
| 30 | + write_mask & hvip_writable_mask); | 50 | |
| 31 | 51 | + *ret_value &= hip_writable_mask; | |
| 32 | - *ret_value &= hip_writable_mask; | 52 | + |
| 33 | + *ret_value &= hvip_writable_mask; | ||
| 34 | |||
| 35 | return ret; | 53 | return ret; |
| 36 | } | 54 | } |
| 55 | |||
| 56 | @@ -XXX,XX +XXX,XX @@ static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val) | ||
| 57 | return 0; | ||
| 58 | } | ||
| 59 | |||
| 60 | +static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val) | ||
| 61 | +{ | ||
| 62 | + qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); | ||
| 63 | + return 0; | ||
| 64 | +} | ||
| 65 | + | ||
| 66 | +static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val) | ||
| 67 | +{ | ||
| 68 | + qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); | ||
| 69 | + return 0; | ||
| 70 | +} | ||
| 71 | + | ||
| 72 | static int read_htval(CPURISCVState *env, int csrno, target_ulong *val) | ||
| 73 | { | ||
| 74 | *val = env->htval; | ||
| 75 | @@ -XXX,XX +XXX,XX @@ static int write_htinst(CPURISCVState *env, int csrno, target_ulong val) | ||
| 76 | return 0; | ||
| 77 | } | ||
| 78 | |||
| 79 | +static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val) | ||
| 80 | +{ | ||
| 81 | + qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); | ||
| 82 | + return 0; | ||
| 83 | +} | ||
| 84 | + | ||
| 85 | +static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val) | ||
| 86 | +{ | ||
| 87 | + qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); | ||
| 88 | + return 0; | ||
| 89 | +} | ||
| 90 | + | ||
| 91 | static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val) | ||
| 92 | { | ||
| 93 | *val = env->hgatp; | ||
| 94 | @@ -XXX,XX +XXX,XX @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { | ||
| 95 | [CSR_HSTATUS] = { hmode, read_hstatus, write_hstatus }, | ||
| 96 | [CSR_HEDELEG] = { hmode, read_hedeleg, write_hedeleg }, | ||
| 97 | [CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg }, | ||
| 98 | + [CSR_HVIP] = { hmode, NULL, NULL, rmw_hvip }, | ||
| 99 | [CSR_HIP] = { hmode, NULL, NULL, rmw_hip }, | ||
| 100 | [CSR_HIE] = { hmode, read_hie, write_hie }, | ||
| 101 | [CSR_HCOUNTEREN] = { hmode, read_hcounteren, write_hcounteren }, | ||
| 102 | + [CSR_HGEIE] = { hmode, read_hgeie, write_hgeie }, | ||
| 103 | [CSR_HTVAL] = { hmode, read_htval, write_htval }, | ||
| 104 | [CSR_HTINST] = { hmode, read_htinst, write_htinst }, | ||
| 105 | + [CSR_HGEIP] = { hmode, read_hgeip, write_hgeip }, | ||
| 106 | [CSR_HGATP] = { hmode, read_hgatp, write_hgatp }, | ||
| 107 | [CSR_HTIMEDELTA] = { hmode, read_htimedelta, write_htimedelta }, | ||
| 108 | #if defined(TARGET_RISCV32) | ||
| 37 | -- | 109 | -- |
| 38 | 2.30.1 | 110 | 2.28.0 |
| 39 | 111 | ||
| 40 | 112 | diff view generated by jsdifflib |
| 1 | From: Frank Chang <frank.chang@sifive.com> | 1 | When performing a CSR access let's return a negative exception value on |
|---|---|---|---|
| 2 | 2 | an error instead of -1. This will allow us to specify the exception in | |
| 3 | vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature | 3 | future patches. |
| 4 | is not enabled. | 4 | |
| 5 | |||
| 6 | If -1 is returned, exception will be raised and cs->exception_index will | ||
| 7 | be set to the negative return value. The exception will then be treated | ||
| 8 | as an instruction access fault instead of illegal instruction fault. | ||
| 9 | |||
| 10 | Signed-off-by: Frank Chang <frank.chang@sifive.com> | ||
| 11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 12 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 13 | Message-id: 20210223065935.20208-1-frank.chang@sifive.com | ||
| 14 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 5 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
| 6 | Message-id: a487dad60c9b8fe7a2b992c5e0dcc2504a9000a7.1597259519.git.alistair.francis@wdc.com | ||
| 7 | Message-Id: <a487dad60c9b8fe7a2b992c5e0dcc2504a9000a7.1597259519.git.alistair.francis@wdc.com> | ||
| 15 | --- | 8 | --- |
| 16 | target/riscv/csr.c | 2 +- | 9 | target/riscv/csr.c | 46 ++++++++++++++++++++-------------------- |
| 17 | 1 file changed, 1 insertion(+), 1 deletion(-) | 10 | target/riscv/op_helper.c | 18 ++++++++++------ |
| 11 | 2 files changed, 35 insertions(+), 29 deletions(-) | ||
| 18 | 12 | ||
| 19 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c | 13 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c |
| 20 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
| 21 | --- a/target/riscv/csr.c | 15 | --- a/target/riscv/csr.c |
| 22 | +++ b/target/riscv/csr.c | 16 | +++ b/target/riscv/csr.c |
| 23 | @@ -XXX,XX +XXX,XX @@ static int vs(CPURISCVState *env, int csrno) | 17 | @@ -XXX,XX +XXX,XX @@ static int fs(CPURISCVState *env, int csrno) |
| 24 | if (env->misa & RVV) { | ||
| 25 | return 0; | 18 | return 0; |
| 26 | } | 19 | } |
| 20 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { | ||
| 21 | - return -1; | ||
| 22 | + return -RISCV_EXCP_ILLEGAL_INST; | ||
| 23 | } | ||
| 24 | #endif | ||
| 25 | return 0; | ||
| 26 | @@ -XXX,XX +XXX,XX @@ static int ctr(CPURISCVState *env, int csrno) | ||
| 27 | |||
| 28 | if (!cpu->cfg.ext_counters) { | ||
| 29 | /* The Counters extensions is not enabled */ | ||
| 30 | - return -1; | ||
| 31 | + return -RISCV_EXCP_ILLEGAL_INST; | ||
| 32 | } | ||
| 33 | #endif | ||
| 34 | return 0; | ||
| 35 | @@ -XXX,XX +XXX,XX @@ static int hmode(CPURISCVState *env, int csrno) | ||
| 36 | } | ||
| 37 | } | ||
| 38 | |||
| 27 | - return -1; | 39 | - return -1; |
| 28 | + return -RISCV_EXCP_ILLEGAL_INST; | 40 | + return -RISCV_EXCP_ILLEGAL_INST; |
| 29 | } | 41 | } |
| 30 | 42 | ||
| 31 | static int ctr(CPURISCVState *env, int csrno) | 43 | static int pmp(CPURISCVState *env, int csrno) |
| 44 | @@ -XXX,XX +XXX,XX @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) | ||
| 45 | { | ||
| 46 | #if !defined(CONFIG_USER_ONLY) | ||
| 47 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { | ||
| 48 | - return -1; | ||
| 49 | + return -RISCV_EXCP_ILLEGAL_INST; | ||
| 50 | } | ||
| 51 | #endif | ||
| 52 | *val = riscv_cpu_get_fflags(env); | ||
| 53 | @@ -XXX,XX +XXX,XX @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) | ||
| 54 | { | ||
| 55 | #if !defined(CONFIG_USER_ONLY) | ||
| 56 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { | ||
| 57 | - return -1; | ||
| 58 | + return -RISCV_EXCP_ILLEGAL_INST; | ||
| 59 | } | ||
| 60 | env->mstatus |= MSTATUS_FS; | ||
| 61 | #endif | ||
| 62 | @@ -XXX,XX +XXX,XX @@ static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) | ||
| 63 | { | ||
| 64 | #if !defined(CONFIG_USER_ONLY) | ||
| 65 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { | ||
| 66 | - return -1; | ||
| 67 | + return -RISCV_EXCP_ILLEGAL_INST; | ||
| 68 | } | ||
| 69 | #endif | ||
| 70 | *val = env->frm; | ||
| 71 | @@ -XXX,XX +XXX,XX @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val) | ||
| 72 | { | ||
| 73 | #if !defined(CONFIG_USER_ONLY) | ||
| 74 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { | ||
| 75 | - return -1; | ||
| 76 | + return -RISCV_EXCP_ILLEGAL_INST; | ||
| 77 | } | ||
| 78 | env->mstatus |= MSTATUS_FS; | ||
| 79 | #endif | ||
| 80 | @@ -XXX,XX +XXX,XX @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) | ||
| 81 | { | ||
| 82 | #if !defined(CONFIG_USER_ONLY) | ||
| 83 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { | ||
| 84 | - return -1; | ||
| 85 | + return -RISCV_EXCP_ILLEGAL_INST; | ||
| 86 | } | ||
| 87 | #endif | ||
| 88 | *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) | ||
| 89 | @@ -XXX,XX +XXX,XX @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val) | ||
| 90 | { | ||
| 91 | #if !defined(CONFIG_USER_ONLY) | ||
| 92 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { | ||
| 93 | - return -1; | ||
| 94 | + return -RISCV_EXCP_ILLEGAL_INST; | ||
| 95 | } | ||
| 96 | env->mstatus |= MSTATUS_FS; | ||
| 97 | #endif | ||
| 98 | @@ -XXX,XX +XXX,XX @@ static int read_time(CPURISCVState *env, int csrno, target_ulong *val) | ||
| 99 | uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; | ||
| 100 | |||
| 101 | if (!env->rdtime_fn) { | ||
| 102 | - return -1; | ||
| 103 | + return -RISCV_EXCP_ILLEGAL_INST; | ||
| 104 | } | ||
| 105 | |||
| 106 | *val = env->rdtime_fn() + delta; | ||
| 107 | @@ -XXX,XX +XXX,XX @@ static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val) | ||
| 108 | uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; | ||
| 109 | |||
| 110 | if (!env->rdtime_fn) { | ||
| 111 | - return -1; | ||
| 112 | + return -RISCV_EXCP_ILLEGAL_INST; | ||
| 113 | } | ||
| 114 | |||
| 115 | *val = (env->rdtime_fn() + delta) >> 32; | ||
| 116 | @@ -XXX,XX +XXX,XX @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val) | ||
| 117 | static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val) | ||
| 118 | { | ||
| 119 | if (env->priv_ver < PRIV_VERSION_1_11_0) { | ||
| 120 | - return -1; | ||
| 121 | + return -RISCV_EXCP_ILLEGAL_INST; | ||
| 122 | } | ||
| 123 | *val = env->mcounteren; | ||
| 124 | return 0; | ||
| 125 | @@ -XXX,XX +XXX,XX @@ static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val) | ||
| 126 | static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val) | ||
| 127 | { | ||
| 128 | if (env->priv_ver < PRIV_VERSION_1_11_0) { | ||
| 129 | - return -1; | ||
| 130 | + return -RISCV_EXCP_ILLEGAL_INST; | ||
| 131 | } | ||
| 132 | env->mcounteren = val; | ||
| 133 | return 0; | ||
| 134 | @@ -XXX,XX +XXX,XX @@ static int read_satp(CPURISCVState *env, int csrno, target_ulong *val) | ||
| 135 | } | ||
| 136 | |||
| 137 | if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { | ||
| 138 | - return -1; | ||
| 139 | + return -RISCV_EXCP_ILLEGAL_INST; | ||
| 140 | } else { | ||
| 141 | *val = env->satp; | ||
| 142 | } | ||
| 143 | @@ -XXX,XX +XXX,XX @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val) | ||
| 144 | ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) | ||
| 145 | { | ||
| 146 | if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { | ||
| 147 | - return -1; | ||
| 148 | + return -RISCV_EXCP_ILLEGAL_INST; | ||
| 149 | } else { | ||
| 150 | if((val ^ env->satp) & SATP_ASID) { | ||
| 151 | tlb_flush(env_cpu(env)); | ||
| 152 | @@ -XXX,XX +XXX,XX @@ static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val) | ||
| 153 | static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val) | ||
| 154 | { | ||
| 155 | if (!env->rdtime_fn) { | ||
| 156 | - return -1; | ||
| 157 | + return -RISCV_EXCP_ILLEGAL_INST; | ||
| 158 | } | ||
| 159 | |||
| 160 | #if defined(TARGET_RISCV32) | ||
| 161 | @@ -XXX,XX +XXX,XX @@ static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val) | ||
| 162 | static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val) | ||
| 163 | { | ||
| 164 | if (!env->rdtime_fn) { | ||
| 165 | - return -1; | ||
| 166 | + return -RISCV_EXCP_ILLEGAL_INST; | ||
| 167 | } | ||
| 168 | |||
| 169 | #if defined(TARGET_RISCV32) | ||
| 170 | @@ -XXX,XX +XXX,XX @@ static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val) | ||
| 171 | static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val) | ||
| 172 | { | ||
| 173 | if (!env->rdtime_fn) { | ||
| 174 | - return -1; | ||
| 175 | + return -RISCV_EXCP_ILLEGAL_INST; | ||
| 176 | } | ||
| 177 | |||
| 178 | *val = env->htimedelta >> 32; | ||
| 179 | @@ -XXX,XX +XXX,XX @@ static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val) | ||
| 180 | static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val) | ||
| 181 | { | ||
| 182 | if (!env->rdtime_fn) { | ||
| 183 | - return -1; | ||
| 184 | + return -RISCV_EXCP_ILLEGAL_INST; | ||
| 185 | } | ||
| 186 | |||
| 187 | env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); | ||
| 188 | @@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, | ||
| 189 | |||
| 190 | if ((write_mask && read_only) || | ||
| 191 | (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { | ||
| 192 | - return -1; | ||
| 193 | + return -RISCV_EXCP_ILLEGAL_INST; | ||
| 194 | } | ||
| 195 | #endif | ||
| 196 | |||
| 197 | /* ensure the CSR extension is enabled. */ | ||
| 198 | if (!cpu->cfg.ext_icsr) { | ||
| 199 | - return -1; | ||
| 200 | + return -RISCV_EXCP_ILLEGAL_INST; | ||
| 201 | } | ||
| 202 | |||
| 203 | /* check predicate */ | ||
| 204 | if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) { | ||
| 205 | - return -1; | ||
| 206 | + return -RISCV_EXCP_ILLEGAL_INST; | ||
| 207 | } | ||
| 208 | |||
| 209 | /* execute combined read/write operation if it exists */ | ||
| 210 | @@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, | ||
| 211 | |||
| 212 | /* if no accessor exists then return failure */ | ||
| 213 | if (!csr_ops[csrno].read) { | ||
| 214 | - return -1; | ||
| 215 | + return -RISCV_EXCP_ILLEGAL_INST; | ||
| 216 | } | ||
| 217 | |||
| 218 | /* read old value */ | ||
| 219 | diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c | ||
| 220 | index XXXXXXX..XXXXXXX 100644 | ||
| 221 | --- a/target/riscv/op_helper.c | ||
| 222 | +++ b/target/riscv/op_helper.c | ||
| 223 | @@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src, | ||
| 224 | target_ulong csr) | ||
| 225 | { | ||
| 226 | target_ulong val = 0; | ||
| 227 | - if (riscv_csrrw(env, csr, &val, src, -1) < 0) { | ||
| 228 | - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); | ||
| 229 | + int ret = riscv_csrrw(env, csr, &val, src, -1); | ||
| 230 | + | ||
| 231 | + if (ret < 0) { | ||
| 232 | + riscv_raise_exception(env, -ret, GETPC()); | ||
| 233 | } | ||
| 234 | return val; | ||
| 235 | } | ||
| 236 | @@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src, | ||
| 237 | target_ulong csr, target_ulong rs1_pass) | ||
| 238 | { | ||
| 239 | target_ulong val = 0; | ||
| 240 | - if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) { | ||
| 241 | - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); | ||
| 242 | + int ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0); | ||
| 243 | + | ||
| 244 | + if (ret < 0) { | ||
| 245 | + riscv_raise_exception(env, -ret, GETPC()); | ||
| 246 | } | ||
| 247 | return val; | ||
| 248 | } | ||
| 249 | @@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src, | ||
| 250 | target_ulong csr, target_ulong rs1_pass) | ||
| 251 | { | ||
| 252 | target_ulong val = 0; | ||
| 253 | - if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) { | ||
| 254 | - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); | ||
| 255 | + int ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0); | ||
| 256 | + | ||
| 257 | + if (ret < 0) { | ||
| 258 | + riscv_raise_exception(env, -ret, GETPC()); | ||
| 259 | } | ||
| 260 | return val; | ||
| 261 | } | ||
| 32 | -- | 262 | -- |
| 33 | 2.30.1 | 263 | 2.28.0 |
| 34 | 264 | ||
| 35 | 265 | diff view generated by jsdifflib |
| 1 | From: Bin Meng <bin.meng@windriver.com> | 1 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
|---|---|---|---|
| 2 | Message-id: 4c744dce9b0b057cbb5cc0f4d4ac75cda682a8af.1597259519.git.alistair.francis@wdc.com | ||
| 3 | Message-Id: <4c744dce9b0b057cbb5cc0f4d4ac75cda682a8af.1597259519.git.alistair.francis@wdc.com> | ||
| 4 | --- | ||
| 5 | target/riscv/cpu_bits.h | 6 +++ | ||
| 6 | target/riscv/helper.h | 1 + | ||
| 7 | target/riscv/csr.c | 64 ++++++++++++++++++++++++- | ||
| 8 | target/riscv/op_helper.c | 42 ++++++++++++++-- | ||
| 9 | target/riscv/insn_trans/trans_rvh.c.inc | 2 +- | ||
| 10 | 5 files changed, 109 insertions(+), 6 deletions(-) | ||
| 2 | 11 | ||
| 3 | Per SST25VF016B datasheet [1], SST flash requires a dummy byte after | 12 | diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h |
| 4 | the address bytes. Note only SPI mode is supported by SST flashes. | 13 | index XXXXXXX..XXXXXXX 100644 |
| 5 | 14 | --- a/target/riscv/cpu_bits.h | |
| 6 | [1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf | 15 | +++ b/target/riscv/cpu_bits.h |
| 7 | 16 | @@ -XXX,XX +XXX,XX @@ | |
| 8 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | 17 | #define HSTATUS_WPRI HSTATUS64_WPRI |
| 9 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | 18 | #endif |
| 10 | Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com | 19 | |
| 11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 20 | +#define HCOUNTEREN_CY (1 << 0) |
| 12 | --- | 21 | +#define HCOUNTEREN_TM (1 << 1) |
| 13 | hw/block/m25p80.c | 3 +++ | 22 | +#define HCOUNTEREN_IR (1 << 2) |
| 14 | 1 file changed, 3 insertions(+) | 23 | +#define HCOUNTEREN_HPM3 (1 << 3) |
| 15 | 24 | + | |
| 16 | diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c | 25 | /* Privilege modes */ |
| 17 | index XXXXXXX..XXXXXXX 100644 | 26 | #define PRV_U 0 |
| 18 | --- a/hw/block/m25p80.c | 27 | #define PRV_S 1 |
| 19 | +++ b/hw/block/m25p80.c | 28 | @@ -XXX,XX +XXX,XX @@ |
| 20 | @@ -XXX,XX +XXX,XX @@ static void decode_fast_read_cmd(Flash *s) | 29 | #define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0 */ |
| 21 | s->needed_bytes = get_addr_length(s); | 30 | #define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14 |
| 22 | switch (get_man(s)) { | 31 | #define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15 |
| 23 | /* Dummy cycles - modeled with bytes writes instead of bits */ | 32 | +#define RISCV_EXCP_VIRT_INSTRUCTION_FAULT 0x16 |
| 24 | + case MAN_SST: | 33 | #define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT 0x17 |
| 25 | + s->needed_bytes += 1; | 34 | |
| 26 | + break; | 35 | #define RISCV_EXCP_INT_FLAG 0x80000000 |
| 27 | case MAN_WINBOND: | 36 | diff --git a/target/riscv/helper.h b/target/riscv/helper.h |
| 28 | s->needed_bytes += 8; | 37 | index XXXXXXX..XXXXXXX 100644 |
| 29 | break; | 38 | --- a/target/riscv/helper.h |
| 39 | +++ b/target/riscv/helper.h | ||
| 40 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(tlb_flush, void, env) | ||
| 41 | /* Hypervisor functions */ | ||
| 42 | #ifndef CONFIG_USER_ONLY | ||
| 43 | DEF_HELPER_1(hyp_tlb_flush, void, env) | ||
| 44 | +DEF_HELPER_1(hyp_gvma_tlb_flush, void, env) | ||
| 45 | DEF_HELPER_4(hyp_load, tl, env, tl, tl, tl) | ||
| 46 | DEF_HELPER_5(hyp_store, void, env, tl, tl, tl, tl) | ||
| 47 | DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl) | ||
| 48 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c | ||
| 49 | index XXXXXXX..XXXXXXX 100644 | ||
| 50 | --- a/target/riscv/csr.c | ||
| 51 | +++ b/target/riscv/csr.c | ||
| 52 | @@ -XXX,XX +XXX,XX @@ static int ctr(CPURISCVState *env, int csrno) | ||
| 53 | /* The Counters extensions is not enabled */ | ||
| 54 | return -RISCV_EXCP_ILLEGAL_INST; | ||
| 55 | } | ||
| 56 | + | ||
| 57 | + if (riscv_cpu_virt_enabled(env)) { | ||
| 58 | + switch (csrno) { | ||
| 59 | + case CSR_CYCLE: | ||
| 60 | + if (!get_field(env->hcounteren, HCOUNTEREN_CY) && | ||
| 61 | + get_field(env->mcounteren, HCOUNTEREN_CY)) { | ||
| 62 | + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; | ||
| 63 | + } | ||
| 64 | + break; | ||
| 65 | + case CSR_TIME: | ||
| 66 | + if (!get_field(env->hcounteren, HCOUNTEREN_TM) && | ||
| 67 | + get_field(env->mcounteren, HCOUNTEREN_TM)) { | ||
| 68 | + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; | ||
| 69 | + } | ||
| 70 | + break; | ||
| 71 | + case CSR_INSTRET: | ||
| 72 | + if (!get_field(env->hcounteren, HCOUNTEREN_IR) && | ||
| 73 | + get_field(env->mcounteren, HCOUNTEREN_IR)) { | ||
| 74 | + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; | ||
| 75 | + } | ||
| 76 | + break; | ||
| 77 | + case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: | ||
| 78 | + if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) && | ||
| 79 | + get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) { | ||
| 80 | + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; | ||
| 81 | + } | ||
| 82 | + break; | ||
| 83 | +#if defined(TARGET_RISCV32) | ||
| 84 | + case CSR_CYCLEH: | ||
| 85 | + if (!get_field(env->hcounteren, HCOUNTEREN_CY) && | ||
| 86 | + get_field(env->mcounteren, HCOUNTEREN_CY)) { | ||
| 87 | + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; | ||
| 88 | + } | ||
| 89 | + break; | ||
| 90 | + case CSR_TIMEH: | ||
| 91 | + if (!get_field(env->hcounteren, HCOUNTEREN_TM) && | ||
| 92 | + get_field(env->mcounteren, HCOUNTEREN_TM)) { | ||
| 93 | + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; | ||
| 94 | + } | ||
| 95 | + break; | ||
| 96 | + case CSR_INSTRETH: | ||
| 97 | + if (!get_field(env->hcounteren, HCOUNTEREN_IR) && | ||
| 98 | + get_field(env->mcounteren, HCOUNTEREN_IR)) { | ||
| 99 | + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; | ||
| 100 | + } | ||
| 101 | + break; | ||
| 102 | + case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: | ||
| 103 | + if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) && | ||
| 104 | + get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) { | ||
| 105 | + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; | ||
| 106 | + } | ||
| 107 | + break; | ||
| 108 | +#endif | ||
| 109 | + } | ||
| 110 | + } | ||
| 111 | #endif | ||
| 112 | return 0; | ||
| 113 | } | ||
| 114 | @@ -XXX,XX +XXX,XX @@ static int hmode(CPURISCVState *env, int csrno) | ||
| 115 | if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || | ||
| 116 | env->priv == PRV_M) { | ||
| 117 | return 0; | ||
| 118 | + } else { | ||
| 119 | + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; | ||
| 120 | } | ||
| 121 | } | ||
| 122 | |||
| 123 | @@ -XXX,XX +XXX,XX @@ static const target_ulong delegable_excps = | ||
| 124 | (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | | ||
| 125 | (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | | ||
| 126 | (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | | ||
| 127 | + (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | | ||
| 128 | (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); | ||
| 129 | static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | | ||
| 130 | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | | ||
| 131 | @@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, | ||
| 132 | } | ||
| 133 | |||
| 134 | /* check predicate */ | ||
| 135 | - if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) { | ||
| 136 | + if (!csr_ops[csrno].predicate) { | ||
| 137 | return -RISCV_EXCP_ILLEGAL_INST; | ||
| 138 | } | ||
| 139 | + ret = csr_ops[csrno].predicate(env, csrno); | ||
| 140 | + if (ret < 0) { | ||
| 141 | + return ret; | ||
| 142 | + } | ||
| 143 | |||
| 144 | /* execute combined read/write operation if it exists */ | ||
| 145 | if (csr_ops[csrno].op) { | ||
| 146 | diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c | ||
| 147 | index XXXXXXX..XXXXXXX 100644 | ||
| 148 | --- a/target/riscv/op_helper.c | ||
| 149 | +++ b/target/riscv/op_helper.c | ||
| 150 | @@ -XXX,XX +XXX,XX @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) | ||
| 151 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); | ||
| 152 | } | ||
| 153 | |||
| 154 | + if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) && | ||
| 155 | + get_field(env->hstatus, HSTATUS_VTSR)) { | ||
| 156 | + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); | ||
| 157 | + } | ||
| 158 | + | ||
| 159 | mstatus = env->mstatus; | ||
| 160 | |||
| 161 | if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) { | ||
| 162 | @@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env) | ||
| 163 | if ((env->priv == PRV_S && | ||
| 164 | get_field(env->mstatus, MSTATUS_TW)) || | ||
| 165 | riscv_cpu_virt_enabled(env)) { | ||
| 166 | - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); | ||
| 167 | + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); | ||
| 168 | } else { | ||
| 169 | cs->halted = 1; | ||
| 170 | cs->exception_index = EXCP_HLT; | ||
| 171 | @@ -XXX,XX +XXX,XX @@ void helper_tlb_flush(CPURISCVState *env) | ||
| 172 | (env->priv == PRV_S && | ||
| 173 | get_field(env->mstatus, MSTATUS_TVM))) { | ||
| 174 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); | ||
| 175 | + } else if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) && | ||
| 176 | + get_field(env->hstatus, HSTATUS_VTVM)) { | ||
| 177 | + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); | ||
| 178 | } else { | ||
| 179 | tlb_flush(cs); | ||
| 180 | } | ||
| 181 | @@ -XXX,XX +XXX,XX @@ void helper_hyp_tlb_flush(CPURISCVState *env) | ||
| 182 | { | ||
| 183 | CPUState *cs = env_cpu(env); | ||
| 184 | |||
| 185 | + if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) { | ||
| 186 | + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); | ||
| 187 | + } | ||
| 188 | + | ||
| 189 | if (env->priv == PRV_M || | ||
| 190 | (env->priv == PRV_S && !riscv_cpu_virt_enabled(env))) { | ||
| 191 | tlb_flush(cs); | ||
| 192 | @@ -XXX,XX +XXX,XX @@ void helper_hyp_tlb_flush(CPURISCVState *env) | ||
| 193 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); | ||
| 194 | } | ||
| 195 | |||
| 196 | +void helper_hyp_gvma_tlb_flush(CPURISCVState *env) | ||
| 197 | +{ | ||
| 198 | + if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env) && | ||
| 199 | + get_field(env->mstatus, MSTATUS_TVM)) { | ||
| 200 | + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); | ||
| 201 | + } | ||
| 202 | + | ||
| 203 | + helper_hyp_tlb_flush(env); | ||
| 204 | +} | ||
| 205 | + | ||
| 206 | target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address, | ||
| 207 | target_ulong attrs, target_ulong memop) | ||
| 208 | { | ||
| 209 | @@ -XXX,XX +XXX,XX @@ target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address, | ||
| 210 | return pte; | ||
| 211 | } | ||
| 212 | |||
| 213 | - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); | ||
| 214 | + if (riscv_cpu_virt_enabled(env)) { | ||
| 215 | + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); | ||
| 216 | + } else { | ||
| 217 | + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); | ||
| 218 | + } | ||
| 219 | return 0; | ||
| 220 | } | ||
| 221 | |||
| 222 | @@ -XXX,XX +XXX,XX @@ void helper_hyp_store(CPURISCVState *env, target_ulong address, | ||
| 223 | return; | ||
| 224 | } | ||
| 225 | |||
| 226 | - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); | ||
| 227 | + if (riscv_cpu_virt_enabled(env)) { | ||
| 228 | + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); | ||
| 229 | + } else { | ||
| 230 | + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); | ||
| 231 | + } | ||
| 232 | } | ||
| 233 | |||
| 234 | target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address, | ||
| 235 | @@ -XXX,XX +XXX,XX @@ target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address, | ||
| 236 | return pte; | ||
| 237 | } | ||
| 238 | |||
| 239 | - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); | ||
| 240 | + if (riscv_cpu_virt_enabled(env)) { | ||
| 241 | + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); | ||
| 242 | + } else { | ||
| 243 | + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); | ||
| 244 | + } | ||
| 245 | return 0; | ||
| 246 | } | ||
| 247 | |||
| 248 | diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc | ||
| 249 | index XXXXXXX..XXXXXXX 100644 | ||
| 250 | --- a/target/riscv/insn_trans/trans_rvh.c.inc | ||
| 251 | +++ b/target/riscv/insn_trans/trans_rvh.c.inc | ||
| 252 | @@ -XXX,XX +XXX,XX @@ static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) | ||
| 253 | { | ||
| 254 | REQUIRE_EXT(ctx, RVH); | ||
| 255 | #ifndef CONFIG_USER_ONLY | ||
| 256 | - gen_helper_hyp_tlb_flush(cpu_env); | ||
| 257 | + gen_helper_hyp_gvma_tlb_flush(cpu_env); | ||
| 258 | return true; | ||
| 259 | #endif | ||
| 260 | return false; | ||
| 30 | -- | 261 | -- |
| 31 | 2.30.1 | 262 | 2.28.0 |
| 32 | 263 | ||
| 33 | 264 | diff view generated by jsdifflib |