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[PULL 00/18] riscv-to-apply queue

Alistair Francis posted 18 patches 3 years, 8 months ago
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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20200825184836.1282371-1-alistair.francis@wdc.com
Maintainers: Alistair Francis <Alistair.Francis@wdc.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Palmer Dabbelt <palmer@dabbelt.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>
There is a newer version of this series
include/hw/riscv/numa.h                 | 113 +++++++
include/hw/riscv/sifive_clint.h         |   7 +-
include/hw/riscv/sifive_plic.h          |  12 +-
include/hw/riscv/spike.h                |  11 +-
include/hw/riscv/virt.h                 |   9 +-
target/riscv/cpu.h                      |   2 +
target/riscv/cpu_bits.h                 |  25 +-
target/riscv/helper.h                   |   4 +
target/riscv/insn32-64.decode           |   5 +
target/riscv/insn32.decode              |  11 +
hw/riscv/numa.c                         | 242 +++++++++++++++
hw/riscv/sifive_clint.c                 |  20 +-
hw/riscv/sifive_e.c                     |   4 +-
hw/riscv/sifive_plic.c                  |  24 +-
hw/riscv/sifive_u.c                     |   4 +-
hw/riscv/spike.c                        | 232 +++++++++-----
hw/riscv/virt.c                         | 526 ++++++++++++++++++--------------
target/riscv/cpu_helper.c               | 123 ++++----
target/riscv/csr.c                      | 171 +++++++++--
target/riscv/op_helper.c                | 176 ++++++++++-
target/riscv/translate.c                |  10 -
hw/riscv/meson.build                    |   1 +
target/riscv/insn_trans/trans_rvh.c.inc | 342 ++++++++++++++++++++-
23 files changed, 1630 insertions(+), 444 deletions(-)
create mode 100644 include/hw/riscv/numa.h
create mode 100644 hw/riscv/numa.c
[PULL 00/18] riscv-to-apply queue
Posted by Alistair Francis 3 years, 8 months ago 
The following changes since commit 7774e403f2ac58b3e87bfe8d2f77676501ba893e:

  Merge remote-tracking branch 'remotes/kraxel/tags/fixes-20200825-pull-request' into staging (2020-08-25 10:54:51 +0100)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200825

for you to fetch changes up to e39a8320b088dd5efc9ebaafe387e52b3d962665:

  target/riscv: Support the Virtual Instruction fault (2020-08-25 09:11:36 -0700)

----------------------------------------------------------------
This pull request first adds support for multi-socket NUMA RISC-V
machines. The Spike and Virt machines both support NUMA sockets.

This PR also updates the current experimental Hypervisor support to the
v0.6.1 spec.

----------------------------------------------------------------
Alistair Francis (13):
      target/riscv: Allow setting a two-stage lookup in the virt status
      target/riscv: Allow generating hlv/hlvx/hsv instructions
      target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
      target/riscv: Don't allow guest to write to htinst
      target/riscv: Convert MSTATUS MTL to GVA
      target/riscv: Fix the interrupt cause code
      target/riscv: Update the Hypervisor trap return/entry
      target/riscv: Update the CSRs to the v0.6 Hyp extension
      target/riscv: Only support a single VSXL length
      target/riscv: Only support little endian guests
      target/riscv: Support the v0.6 Hypervisor extension CRSs
      target/riscv: Return the exception from invalid CSR accesses
      target/riscv: Support the Virtual Instruction fault

Anup Patel (5):
      hw/riscv: Allow creating multiple instances of CLINT
      hw/riscv: Allow creating multiple instances of PLIC
      hw/riscv: Add helpers for RISC-V multi-socket NUMA machines
      hw/riscv: spike: Allow creating multiple NUMA sockets
      hw/riscv: virt: Allow creating multiple NUMA sockets

 include/hw/riscv/numa.h                 | 113 +++++++
 include/hw/riscv/sifive_clint.h         |   7 +-
 include/hw/riscv/sifive_plic.h          |  12 +-
 include/hw/riscv/spike.h                |  11 +-
 include/hw/riscv/virt.h                 |   9 +-
 target/riscv/cpu.h                      |   2 +
 target/riscv/cpu_bits.h                 |  25 +-
 target/riscv/helper.h                   |   4 +
 target/riscv/insn32-64.decode           |   5 +
 target/riscv/insn32.decode              |  11 +
 hw/riscv/numa.c                         | 242 +++++++++++++++
 hw/riscv/sifive_clint.c                 |  20 +-
 hw/riscv/sifive_e.c                     |   4 +-
 hw/riscv/sifive_plic.c                  |  24 +-
 hw/riscv/sifive_u.c                     |   4 +-
 hw/riscv/spike.c                        | 232 +++++++++-----
 hw/riscv/virt.c                         | 526 ++++++++++++++++++--------------
 target/riscv/cpu_helper.c               | 123 ++++----
 target/riscv/csr.c                      | 171 +++++++++--
 target/riscv/op_helper.c                | 176 ++++++++++-
 target/riscv/translate.c                |  10 -
 hw/riscv/meson.build                    |   1 +
 target/riscv/insn_trans/trans_rvh.c.inc | 342 ++++++++++++++++++++-
 23 files changed, 1630 insertions(+), 444 deletions(-)
 create mode 100644 include/hw/riscv/numa.h
 create mode 100644 hw/riscv/numa.c
Re: [PULL 00/18] riscv-to-apply queue
Posted by Peter Maydell 3 years, 8 months ago 
On Tue, 25 Aug 2020 at 20:01, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit 7774e403f2ac58b3e87bfe8d2f77676501ba893e:
>
>   Merge remote-tracking branch 'remotes/kraxel/tags/fixes-20200825-pull-request' into staging (2020-08-25 10:54:51 +0100)
>
> are available in the Git repository at:
>
>   git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200825
>
> for you to fetch changes up to e39a8320b088dd5efc9ebaafe387e52b3d962665:
>
>   target/riscv: Support the Virtual Instruction fault (2020-08-25 09:11:36 -0700)
>
> ----------------------------------------------------------------
> This pull request first adds support for multi-socket NUMA RISC-V
> machines. The Spike and Virt machines both support NUMA sockets.
>
> This PR also updates the current experimental Hypervisor support to the
> v0.6.1 spec.
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.2
for any user-visible changes.

-- PMM
Re: [PULL 00/18] riscv-to-apply queue
Posted by Peter Maydell 3 years, 8 months ago 
On Tue, 25 Aug 2020 at 20:01, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit 7774e403f2ac58b3e87bfe8d2f77676501ba893e:
>
>   Merge remote-tracking branch 'remotes/kraxel/tags/fixes-20200825-pull-request' into staging (2020-08-25 10:54:51 +0100)
>
> are available in the Git repository at:
>
>   git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200825
>
> for you to fetch changes up to e39a8320b088dd5efc9ebaafe387e52b3d962665:
>
>   target/riscv: Support the Virtual Instruction fault (2020-08-25 09:11:36 -0700)
>
> ----------------------------------------------------------------
> This pull request first adds support for multi-socket NUMA RISC-V
> machines. The Spike and Virt machines both support NUMA sockets.
>
> This PR also updates the current experimental Hypervisor support to the
> v0.6.1 spec.
>
> ----------------------------------------------------------------

The hypervisor related patches don't seem to have any
reviewed-by tags, which seems a shame for a fairly significant
chunk of work. Is there really nobody who can review them
for you ?

thanks
-- PMM
Re: [PULL 00/18] riscv-to-apply queue
Posted by Alistair Francis 3 years, 8 months ago 
On Tue, Aug 25, 2020 at 2:24 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Tue, 25 Aug 2020 at 20:01, Alistair Francis <alistair.francis@wdc.com> wrote:
> >
> > The following changes since commit 7774e403f2ac58b3e87bfe8d2f77676501ba893e:
> >
> >   Merge remote-tracking branch 'remotes/kraxel/tags/fixes-20200825-pull-request' into staging (2020-08-25 10:54:51 +0100)
> >
> > are available in the Git repository at:
> >
> >   git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200825
> >
> > for you to fetch changes up to e39a8320b088dd5efc9ebaafe387e52b3d962665:
> >
> >   target/riscv: Support the Virtual Instruction fault (2020-08-25 09:11:36 -0700)
> >
> > ----------------------------------------------------------------
> > This pull request first adds support for multi-socket NUMA RISC-V
> > machines. The Spike and Virt machines both support NUMA sockets.
> >
> > This PR also updates the current experimental Hypervisor support to the
> > v0.6.1 spec.
> >
> > ----------------------------------------------------------------
>
> The hypervisor related patches don't seem to have any
> reviewed-by tags, which seems a shame for a fairly significant
> chunk of work. Is there really nobody who can review them
> for you ?

Unfortunately not. They have been on the list since April and haven't
received any feedback.

There isn't a lot of people reviewing the RISC-V patches unfortunately.

Alistair

>
> thanks
> -- PMM
Re: [PULL 00/18] riscv-to-apply queue
Posted by Peter Maydell 3 years, 8 months ago 
On Tue, 25 Aug 2020 at 22:32, Alistair Francis <alistair23@gmail.com> wrote:
>
> On Tue, Aug 25, 2020 at 2:24 PM Peter Maydell <peter.maydell@linaro.org> wrote:
> > The hypervisor related patches don't seem to have any
> > reviewed-by tags, which seems a shame for a fairly significant
> > chunk of work. Is there really nobody who can review them
> > for you ?
>
> Unfortunately not. They have been on the list since April and haven't
> received any feedback.
>
> There isn't a lot of people reviewing the RISC-V patches unfortunately.

:-(   I'd hoped it was a more active target than that.

-- PMM
Re: [PULL 00/18] riscv-to-apply queue
Posted by Alistair Francis 3 years, 8 months ago 
On Tue, Aug 25, 2020 at 2:50 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Tue, 25 Aug 2020 at 22:32, Alistair Francis <alistair23@gmail.com> wrote:
> >
> > On Tue, Aug 25, 2020 at 2:24 PM Peter Maydell <peter.maydell@linaro.org> wrote:
> > > The hypervisor related patches don't seem to have any
> > > reviewed-by tags, which seems a shame for a fairly significant
> > > chunk of work. Is there really nobody who can review them
> > > for you ?
> >
> > Unfortunately not. They have been on the list since April and haven't
> > received any feedback.
> >
> > There isn't a lot of people reviewing the RISC-V patches unfortunately.
>
> :-(   I'd hoped it was a more active target than that.

There are lots of active contributors, we are just short on reviewers.

Richard and Philippe review patches and some of the RISC-V patches get
reviewed by the RISC-V community. The main problem (which is a common
problem in open source) is that large technical patch series just get
ignored.

Alistair

>
> -- PMM
Re: [PULL 00/18] riscv-to-apply queue
Posted by Bin Meng 3 years, 8 months ago 
On Wed, Aug 26, 2020 at 6:41 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Tue, Aug 25, 2020 at 2:50 PM Peter Maydell <peter.maydell@linaro.org> wrote:
> >
> > On Tue, 25 Aug 2020 at 22:32, Alistair Francis <alistair23@gmail.com> wrote:
> > >
> > > On Tue, Aug 25, 2020 at 2:24 PM Peter Maydell <peter.maydell@linaro.org> wrote:
> > > > The hypervisor related patches don't seem to have any
> > > > reviewed-by tags, which seems a shame for a fairly significant
> > > > chunk of work. Is there really nobody who can review them
> > > > for you ?
> > >
> > > Unfortunately not. They have been on the list since April and haven't
> > > received any feedback.
> > >
> > > There isn't a lot of people reviewing the RISC-V patches unfortunately.
> >
> > :-(   I'd hoped it was a more active target than that.
>
> There are lots of active contributors, we are just short on reviewers.
>
> Richard and Philippe review patches and some of the RISC-V patches get
> reviewed by the RISC-V community. The main problem (which is a common
> problem in open source) is that large technical patch series just get
> ignored.

Yep, I am only comfortable reviewing patches which I have confidence
in. Right now I am not working on any H- or V - extension for RISC-V
so I cannot contribute to any review of these large numbers of H- or
V- extension related patches. Sorry!

Regards,
Bin
Re: [PULL 00/18] riscv-to-apply queue
Posted by Peter Maydell 3 years, 8 months ago 
On Wed, 26 Aug 2020 at 04:21, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Wed, Aug 26, 2020 at 6:41 AM Alistair Francis <alistair23@gmail.com> wrote:
> > Richard and Philippe review patches and some of the RISC-V patches get
> > reviewed by the RISC-V community. The main problem (which is a common
> > problem in open source) is that large technical patch series just get
> > ignored.
>
> Yep, I am only comfortable reviewing patches which I have confidence
> in. Right now I am not working on any H- or V - extension for RISC-V
> so I cannot contribute to any review of these large numbers of H- or
> V- extension related patches. Sorry!

So, everybody has a ton of work they need to do and only a limited
amount of time they might have for code review, so it's important to
prioritise. But I would encourage you, and other people contributing
to RISC-V parts of QEMU, to at least sometimes review changes that are
a little bit out of your "comfort zone" if nobody else seems to be
doing so. Review can find bugs, areas that are confusing or need
comments, etc, even without a thorough knowledge of the relevant spec.
(In fact, not knowing the spec can help in identifying where
explanatory comments can help the reader!) And for the project it means
we have more people who at least have some idea of what that bit of code
is doing. Review that is limited to "this code seems to make sense but
I haven't checked it against the spec" is better than patches getting
no review at all, I think. And it's a good way to build your knowledge
of the codebase and the architecture over time.

thanks
-- PMM
Re: [PULL 00/18] riscv-to-apply queue
Posted by Bin Meng 3 years, 8 months ago 
Hi Peter,

On Wed, Aug 26, 2020 at 5:25 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Wed, 26 Aug 2020 at 04:21, Bin Meng <bmeng.cn@gmail.com> wrote:
> > On Wed, Aug 26, 2020 at 6:41 AM Alistair Francis <alistair23@gmail.com> wrote:
> > > Richard and Philippe review patches and some of the RISC-V patches get
> > > reviewed by the RISC-V community. The main problem (which is a common
> > > problem in open source) is that large technical patch series just get
> > > ignored.
> >
> > Yep, I am only comfortable reviewing patches which I have confidence
> > in. Right now I am not working on any H- or V - extension for RISC-V
> > so I cannot contribute to any review of these large numbers of H- or
> > V- extension related patches. Sorry!
>
> So, everybody has a ton of work they need to do and only a limited
> amount of time they might have for code review, so it's important to
> prioritise. But I would encourage you, and other people contributing
> to RISC-V parts of QEMU, to at least sometimes review changes that are
> a little bit out of your "comfort zone" if nobody else seems to be
> doing so. Review can find bugs, areas that are confusing or need
> comments, etc, even without a thorough knowledge of the relevant spec.
> (In fact, not knowing the spec can help in identifying where
> explanatory comments can help the reader!) And for the project it means
> we have more people who at least have some idea of what that bit of code
> is doing. Review that is limited to "this code seems to make sense but
> I haven't checked it against the spec" is better than patches getting
> no review at all, I think. And it's a good way to build your knowledge
> of the codebase and the architecture over time.

Agree. I really wanted to spend more time on this project but like you
said it's priorities.

One thing I do not understand is that according to MAINTAINTERS there
are 4 custodians for the RISC-V maintenance work but it looks to me so
far only Alistair is actively reviewing patches. I know Palmer used to
review patches but if it's only one person that might be some issues.
At least MAINTAINTERS can cross-review, and we have 4 there.

Regards,
Bin
Re: [PULL 00/18] riscv-to-apply queue
Posted by Alistair Francis 3 years, 8 months ago 
On Wed, Aug 26, 2020 at 3:06 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Peter,
>
> On Wed, Aug 26, 2020 at 5:25 PM Peter Maydell <peter.maydell@linaro.org> wrote:
> >
> > On Wed, 26 Aug 2020 at 04:21, Bin Meng <bmeng.cn@gmail.com> wrote:
> > > On Wed, Aug 26, 2020 at 6:41 AM Alistair Francis <alistair23@gmail.com> wrote:
> > > > Richard and Philippe review patches and some of the RISC-V patches get
> > > > reviewed by the RISC-V community. The main problem (which is a common
> > > > problem in open source) is that large technical patch series just get
> > > > ignored.
> > >
> > > Yep, I am only comfortable reviewing patches which I have confidence
> > > in. Right now I am not working on any H- or V - extension for RISC-V
> > > so I cannot contribute to any review of these large numbers of H- or
> > > V- extension related patches. Sorry!
> >
> > So, everybody has a ton of work they need to do and only a limited
> > amount of time they might have for code review, so it's important to
> > prioritise. But I would encourage you, and other people contributing
> > to RISC-V parts of QEMU, to at least sometimes review changes that are
> > a little bit out of your "comfort zone" if nobody else seems to be
> > doing so. Review can find bugs, areas that are confusing or need
> > comments, etc, even without a thorough knowledge of the relevant spec.
> > (In fact, not knowing the spec can help in identifying where
> > explanatory comments can help the reader!) And for the project it means
> > we have more people who at least have some idea of what that bit of code
> > is doing. Review that is limited to "this code seems to make sense but
> > I haven't checked it against the spec" is better than patches getting
> > no review at all, I think. And it's a good way to build your knowledge
> > of the codebase and the architecture over time.
>
> Agree. I really wanted to spend more time on this project but like you
> said it's priorities.
>
> One thing I do not understand is that according to MAINTAINTERS there
> are 4 custodians for the RISC-V maintenance work but it looks to me so
> far only Alistair is actively reviewing patches. I know Palmer used to
> review patches but if it's only one person that might be some issues.
> At least MAINTAINTERS can cross-review, and we have 4 there.

Yeah, most of the people in the RISC-V MAINTAINERS file are inactive.
Besides Palmer and myself I haven't seen an email from anyone.

Alistair


>
> Regards,
> Bin
Re: [PULL 00/18] riscv-to-apply queue
Posted by LIU Zhiwei 3 years, 8 months ago 

On 2020/8/26 6:30, Alistair Francis wrote:
> On Tue, Aug 25, 2020 at 2:50 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>> On Tue, 25 Aug 2020 at 22:32, Alistair Francis <alistair23@gmail.com> wrote:
>>> On Tue, Aug 25, 2020 at 2:24 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>>>> The hypervisor related patches don't seem to have any
>>>> reviewed-by tags, which seems a shame for a fairly significant
>>>> chunk of work. Is there really nobody who can review them
>>>> for you ?
>>> Unfortunately not. They have been on the list since April and haven't
>>> received any feedback.
>>>
>>> There isn't a lot of people reviewing the RISC-V patches unfortunately.
>> :-(   I'd hoped it was a more active target than that.
> There are lots of active contributors, we are just short on reviewers.
>
> Richard and Philippe review patches and some of the RISC-V patches get
> reviewed by the RISC-V community. The main problem (which is a common
> problem in open source) is that large technical patch series just get
> ignored.
Hi Alistair,

It's really a pity.

I will review every patch that CC me in no more than a week if no other 
people reviewed this patch.

So if there too many patches, just ease to CC me.


Best Regards,
Zhiwei
>
> Alistair
>
>> -- PMM
Re: [PULL 00/18] riscv-to-apply queue
Posted by Alistair Francis 3 years, 8 months ago 
On Sat, Aug 29, 2020 at 8:50 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
>
>
> On 2020/8/26 6:30, Alistair Francis wrote:
> > On Tue, Aug 25, 2020 at 2:50 PM Peter Maydell <peter.maydell@linaro.org> wrote:
> >> On Tue, 25 Aug 2020 at 22:32, Alistair Francis <alistair23@gmail.com> wrote:
> >>> On Tue, Aug 25, 2020 at 2:24 PM Peter Maydell <peter.maydell@linaro.org> wrote:
> >>>> The hypervisor related patches don't seem to have any
> >>>> reviewed-by tags, which seems a shame for a fairly significant
> >>>> chunk of work. Is there really nobody who can review them
> >>>> for you ?
> >>> Unfortunately not. They have been on the list since April and haven't
> >>> received any feedback.
> >>>
> >>> There isn't a lot of people reviewing the RISC-V patches unfortunately.
> >> :-(   I'd hoped it was a more active target than that.
> > There are lots of active contributors, we are just short on reviewers.
> >
> > Richard and Philippe review patches and some of the RISC-V patches get
> > reviewed by the RISC-V community. The main problem (which is a common
> > problem in open source) is that large technical patch series just get
> > ignored.
> Hi Alistair,
>
> It's really a pity.
>
> I will review every patch that CC me in no more than a week if no other
> people reviewed this patch.
>
> So if there too many patches, just ease to CC me.

Thanks!

If you want to review more it's also a good idea to sign up to the
RISC-V QEMU mailing list. That way you can keep an eye on all patches
and start with reviewing ones that are interesting to you.

Alistair

>
>
> Best Regards,
> Zhiwei
> >
> > Alistair
> >
> >> -- PMM
>

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