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charset="utf-8" From: Anup Patel We extend CLINT emulation to allow multiple instances of CLINT in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from CLINT emulation. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Palmer Dabbelt Message-Id: <20200616032229.766089-2-anup.patel@wdc.com> Signed-off-by: Alistair Francis reviewed-by tags, which seems a shame for a fairly significant --- include/hw/riscv/sifive_clint.h | 7 ++++--- hw/riscv/sifive_clint.c | 20 ++++++++++++-------- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 2 +- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 2 +- 6 files changed, 20 insertions(+), 15 deletions(-) diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/riscv/sifive_clin= t.h index 4a720bfece..9f5fb3d31d 100644 --- a/include/hw/riscv/sifive_clint.h +++ b/include/hw/riscv/sifive_clint.h @@ -33,6 +33,7 @@ typedef struct SiFiveCLINTState { =20 /*< public >*/ MemoryRegion mmio; + uint32_t hartid_base; uint32_t num_harts; uint32_t sip_base; uint32_t timecmp_base; @@ -40,9 +41,9 @@ typedef struct SiFiveCLINTState { uint32_t aperture_size; } SiFiveCLINTState; =20 -DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_ha= rts, - uint32_t sip_base, uint32_t timecmp_base, uint32_t time_base, - bool provide_rdtime); +DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, + uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base, + uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime); =20 enum { SIFIVE_SIP_BASE =3D 0x0, diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c index 669c21adc2..15e13d5f7a 100644 --- a/hw/riscv/sifive_clint.c +++ b/hw/riscv/sifive_clint.c @@ -79,7 +79,7 @@ static uint64_t sifive_clint_read(void *opaque, hwaddr ad= dr, unsigned size) SiFiveCLINTState *clint =3D opaque; if (addr >=3D clint->sip_base && addr < clint->sip_base + (clint->num_harts << 2)) { - size_t hartid =3D (addr - clint->sip_base) >> 2; + size_t hartid =3D clint->hartid_base + ((addr - clint->sip_base) >= > 2); CPUState *cpu =3D qemu_get_cpu(hartid); CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; if (!env) { @@ -92,7 +92,8 @@ static uint64_t sifive_clint_read(void *opaque, hwaddr ad= dr, unsigned size) } } else if (addr >=3D clint->timecmp_base && addr < clint->timecmp_base + (clint->num_harts << 3)) { - size_t hartid =3D (addr - clint->timecmp_base) >> 3; + size_t hartid =3D clint->hartid_base + + ((addr - clint->timecmp_base) >> 3); CPUState *cpu =3D qemu_get_cpu(hartid); CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; if (!env) { @@ -129,7 +130,7 @@ static void sifive_clint_write(void *opaque, hwaddr add= r, uint64_t value, =20 if (addr >=3D clint->sip_base && addr < clint->sip_base + (clint->num_harts << 2)) { - size_t hartid =3D (addr - clint->sip_base) >> 2; + size_t hartid =3D clint->hartid_base + ((addr - clint->sip_base) >= > 2); CPUState *cpu =3D qemu_get_cpu(hartid); CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; if (!env) { @@ -142,7 +143,8 @@ static void sifive_clint_write(void *opaque, hwaddr add= r, uint64_t value, return; } else if (addr >=3D clint->timecmp_base && addr < clint->timecmp_base + (clint->num_harts << 3)) { - size_t hartid =3D (addr - clint->timecmp_base) >> 3; + size_t hartid =3D clint->hartid_base + + ((addr - clint->timecmp_base) >> 3); CPUState *cpu =3D qemu_get_cpu(hartid); CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; if (!env) { @@ -186,6 +188,7 @@ static const MemoryRegionOps sifive_clint_ops =3D { }; =20 static Property sifive_clint_properties[] =3D { + DEFINE_PROP_UINT32("hartid-base", SiFiveCLINTState, hartid_base, 0), DEFINE_PROP_UINT32("num-harts", SiFiveCLINTState, num_harts, 0), DEFINE_PROP_UINT32("sip-base", SiFiveCLINTState, sip_base, 0), DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0), @@ -227,13 +230,13 @@ type_init(sifive_clint_register_types) /* * Create CLINT device. */ -DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_ha= rts, - uint32_t sip_base, uint32_t timecmp_base, uint32_t time_base, - bool provide_rdtime) +DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, + uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base, + uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime) { int i; for (i =3D 0; i < num_harts; i++) { - CPUState *cpu =3D qemu_get_cpu(i); + CPUState *cpu =3D qemu_get_cpu(hartid_base + i); CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; if (!env) { continue; @@ -247,6 +250,7 @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr si= ze, uint32_t num_harts, } =20 DeviceState *dev =3D qdev_new(TYPE_SIFIVE_CLINT); + qdev_prop_set_uint32(dev, "hartid-base", hartid_base); qdev_prop_set_uint32(dev, "num-harts", num_harts); qdev_prop_set_uint32(dev, "sip-base", sip_base); qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base); diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index c8b060486a..01f661d00c 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -211,7 +211,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Erro= r **errp) SIFIVE_E_PLIC_CONTEXT_STRIDE, memmap[SIFIVE_E_PLIC].size); sifive_clint_create(memmap[SIFIVE_E_CLINT].base, - memmap[SIFIVE_E_CLINT].size, ms->smp.cpus, + memmap[SIFIVE_E_CLINT].size, 0, ms->smp.cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); create_unimplemented_device("riscv.sifive.e.aon", memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 18301e6fa5..8d2ee9d026 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -703,7 +703,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Erro= r **errp) sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ= )); sifive_clint_create(memmap[SIFIVE_U_CLINT].base, - memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, + memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); =20 if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 13958bdbeb..5d422b4944 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -234,7 +234,7 @@ static void spike_board_init(MachineState *machine) =20 /* Core Local Interruptor (timer and IPI) */ sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, - smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, + 0, smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BAS= E, false); } =20 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 6e91cf129e..69cfca8501 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -571,7 +571,7 @@ static void virt_machine_init(MachineState *machine) VIRT_PLIC_CONTEXT_STRIDE, memmap[VIRT_PLIC].size); sifive_clint_create(memmap[VIRT_CLINT].base, - memmap[VIRT_CLINT].size, smp_cpus, + memmap[VIRT_CLINT].size, 0, smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true); 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charset="utf-8" From: Anup Patel We extend PLIC emulation to allow multiple instances of PLIC in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from PLIC emulation. Signed-off-by: Anup Patel Reviewed-by: Palmer Dabbelt Reviewed-by: Alistair Francis Message-Id: <20200616032229.766089-3-anup.patel@wdc.com> Signed-off-by: Alistair Francis reviewed-by tags, which seems a shame for a fairly significant --- include/hw/riscv/sifive_plic.h | 12 +++++++----- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_plic.c | 24 +++++++++++++----------- hw/riscv/sifive_u.c | 2 +- hw/riscv/virt.c | 2 +- 5 files changed, 23 insertions(+), 19 deletions(-) diff --git a/include/hw/riscv/sifive_plic.h b/include/hw/riscv/sifive_plic.h index 4421e81249..ace76d0f1b 100644 --- a/include/hw/riscv/sifive_plic.h +++ b/include/hw/riscv/sifive_plic.h @@ -48,6 +48,7 @@ typedef struct SiFivePLICState { /*< public >*/ MemoryRegion mmio; uint32_t num_addrs; + uint32_t num_harts; uint32_t bitfield_words; PLICAddr *addr_config; uint32_t *source_priority; @@ -58,6 +59,7 @@ typedef struct SiFivePLICState { =20 /* config */ char *hart_config; + uint32_t hartid_base; uint32_t num_sources; uint32_t num_priorities; uint32_t priority_base; @@ -70,10 +72,10 @@ typedef struct SiFivePLICState { } SiFivePLICState; =20 DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, - uint32_t num_sources, uint32_t num_priorities, - uint32_t priority_base, uint32_t pending_base, - uint32_t enable_base, uint32_t enable_stride, - uint32_t context_base, uint32_t context_stride, - uint32_t aperture_size); + uint32_t hartid_base, uint32_t num_sources, + uint32_t num_priorities, uint32_t priority_base, + uint32_t pending_base, uint32_t enable_base, + uint32_t enable_stride, uint32_t context_base, + uint32_t context_stride, uint32_t aperture_size); =20 #endif diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 01f661d00c..ca55cc438a 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -200,7 +200,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Erro= r **errp) =20 /* MMIO */ s->plic =3D sifive_plic_create(memmap[SIFIVE_E_PLIC].base, - (char *)SIFIVE_E_PLIC_HART_CONFIG, + (char *)SIFIVE_E_PLIC_HART_CONFIG, 0, SIFIVE_E_PLIC_NUM_SOURCES, SIFIVE_E_PLIC_NUM_PRIORITIES, SIFIVE_E_PLIC_PRIORITY_BASE, diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index c20c192034..11ef147606 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -361,6 +361,7 @@ static const MemoryRegionOps sifive_plic_ops =3D { =20 static Property sifive_plic_properties[] =3D { DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config), + DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0), DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0), DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, = 0), DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0), @@ -409,10 +410,12 @@ static void parse_hart_config(SiFivePLICState *plic) } hartid++; =20 - /* store hart/mode combinations */ plic->num_addrs =3D addrid; + plic->num_harts =3D hartid; + + /* store hart/mode combinations */ plic->addr_config =3D g_new(PLICAddr, plic->num_addrs); - addrid =3D 0, hartid =3D 0; + addrid =3D 0, hartid =3D plic->hartid_base; p =3D plic->hart_config; while ((c =3D *p++)) { if (c =3D=3D ',') { @@ -438,8 +441,6 @@ static void sifive_plic_irq_request(void *opaque, int i= rq, int level) =20 static void sifive_plic_realize(DeviceState *dev, Error **errp) { - MachineState *ms =3D MACHINE(qdev_get_machine()); - unsigned int smp_cpus =3D ms->smp.cpus; SiFivePLICState *plic =3D SIFIVE_PLIC(dev); int i; =20 @@ -460,8 +461,8 @@ static void sifive_plic_realize(DeviceState *dev, Error= **errp) * lost a interrupt in the case a PLIC is attached. The SEIP bit must = be * hardware controlled when a PLIC is attached. */ - for (i =3D 0; i < smp_cpus; i++) { - RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(i)); + for (i =3D 0; i < plic->num_harts; i++) { + RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(plic->hartid_base + i)); if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) { error_report("SEIP already claimed"); exit(1); @@ -497,16 +498,17 @@ type_init(sifive_plic_register_types) * Create PLIC device. */ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, - uint32_t num_sources, uint32_t num_priorities, - uint32_t priority_base, uint32_t pending_base, - uint32_t enable_base, uint32_t enable_stride, - uint32_t context_base, uint32_t context_stride, - uint32_t aperture_size) + uint32_t hartid_base, uint32_t num_sources, + uint32_t num_priorities, uint32_t priority_base, + uint32_t pending_base, uint32_t enable_base, + uint32_t enable_stride, uint32_t context_base, + uint32_t context_stride, uint32_t aperture_size) { DeviceState *dev =3D qdev_new(TYPE_SIFIVE_PLIC); assert(enable_stride =3D=3D (enable_stride & -enable_stride)); assert(context_stride =3D=3D (context_stride & -context_stride)); qdev_prop_set_string(dev, "hart-config", hart_config); + qdev_prop_set_uint32(dev, "hartid-base", hartid_base); qdev_prop_set_uint32(dev, "num-sources", num_sources); qdev_prop_set_uint32(dev, "num-priorities", num_priorities); qdev_prop_set_uint32(dev, "priority-base", priority_base); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 8d2ee9d026..a48046c6a0 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -687,7 +687,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Erro= r **errp) =20 /* MMIO */ s->plic =3D sifive_plic_create(memmap[SIFIVE_U_PLIC].base, - plic_hart_config, + plic_hart_config, 0, SIFIVE_U_PLIC_NUM_SOURCES, SIFIVE_U_PLIC_NUM_PRIORITIES, SIFIVE_U_PLIC_PRIORITY_BASE, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 69cfca8501..8a66f43ee0 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -560,7 +560,7 @@ static void virt_machine_init(MachineState *machine) =20 /* MMIO */ s->plic =3D sifive_plic_create(memmap[VIRT_PLIC].base, - plic_hart_config, + plic_hart_config, 0, VIRT_PLIC_NUM_SOURCES, VIRT_PLIC_NUM_PRIORITIES, VIRT_PLIC_PRIORITY_BASE, --=20 2.28.0 From nobody Sat May 18 21:26:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Anup Patel We add common helper routines which can be shared by RISC-V multi-socket NUMA machines. We have two types of helpers: 1. riscv_socket_xyz() - These helper assist managing multiple sockets irrespective whether QEMU NUMA is enabled/disabled 2. riscv_numa_xyz() - These helpers assist in providing necessary QEMU machine callbacks for QEMU NUMA emulation Signed-off-by: Anup Patel Reviewed-by: Atish Patra Message-Id: <20200616032229.766089-4-anup.patel@wdc.com> Signed-off-by: Alistair Francis reviewed-by tags, which seems a shame for a fairly significant --- include/hw/riscv/numa.h | 113 +++++++++++++++++++ hw/riscv/numa.c | 242 ++++++++++++++++++++++++++++++++++++++++ hw/riscv/meson.build | 1 + 3 files changed, 356 insertions(+) create mode 100644 include/hw/riscv/numa.h create mode 100644 hw/riscv/numa.c diff --git a/include/hw/riscv/numa.h b/include/hw/riscv/numa.h new file mode 100644 index 0000000000..fcce942cee --- /dev/null +++ b/include/hw/riscv/numa.h @@ -0,0 +1,113 @@ +/* + * QEMU RISC-V NUMA Helper + * + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef RISCV_NUMA_H +#define RISCV_NUMA_H + +#include "hw/sysbus.h" +#include "sysemu/numa.h" + +/** + * riscv_socket_count: + * @ms: pointer to machine state + * + * Returns: number of sockets for a numa system and 1 for a non-numa system + */ +int riscv_socket_count(const MachineState *ms); + +/** + * riscv_socket_first_hartid: + * @ms: pointer to machine state + * @socket_id: socket index + * + * Returns: first hartid for a valid socket and -1 for an invalid socket + */ +int riscv_socket_first_hartid(const MachineState *ms, int socket_id); + +/** + * riscv_socket_last_hartid: + * @ms: pointer to machine state + * @socket_id: socket index + * + * Returns: last hartid for a valid socket and -1 for an invalid socket + */ +int riscv_socket_last_hartid(const MachineState *ms, int socket_id); + +/** + * riscv_socket_hart_count: + * @ms: pointer to machine state + * @socket_id: socket index + * + * Returns: number of harts for a valid socket and -1 for an invalid socket + */ +int riscv_socket_hart_count(const MachineState *ms, int socket_id); + +/** + * riscv_socket_mem_offset: + * @ms: pointer to machine state + * @socket_id: socket index + * + * Returns: offset of ram belonging to given socket + */ +uint64_t riscv_socket_mem_offset(const MachineState *ms, int socket_id); + +/** + * riscv_socket_mem_size: + * @ms: pointer to machine state + * @socket_id: socket index + * + * Returns: size of ram belonging to given socket + */ +uint64_t riscv_socket_mem_size(const MachineState *ms, int socket_id); + +/** + * riscv_socket_check_hartids: + * @ms: pointer to machine state + * @socket_id: socket index + * + * Returns: true if hardids belonging to given socket are contiguous else = false + */ +bool riscv_socket_check_hartids(const MachineState *ms, int socket_id); + +/** + * riscv_socket_fdt_write_id: + * @ms: pointer to machine state + * @socket_id: socket index + * + * Write NUMA node-id FDT property for given FDT node + */ +void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt, + const char *node_name, int socket_id); + +/** + * riscv_socket_fdt_write_distance_matrix: + * @ms: pointer to machine state + * @socket_id: socket index + * + * Write NUMA distance matrix in FDT for given machine + */ +void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *= fdt); + +CpuInstanceProperties +riscv_numa_cpu_index_to_props(MachineState *ms, unsigned cpu_index); + +int64_t riscv_numa_get_default_cpu_node_id(const MachineState *ms, int idx= ); + +const CPUArchIdList *riscv_numa_possible_cpu_arch_ids(MachineState *ms); + +#endif /* RISCV_NUMA_H */ diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c new file mode 100644 index 0000000000..4f92307102 --- /dev/null +++ b/hw/riscv/numa.c @@ -0,0 +1,242 @@ +/* + * QEMU RISC-V NUMA Helper + * + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/qdev-properties.h" +#include "hw/riscv/numa.h" +#include "sysemu/device_tree.h" + +static bool numa_enabled(const MachineState *ms) +{ + return (ms->numa_state && ms->numa_state->num_nodes) ? true : false; +} + +int riscv_socket_count(const MachineState *ms) +{ + return (numa_enabled(ms)) ? ms->numa_state->num_nodes : 1; +} + +int riscv_socket_first_hartid(const MachineState *ms, int socket_id) +{ + int i, first_hartid =3D ms->smp.cpus; + + if (!numa_enabled(ms)) { + return (!socket_id) ? 0 : -1; + } + + for (i =3D 0; i < ms->smp.cpus; i++) { + if (ms->possible_cpus->cpus[i].props.node_id !=3D socket_id) { + continue; + } + if (i < first_hartid) { + first_hartid =3D i; + } + } + + return (first_hartid < ms->smp.cpus) ? first_hartid : -1; +} + +int riscv_socket_last_hartid(const MachineState *ms, int socket_id) +{ + int i, last_hartid =3D -1; + + if (!numa_enabled(ms)) { + return (!socket_id) ? ms->smp.cpus - 1 : -1; + } + + for (i =3D 0; i < ms->smp.cpus; i++) { + if (ms->possible_cpus->cpus[i].props.node_id !=3D socket_id) { + continue; + } + if (i > last_hartid) { + last_hartid =3D i; + } + } + + return (last_hartid < ms->smp.cpus) ? last_hartid : -1; +} + +int riscv_socket_hart_count(const MachineState *ms, int socket_id) +{ + int first_hartid, last_hartid; + + if (!numa_enabled(ms)) { + return (!socket_id) ? ms->smp.cpus : -1; + } + + first_hartid =3D riscv_socket_first_hartid(ms, socket_id); + if (first_hartid < 0) { + return -1; + } + + last_hartid =3D riscv_socket_last_hartid(ms, socket_id); + if (last_hartid < 0) { + return -1; + } + + if (first_hartid > last_hartid) { + return -1; + } + + return last_hartid - first_hartid + 1; +} + +bool riscv_socket_check_hartids(const MachineState *ms, int socket_id) +{ + int i, first_hartid, last_hartid; + + if (!numa_enabled(ms)) { + return (!socket_id) ? true : false; + } + + first_hartid =3D riscv_socket_first_hartid(ms, socket_id); + if (first_hartid < 0) { + return false; + } + + last_hartid =3D riscv_socket_last_hartid(ms, socket_id); + if (last_hartid < 0) { + return false; + } + + for (i =3D first_hartid; i <=3D last_hartid; i++) { + if (ms->possible_cpus->cpus[i].props.node_id !=3D socket_id) { + return false; + } + } + + return true; +} + +uint64_t riscv_socket_mem_offset(const MachineState *ms, int socket_id) +{ + int i; + uint64_t mem_offset =3D 0; + + if (!numa_enabled(ms)) { + return 0; + } + + for (i =3D 0; i < ms->numa_state->num_nodes; i++) { + if (i =3D=3D socket_id) { + break; + } + mem_offset +=3D ms->numa_state->nodes[i].node_mem; + } + + return (i =3D=3D socket_id) ? mem_offset : 0; +} + +uint64_t riscv_socket_mem_size(const MachineState *ms, int socket_id) +{ + if (!numa_enabled(ms)) { + return (!socket_id) ? ms->ram_size : 0; + } + + return (socket_id < ms->numa_state->num_nodes) ? + ms->numa_state->nodes[socket_id].node_mem : 0; +} + +void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt, + const char *node_name, int socket_id) +{ + if (numa_enabled(ms)) { + qemu_fdt_setprop_cell(fdt, node_name, "numa-node-id", socket_id); + } +} + +void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *= fdt) +{ + int i, j, idx; + uint32_t *dist_matrix, dist_matrix_size; + + if (numa_enabled(ms) && ms->numa_state->have_numa_distance) { + dist_matrix_size =3D riscv_socket_count(ms) * riscv_socket_count(m= s); + dist_matrix_size *=3D (3 * sizeof(uint32_t)); + dist_matrix =3D g_malloc0(dist_matrix_size); + + for (i =3D 0; i < riscv_socket_count(ms); i++) { + for (j =3D 0; j < riscv_socket_count(ms); j++) { + idx =3D (i * riscv_socket_count(ms) + j) * 3; + dist_matrix[idx + 0] =3D cpu_to_be32(i); + dist_matrix[idx + 1] =3D cpu_to_be32(j); + dist_matrix[idx + 2] =3D + cpu_to_be32(ms->numa_state->nodes[i].distance[j]); + } + } + + qemu_fdt_add_subnode(fdt, "/distance-map"); + qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", + "numa-distance-map-v1"); + qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", + dist_matrix, dist_matrix_size); + g_free(dist_matrix); + } +} + +CpuInstanceProperties +riscv_numa_cpu_index_to_props(MachineState *ms, unsigned cpu_index) +{ + MachineClass *mc =3D MACHINE_GET_CLASS(ms); + const CPUArchIdList *possible_cpus =3D mc->possible_cpu_arch_ids(ms); + + assert(cpu_index < possible_cpus->len); + return possible_cpus->cpus[cpu_index].props; +} + +int64_t riscv_numa_get_default_cpu_node_id(const MachineState *ms, int idx) +{ + int64_t nidx =3D 0; + + if (ms->numa_state->num_nodes) { + nidx =3D idx / (ms->smp.cpus / ms->numa_state->num_nodes); + if (ms->numa_state->num_nodes <=3D nidx) { + nidx =3D ms->numa_state->num_nodes - 1; + } + } + + return nidx; +} + +const CPUArchIdList *riscv_numa_possible_cpu_arch_ids(MachineState *ms) +{ + int n; + unsigned int max_cpus =3D ms->smp.max_cpus; + + if (ms->possible_cpus) { + assert(ms->possible_cpus->len =3D=3D max_cpus); + return ms->possible_cpus; + } + + ms->possible_cpus =3D g_malloc0(sizeof(CPUArchIdList) + + sizeof(CPUArchId) * max_cpus); + ms->possible_cpus->len =3D max_cpus; + for (n =3D 0; n < ms->possible_cpus->len; n++) { + ms->possible_cpus->cpus[n].type =3D ms->cpu_type; + ms->possible_cpus->cpus[n].arch_id =3D n; + ms->possible_cpus->cpus[n].props.has_core_id =3D true; + ms->possible_cpus->cpus[n].props.core_id =3D n; + } + + return ms->possible_cpus; +} diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 2de8e5a2fe..25af9db75e 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -1,5 +1,6 @@ riscv_ss =3D ss.source_set() riscv_ss.add(files('boot.c')) +riscv_ss.add(files('numa.c')) riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c')) riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) --=20 2.28.0 From nobody Sat May 18 21:26:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1598382023; cv=none; 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d="scan'208";a="150145286" IronPort-SDR: Q7BwrAo9ReuIwG9LpEtzuMassjADRGaCEl3cpWlIfjcAD7hJ13IUea66fOIPWLXmIXZxUrJW3w 9blzi2nrGW+w== IronPort-SDR: rmDDOUTxSzaOPCKSKwTU/HzUykQu+3pcya6qkeFJalwo/tjP7SnGsIzXnfotyAHZ/t/bWlWD/B 5orJbZXwsRtg== WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org Subject: [PULL 04/18] hw/riscv: spike: Allow creating multiple NUMA sockets Date: Tue, 25 Aug 2020 11:48:22 -0700 Message-Id: <20200825184836.1282371-5-alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200825184836.1282371-1-alistair.francis@wdc.com> References: <20200825184836.1282371-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=49978a6e9=alistair.francis@wdc.com; helo=esa3.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/25 14:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Anup Patel , alistair.francis@wdc.com, Atish Patra Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Anup Patel We extend RISC-V spike machine to allow creating a multi-socket machine. Each RISC-V spike machine socket is a NUMA node having a set of HARTs, a memory instance, and a CLINT instance. Other devices are shared between all sockets. We also update the generated device tree accordingly. By default, NUMA multi-socket support is disabled for RISC-V spike machine. To enable it, users can use "-numa" command-line options of QEMU. Example1: For two NUMA nodes with 2 CPUs each, append following to command-line options: "-smp 4 -numa node -numa node" Example2: For two NUMA nodes with 1 and 3 CPUs, append following to command-line options: "-smp 4 -numa node -numa node -numa cpu,node-id=3D0,core-id=3D0 \ -numa cpu,node-id=3D1,core-id=3D1 -numa cpu,node-id=3D1,core-id=3D2 \ -numa cpu,node-id=3D1,core-id=3D3" The maximum number of sockets in a RISC-V spike machine is 8 but this limit can be changed in future. Signed-off-by: Anup Patel Reviewed-by: Atish Patra Message-Id: <20200616032229.766089-5-anup.patel@wdc.com> Signed-off-by: Alistair Francis reviewed-by tags, which seems a shame for a fairly significant --- include/hw/riscv/spike.h | 11 +- hw/riscv/spike.c | 232 ++++++++++++++++++++++++++------------- 2 files changed, 167 insertions(+), 76 deletions(-) diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index 1cd72b85d6..b0a18a9c94 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -22,12 +22,19 @@ #include "hw/riscv/riscv_hart.h" #include "hw/sysbus.h" =20 +#define SPIKE_CPUS_MAX 8 +#define SPIKE_SOCKETS_MAX 8 + +#define TYPE_SPIKE_MACHINE MACHINE_TYPE_NAME("spike") +#define SPIKE_MACHINE(obj) \ + OBJECT_CHECK(SpikeState, (obj), TYPE_SPIKE_MACHINE) + typedef struct { /*< private >*/ - SysBusDevice parent_obj; + MachineState parent; =20 /*< public >*/ - RISCVHartArrayState soc; + RISCVHartArrayState soc[SPIKE_SOCKETS_MAX]; void *fdt; int fdt_size; } SpikeState; diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 5d422b4944..56f5fe73c7 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -36,6 +36,7 @@ #include "hw/riscv/sifive_clint.h" #include "hw/riscv/spike.h" #include "hw/riscv/boot.h" +#include "hw/riscv/numa.h" #include "chardev/char.h" #include "sysemu/arch_init.h" #include "sysemu/device_tree.h" @@ -66,9 +67,14 @@ static void create_fdt(SpikeState *s, const struct Memma= pEntry *memmap, uint64_t mem_size, const char *cmdline) { void *fdt; - int cpu; - uint32_t *cells; - char *nodename; + uint64_t addr, size; + unsigned long clint_addr; + int cpu, socket; + MachineState *mc =3D MACHINE(s); + uint32_t *clint_cells; + uint32_t cpu_phandle, intc_phandle, phandle =3D 1; + char *name, *mem_name, *clint_name, *clust_name; + char *core_name, *cpu_name, *intc_name; =20 fdt =3D s->fdt =3D create_device_tree(&s->fdt_size); if (!fdt) { @@ -90,68 +96,91 @@ static void create_fdt(SpikeState *s, const struct Memm= apEntry *memmap, qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); =20 - nodename =3D g_strdup_printf("/memory@%lx", - (long)memmap[SPIKE_DRAM].base); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cells(fdt, nodename, "reg", - memmap[SPIKE_DRAM].base >> 32, memmap[SPIKE_DRAM].base, - mem_size >> 32, mem_size); - qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); - g_free(nodename); - qemu_fdt_add_subnode(fdt, "/cpus"); qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", SIFIVE_CLINT_TIMEBASE_FREQ); qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); + qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); + + for (socket =3D (riscv_socket_count(mc) - 1); socket >=3D 0; socket--)= { + clust_name =3D g_strdup_printf("/cpus/cpu-map/cluster%d", socket); + qemu_fdt_add_subnode(fdt, clust_name); + + clint_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 4); =20 - for (cpu =3D s->soc.num_harts - 1; cpu >=3D 0; cpu--) { - nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); - char *intc =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controller"= , cpu); - char *isa =3D riscv_isa_string(&s->soc.harts[cpu]); - qemu_fdt_add_subnode(fdt, nodename); + for (cpu =3D s->soc[socket].num_harts - 1; cpu >=3D 0; cpu--) { + cpu_phandle =3D phandle++; + + cpu_name =3D g_strdup_printf("/cpus/cpu@%d", + s->soc[socket].hartid_base + cpu); + qemu_fdt_add_subnode(fdt, cpu_name); #if defined(TARGET_RISCV32) - qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32= "); #else - qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48= "); #endif - qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); - qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); - qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); - qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); - qemu_fdt_add_subnode(fdt, intc); - qemu_fdt_setprop_cell(fdt, intc, "phandle", 1); - qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); - qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); - g_free(isa); - g_free(intc); - g_free(nodename); - } + name =3D riscv_isa_string(&s->soc[socket].harts[cpu]); + qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); + g_free(name); + qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); + qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); + qemu_fdt_setprop_cell(fdt, cpu_name, "reg", + s->soc[socket].hartid_base + cpu); + qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); + riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); + qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); =20 - cells =3D g_new0(uint32_t, s->soc.num_harts * 4); - for (cpu =3D 0; cpu < s->soc.num_harts; cpu++) { - nodename =3D - g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); - uint32_t intc_phandle =3D qemu_fdt_get_phandle(fdt, nodename); - cells[cpu * 4 + 0] =3D cpu_to_be32(intc_phandle); - cells[cpu * 4 + 1] =3D cpu_to_be32(IRQ_M_SOFT); - cells[cpu * 4 + 2] =3D cpu_to_be32(intc_phandle); - cells[cpu * 4 + 3] =3D cpu_to_be32(IRQ_M_TIMER); - g_free(nodename); + intc_name =3D g_strdup_printf("%s/interrupt-controller", cpu_n= ame); + qemu_fdt_add_subnode(fdt, intc_name); + intc_phandle =3D phandle++; + qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle); + qemu_fdt_setprop_string(fdt, intc_name, "compatible", + "riscv,cpu-intc"); + qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL,= 0); + qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); + + clint_cells[cpu * 4 + 0] =3D cpu_to_be32(intc_phandle); + clint_cells[cpu * 4 + 1] =3D cpu_to_be32(IRQ_M_SOFT); + clint_cells[cpu * 4 + 2] =3D cpu_to_be32(intc_phandle); + clint_cells[cpu * 4 + 3] =3D cpu_to_be32(IRQ_M_TIMER); + + core_name =3D g_strdup_printf("%s/core%d", clust_name, cpu); + qemu_fdt_add_subnode(fdt, core_name); + qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); + + g_free(core_name); + g_free(intc_name); + g_free(cpu_name); + } + + addr =3D memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, soc= ket); + size =3D riscv_socket_mem_size(mc, socket); + mem_name =3D g_strdup_printf("/memory@%lx", (long)addr); + qemu_fdt_add_subnode(fdt, mem_name); + qemu_fdt_setprop_cells(fdt, mem_name, "reg", + addr >> 32, addr, size >> 32, size); + qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); + riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); + g_free(mem_name); + + clint_addr =3D memmap[SPIKE_CLINT].base + + (memmap[SPIKE_CLINT].size * socket); + clint_name =3D g_strdup_printf("/soc/clint@%lx", clint_addr); + qemu_fdt_add_subnode(fdt, clint_name); + qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clin= t0"); + qemu_fdt_setprop_cells(fdt, clint_name, "reg", + 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); + qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", + clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); + riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); + + g_free(clint_name); + g_free(clint_cells); + g_free(clust_name); } - nodename =3D g_strdup_printf("/soc/clint@%lx", - (long)memmap[SPIKE_CLINT].base); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); - qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[SPIKE_CLINT].base, - 0x0, memmap[SPIKE_CLINT].size); - qemu_fdt_setprop(fdt, nodename, "interrupts-extended", - cells, s->soc.num_harts * sizeof(uint32_t) * 4); - g_free(cells); - g_free(nodename); + + riscv_socket_fdt_write_distance_matrix(mc, fdt); =20 if (cmdline) { qemu_fdt_add_subnode(fdt, "/chosen"); @@ -162,23 +191,59 @@ static void create_fdt(SpikeState *s, const struct Me= mmapEntry *memmap, static void spike_board_init(MachineState *machine) { const struct MemmapEntry *memmap =3D spike_memmap; - - SpikeState *s =3D g_new0(SpikeState, 1); + SpikeState *s =3D SPIKE_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); - unsigned int smp_cpus =3D machine->smp.cpus; uint32_t fdt_load_addr; uint64_t kernel_entry; + char *soc_name; + int i, base_hartid, hart_count; =20 - /* Initialize SOC */ - object_initialize_child(OBJECT(machine), "soc", &s->soc, - TYPE_RISCV_HART_ARRAY); - object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, - &error_abort); - object_property_set_int(OBJECT(&s->soc), "num-harts", smp_cpus, - &error_abort); - sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort); + /* Check socket count limit */ + if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) { + error_report("number of sockets/nodes should be less than %d", + SPIKE_SOCKETS_MAX); + exit(1); + } + + /* Initialize sockets */ + for (i =3D 0; i < riscv_socket_count(machine); i++) { + if (!riscv_socket_check_hartids(machine, i)) { + error_report("discontinuous hartids in socket%d", i); + exit(1); + } + + base_hartid =3D riscv_socket_first_hartid(machine, i); + if (base_hartid < 0) { + error_report("can't find hartid base for socket%d", i); + exit(1); + } + + hart_count =3D riscv_socket_hart_count(machine, i); + if (hart_count < 0) { + error_report("can't find hart count for socket%d", i); + exit(1); + } + + soc_name =3D g_strdup_printf("soc%d", i); + object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], + TYPE_RISCV_HART_ARRAY); + g_free(soc_name); + object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", + machine->cpu_type, &error_abort); + object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", + base_hartid, &error_abort); + object_property_set_int(OBJECT(&s->soc[i]), "num-harts", + hart_count, &error_abort); + sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); + + /* Core Local Interruptor (timer and IPI) for each socket */ + sifive_clint_create( + memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size, + memmap[SPIKE_CLINT].size, base_hartid, hart_count, + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); + } =20 /* register system main memory (actual RAM) */ memory_region_init_ram(main_mem, NULL, "riscv.spike.ram", @@ -230,21 +295,40 @@ static void spike_board_init(MachineState *machine) fdt_load_addr, s->fdt); =20 /* initialize HTIF using symbols found in load_kernel */ - htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(= 0)); + htif_mm_init(system_memory, mask_rom, + &s->soc[0].harts[0].env, serial_hd(0)); +} =20 - /* Core Local Interruptor (timer and IPI) */ - sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, - 0, smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BAS= E, - false); +static void spike_machine_instance_init(Object *obj) +{ } =20 -static void spike_machine_init(MachineClass *mc) +static void spike_machine_class_init(ObjectClass *oc, void *data) { - mc->desc =3D "RISC-V Spike Board"; + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "RISC-V Spike board"; mc->init =3D spike_board_init; - mc->max_cpus =3D 8; + mc->max_cpus =3D SPIKE_CPUS_MAX; mc->is_default =3D true; mc->default_cpu_type =3D SPIKE_V1_10_0_CPU; + mc->possible_cpu_arch_ids =3D riscv_numa_possible_cpu_arch_ids; + mc->cpu_index_to_instance_props =3D riscv_numa_cpu_index_to_props; + mc->get_default_cpu_node_id =3D riscv_numa_get_default_cpu_node_id; + mc->numa_mem_supported =3D true; +} + +static const TypeInfo spike_machine_typeinfo =3D { + .name =3D MACHINE_TYPE_NAME("spike"), + .parent =3D TYPE_MACHINE, + .class_init =3D spike_machine_class_init, + .instance_init =3D spike_machine_instance_init, + .instance_size =3D sizeof(SpikeState), +}; + +static void spike_machine_init_register_types(void) +{ + type_register_static(&spike_machine_typeinfo); } =20 -DEFINE_MACHINE("spike", spike_machine_init) +type_init(spike_machine_init_register_types) --=20 2.28.0 From nobody Sat May 18 21:26:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="150145287" IronPort-SDR: y4Y7Af/4DZAVK8ekbyGGP3K+8WNQti7my6VIfVqHJVaoRVwR3Av17oNvSzhrzCyrCM4OEzaEft i6yb6RDE2bDA== IronPort-SDR: qW8Zz5jJ/OcfaSxP3ovrSJ5FudVa7ivnpLxsD/dWx83h7gvRSFVAgo9H1DSv7Bnr9abKQFQcqu SelZuMGU/AKg== WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org Subject: [PULL 05/18] hw/riscv: virt: Allow creating multiple NUMA sockets Date: Tue, 25 Aug 2020 11:48:23 -0700 Message-Id: <20200825184836.1282371-6-alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200825184836.1282371-1-alistair.francis@wdc.com> References: <20200825184836.1282371-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=49978a6e9=alistair.francis@wdc.com; helo=esa3.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/25 14:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Anup Patel , alistair.francis@wdc.com, Atish Patra Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Anup Patel We extend RISC-V virt machine to allow creating a multi-socket machine. Each RISC-V virt machine socket is a NUMA node having a set of HARTs, a memory instance, a CLINT instance, and a PLIC instance. Other devices are shared between all sockets. We also update the generated device tree accordingly. By default, NUMA multi-socket support is disabled for RISC-V virt machine. To enable it, users can use "-numa" command-line options of QEMU. Example1: For two NUMA nodes with 2 CPUs each, append following to command-line options: "-smp 4 -numa node -numa node" Example2: For two NUMA nodes with 1 and 3 CPUs, append following to command-line options: "-smp 4 -numa node -numa node -numa cpu,node-id=3D0,core-id=3D0 \ -numa cpu,node-id=3D1,core-id=3D1 -numa cpu,node-id=3D1,core-id=3D2 \ -numa cpu,node-id=3D1,core-id=3D3" The maximum number of sockets in a RISC-V virt machine is 8 but this limit can be changed in future. Signed-off-by: Anup Patel Reviewed-by: Atish Patra Message-Id: <20200616032229.766089-6-anup.patel@wdc.com> Signed-off-by: Alistair Francis reviewed-by tags, which seems a shame for a fairly significant --- include/hw/riscv/virt.h | 9 +- hw/riscv/virt.c | 526 +++++++++++++++++++++++----------------- 2 files changed, 306 insertions(+), 229 deletions(-) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index e69355efaf..1beacd7666 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -23,6 +23,9 @@ #include "hw/sysbus.h" #include "hw/block/flash.h" =20 +#define VIRT_CPUS_MAX 8 +#define VIRT_SOCKETS_MAX 8 + #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt") #define RISCV_VIRT_MACHINE(obj) \ OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_MACHINE) @@ -32,8 +35,8 @@ typedef struct { MachineState parent; =20 /*< public >*/ - RISCVHartArrayState soc; - DeviceState *plic; + RISCVHartArrayState soc[VIRT_SOCKETS_MAX]; + DeviceState *plic[VIRT_SOCKETS_MAX]; PFlashCFI01 *flash[2]; =20 void *fdt; @@ -74,6 +77,8 @@ enum { #define VIRT_PLIC_ENABLE_STRIDE 0x80 #define VIRT_PLIC_CONTEXT_BASE 0x200000 #define VIRT_PLIC_CONTEXT_STRIDE 0x1000 +#define VIRT_PLIC_SIZE(__num_context) \ + (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE) =20 #define FDT_PCI_ADDR_CELLS 3 #define FDT_PCI_INT_CELLS 1 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 8a66f43ee0..6fca513ec9 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -35,6 +35,7 @@ #include "hw/riscv/sifive_test.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" +#include "hw/riscv/numa.h" #include "chardev/char.h" #include "sysemu/arch_init.h" #include "sysemu/device_tree.h" @@ -58,7 +59,7 @@ static const struct MemmapEntry { [VIRT_RTC] =3D { 0x101000, 0x1000 }, [VIRT_CLINT] =3D { 0x2000000, 0x10000 }, [VIRT_PCIE_PIO] =3D { 0x3000000, 0x10000 }, - [VIRT_PLIC] =3D { 0xc000000, 0x4000000 }, + [VIRT_PLIC] =3D { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2)= }, [VIRT_UART0] =3D { 0x10000000, 0x100 }, [VIRT_VIRTIO] =3D { 0x10001000, 0x1000 }, [VIRT_FLASH] =3D { 0x20000000, 0x4000000 }, @@ -179,10 +180,17 @@ static void create_fdt(RISCVVirtState *s, const struc= t MemmapEntry *memmap, uint64_t mem_size, const char *cmdline) { void *fdt; - int cpu, i; - uint32_t *cells; - char *nodename; - uint32_t plic_phandle, test_phandle, phandle =3D 1; + int i, cpu, socket; + MachineState *mc =3D MACHINE(s); + uint64_t addr, size; + uint32_t *clint_cells, *plic_cells; + unsigned long clint_addr, plic_addr; + uint32_t plic_phandle[MAX_NODES]; + uint32_t cpu_phandle, intc_phandle, test_phandle; + uint32_t phandle =3D 1, plic_mmio_phandle =3D 1; + uint32_t plic_pcie_phandle =3D 1, plic_virtio_phandle =3D 1; + char *mem_name, *cpu_name, *core_name, *intc_name; + char *name, *clint_name, *plic_name, *clust_name; hwaddr flashsize =3D virt_memmap[VIRT_FLASH].size / 2; hwaddr flashbase =3D virt_memmap[VIRT_FLASH].base; =20 @@ -203,231 +211,238 @@ static void create_fdt(RISCVVirtState *s, const str= uct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); =20 - nodename =3D g_strdup_printf("/memory@%lx", - (long)memmap[VIRT_DRAM].base); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cells(fdt, nodename, "reg", - memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base, - mem_size >> 32, mem_size); - qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); - g_free(nodename); - qemu_fdt_add_subnode(fdt, "/cpus"); qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", SIFIVE_CLINT_TIMEBASE_FREQ); qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); + qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); + + for (socket =3D (riscv_socket_count(mc) - 1); socket >=3D 0; socket--)= { + clust_name =3D g_strdup_printf("/cpus/cpu-map/cluster%d", socket); + qemu_fdt_add_subnode(fdt, clust_name); + + plic_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 4); + clint_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 4); + + for (cpu =3D s->soc[socket].num_harts - 1; cpu >=3D 0; cpu--) { + cpu_phandle =3D phandle++; =20 - for (cpu =3D s->soc.num_harts - 1; cpu >=3D 0; cpu--) { - int cpu_phandle =3D phandle++; - int intc_phandle; - nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); - char *intc =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controller"= , cpu); - char *isa =3D riscv_isa_string(&s->soc.harts[cpu]); - qemu_fdt_add_subnode(fdt, nodename); + cpu_name =3D g_strdup_printf("/cpus/cpu@%d", + s->soc[socket].hartid_base + cpu); + qemu_fdt_add_subnode(fdt, cpu_name); #if defined(TARGET_RISCV32) - qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32= "); #else - qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48= "); #endif - qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); - qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); - qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); - qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); - qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle); - intc_phandle =3D phandle++; - qemu_fdt_add_subnode(fdt, intc); - qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle); - qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); - qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); - g_free(isa); - g_free(intc); - g_free(nodename); - } + name =3D riscv_isa_string(&s->soc[socket].harts[cpu]); + qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); + g_free(name); + qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); + qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); + qemu_fdt_setprop_cell(fdt, cpu_name, "reg", + s->soc[socket].hartid_base + cpu); + qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); + riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); + qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); + + intc_name =3D g_strdup_printf("%s/interrupt-controller", cpu_n= ame); + qemu_fdt_add_subnode(fdt, intc_name); + intc_phandle =3D phandle++; + qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle); + qemu_fdt_setprop_string(fdt, intc_name, "compatible", + "riscv,cpu-intc"); + qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL,= 0); + qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); + + clint_cells[cpu * 4 + 0] =3D cpu_to_be32(intc_phandle); + clint_cells[cpu * 4 + 1] =3D cpu_to_be32(IRQ_M_SOFT); + clint_cells[cpu * 4 + 2] =3D cpu_to_be32(intc_phandle); + clint_cells[cpu * 4 + 3] =3D cpu_to_be32(IRQ_M_TIMER); + + plic_cells[cpu * 4 + 0] =3D cpu_to_be32(intc_phandle); + plic_cells[cpu * 4 + 1] =3D cpu_to_be32(IRQ_M_EXT); + plic_cells[cpu * 4 + 2] =3D cpu_to_be32(intc_phandle); + plic_cells[cpu * 4 + 3] =3D cpu_to_be32(IRQ_S_EXT); + + core_name =3D g_strdup_printf("%s/core%d", clust_name, cpu); + qemu_fdt_add_subnode(fdt, core_name); + qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); + + g_free(core_name); + g_free(intc_name); + g_free(cpu_name); + } =20 - /* Add cpu-topology node */ - qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); - qemu_fdt_add_subnode(fdt, "/cpus/cpu-map/cluster0"); - for (cpu =3D s->soc.num_harts - 1; cpu >=3D 0; cpu--) { - char *core_nodename =3D g_strdup_printf("/cpus/cpu-map/cluster0/co= re%d", - cpu); - char *cpu_nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); - uint32_t intc_phandle =3D qemu_fdt_get_phandle(fdt, cpu_nodename); - qemu_fdt_add_subnode(fdt, core_nodename); - qemu_fdt_setprop_cell(fdt, core_nodename, "cpu", intc_phandle); - g_free(core_nodename); - g_free(cpu_nodename); + addr =3D memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, sock= et); + size =3D riscv_socket_mem_size(mc, socket); + mem_name =3D g_strdup_printf("/memory@%lx", (long)addr); + qemu_fdt_add_subnode(fdt, mem_name); + qemu_fdt_setprop_cells(fdt, mem_name, "reg", + addr >> 32, addr, size >> 32, size); + qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); + riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); + g_free(mem_name); + + clint_addr =3D memmap[VIRT_CLINT].base + + (memmap[VIRT_CLINT].size * socket); + clint_name =3D g_strdup_printf("/soc/clint@%lx", clint_addr); + qemu_fdt_add_subnode(fdt, clint_name); + qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clin= t0"); + qemu_fdt_setprop_cells(fdt, clint_name, "reg", + 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); + qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", + clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); + riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); + g_free(clint_name); + + plic_phandle[socket] =3D phandle++; + plic_addr =3D memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * s= ocket); + plic_name =3D g_strdup_printf("/soc/plic@%lx", plic_addr); + qemu_fdt_add_subnode(fdt, plic_name); + qemu_fdt_setprop_cell(fdt, plic_name, + "#address-cells", FDT_PLIC_ADDR_CELLS); + qemu_fdt_setprop_cell(fdt, plic_name, + "#interrupt-cells", FDT_PLIC_INT_CELLS); + qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0= "); + qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(fdt, plic_name, "interrupts-extended", + plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); + qemu_fdt_setprop_cells(fdt, plic_name, "reg", + 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); + qemu_fdt_setprop_cell(fdt, plic_name, "riscv,ndev", VIRTIO_NDEV); + riscv_socket_fdt_write_id(mc, fdt, plic_name, socket); + qemu_fdt_setprop_cell(fdt, plic_name, "phandle", plic_phandle[sock= et]); + g_free(plic_name); + + g_free(clint_cells); + g_free(plic_cells); + g_free(clust_name); } =20 - cells =3D g_new0(uint32_t, s->soc.num_harts * 4); - for (cpu =3D 0; cpu < s->soc.num_harts; cpu++) { - nodename =3D - g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); - uint32_t intc_phandle =3D qemu_fdt_get_phandle(fdt, nodename); - cells[cpu * 4 + 0] =3D cpu_to_be32(intc_phandle); - cells[cpu * 4 + 1] =3D cpu_to_be32(IRQ_M_SOFT); - cells[cpu * 4 + 2] =3D cpu_to_be32(intc_phandle); - cells[cpu * 4 + 3] =3D cpu_to_be32(IRQ_M_TIMER); - g_free(nodename); - } - nodename =3D g_strdup_printf("/soc/clint@%lx", - (long)memmap[VIRT_CLINT].base); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); - qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[VIRT_CLINT].base, - 0x0, memmap[VIRT_CLINT].size); - qemu_fdt_setprop(fdt, nodename, "interrupts-extended", - cells, s->soc.num_harts * sizeof(uint32_t) * 4); - g_free(cells); - g_free(nodename); - - plic_phandle =3D phandle++; - cells =3D g_new0(uint32_t, s->soc.num_harts * 4); - for (cpu =3D 0; cpu < s->soc.num_harts; cpu++) { - nodename =3D - g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); - uint32_t intc_phandle =3D qemu_fdt_get_phandle(fdt, nodename); - cells[cpu * 4 + 0] =3D cpu_to_be32(intc_phandle); - cells[cpu * 4 + 1] =3D cpu_to_be32(IRQ_M_EXT); - cells[cpu * 4 + 2] =3D cpu_to_be32(intc_phandle); - cells[cpu * 4 + 3] =3D cpu_to_be32(IRQ_S_EXT); - g_free(nodename); + for (socket =3D 0; socket < riscv_socket_count(mc); socket++) { + if (socket =3D=3D 0) { + plic_mmio_phandle =3D plic_phandle[socket]; + plic_virtio_phandle =3D plic_phandle[socket]; + plic_pcie_phandle =3D plic_phandle[socket]; + } + if (socket =3D=3D 1) { + plic_virtio_phandle =3D plic_phandle[socket]; + plic_pcie_phandle =3D plic_phandle[socket]; + } + if (socket =3D=3D 2) { + plic_pcie_phandle =3D plic_phandle[socket]; + } } - nodename =3D g_strdup_printf("/soc/interrupt-controller@%lx", - (long)memmap[VIRT_PLIC].base); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", - FDT_PLIC_ADDR_CELLS); - qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", - FDT_PLIC_INT_CELLS); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); - qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(fdt, nodename, "interrupts-extended", - cells, s->soc.num_harts * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[VIRT_PLIC].base, - 0x0, memmap[VIRT_PLIC].size); - qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV); - qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); - plic_phandle =3D qemu_fdt_get_phandle(fdt, nodename); - g_free(cells); - g_free(nodename); + + riscv_socket_fdt_write_distance_matrix(mc, fdt); =20 for (i =3D 0; i < VIRTIO_COUNT; i++) { - nodename =3D g_strdup_printf("/virtio_mmio@%lx", + name =3D g_strdup_printf("/soc/virtio_mmio@%lx", (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size= )); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio"= ); - qemu_fdt_setprop_cells(fdt, nodename, "reg", + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio"); + qemu_fdt_setprop_cells(fdt, name, "reg", 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 0x0, memmap[VIRT_VIRTIO].size); - qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phan= dle); - qemu_fdt_setprop_cell(fdt, nodename, "interrupts", VIRTIO_IRQ + i); - g_free(nodename); + qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", + plic_virtio_phandle); + qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i); + g_free(name); } =20 - nodename =3D g_strdup_printf("/soc/pci@%lx", + name =3D g_strdup_printf("/soc/pci@%lx", (long) memmap[VIRT_PCIE_ECAM].base); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", - FDT_PCI_ADDR_CELLS); - qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", - FDT_PCI_INT_CELLS); - qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0x2); - qemu_fdt_setprop_string(fdt, nodename, "compatible", - "pci-host-ecam-generic"); - qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci"); - qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0); - qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0, - memmap[VIRT_PCIE_ECAM].size / - PCIE_MMCFG_SIZE_MIN - 1); - qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0); - qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM]= .base, - 0, memmap[VIRT_PCIE_ECAM].size); - qemu_fdt_setprop_sized_cells(fdt, nodename, "ranges", + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); + qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS= ); + qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2); + qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generi= c"); + qemu_fdt_setprop_string(fdt, name, "device_type", "pci"); + qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0); + qemu_fdt_setprop_cells(fdt, name, "bus-range", 0, + memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); + qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0); + qemu_fdt_setprop_cells(fdt, name, "reg", 0, + memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); + qemu_fdt_setprop_sized_cells(fdt, name, "ranges", 1, FDT_PCI_RANGE_IOPORT, 2, 0, 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 1, FDT_PCI_RANGE_MMIO, 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size); - create_pcie_irq_map(fdt, nodename, plic_phandle); - g_free(nodename); + create_pcie_irq_map(fdt, name, plic_pcie_phandle); + g_free(name); =20 test_phandle =3D phandle++; - nodename =3D g_strdup_printf("/test@%lx", + name =3D g_strdup_printf("/soc/test@%lx", (long)memmap[VIRT_TEST].base); - qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_add_subnode(fdt, name); { const char compat[] =3D "sifive,test1\0sifive,test0\0syscon"; - qemu_fdt_setprop(fdt, nodename, "compatible", compat, sizeof(compa= t)); + qemu_fdt_setprop(fdt, name, "compatible", compat, sizeof(compat)); } - qemu_fdt_setprop_cells(fdt, nodename, "reg", + qemu_fdt_setprop_cells(fdt, name, "reg", 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); - qemu_fdt_setprop_cell(fdt, nodename, "phandle", test_phandle); - test_phandle =3D qemu_fdt_get_phandle(fdt, nodename); - g_free(nodename); - - nodename =3D g_strdup_printf("/reboot"); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-reboot"); - qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_phandle); - qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0); - qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_RESET); - g_free(nodename); - - nodename =3D g_strdup_printf("/poweroff"); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-poweroff"= ); - qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_phandle); - qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0); - qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_PASS); - g_free(nodename); - - nodename =3D g_strdup_printf("/uart@%lx", - (long)memmap[VIRT_UART0].base); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a"); - qemu_fdt_setprop_cells(fdt, nodename, "reg", + qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle); + test_phandle =3D qemu_fdt_get_phandle(fdt, name); + g_free(name); + + name =3D g_strdup_printf("/soc/reboot"); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot"); + qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); + qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); + qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET); + g_free(name); + + name =3D g_strdup_printf("/soc/poweroff"); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff"); + qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); + qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); + qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS); + g_free(name); + + name =3D g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].bas= e); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a"); + qemu_fdt_setprop_cells(fdt, name, "reg", 0x0, memmap[VIRT_UART0].base, 0x0, memmap[VIRT_UART0].size); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400); - qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); - qemu_fdt_setprop_cell(fdt, nodename, "interrupts", UART0_IRQ); + qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400); + qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle= ); + qemu_fdt_setprop_cell(fdt, name, "interrupts", UART0_IRQ); =20 qemu_fdt_add_subnode(fdt, "/chosen"); - qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); + qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name); if (cmdline) { qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); } - g_free(nodename); - - nodename =3D g_strdup_printf("/rtc@%lx", - (long)memmap[VIRT_RTC].base); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", - "google,goldfish-rtc"); - qemu_fdt_setprop_cells(fdt, nodename, "reg", + g_free(name); + + name =3D g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc"= ); + qemu_fdt_setprop_cells(fdt, name, "reg", 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); - qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); - qemu_fdt_setprop_cell(fdt, nodename, "interrupts", RTC_IRQ); - g_free(nodename); - - nodename =3D g_strdup_printf("/flash@%" PRIx64, flashbase); - qemu_fdt_add_subnode(s->fdt, nodename); - qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "cfi-flash"); - qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg", + qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle= ); + qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ); + g_free(name); + + name =3D g_strdup_printf("/soc/flash@%" PRIx64, flashbase); + qemu_fdt_add_subnode(s->fdt, name); + qemu_fdt_setprop_string(s->fdt, name, "compatible", "cfi-flash"); + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 2, flashbase, 2, flashsize, 2, flashbase + flashsize, 2, flashsize); - qemu_fdt_setprop_cell(s->fdt, nodename, "bank-width", 4); - g_free(nodename); + qemu_fdt_setprop_cell(s->fdt, name, "bank-width", 4); + g_free(name); } =20 - static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, hwaddr ecam_base, hwaddr ecam_si= ze, hwaddr mmio_base, hwaddr mmio_si= ze, @@ -475,22 +490,101 @@ static void virt_machine_init(MachineState *machine) MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); - char *plic_hart_config; + char *plic_hart_config, *soc_name; size_t plic_hart_config_len; target_ulong start_addr =3D memmap[VIRT_DRAM].base; uint32_t fdt_load_addr; uint64_t kernel_entry; - int i; - unsigned int smp_cpus =3D machine->smp.cpus; + DeviceState *mmio_plic, *virtio_plic, *pcie_plic; + int i, j, base_hartid, hart_count; =20 - /* Initialize SOC */ - object_initialize_child(OBJECT(machine), "soc", &s->soc, - TYPE_RISCV_HART_ARRAY); - object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, - &error_abort); - object_property_set_int(OBJECT(&s->soc), "num-harts", smp_cpus, - &error_abort); - sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort); + /* Check socket count limit */ + if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { + error_report("number of sockets/nodes should be less than %d", + VIRT_SOCKETS_MAX); + exit(1); + } + + /* Initialize sockets */ + mmio_plic =3D virtio_plic =3D pcie_plic =3D NULL; + for (i =3D 0; i < riscv_socket_count(machine); i++) { + if (!riscv_socket_check_hartids(machine, i)) { + error_report("discontinuous hartids in socket%d", i); + exit(1); + } + + base_hartid =3D riscv_socket_first_hartid(machine, i); + if (base_hartid < 0) { + error_report("can't find hartid base for socket%d", i); + exit(1); + } + + hart_count =3D riscv_socket_hart_count(machine, i); + if (hart_count < 0) { + error_report("can't find hart count for socket%d", i); + exit(1); + } + + soc_name =3D g_strdup_printf("soc%d", i); + object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], + TYPE_RISCV_HART_ARRAY); + g_free(soc_name); + object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", + machine->cpu_type, &error_abort); + object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", + base_hartid, &error_abort); + object_property_set_int(OBJECT(&s->soc[i]), "num-harts", + hart_count, &error_abort); + sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); + + /* Per-socket CLINT */ + sifive_clint_create( + memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, + memmap[VIRT_CLINT].size, base_hartid, hart_count, + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true); + + /* Per-socket PLIC hart topology configuration string */ + plic_hart_config_len =3D + (strlen(VIRT_PLIC_HART_CONFIG) + 1) * hart_count; + plic_hart_config =3D g_malloc0(plic_hart_config_len); + for (j =3D 0; j < hart_count; j++) { + if (j !=3D 0) { + strncat(plic_hart_config, ",", plic_hart_config_len); + } + strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, + plic_hart_config_len); + plic_hart_config_len -=3D (strlen(VIRT_PLIC_HART_CONFIG) + 1); + } + + /* Per-socket PLIC */ + s->plic[i] =3D sifive_plic_create( + memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size, + plic_hart_config, base_hartid, + VIRT_PLIC_NUM_SOURCES, + VIRT_PLIC_NUM_PRIORITIES, + VIRT_PLIC_PRIORITY_BASE, + VIRT_PLIC_PENDING_BASE, + VIRT_PLIC_ENABLE_BASE, + VIRT_PLIC_ENABLE_STRIDE, + VIRT_PLIC_CONTEXT_BASE, + VIRT_PLIC_CONTEXT_STRIDE, + memmap[VIRT_PLIC].size); + g_free(plic_hart_config); + + /* Try to use different PLIC instance based device type */ + if (i =3D=3D 0) { + mmio_plic =3D s->plic[i]; + virtio_plic =3D s->plic[i]; + pcie_plic =3D s->plic[i]; + } + if (i =3D=3D 1) { + virtio_plic =3D s->plic[i]; + pcie_plic =3D s->plic[i]; + } + if (i =3D=3D 2) { + pcie_plic =3D s->plic[i]; + } + } =20 /* register system main memory (actual RAM) */ memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram", @@ -547,38 +641,14 @@ static void virt_machine_init(MachineState *machine) virt_memmap[VIRT_MROM].size, kernel_entry, fdt_load_addr, s->fdt); =20 - /* create PLIC hart topology configuration string */ - plic_hart_config_len =3D (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpu= s; - plic_hart_config =3D g_malloc0(plic_hart_config_len); - for (i =3D 0; i < smp_cpus; i++) { - if (i !=3D 0) { - strncat(plic_hart_config, ",", plic_hart_config_len); - } - strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_= len); - plic_hart_config_len -=3D (strlen(VIRT_PLIC_HART_CONFIG) + 1); - } - - /* MMIO */ - s->plic =3D sifive_plic_create(memmap[VIRT_PLIC].base, - plic_hart_config, 0, - VIRT_PLIC_NUM_SOURCES, - VIRT_PLIC_NUM_PRIORITIES, - VIRT_PLIC_PRIORITY_BASE, - VIRT_PLIC_PENDING_BASE, - VIRT_PLIC_ENABLE_BASE, - VIRT_PLIC_ENABLE_STRIDE, - VIRT_PLIC_CONTEXT_BASE, - VIRT_PLIC_CONTEXT_STRIDE, - memmap[VIRT_PLIC].size); - sifive_clint_create(memmap[VIRT_CLINT].base, - memmap[VIRT_CLINT].size, 0, smp_cpus, - SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true); + /* SiFive Test MMIO device */ sifive_test_create(memmap[VIRT_TEST].base); =20 + /* VirtIO MMIO devices */ for (i =3D 0; i < VIRTIO_COUNT; i++) { sysbus_create_simple("virtio-mmio", memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, - qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i)); + qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i)); } =20 gpex_pcie_init(system_memory, @@ -587,14 +657,14 @@ static void virt_machine_init(MachineState *machine) memmap[VIRT_PCIE_MMIO].base, memmap[VIRT_PCIE_MMIO].size, memmap[VIRT_PCIE_PIO].base, - DEVICE(s->plic), true); + DEVICE(pcie_plic), true); =20 serial_mm_init(system_memory, memmap[VIRT_UART0].base, - 0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193, + 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193, serial_hd(0), DEVICE_LITTLE_ENDIAN); =20 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, - qdev_get_gpio_in(DEVICE(s->plic), RTC_IRQ)); + qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ)); =20 virt_flash_create(s); =20 @@ -604,8 +674,6 @@ static void virt_machine_init(MachineState *machine) drive_get(IF_PFLASH, 0, i)); } virt_flash_map(s, system_memory); - - g_free(plic_hart_config); } =20 static void virt_machine_instance_init(Object *obj) @@ -618,9 +686,13 @@ static void virt_machine_class_init(ObjectClass *oc, v= oid *data) =20 mc->desc =3D "RISC-V VirtIO board"; mc->init =3D virt_machine_init; - mc->max_cpus =3D 8; + mc->max_cpus =3D VIRT_CPUS_MAX; mc->default_cpu_type =3D VIRT_CPU; mc->pci_allow_0_address =3D true; + mc->possible_cpu_arch_ids =3D riscv_numa_possible_cpu_arch_ids; + mc->cpu_index_to_instance_props =3D riscv_numa_cpu_index_to_props; + mc->get_default_cpu_node_id =3D riscv_numa_get_default_cpu_node_id; + mc->numa_mem_supported =3D true; } =20 static const TypeInfo virt_machine_typeinfo =3D { --=20 2.28.0 From nobody Sat May 18 21:26:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=49978a6e9=alistair.francis@wdc.com; helo=esa3.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/25 14:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Message-id: 08cdefb171b1bdb0c9e3151c509aaadefc3dcd3e.1597259519.git.alistai= r.francis@wdc.com Message-Id: <08cdefb171b1bdb0c9e3151c509aaadefc3dcd3e.1597259519.git.alista= ir.francis@wdc.com> reviewed-by tags, which seems a shame for a fairly significant --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 18 ++++++++++++++++++ 3 files changed, 21 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a804a5d0ba..383808bf88 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -321,6 +321,8 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); +bool riscv_cpu_two_stage_lookup(CPURISCVState *env); +void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8117e8b5a7..ba0a5b50ff 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -467,6 +467,7 @@ * page table fault. */ #define FORCE_HS_EXCEP 2 +#define HS_TWO_STAGE 4 =20 /* RV32 satp CSR field masks */ #define SATP32_MODE 0x80000000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index fd1d373b6f..e5e0d80c32 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -220,6 +220,24 @@ void riscv_cpu_set_force_hs_excep(CPURISCVState *env, = bool enable) env->virt =3D set_field(env->virt, FORCE_HS_EXCEP, enable); } =20 +bool riscv_cpu_two_stage_lookup(CPURISCVState *env) +{ + if (!riscv_has_ext(env, RVH)) { + return false; + } + + return get_field(env->virt, HS_TWO_STAGE); +} + +void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable) +{ + if (!riscv_has_ext(env, RVH)) { + return; + } + + env->virt =3D set_field(env->virt, HS_TWO_STAGE, enable); +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) { CPURISCVState *env =3D &cpu->env; --=20 2.28.0 From nobody Sat May 18 21:26:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1598382214; cv=none; d=zohomail.com; s=zohoarc; b=dIZOdwd8+qQLlVytnNYgzkREiftduX7yjLVKxLu/1xL3vP2xn8T3v+J0CTBCLPbKAo3aXWwg19vfT8Rtf9ijktd+9AMoNOXM6aEQ0L4c4seRopA29BBJmHnrG12DN/Ysl1aVMaRL0YgrbbqoCyl/Mgt1/gaU3Je693LPTQ81ymI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598382214; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=49978a6e9=alistair.francis@wdc.com; helo=esa3.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/25 14:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Message-id: 477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistai= r.francis@wdc.com Message-Id: <477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alista= ir.francis@wdc.com> reviewed-by tags, which seems a shame for a fairly significant --- target/riscv/cpu_bits.h | 1 + target/riscv/helper.h | 3 + target/riscv/insn32-64.decode | 5 + target/riscv/insn32.decode | 11 + target/riscv/op_helper.c | 114 ++++++++ target/riscv/insn_trans/trans_rvh.c.inc | 340 ++++++++++++++++++++++++ 6 files changed, 474 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index ba0a5b50ff..7abae4267f 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -443,6 +443,7 @@ #define HSTATUS_SP2V 0x00000200 #define HSTATUS_VTVM 0x00100000 #define HSTATUS_VTSR 0x00400000 +#define HSTATUS_HU 0x00000200 =20 #define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL diff --git a/target/riscv/helper.h b/target/riscv/helper.h index acc298219d..c8029d83f9 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -80,6 +80,9 @@ DEF_HELPER_1(tlb_flush, void, env) /* Hypervisor functions */ #ifndef CONFIG_USER_ONLY DEF_HELPER_1(hyp_tlb_flush, void, env) +DEF_HELPER_4(hyp_load, tl, env, tl, tl, tl) +DEF_HELPER_5(hyp_store, void, env, tl, tl, tl, tl) +DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl) #endif =20 /* Vector functions */ diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 86153d93fa..8157dee8b7 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -81,3 +81,8 @@ fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2 fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2 + +# *** RV32H Base Instruction Set *** +hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2 +hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2 +hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index bdd8563067..84080dd18c 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -78,6 +78,7 @@ @r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=3D0 %rs2 %rs1 = %rd @r_wdvm ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd @r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd +@r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 =20 @hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1 @hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1 @@ -223,6 +224,16 @@ fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_= rm fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm =20 # *** RV32H Base Instruction Set *** +hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2 +hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2 +hlv_h 0110010 00000 ..... 100 ..... 1110011 @r2 +hlv_hu 0110010 00001 ..... 100 ..... 1110011 @r2 +hlvx_hu 0110010 00011 ..... 100 ..... 1110011 @r2 +hlv_w 0110100 00000 ..... 100 ..... 1110011 @r2 +hlvx_wu 0110100 00011 ..... 100 ..... 1110011 @r2 +hsv_b 0110001 ..... ..... 100 00000 1110011 @r2_s +hsv_h 0110011 ..... ..... 100 00000 1110011 @r2_s +hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma =20 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 7cccd42a1e..3d306c343c 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -207,4 +207,118 @@ void helper_hyp_tlb_flush(CPURISCVState *env) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } =20 +target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address, + target_ulong attrs, target_ulong memop) +{ + if (env->priv =3D=3D PRV_M || + (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + target_ulong pte; + + riscv_cpu_set_two_stage_lookup(env, true); + + switch (memop) { + case MO_SB: + pte =3D cpu_ldsb_data_ra(env, address, GETPC()); + break; + case MO_UB: + pte =3D cpu_ldub_data_ra(env, address, GETPC()); + break; + case MO_TESW: + pte =3D cpu_ldsw_data_ra(env, address, GETPC()); + break; + case MO_TEUW: + pte =3D cpu_lduw_data_ra(env, address, GETPC()); + break; + case MO_TESL: + pte =3D cpu_ldl_data_ra(env, address, GETPC()); + break; + case MO_TEUL: + pte =3D cpu_ldl_data_ra(env, address, GETPC()); + break; + case MO_TEQ: + pte =3D cpu_ldq_data_ra(env, address, GETPC()); + break; + default: + g_assert_not_reached(); + } + + riscv_cpu_set_two_stage_lookup(env, false); + + return pte; + } + + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + return 0; +} + +void helper_hyp_store(CPURISCVState *env, target_ulong address, + target_ulong val, target_ulong attrs, target_ulong m= emop) +{ + if (env->priv =3D=3D PRV_M || + (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + riscv_cpu_set_two_stage_lookup(env, true); + + switch (memop) { + case MO_SB: + case MO_UB: + cpu_stb_data_ra(env, address, val, GETPC()); + break; + case MO_TESW: + case MO_TEUW: + cpu_stw_data_ra(env, address, val, GETPC()); + break; + case MO_TESL: + case MO_TEUL: + cpu_stl_data_ra(env, address, val, GETPC()); + break; + case MO_TEQ: + cpu_stq_data_ra(env, address, val, GETPC()); + break; + default: + g_assert_not_reached(); + } + + riscv_cpu_set_two_stage_lookup(env, false); + + return; + } + + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); +} + +target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address, + target_ulong attrs, target_ulong memop) +{ + if (env->priv =3D=3D PRV_M || + (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + target_ulong pte; + + riscv_cpu_set_two_stage_lookup(env, true); + + switch (memop) { + case MO_TEUL: + pte =3D cpu_ldub_data_ra(env, address, GETPC()); + break; + case MO_TEUW: + pte =3D cpu_lduw_data_ra(env, address, GETPC()); + break; + default: + g_assert_not_reached(); + } + + riscv_cpu_set_two_stage_lookup(env, false); + + return pte; + } + + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + return 0; +} + #endif /* !CONFIG_USER_ONLY */ diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_tr= ans/trans_rvh.c.inc index 263b652d90..db650ae62a 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -16,6 +16,346 @@ * this program. If not, see . */ =20 +static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_SB); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TESW); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TESL); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_UB); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TEUW); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv dat =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + gen_get_gpr(dat, a->rs2); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_SB); + + gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + + tcg_temp_free(t0); + tcg_temp_free(dat); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv dat =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + gen_get_gpr(dat, a->rs2); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TESW); + + gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + + tcg_temp_free(t0); + tcg_temp_free(dat); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv dat =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + gen_get_gpr(dat, a->rs2); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TESL); + + gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + + tcg_temp_free(t0); + tcg_temp_free(dat); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +#ifdef TARGET_RISCV64 +static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TEUL); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TEQ); + + gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv dat =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + gen_get_gpr(dat, a->rs2); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TEQ); + + gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + + tcg_temp_free(t0); + tcg_temp_free(dat); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} +#endif + +static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TEUW); + + gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + +static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx_wu *a) +{ + REQUIRE_EXT(ctx, RVH); +#ifndef CONFIG_USER_ONLY + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + TCGv mem_idx =3D tcg_temp_new(); + TCGv memop =3D tcg_temp_new(); + + gen_get_gpr(t0, a->rs1); + tcg_gen_movi_tl(mem_idx, ctx->mem_idx); + tcg_gen_movi_tl(memop, MO_TEUL); + + gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop); + gen_set_gpr(a->rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(mem_idx); + tcg_temp_free(memop); + return true; +#else + return false; +#endif +} + static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) { REQUIRE_EXT(ctx, RVH); --=20 2.28.0 From nobody Sat May 18 21:26:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1598382164; cv=none; d=zohomail.com; s=zohoarc; b=f4HvfokvMI4RUvFyKF5APHtl1htAfbYdeJZ8s/1oMXKXcO4HCYOgGyvLOUq/hT5I4LjeKxt9pBr/rpex4DKvxuKBoHFG7f6Ig6B5TC6M60akmy0Z16rI6bDtzHNDXVL/g0Q0zblLJKMxqNAa8e9+VHksHOHdoho1Gz17iFPl488= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=49978a6e9=alistair.francis@wdc.com; helo=esa3.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/25 14:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Message-id: 024ad8a594fb2feaf0950fbfad1508cfa82ce7f0.1597259519.git.alistai= r.francis@wdc.com Message-Id: <024ad8a594fb2feaf0950fbfad1508cfa82ce7f0.1597259519.git.alista= ir.francis@wdc.com> reviewed-by tags, which seems a shame for a fairly significant --- target/riscv/cpu_helper.c | 60 ++++++++++++++++----------------------- 1 file changed, 25 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e5e0d80c32..5efb3b16e0 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -340,22 +340,13 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, * was called. Background registers will be used if the guest has * forced a two stage translation to be on (in HS or M mode). */ + if (riscv_cpu_two_stage_lookup(env) && access_type !=3D MMU_INST_FETCH= ) { + use_background =3D true; + } + if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH) { if (get_field(env->mstatus, MSTATUS_MPRV)) { mode =3D get_field(env->mstatus, MSTATUS_MPP); - - if (riscv_has_ext(env, RVH) && - MSTATUS_MPV_ISSET(env)) { - use_background =3D true; - } - } - } - - if (mode =3D=3D PRV_S && access_type !=3D MMU_INST_FETCH && - riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) { - if (get_field(env->hstatus, HSTATUS_SPRV)) { - mode =3D get_field(env->mstatus, SSTATUS_SPP); - use_background =3D true; } } =20 @@ -608,7 +599,8 @@ static void raise_mmu_exception(CPURISCVState *env, tar= get_ulong address, } break; case MMU_DATA_LOAD: - if (riscv_cpu_virt_enabled(env) && !first_stage) { + if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env= )) && + !first_stage) { cs->exception_index =3D RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; } else { cs->exception_index =3D page_fault_exceptions ? @@ -616,7 +608,8 @@ static void raise_mmu_exception(CPURISCVState *env, tar= get_ulong address, } break; case MMU_DATA_STORE: - if (riscv_cpu_virt_enabled(env) && !first_stage) { + if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env= )) && + !first_stage) { cs->exception_index =3D RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAUL= T; } else { cs->exception_index =3D page_fault_exceptions ? @@ -706,8 +699,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, hwaddr pa =3D 0; int prot, prot2; bool pmp_violation =3D false; - bool m_mode_two_stage =3D false; - bool hs_mode_two_stage =3D false; bool first_stage_error =3D true; int ret =3D TRANSLATE_FAIL; int mode =3D mmu_idx; @@ -718,30 +709,21 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, address, access_type, mmu_idx); =20 - /* - * Determine if we are in M mode and MPRV is set or in HS mode and SPR= V is - * set and we want to access a virtulisation address. - */ - if (riscv_has_ext(env, RVH)) { - m_mode_two_stage =3D env->priv =3D=3D PRV_M && - access_type !=3D MMU_INST_FETCH && - get_field(env->mstatus, MSTATUS_MPRV) && - MSTATUS_MPV_ISSET(env); - - hs_mode_two_stage =3D env->priv =3D=3D PRV_S && - !riscv_cpu_virt_enabled(env) && - access_type !=3D MMU_INST_FETCH && - get_field(env->hstatus, HSTATUS_SPRV) && - get_field(env->hstatus, HSTATUS_SPV); - } - if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH) { if (get_field(env->mstatus, MSTATUS_MPRV)) { mode =3D get_field(env->mstatus, MSTATUS_MPP); } } =20 - if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_sta= ge) { + if (riscv_has_ext(env, RVH) && env->priv =3D=3D PRV_M && + access_type !=3D MMU_INST_FETCH && + get_field(env->mstatus, MSTATUS_MPRV) && + MSTATUS_MPV_ISSET(env)) { + riscv_cpu_set_two_stage_lookup(env, true); + } + + if (riscv_cpu_virt_enabled(env) || + (riscv_cpu_two_stage_lookup(env) && access_type !=3D MMU_INST_FETC= H)) { /* Two stage lookup */ ret =3D get_physical_address(env, &pa, &prot, address, access_type, mmu_idx, true, true); @@ -793,6 +775,14 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, __func__, address, ret, pa, prot); } =20 + /* We did the two stage lookup based on MPRV, unset the lookup */ + if (riscv_has_ext(env, RVH) && env->priv =3D=3D PRV_M && + access_type !=3D MMU_INST_FETCH && + get_field(env->mstatus, MSTATUS_MPRV) && + MSTATUS_MPV_ISSET(env)) { + riscv_cpu_set_two_stage_lookup(env, false); + } + if (riscv_feature(env, RISCV_FEATURE_PMP) && (ret =3D=3D TRANSLATE_SUCCESS) && !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) { --=20 2.28.0 From nobody Sat May 18 21:26:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1598382266; cv=none; d=zohomail.com; s=zohoarc; b=cZ26xQW9u00BRqtlz6XcpnYCmXCrDN5ebccswQn4wr+VfOtDjq6rRB2SjUIJDX7nSkBUqnmsX+Eiila3RDBB2/xGtZyVoNr4JvcutuuHhIHetCvwqENif8cCLLCzQgJPV36JORquIn70efmSGtTIoexEYMBeqgGhZwTLE7d7BbM= ARC-Message-Signature: i=1; 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charset="utf-8" Signed-off-by: Alistair Francis Message-id: ca5359fec6b2aff851eef3b3bc4b53cb5d4ad194.1597259519.git.alistai= r.francis@wdc.com Message-Id: reviewed-by tags, which seems a shame for a fairly significant --- target/riscv/csr.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6a96a01b1c..0f035d33b1 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -922,7 +922,6 @@ static int read_htinst(CPURISCVState *env, int csrno, t= arget_ulong *val) =20 static int write_htinst(CPURISCVState *env, int csrno, target_ulong val) { - env->htinst =3D val; return 0; } =20 --=20 2.28.0 From nobody Sat May 18 21:26:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; 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d="scan'208";a="150145292" IronPort-SDR: pXaGjbQStVQseaXVhT6nG4U1xQgQaEojuGJJ2DQVWVkoNznBxm06RgUsVoT3m5LCUriEcquyGJ uyHUpqjpzeVQ== IronPort-SDR: 7DSZie4UTo7+i2r2lVqa9y1ajAaN+4dMFCh4W6EhO8zJgiBkd0ZM8UfOBiPT2HFX1yF3mEHS9t gF3jJZSahsnA== WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org Subject: [PULL 10/18] target/riscv: Convert MSTATUS MTL to GVA Date: Tue, 25 Aug 2020 11:48:28 -0700 Message-Id: <20200825184836.1282371-11-alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200825184836.1282371-1-alistair.francis@wdc.com> References: <20200825184836.1282371-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=49978a6e9=alistair.francis@wdc.com; helo=esa3.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/25 14:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Message-id: 9308432988946de550a68524ed76e4b8683f10e2.1597259519.git.alistai= r.francis@wdc.com Message-Id: <9308432988946de550a68524ed76e4b8683f10e2.1597259519.git.alista= ir.francis@wdc.com> reviewed-by tags, which seems a shame for a fairly significant --- target/riscv/cpu_bits.h | 5 +++-- target/riscv/cpu_helper.c | 24 ++++++++++++++++++++---- target/riscv/csr.c | 6 +++--- 3 files changed, 26 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7abae4267f..43617e7c1f 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -379,10 +379,10 @@ #define MSTATUS_TW 0x20000000 /* since: priv-1.10 */ #define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */ #if defined(TARGET_RISCV64) -#define MSTATUS_MTL 0x4000000000ULL +#define MSTATUS_GVA 0x4000000000ULL #define MSTATUS_MPV 0x8000000000ULL #elif defined(TARGET_RISCV32) -#define MSTATUS_MTL 0x00000040 +#define MSTATUS_GVA 0x00000040 #define MSTATUS_MPV 0x00000080 #endif =20 @@ -444,6 +444,7 @@ #define HSTATUS_VTVM 0x00100000 #define HSTATUS_VTSR 0x00400000 #define HSTATUS_HU 0x00000200 +#define HSTATUS_GVA 0x00000040 =20 #define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 5efb3b16e0..0b4ad4bf46 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -901,6 +901,19 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (riscv_has_ext(env, RVH)) { target_ulong hdeleg =3D async ? env->hideleg : env->hedeleg; =20 + if ((riscv_cpu_virt_enabled(env) || + riscv_cpu_two_stage_lookup(env)) && tval) { + /* + * If we are writing a guest virtual address to stval, set + * this to 1. If we are trapping to VS we will set this to= 0 + * later. + */ + env->hstatus =3D set_field(env->hstatus, HSTATUS_GVA, 1); + } else { + /* For other HS-mode traps, we set this to 0. */ + env->hstatus =3D set_field(env->hstatus, HSTATUS_GVA, 0); + } + if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && !force_hs_execp) { /* @@ -911,6 +924,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) cause =3D=3D IRQ_VS_EXT) cause =3D cause - 1; /* Trap to VS mode */ + env->hstatus =3D set_field(env->hstatus, HSTATUS_GVA, 0); } else if (riscv_cpu_virt_enabled(env)) { /* Trap into HS mode, from virt */ riscv_cpu_swap_hypervisor_regs(env); @@ -959,13 +973,15 @@ void riscv_cpu_do_interrupt(CPUState *cs) #ifdef TARGET_RISCV32 env->mstatush =3D set_field(env->mstatush, MSTATUS_MPV, riscv_cpu_virt_enabled(env)); - env->mstatush =3D set_field(env->mstatush, MSTATUS_MTL, - riscv_cpu_force_hs_excep_enabled(en= v)); + if (riscv_cpu_virt_enabled(env) && tval) { + env->mstatush =3D set_field(env->mstatush, MSTATUS_GVA, 1); + } #else env->mstatus =3D set_field(env->mstatus, MSTATUS_MPV, riscv_cpu_virt_enabled(env)); - env->mstatus =3D set_field(env->mstatus, MSTATUS_MTL, - riscv_cpu_force_hs_excep_enabled(env= )); + if (riscv_cpu_virt_enabled(env) && tval) { + env->mstatus =3D set_field(env->mstatus, MSTATUS_GVA, 1); + } #endif =20 mtval2 =3D env->guest_phys_fault_addr; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0f035d33b1..f9ac21d687 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -403,10 +403,10 @@ static int write_mstatus(CPURISCVState *env, int csrn= o, target_ulong val) MSTATUS_TW; #if defined(TARGET_RISCV64) /* - * RV32: MPV and MTL are not in mstatus. The current plan is to + * RV32: MPV and GVA are not in mstatus. The current plan is to * add them to mstatush. For now, we just don't support it. */ - mask |=3D MSTATUS_MTL | MSTATUS_MPV; + mask |=3D MSTATUS_MPV | MSTATUS_GVA; #endif =20 mstatus =3D (mstatus & ~mask) | (val & mask); @@ -432,7 +432,7 @@ static int write_mstatush(CPURISCVState *env, int csrno= , target_ulong val) tlb_flush(env_cpu(env)); } =20 - val &=3D MSTATUS_MPV | MSTATUS_MTL; + val &=3D MSTATUS_MPV | MSTATUS_GVA; =20 env->mstatush =3D val; =20 --=20 2.28.0 From nobody Sat May 18 21:26:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1598382417; cv=none; d=zohomail.com; s=zohoarc; b=CWqwaiQ+c+TzkbesHbmaR3fUlb9SFM7CtNn9g3cB7V8yh2CTjhXMB1+boIKudCL7/M8108+zQNtGK5AiVm/3++/9ixZhArDwkXsE5Pdk1EmaEcJY5KbNussmdKvE8iejhkid8BQ3WaLHj6orlvwoPL/pt6Hw5XPwm83IcwLo+vQ= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=49978a6e9=alistair.francis@wdc.com; helo=esa3.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/25 14:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Message-id: 85b7fdba8abd87adb83275cdc3043ce35a1ed5c3.1597259519.git.alistai= r.francis@wdc.com Message-Id: <85b7fdba8abd87adb83275cdc3043ce35a1ed5c3.1597259519.git.alista= ir.francis@wdc.com> reviewed-by tags, which seems a shame for a fairly significant --- target/riscv/cpu_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 0b4ad4bf46..661e790fdc 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -916,14 +916,15 @@ void riscv_cpu_do_interrupt(CPUState *cs) =20 if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && !force_hs_execp) { + /* Trap to VS mode */ /* * See if we need to adjust cause. Yes if its VS mode inte= rrupt * no if hypervisor has delegated one of hs mode's interru= pt */ if (cause =3D=3D IRQ_VS_TIMER || cause =3D=3D IRQ_VS_SOFT = || - cause =3D=3D IRQ_VS_EXT) + cause =3D=3D IRQ_VS_EXT) { cause =3D cause - 1; - /* Trap to VS mode */ + } env->hstatus =3D set_field(env->hstatus, HSTATUS_GVA, 0); } else if (riscv_cpu_virt_enabled(env)) { /* Trap into HS mode, from virt */ --=20 2.28.0 From nobody Sat May 18 21:26:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1598382271; cv=none; d=zohomail.com; s=zohoarc; b=Gd7QnyfgM+n5DJwPeCxHyHFXRa23/BMl3TPyqey4fstiIHm6KiRCIzS5KxuVZGLZVdrnXTrxLAqxXTcGVlM1BBa3tiLn0Ps8GW282YunX8han1u0jAzc5RwBO7Ka5aq6f7G8KcHHTA5QiEbRZ8P6naNNA1l2SnJX+V3fVClSa2E= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=49978a6e9=alistair.francis@wdc.com; helo=esa3.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/25 14:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Message-id: e7e4e801234f2934306e734f65860f601a5745bd.1597259519.git.alistai= r.francis@wdc.com Message-Id: reviewed-by tags, which seems a shame for a fairly significant --- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 16 ++++++---------- target/riscv/op_helper.c | 8 ++------ target/riscv/translate.c | 10 ---------- 4 files changed, 9 insertions(+), 26 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 43617e7c1f..fb6a3e9092 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -445,6 +445,7 @@ #define HSTATUS_VTSR 0x00400000 #define HSTATUS_HU 0x00000200 #define HSTATUS_GVA 0x00000040 +#define HSTATUS_SPVP 0x00000100 =20 #define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 661e790fdc..dc7ae3e7b1 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -929,9 +929,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) } else if (riscv_cpu_virt_enabled(env)) { /* Trap into HS mode, from virt */ riscv_cpu_swap_hypervisor_regs(env); - env->hstatus =3D set_field(env->hstatus, HSTATUS_SP2V, - get_field(env->hstatus, HSTATUS_S= PV)); - env->hstatus =3D set_field(env->hstatus, HSTATUS_SP2P, + env->hstatus =3D set_field(env->hstatus, HSTATUS_SPVP, get_field(env->mstatus, SSTATUS_S= PP)); env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, riscv_cpu_virt_enabled(env)); @@ -942,13 +940,11 @@ void riscv_cpu_do_interrupt(CPUState *cs) riscv_cpu_set_force_hs_excep(env, 0); } else { /* Trap into HS mode */ - env->hstatus =3D set_field(env->hstatus, HSTATUS_SP2V, - get_field(env->hstatus, HSTATUS_S= PV)); - env->hstatus =3D set_field(env->hstatus, HSTATUS_SP2P, - get_field(env->mstatus, SSTATUS_S= PP)); - env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, - riscv_cpu_virt_enabled(env)); - + if (!riscv_cpu_two_stage_lookup(env)) { + env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, + riscv_cpu_virt_enabled(env)); + } + riscv_cpu_set_two_stage_lookup(env, false); htval =3D env->guest_phys_fault_addr; } } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 3d306c343c..4b64bfe7d2 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -97,12 +97,8 @@ target_ulong helper_sret(CPURISCVState *env, target_ulon= g cpu_pc_deb) prev_priv =3D get_field(mstatus, MSTATUS_SPP); prev_virt =3D get_field(hstatus, HSTATUS_SPV); =20 - hstatus =3D set_field(hstatus, HSTATUS_SPV, - get_field(hstatus, HSTATUS_SP2V)); - mstatus =3D set_field(mstatus, MSTATUS_SPP, - get_field(hstatus, HSTATUS_SP2P)); - hstatus =3D set_field(hstatus, HSTATUS_SP2V, 0); - hstatus =3D set_field(hstatus, HSTATUS_SP2P, 0); + hstatus =3D set_field(hstatus, HSTATUS_SPV, 0); + mstatus =3D set_field(mstatus, MSTATUS_SPP, 0); mstatus =3D set_field(mstatus, SSTATUS_SIE, get_field(mstatus, SSTATUS_SPIE)); mstatus =3D set_field(mstatus, SSTATUS_SPIE, 1); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3919f570f7..79dca2291b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -797,16 +797,6 @@ static void riscv_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) #if !defined(CONFIG_USER_ONLY) if (riscv_has_ext(env, RVH)) { ctx->virt_enabled =3D riscv_cpu_virt_enabled(env); - if (env->priv_ver =3D=3D PRV_M && - get_field(env->mstatus, MSTATUS_MPRV) && - MSTATUS_MPV_ISSET(env)) { - ctx->virt_enabled =3D true; - } else if (env->priv =3D=3D PRV_S && - !riscv_cpu_virt_enabled(env) && - get_field(env->hstatus, HSTATUS_SPRV) && - get_field(env->hstatus, HSTATUS_SPV)) { - ctx->virt_enabled =3D true; - } } else { ctx->virt_enabled =3D false; } --=20 2.28.0 From nobody Sat May 18 21:26:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1598382367; cv=none; d=zohomail.com; s=zohoarc; b=W6lESUOdTHrlJFTPuSsFNwPB8L9kj5AAFKxYxXEOyLYfBmYwXF144jBKdTmc9U9DI4xzAJhaCtwMU4BU4AoV2y2O8ICXPKz/da0P+6thtogWrLfVGh3H2Ye+LeoR6HrCQY1w6l/7uKlmXued04+g2K6RTr5GnLGCWzkp8PyfTz8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598382367; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Signed-off-by: Alistair Francis Message-id: 4f227b30cb1816795296c0994f1123fab143666a.1597259519.git.alistai= r.francis@wdc.com Message-Id: <4f227b30cb1816795296c0994f1123fab143666a.1597259519.git.alista= ir.francis@wdc.com> reviewed-by tags, which seems a shame for a fairly significant --- target/riscv/cpu_bits.h | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index fb6a3e9092..573d85da41 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -437,15 +437,17 @@ #endif =20 /* hstatus CSR bits */ -#define HSTATUS_SPRV 0x00000001 +#define HSTATUS_VSBE 0x00000020 +#define HSTATUS_GVA 0x00000040 #define HSTATUS_SPV 0x00000080 -#define HSTATUS_SP2P 0x00000100 -#define HSTATUS_SP2V 0x00000200 +#define HSTATUS_SPVP 0x00000100 +#define HSTATUS_HU 0x00000200 +#define HSTATUS_VGEIN 0x0003F000 #define HSTATUS_VTVM 0x00100000 #define HSTATUS_VTSR 0x00400000 -#define HSTATUS_HU 0x00000200 -#define HSTATUS_GVA 0x00000040 -#define HSTATUS_SPVP 0x00000100 +#if defined(TARGET_RISCV64) +#define HSTATUS_VSXL 0x300000000 +#endif =20 #define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL --=20 2.28.0 From nobody Sat May 18 21:26:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Signed-off-by: Alistair Francis Message-id: f3f4fd2ec22a07cc1d750e96895d6813f131de4d.1597259519.git.alistai= r.francis@wdc.com Message-Id: reviewed-by tags, which seems a shame for a fairly significant --- target/riscv/csr.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f9ac21d687..390ef781e4 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -836,12 +836,21 @@ static int write_satp(CPURISCVState *env, int csrno, = target_ulong val) static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) { *val =3D env->hstatus; +#ifdef TARGET_RISCV64 + /* We only support 64-bit VSXL */ + *val =3D set_field(*val, HSTATUS_VSXL, 2); +#endif return 0; } =20 static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val) { env->hstatus =3D val; +#ifdef TARGET_RISCV64 + if (get_field(val, HSTATUS_VSXL) !=3D 2) { + qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN optio= ns."); + } +#endif return 0; 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charset="utf-8" Signed-off-by: Alistair Francis Message-id: 93e5d4f13eca0d2a588e407187f33c6437aeaaf9.1597259519.git.alistai= r.francis@wdc.com Message-Id: <93e5d4f13eca0d2a588e407187f33c6437aeaaf9.1597259519.git.alista= ir.francis@wdc.com> reviewed-by tags, which seems a shame for a fairly significant --- target/riscv/csr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 390ef781e4..5e50683c58 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -840,6 +840,8 @@ static int read_hstatus(CPURISCVState *env, int csrno, = target_ulong *val) /* We only support 64-bit VSXL */ *val =3D set_field(*val, HSTATUS_VSXL, 2); #endif + /* We only support little endian */ + *val =3D set_field(*val, HSTATUS_VSBE, 0); return 0; } =20 @@ -851,6 +853,9 @@ static int write_hstatus(CPURISCVState *env, int csrno,= target_ulong val) qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN optio= ns."); } #endif + if (get_field(val, HSTATUS_VSBE) !=3D 0) { + qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.= "); + } return 0; } =20 --=20 2.28.0 From nobody Sat May 18 21:26:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1598382515; cv=none; d=zohomail.com; s=zohoarc; b=YqRgmMnUF/x1Hp69FUdFltzuvVyqyqpFdWQXpWX/wp/RPoM1x3xPDFkmemEiG3QNjSIhYqMOfPWw06/9fuqP/MUsf1dWl82CK835gzNN8rsP1nZBbso6fPXAaOQevtSvNzB/pOKI28tzZ3Rkju9+e5LDlonpUaBCMGnBriUJRUI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598382515; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ofFV2+x2MvsJqzmkSb9IrTsehdalzRABOwukNMDqq5M=; b=K2E3QZ+wGmhvYO37ilECgL9hL1dNKN0Prw7o/mijuHOde1Rvg75nTmkY2GSmKbeNx/8+RqOfXjZYPxgBptIa3/zAzzEEhRBWKo956ySZZJWolKL7FnvcGvnFzAs4fXd/rnds+6CuMMpJ5V+jev7jEiDtKxTxcOOqLQ3ITZWHdbs= ARC-Authentication-Results: i=1; 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IronPort-SDR: tVNBhiQ2GOSMxQNuZq4bf8954aDMmkxsHx6WWvmvWt2mjNHcrcnno+rEMHtQQYCKDYxCtP4se/ fU5N4X/AmSrvtQ4Ckn/LJL1cjzV351tTpQVbFn2kaW/vvxPVTScO2GpfmDsAb721XD4rD+0TL2 c8s8Coz8b6rMZ8+PPfGHX/HdYMMHfrCzQ+2ePmeO04lYFaY3cQWCTPsSgb47QQwWww2R/REa1C DMEoDVMpP+j0+q9RQrqCZVW+oEnCniCoZM5yWcj+qg9+MuFR4MVPBzxn+4Vn3pF/jaHfFTgjCt 4Co= X-IronPort-AV: E=Sophos;i="5.76,353,1592841600"; d="scan'208";a="150145299" IronPort-SDR: xzVl+DTuKGi50sphAuNEBFfvrs4h2Jg1uA9Z46LHuo88KUOm8dwWaFDZJErsE8VLZFHsCQja4r BXDmYLTcfgBg== IronPort-SDR: emIWswTmUDFuWoBLllH/Hs+RLSMo1I2LYfjxuNoFjSG6nZ6vZLzK5b/Gl0sflMjb93IVEnquJH zkPy6JBgHCqw== WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org Subject: [PULL 16/18] target/riscv: Support the v0.6 Hypervisor extension CRSs Date: Tue, 25 Aug 2020 11:48:34 -0700 Message-Id: <20200825184836.1282371-17-alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200825184836.1282371-1-alistair.francis@wdc.com> References: <20200825184836.1282371-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=49978a6e9=alistair.francis@wdc.com; helo=esa3.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/25 14:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Message-id: 644b6c114b1a81adbee0ab8c9c66a8672059ec96.1597259519.git.alistai= r.francis@wdc.com Message-Id: <644b6c114b1a81adbee0ab8c9c66a8672059ec96.1597259519.git.alista= ir.francis@wdc.com> reviewed-by tags, which seems a shame for a fairly significant --- target/riscv/cpu_bits.h | 3 +++ target/riscv/csr.c | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 573d85da41..d88e2ea30d 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -197,9 +197,12 @@ #define CSR_HIDELEG 0x603 #define CSR_HIE 0x604 #define CSR_HCOUNTEREN 0x606 +#define CSR_HGEIE 0x607 #define CSR_HTVAL 0x643 +#define CSR_HVIP 0x645 #define CSR_HIP 0x644 #define CSR_HTINST 0x64A +#define CSR_HGEIP 0xE12 #define CSR_HGATP 0x680 #define CSR_HTIMEDELTA 0x605 #define CSR_HTIMEDELTAH 0x615 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5e50683c58..7dc50e6299 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -883,12 +883,25 @@ static int write_hideleg(CPURISCVState *env, int csrn= o, target_ulong val) return 0; } =20 +static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value, + target_ulong new_value, target_ulong write_mask) +{ + int ret =3D rmw_mip(env, 0, ret_value, new_value, + write_mask & hip_writable_mask); + + *ret_value &=3D hip_writable_mask; + + return ret; +} + static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask) { int ret =3D rmw_mip(env, 0, ret_value, new_value, write_mask & hip_writable_mask); =20 + *ret_value &=3D hip_writable_mask; + return ret; } =20 @@ -916,6 +929,18 @@ static int write_hcounteren(CPURISCVState *env, int cs= rno, target_ulong val) return 0; } =20 +static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val) +{ + qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); + return 0; +} + +static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val) +{ + qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); + return 0; +} + static int read_htval(CPURISCVState *env, int csrno, target_ulong *val) { *val =3D env->htval; @@ -939,6 +964,18 @@ static int write_htinst(CPURISCVState *env, int csrno,= target_ulong val) return 0; } =20 +static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val) +{ + qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); + return 0; +} + +static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val) +{ + qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN."); + return 0; +} + static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val) { *val =3D env->hgatp; @@ -1341,11 +1378,14 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE]= =3D { [CSR_HSTATUS] =3D { hmode, read_hstatus, write_hstat= us }, [CSR_HEDELEG] =3D { hmode, read_hedeleg, write_hedel= eg }, [CSR_HIDELEG] =3D { hmode, read_hideleg, write_hidel= eg }, + [CSR_HVIP] =3D { hmode, NULL, NULL, rmw_hvip = }, [CSR_HIP] =3D { hmode, NULL, NULL, rmw_hip = }, [CSR_HIE] =3D { hmode, read_hie, write_hie = }, [CSR_HCOUNTEREN] =3D { hmode, read_hcounteren, write_hcoun= teren }, + [CSR_HGEIE] =3D { hmode, read_hgeie, write_hgeie= }, [CSR_HTVAL] =3D { hmode, read_htval, write_htval= }, [CSR_HTINST] =3D { hmode, read_htinst, write_htins= t }, + [CSR_HGEIP] =3D { hmode, read_hgeip, write_hgeip= }, [CSR_HGATP] =3D { hmode, read_hgatp, write_hgatp= }, [CSR_HTIMEDELTA] =3D { hmode, read_htimedelta, write_htime= delta }, #if defined(TARGET_RISCV32) --=20 2.28.0 From nobody Sat May 18 21:26:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" When performing a CSR access let's return a negative exception value on an error instead of -1. This will allow us to specify the exception in future patches. Signed-off-by: Alistair Francis Message-id: a487dad60c9b8fe7a2b992c5e0dcc2504a9000a7.1597259519.git.alistai= r.francis@wdc.com Message-Id: reviewed-by tags, which seems a shame for a fairly significant --- target/riscv/csr.c | 46 ++++++++++++++++++++-------------------- target/riscv/op_helper.c | 18 ++++++++++------ 2 files changed, 35 insertions(+), 29 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 7dc50e6299..197ce97e95 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -51,7 +51,7 @@ static int fs(CPURISCVState *env, int csrno) return 0; } if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } #endif return 0; @@ -73,7 +73,7 @@ static int ctr(CPURISCVState *env, int csrno) =20 if (!cpu->cfg.ext_counters) { /* The Counters extensions is not enabled */ - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } #endif return 0; @@ -101,7 +101,7 @@ static int hmode(CPURISCVState *env, int csrno) } } =20 - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 static int pmp(CPURISCVState *env, int csrno) @@ -115,7 +115,7 @@ static int read_fflags(CPURISCVState *env, int csrno, t= arget_ulong *val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } #endif *val =3D riscv_cpu_get_fflags(env); @@ -126,7 +126,7 @@ static int write_fflags(CPURISCVState *env, int csrno, = target_ulong val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } env->mstatus |=3D MSTATUS_FS; #endif @@ -138,7 +138,7 @@ static int read_frm(CPURISCVState *env, int csrno, targ= et_ulong *val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } #endif *val =3D env->frm; @@ -149,7 +149,7 @@ static int write_frm(CPURISCVState *env, int csrno, tar= get_ulong val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } env->mstatus |=3D MSTATUS_FS; #endif @@ -161,7 +161,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, tar= get_ulong *val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } #endif *val =3D (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) @@ -177,7 +177,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, ta= rget_ulong val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } env->mstatus |=3D MSTATUS_FS; #endif @@ -291,7 +291,7 @@ static int read_time(CPURISCVState *env, int csrno, tar= get_ulong *val) uint64_t delta =3D riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; =20 if (!env->rdtime_fn) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 *val =3D env->rdtime_fn() + delta; @@ -304,7 +304,7 @@ static int read_timeh(CPURISCVState *env, int csrno, ta= rget_ulong *val) uint64_t delta =3D riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; =20 if (!env->rdtime_fn) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 *val =3D (env->rdtime_fn() + delta) >> 32; @@ -570,7 +570,7 @@ static int write_mcounteren(CPURISCVState *env, int csr= no, target_ulong val) static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *v= al) { if (env->priv_ver < PRIV_VERSION_1_11_0) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } *val =3D env->mcounteren; return 0; @@ -580,7 +580,7 @@ static int read_mscounteren(CPURISCVState *env, int csr= no, target_ulong *val) static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong v= al) { if (env->priv_ver < PRIV_VERSION_1_11_0) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } env->mcounteren =3D val; return 0; @@ -804,7 +804,7 @@ static int read_satp(CPURISCVState *env, int csrno, tar= get_ulong *val) } =20 if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } else { *val =3D env->satp; } @@ -821,7 +821,7 @@ static int write_satp(CPURISCVState *env, int csrno, ta= rget_ulong val) ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) { if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)= ) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } else { if((val ^ env->satp) & SATP_ASID) { tlb_flush(env_cpu(env)); @@ -991,7 +991,7 @@ static int write_hgatp(CPURISCVState *env, int csrno, t= arget_ulong val) static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *va= l) { if (!env->rdtime_fn) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 #if defined(TARGET_RISCV32) @@ -1005,7 +1005,7 @@ static int read_htimedelta(CPURISCVState *env, int cs= rno, target_ulong *val) static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong va= l) { if (!env->rdtime_fn) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 #if defined(TARGET_RISCV32) @@ -1020,7 +1020,7 @@ static int write_htimedelta(CPURISCVState *env, int c= srno, target_ulong val) static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *v= al) { if (!env->rdtime_fn) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 *val =3D env->htimedelta >> 32; @@ -1030,7 +1030,7 @@ static int read_htimedeltah(CPURISCVState *env, int c= srno, target_ulong *val) static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong v= al) { if (!env->rdtime_fn) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 env->htimedelta =3D deposit64(env->htimedelta, 32, 32, (uint64_t)val); @@ -1228,18 +1228,18 @@ int riscv_csrrw(CPURISCVState *env, int csrno, targ= et_ulong *ret_value, =20 if ((write_mask && read_only) || (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } #endif =20 /* ensure the CSR extension is enabled. */ if (!cpu->cfg.ext_icsr) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 /* check predicate */ if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) = < 0) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 /* execute combined read/write operation if it exists */ @@ -1249,7 +1249,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target= _ulong *ret_value, =20 /* if no accessor exists then return failure */ if (!csr_ops[csrno].read) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 /* read old value */ diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 4b64bfe7d2..948d204793 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -43,8 +43,10 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulo= ng src, target_ulong csr) { target_ulong val =3D 0; - if (riscv_csrrw(env, csr, &val, src, -1) < 0) { - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + int ret =3D riscv_csrrw(env, csr, &val, src, -1); + + if (ret < 0) { + riscv_raise_exception(env, -ret, GETPC()); } return val; } @@ -53,8 +55,10 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulo= ng src, target_ulong csr, target_ulong rs1_pass) { target_ulong val =3D 0; - if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) { - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + int ret =3D riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0); + + if (ret < 0) { + riscv_raise_exception(env, -ret, GETPC()); } return val; } @@ -63,8 +67,10 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulo= ng src, target_ulong csr, target_ulong rs1_pass) { target_ulong val =3D 0; - if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) { - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + int ret =3D riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0); + + if (ret < 0) { + riscv_raise_exception(env, -ret, GETPC()); } return val; } --=20 2.28.0 From nobody Sat May 18 21:26:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1598382709; cv=none; d=zohomail.com; s=zohoarc; b=jfvhDijGnq//WIpd9yGPOQcQYRccVLymvfZOEvgpj5pHnynujMjwnR1OZ3tWriH14LdEmnDnC7R574qGXIkfk9lj50PdOW03+upAfIyN2t5X9qIpWtORvM4tPVl5z7PA2PBn52wda52hhYSj7ZjVWa5ASW/MavWgUHJjPib+6GA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598382709; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/ep5j+2tCCQEqO+Cq71MA2oXTu4IgQ6t+xZhbeD/p4E=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=49978a6e9=alistair.francis@wdc.com; helo=esa3.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/25 14:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Message-id: 4c744dce9b0b057cbb5cc0f4d4ac75cda682a8af.1597259519.git.alistai= r.francis@wdc.com Message-Id: <4c744dce9b0b057cbb5cc0f4d4ac75cda682a8af.1597259519.git.alista= ir.francis@wdc.com> reviewed-by tags, which seems a shame for a fairly significant --- target/riscv/cpu_bits.h | 6 +++ target/riscv/helper.h | 1 + target/riscv/csr.c | 64 ++++++++++++++++++++++++- target/riscv/op_helper.c | 42 ++++++++++++++-- target/riscv/insn_trans/trans_rvh.c.inc | 2 +- 5 files changed, 109 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index d88e2ea30d..bd36062877 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -461,6 +461,11 @@ #define HSTATUS_WPRI HSTATUS64_WPRI #endif =20 +#define HCOUNTEREN_CY (1 << 0) +#define HCOUNTEREN_TM (1 << 1) +#define HCOUNTEREN_IR (1 << 2) +#define HCOUNTEREN_HPM3 (1 << 3) + /* Privilege modes */ #define PRV_U 0 #define PRV_S 1 @@ -553,6 +558,7 @@ #define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0= */ #define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14 #define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15 +#define RISCV_EXCP_VIRT_INSTRUCTION_FAULT 0x16 #define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT 0x17 =20 #define RISCV_EXCP_INT_FLAG 0x80000000 diff --git a/target/riscv/helper.h b/target/riscv/helper.h index c8029d83f9..4b690147fb 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -80,6 +80,7 @@ DEF_HELPER_1(tlb_flush, void, env) /* Hypervisor functions */ #ifndef CONFIG_USER_ONLY DEF_HELPER_1(hyp_tlb_flush, void, env) +DEF_HELPER_1(hyp_gvma_tlb_flush, void, env) DEF_HELPER_4(hyp_load, tl, env, tl, tl, tl) DEF_HELPER_5(hyp_store, void, env, tl, tl, tl, tl) DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 197ce97e95..200001de74 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -75,6 +75,61 @@ static int ctr(CPURISCVState *env, int csrno) /* The Counters extensions is not enabled */ return -RISCV_EXCP_ILLEGAL_INST; } + + if (riscv_cpu_virt_enabled(env)) { + switch (csrno) { + case CSR_CYCLE: + if (!get_field(env->hcounteren, HCOUNTEREN_CY) && + get_field(env->mcounteren, HCOUNTEREN_CY)) { + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + break; + case CSR_TIME: + if (!get_field(env->hcounteren, HCOUNTEREN_TM) && + get_field(env->mcounteren, HCOUNTEREN_TM)) { + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + break; + case CSR_INSTRET: + if (!get_field(env->hcounteren, HCOUNTEREN_IR) && + get_field(env->mcounteren, HCOUNTEREN_IR)) { + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + break; + case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: + if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)= ) && + get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))= ) { + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + break; +#if defined(TARGET_RISCV32) + case CSR_CYCLEH: + if (!get_field(env->hcounteren, HCOUNTEREN_CY) && + get_field(env->mcounteren, HCOUNTEREN_CY)) { + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + break; + case CSR_TIMEH: + if (!get_field(env->hcounteren, HCOUNTEREN_TM) && + get_field(env->mcounteren, HCOUNTEREN_TM)) { + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + break; + case CSR_INSTRETH: + if (!get_field(env->hcounteren, HCOUNTEREN_IR) && + get_field(env->mcounteren, HCOUNTEREN_IR)) { + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + break; + case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: + if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H= )) && + get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)= )) { + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + break; +#endif + } + } #endif return 0; } @@ -98,6 +153,8 @@ static int hmode(CPURISCVState *env, int csrno) if ((env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || env->priv =3D=3D PRV_M) { return 0; + } else { + return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } } =20 @@ -340,6 +397,7 @@ static const target_ulong delegable_excps =3D (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | + (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); static const target_ulong sstatus_v1_10_mask =3D SSTATUS_SIE | SSTATUS_SPI= E | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | @@ -1238,9 +1296,13 @@ int riscv_csrrw(CPURISCVState *env, int csrno, targe= t_ulong *ret_value, } =20 /* check predicate */ - if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) = < 0) { + if (!csr_ops[csrno].predicate) { return -RISCV_EXCP_ILLEGAL_INST; } + ret =3D csr_ops[csrno].predicate(env, csrno); + if (ret < 0) { + return ret; + } =20 /* execute combined read/write operation if it exists */ if (csr_ops[csrno].op) { diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 948d204793..9b9ada45a9 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -94,6 +94,11 @@ target_ulong helper_sret(CPURISCVState *env, target_ulon= g cpu_pc_deb) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } =20 + if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_VTSR)) { + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); + } + mstatus =3D env->mstatus; =20 if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) { @@ -176,7 +181,7 @@ void helper_wfi(CPURISCVState *env) if ((env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TW)) || riscv_cpu_virt_enabled(env)) { - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } else { cs->halted =3D 1; cs->exception_index =3D EXCP_HLT; @@ -191,6 +196,9 @@ void helper_tlb_flush(CPURISCVState *env) (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM))) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } else if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_VTVM)) { + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } else { tlb_flush(cs); } @@ -200,6 +208,10 @@ void helper_hyp_tlb_flush(CPURISCVState *env) { CPUState *cs =3D env_cpu(env); =20 + if (env->priv =3D=3D PRV_S && riscv_cpu_virt_enabled(env)) { + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); + } + if (env->priv =3D=3D PRV_M || (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env))) { tlb_flush(cs); @@ -209,6 +221,16 @@ void helper_hyp_tlb_flush(CPURISCVState *env) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } =20 +void helper_hyp_gvma_tlb_flush(CPURISCVState *env) +{ + if (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env) && + get_field(env->mstatus, MSTATUS_TVM)) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + helper_hyp_tlb_flush(env); +} + target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address, target_ulong attrs, target_ulong memop) { @@ -251,7 +273,11 @@ target_ulong helper_hyp_load(CPURISCVState *env, targe= t_ulong address, return pte; } =20 - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + if (riscv_cpu_virt_enabled(env)) { + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); + } else { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } return 0; } =20 @@ -289,7 +315,11 @@ void helper_hyp_store(CPURISCVState *env, target_ulong= address, return; } =20 - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + if (riscv_cpu_virt_enabled(env)) { + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); + } else { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } } =20 target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address, @@ -319,7 +349,11 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, tar= get_ulong address, return pte; } =20 - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + if (riscv_cpu_virt_enabled(env)) { + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); + } else { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } return 0; } =20 diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_tr= ans/trans_rvh.c.inc index db650ae62a..881c9ef4d2 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -360,7 +360,7 @@ static bool trans_hfence_gvma(DisasContext *ctx, arg_sf= ence_vma *a) { REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY - gen_helper_hyp_tlb_flush(cpu_env); + gen_helper_hyp_gvma_tlb_flush(cpu_env); return true; #endif return false; --=20 2.28.0