[v3] target/arm: Add support for FEAT_TLBIOS and FEAT_TLBIRANGE

[PATCH v3 0/3] target/arm: Add support for FEAT_TLBIOS and FEAT_TLBIRANGE

Rebecca Cran posted 3 patches 4 years, 8 months ago

Diff against v2 v4 v5 v6
Download series mbox

Test checkpatch passed

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20210310002917.8876-1-rebecca@nuviainc.com

Maintainers: Richard Henderson <richard.henderson@linaro.org>, Paolo Bonzini <pbonzini@redhat.com>, Peter Maydell <peter.maydell@linaro.org>

There is a newer version of this series

accel/tcg/cputlb.c      |  22 ++
include/exec/exec-all.h |  41 +++
target/arm/cpu.h        |  11 +
target/arm/cpu64.c      |   1 +
target/arm/helper.c     | 323 ++++++++++++++++++++
5 files changed, 398 insertions(+)

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[PATCH v3 0/3] target/arm: Add support for FEAT_TLBIOS and FEAT_TLBIRANGE

Posted by Rebecca Cran 4 years, 8 months ago

ARMv8.4 adds the mandatory FEAT_TLBIOS and FEAT_TLBIRANGE. 
They provides TLBI maintenance instructions that extend to the Outer
Shareable domain and that apply to a range of input addresses.
    
Changes from v2 to v3:

o Change the functions in cputlb.c to do a full flush. This should
  only be a short-term implementation.

Testing:
  o Ran scripts/checkpatch.pl: functions in exec-all.h fail,
    but I think that's acceptable?
  o Built all targets
  o Ran test code that executed the new instructions
  o Ran "make test"

Rebecca Cran (3):
  target/arm: Add support for FEAT_TLBIRANGE
  target/arm: Add support for FEAT_TLBIOS
  target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type

 accel/tcg/cputlb.c      |  22 ++
 include/exec/exec-all.h |  41 +++
 target/arm/cpu.h        |  11 +
 target/arm/cpu64.c      |   1 +
 target/arm/helper.c     | 323 ++++++++++++++++++++
 5 files changed, 398 insertions(+)

-- 
2.26.2