From nobody Wed Nov 19 07:05:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1615336400; cv=none; d=zohomail.com; s=zohoarc; b=d1tfwWk/04qnC6+DfC6NaMf6+4DZHYYf2fYU4i9PRa9Wdg9L04V0kj3xxtbMe45PiLNGRwHsZ5kQEBnD0oYjjbn88jFUNd/+IgCxZIUbE8gWerd1y1+oughrjO+918SLnfV/7ZAEw10Kb8X5eW8Bo6/MksyzC63aFws2qQHCb/4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615336400; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0rMz1FtL7RQxG5i7Rgib/rdQSH/PwoRE3DozIs3GVI0=; b=XrmZDBnKLuy/Q1d2fMsV6sdBVUKXpnEPT6kzRjYNGxIApg6LcRdNcp9BXlO8/9x0uR0S0ILOHiqoR5vG0T5FBfrtlRKOrauBX3TGdWPcrZRLFPQpjb8TCRsXuT8wXEeKi4u2lE50ZwV4WrbFXCfG+aBlHY+GXgyrWxa7S5IOnOk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1615336400615804.6821504057456; Tue, 9 Mar 2021 16:33:20 -0800 (PST) Received: from localhost ([::1]:33432 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lJmmt-0004Ly-Hb for importer@patchew.org; Tue, 09 Mar 2021 19:33:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39584) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lJmjC-0000VB-8b for qemu-devel@nongnu.org; Tue, 09 Mar 2021 19:29:31 -0500 Received: from mail-il1-x131.google.com ([2607:f8b0:4864:20::131]:41791) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lJmj6-0001HR-Cw for qemu-devel@nongnu.org; Tue, 09 Mar 2021 19:29:29 -0500 Received: by mail-il1-x131.google.com with SMTP id c10so13903561ilo.8 for ; Tue, 09 Mar 2021 16:29:24 -0800 (PST) Received: from cube.int.bluestop.org (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id h23sm8048808ila.15.2021.03.09.16.29.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Mar 2021 16:29:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0rMz1FtL7RQxG5i7Rgib/rdQSH/PwoRE3DozIs3GVI0=; b=yi2Vz9IoleNeV3lasWMbrGSuvelUHaFGTA6noOEguI8QWsSDIZlctL5RiRWr6g93in LcD5fCK/AHyE8aPJoJgNlK8u7Ig7QfFHc4MVquO2Of/GtruWQ2MG4LgHndt0yKlaPwPg caejwLtYSya+lAILTSqnA5AsDcVFxZ+eEyFDyGfv53gfdYKL2DghsnweR7h0aU5MuHAA /NVHhla8R5ZLxKmMpySuMYd8KzJcJFXUPgXQXvPTA32oxxPZaUGKDQkAnQrmdeAJod+w 4Tlr2nwwTcaquys8y4PA/Hv9L0eaZz4Ig2LZqDACbEFpJvjJrgS0OxGogTYO2p7UrWlj e3hA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0rMz1FtL7RQxG5i7Rgib/rdQSH/PwoRE3DozIs3GVI0=; b=kyiPKEeMfJeHMUMloM4JBkgbJpKNwmApgha/vz2Ui9KdCVbQY1ASHryYjedosWIugQ lEDrAb5zvyiUG8DHIOhPxRY9Ert4c/z+9xaySwbsZ0jJs4wUzBmy7Y+dbK1vQrPzpq9o LQKOFzo5cSruNtxMnPw57Y3Ben3ZkJygk6vIF19K3YrrSvH13JNvG8LSIPQQ7E/WYH2z bwgmNI9eji7GCw5A83e3YllXgmjvCXaFiUmCDo5A0RYwn4s1HpHZ2rK7/5hUkr5jPzcT u54M79y5+S79ZJSFwihfhZ2AtPrF7F/rjpi2fVRYLVR7HM3e2hCR7bUcgGAVWiBc8wsT C50A== X-Gm-Message-State: AOAM531lc958OG2z0wJqJac31519gnp/IiZMT2Vn4O27wOKHy3C4DJoO SI/g3Y6749hxh7K9NTebeH4umw== X-Google-Smtp-Source: ABdhPJzWwRpJE/H05jbLtQF+Ywp8v65sD5X5xZdJQ2+nUI+3pBd6YhKc94b49D7X/hGnnFgyy5Z7Lw== X-Received: by 2002:a05:6e02:1351:: with SMTP id k17mr714578ilr.204.1615336163282; Tue, 09 Mar 2021 16:29:23 -0800 (PST) From: Rebecca Cran To: Peter Maydell , Richard Henderson , qemu-arm@nongnu.org Subject: [PATCH v3 1/3] target/arm: Add support for FEAT_TLBIRANGE Date: Tue, 9 Mar 2021 17:29:15 -0700 Message-Id: <20210310002917.8876-2-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210310002917.8876-1-rebecca@nuviainc.com> References: <20210310002917.8876-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::131; envelope-from=rebecca@nuviainc.com; helo=mail-il1-x131.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @nuviainc-com.20150623.gappssmtp.com) Content-Type: text/plain; charset="utf-8" ARMv8.4 adds the mandatory FEAT_TLBIRANGE. It provides TLBI maintenance instructions that apply to a range of input addresses. Signed-off-by: Rebecca Cran --- accel/tcg/cputlb.c | 22 ++ include/exec/exec-all.h | 41 ++++ target/arm/cpu.h | 5 + target/arm/helper.c | 248 ++++++++++++++++++++ 4 files changed, 316 insertions(+) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 8a7b779270a4..233fe302c236 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -623,6 +623,28 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr) tlb_flush_page_by_mmuidx(cpu, addr, ALL_MMUIDX_BITS); } =20 +void tlb_flush_page_range_by_mmuidx(CPUState *cpu, target_ulong addr, + unsigned int num_pages, uint16_t idxma= p) +{ + /* + * We currently do a full flush, but for performance this should be + * updated to only flush the requested pages, taking TBI into account. + */ + tlb_flush_by_mmuidx(cpu, idxmap); +} + +void tlb_flush_page_range_by_mmuidx_all_cpus_synced(CPUState *src_cpu, + target_ulong addr, + unsigned int num_pages, + uint16_t idxmap) +{ + /* + * We currently do a full flush, but for performance this should be + * updated to only flush the requested pages, taking TBI into account. + */ + tlb_flush_by_mmuidx_all_cpus_synced(src_cpu, idxmap); +} + void tlb_flush_page_by_mmuidx_all_cpus(CPUState *src_cpu, target_ulong add= r, uint16_t idxmap) { diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 6b036cae8f65..91232cd48d22 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -212,6 +212,35 @@ void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, = target_ulong addr, */ void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong = addr, uint16_t idxmap); +/** + * tlb_flush_page_range_by_mmuidx: + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of start of page range to be flushed + * @num_pages: the number of pages to be flushed + * @idxmap: bitmap of MMU indexes to flush + * + * Flush a range of pages from the TLB of the specified CPU, for the speci= fied + * MMU indexes. + */ +void tlb_flush_page_range_by_mmuidx(CPUState *cpu, target_ulong addr, + unsigned int num_pages, uint16_t idxma= p); +/** + * tlb_flush_page_range_by_mmuidx_all_cpus_synced: + * @cpu: Originating CPU of the flush + * @addr: virtual address of start of page range to be flushed + * @num_pages: the number of pages to be flushed + * @idxmap: bitmap of MMU indexes to flush + * + * Flush a range of pages from the TLB of all CPUs, for the specified MMU + * indexes like tlb_flush_page_by_mmuidx_all_cpus except the source + * vCPUs work is scheduled as safe work meaning all flushes will be + * complete once the source vCPUs safe work is complete. This will + * depend on when the guests translation ends the TB. + */ +void tlb_flush_page_range_by_mmuidx_all_cpus_synced(CPUState *cpu, + target_ulong addr, + unsigned int num_pages, + uint16_t idxmap); /** * tlb_flush_by_mmuidx: * @cpu: CPU whose TLB should be flushed @@ -313,6 +342,18 @@ static inline void tlb_flush_page_all_cpus_synced(CPUS= tate *src, target_ulong addr) { } +static inline void tlb_flush_page_range_by_mmuidx(CPUState *cpu, + target_ulong addr, + unsigned int num_pages, + int idxmap) +{ +} +static inline void tlb_flush_page_range_by_mmuidx_all_cpus_synced(CPUState= *src_cpu, + target_u= long addr, + unsigned= int num_pages, + uint16_t= idxmap) +{ +} static inline void tlb_flush(CPUState *cpu) { } diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 193a49ec7fac..32b78a4ef587 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4038,6 +4038,11 @@ static inline bool isar_feature_aa64_pauth_arch(cons= t ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) !=3D 0; } =20 +static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) =3D=3D 2; +} + static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 904b0927cd22..ec81586d90dd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4759,6 +4759,171 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env= , const ARMCPRegInfo *ri, ARMMMUIdxBit_SE3, bits); } =20 +#ifdef TARGET_AARCH64 +static unsigned int tlbi_aa64_range_get_num_pages(CPUARMState *env, + uint64_t value, + uint64_t addr) +{ + unsigned int page_size; + unsigned int page_shift; + unsigned int page_size_granule; + uint64_t num; + uint64_t scale; + uint64_t exponent; + uint64_t high_addr; + + num =3D (value >> 39) & 0xF; + scale =3D (value >> 44) & 0x3; + page_size_granule =3D (value >> 46) & 0x3; + + switch (page_size_granule) { + case 1: + page_size =3D 4096; + page_shift =3D 12; + break; + case 2: + page_size =3D 16384; + page_shift =3D 14; + break; + case 3: + page_size =3D 65536; + page_shift =3D 16; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n", + page_size_granule); + + raise_exception(env, EXCP_UDEF, syn_uncategorized(), + exception_target_el(env)); + + break; + } + + exponent =3D (5 * scale) + 1; + high_addr =3D addr + (((num + 1) << exponent) * page_size); + + return (high_addr - addr) >> page_shift; +} + +static void tlbi_aa64_rvae1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL1&0. + * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1, + * since we don't support flush-for-specific-ASID-only or + * flush-last-level-only. + */ + CPUState *cs =3D env_cpu(env); + int mask =3D vae1_tlbmask(env); + uint64_t addr =3D (value & 0xFFFFFFFFFUL) << TARGET_PAGE_BITS; + unsigned int num_pages =3D tlbi_aa64_range_get_num_pages(env, value, a= ddr); + + if (tlb_force_broadcast(env)) { + tlb_flush_page_range_by_mmuidx_all_cpus_synced(cs, addr, num_pages, + mask); + } else { + tlb_flush_page_range_by_mmuidx(cs, addr, num_pages, mask); + } +} + +static void tlbi_aa64_rvae1is_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + /* + * Invalidate by VA range, Inner/Outer Shareable EL1&0. + * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS, + * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support + * flush-for-specific-ASID-only, flush-last-level-only or inner/outer + * shareable specific flushes. + */ + CPUState *cs =3D env_cpu(env); + int mask =3D vae1_tlbmask(env); + uint64_t addr =3D (value & 0xFFFFFFFFFUL) << TARGET_PAGE_BITS; + unsigned int num_pages =3D tlbi_aa64_range_get_num_pages(env, value, a= ddr); + + tlb_flush_page_range_by_mmuidx_all_cpus_synced(cs, addr, num_pages, ma= sk); +} + +static void tlbi_aa64_rvae2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL2. + * Currently handles all of RVAE2, RVAAE2, RVAALE2 and RVALE2, + * since we don't support flush-for-specific-ASID-only or + * flush-last-level-only. + */ + CPUState *cs =3D env_cpu(env); + uint64_t addr =3D (value & 0xFFFFFFFFFUL) << TARGET_PAGE_BITS; + unsigned int num_pages =3D tlbi_aa64_range_get_num_pages(env, value, a= ddr); + + if (tlb_force_broadcast(env)) { + tlb_flush_page_range_by_mmuidx_all_cpus_synced(cs, addr, num_pages, + ARMMMUIdxBit_E2); + } else { + tlb_flush_page_range_by_mmuidx(cs, addr, num_pages, ARMMMUIdxBit_E= 2); + } +} + +static void tlbi_aa64_rvae2is_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + /* + * Invalidate by VA range, Inner/Outer Shareable, EL2. + * Currently handles all of RVAE2IS, RVAE2OS, RVAAE2IS, RVAAE2OS, + * RVAALE2IS, RVAALE2OS, RVALE2IS and RVALE2OS, since we don't support + * flush-for-specific-ASID-only, flush-last-level-only or inner/outer + * shareable specific flushes. + */ + CPUState *cs =3D env_cpu(env); + uint64_t addr =3D (value & 0xFFFFFFFFFUL) << TARGET_PAGE_BITS; + unsigned int num_pages =3D tlbi_aa64_range_get_num_pages(env, value, a= ddr); + + tlb_flush_page_range_by_mmuidx_all_cpus_synced(cs, addr, num_pages, + ARMMMUIdxBit_E2); +} + +static void tlbi_aa64_rvae3_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL3. + * Currently handles all of RVAE3, RVAAE3, RVAALE3 and RVALE3, + * since we don't support flush-for-specific-ASID-only or + * flush-last-level-only. + */ + CPUState *cs =3D env_cpu(env); + uint64_t addr =3D (value & 0xFFFFFFFFFUL) << TARGET_PAGE_BITS; + unsigned int num_pages =3D tlbi_aa64_range_get_num_pages(env, value, a= ddr); + + if (tlb_force_broadcast(env)) { + tlb_flush_page_range_by_mmuidx_all_cpus_synced(cs, addr, num_pages, + ARMMMUIdxBit_SE3); + } else { + tlb_flush_page_range_by_mmuidx(cs, addr, num_pages, ARMMMUIdxBit_S= E3); + } +} + +static void tlbi_aa64_rvae3is_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL3, Inner/Outer Shareable. + * Currently handles all of RVAE3IS, RVAE3OS, RVAAE3IS, RVAAE3OS, + * RVAALE3IS, RVAALE3OS, RVALE3IS, and RVALE3OS, since we don't support + * flush-for-specific-ASID-only, flush-last-level-only or inner/outer + * specific flushes. + */ + CPUState *cs =3D env_cpu(env); + uint64_t addr =3D (value & 0xFFFFFFFFFUL) << TARGET_PAGE_BITS; + unsigned int num_pages =3D tlbi_aa64_range_get_num_pages(env, value, a= ddr); + + tlb_flush_page_range_by_mmuidx_all_cpus_synced(cs, addr, num_pages, + ARMMMUIdxBit_SE3); +} +#endif + static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo= *ri, bool isread) { @@ -6920,6 +7085,86 @@ static const ARMCPRegInfo pauth_reginfo[] =3D { REGINFO_SENTINEL }; =20 +static const ARMCPRegInfo tlbirange_reginfo[] =3D { + { .name =3D "TLBI_RVAE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAAE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 3, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVALE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAALE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 7, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1_write }, + { .name =3D "TLBI_RVAAE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 3, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1_write }, + { .name =3D "TLBI_RVALE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1_write }, + { .name =3D "TLBI_RVAALE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 7, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1_write }, + { .name =3D "TLBI_RIPAS2E1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 2, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2LE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RVAE2IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2is_write }, + { .name =3D "TLBI_RVALE2IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2is_write }, + { .name =3D "TLBI_RIPAS2E1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 2, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2LE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RVAE2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2_write }, + { .name =3D "TLBI_RVALE2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2_write }, + { .name =3D "TLBI_RVAE3IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3is_write }, + { .name =3D "TLBI_RVALE3IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3is_write }, + { .name =3D "TLBI_RVAE3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3_write }, + { .name =3D "TLBI_RVALE3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3_write }, + REGINFO_SENTINEL +}; + static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) { Error *err =3D NULL; @@ -8289,6 +8534,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_rndr, cpu)) { define_arm_cp_regs(cpu, rndr_reginfo); } + if (cpu_isar_feature(aa64_tlbirange, cpu)) { + define_arm_cp_regs(cpu, tlbirange_reginfo); + } #ifndef CONFIG_USER_ONLY /* Data Cache clean instructions up to PoP */ if (cpu_isar_feature(aa64_dcpop, cpu)) { --=20 2.26.2 From nobody Wed Nov 19 07:05:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1615336300; cv=none; d=zohomail.com; s=zohoarc; b=Ad9vF01U15CMlB8xpyScsWNtbyyBjCATNKq+5GbbUYAtc1GZpbPmI4dzLQMnKaQHx3CVnGYFTBxBShzTiNGswtDfmBYFEg87CAQSEh+3C7EsRJBRUZaV3YJdQpT3/H/elFmUZtm62k0kUs/okS9s+61okpRxq2oEJzmCwwNYwTA= ARC-Message-Signature: i=1; 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id h23sm8048808ila.15.2021.03.09.16.29.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Mar 2021 16:29:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ABbzHq/dojuUgxv8IlC5DB9LOuMI2xkumPREVmWvePA=; b=HLx47ODPMXqJz472Q6G4YBsQeRVDeUToMdAkTJjbzg0vMcpBs9JwRtTbI/sL2T8FJd eb52m093TwC1n9a0Hv7hf0U8hO1cm1mYYl98hYzgA+vIqRwAmMEQMFPRuy/6nG/bToQn jH2NMFmFc6qLYAdzLDjvAs+kMIO1CYgfsgigZr8XeYxLPzgHauUYBU5WFgCc8NwpjmQo DAijFjwu3yFhMxzL7g+tqo96AYbrjTWGgWU69ndoDXkdQ0TX9/zimZhecL8TMathSFT7 RIA06OiFsWlvB6LEhO+I6EBB0dXtqigxNf+J8w4R6NYGJAOrfo3Fahh9Wr4pKl0dWEdX KrGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ABbzHq/dojuUgxv8IlC5DB9LOuMI2xkumPREVmWvePA=; b=pM1fy1M/4Qwnxwv9npeprH6awZFg/g0ZVaI4/eNIOw76fUksCl2Hq026lhZVXWeiQ9 D05801qqbY6XtR38SSyqhkqqO+FUUd2HrR0VPjNsGOl0sG8h4hB1bZUa2U16Hf/sZ2Ug zXyX+mc6YZkMLep6XjLNTZ/PkGVgKRonJ9KlF3P/4L2Ter60IxaxdJT6HlZCbUAOg0Up yKt42OTps4gJZwdcxNO7DcR6Swq3hOWVA00deRRB3QiDbHb7um2e9sOPSRPc4dpqEu5A pWLmkuxLofdKjK/1Raq9M4kA7ecncMZqo55r4JVh0F6mWuQai5Drf8LZ+DuMI5F6D5NC 5wNA== X-Gm-Message-State: AOAM532EdZLLhfYXE+daa4Rk7Gf1n2YP3llV07LoeMbab4znUlk7nHlx mwi9uCgu0VuCMqEOnczTv9CdjQ== X-Google-Smtp-Source: ABdhPJzCuRMSlboeRN05JYJbAfKjG1ZhqyKU1OFlrvNSYgS04Fd0Mkf54TaancYIyxgeeSlpFJ8oAg== X-Received: by 2002:a92:6909:: with SMTP id e9mr673983ilc.34.1615336164183; Tue, 09 Mar 2021 16:29:24 -0800 (PST) From: Rebecca Cran To: Peter Maydell , Richard Henderson , qemu-arm@nongnu.org Subject: [PATCH v3 2/3] target/arm: Add support for FEAT_TLBIOS Date: Tue, 9 Mar 2021 17:29:16 -0700 Message-Id: <20210310002917.8876-3-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210310002917.8876-1-rebecca@nuviainc.com> References: <20210310002917.8876-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::12e; envelope-from=rebecca@nuviainc.com; helo=mail-il1-x12e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @nuviainc-com.20150623.gappssmtp.com) Content-Type: text/plain; charset="utf-8" ARMv8.4 adds the mandatory FEAT_TLBIOS. It provides TLBI maintenance instructions that extend to the Outer Shareable domain. Signed-off-by: Rebecca Cran --- target/arm/cpu.h | 6 ++ target/arm/helper.c | 75 ++++++++++++++++++++ 2 files changed, 81 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 32b78a4ef587..cf0801994a5f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4043,6 +4043,12 @@ static inline bool isar_feature_aa64_tlbirange(const= ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) =3D=3D 2; } =20 +static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) =3D=3D 1 || + FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) =3D=3D 2; +} + static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index ec81586d90dd..b1f634b0c897 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7165,6 +7165,78 @@ static const ARMCPRegInfo tlbirange_reginfo[] =3D { REGINFO_SENTINEL }; =20 +static const ARMCPRegInfo tlbios_reginfo[] =3D { + { .name =3D "TLBI_VMALLE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vmalle1is_write }, + { .name =3D "TLBI_ASIDE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 2, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vmalle1is_write }, + { .name =3D "TLBI_RVAE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAAE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 3, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVALE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAALE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 7, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_ALLE2OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle2is_write }, + { .name =3D "TLBI_ALLE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 4, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle1is_write }, + { .name =3D "TLBI_VMALLS12E1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle1is_write }, + { .name =3D "TLBI_IPAS2E1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 0, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2E1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 3, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_IPAS2LE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 4, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2LE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 7, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RVAE2OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2is_write }, + { .name =3D "TLBI_RVALE2OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2is_write }, + { .name =3D "TLBI_ALLE3OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle3is_write }, + { .name =3D "TLBI_RVAE3OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3is_write }, + { .name =3D "TLBI_RVALE3OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3is_write }, + REGINFO_SENTINEL +}; + static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) { Error *err =3D NULL; @@ -8537,6 +8609,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_tlbirange, cpu)) { define_arm_cp_regs(cpu, tlbirange_reginfo); } + if (cpu_isar_feature(aa64_tlbios, cpu)) { + define_arm_cp_regs(cpu, tlbios_reginfo); + } #ifndef CONFIG_USER_ONLY /* Data Cache clean instructions up to PoP */ if (cpu_isar_feature(aa64_dcpop, cpu)) { --=20 2.26.2 From nobody Wed Nov 19 07:05:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1615336342; cv=none; d=zohomail.com; s=zohoarc; b=kL1g5zPzWAx+mfTgv3bYnk/DVC/sBFmhFFFJIxr/Z1WefNCcE0Mi4fNIta4qyFYqNe13tMraQ/1ZMy1wxcyFLjRPiMISfpjX8jWW/ChgNG/y1Yj9rfqbUlhFPd7TdUX0zQBPcjdQRpo06LKrDYdRJ6e58wmkqJVe4kFXWikoawU= ARC-Message-Signature: i=1; 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id h23sm8048808ila.15.2021.03.09.16.29.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Mar 2021 16:29:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MtrYd2+kxak4VR0FTDOw2marOmVpM5v4db/Bahi46Lk=; b=TxsM5xMYm4zV/19duA2bA2Ow9hoMsbDBuZdcnbhlAd3cs0X7IwXTlnNW34Rw9aXafs omeeNRN40pV+wNVfdJO7aSbjjBrdS+jnCtBQCaaBYyAA7PTXtwsh+cIqSL8WCnMJ2eki 3xzsYbBLUb5kPaj9ntyyr6mIc/2L++mrkHkXfYt3s1sQai8JuIKcvP5RlYeWO0SIH/gy lDdEJWd+6izdTjIuGxWNG61FyoMQA+baXph9s+Yii/PLfjGaimYH1R7hbt+YTmpWFJmA jg65ifQcf4Hhw33gWLIogvSlj61Ruj8gv8EuBJc7I9MhgQw1Dhn3iCdXQvYT4PqB6Ca2 yC5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MtrYd2+kxak4VR0FTDOw2marOmVpM5v4db/Bahi46Lk=; b=q5HQxlzd73iYoO+YJBgrbDNVuKNADZnbupuHnTcav/Eb6DGRh+nn2YZP/xeXiaxvE0 jNwulOTB2jnOOoA+fBc4nJfjwueqpw9Nxv1PI8K3WRQZ8ho62ytgkwsac/Gire4fF3/Y RavQ2BDnNNlC1Sq222+HgKNjJi+wjtn9b78Yi5iZzVvUgoiFF+kf4HFk2qu4jOpEkr3n xe93GiVXK9Pq9fYuetTCUkIxZLSWJYneGI3yIPQqtBEMVXOFw3mfyvhuuGRTUcBTgkBa 4TCN1D/lkrYNoBQ38H9jPlPtauw8zJ7cXXF0D58Ncp9CVvWfFqkMtiZullSdXY6h74Gy +A3w== X-Gm-Message-State: AOAM5330Bc4xRA+gZgLd/FJbZQoz0l92Weom9YhTOfalbFFz0rC/z1JJ 5RqwQdRhFgi4WvConXvZC/bJCg== X-Google-Smtp-Source: ABdhPJwmeaAuf6O551PO3TFxIpk/8i447GzdJf6NjoADAcL2vVG8KB7qcr9d9bv6IPQLPSdwQph/hg== X-Received: by 2002:a05:6e02:12e3:: with SMTP id l3mr714513iln.24.1615336165181; Tue, 09 Mar 2021 16:29:25 -0800 (PST) From: Rebecca Cran To: Peter Maydell , Richard Henderson , qemu-arm@nongnu.org Subject: [PATCH v3 3/3] target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type Date: Tue, 9 Mar 2021 17:29:17 -0700 Message-Id: <20210310002917.8876-4-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210310002917.8876-1-rebecca@nuviainc.com> References: <20210310002917.8876-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::12f; envelope-from=rebecca@nuviainc.com; helo=mail-il1-x12f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @nuviainc-com.20150623.gappssmtp.com) Content-Type: text/plain; charset="utf-8" Indicate support for FEAT_TLBIOS and FEAT_TLBIRANGE by setting ID_AA64ISAR0.TLB to 2 for the max AARCH64 CPU type. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson --- target/arm/cpu64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f0a9e968c9c1..e34a6a6174fe 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -651,6 +651,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); cpu->isar.id_aa64isar0 =3D t; =20 --=20 2.26.2