Introduce decodetree structure to decode the tx79 opcodes.
Start it by moving the existing MFHI1 and MFLO1 opcodes.
Remove unnecessary comments.
As the TX79 share opcodes with the TX19/TX39/TX49 CPUs,
we introduce the decode_ext_txx9() dispatcher where we
will add the other decoders later.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.h | 4 ++++
target/mips/tx79.decode | 25 ++++++++++++++++++++++++
target/mips/translate.c | 15 +++------------
target/mips/tx79_translate.c | 37 ++++++++++++++++++++++++++++++++++++
target/mips/txx9_translate.c | 20 +++++++++++++++++++
target/mips/meson.build | 5 +++++
6 files changed, 94 insertions(+), 12 deletions(-)
create mode 100644 target/mips/tx79.decode
create mode 100644 target/mips/tx79_translate.c
create mode 100644 target/mips/txx9_translate.c
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 468e29d7578..bc91ac4f53f 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -181,5 +181,9 @@ void msa_translate_init(void);
/* decodetree generated */
bool decode_isa_rel6(DisasContext *ctx, uint32_t insn);
bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
+bool decode_ext_txx9(DisasContext *ctx, uint32_t insn);
+#if defined(TARGET_MIPS64)
+bool decode_ext_tx79(DisasContext *ctx, uint32_t insn);
+#endif
#endif
diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
new file mode 100644
index 00000000000..2e287ebbf36
--- /dev/null
+++ b/target/mips/tx79.decode
@@ -0,0 +1,25 @@
+# Toshiba C790's instruction set
+#
+# Copyright (C) 2021 Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Toshiba Appendix B C790-Specific Instruction Set Details
+
+###########################################################################
+# Named attribute sets. These are used to make nice(er) names
+# when creating helpers common to those for the individual
+# instruction patterns.
+
+&rtype rs rt rd sa
+
+###########################################################################
+# Named instruction formats. These are generally used to
+# reduce the amount of duplication between instruction patterns.
+
+@rd ...... .......... rd:5 ..... ...... &rtype rs=0 rt=0 sa=0
+
+###########################################################################
+
+MFHI1 011100 0000000000 ..... 00000 010000 @rd
+MFLO1 011100 0000000000 ..... 00000 010010 @rd
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a2994eb0aa6..de67e534121 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1973,9 +1973,7 @@ enum {
MMI_OPC_PLZCW = 0x04 | MMI_OPC_CLASS_MMI,
MMI_OPC_CLASS_MMI0 = 0x08 | MMI_OPC_CLASS_MMI,
MMI_OPC_CLASS_MMI2 = 0x09 | MMI_OPC_CLASS_MMI,
- MMI_OPC_MFHI1 = 0x10 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MFHI */
MMI_OPC_MTHI1 = 0x11 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MTHI */
- MMI_OPC_MFLO1 = 0x12 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MFLO */
MMI_OPC_MTLO1 = 0x13 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MTLO */
MMI_OPC_MULT1 = 0x18 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MULT */
MMI_OPC_MULTU1 = 0x19 | MMI_OPC_CLASS_MMI, /* Same min. as OPC_MULTU */
@@ -4127,12 +4125,6 @@ static void gen_shift(DisasContext *ctx, uint32_t opc,
static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg)
{
switch (opc) {
- case MMI_OPC_MFHI1:
- gen_store_gpr(cpu_HI[1], reg);
- break;
- case MMI_OPC_MFLO1:
- gen_store_gpr(cpu_LO[1], reg);
- break;
case MMI_OPC_MTHI1:
gen_load_gpr(cpu_HI[1], reg);
break;
@@ -28027,10 +28019,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_MTHI1:
gen_HILO1_tx79(ctx, opc, rs);
break;
- case MMI_OPC_MFLO1:
- case MMI_OPC_MFHI1:
- gen_HILO1_tx79(ctx, opc, rd);
- break;
case MMI_OPC_PLZCW: /* TODO: MMI_OPC_PLZCW */
case MMI_OPC_PMFHL: /* TODO: MMI_OPC_PMFHL */
case MMI_OPC_PMTHL: /* TODO: MMI_OPC_PMTHL */
@@ -28997,6 +28985,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx, ctx->opcode)) {
return;
}
+ if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opcode)) {
+ return;
+ }
if (decode_opc_legacy(env, ctx)) {
return;
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
new file mode 100644
index 00000000000..22bd6033e55
--- /dev/null
+++ b/target/mips/tx79_translate.c
@@ -0,0 +1,37 @@
+/*
+ * Toshiba TX79-specific instructions translation routines
+ *
+ * Copyright (c) 2018 Fredrik Noring
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "tcg/tcg-op.h"
+#include "exec/helper-gen.h"
+#include "translate.h"
+
+/* Include the auto-generated decoder. */
+#include "decode-tx79.c.inc"
+
+bool decode_ext_tx79(DisasContext *ctx, uint32_t insn)
+{
+ if (TARGET_LONG_BITS == 64 && decode_tx79(ctx, insn)) {
+ return true;
+ }
+ return false;
+}
+
+static bool trans_MFHI1(DisasContext *ctx, arg_rtype *a)
+{
+ gen_store_gpr(cpu_HI[1], a->rd);
+
+ return true;
+}
+
+static bool trans_MFLO1(DisasContext *ctx, arg_rtype *a)
+{
+ gen_store_gpr(cpu_LO[1], a->rd);
+
+ return true;
+}
diff --git a/target/mips/txx9_translate.c b/target/mips/txx9_translate.c
new file mode 100644
index 00000000000..8a2c0b766bd
--- /dev/null
+++ b/target/mips/txx9_translate.c
@@ -0,0 +1,20 @@
+/*
+ * Toshiba TXx9 instructions translation routines
+ *
+ * Copyright (c) 2021 Philippe Mathieu-Daudé
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "translate.h"
+
+bool decode_ext_txx9(DisasContext *ctx, uint32_t insn)
+{
+#if defined(TARGET_MIPS64)
+ if (decode_ext_tx79(ctx, insn)) {
+ return true;
+ }
+#endif
+ return false;
+}
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 9741545440c..8836978e24a 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -3,6 +3,7 @@
decodetree.process('mips64r6.decode', extra_args: '--static-decode=decode_mips64r6'),
decodetree.process('msa32.decode', extra_args: '--static-decode=decode_msa32'),
decodetree.process('msa64.decode', extra_args: '--static-decode=decode_msa64'),
+ decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
]
mips_ss = ss.source_set()
@@ -22,6 +23,10 @@
'tlb_helper.c',
'translate.c',
'translate_addr_const.c',
+ 'txx9_translate.c',
+))
+mips_ss.add(when: ['CONFIG_TCG', 'TARGET_MIPS64'], if_true: files(
+ 'tx79_translate.c',
))
mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
--
2.26.2