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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id 101sm10400133wrk.4.2021.02.14.09.59.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 09:59:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vZITEFgnUYwtQ6EJ1PixPBWXKAXmo7nnSQHi00WvakQ=; b=vQsBjiW7CRjK08z7P4rllTClsVDtXur9JOMQnpdrS8/dObG3aQkq2IO2DQJFSlgObO 7f3/9kR7IQ/pr/eCJqR2l/ZeQPrOsaYZEDjoZEXk62KsJVERORHvnfF7i+UGk10FswAe BTgeDX3ZGB6E75oqaOZX6bzpxtu38eAl+SOpHZkv9Hmv5mJPbFfKqCBAwttStmX7xXBZ 793BGfLqZzaipo97u2VTnZCIXdkEqZbsWSnoBkxRhmrm2+hmAtVp6tO22icncD2ZuKZu YXY7/BhyboZySaOU1Uhbs6XPyTt7BpvorQa+zza1yytKZH/XPoDPsMdJT26NKA7Z/zfG mfBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=vZITEFgnUYwtQ6EJ1PixPBWXKAXmo7nnSQHi00WvakQ=; b=Sobh7iW4SNgh5eiUs0WpBpNOqDSaZ6adiXAGWIFhnGNZTAKB4oZJlsNgZR4Ru6RLQv EfV9AF/36GH5cmdoK0mUNw1mWt5lVG0UfmmkPJTw3O8f54bovVV4mpBZ7LIoCtJhV+vZ RCiGnPm0dMVUB9zgJY4sWK4yLSChR+DboH81KJhXMmFDh3l94CRnk10glTloHkUmIVWy 5QKwg/eV2PfNYNh1ixONVJyyaDqGJuIJG17NKORYLfTI3dr50qf40CHB5x91G6RP7fNs DBnwP/9Naaa9heul9jTnrWtaAzEDXkt1n9TTAOC4PL8xs8kaD3WC29SbkCAkBJPzWP3B Yfvw== X-Gm-Message-State: AOAM532XJjhwVdoUHWr6MR3Zlx6YUHxa1dEI5HPKD81Bo9khJkLdB+hz 3wmVpvb8Kx9yoPEbkYJJ1nI= X-Google-Smtp-Source: ABdhPJzcI3vEpDgj2pJIZnb/xr/hgIApmWNL51uOLWyRGLP6qnLPiYxpSmTf550rCD+YsLqQbqghCg== X-Received: by 2002:adf:80c3:: with SMTP id 61mr14818227wrl.100.1613325595054; Sun, 14 Feb 2021 09:59:55 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Fredrik Noring , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Maciej W. Rozycki" , Thomas Huth , Aurelien Jarno , Richard Henderson , Aleksandar Rikalo Subject: [RFC PATCH 08/42] target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree Date: Sun, 14 Feb 2021 18:58:38 +0100 Message-Id: <20210214175912.732946-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Introduce decodetree structure to decode the tx79 opcodes. Start it by moving the existing MFHI1 and MFLO1 opcodes. Remove unnecessary comments. As the TX79 share opcodes with the TX19/TX39/TX49 CPUs, we introduce the decode_ext_txx9() dispatcher where we will add the other decoders later. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/translate.h | 4 ++++ target/mips/tx79.decode | 25 ++++++++++++++++++++++++ target/mips/translate.c | 15 +++------------ target/mips/tx79_translate.c | 37 ++++++++++++++++++++++++++++++++++++ target/mips/txx9_translate.c | 20 +++++++++++++++++++ target/mips/meson.build | 5 +++++ 6 files changed, 94 insertions(+), 12 deletions(-) create mode 100644 target/mips/tx79.decode create mode 100644 target/mips/tx79_translate.c create mode 100644 target/mips/txx9_translate.c diff --git a/target/mips/translate.h b/target/mips/translate.h index 468e29d7578..bc91ac4f53f 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -181,5 +181,9 @@ void msa_translate_init(void); /* decodetree generated */ bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); bool decode_ase_msa(DisasContext *ctx, uint32_t insn); +bool decode_ext_txx9(DisasContext *ctx, uint32_t insn); +#if defined(TARGET_MIPS64) +bool decode_ext_tx79(DisasContext *ctx, uint32_t insn); +#endif =20 #endif diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode new file mode 100644 index 00000000000..2e287ebbf36 --- /dev/null +++ b/target/mips/tx79.decode @@ -0,0 +1,25 @@ +# Toshiba C790's instruction set +# +# Copyright (C) 2021 Philippe Mathieu-Daud=C3=A9 +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Toshiba Appendix B C790-Specific Instruction Set Details + +########################################################################### +# Named attribute sets. These are used to make nice(er) names +# when creating helpers common to those for the individual +# instruction patterns. + +&rtype rs rt rd sa + +########################################################################### +# Named instruction formats. These are generally used to +# reduce the amount of duplication between instruction patterns. + +@rd ...... .......... rd:5 ..... ...... &rtype rs=3D0 rt= =3D0 sa=3D0 + +########################################################################### + +MFHI1 011100 0000000000 ..... 00000 010000 @rd +MFLO1 011100 0000000000 ..... 00000 010010 @rd diff --git a/target/mips/translate.c b/target/mips/translate.c index a2994eb0aa6..de67e534121 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1973,9 +1973,7 @@ enum { MMI_OPC_PLZCW =3D 0x04 | MMI_OPC_CLASS_MMI, MMI_OPC_CLASS_MMI0 =3D 0x08 | MMI_OPC_CLASS_MMI, MMI_OPC_CLASS_MMI2 =3D 0x09 | MMI_OPC_CLASS_MMI, - MMI_OPC_MFHI1 =3D 0x10 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_= MFHI */ MMI_OPC_MTHI1 =3D 0x11 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_= MTHI */ - MMI_OPC_MFLO1 =3D 0x12 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_= MFLO */ MMI_OPC_MTLO1 =3D 0x13 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_= MTLO */ MMI_OPC_MULT1 =3D 0x18 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_= MULT */ MMI_OPC_MULTU1 =3D 0x19 | MMI_OPC_CLASS_MMI, /* Same min. as OPC_M= ULTU */ @@ -4127,12 +4125,6 @@ static void gen_shift(DisasContext *ctx, uint32_t op= c, static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg) { switch (opc) { - case MMI_OPC_MFHI1: - gen_store_gpr(cpu_HI[1], reg); - break; - case MMI_OPC_MFLO1: - gen_store_gpr(cpu_LO[1], reg); - break; case MMI_OPC_MTHI1: gen_load_gpr(cpu_HI[1], reg); break; @@ -28027,10 +28019,6 @@ static void decode_mmi(CPUMIPSState *env, DisasCon= text *ctx) case MMI_OPC_MTHI1: gen_HILO1_tx79(ctx, opc, rs); break; - case MMI_OPC_MFLO1: - case MMI_OPC_MFHI1: - gen_HILO1_tx79(ctx, opc, rd); - break; case MMI_OPC_PLZCW: /* TODO: MMI_OPC_PLZCW */ case MMI_OPC_PMFHL: /* TODO: MMI_OPC_PMFHL */ case MMI_OPC_PMTHL: /* TODO: MMI_OPC_PMTHL */ @@ -28997,6 +28985,9 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx, ctx->op= code)) { return; } + if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opc= ode)) { + return; + } =20 if (decode_opc_legacy(env, ctx)) { return; diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c new file mode 100644 index 00000000000..22bd6033e55 --- /dev/null +++ b/target/mips/tx79_translate.c @@ -0,0 +1,37 @@ +/* + * Toshiba TX79-specific instructions translation routines + * + * Copyright (c) 2018 Fredrik Noring + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "exec/helper-gen.h" +#include "translate.h" + +/* Include the auto-generated decoder. */ +#include "decode-tx79.c.inc" + +bool decode_ext_tx79(DisasContext *ctx, uint32_t insn) +{ + if (TARGET_LONG_BITS =3D=3D 64 && decode_tx79(ctx, insn)) { + return true; + } + return false; +} + +static bool trans_MFHI1(DisasContext *ctx, arg_rtype *a) +{ + gen_store_gpr(cpu_HI[1], a->rd); + + return true; +} + +static bool trans_MFLO1(DisasContext *ctx, arg_rtype *a) +{ + gen_store_gpr(cpu_LO[1], a->rd); + + return true; +} diff --git a/target/mips/txx9_translate.c b/target/mips/txx9_translate.c new file mode 100644 index 00000000000..8a2c0b766bd --- /dev/null +++ b/target/mips/txx9_translate.c @@ -0,0 +1,20 @@ +/* + * Toshiba TXx9 instructions translation routines + * + * Copyright (c) 2021 Philippe Mathieu-Daud=C3=A9 + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "translate.h" + +bool decode_ext_txx9(DisasContext *ctx, uint32_t insn) +{ +#if defined(TARGET_MIPS64) + if (decode_ext_tx79(ctx, insn)) { + return true; + } +#endif + return false; +} diff --git a/target/mips/meson.build b/target/mips/meson.build index 9741545440c..8836978e24a 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -3,6 +3,7 @@ decodetree.process('mips64r6.decode', extra_args: '--static-decode=3Ddec= ode_mips64r6'), decodetree.process('msa32.decode', extra_args: '--static-decode=3Ddecode= _msa32'), decodetree.process('msa64.decode', extra_args: '--static-decode=3Ddecode= _msa64'), + decodetree.process('tx79.decode', extra_args: '--static-decode=3Ddecode_= tx79'), ] =20 mips_ss =3D ss.source_set() @@ -22,6 +23,10 @@ 'tlb_helper.c', 'translate.c', 'translate_addr_const.c', + 'txx9_translate.c', +)) +mips_ss.add(when: ['CONFIG_TCG', 'TARGET_MIPS64'], if_true: files( + 'tx79_translate.c', )) mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 --=20 2.26.2