[PULL 00/21] target-arm queue
[PULL 00/24] target-arm queue
1
Mostly just bug fixes. The important one here is
1
Hi; here's the latest round of arm patches. I have included also
2
hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
2
my patchset for the RTC devices to avoid keeping time_t and
3
which fixes a buffer overrun that's a security issue if you're running
3
time_t diffs in 32-bit variables.
4
KVM on Arm with kernel-irqchip=off (which hopefully nobody is doing in
5
a security context, because kernel-irqchip=on is the default and the
6
sensible choice for performance).
7
4
5
thanks
8
-- PMM
6
-- PMM
9
7
10
The following changes since commit cf7ca7d5b9faca13f1f8e3ea92cfb2f741eb0c0e:
8
The following changes since commit 156618d9ea67f2f2e31d9dedd97f2dcccbe6808c:
11
9
12
Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/tracing-pull-request' into staging (2021-02-01 16:28:00 +0000)
10
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-08-30 09:20:27 -0400)
13
11
14
are available in the Git repository at:
12
are available in the Git repository at:
15
13
16
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210202-1
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230831
17
15
18
for you to fetch changes up to 14657850c9cc10948551fbb884c30eb5a3a7370a:
16
for you to fetch changes up to e73b8bb8a3e9a162f70e9ffbf922d4fafc96bbfb:
19
17
20
hw/arm: Display CPU type in machine description (2021-02-02 17:53:44 +0000)
18
hw/arm: Set number of MPU regions correctly for an505, an521, an524 (2023-08-31 11:07:02 +0100)
21
19
22
----------------------------------------------------------------
20
----------------------------------------------------------------
23
target-arm queue:
21
target-arm queue:
24
* hw/intc/arm_gic: Allow to use QTest without crashing
22
* Some of the preliminary patches for Cortex-A710 support
25
* hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled
23
* i.MX7 and i.MX6UL refactoring
26
* hw/char/exynos4210_uart: Fix missing call to report ready for input
24
* Implement SRC device for i.MX7
27
* hw/arm/smmuv3: Fix addr_mask for range-based invalidation
25
* Catch illegal-exception-return from EL3 with bad NSE/NS
28
* hw/ssi/imx_spi: Fix various minor bugs
26
* Use 64-bit offsets for holding time_t differences in RTC devices
29
* hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
27
* Model correct number of MPU regions for an505, an521, an524 boards
30
* hw/arm: Add missing Kconfig dependencies
31
* hw/arm: Display CPU type in machine description
32
28
33
----------------------------------------------------------------
29
----------------------------------------------------------------
34
Bin Meng (5):
30
Alex Bennée (1):
35
hw/ssi: imx_spi: Use a macro for number of chip selects supported
31
target/arm: properly document FEAT_CRC32
36
hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset()
37
hw/ssi: imx_spi: Round up the burst length to be multiple of 8
38
hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic
39
hw/ssi: imx_spi: Correct tx and rx fifo endianness
40
32
41
Iris Johnson (2):
33
Jean-Christophe Dubois (6):
42
hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled
34
Remove i.MX7 IOMUX GPR device from i.MX6UL
43
hw/char/exynos4210_uart: Fix missing call to report ready for input
35
Refactor i.MX6UL processor code
36
Add i.MX6UL missing devices.
37
Refactor i.MX7 processor code
38
Add i.MX7 missing TZ devices and memory regions
39
Add i.MX7 SRC device implementation
44
40
45
Philippe Mathieu-Daudé (12):
41
Peter Maydell (8):
46
hw/intc/arm_gic: Allow to use QTest without crashing
42
target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS
47
hw/ssi: imx_spi: Remove pointless variable initialization
43
hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()
48
hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value
44
hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec
49
hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled
45
hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference
50
hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled
46
rtc: Use time_t for passing and returning time offsets
51
hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
47
target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init
52
hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ
48
hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties
53
hw/arm/exynos4210: Add missing dependency on OR_IRQ
49
hw/arm: Set number of MPU regions correctly for an505, an521, an524
54
hw/arm/xlnx-versal: Versal SoC requires ZDMA
55
hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals
56
hw/net/can: ZynqMP CAN device requires PTIMER
57
hw/arm: Display CPU type in machine description
58
50
59
Xuzhou Cheng (1):
51
Richard Henderson (9):
60
hw/ssi: imx_spi: Disable chip selects when controller is disabled
52
target/arm: Reduce dcz_blocksize to uint8_t
53
target/arm: Allow cpu to configure GM blocksize
54
target/arm: Support more GM blocksizes
55
target/arm: When tag memory is not present, set MTE=1
56
target/arm: Introduce make_ccsidr64
57
target/arm: Apply access checks to neoverse-n1 special registers
58
target/arm: Apply access checks to neoverse-v1 special registers
59
target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)
60
target/arm: Implement FEAT_HPDS2 as a no-op
61
61
62
Zenghui Yu (1):
62
docs/system/arm/emulation.rst | 2 +
63
hw/arm/smmuv3: Fix addr_mask for range-based invalidation
63
include/hw/arm/armsse.h | 5 +
64
include/hw/arm/armv7m.h | 8 +
65
include/hw/arm/fsl-imx6ul.h | 158 ++++++++++++++++---
66
include/hw/arm/fsl-imx7.h | 338 ++++++++++++++++++++++++++++++-----------
67
include/hw/misc/imx7_src.h | 66 ++++++++
68
include/hw/rtc/aspeed_rtc.h | 2 +-
69
include/sysemu/rtc.h | 4 +-
70
target/arm/cpregs.h | 2 +
71
target/arm/cpu.h | 5 +-
72
target/arm/internals.h | 6 -
73
target/arm/tcg/translate.h | 2 +
74
hw/arm/armsse.c | 16 ++
75
hw/arm/armv7m.c | 21 +++
76
hw/arm/fsl-imx6ul.c | 174 +++++++++++++--------
77
hw/arm/fsl-imx7.c | 201 +++++++++++++++++++-----
78
hw/arm/mps2-tz.c | 29 ++++
79
hw/misc/imx7_src.c | 276 +++++++++++++++++++++++++++++++++
80
hw/rtc/aspeed_rtc.c | 5 +-
81
hw/rtc/m48t59.c | 2 +-
82
hw/rtc/twl92230.c | 4 +-
83
softmmu/rtc.c | 4 +-
84
target/arm/cpu.c | 207 ++++++++++++++-----------
85
target/arm/helper.c | 15 +-
86
target/arm/tcg/cpu32.c | 2 +-
87
target/arm/tcg/cpu64.c | 102 +++++++++----
88
target/arm/tcg/helper-a64.c | 9 ++
89
target/arm/tcg/mte_helper.c | 90 ++++++++---
90
target/arm/tcg/translate-a64.c | 5 +-
91
hw/misc/meson.build | 1 +
92
hw/misc/trace-events | 4 +
93
31 files changed, 1393 insertions(+), 372 deletions(-)
94
create mode 100644 include/hw/misc/imx7_src.h
95
create mode 100644 hw/misc/imx7_src.c
64
96
65
include/hw/ssi/imx_spi.h | 5 +-
66
hw/arm/digic_boards.c | 2 +-
67
hw/arm/microbit.c | 2 +-
68
hw/arm/netduino2.c | 2 +-
69
hw/arm/netduinoplus2.c | 2 +-
70
hw/arm/orangepi.c | 2 +-
71
hw/arm/smmuv3.c | 4 +-
72
hw/arm/stellaris.c | 4 +-
73
hw/char/exynos4210_uart.c | 7 ++-
74
hw/intc/arm_gic.c | 5 +-
75
hw/ssi/imx_spi.c | 153 +++++++++++++++++++++++++++++-----------------
76
hw/Kconfig | 1 +
77
hw/arm/Kconfig | 5 ++
78
hw/dma/Kconfig | 3 +
79
hw/dma/meson.build | 2 +-
80
15 files changed, 130 insertions(+), 69 deletions(-)
81
diff view generated by jsdifflib
[PULL 15/21] hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
[PULL 01/24] target/arm: Reduce dcz_blocksize to uint8_t
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Per the ARM Generic Interrupt Controller Architecture specification
3
This value is only 4 bits wide.
4
(document "ARM IHI 0048B.b (ID072613)"), the SGIINTID field is 4 bit,
5
not 10:
6
4
7
- 4.3 Distributor register descriptions
8
- 4.3.15 Software Generated Interrupt Register, GICD_SG
9
10
- Table 4-21 GICD_SGIR bit assignments
11
12
The Interrupt ID of the SGI to forward to the specified CPU
13
interfaces. The value of this field is the Interrupt ID, in
14
the range 0-15, for example a value of 0b0011 specifies
15
Interrupt ID 3.
16
17
Correct the irq mask to fix an undefined behavior (which eventually
18
lead to a heap-buffer-overflow, see [Buglink]):
19
20
$ echo 'writel 0x8000f00 0xff4affb0' | qemu-system-aarch64 -M virt,accel=qtest -qtest stdio
21
[I 1612088147.116987] OPENED
22
[R +0.278293] writel 0x8000f00 0xff4affb0
23
../hw/intc/arm_gic.c:1498:13: runtime error: index 944 out of bounds for type 'uint8_t [16][8]'
24
SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior ../hw/intc/arm_gic.c:1498:13
25
26
This fixes a security issue when running with KVM on Arm with
27
kernel-irqchip=off. (The default is kernel-irqchip=on, which is
28
unaffected, and which is also the correct choice for performance.)
29
30
Cc: qemu-stable@nongnu.org
31
Fixes: 9ee6e8bb853 ("ARMv7 support.")
32
Buglink: https://bugs.launchpad.net/qemu/+bug/1913916
33
Buglink: https://bugs.launchpad.net/qemu/+bug/1913917
34
Reported-by: Alexander Bulekov <alxndr@bu.edu>
35
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
36
Message-id: 20210131103401.217160-1-f4bug@amsat.org
37
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20230811214031.171020-2-richard.henderson@linaro.org
38
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
39
---
10
---
40
hw/intc/arm_gic.c | 2 +-
11
target/arm/cpu.h | 3 ++-
41
1 file changed, 1 insertion(+), 1 deletion(-)
12
1 file changed, 2 insertions(+), 1 deletion(-)
42
13
43
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
44
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/intc/arm_gic.c
16
--- a/target/arm/cpu.h
46
+++ b/hw/intc/arm_gic.c
17
+++ b/target/arm/cpu.h
47
@@ -XXX,XX +XXX,XX @@ static void gic_dist_writel(void *opaque, hwaddr offset,
18
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
48
int target_cpu;
19
bool prop_lpa2;
49
20
50
cpu = gic_get_current_cpu(s);
21
/* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
51
- irq = value & 0x3ff;
22
- uint32_t dcz_blocksize;
52
+ irq = value & 0xf;
23
+ uint8_t dcz_blocksize;
53
switch ((value >> 24) & 3) {
24
+
54
case 0:
25
uint64_t rvbar_prop; /* Property/input signals. */
55
mask = (value >> 16) & ALL_CPU_MASK;
26
27
/* Configurable aspects of GIC cpu interface (which is part of the CPU) */
56
--
28
--
57
2.20.1
29
2.34.1
58
30
59
31
diff view generated by jsdifflib
[PULL 09/21] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled
[PULL 02/24] target/arm: Allow cpu to configure GM blocksize
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
When the block is disabled, it stay it is 'internal reset logic'
3
Previously we hard-coded the blocksize with GMID_EL1_BS.
4
(internal clocks are gated off). Reading any register returns
4
But the value we choose for -cpu max does not match the
5
its reset value. Only update this value if the device is enabled.
5
value that cortex-a710 uses.
6
6
7
Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM),
7
Mirror the way we handle dcz_blocksize.
8
chapter 21.7.3: Control Register (ECSPIx_CONREG)
8
9
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Juan Quintela <quintela@redhat.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20230811214031.171020-3-richard.henderson@linaro.org
12
Reviewed-by: Bin Meng <bin.meng@windriver.com>
13
Signed-off-by: Bin Meng <bin.meng@windriver.com>
14
Message-id: 20210129132323.30946-6-bmeng.cn@gmail.com
15
Message-Id: <20210115153049.3353008-5-f4bug@amsat.org>
16
Reviewed-by: Bin Meng <bin.meng@windriver.com>
17
Signed-off-by: Bin Meng <bin.meng@windriver.com>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
13
---
20
hw/ssi/imx_spi.c | 60 +++++++++++++++++++++++-------------------------
14
target/arm/cpu.h | 2 ++
21
1 file changed, 29 insertions(+), 31 deletions(-)
15
target/arm/internals.h | 6 -----
22
16
target/arm/tcg/translate.h | 2 ++
23
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
17
target/arm/helper.c | 11 +++++---
24
index XXXXXXX..XXXXXXX 100644
18
target/arm/tcg/cpu64.c | 1 +
25
--- a/hw/ssi/imx_spi.c
19
target/arm/tcg/mte_helper.c | 46 ++++++++++++++++++++++------------
26
+++ b/hw/ssi/imx_spi.c
20
target/arm/tcg/translate-a64.c | 5 ++--
27
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
21
7 files changed, 45 insertions(+), 28 deletions(-)
22
23
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/cpu.h
26
+++ b/target/arm/cpu.h
27
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
28
29
/* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
30
uint8_t dcz_blocksize;
31
+ /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */
32
+ uint8_t gm_blocksize;
33
34
uint64_t rvbar_prop; /* Property/input signals. */
35
36
diff --git a/target/arm/internals.h b/target/arm/internals.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/internals.h
39
+++ b/target/arm/internals.h
40
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs);
41
42
#endif /* !CONFIG_USER_ONLY */
43
44
-/*
45
- * The log2 of the words in the tag block, for GMID_EL1.BS.
46
- * The is the maximum, 256 bytes, which manipulates 64-bits of tags.
47
- */
48
-#define GMID_EL1_BS 6
49
-
50
/*
51
* SVE predicates are 1/8 the size of SVE vectors, and cannot use
52
* the same simd_desc() encoding due to restrictions on size.
53
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
54
index XXXXXXX..XXXXXXX 100644
55
--- a/target/arm/tcg/translate.h
56
+++ b/target/arm/tcg/translate.h
57
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
58
int8_t btype;
59
/* A copy of cpu->dcz_blocksize. */
60
uint8_t dcz_blocksize;
61
+ /* A copy of cpu->gm_blocksize. */
62
+ uint8_t gm_blocksize;
63
/* True if this page is guarded. */
64
bool guarded_page;
65
/* Bottom two bits of XScale c15_cpar coprocessor access control reg */
66
diff --git a/target/arm/helper.c b/target/arm/helper.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/arm/helper.c
69
+++ b/target/arm/helper.c
70
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
71
.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6,
72
.access = PL1_RW, .accessfn = access_mte,
73
.fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) },
74
- { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
75
- .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
76
- .access = PL1_R, .accessfn = access_aa64_tid5,
77
- .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS },
78
{ .name = "TCO", .state = ARM_CP_STATE_AA64,
79
.opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
80
.type = ARM_CP_NO_RAW,
81
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
82
* then define only a RAZ/WI version of PSTATE.TCO.
83
*/
84
if (cpu_isar_feature(aa64_mte, cpu)) {
85
+ ARMCPRegInfo gmid_reginfo = {
86
+ .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
87
+ .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
88
+ .access = PL1_R, .accessfn = access_aa64_tid5,
89
+ .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize,
90
+ };
91
+ define_one_arm_cp_reg(cpu, &gmid_reginfo);
92
define_arm_cp_regs(cpu, mte_reginfo);
93
define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
94
} else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) {
95
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
96
index XXXXXXX..XXXXXXX 100644
97
--- a/target/arm/tcg/cpu64.c
98
+++ b/target/arm/tcg/cpu64.c
99
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
100
cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
101
cpu->dcz_blocksize = 7; /* 512 bytes */
102
#endif
103
+ cpu->gm_blocksize = 6; /* 256 bytes */
104
105
cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
106
cpu->sme_vq.supported = SVE_VQ_POW2_MAP;
107
diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
108
index XXXXXXX..XXXXXXX 100644
109
--- a/target/arm/tcg/mte_helper.c
110
+++ b/target/arm/tcg/mte_helper.c
111
@@ -XXX,XX +XXX,XX @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr)
112
}
113
}
114
115
-#define LDGM_STGM_SIZE (4 << GMID_EL1_BS)
116
-
117
uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
118
{
119
int mmu_idx = cpu_mmu_index(env, false);
120
uintptr_t ra = GETPC();
121
+ int gm_bs = env_archcpu(env)->gm_blocksize;
122
+ int gm_bs_bytes = 4 << gm_bs;
123
void *tag_mem;
124
125
- ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
126
+ ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
127
128
/* Trap if accessing an invalid page. */
129
tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD,
130
- LDGM_STGM_SIZE, MMU_DATA_LOAD,
131
- LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
132
+ gm_bs_bytes, MMU_DATA_LOAD,
133
+ gm_bs_bytes / (2 * TAG_GRANULE), ra);
134
135
/* The tag is squashed to zero if the page does not support tags. */
136
if (!tag_mem) {
28
return 0;
137
return 0;
29
}
138
}
30
139
31
- switch (index) {
140
- QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
32
- case ECSPI_RXDATA:
141
/*
33
- if (!imx_spi_is_enabled(s)) {
142
- * We are loading 64-bits worth of tags. The ordering of elements
34
- value = 0;
143
- * within the word corresponds to a 64-bit little-endian operation.
35
- } else if (fifo32_is_empty(&s->rx_fifo)) {
144
+ * The ordering of elements within the word corresponds to
36
- /* value is undefined */
145
+ * a little-endian operation.
37
- value = 0xdeadbeef;
146
*/
38
- } else {
147
- return ldq_le_p(tag_mem);
39
- /* read from the RX FIFO */
148
+ switch (gm_bs) {
40
- value = fifo32_pop(&s->rx_fifo);
149
+ case 6:
41
+ value = s->regs[index];
150
+ /* 256 bytes -> 16 tags -> 64 result bits */
42
+
151
+ return ldq_le_p(tag_mem);
43
+ if (imx_spi_is_enabled(s)) {
152
+ default:
44
+ switch (index) {
153
+ /* cpu configured with unsupported gm blocksize. */
45
+ case ECSPI_RXDATA:
154
+ g_assert_not_reached();
46
+ if (fifo32_is_empty(&s->rx_fifo)) {
155
+ }
47
+ /* value is undefined */
156
}
48
+ value = 0xdeadbeef;
157
49
+ } else {
158
void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
50
+ /* read from the RX FIFO */
159
{
51
+ value = fifo32_pop(&s->rx_fifo);
160
int mmu_idx = cpu_mmu_index(env, false);
52
+ }
161
uintptr_t ra = GETPC();
53
+ break;
162
+ int gm_bs = env_archcpu(env)->gm_blocksize;
54
+ case ECSPI_TXDATA:
163
+ int gm_bs_bytes = 4 << gm_bs;
55
+ qemu_log_mask(LOG_GUEST_ERROR,
164
void *tag_mem;
56
+ "[%s]%s: Trying to read from TX FIFO\n",
165
57
+ TYPE_IMX_SPI, __func__);
166
- ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
58
+
167
+ ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
59
+ /* Reading from TXDATA gives 0 */
168
60
+ break;
169
/* Trap if accessing an invalid page. */
61
+ case ECSPI_MSGDATA:
170
tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE,
62
+ qemu_log_mask(LOG_GUEST_ERROR,
171
- LDGM_STGM_SIZE, MMU_DATA_LOAD,
63
+ "[%s]%s: Trying to read from MSG FIFO\n",
172
- LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
64
+ TYPE_IMX_SPI, __func__);
173
+ gm_bs_bytes, MMU_DATA_LOAD,
65
+ /* Reading from MSGDATA gives 0 */
174
+ gm_bs_bytes / (2 * TAG_GRANULE), ra);
66
+ break;
175
67
+ default:
176
/*
68
+ break;
177
* Tag store only happens if the page support tags,
69
}
178
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
70
179
return;
71
- break;
72
- case ECSPI_TXDATA:
73
- qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from TX FIFO\n",
74
- TYPE_IMX_SPI, __func__);
75
-
76
- /* Reading from TXDATA gives 0 */
77
-
78
- break;
79
- case ECSPI_MSGDATA:
80
- qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from MSG FIFO\n",
81
- TYPE_IMX_SPI, __func__);
82
-
83
- /* Reading from MSGDATA gives 0 */
84
-
85
- break;
86
- default:
87
- value = s->regs[index];
88
- break;
89
+ imx_spi_update_irq(s);
90
}
180
}
91
-
181
92
DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_spi_reg_name(index), value);
182
- QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
93
183
/*
94
- imx_spi_update_irq(s);
184
- * We are storing 64-bits worth of tags. The ordering of elements
95
-
185
- * within the word corresponds to a 64-bit little-endian operation.
96
return (uint64_t)value;
186
+ * The ordering of elements within the word corresponds to
187
+ * a little-endian operation.
188
*/
189
- stq_le_p(tag_mem, val);
190
+ switch (gm_bs) {
191
+ case 6:
192
+ stq_le_p(tag_mem, val);
193
+ break;
194
+ default:
195
+ /* cpu configured with unsupported gm blocksize. */
196
+ g_assert_not_reached();
197
+ }
97
}
198
}
98
199
200
void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val)
201
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
202
index XXXXXXX..XXXXXXX 100644
203
--- a/target/arm/tcg/translate-a64.c
204
+++ b/target/arm/tcg/translate-a64.c
205
@@ -XXX,XX +XXX,XX @@ static bool trans_STGM(DisasContext *s, arg_ldst_tag *a)
206
gen_helper_stgm(cpu_env, addr, tcg_rt);
207
} else {
208
MMUAccessType acc = MMU_DATA_STORE;
209
- int size = 4 << GMID_EL1_BS;
210
+ int size = 4 << s->gm_blocksize;
211
212
clean_addr = clean_data_tbi(s, addr);
213
tcg_gen_andi_i64(clean_addr, clean_addr, -size);
214
@@ -XXX,XX +XXX,XX @@ static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a)
215
gen_helper_ldgm(tcg_rt, cpu_env, addr);
216
} else {
217
MMUAccessType acc = MMU_DATA_LOAD;
218
- int size = 4 << GMID_EL1_BS;
219
+ int size = 4 << s->gm_blocksize;
220
221
clean_addr = clean_data_tbi(s, addr);
222
tcg_gen_andi_i64(clean_addr, clean_addr, -size);
223
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
224
dc->cp_regs = arm_cpu->cp_regs;
225
dc->features = env->features;
226
dc->dcz_blocksize = arm_cpu->dcz_blocksize;
227
+ dc->gm_blocksize = arm_cpu->gm_blocksize;
228
229
#ifdef CONFIG_USER_ONLY
230
/* In sve_probe_page, we assume TBI is enabled. */
99
--
231
--
100
2.20.1
232
2.34.1
101
102
diff view generated by jsdifflib
[PULL 07/21] hw/ssi: imx_spi: Remove pointless variable initialization
[PULL 03/24] target/arm: Support more GM blocksizes
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
'burst_length' is cleared in imx_spi_reset(), which is called
3
Support all of the easy GM block sizes.
4
after imx_spi_realize(). Remove the initialization to simplify.
4
Use direct memory operations, since the pointers are aligned.
5
5
6
Reviewed-by: Juan Quintela <quintela@redhat.com>
6
While BS=2 (16 bytes, 1 tag) is a legal setting, that requires
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
an atomic store of one nibble. This is not difficult, but there
8
Reviewed-by: Bin Meng <bin.meng@windriver.com>
8
is also no point in supporting it until required.
9
Signed-off-by: Bin Meng <bin.meng@windriver.com>
9
10
Message-id: 20210129132323.30946-4-bmeng.cn@gmail.com
10
Note that cortex-a710 sets GM blocksize to match its cacheline
11
Message-Id: <20210115153049.3353008-3-f4bug@amsat.org>
11
size of 64 bytes. I expect many implementations will also
12
Reviewed-by: Bin Meng <bin.meng@windriver.com>
12
match the cacheline, which makes 16 bytes very unlikely.
13
Signed-off-by: Bin Meng <bin.meng@windriver.com>
13
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Message-id: 20230811214031.171020-4-richard.henderson@linaro.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
18
---
16
hw/ssi/imx_spi.c | 2 --
19
target/arm/cpu.c | 18 +++++++++---
17
1 file changed, 2 deletions(-)
20
target/arm/tcg/mte_helper.c | 56 +++++++++++++++++++++++++++++++------
21
2 files changed, 62 insertions(+), 12 deletions(-)
18
22
19
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
23
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
20
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/ssi/imx_spi.c
25
--- a/target/arm/cpu.c
22
+++ b/hw/ssi/imx_spi.c
26
+++ b/target/arm/cpu.c
23
@@ -XXX,XX +XXX,XX @@ static void imx_spi_realize(DeviceState *dev, Error **errp)
27
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
24
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]);
28
ID_PFR1, VIRTUALIZATION, 0);
25
}
29
}
26
30
27
- s->burst_length = 0;
31
+ if (cpu_isar_feature(aa64_mte, cpu)) {
28
-
32
+ /*
29
fifo32_create(&s->tx_fifo, ECSPI_FIFO_SIZE);
33
+ * The architectural range of GM blocksize is 2-6, however qemu
30
fifo32_create(&s->rx_fifo, ECSPI_FIFO_SIZE);
34
+ * doesn't support blocksize of 2 (see HELPER(ldgm)).
35
+ */
36
+ if (tcg_enabled()) {
37
+ assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6);
38
+ }
39
+
40
#ifndef CONFIG_USER_ONLY
41
- if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) {
42
/*
43
* Disable the MTE feature bits if we do not have tag-memory
44
* provided by the machine.
45
*/
46
- cpu->isar.id_aa64pfr1 =
47
- FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
48
- }
49
+ if (cpu->tag_memory == NULL) {
50
+ cpu->isar.id_aa64pfr1 =
51
+ FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
52
+ }
53
#endif
54
+ }
55
56
if (tcg_enabled()) {
57
/*
58
diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/tcg/mte_helper.c
61
+++ b/target/arm/tcg/mte_helper.c
62
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
63
int gm_bs = env_archcpu(env)->gm_blocksize;
64
int gm_bs_bytes = 4 << gm_bs;
65
void *tag_mem;
66
+ uint64_t ret;
67
+ int shift;
68
69
ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
70
71
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
72
73
/*
74
* The ordering of elements within the word corresponds to
75
- * a little-endian operation.
76
+ * a little-endian operation. Computation of shift comes from
77
+ *
78
+ * index = address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE>
79
+ * data<index*4+3:index*4> = tag
80
+ *
81
+ * Because of the alignment of ptr above, BS=6 has shift=0.
82
+ * All memory operations are aligned. Defer support for BS=2,
83
+ * requiring insertion or extraction of a nibble, until we
84
+ * support a cpu that requires it.
85
*/
86
switch (gm_bs) {
87
+ case 3:
88
+ /* 32 bytes -> 2 tags -> 8 result bits */
89
+ ret = *(uint8_t *)tag_mem;
90
+ break;
91
+ case 4:
92
+ /* 64 bytes -> 4 tags -> 16 result bits */
93
+ ret = cpu_to_le16(*(uint16_t *)tag_mem);
94
+ break;
95
+ case 5:
96
+ /* 128 bytes -> 8 tags -> 32 result bits */
97
+ ret = cpu_to_le32(*(uint32_t *)tag_mem);
98
+ break;
99
case 6:
100
/* 256 bytes -> 16 tags -> 64 result bits */
101
- return ldq_le_p(tag_mem);
102
+ return cpu_to_le64(*(uint64_t *)tag_mem);
103
default:
104
- /* cpu configured with unsupported gm blocksize. */
105
+ /*
106
+ * CPU configured with unsupported/invalid gm blocksize.
107
+ * This is detected early in arm_cpu_realizefn.
108
+ */
109
g_assert_not_reached();
110
}
111
+ shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
112
+ return ret << shift;
31
}
113
}
114
115
void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
116
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
117
int gm_bs = env_archcpu(env)->gm_blocksize;
118
int gm_bs_bytes = 4 << gm_bs;
119
void *tag_mem;
120
+ int shift;
121
122
ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
123
124
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
125
return;
126
}
127
128
- /*
129
- * The ordering of elements within the word corresponds to
130
- * a little-endian operation.
131
- */
132
+ /* See LDGM for comments on BS and on shift. */
133
+ shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
134
+ val >>= shift;
135
switch (gm_bs) {
136
+ case 3:
137
+ /* 32 bytes -> 2 tags -> 8 result bits */
138
+ *(uint8_t *)tag_mem = val;
139
+ break;
140
+ case 4:
141
+ /* 64 bytes -> 4 tags -> 16 result bits */
142
+ *(uint16_t *)tag_mem = cpu_to_le16(val);
143
+ break;
144
+ case 5:
145
+ /* 128 bytes -> 8 tags -> 32 result bits */
146
+ *(uint32_t *)tag_mem = cpu_to_le32(val);
147
+ break;
148
case 6:
149
- stq_le_p(tag_mem, val);
150
+ /* 256 bytes -> 16 tags -> 64 result bits */
151
+ *(uint64_t *)tag_mem = cpu_to_le64(val);
152
break;
153
default:
154
/* cpu configured with unsupported gm blocksize. */
32
--
155
--
33
2.20.1
156
2.34.1
34
35
diff view generated by jsdifflib
New patch
[PULL 04/24] target/arm: When tag memory is not present, set MTE=1
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
When the cpu support MTE, but the system does not, reduce cpu
4
support to user instructions at EL0 instead of completely
5
disabling MTE. If we encounter a cpu implementation which does
6
something else, we can revisit this setting.
7
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20230811214031.171020-5-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/cpu.c | 7 ++++---
14
1 file changed, 4 insertions(+), 3 deletions(-)
15
16
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.c
19
+++ b/target/arm/cpu.c
20
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
21
22
#ifndef CONFIG_USER_ONLY
23
/*
24
- * Disable the MTE feature bits if we do not have tag-memory
25
- * provided by the machine.
26
+ * If we do not have tag-memory provided by the machine,
27
+ * reduce MTE support to instructions enabled at EL0.
28
+ * This matches Cortex-A710 BROADCASTMTE input being LOW.
29
*/
30
if (cpu->tag_memory == NULL) {
31
cpu->isar.id_aa64pfr1 =
32
- FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
33
+ FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
34
}
35
#endif
36
}
37
--
38
2.34.1
diff view generated by jsdifflib
[PULL 21/21] hw/arm: Display CPU type in machine description
[PULL 05/24] target/arm: Introduce make_ccsidr64
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Most of ARM machines display their CPU when QEMU list the available
3
Do not hard-code the constants for Neoverse V1.
4
machines (-M help). Some machines do not. Fix to unify the help
5
output.
6
4
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20210131184449.382425-7-f4bug@amsat.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20230811214031.171020-6-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
9
---
14
hw/arm/digic_boards.c | 2 +-
10
target/arm/tcg/cpu64.c | 48 ++++++++++++++++++++++++++++--------------
15
hw/arm/microbit.c | 2 +-
11
1 file changed, 32 insertions(+), 16 deletions(-)
16
hw/arm/netduino2.c | 2 +-
17
hw/arm/netduinoplus2.c | 2 +-
18
hw/arm/orangepi.c | 2 +-
19
hw/arm/stellaris.c | 4 ++--
20
6 files changed, 7 insertions(+), 7 deletions(-)
21
12
22
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
13
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
23
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/arm/digic_boards.c
15
--- a/target/arm/tcg/cpu64.c
25
+++ b/hw/arm/digic_boards.c
16
+++ b/target/arm/tcg/cpu64.c
26
@@ -XXX,XX +XXX,XX @@ static void canon_a1100_init(MachineState *machine)
17
@@ -XXX,XX +XXX,XX @@
27
18
#include "qemu/module.h"
28
static void canon_a1100_machine_init(MachineClass *mc)
19
#include "qapi/visitor.h"
20
#include "hw/qdev-properties.h"
21
+#include "qemu/units.h"
22
#include "internals.h"
23
#include "cpregs.h"
24
25
+static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize,
26
+ unsigned cachesize)
27
+{
28
+ unsigned lg_linesize = ctz32(linesize);
29
+ unsigned sets;
30
+
31
+ /*
32
+ * The 64-bit CCSIDR_EL1 format is:
33
+ * [55:32] number of sets - 1
34
+ * [23:3] associativity - 1
35
+ * [2:0] log2(linesize) - 4
36
+ * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
37
+ */
38
+ assert(assoc != 0);
39
+ assert(is_power_of_2(linesize));
40
+ assert(lg_linesize >= 4 && lg_linesize <= 7 + 4);
41
+
42
+ /* sets * associativity * linesize == cachesize. */
43
+ sets = cachesize / (assoc * linesize);
44
+ assert(cachesize % (assoc * linesize) == 0);
45
+
46
+ return ((uint64_t)(sets - 1) << 32)
47
+ | ((assoc - 1) << 3)
48
+ | (lg_linesize - 4);
49
+}
50
+
51
static void aarch64_a35_initfn(Object *obj)
29
{
52
{
30
- mc->desc = "Canon PowerShot A1100 IS";
53
ARMCPU *cpu = ARM_CPU(obj);
31
+ mc->desc = "Canon PowerShot A1100 IS (ARM946)";
54
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj)
32
mc->init = &canon_a1100_init;
55
* The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values,
33
mc->ignore_memory_transaction_failures = true;
56
* but also says it implements CCIDX, which means they should be
34
mc->default_ram_size = 64 * MiB;
57
* 64-bit format. So we here use values which are based on the textual
35
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
58
- * information in chapter 2 of the TRM (and on the fact that
36
index XXXXXXX..XXXXXXX 100644
59
- * sets * associativity * linesize == cachesize).
37
--- a/hw/arm/microbit.c
60
- *
38
+++ b/hw/arm/microbit.c
61
- * The 64-bit CCSIDR_EL1 format is:
39
@@ -XXX,XX +XXX,XX @@ static void microbit_machine_class_init(ObjectClass *oc, void *data)
62
- * [55:32] number of sets - 1
40
{
63
- * [23:3] associativity - 1
41
MachineClass *mc = MACHINE_CLASS(oc);
64
- * [2:0] log2(linesize) - 4
42
65
- * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
43
- mc->desc = "BBC micro:bit";
66
- *
44
+ mc->desc = "BBC micro:bit (Cortex-M0)";
67
- * L1: 4-way set associative 64-byte line size, total size 64K,
45
mc->init = microbit_init;
68
- * so sets is 256.
46
mc->max_cpus = 1;
69
+ * information in chapter 2 of the TRM:
47
}
70
*
48
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
71
+ * L1: 4-way set associative 64-byte line size, total size 64K.
49
index XXXXXXX..XXXXXXX 100644
72
* L2: 8-way set associative, 64 byte line size, either 512K or 1MB.
50
--- a/hw/arm/netduino2.c
73
- * We pick 1MB, so this has 2048 sets.
51
+++ b/hw/arm/netduino2.c
74
- *
52
@@ -XXX,XX +XXX,XX @@ static void netduino2_init(MachineState *machine)
75
* L3: No L3 (this matches the CLIDR_EL1 value).
53
76
*/
54
static void netduino2_machine_init(MachineClass *mc)
77
- cpu->ccsidr[0] = 0x000000ff0000001aull; /* 64KB L1 dcache */
55
{
78
- cpu->ccsidr[1] = 0x000000ff0000001aull; /* 64KB L1 icache */
56
- mc->desc = "Netduino 2 Machine";
79
- cpu->ccsidr[2] = 0x000007ff0000003aull; /* 1MB L2 cache */
57
+ mc->desc = "Netduino 2 Machine (Cortex-M3)";
80
+ cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */
58
mc->init = netduino2_init;
81
+ cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */
59
mc->ignore_memory_transaction_failures = true;
82
+ cpu->ccsidr[2] = make_ccsidr64(8, 64, 1 * MiB); /* L2 cache */
60
}
83
61
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
84
/* From 3.2.115 SCTLR_EL3 */
62
index XXXXXXX..XXXXXXX 100644
85
cpu->reset_sctlr = 0x30c50838;
63
--- a/hw/arm/netduinoplus2.c
64
+++ b/hw/arm/netduinoplus2.c
65
@@ -XXX,XX +XXX,XX @@ static void netduinoplus2_init(MachineState *machine)
66
67
static void netduinoplus2_machine_init(MachineClass *mc)
68
{
69
- mc->desc = "Netduino Plus 2 Machine";
70
+ mc->desc = "Netduino Plus 2 Machine (Cortex-M4)";
71
mc->init = netduinoplus2_init;
72
}
73
74
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
75
index XXXXXXX..XXXXXXX 100644
76
--- a/hw/arm/orangepi.c
77
+++ b/hw/arm/orangepi.c
78
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
79
80
static void orangepi_machine_init(MachineClass *mc)
81
{
82
- mc->desc = "Orange Pi PC";
83
+ mc->desc = "Orange Pi PC (Cortex-A7)";
84
mc->init = orangepi_init;
85
mc->block_default_type = IF_SD;
86
mc->units_per_default_bus = 1;
87
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
88
index XXXXXXX..XXXXXXX 100644
89
--- a/hw/arm/stellaris.c
90
+++ b/hw/arm/stellaris.c
91
@@ -XXX,XX +XXX,XX @@ static void lm3s811evb_class_init(ObjectClass *oc, void *data)
92
{
93
MachineClass *mc = MACHINE_CLASS(oc);
94
95
- mc->desc = "Stellaris LM3S811EVB";
96
+ mc->desc = "Stellaris LM3S811EVB (Cortex-M3)";
97
mc->init = lm3s811evb_init;
98
mc->ignore_memory_transaction_failures = true;
99
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
100
@@ -XXX,XX +XXX,XX @@ static void lm3s6965evb_class_init(ObjectClass *oc, void *data)
101
{
102
MachineClass *mc = MACHINE_CLASS(oc);
103
104
- mc->desc = "Stellaris LM3S6965EVB";
105
+ mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)";
106
mc->init = lm3s6965evb_init;
107
mc->ignore_memory_transaction_failures = true;
108
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
109
--
86
--
110
2.20.1
87
2.34.1
111
112
diff view generated by jsdifflib
[PULL 08/21] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value
[PULL 06/24] target/arm: Apply access checks to neoverse-n1 special registers
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
When the block is disabled, all registers are reset with the
3
Access to many of the special registers is enabled or disabled
4
exception of the ECSPI_CONREG. It is initialized to zero
4
by ACTLR_EL[23], which we implement as constant 0, which means
5
when the instance is created.
5
that all writes outside EL3 should trap.
6
6
7
Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM),
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
chapter 21.7.3: Control Register (ECSPIx_CONREG)
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
9
Message-id: 20230811214031.171020-7-richard.henderson@linaro.org
10
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Signed-off-by: Bin Meng <bin.meng@windriver.com>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20210129132323.30946-5-bmeng.cn@gmail.com
14
[bmeng: add a 'common_reset' function that does most of reset operation]
15
Signed-off-by: Bin Meng <bin.meng@windriver.com>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
11
---
18
hw/ssi/imx_spi.c | 32 ++++++++++++++++++++++++--------
12
target/arm/cpregs.h | 2 ++
19
1 file changed, 24 insertions(+), 8 deletions(-)
13
target/arm/helper.c | 4 ++--
14
target/arm/tcg/cpu64.c | 46 +++++++++++++++++++++++++++++++++---------
15
3 files changed, 41 insertions(+), 11 deletions(-)
20
16
21
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
17
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
22
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/ssi/imx_spi.c
19
--- a/target/arm/cpregs.h
24
+++ b/hw/ssi/imx_spi.c
20
+++ b/target/arm/cpregs.h
25
@@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
21
@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
26
fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo));
22
void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
23
#endif
24
25
+CPAccessResult access_tvm_trvm(CPUARMState *, const ARMCPRegInfo *, bool);
26
+
27
#endif /* TARGET_ARM_CPREGS_H */
28
diff --git a/target/arm/helper.c b/target/arm/helper.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/helper.c
31
+++ b/target/arm/helper.c
32
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
27
}
33
}
28
34
29
-static void imx_spi_reset(DeviceState *dev)
35
/* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
30
+static void imx_spi_common_reset(IMXSPIState *s)
36
-static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
37
- bool isread)
38
+CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
39
+ bool isread)
31
{
40
{
32
- IMXSPIState *s = IMX_SPI(dev);
41
if (arm_current_el(env) == 1) {
33
+ int i;
42
uint64_t trap = isread ? HCR_TRVM : HCR_TVM;
34
43
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
35
- DPRINTF("\n");
44
index XXXXXXX..XXXXXXX 100644
36
-
45
--- a/target/arm/tcg/cpu64.c
37
- memset(s->regs, 0, sizeof(s->regs));
46
+++ b/target/arm/tcg/cpu64.c
38
-
47
@@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj)
39
- s->regs[ECSPI_STATREG] = 0x00000003;
48
/* TODO: Add A64FX specific HPC extension registers */
40
+ for (i = 0; i < ARRAY_SIZE(s->regs); i++) {
49
}
41
+ switch (i) {
50
42
+ case ECSPI_CONREG:
51
+static CPAccessResult access_actlr_w(CPUARMState *env, const ARMCPRegInfo *r,
43
+ /* CONREG is not updated on soft reset */
52
+ bool read)
44
+ break;
53
+{
45
+ case ECSPI_STATREG:
54
+ if (!read) {
46
+ s->regs[i] = 0x00000003;
55
+ int el = arm_current_el(env);
47
+ break;
56
+
48
+ default:
57
+ /* Because ACTLR_EL2 is constant 0, writes below EL2 trap to EL2. */
49
+ s->regs[i] = 0;
58
+ if (el < 2 && arm_is_el2_enabled(env)) {
50
+ break;
59
+ return CP_ACCESS_TRAP_EL2;
60
+ }
61
+ /* Because ACTLR_EL3 is constant 0, writes below EL3 trap to EL3. */
62
+ if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) {
63
+ return CP_ACCESS_TRAP_EL3;
51
+ }
64
+ }
52
+ }
65
+ }
53
66
+ return CP_ACCESS_OK;
54
imx_spi_rxfifo_reset(s);
55
imx_spi_txfifo_reset(s);
56
@@ -XXX,XX +XXX,XX @@ static void imx_spi_reset(DeviceState *dev)
57
58
static void imx_spi_soft_reset(IMXSPIState *s)
59
{
60
- imx_spi_reset(DEVICE(s));
61
+ imx_spi_common_reset(s);
62
63
imx_spi_update_irq(s);
64
}
65
66
+static void imx_spi_reset(DeviceState *dev)
67
+{
68
+ IMXSPIState *s = IMX_SPI(dev);
69
+
70
+ imx_spi_common_reset(s);
71
+ s->regs[ECSPI_CONREG] = 0;
72
+}
67
+}
73
+
68
+
74
static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
69
static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
75
{
70
{ .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
76
uint32_t value = 0;
71
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
72
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
73
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
74
+ /* Traps and enables are the same as for TCR_EL1. */
75
+ .accessfn = access_tvm_trvm, .fgt = FGT_TCR_EL1, },
76
{ .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
77
.opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
78
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
79
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
80
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
81
{ .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
82
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
83
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
84
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
85
+ .accessfn = access_actlr_w },
86
{ .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64,
87
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
88
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
89
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
90
+ .accessfn = access_actlr_w },
91
{ .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64,
92
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
93
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
94
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
95
+ .accessfn = access_actlr_w },
96
/*
97
* Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
98
* (and in particular its system registers).
99
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
100
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
101
{ .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
102
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
103
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 },
104
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010,
105
+ .accessfn = access_actlr_w },
106
{ .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64,
107
.opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1,
108
.access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
109
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
110
.access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
111
{ .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64,
112
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
113
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
114
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
115
+ .accessfn = access_actlr_w },
116
{ .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64,
117
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2,
118
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
119
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
120
+ .accessfn = access_actlr_w },
121
{ .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64,
122
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1,
123
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
124
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
125
+ .accessfn = access_actlr_w },
126
{ .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64,
127
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
128
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
129
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
130
+ .accessfn = access_actlr_w },
131
};
132
133
static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
77
--
134
--
78
2.20.1
135
2.34.1
79
80
diff view generated by jsdifflib
[PULL 01/21] hw/intc/arm_gic: Allow to use QTest without crashing
[PULL 07/24] target/arm: Apply access checks to neoverse-v1 special registers
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Alexander reported an issue in gic_get_current_cpu() using the
3
There is only one additional EL1 register modeled, which
4
fuzzer. Yet another "deref current_cpu with QTest" bug, reproducible
4
also needs to use access_actlr_w.
5
doing:
6
5
7
$ echo readb 0xf03ff000 | qemu-system-arm -M npcm750-evb,accel=qtest -qtest stdio
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
[I 1611849440.651452] OPENED
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
[R +0.242498] readb 0xf03ff000
8
Message-id: 20230811214031.171020-8-richard.henderson@linaro.org
10
hw/intc/arm_gic.c:63:29: runtime error: member access within null pointer of type 'CPUState' (aka 'struct CPUState')
11
SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior hw/intc/arm_gic.c:63:29 in
12
AddressSanitizer:DEADLYSIGNAL
13
=================================================================
14
==3719691==ERROR: AddressSanitizer: SEGV on unknown address 0x0000000082a0 (pc 0x5618790ac882 bp 0x7ffca946f4f0 sp 0x7ffca946f4a0 T0)
15
==3719691==The signal is caused by a READ memory access.
16
#0 0x5618790ac882 in gic_get_current_cpu hw/intc/arm_gic.c:63:29
17
#1 0x5618790a8901 in gic_dist_readb hw/intc/arm_gic.c:955:11
18
#2 0x5618790a7489 in gic_dist_read hw/intc/arm_gic.c:1158:17
19
#3 0x56187adc573b in memory_region_read_with_attrs_accessor softmmu/memory.c:464:9
20
#4 0x56187ad7903a in access_with_adjusted_size softmmu/memory.c:552:18
21
#5 0x56187ad766d6 in memory_region_dispatch_read1 softmmu/memory.c:1426:16
22
#6 0x56187ad758a8 in memory_region_dispatch_read softmmu/memory.c:1449:9
23
#7 0x56187b09e84c in flatview_read_continue softmmu/physmem.c:2822:23
24
#8 0x56187b0a0115 in flatview_read softmmu/physmem.c:2862:12
25
#9 0x56187b09fc9e in address_space_read_full softmmu/physmem.c:2875:18
26
#10 0x56187aa88633 in address_space_read include/exec/memory.h:2489:18
27
#11 0x56187aa88633 in qtest_process_command softmmu/qtest.c:558:13
28
#12 0x56187aa81881 in qtest_process_inbuf softmmu/qtest.c:797:9
29
#13 0x56187aa80e02 in qtest_read softmmu/qtest.c:809:5
30
31
current_cpu is NULL because QTest accelerator does not use CPU.
32
33
Fix by skipping the check and returning the first CPU index when
34
QTest accelerator is used, similarly to commit c781a2cc423
35
("hw/i386/vmport: Allow QTest use without crashing").
36
37
Reported-by: Alexander Bulekov <alxndr@bu.edu>
38
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
39
Reviewed-by: Darren Kenny <darren.kenny@oracle.com>
40
Reviewed-by: Alexander Bulekov <alxndr@bu.edu>
41
Message-id: 20210128161417.3726358-1-philmd@redhat.com
42
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
43
---
10
---
44
hw/intc/arm_gic.c | 3 ++-
11
target/arm/tcg/cpu64.c | 3 ++-
45
1 file changed, 2 insertions(+), 1 deletion(-)
12
1 file changed, 2 insertions(+), 1 deletion(-)
46
13
47
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
14
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
48
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
49
--- a/hw/intc/arm_gic.c
16
--- a/target/arm/tcg/cpu64.c
50
+++ b/hw/intc/arm_gic.c
17
+++ b/target/arm/tcg/cpu64.c
51
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
52
#include "qemu/module.h"
19
static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = {
53
#include "trace.h"
20
{ .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64,
54
#include "sysemu/kvm.h"
21
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5,
55
+#include "sysemu/qtest.h"
22
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
56
23
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
57
/* #define DEBUG_GIC */
24
+ .accessfn = access_actlr_w },
58
25
{ .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64,
59
@@ -XXX,XX +XXX,XX @@ static const uint8_t gic_id_gicv2[] = {
26
.opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0,
60
27
.access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
61
static inline int gic_get_current_cpu(GICState *s)
62
{
63
- if (s->num_cpu > 1) {
64
+ if (!qtest_enabled() && s->num_cpu > 1) {
65
return current_cpu->cpu_index;
66
}
67
return 0;
68
--
28
--
69
2.20.1
29
2.34.1
70
71
diff view generated by jsdifflib
New patch
[PULL 08/24] target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Like FEAT_TRF (Self-hosted Trace Extension), suppress tracing
4
external to the cpu, which is out of scope for QEMU.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20230811214031.171020-10-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/cpu.c | 3 +++
12
1 file changed, 3 insertions(+)
13
14
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.c
17
+++ b/target/arm/cpu.c
18
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
19
/* FEAT_SPE (Statistical Profiling Extension) */
20
cpu->isar.id_aa64dfr0 =
21
FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
22
+ /* FEAT_TRBE (Trace Buffer Extension) */
23
+ cpu->isar.id_aa64dfr0 =
24
+ FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0);
25
/* FEAT_TRF (Self-hosted Trace Extension) */
26
cpu->isar.id_aa64dfr0 =
27
FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0);
28
--
29
2.34.1
diff view generated by jsdifflib
[PULL 20/21] hw/net/can: ZynqMP CAN device requires PTIMER
[PULL 09/24] target/arm: Implement FEAT_HPDS2 as a no-op
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Add a dependency XLNX_ZYNQMP -> PTIMER to fix:
3
This feature allows the operating system to set TCR_ELx.HWU*
4
to allow the implementation to use the PBHA bits from the
5
block and page descriptors for for IMPLEMENTATION DEFINED
6
purposes. Since QEMU has no need to use these bits, we may
7
simply ignore them.
4
8
5
/usr/bin/ld:
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
libcommon.fa.p/hw_net_can_xlnx-zynqmp-can.c.o: in function `xlnx_zynqmp_can_realize':
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
hw/net/can/xlnx-zynqmp-can.c:1082: undefined reference to `ptimer_init'
11
Message-id: 20230811214031.171020-11-richard.henderson@linaro.org
8
hw/net/can/xlnx-zynqmp-can.c:1085: undefined reference to `ptimer_transaction_begin'
9
hw/net/can/xlnx-zynqmp-can.c:1087: undefined reference to `ptimer_set_freq'
10
hw/net/can/xlnx-zynqmp-can.c:1088: undefined reference to `ptimer_set_limit'
11
hw/net/can/xlnx-zynqmp-can.c:1089: undefined reference to `ptimer_run'
12
hw/net/can/xlnx-zynqmp-can.c:1090: undefined reference to `ptimer_transaction_commit'
13
libcommon.fa.p/hw_net_can_xlnx-zynqmp-can.c.o:(.data.rel+0x2c8): undefined reference to `vmstate_ptimer'
14
15
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
16
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
17
Message-id: 20210131184449.382425-6-f4bug@amsat.org
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
13
---
20
hw/Kconfig | 1 +
14
docs/system/arm/emulation.rst | 1 +
21
1 file changed, 1 insertion(+)
15
target/arm/tcg/cpu32.c | 2 +-
16
target/arm/tcg/cpu64.c | 2 +-
17
3 files changed, 3 insertions(+), 2 deletions(-)
22
18
23
diff --git a/hw/Kconfig b/hw/Kconfig
19
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
24
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/Kconfig
21
--- a/docs/system/arm/emulation.rst
26
+++ b/hw/Kconfig
22
+++ b/docs/system/arm/emulation.rst
27
@@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP
23
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
28
bool
24
- FEAT_HAFDBS (Hardware management of the access flag and dirty bit state)
29
select REGISTER
25
- FEAT_HCX (Support for the HCRX_EL2 register)
30
select CAN_BUS
26
- FEAT_HPDS (Hierarchical permission disables)
31
+ select PTIMER
27
+- FEAT_HPDS2 (Translation table page-based hardware attributes)
28
- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
29
- FEAT_IDST (ID space trap handling)
30
- FEAT_IESB (Implicit error synchronization event)
31
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/tcg/cpu32.c
34
+++ b/target/arm/tcg/cpu32.c
35
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
36
cpu->isar.id_mmfr3 = t;
37
38
t = cpu->isar.id_mmfr4;
39
- t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */
40
+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */
41
t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
42
t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
43
t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */
44
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/tcg/cpu64.c
47
+++ b/target/arm/tcg/cpu64.c
48
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
49
t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */
50
t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
51
t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */
52
- t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */
53
+ t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2); /* FEAT_HPDS2 */
54
t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */
55
t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */
56
t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */
32
--
57
--
33
2.20.1
58
2.34.1
34
35
diff view generated by jsdifflib
[PULL 19/21] hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals
[PULL 10/24] target/arm: properly document FEAT_CRC32
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
The Versal SoC instantiates the TYPE_XLNX_ZYNQMP_RTC object in
3
This is a mandatory feature for Armv8.1 architectures but we don't
4
versal_create_rtc()(). Select CONFIG_XLNX_ZYNQMP to fix:
4
state the feature clearly in our emulation list. Also include
5
FEAT_CRC32 comment in aarch64_max_tcg_initfn for ease of grepping.
5
6
6
$ make check-qtest-aarch64
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
...
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Running test qtest-aarch64/qom-test
9
Message-id: 20230824075406.1515566-1-alex.bennee@linaro.org
9
qemu-system-aarch64: missing object type 'xlnx-zynmp.rtc'
10
Cc: qemu-stable@nongnu.org
10
Broken pipe
11
Message-Id: <20230222110104.3996971-1-alex.bennee@linaro.org>
11
12
[PMM: pluralize 'instructions' in docs]
12
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Message-id: 20210131184449.382425-5-f4bug@amsat.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
14
---
17
hw/arm/Kconfig | 1 +
15
docs/system/arm/emulation.rst | 1 +
18
1 file changed, 1 insertion(+)
16
target/arm/tcg/cpu64.c | 2 +-
17
2 files changed, 2 insertions(+), 1 deletion(-)
19
18
20
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
19
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
21
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/Kconfig
21
--- a/docs/system/arm/emulation.rst
23
+++ b/hw/arm/Kconfig
22
+++ b/docs/system/arm/emulation.rst
24
@@ -XXX,XX +XXX,XX @@ config XLNX_VERSAL
23
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
25
select VIRTIO_MMIO
24
- FEAT_BBM at level 2 (Translation table break-before-make levels)
26
select UNIMP
25
- FEAT_BF16 (AArch64 BFloat16 instructions)
27
select XLNX_ZDMA
26
- FEAT_BTI (Branch Target Identification)
28
+ select XLNX_ZYNQMP
27
+- FEAT_CRC32 (CRC32 instructions)
29
28
- FEAT_CSV2 (Cache speculation variant 2)
30
config NPCM7XX
29
- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
31
bool
30
- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
31
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/tcg/cpu64.c
34
+++ b/target/arm/tcg/cpu64.c
35
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
36
t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */
37
t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */
38
t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */
39
- t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
40
+ t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* FEAT_CRC32 */
41
t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */
42
t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */
43
t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */
32
--
44
--
33
2.20.1
45
2.34.1
34
46
35
47
diff view generated by jsdifflib
[PULL 17/21] hw/arm/exynos4210: Add missing dependency on OR_IRQ
[PULL 11/24] Remove i.MX7 IOMUX GPR device from i.MX6UL
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
2
3
The Exynos4210 SoC uses an OR gate on the PL330 IRQ lines.
3
i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device.
4
In particular, register 22 is not present on i.MX6UL and this is actualy
5
The only register that is really emulated in the i.MX7 IOMUX GPR device.
4
6
5
Fixes: dab15fbe2ab ("hw/arm/exynos4210: Fix DMA initialization")
7
Note: The i.MX6UL code is actually also implementing the IOMUX GPR device
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
as an unimplemented device at the same bus adress and the 2 instantiations
7
Message-id: 20210131184449.382425-3-f4bug@amsat.org
9
were actualy colliding. So we go back to the unimplemented device for now.
10
11
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
12
Message-id: 48681bf51ee97646479bb261bee19abebbc8074e.1692964892.git.jcd@tribudubois.net
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
15
---
11
hw/arm/Kconfig | 1 +
16
include/hw/arm/fsl-imx6ul.h | 2 --
12
1 file changed, 1 insertion(+)
17
hw/arm/fsl-imx6ul.c | 11 -----------
18
2 files changed, 13 deletions(-)
13
19
14
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
20
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
15
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/Kconfig
22
--- a/include/hw/arm/fsl-imx6ul.h
17
+++ b/hw/arm/Kconfig
23
+++ b/include/hw/arm/fsl-imx6ul.h
18
@@ -XXX,XX +XXX,XX @@ config EXYNOS4
24
@@ -XXX,XX +XXX,XX @@
19
select PTIMER
25
#include "hw/misc/imx6ul_ccm.h"
20
select SDHCI
26
#include "hw/misc/imx6_src.h"
21
select USB_EHCI_SYSBUS
27
#include "hw/misc/imx7_snvs.h"
22
+ select OR_IRQ
28
-#include "hw/misc/imx7_gpr.h"
23
29
#include "hw/intc/imx_gpcv2.h"
24
config HIGHBANK
30
#include "hw/watchdog/wdt_imx2.h"
25
bool
31
#include "hw/gpio/imx_gpio.h"
32
@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
33
IMX6SRCState src;
34
IMX7SNVSState snvs;
35
IMXGPCv2State gpcv2;
36
- IMX7GPRState gpr;
37
IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
38
IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
39
IMXSerialState uart[FSL_IMX6UL_NUM_UARTS];
40
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/arm/fsl-imx6ul.c
43
+++ b/hw/arm/fsl-imx6ul.c
44
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
45
*/
46
object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
47
48
- /*
49
- * GPR
50
- */
51
- object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
52
-
53
/*
54
* GPIOs 1 to 5
55
*/
56
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
57
FSL_IMX6UL_WDOGn_IRQ[i]));
58
}
59
60
- /*
61
- * GPR
62
- */
63
- sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
64
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR);
65
-
66
/*
67
* SDMA
68
*/
26
--
69
--
27
2.20.1
70
2.34.1
28
29
diff view generated by jsdifflib
[PULL 03/21] hw/char/exynos4210_uart: Fix missing call to report ready for input
[PULL 12/24] Refactor i.MX6UL processor code
1
From: Iris Johnson <iris@modwiz.com>
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
2
3
When the frontend device has no space for a read the fd is removed
3
* Add Addr and size definition for most i.MX6UL devices in i.MX6UL header file.
4
from polling to allow time for the guest to read and clear the buffer.
4
* Use those newly defined named constants whenever possible.
5
Without the call to qemu_chr_fe_accept_input(), the poll will not be
5
* Standardize the way we init a familly of unimplemented devices
6
broken out of when the guest has cleared the buffer causing significant
6
- SAI
7
IO delays that get worse with smaller buffers.
7
- PWM
8
- CAN
9
* Add/rework few comments
8
10
9
Buglink: https://bugs.launchpad.net/qemu/+bug/1913341
11
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
10
Signed-off-by: Iris Johnson <iris@modwiz.com>
12
Message-id: d579043fbd4e4b490370783fda43fc02c8e9be75.1692964892.git.jcd@tribudubois.net
11
Message-id: 20210130184016.1787097-1-iris@modwiz.com
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
---
15
hw/char/exynos4210_uart.c | 1 +
16
include/hw/arm/fsl-imx6ul.h | 156 +++++++++++++++++++++++++++++++-----
16
1 file changed, 1 insertion(+)
17
hw/arm/fsl-imx6ul.c | 147 ++++++++++++++++++++++-----------
18
2 files changed, 232 insertions(+), 71 deletions(-)
17
19
18
diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c
20
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
19
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/char/exynos4210_uart.c
22
--- a/include/hw/arm/fsl-imx6ul.h
21
+++ b/hw/char/exynos4210_uart.c
23
+++ b/include/hw/arm/fsl-imx6ul.h
22
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset,
24
@@ -XXX,XX +XXX,XX @@
23
s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;
25
#include "exec/memory.h"
24
res = s->reg[I_(URXH)];
26
#include "cpu.h"
25
}
27
#include "qom/object.h"
26
+ qemu_chr_fe_accept_input(&s->chr);
28
+#include "qemu/units.h"
27
exynos4210_uart_update_dmabusy(s);
29
28
trace_exynos_uart_read(s->channel, offset,
30
#define TYPE_FSL_IMX6UL "fsl-imx6ul"
29
exynos4210_uart_regname(offset), res);
31
OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6ULState, FSL_IMX6UL)
32
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
33
FSL_IMX6UL_NUM_ADCS = 2,
34
FSL_IMX6UL_NUM_USB_PHYS = 2,
35
FSL_IMX6UL_NUM_USBS = 2,
36
+ FSL_IMX6UL_NUM_SAIS = 3,
37
+ FSL_IMX6UL_NUM_CANS = 2,
38
+ FSL_IMX6UL_NUM_PWMS = 4,
39
};
40
41
struct FslIMX6ULState {
42
@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
43
44
enum FslIMX6ULMemoryMap {
45
FSL_IMX6UL_MMDC_ADDR = 0x80000000,
46
- FSL_IMX6UL_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL,
47
+ FSL_IMX6UL_MMDC_SIZE = (2 * GiB),
48
49
FSL_IMX6UL_QSPI1_MEM_ADDR = 0x60000000,
50
- FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000,
51
- FSL_IMX6UL_EIM_CS_ADDR = 0x50000000,
52
- FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000,
53
- FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000,
54
+ FSL_IMX6UL_QSPI1_MEM_SIZE = (256 * MiB),
55
56
- /* AIPS-2 */
57
+ FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000,
58
+ FSL_IMX6UL_EIM_ALIAS_SIZE = (128 * MiB),
59
+
60
+ FSL_IMX6UL_EIM_CS_ADDR = 0x50000000,
61
+ FSL_IMX6UL_EIM_CS_SIZE = (128 * MiB),
62
+
63
+ FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000,
64
+ FSL_IMX6UL_AES_ENCRYPT_SIZE = (1 * MiB),
65
+
66
+ FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000,
67
+ FSL_IMX6UL_QSPI1_RX_SIZE = (32 * MiB),
68
+
69
+ /* AIPS-2 Begin */
70
FSL_IMX6UL_UART6_ADDR = 0x021FC000,
71
+
72
FSL_IMX6UL_I2C4_ADDR = 0x021F8000,
73
+
74
FSL_IMX6UL_UART5_ADDR = 0x021F4000,
75
FSL_IMX6UL_UART4_ADDR = 0x021F0000,
76
FSL_IMX6UL_UART3_ADDR = 0x021EC000,
77
FSL_IMX6UL_UART2_ADDR = 0x021E8000,
78
+
79
FSL_IMX6UL_WDOG3_ADDR = 0x021E4000,
80
+
81
FSL_IMX6UL_QSPI_ADDR = 0x021E0000,
82
+ FSL_IMX6UL_QSPI_SIZE = 0x500,
83
+
84
FSL_IMX6UL_SYS_CNT_CTRL_ADDR = 0x021DC000,
85
+ FSL_IMX6UL_SYS_CNT_CTRL_SIZE = (16 * KiB),
86
+
87
FSL_IMX6UL_SYS_CNT_CMP_ADDR = 0x021D8000,
88
+ FSL_IMX6UL_SYS_CNT_CMP_SIZE = (16 * KiB),
89
+
90
FSL_IMX6UL_SYS_CNT_RD_ADDR = 0x021D4000,
91
+ FSL_IMX6UL_SYS_CNT_RD_SIZE = (16 * KiB),
92
+
93
FSL_IMX6UL_TZASC_ADDR = 0x021D0000,
94
+ FSL_IMX6UL_TZASC_SIZE = (16 * KiB),
95
+
96
FSL_IMX6UL_PXP_ADDR = 0x021CC000,
97
+ FSL_IMX6UL_PXP_SIZE = (16 * KiB),
98
+
99
FSL_IMX6UL_LCDIF_ADDR = 0x021C8000,
100
+ FSL_IMX6UL_LCDIF_SIZE = 0x100,
101
+
102
FSL_IMX6UL_CSI_ADDR = 0x021C4000,
103
+ FSL_IMX6UL_CSI_SIZE = 0x100,
104
+
105
FSL_IMX6UL_CSU_ADDR = 0x021C0000,
106
+ FSL_IMX6UL_CSU_SIZE = (16 * KiB),
107
+
108
FSL_IMX6UL_OCOTP_CTRL_ADDR = 0x021BC000,
109
+ FSL_IMX6UL_OCOTP_CTRL_SIZE = (4 * KiB),
110
+
111
FSL_IMX6UL_EIM_ADDR = 0x021B8000,
112
+ FSL_IMX6UL_EIM_SIZE = 0x100,
113
+
114
FSL_IMX6UL_SIM2_ADDR = 0x021B4000,
115
+
116
FSL_IMX6UL_MMDC_CFG_ADDR = 0x021B0000,
117
+ FSL_IMX6UL_MMDC_CFG_SIZE = (4 * KiB),
118
+
119
FSL_IMX6UL_ROMCP_ADDR = 0x021AC000,
120
+ FSL_IMX6UL_ROMCP_SIZE = 0x300,
121
+
122
FSL_IMX6UL_I2C3_ADDR = 0x021A8000,
123
FSL_IMX6UL_I2C2_ADDR = 0x021A4000,
124
FSL_IMX6UL_I2C1_ADDR = 0x021A0000,
125
+
126
FSL_IMX6UL_ADC2_ADDR = 0x0219C000,
127
FSL_IMX6UL_ADC1_ADDR = 0x02198000,
128
+ FSL_IMX6UL_ADCn_SIZE = 0x100,
129
+
130
FSL_IMX6UL_USDHC2_ADDR = 0x02194000,
131
FSL_IMX6UL_USDHC1_ADDR = 0x02190000,
132
- FSL_IMX6UL_SIM1_ADDR = 0x0218C000,
133
- FSL_IMX6UL_ENET1_ADDR = 0x02188000,
134
- FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800,
135
- FSL_IMX6UL_USBO2_USB_ADDR = 0x02184000,
136
- FSL_IMX6UL_USBO2_PL301_ADDR = 0x02180000,
137
- FSL_IMX6UL_AIPS2_CFG_ADDR = 0x0217C000,
138
- FSL_IMX6UL_CAAM_ADDR = 0x02140000,
139
- FSL_IMX6UL_A7MPCORE_DAP_ADDR = 0x02100000,
140
141
- /* AIPS-1 */
142
+ FSL_IMX6UL_SIM1_ADDR = 0x0218C000,
143
+ FSL_IMX6UL_SIMn_SIZE = (16 * KiB),
144
+
145
+ FSL_IMX6UL_ENET1_ADDR = 0x02188000,
146
+
147
+ FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800,
148
+ FSL_IMX6UL_USBO2_USB1_ADDR = 0x02184000,
149
+ FSL_IMX6UL_USBO2_USB2_ADDR = 0x02184200,
150
+
151
+ FSL_IMX6UL_USBO2_PL301_ADDR = 0x02180000,
152
+ FSL_IMX6UL_USBO2_PL301_SIZE = (16 * KiB),
153
+
154
+ FSL_IMX6UL_AIPS2_CFG_ADDR = 0x0217C000,
155
+ FSL_IMX6UL_AIPS2_CFG_SIZE = 0x100,
156
+
157
+ FSL_IMX6UL_CAAM_ADDR = 0x02140000,
158
+ FSL_IMX6UL_CAAM_SIZE = (16 * KiB),
159
+
160
+ FSL_IMX6UL_A7MPCORE_DAP_ADDR = 0x02100000,
161
+ FSL_IMX6UL_A7MPCORE_DAP_SIZE = (4 * KiB),
162
+ /* AIPS-2 End */
163
+
164
+ /* AIPS-1 Begin */
165
FSL_IMX6UL_PWM8_ADDR = 0x020FC000,
166
FSL_IMX6UL_PWM7_ADDR = 0x020F8000,
167
FSL_IMX6UL_PWM6_ADDR = 0x020F4000,
168
FSL_IMX6UL_PWM5_ADDR = 0x020F0000,
169
+
170
FSL_IMX6UL_SDMA_ADDR = 0x020EC000,
171
+ FSL_IMX6UL_SDMA_SIZE = 0x300,
172
+
173
FSL_IMX6UL_GPT2_ADDR = 0x020E8000,
174
+
175
FSL_IMX6UL_IOMUXC_GPR_ADDR = 0x020E4000,
176
+ FSL_IMX6UL_IOMUXC_GPR_SIZE = 0x40,
177
+
178
FSL_IMX6UL_IOMUXC_ADDR = 0x020E0000,
179
+ FSL_IMX6UL_IOMUXC_SIZE = 0x700,
180
+
181
FSL_IMX6UL_GPC_ADDR = 0x020DC000,
182
+
183
FSL_IMX6UL_SRC_ADDR = 0x020D8000,
184
+
185
FSL_IMX6UL_EPIT2_ADDR = 0x020D4000,
186
FSL_IMX6UL_EPIT1_ADDR = 0x020D0000,
187
+
188
FSL_IMX6UL_SNVS_HP_ADDR = 0x020CC000,
189
+
190
FSL_IMX6UL_USBPHY2_ADDR = 0x020CA000,
191
- FSL_IMX6UL_USBPHY2_SIZE = (4 * 1024),
192
FSL_IMX6UL_USBPHY1_ADDR = 0x020C9000,
193
- FSL_IMX6UL_USBPHY1_SIZE = (4 * 1024),
194
+
195
FSL_IMX6UL_ANALOG_ADDR = 0x020C8000,
196
+ FSL_IMX6UL_ANALOG_SIZE = 0x300,
197
+
198
FSL_IMX6UL_CCM_ADDR = 0x020C4000,
199
+
200
FSL_IMX6UL_WDOG2_ADDR = 0x020C0000,
201
FSL_IMX6UL_WDOG1_ADDR = 0x020BC000,
202
+
203
FSL_IMX6UL_KPP_ADDR = 0x020B8000,
204
+ FSL_IMX6UL_KPP_SIZE = 0x10,
205
+
206
FSL_IMX6UL_ENET2_ADDR = 0x020B4000,
207
+
208
FSL_IMX6UL_SNVS_LP_ADDR = 0x020B0000,
209
+ FSL_IMX6UL_SNVS_LP_SIZE = (16 * KiB),
210
+
211
FSL_IMX6UL_GPIO5_ADDR = 0x020AC000,
212
FSL_IMX6UL_GPIO4_ADDR = 0x020A8000,
213
FSL_IMX6UL_GPIO3_ADDR = 0x020A4000,
214
FSL_IMX6UL_GPIO2_ADDR = 0x020A0000,
215
FSL_IMX6UL_GPIO1_ADDR = 0x0209C000,
216
+
217
FSL_IMX6UL_GPT1_ADDR = 0x02098000,
218
+
219
FSL_IMX6UL_CAN2_ADDR = 0x02094000,
220
FSL_IMX6UL_CAN1_ADDR = 0x02090000,
221
+ FSL_IMX6UL_CANn_SIZE = (4 * KiB),
222
+
223
FSL_IMX6UL_PWM4_ADDR = 0x0208C000,
224
FSL_IMX6UL_PWM3_ADDR = 0x02088000,
225
FSL_IMX6UL_PWM2_ADDR = 0x02084000,
226
FSL_IMX6UL_PWM1_ADDR = 0x02080000,
227
+ FSL_IMX6UL_PWMn_SIZE = 0x20,
228
+
229
FSL_IMX6UL_AIPS1_CFG_ADDR = 0x0207C000,
230
+ FSL_IMX6UL_AIPS1_CFG_SIZE = (16 * KiB),
231
+
232
FSL_IMX6UL_BEE_ADDR = 0x02044000,
233
+ FSL_IMX6UL_BEE_SIZE = (16 * KiB),
234
+
235
FSL_IMX6UL_TOUCH_CTRL_ADDR = 0x02040000,
236
+ FSL_IMX6UL_TOUCH_CTRL_SIZE = 0x100,
237
+
238
FSL_IMX6UL_SPBA_ADDR = 0x0203C000,
239
+ FSL_IMX6UL_SPBA_SIZE = 0x100,
240
+
241
FSL_IMX6UL_ASRC_ADDR = 0x02034000,
242
+ FSL_IMX6UL_ASRC_SIZE = 0x100,
243
+
244
FSL_IMX6UL_SAI3_ADDR = 0x02030000,
245
FSL_IMX6UL_SAI2_ADDR = 0x0202C000,
246
FSL_IMX6UL_SAI1_ADDR = 0x02028000,
247
+ FSL_IMX6UL_SAIn_SIZE = 0x200,
248
+
249
FSL_IMX6UL_UART8_ADDR = 0x02024000,
250
FSL_IMX6UL_UART1_ADDR = 0x02020000,
251
FSL_IMX6UL_UART7_ADDR = 0x02018000,
252
+
253
FSL_IMX6UL_ECSPI4_ADDR = 0x02014000,
254
FSL_IMX6UL_ECSPI3_ADDR = 0x02010000,
255
FSL_IMX6UL_ECSPI2_ADDR = 0x0200C000,
256
FSL_IMX6UL_ECSPI1_ADDR = 0x02008000,
257
+
258
FSL_IMX6UL_SPDIF_ADDR = 0x02004000,
259
+ FSL_IMX6UL_SPDIF_SIZE = 0x100,
260
+ /* AIPS-1 End */
261
+
262
+ FSL_IMX6UL_BCH_ADDR = 0x01808000,
263
+ FSL_IMX6UL_BCH_SIZE = 0x200,
264
+
265
+ FSL_IMX6UL_GPMI_ADDR = 0x01806000,
266
+ FSL_IMX6UL_GPMI_SIZE = 0x200,
267
268
FSL_IMX6UL_APBH_DMA_ADDR = 0x01804000,
269
- FSL_IMX6UL_APBH_DMA_SIZE = (32 * 1024),
270
+ FSL_IMX6UL_APBH_DMA_SIZE = (4 * KiB),
271
272
FSL_IMX6UL_A7MPCORE_ADDR = 0x00A00000,
273
274
FSL_IMX6UL_OCRAM_ALIAS_ADDR = 0x00920000,
275
- FSL_IMX6UL_OCRAM_ALIAS_SIZE = 0x00060000,
276
+ FSL_IMX6UL_OCRAM_ALIAS_SIZE = (384 * KiB),
277
+
278
FSL_IMX6UL_OCRAM_MEM_ADDR = 0x00900000,
279
- FSL_IMX6UL_OCRAM_MEM_SIZE = 0x00020000,
280
+ FSL_IMX6UL_OCRAM_MEM_SIZE = (128 * KiB),
281
+
282
FSL_IMX6UL_CAAM_MEM_ADDR = 0x00100000,
283
- FSL_IMX6UL_CAAM_MEM_SIZE = 0x00008000,
284
+ FSL_IMX6UL_CAAM_MEM_SIZE = (32 * KiB),
285
+
286
FSL_IMX6UL_ROM_ADDR = 0x00000000,
287
- FSL_IMX6UL_ROM_SIZE = 0x00018000,
288
+ FSL_IMX6UL_ROM_SIZE = (96 * KiB),
289
};
290
291
enum FslIMX6ULIRQs {
292
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
293
index XXXXXXX..XXXXXXX 100644
294
--- a/hw/arm/fsl-imx6ul.c
295
+++ b/hw/arm/fsl-imx6ul.c
296
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
297
object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
298
299
/*
300
- * GPIOs 1 to 5
301
+ * GPIOs
302
*/
303
for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
304
snprintf(name, NAME_SIZE, "gpio%d", i);
305
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
306
}
307
308
/*
309
- * GPT 1, 2
310
+ * GPTs
311
*/
312
for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
313
snprintf(name, NAME_SIZE, "gpt%d", i);
314
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
315
}
316
317
/*
318
- * EPIT 1, 2
319
+ * EPITs
320
*/
321
for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
322
snprintf(name, NAME_SIZE, "epit%d", i + 1);
323
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
324
}
325
326
/*
327
- * eCSPI
328
+ * eCSPIs
329
*/
330
for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
331
snprintf(name, NAME_SIZE, "spi%d", i + 1);
332
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
333
}
334
335
/*
336
- * I2C
337
+ * I2Cs
338
*/
339
for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
340
snprintf(name, NAME_SIZE, "i2c%d", i + 1);
341
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
342
}
343
344
/*
345
- * UART
346
+ * UARTs
347
*/
348
for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
349
snprintf(name, NAME_SIZE, "uart%d", i);
350
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
351
}
352
353
/*
354
- * Ethernet
355
+ * Ethernets
356
*/
357
for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
358
snprintf(name, NAME_SIZE, "eth%d", i);
359
object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
360
}
361
362
- /* USB */
363
+ /*
364
+ * USB PHYs
365
+ */
366
for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
367
snprintf(name, NAME_SIZE, "usbphy%d", i);
368
object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
369
}
370
+
371
+ /*
372
+ * USBs
373
+ */
374
for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
375
snprintf(name, NAME_SIZE, "usb%d", i);
376
object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
377
}
378
379
/*
380
- * SDHCI
381
+ * SDHCIs
382
*/
383
for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
384
snprintf(name, NAME_SIZE, "usdhc%d", i);
385
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
386
}
387
388
/*
389
- * Watchdog
390
+ * Watchdogs
391
*/
392
for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
393
snprintf(name, NAME_SIZE, "wdt%d", i);
394
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
395
* A7MPCORE DAP
396
*/
397
create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR,
398
- 0x100000);
399
+ FSL_IMX6UL_A7MPCORE_DAP_SIZE);
400
401
/*
402
- * GPT 1, 2
403
+ * GPTs
404
*/
405
for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
406
static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = {
407
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
408
}
409
410
/*
411
- * EPIT 1, 2
412
+ * EPITs
413
*/
414
for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
415
static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = {
416
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
417
}
418
419
/*
420
- * GPIO
421
+ * GPIOs
422
*/
423
for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
424
static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = {
425
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
426
}
427
428
/*
429
- * IOMUXC and IOMUXC_GPR
430
+ * IOMUXC
431
*/
432
- for (i = 0; i < 1; i++) {
433
- static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = {
434
- FSL_IMX6UL_IOMUXC_ADDR,
435
- FSL_IMX6UL_IOMUXC_GPR_ADDR,
436
- };
437
-
438
- snprintf(name, NAME_SIZE, "iomuxc%d", i);
439
- create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000);
440
- }
441
+ create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR,
442
+ FSL_IMX6UL_IOMUXC_SIZE);
443
+ create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR,
444
+ FSL_IMX6UL_IOMUXC_GPR_SIZE);
445
446
/*
447
* CCM
448
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
449
sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
450
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
451
452
- /* Initialize all ECSPI */
453
+ /*
454
+ * ECSPIs
455
+ */
456
for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
457
static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = {
458
FSL_IMX6UL_ECSPI1_ADDR,
459
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
460
}
461
462
/*
463
- * I2C
464
+ * I2Cs
465
*/
466
for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
467
static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = {
468
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
469
}
470
471
/*
472
- * UART
473
+ * UARTs
474
*/
475
for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
476
static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = {
477
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
478
}
479
480
/*
481
- * Ethernet
482
+ * Ethernets
483
*
484
* We must use two loops since phy_connected affects the other interface
485
* and we have to set all properties before calling sysbus_realize().
486
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
487
FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
488
}
489
490
- /* USB */
491
+ /*
492
+ * USB PHYs
493
+ */
494
for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
495
+ static const hwaddr
496
+ FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] = {
497
+ FSL_IMX6UL_USBPHY1_ADDR,
498
+ FSL_IMX6UL_USBPHY2_ADDR,
499
+ };
500
+
501
sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
502
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
503
- FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000);
504
+ FSL_IMX6UL_USB_PHYn_ADDR[i]);
505
}
506
507
+ /*
508
+ * USBs
509
+ */
510
for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
511
+ static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS] = {
512
+ FSL_IMX6UL_USBO2_USB1_ADDR,
513
+ FSL_IMX6UL_USBO2_USB2_ADDR,
514
+ };
515
+
516
static const int FSL_IMX6UL_USBn_IRQ[] = {
517
FSL_IMX6UL_USB1_IRQ,
518
FSL_IMX6UL_USB2_IRQ,
519
};
520
+
521
sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
522
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
523
- FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200);
524
+ FSL_IMX6UL_USB02_USBn_ADDR[i]);
525
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
526
qdev_get_gpio_in(DEVICE(&s->a7mpcore),
527
FSL_IMX6UL_USBn_IRQ[i]));
528
}
529
530
/*
531
- * USDHC
532
+ * USDHCs
533
*/
534
for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
535
static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = {
536
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
537
sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
538
539
/*
540
- * Watchdog
541
+ * Watchdogs
542
*/
543
for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
544
static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = {
545
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
546
FSL_IMX6UL_WDOG2_ADDR,
547
FSL_IMX6UL_WDOG3_ADDR,
548
};
549
+
550
static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = {
551
FSL_IMX6UL_WDOG1_IRQ,
552
FSL_IMX6UL_WDOG2_IRQ,
553
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
554
/*
555
* SDMA
556
*/
557
- create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
558
+ create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR,
559
+ FSL_IMX6UL_SDMA_SIZE);
560
561
/*
562
- * SAI (Audio SSI (Synchronous Serial Interface))
563
+ * SAIs (Audio SSI (Synchronous Serial Interface))
564
*/
565
- create_unimplemented_device("sai1", FSL_IMX6UL_SAI1_ADDR, 0x4000);
566
- create_unimplemented_device("sai2", FSL_IMX6UL_SAI2_ADDR, 0x4000);
567
- create_unimplemented_device("sai3", FSL_IMX6UL_SAI3_ADDR, 0x4000);
568
+ for (i = 0; i < FSL_IMX6UL_NUM_SAIS; i++) {
569
+ static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] = {
570
+ FSL_IMX6UL_SAI1_ADDR,
571
+ FSL_IMX6UL_SAI2_ADDR,
572
+ FSL_IMX6UL_SAI3_ADDR,
573
+ };
574
+
575
+ snprintf(name, NAME_SIZE, "sai%d", i);
576
+ create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i],
577
+ FSL_IMX6UL_SAIn_SIZE);
578
+ }
579
580
/*
581
- * PWM
582
+ * PWMs
583
*/
584
- create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000);
585
- create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000);
586
- create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000);
587
- create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000);
588
+ for (i = 0; i < FSL_IMX6UL_NUM_PWMS; i++) {
589
+ static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] = {
590
+ FSL_IMX6UL_PWM1_ADDR,
591
+ FSL_IMX6UL_PWM2_ADDR,
592
+ FSL_IMX6UL_PWM3_ADDR,
593
+ FSL_IMX6UL_PWM4_ADDR,
594
+ };
595
+
596
+ snprintf(name, NAME_SIZE, "pwm%d", i);
597
+ create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i],
598
+ FSL_IMX6UL_PWMn_SIZE);
599
+ }
600
601
/*
602
* Audio ASRC (asynchronous sample rate converter)
603
*/
604
- create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, 0x4000);
605
+ create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR,
606
+ FSL_IMX6UL_ASRC_SIZE);
607
608
/*
609
- * CAN
610
+ * CANs
611
*/
612
- create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000);
613
- create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000);
614
+ for (i = 0; i < FSL_IMX6UL_NUM_CANS; i++) {
615
+ static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] = {
616
+ FSL_IMX6UL_CAN1_ADDR,
617
+ FSL_IMX6UL_CAN2_ADDR,
618
+ };
619
+
620
+ snprintf(name, NAME_SIZE, "can%d", i);
621
+ create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i],
622
+ FSL_IMX6UL_CANn_SIZE);
623
+ }
624
625
/*
626
* APHB_DMA
627
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
628
};
629
630
snprintf(name, NAME_SIZE, "adc%d", i);
631
- create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000);
632
+ create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i],
633
+ FSL_IMX6UL_ADCn_SIZE);
634
}
635
636
/*
637
* LCD
638
*/
639
- create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000);
640
+ create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
641
+ FSL_IMX6UL_LCDIF_SIZE);
642
643
/*
644
* ROM memory
30
--
645
--
31
2.20.1
646
2.34.1
32
33
diff view generated by jsdifflib
[PULL 18/21] hw/arm/xlnx-versal: Versal SoC requires ZDMA
[PULL 13/24] Add i.MX6UL missing devices.
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
2
3
The Versal SoC instantiates the TYPE_XLNX_ZDMA object in
3
* Add TZASC as unimplemented device.
4
versal_create_admas(). Introduce the XLNX_ZDMA configuration
4
- Allow bare metal application to access this (unimplemented) device
5
and select it to fix:
5
* Add CSU as unimplemented device.
6
- Allow bare metal application to access this (unimplemented) device
7
* Add 4 missing PWM devices
6
8
7
$ qemu-system-aarch64 -M xlnx-versal-virt ...
9
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
8
qemu-system-aarch64: missing object type 'xlnx.zdma'
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
11
Message-id: 59e4dc56e14eccfefd379275ec19048dff9c10b3.1692964892.git.jcd@tribudubois.net
10
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-id: 20210131184449.382425-4-f4bug@amsat.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
13
---
15
hw/arm/Kconfig | 2 ++
14
include/hw/arm/fsl-imx6ul.h | 2 +-
16
hw/dma/Kconfig | 3 +++
15
hw/arm/fsl-imx6ul.c | 16 ++++++++++++++++
17
hw/dma/meson.build | 2 +-
16
2 files changed, 17 insertions(+), 1 deletion(-)
18
3 files changed, 6 insertions(+), 1 deletion(-)
19
17
20
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
18
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
21
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/Kconfig
20
--- a/include/hw/arm/fsl-imx6ul.h
23
+++ b/hw/arm/Kconfig
21
+++ b/include/hw/arm/fsl-imx6ul.h
24
@@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP_ARM
22
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
25
select XILINX_AXI
23
FSL_IMX6UL_NUM_USBS = 2,
26
select XILINX_SPIPS
24
FSL_IMX6UL_NUM_SAIS = 3,
27
select XLNX_ZYNQMP
25
FSL_IMX6UL_NUM_CANS = 2,
28
+ select XLNX_ZDMA
26
- FSL_IMX6UL_NUM_PWMS = 4,
29
27
+ FSL_IMX6UL_NUM_PWMS = 8,
30
config XLNX_VERSAL
28
};
31
bool
29
32
@@ -XXX,XX +XXX,XX @@ config XLNX_VERSAL
30
struct FslIMX6ULState {
33
select CADENCE
31
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
34
select VIRTIO_MMIO
35
select UNIMP
36
+ select XLNX_ZDMA
37
38
config NPCM7XX
39
bool
40
diff --git a/hw/dma/Kconfig b/hw/dma/Kconfig
41
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/dma/Kconfig
33
--- a/hw/arm/fsl-imx6ul.c
43
+++ b/hw/dma/Kconfig
34
+++ b/hw/arm/fsl-imx6ul.c
44
@@ -XXX,XX +XXX,XX @@ config ZYNQ_DEVCFG
35
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
45
bool
36
FSL_IMX6UL_PWM2_ADDR,
46
select REGISTER
37
FSL_IMX6UL_PWM3_ADDR,
47
38
FSL_IMX6UL_PWM4_ADDR,
48
+config XLNX_ZDMA
39
+ FSL_IMX6UL_PWM5_ADDR,
49
+ bool
40
+ FSL_IMX6UL_PWM6_ADDR,
41
+ FSL_IMX6UL_PWM7_ADDR,
42
+ FSL_IMX6UL_PWM8_ADDR,
43
};
44
45
snprintf(name, NAME_SIZE, "pwm%d", i);
46
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
47
create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
48
FSL_IMX6UL_LCDIF_SIZE);
49
50
+ /*
51
+ * CSU
52
+ */
53
+ create_unimplemented_device("csu", FSL_IMX6UL_CSU_ADDR,
54
+ FSL_IMX6UL_CSU_SIZE);
50
+
55
+
51
config STP2000
56
+ /*
52
bool
57
+ * TZASC
53
58
+ */
54
diff --git a/hw/dma/meson.build b/hw/dma/meson.build
59
+ create_unimplemented_device("tzasc", FSL_IMX6UL_TZASC_ADDR,
55
index XXXXXXX..XXXXXXX 100644
60
+ FSL_IMX6UL_TZASC_SIZE);
56
--- a/hw/dma/meson.build
61
+
57
+++ b/hw/dma/meson.build
62
/*
58
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ZYNQ_DEVCFG', if_true: files('xlnx-zynq-devcfg.c'))
63
* ROM memory
59
softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_dma.c'))
64
*/
60
softmmu_ss.add(when: 'CONFIG_STP2000', if_true: files('sparc32_dma.c'))
61
softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx_dpdma.c'))
62
-softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zdma.c'))
63
+softmmu_ss.add(when: 'CONFIG_XLNX_ZDMA', if_true: files('xlnx-zdma.c'))
64
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_dma.c', 'soc_dma.c'))
65
softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_dma.c'))
66
softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_dma.c'))
67
--
65
--
68
2.20.1
66
2.34.1
69
67
70
68
diff view generated by jsdifflib
[PULL 12/21] hw/ssi: imx_spi: Round up the burst length to be multiple of 8
[PULL 14/24] Refactor i.MX7 processor code
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
2
3
Current implementation of the imx spi controller expects the burst
3
* Add Addr and size definition for all i.MX7 devices in i.MX7 header file.
4
length to be multiple of 8, which is the most common use case.
4
* Use those newly defined named constants whenever possible.
5
* Standardize the way we init a familly of unimplemented devices
6
- SAI
7
- PWM
8
- CAN
9
* Add/rework few comments
5
10
6
In case the burst length is not what we expect, log it to give user
11
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
7
a chance to notice it, and round it up to be multiple of 8.
12
Message-id: 59e195d33e4d486a8d131392acd46633c8c10ed7.1692964892.git.jcd@tribudubois.net
8
9
Signed-off-by: Bin Meng <bin.meng@windriver.com>
10
Message-id: 20210129132323.30946-9-bmeng.cn@gmail.com
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
15
---
14
hw/ssi/imx_spi.c | 17 ++++++++++++++++-
16
include/hw/arm/fsl-imx7.h | 330 ++++++++++++++++++++++++++++----------
15
1 file changed, 16 insertions(+), 1 deletion(-)
17
hw/arm/fsl-imx7.c | 130 ++++++++++-----
18
2 files changed, 335 insertions(+), 125 deletions(-)
16
19
17
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
20
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
18
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/ssi/imx_spi.c
22
--- a/include/hw/arm/fsl-imx7.h
20
+++ b/hw/ssi/imx_spi.c
23
+++ b/include/hw/arm/fsl-imx7.h
21
@@ -XXX,XX +XXX,XX @@ static uint8_t imx_spi_selected_channel(IMXSPIState *s)
24
@@ -XXX,XX +XXX,XX @@
22
25
#include "hw/misc/imx7_ccm.h"
23
static uint32_t imx_spi_burst_length(IMXSPIState *s)
26
#include "hw/misc/imx7_snvs.h"
24
{
27
#include "hw/misc/imx7_gpr.h"
25
- return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
28
-#include "hw/misc/imx6_src.h"
26
+ uint32_t burst;
29
#include "hw/watchdog/wdt_imx2.h"
27
+
30
#include "hw/gpio/imx_gpio.h"
28
+ burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
31
#include "hw/char/imx_serial.h"
29
+ if (burst % 8) {
32
@@ -XXX,XX +XXX,XX @@
30
+ burst = ROUND_UP(burst, 8);
33
#include "hw/usb/chipidea.h"
34
#include "cpu.h"
35
#include "qom/object.h"
36
+#include "qemu/units.h"
37
38
#define TYPE_FSL_IMX7 "fsl-imx7"
39
OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7)
40
@@ -XXX,XX +XXX,XX @@ enum FslIMX7Configuration {
41
FSL_IMX7_NUM_ECSPIS = 4,
42
FSL_IMX7_NUM_USBS = 3,
43
FSL_IMX7_NUM_ADCS = 2,
44
+ FSL_IMX7_NUM_SAIS = 3,
45
+ FSL_IMX7_NUM_CANS = 2,
46
+ FSL_IMX7_NUM_PWMS = 4,
47
};
48
49
struct FslIMX7State {
50
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
51
52
enum FslIMX7MemoryMap {
53
FSL_IMX7_MMDC_ADDR = 0x80000000,
54
- FSL_IMX7_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL,
55
+ FSL_IMX7_MMDC_SIZE = (2 * GiB),
56
57
- FSL_IMX7_GPIO1_ADDR = 0x30200000,
58
- FSL_IMX7_GPIO2_ADDR = 0x30210000,
59
- FSL_IMX7_GPIO3_ADDR = 0x30220000,
60
- FSL_IMX7_GPIO4_ADDR = 0x30230000,
61
- FSL_IMX7_GPIO5_ADDR = 0x30240000,
62
- FSL_IMX7_GPIO6_ADDR = 0x30250000,
63
- FSL_IMX7_GPIO7_ADDR = 0x30260000,
64
+ FSL_IMX7_QSPI1_MEM_ADDR = 0x60000000,
65
+ FSL_IMX7_QSPI1_MEM_SIZE = (256 * MiB),
66
67
- FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
68
+ FSL_IMX7_PCIE1_MEM_ADDR = 0x40000000,
69
+ FSL_IMX7_PCIE1_MEM_SIZE = (256 * MiB),
70
71
- FSL_IMX7_WDOG1_ADDR = 0x30280000,
72
- FSL_IMX7_WDOG2_ADDR = 0x30290000,
73
- FSL_IMX7_WDOG3_ADDR = 0x302A0000,
74
- FSL_IMX7_WDOG4_ADDR = 0x302B0000,
75
+ FSL_IMX7_QSPI1_RX_BUF_ADDR = 0x34000000,
76
+ FSL_IMX7_QSPI1_RX_BUF_SIZE = (32 * MiB),
77
78
- FSL_IMX7_IOMUXC_LPSR_ADDR = 0x302C0000,
79
+ /* PCIe Peripherals */
80
+ FSL_IMX7_PCIE_REG_ADDR = 0x33800000,
81
82
- FSL_IMX7_GPT1_ADDR = 0x302D0000,
83
- FSL_IMX7_GPT2_ADDR = 0x302E0000,
84
- FSL_IMX7_GPT3_ADDR = 0x302F0000,
85
- FSL_IMX7_GPT4_ADDR = 0x30300000,
86
+ /* MMAP Peripherals */
87
+ FSL_IMX7_DMA_APBH_ADDR = 0x33000000,
88
+ FSL_IMX7_DMA_APBH_SIZE = 0x8000,
89
90
- FSL_IMX7_IOMUXC_ADDR = 0x30330000,
91
- FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000,
92
- FSL_IMX7_IOMUXCn_SIZE = 0x1000,
93
+ /* GPV configuration */
94
+ FSL_IMX7_GPV6_ADDR = 0x32600000,
95
+ FSL_IMX7_GPV5_ADDR = 0x32500000,
96
+ FSL_IMX7_GPV4_ADDR = 0x32400000,
97
+ FSL_IMX7_GPV3_ADDR = 0x32300000,
98
+ FSL_IMX7_GPV2_ADDR = 0x32200000,
99
+ FSL_IMX7_GPV1_ADDR = 0x32100000,
100
+ FSL_IMX7_GPV0_ADDR = 0x32000000,
101
+ FSL_IMX7_GPVn_SIZE = (1 * MiB),
102
103
- FSL_IMX7_OCOTP_ADDR = 0x30350000,
104
- FSL_IMX7_OCOTP_SIZE = 0x10000,
105
+ /* Arm Peripherals */
106
+ FSL_IMX7_A7MPCORE_ADDR = 0x31000000,
107
108
- FSL_IMX7_ANALOG_ADDR = 0x30360000,
109
- FSL_IMX7_SNVS_ADDR = 0x30370000,
110
- FSL_IMX7_CCM_ADDR = 0x30380000,
111
+ /* AIPS-3 Begin */
112
113
- FSL_IMX7_SRC_ADDR = 0x30390000,
114
- FSL_IMX7_SRC_SIZE = 0x1000,
115
+ FSL_IMX7_ENET2_ADDR = 0x30BF0000,
116
+ FSL_IMX7_ENET1_ADDR = 0x30BE0000,
117
118
- FSL_IMX7_ADC1_ADDR = 0x30610000,
119
- FSL_IMX7_ADC2_ADDR = 0x30620000,
120
- FSL_IMX7_ADCn_SIZE = 0x1000,
121
+ FSL_IMX7_SDMA_ADDR = 0x30BD0000,
122
+ FSL_IMX7_SDMA_SIZE = (4 * KiB),
123
124
- FSL_IMX7_PWM1_ADDR = 0x30660000,
125
- FSL_IMX7_PWM2_ADDR = 0x30670000,
126
- FSL_IMX7_PWM3_ADDR = 0x30680000,
127
- FSL_IMX7_PWM4_ADDR = 0x30690000,
128
- FSL_IMX7_PWMn_SIZE = 0x10000,
129
+ FSL_IMX7_EIM_ADDR = 0x30BC0000,
130
+ FSL_IMX7_EIM_SIZE = (4 * KiB),
131
132
- FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000,
133
- FSL_IMX7_PCIE_PHY_SIZE = 0x10000,
134
+ FSL_IMX7_QSPI_ADDR = 0x30BB0000,
135
+ FSL_IMX7_QSPI_SIZE = 0x8000,
136
137
- FSL_IMX7_GPC_ADDR = 0x303A0000,
138
+ FSL_IMX7_SIM2_ADDR = 0x30BA0000,
139
+ FSL_IMX7_SIM1_ADDR = 0x30B90000,
140
+ FSL_IMX7_SIMn_SIZE = (4 * KiB),
141
+
142
+ FSL_IMX7_USDHC3_ADDR = 0x30B60000,
143
+ FSL_IMX7_USDHC2_ADDR = 0x30B50000,
144
+ FSL_IMX7_USDHC1_ADDR = 0x30B40000,
145
+
146
+ FSL_IMX7_USB3_ADDR = 0x30B30000,
147
+ FSL_IMX7_USBMISC3_ADDR = 0x30B30200,
148
+ FSL_IMX7_USB2_ADDR = 0x30B20000,
149
+ FSL_IMX7_USBMISC2_ADDR = 0x30B20200,
150
+ FSL_IMX7_USB1_ADDR = 0x30B10000,
151
+ FSL_IMX7_USBMISC1_ADDR = 0x30B10200,
152
+ FSL_IMX7_USBMISCn_SIZE = 0x200,
153
+
154
+ FSL_IMX7_USB_PL301_ADDR = 0x30AD0000,
155
+ FSL_IMX7_USB_PL301_SIZE = (64 * KiB),
156
+
157
+ FSL_IMX7_SEMAPHORE_HS_ADDR = 0x30AC0000,
158
+ FSL_IMX7_SEMAPHORE_HS_SIZE = (64 * KiB),
159
+
160
+ FSL_IMX7_MUB_ADDR = 0x30AB0000,
161
+ FSL_IMX7_MUA_ADDR = 0x30AA0000,
162
+ FSL_IMX7_MUn_SIZE = (KiB),
163
+
164
+ FSL_IMX7_UART7_ADDR = 0x30A90000,
165
+ FSL_IMX7_UART6_ADDR = 0x30A80000,
166
+ FSL_IMX7_UART5_ADDR = 0x30A70000,
167
+ FSL_IMX7_UART4_ADDR = 0x30A60000,
168
+
169
+ FSL_IMX7_I2C4_ADDR = 0x30A50000,
170
+ FSL_IMX7_I2C3_ADDR = 0x30A40000,
171
+ FSL_IMX7_I2C2_ADDR = 0x30A30000,
172
+ FSL_IMX7_I2C1_ADDR = 0x30A20000,
173
+
174
+ FSL_IMX7_CAN2_ADDR = 0x30A10000,
175
+ FSL_IMX7_CAN1_ADDR = 0x30A00000,
176
+ FSL_IMX7_CANn_SIZE = (4 * KiB),
177
+
178
+ FSL_IMX7_AIPS3_CONF_ADDR = 0x309F0000,
179
+ FSL_IMX7_AIPS3_CONF_SIZE = (64 * KiB),
180
181
FSL_IMX7_CAAM_ADDR = 0x30900000,
182
- FSL_IMX7_CAAM_SIZE = 0x40000,
183
+ FSL_IMX7_CAAM_SIZE = (256 * KiB),
184
185
- FSL_IMX7_CAN1_ADDR = 0x30A00000,
186
- FSL_IMX7_CAN2_ADDR = 0x30A10000,
187
- FSL_IMX7_CANn_SIZE = 0x10000,
188
+ FSL_IMX7_SPBA_ADDR = 0x308F0000,
189
+ FSL_IMX7_SPBA_SIZE = (4 * KiB),
190
191
- FSL_IMX7_I2C1_ADDR = 0x30A20000,
192
- FSL_IMX7_I2C2_ADDR = 0x30A30000,
193
- FSL_IMX7_I2C3_ADDR = 0x30A40000,
194
- FSL_IMX7_I2C4_ADDR = 0x30A50000,
195
+ FSL_IMX7_SAI3_ADDR = 0x308C0000,
196
+ FSL_IMX7_SAI2_ADDR = 0x308B0000,
197
+ FSL_IMX7_SAI1_ADDR = 0x308A0000,
198
+ FSL_IMX7_SAIn_SIZE = (4 * KiB),
199
200
- FSL_IMX7_ECSPI1_ADDR = 0x30820000,
201
- FSL_IMX7_ECSPI2_ADDR = 0x30830000,
202
- FSL_IMX7_ECSPI3_ADDR = 0x30840000,
203
- FSL_IMX7_ECSPI4_ADDR = 0x30630000,
204
-
205
- FSL_IMX7_LCDIF_ADDR = 0x30730000,
206
- FSL_IMX7_LCDIF_SIZE = 0x1000,
207
-
208
- FSL_IMX7_UART1_ADDR = 0x30860000,
209
+ FSL_IMX7_UART3_ADDR = 0x30880000,
210
/*
211
* Some versions of the reference manual claim that UART2 is @
212
* 0x30870000, but experiments with HW + DT files in upstream
213
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
214
* actually located @ 0x30890000
215
*/
216
FSL_IMX7_UART2_ADDR = 0x30890000,
217
- FSL_IMX7_UART3_ADDR = 0x30880000,
218
- FSL_IMX7_UART4_ADDR = 0x30A60000,
219
- FSL_IMX7_UART5_ADDR = 0x30A70000,
220
- FSL_IMX7_UART6_ADDR = 0x30A80000,
221
- FSL_IMX7_UART7_ADDR = 0x30A90000,
222
+ FSL_IMX7_UART1_ADDR = 0x30860000,
223
224
- FSL_IMX7_SAI1_ADDR = 0x308A0000,
225
- FSL_IMX7_SAI2_ADDR = 0x308B0000,
226
- FSL_IMX7_SAI3_ADDR = 0x308C0000,
227
- FSL_IMX7_SAIn_SIZE = 0x10000,
228
+ FSL_IMX7_ECSPI3_ADDR = 0x30840000,
229
+ FSL_IMX7_ECSPI2_ADDR = 0x30830000,
230
+ FSL_IMX7_ECSPI1_ADDR = 0x30820000,
231
+ FSL_IMX7_ECSPIn_SIZE = (4 * KiB),
232
233
- FSL_IMX7_ENET1_ADDR = 0x30BE0000,
234
- FSL_IMX7_ENET2_ADDR = 0x30BF0000,
235
+ /* AIPS-3 End */
236
237
- FSL_IMX7_USB1_ADDR = 0x30B10000,
238
- FSL_IMX7_USBMISC1_ADDR = 0x30B10200,
239
- FSL_IMX7_USB2_ADDR = 0x30B20000,
240
- FSL_IMX7_USBMISC2_ADDR = 0x30B20200,
241
- FSL_IMX7_USB3_ADDR = 0x30B30000,
242
- FSL_IMX7_USBMISC3_ADDR = 0x30B30200,
243
- FSL_IMX7_USBMISCn_SIZE = 0x200,
244
+ /* AIPS-2 Begin */
245
246
- FSL_IMX7_USDHC1_ADDR = 0x30B40000,
247
- FSL_IMX7_USDHC2_ADDR = 0x30B50000,
248
- FSL_IMX7_USDHC3_ADDR = 0x30B60000,
249
+ FSL_IMX7_AXI_DEBUG_MON_ADDR = 0x307E0000,
250
+ FSL_IMX7_AXI_DEBUG_MON_SIZE = (64 * KiB),
251
252
- FSL_IMX7_SDMA_ADDR = 0x30BD0000,
253
- FSL_IMX7_SDMA_SIZE = 0x1000,
254
+ FSL_IMX7_PERFMON2_ADDR = 0x307D0000,
255
+ FSL_IMX7_PERFMON1_ADDR = 0x307C0000,
256
+ FSL_IMX7_PERFMONn_SIZE = (64 * KiB),
257
+
258
+ FSL_IMX7_DDRC_ADDR = 0x307A0000,
259
+ FSL_IMX7_DDRC_SIZE = (4 * KiB),
260
+
261
+ FSL_IMX7_DDRC_PHY_ADDR = 0x30790000,
262
+ FSL_IMX7_DDRC_PHY_SIZE = (4 * KiB),
263
+
264
+ FSL_IMX7_TZASC_ADDR = 0x30780000,
265
+ FSL_IMX7_TZASC_SIZE = (64 * KiB),
266
+
267
+ FSL_IMX7_MIPI_DSI_ADDR = 0x30760000,
268
+ FSL_IMX7_MIPI_DSI_SIZE = (4 * KiB),
269
+
270
+ FSL_IMX7_MIPI_CSI_ADDR = 0x30750000,
271
+ FSL_IMX7_MIPI_CSI_SIZE = 0x4000,
272
+
273
+ FSL_IMX7_LCDIF_ADDR = 0x30730000,
274
+ FSL_IMX7_LCDIF_SIZE = 0x8000,
275
+
276
+ FSL_IMX7_CSI_ADDR = 0x30710000,
277
+ FSL_IMX7_CSI_SIZE = (4 * KiB),
278
+
279
+ FSL_IMX7_PXP_ADDR = 0x30700000,
280
+ FSL_IMX7_PXP_SIZE = 0x4000,
281
+
282
+ FSL_IMX7_EPDC_ADDR = 0x306F0000,
283
+ FSL_IMX7_EPDC_SIZE = (4 * KiB),
284
+
285
+ FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000,
286
+ FSL_IMX7_PCIE_PHY_SIZE = (4 * KiB),
287
+
288
+ FSL_IMX7_SYSCNT_CTRL_ADDR = 0x306C0000,
289
+ FSL_IMX7_SYSCNT_CMP_ADDR = 0x306B0000,
290
+ FSL_IMX7_SYSCNT_RD_ADDR = 0x306A0000,
291
+
292
+ FSL_IMX7_PWM4_ADDR = 0x30690000,
293
+ FSL_IMX7_PWM3_ADDR = 0x30680000,
294
+ FSL_IMX7_PWM2_ADDR = 0x30670000,
295
+ FSL_IMX7_PWM1_ADDR = 0x30660000,
296
+ FSL_IMX7_PWMn_SIZE = (4 * KiB),
297
+
298
+ FSL_IMX7_FlEXTIMER2_ADDR = 0x30650000,
299
+ FSL_IMX7_FlEXTIMER1_ADDR = 0x30640000,
300
+ FSL_IMX7_FLEXTIMERn_SIZE = (4 * KiB),
301
+
302
+ FSL_IMX7_ECSPI4_ADDR = 0x30630000,
303
+
304
+ FSL_IMX7_ADC2_ADDR = 0x30620000,
305
+ FSL_IMX7_ADC1_ADDR = 0x30610000,
306
+ FSL_IMX7_ADCn_SIZE = (4 * KiB),
307
+
308
+ FSL_IMX7_AIPS2_CONF_ADDR = 0x305F0000,
309
+ FSL_IMX7_AIPS2_CONF_SIZE = (64 * KiB),
310
+
311
+ /* AIPS-2 End */
312
+
313
+ /* AIPS-1 Begin */
314
+
315
+ FSL_IMX7_CSU_ADDR = 0x303E0000,
316
+ FSL_IMX7_CSU_SIZE = (64 * KiB),
317
+
318
+ FSL_IMX7_RDC_ADDR = 0x303D0000,
319
+ FSL_IMX7_RDC_SIZE = (4 * KiB),
320
+
321
+ FSL_IMX7_SEMAPHORE2_ADDR = 0x303C0000,
322
+ FSL_IMX7_SEMAPHORE1_ADDR = 0x303B0000,
323
+ FSL_IMX7_SEMAPHOREn_SIZE = (4 * KiB),
324
+
325
+ FSL_IMX7_GPC_ADDR = 0x303A0000,
326
+
327
+ FSL_IMX7_SRC_ADDR = 0x30390000,
328
+ FSL_IMX7_SRC_SIZE = (4 * KiB),
329
+
330
+ FSL_IMX7_CCM_ADDR = 0x30380000,
331
+
332
+ FSL_IMX7_SNVS_HP_ADDR = 0x30370000,
333
+
334
+ FSL_IMX7_ANALOG_ADDR = 0x30360000,
335
+
336
+ FSL_IMX7_OCOTP_ADDR = 0x30350000,
337
+ FSL_IMX7_OCOTP_SIZE = 0x10000,
338
+
339
+ FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000,
340
+ FSL_IMX7_IOMUXC_GPR_SIZE = (4 * KiB),
341
+
342
+ FSL_IMX7_IOMUXC_ADDR = 0x30330000,
343
+ FSL_IMX7_IOMUXC_SIZE = (4 * KiB),
344
+
345
+ FSL_IMX7_KPP_ADDR = 0x30320000,
346
+ FSL_IMX7_KPP_SIZE = (4 * KiB),
347
+
348
+ FSL_IMX7_ROMCP_ADDR = 0x30310000,
349
+ FSL_IMX7_ROMCP_SIZE = (4 * KiB),
350
+
351
+ FSL_IMX7_GPT4_ADDR = 0x30300000,
352
+ FSL_IMX7_GPT3_ADDR = 0x302F0000,
353
+ FSL_IMX7_GPT2_ADDR = 0x302E0000,
354
+ FSL_IMX7_GPT1_ADDR = 0x302D0000,
355
+
356
+ FSL_IMX7_IOMUXC_LPSR_ADDR = 0x302C0000,
357
+ FSL_IMX7_IOMUXC_LPSR_SIZE = (4 * KiB),
358
+
359
+ FSL_IMX7_WDOG4_ADDR = 0x302B0000,
360
+ FSL_IMX7_WDOG3_ADDR = 0x302A0000,
361
+ FSL_IMX7_WDOG2_ADDR = 0x30290000,
362
+ FSL_IMX7_WDOG1_ADDR = 0x30280000,
363
+
364
+ FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
365
+
366
+ FSL_IMX7_GPIO7_ADDR = 0x30260000,
367
+ FSL_IMX7_GPIO6_ADDR = 0x30250000,
368
+ FSL_IMX7_GPIO5_ADDR = 0x30240000,
369
+ FSL_IMX7_GPIO4_ADDR = 0x30230000,
370
+ FSL_IMX7_GPIO3_ADDR = 0x30220000,
371
+ FSL_IMX7_GPIO2_ADDR = 0x30210000,
372
+ FSL_IMX7_GPIO1_ADDR = 0x30200000,
373
+
374
+ FSL_IMX7_AIPS1_CONF_ADDR = 0x301F0000,
375
+ FSL_IMX7_AIPS1_CONF_SIZE = (64 * KiB),
376
377
- FSL_IMX7_A7MPCORE_ADDR = 0x31000000,
378
FSL_IMX7_A7MPCORE_DAP_ADDR = 0x30000000,
379
+ FSL_IMX7_A7MPCORE_DAP_SIZE = (1 * MiB),
380
381
- FSL_IMX7_PCIE_REG_ADDR = 0x33800000,
382
- FSL_IMX7_PCIE_REG_SIZE = 16 * 1024,
383
+ /* AIPS-1 End */
384
385
- FSL_IMX7_GPR_ADDR = 0x30340000,
386
+ FSL_IMX7_EIM_CS0_ADDR = 0x28000000,
387
+ FSL_IMX7_EIM_CS0_SIZE = (128 * MiB),
388
389
- FSL_IMX7_DMA_APBH_ADDR = 0x33000000,
390
- FSL_IMX7_DMA_APBH_SIZE = 0x2000,
391
+ FSL_IMX7_OCRAM_PXP_ADDR = 0x00940000,
392
+ FSL_IMX7_OCRAM_PXP_SIZE = (32 * KiB),
393
+
394
+ FSL_IMX7_OCRAM_EPDC_ADDR = 0x00920000,
395
+ FSL_IMX7_OCRAM_EPDC_SIZE = (128 * KiB),
396
+
397
+ FSL_IMX7_OCRAM_MEM_ADDR = 0x00900000,
398
+ FSL_IMX7_OCRAM_MEM_SIZE = (128 * KiB),
399
+
400
+ FSL_IMX7_TCMU_ADDR = 0x00800000,
401
+ FSL_IMX7_TCMU_SIZE = (32 * KiB),
402
+
403
+ FSL_IMX7_TCML_ADDR = 0x007F8000,
404
+ FSL_IMX7_TCML_SIZE = (32 * KiB),
405
+
406
+ FSL_IMX7_OCRAM_S_ADDR = 0x00180000,
407
+ FSL_IMX7_OCRAM_S_SIZE = (32 * KiB),
408
+
409
+ FSL_IMX7_CAAM_MEM_ADDR = 0x00100000,
410
+ FSL_IMX7_CAAM_MEM_SIZE = (32 * KiB),
411
+
412
+ FSL_IMX7_ROM_ADDR = 0x00000000,
413
+ FSL_IMX7_ROM_SIZE = (96 * KiB),
414
};
415
416
enum FslIMX7IRQs {
417
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
418
index XXXXXXX..XXXXXXX 100644
419
--- a/hw/arm/fsl-imx7.c
420
+++ b/hw/arm/fsl-imx7.c
421
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
422
char name[NAME_SIZE];
423
int i;
424
425
+ /*
426
+ * CPUs
427
+ */
428
for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) {
429
snprintf(name, NAME_SIZE, "cpu%d", i);
430
object_initialize_child(obj, name, &s->cpu[i],
431
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
432
TYPE_A15MPCORE_PRIV);
433
434
/*
435
- * GPIOs 1 to 7
436
+ * GPIOs
437
*/
438
for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
439
snprintf(name, NAME_SIZE, "gpio%d", i);
440
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
441
}
442
443
/*
444
- * GPT1, 2, 3, 4
445
+ * GPTs
446
*/
447
for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
448
snprintf(name, NAME_SIZE, "gpt%d", i);
449
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
450
*/
451
object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
452
453
+ /*
454
+ * ECSPIs
455
+ */
456
for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
457
snprintf(name, NAME_SIZE, "spi%d", i + 1);
458
object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
459
}
460
461
-
462
+ /*
463
+ * I2Cs
464
+ */
465
for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
466
snprintf(name, NAME_SIZE, "i2c%d", i + 1);
467
object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
468
}
469
470
/*
471
- * UART
472
+ * UARTs
473
*/
474
for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
475
snprintf(name, NAME_SIZE, "uart%d", i);
476
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
477
}
478
479
/*
480
- * Ethernet
481
+ * Ethernets
482
*/
483
for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
484
snprintf(name, NAME_SIZE, "eth%d", i);
485
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
486
}
487
488
/*
489
- * SDHCI
490
+ * SDHCIs
491
*/
492
for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
493
snprintf(name, NAME_SIZE, "usdhc%d", i);
494
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
495
object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
496
497
/*
498
- * Watchdog
499
+ * Watchdogs
500
*/
501
for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
502
snprintf(name, NAME_SIZE, "wdt%d", i);
503
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
504
*/
505
object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
506
507
+ /*
508
+ * PCIE
509
+ */
510
object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
511
512
+ /*
513
+ * USBs
514
+ */
515
for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
516
snprintf(name, NAME_SIZE, "usb%d", i);
517
object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
518
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
519
return;
520
}
521
522
+ /*
523
+ * CPUs
524
+ */
525
for (i = 0; i < smp_cpus; i++) {
526
o = OBJECT(&s->cpu[i]);
527
528
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
529
* A7MPCORE DAP
530
*/
531
create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR,
532
- 0x100000);
533
+ FSL_IMX7_A7MPCORE_DAP_SIZE);
534
535
/*
536
- * GPT1, 2, 3, 4
537
+ * GPTs
538
*/
539
for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
540
static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = {
541
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
542
FSL_IMX7_GPTn_IRQ[i]));
543
}
544
545
+ /*
546
+ * GPIOs
547
+ */
548
for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
549
static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = {
550
FSL_IMX7_GPIO1_ADDR,
551
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
552
/*
553
* IOMUXC and IOMUXC_LPSR
554
*/
555
- for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) {
556
- static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = {
557
- FSL_IMX7_IOMUXC_ADDR,
558
- FSL_IMX7_IOMUXC_LPSR_ADDR,
559
- };
560
-
561
- snprintf(name, NAME_SIZE, "iomuxc%d", i);
562
- create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i],
563
- FSL_IMX7_IOMUXCn_SIZE);
564
- }
565
+ create_unimplemented_device("iomuxc", FSL_IMX7_IOMUXC_ADDR,
566
+ FSL_IMX7_IOMUXC_SIZE);
567
+ create_unimplemented_device("iomuxc_lspr", FSL_IMX7_IOMUXC_LPSR_ADDR,
568
+ FSL_IMX7_IOMUXC_LPSR_SIZE);
569
570
/*
571
* CCM
572
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
573
sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
574
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
575
576
- /* Initialize all ECSPI */
577
+ /*
578
+ * ECSPIs
579
+ */
580
for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
581
static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = {
582
FSL_IMX7_ECSPI1_ADDR,
583
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
584
FSL_IMX7_SPIn_IRQ[i]));
585
}
586
587
+ /*
588
+ * I2Cs
589
+ */
590
for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
591
static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = {
592
FSL_IMX7_I2C1_ADDR,
593
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
594
}
595
596
/*
597
- * UART
598
+ * UARTs
599
*/
600
for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
601
static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = {
602
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
603
}
604
605
/*
606
- * Ethernet
607
+ * Ethernets
608
*
609
* We must use two loops since phy_connected affects the other interface
610
* and we have to set all properties before calling sysbus_realize().
611
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
612
}
613
614
/*
615
- * USDHC
616
+ * USDHCs
617
*/
618
for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
619
static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = {
620
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
621
* SNVS
622
*/
623
sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
624
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR);
625
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_HP_ADDR);
626
627
/*
628
* SRC
629
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
630
create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
631
632
/*
633
- * Watchdog
634
+ * Watchdogs
635
*/
636
for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
637
static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = {
638
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
639
create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE);
640
641
/*
642
- * PWM
643
+ * PWMs
644
*/
645
- create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE);
646
- create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE);
647
- create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE);
648
- create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE);
649
+ for (i = 0; i < FSL_IMX7_NUM_PWMS; i++) {
650
+ static const hwaddr FSL_IMX7_PWMn_ADDR[FSL_IMX7_NUM_PWMS] = {
651
+ FSL_IMX7_PWM1_ADDR,
652
+ FSL_IMX7_PWM2_ADDR,
653
+ FSL_IMX7_PWM3_ADDR,
654
+ FSL_IMX7_PWM4_ADDR,
655
+ };
656
+
657
+ snprintf(name, NAME_SIZE, "pwm%d", i);
658
+ create_unimplemented_device(name, FSL_IMX7_PWMn_ADDR[i],
659
+ FSL_IMX7_PWMn_SIZE);
31
+ }
660
+ }
32
+
661
33
+ return burst;
662
/*
663
- * CAN
664
+ * CANs
665
*/
666
- create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE);
667
- create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE);
668
+ for (i = 0; i < FSL_IMX7_NUM_CANS; i++) {
669
+ static const hwaddr FSL_IMX7_CANn_ADDR[FSL_IMX7_NUM_CANS] = {
670
+ FSL_IMX7_CAN1_ADDR,
671
+ FSL_IMX7_CAN2_ADDR,
672
+ };
673
+
674
+ snprintf(name, NAME_SIZE, "can%d", i);
675
+ create_unimplemented_device(name, FSL_IMX7_CANn_ADDR[i],
676
+ FSL_IMX7_CANn_SIZE);
677
+ }
678
679
/*
680
- * SAI (Audio SSI (Synchronous Serial Interface))
681
+ * SAIs (Audio SSI (Synchronous Serial Interface))
682
*/
683
- create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR, FSL_IMX7_SAIn_SIZE);
684
- create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR, FSL_IMX7_SAIn_SIZE);
685
- create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR, FSL_IMX7_SAIn_SIZE);
686
+ for (i = 0; i < FSL_IMX7_NUM_SAIS; i++) {
687
+ static const hwaddr FSL_IMX7_SAIn_ADDR[FSL_IMX7_NUM_SAIS] = {
688
+ FSL_IMX7_SAI1_ADDR,
689
+ FSL_IMX7_SAI2_ADDR,
690
+ FSL_IMX7_SAI3_ADDR,
691
+ };
692
+
693
+ snprintf(name, NAME_SIZE, "sai%d", i);
694
+ create_unimplemented_device(name, FSL_IMX7_SAIn_ADDR[i],
695
+ FSL_IMX7_SAIn_SIZE);
696
+ }
697
698
/*
699
* OCOTP
700
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
701
create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
702
FSL_IMX7_OCOTP_SIZE);
703
704
+ /*
705
+ * GPR
706
+ */
707
sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
708
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR);
709
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_IOMUXC_GPR_ADDR);
710
711
+ /*
712
+ * PCIE
713
+ */
714
sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
715
sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
716
717
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
718
irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ);
719
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
720
721
-
722
+ /*
723
+ * USBs
724
+ */
725
for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
726
static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = {
727
FSL_IMX7_USBMISC1_ADDR,
728
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
729
*/
730
create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
731
FSL_IMX7_PCIE_PHY_SIZE);
732
+
34
}
733
}
35
734
36
static bool imx_spi_is_enabled(IMXSPIState *s)
735
static Property fsl_imx7_properties[] = {
37
@@ -XXX,XX +XXX,XX @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
38
IMXSPIState *s = opaque;
39
uint32_t index = offset >> 2;
40
uint32_t change_mask;
41
+ uint32_t burst;
42
43
if (index >= ECSPI_MAX) {
44
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
45
@@ -XXX,XX +XXX,XX @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
46
case ECSPI_CONREG:
47
s->regs[ECSPI_CONREG] = value;
48
49
+ burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
50
+ if (burst % 8) {
51
+ qemu_log_mask(LOG_UNIMP,
52
+ "[%s]%s: burst length %d not supported: rounding up to next multiple of 8\n",
53
+ TYPE_IMX_SPI, __func__, burst);
54
+ }
55
+
56
if (!imx_spi_is_enabled(s)) {
57
/* device is disabled, so this is a soft reset */
58
imx_spi_soft_reset(s);
59
--
736
--
60
2.20.1
737
2.34.1
61
62
diff view generated by jsdifflib
[PULL 11/21] hw/ssi: imx_spi: Disable chip selects when controller is disabled
[PULL 15/24] Add i.MX7 missing TZ devices and memory regions
1
From: Xuzhou Cheng <xuzhou.cheng@windriver.com>
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
2
3
When a write to ECSPI_CONREG register to disable the SPI controller,
3
* Add TZASC as unimplemented device.
4
imx_spi_soft_reset() is called to reset the controller, but chip
4
- Allow bare metal application to access this (unimplemented) device
5
select lines should have been disabled, otherwise the state machine
5
* Add CSU as unimplemented device.
6
of any devices (e.g.: SPI flashes) connected to the SPI master is
6
- Allow bare metal application to access this (unimplemented) device
7
stuck to its last state and responds incorrectly to any follow-up
7
* Add various memory segments
8
commands.
8
- OCRAM
9
- OCRAM EPDC
10
- OCRAM PXP
11
- OCRAM S
12
- ROM
13
- CAAM
9
14
10
Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller")
15
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
11
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
16
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Signed-off-by: Bin Meng <bin.meng@windriver.com>
17
Message-id: f887a3483996ba06d40bd62ffdfb0ecf68621987.1692964892.git.jcd@tribudubois.net
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20210129132323.30946-8-bmeng.cn@gmail.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
19
---
17
hw/ssi/imx_spi.c | 6 ++++++
20
include/hw/arm/fsl-imx7.h | 7 +++++
18
1 file changed, 6 insertions(+)
21
hw/arm/fsl-imx7.c | 63 +++++++++++++++++++++++++++++++++++++++
22
2 files changed, 70 insertions(+)
19
23
20
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
24
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
21
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/ssi/imx_spi.c
26
--- a/include/hw/arm/fsl-imx7.h
23
+++ b/hw/ssi/imx_spi.c
27
+++ b/include/hw/arm/fsl-imx7.h
24
@@ -XXX,XX +XXX,XX @@ static void imx_spi_common_reset(IMXSPIState *s)
28
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
25
29
IMX7GPRState gpr;
26
static void imx_spi_soft_reset(IMXSPIState *s)
30
ChipideaState usb[FSL_IMX7_NUM_USBS];
27
{
31
DesignwarePCIEHost pcie;
28
+ int i;
32
+ MemoryRegion rom;
33
+ MemoryRegion caam;
34
+ MemoryRegion ocram;
35
+ MemoryRegion ocram_epdc;
36
+ MemoryRegion ocram_pxp;
37
+ MemoryRegion ocram_s;
29
+
38
+
30
imx_spi_common_reset(s);
39
uint32_t phy_num[FSL_IMX7_NUM_ETHS];
31
40
bool phy_connected[FSL_IMX7_NUM_ETHS];
32
imx_spi_update_irq(s);
41
};
42
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/arm/fsl-imx7.c
45
+++ b/hw/arm/fsl-imx7.c
46
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
47
create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
48
FSL_IMX7_PCIE_PHY_SIZE);
49
50
+ /*
51
+ * CSU
52
+ */
53
+ create_unimplemented_device("csu", FSL_IMX7_CSU_ADDR,
54
+ FSL_IMX7_CSU_SIZE);
33
+
55
+
34
+ for (i = 0; i < ECSPI_NUM_CS; i++) {
56
+ /*
35
+ qemu_set_irq(s->cs_lines[i], 1);
57
+ * TZASC
36
+ }
58
+ */
59
+ create_unimplemented_device("tzasc", FSL_IMX7_TZASC_ADDR,
60
+ FSL_IMX7_TZASC_SIZE);
61
+
62
+ /*
63
+ * OCRAM memory
64
+ */
65
+ memory_region_init_ram(&s->ocram, NULL, "imx7.ocram",
66
+ FSL_IMX7_OCRAM_MEM_SIZE,
67
+ &error_abort);
68
+ memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_MEM_ADDR,
69
+ &s->ocram);
70
+
71
+ /*
72
+ * OCRAM EPDC memory
73
+ */
74
+ memory_region_init_ram(&s->ocram_epdc, NULL, "imx7.ocram_epdc",
75
+ FSL_IMX7_OCRAM_EPDC_SIZE,
76
+ &error_abort);
77
+ memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_EPDC_ADDR,
78
+ &s->ocram_epdc);
79
+
80
+ /*
81
+ * OCRAM PXP memory
82
+ */
83
+ memory_region_init_ram(&s->ocram_pxp, NULL, "imx7.ocram_pxp",
84
+ FSL_IMX7_OCRAM_PXP_SIZE,
85
+ &error_abort);
86
+ memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_PXP_ADDR,
87
+ &s->ocram_pxp);
88
+
89
+ /*
90
+ * OCRAM_S memory
91
+ */
92
+ memory_region_init_ram(&s->ocram_s, NULL, "imx7.ocram_s",
93
+ FSL_IMX7_OCRAM_S_SIZE,
94
+ &error_abort);
95
+ memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_S_ADDR,
96
+ &s->ocram_s);
97
+
98
+ /*
99
+ * ROM memory
100
+ */
101
+ memory_region_init_rom(&s->rom, OBJECT(dev), "imx7.rom",
102
+ FSL_IMX7_ROM_SIZE, &error_abort);
103
+ memory_region_add_subregion(get_system_memory(), FSL_IMX7_ROM_ADDR,
104
+ &s->rom);
105
+
106
+ /*
107
+ * CAAM memory
108
+ */
109
+ memory_region_init_rom(&s->caam, OBJECT(dev), "imx7.caam",
110
+ FSL_IMX7_CAAM_MEM_SIZE, &error_abort);
111
+ memory_region_add_subregion(get_system_memory(), FSL_IMX7_CAAM_MEM_ADDR,
112
+ &s->caam);
37
}
113
}
38
114
39
static void imx_spi_reset(DeviceState *dev)
115
static Property fsl_imx7_properties[] = {
40
--
116
--
41
2.20.1
117
2.34.1
42
118
43
119
diff view generated by jsdifflib
[PULL 16/21] hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ
[PULL 16/24] Add i.MX7 SRC device implementation
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
2
3
The STM32F405 SoC uses an OR gate on its ADC IRQs.
3
The SRC device is normally used to start the secondary CPU.
4
4
5
Fixes: 529fc5fd3e1 ("hw/arm: Add the STM32F4xx SoC")
5
When running Linux directly, QEMU is emulating a PSCI interface that UBOOT
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
is installing at boot time and therefore the fact that the SRC device is
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
unimplemented is hidden as Qemu respond directly to PSCI requets without
8
Message-id: 20210131184449.382425-2-f4bug@amsat.org
8
using the SRC device.
9
10
But if you try to run a more bare metal application (maybe uboot itself),
11
then it is not possible to start the secondary CPU as the SRC is an
12
unimplemented device.
13
14
This patch adds the ability to start the secondary CPU through the SRC
15
device so that you can use this feature in bare metal applications.
16
17
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Message-id: ce9a0162defd2acee5dc7f8a674743de0cded569.1692964892.git.jcd@tribudubois.net
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
21
---
11
hw/arm/Kconfig | 1 +
22
include/hw/arm/fsl-imx7.h | 3 +-
12
1 file changed, 1 insertion(+)
23
include/hw/misc/imx7_src.h | 66 +++++++++
13
24
hw/arm/fsl-imx7.c | 8 +-
14
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
25
hw/misc/imx7_src.c | 276 +++++++++++++++++++++++++++++++++++++
26
hw/misc/meson.build | 1 +
27
hw/misc/trace-events | 4 +
28
6 files changed, 356 insertions(+), 2 deletions(-)
29
create mode 100644 include/hw/misc/imx7_src.h
30
create mode 100644 hw/misc/imx7_src.c
31
32
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
15
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/Kconfig
34
--- a/include/hw/arm/fsl-imx7.h
17
+++ b/hw/arm/Kconfig
35
+++ b/include/hw/arm/fsl-imx7.h
18
@@ -XXX,XX +XXX,XX @@ config STM32F205_SOC
36
@@ -XXX,XX +XXX,XX @@
19
config STM32F405_SOC
37
#include "hw/misc/imx7_ccm.h"
20
bool
38
#include "hw/misc/imx7_snvs.h"
21
select ARM_V7M
39
#include "hw/misc/imx7_gpr.h"
22
+ select OR_IRQ
40
+#include "hw/misc/imx7_src.h"
23
select STM32F4XX_SYSCFG
41
#include "hw/watchdog/wdt_imx2.h"
24
select STM32F4XX_EXTI
42
#include "hw/gpio/imx_gpio.h"
25
43
#include "hw/char/imx_serial.h"
44
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
45
IMX7CCMState ccm;
46
IMX7AnalogState analog;
47
IMX7SNVSState snvs;
48
+ IMX7SRCState src;
49
IMXGPCv2State gpcv2;
50
IMXSPIState spi[FSL_IMX7_NUM_ECSPIS];
51
IMXI2CState i2c[FSL_IMX7_NUM_I2CS];
52
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
53
FSL_IMX7_GPC_ADDR = 0x303A0000,
54
55
FSL_IMX7_SRC_ADDR = 0x30390000,
56
- FSL_IMX7_SRC_SIZE = (4 * KiB),
57
58
FSL_IMX7_CCM_ADDR = 0x30380000,
59
60
diff --git a/include/hw/misc/imx7_src.h b/include/hw/misc/imx7_src.h
61
new file mode 100644
62
index XXXXXXX..XXXXXXX
63
--- /dev/null
64
+++ b/include/hw/misc/imx7_src.h
65
@@ -XXX,XX +XXX,XX @@
66
+/*
67
+ * IMX7 System Reset Controller
68
+ *
69
+ * Copyright (C) 2023 Jean-Christophe Dubois <jcd@tribudubois.net>
70
+ *
71
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
72
+ * See the COPYING file in the top-level directory.
73
+ */
74
+
75
+#ifndef IMX7_SRC_H
76
+#define IMX7_SRC_H
77
+
78
+#include "hw/sysbus.h"
79
+#include "qemu/bitops.h"
80
+#include "qom/object.h"
81
+
82
+#define SRC_SCR 0
83
+#define SRC_A7RCR0 1
84
+#define SRC_A7RCR1 2
85
+#define SRC_M4RCR 3
86
+#define SRC_ERCR 5
87
+#define SRC_HSICPHY_RCR 7
88
+#define SRC_USBOPHY1_RCR 8
89
+#define SRC_USBOPHY2_RCR 9
90
+#define SRC_MPIPHY_RCR 10
91
+#define SRC_PCIEPHY_RCR 11
92
+#define SRC_SBMR1 22
93
+#define SRC_SRSR 23
94
+#define SRC_SISR 26
95
+#define SRC_SIMR 27
96
+#define SRC_SBMR2 28
97
+#define SRC_GPR1 29
98
+#define SRC_GPR2 30
99
+#define SRC_GPR3 31
100
+#define SRC_GPR4 32
101
+#define SRC_GPR5 33
102
+#define SRC_GPR6 34
103
+#define SRC_GPR7 35
104
+#define SRC_GPR8 36
105
+#define SRC_GPR9 37
106
+#define SRC_GPR10 38
107
+#define SRC_MAX 39
108
+
109
+/* SRC_A7SCR1 */
110
+#define R_CORE1_ENABLE_SHIFT 1
111
+#define R_CORE1_ENABLE_LENGTH 1
112
+/* SRC_A7SCR0 */
113
+#define R_CORE1_RST_SHIFT 5
114
+#define R_CORE1_RST_LENGTH 1
115
+#define R_CORE0_RST_SHIFT 4
116
+#define R_CORE0_RST_LENGTH 1
117
+
118
+#define TYPE_IMX7_SRC "imx7.src"
119
+OBJECT_DECLARE_SIMPLE_TYPE(IMX7SRCState, IMX7_SRC)
120
+
121
+struct IMX7SRCState {
122
+ /* <private> */
123
+ SysBusDevice parent_obj;
124
+
125
+ /* <public> */
126
+ MemoryRegion iomem;
127
+
128
+ uint32_t regs[SRC_MAX];
129
+};
130
+
131
+#endif /* IMX7_SRC_H */
132
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
133
index XXXXXXX..XXXXXXX 100644
134
--- a/hw/arm/fsl-imx7.c
135
+++ b/hw/arm/fsl-imx7.c
136
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
137
*/
138
object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
139
140
+ /*
141
+ * SRC
142
+ */
143
+ object_initialize_child(obj, "src", &s->src, TYPE_IMX7_SRC);
144
+
145
/*
146
* ECSPIs
147
*/
148
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
149
/*
150
* SRC
151
*/
152
- create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
153
+ sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort);
154
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX7_SRC_ADDR);
155
156
/*
157
* Watchdogs
158
diff --git a/hw/misc/imx7_src.c b/hw/misc/imx7_src.c
159
new file mode 100644
160
index XXXXXXX..XXXXXXX
161
--- /dev/null
162
+++ b/hw/misc/imx7_src.c
163
@@ -XXX,XX +XXX,XX @@
164
+/*
165
+ * IMX7 System Reset Controller
166
+ *
167
+ * Copyright (c) 2023 Jean-Christophe Dubois <jcd@tribudubois.net>
168
+ *
169
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
170
+ * See the COPYING file in the top-level directory.
171
+ *
172
+ */
173
+
174
+#include "qemu/osdep.h"
175
+#include "hw/misc/imx7_src.h"
176
+#include "migration/vmstate.h"
177
+#include "qemu/bitops.h"
178
+#include "qemu/log.h"
179
+#include "qemu/main-loop.h"
180
+#include "qemu/module.h"
181
+#include "target/arm/arm-powerctl.h"
182
+#include "hw/core/cpu.h"
183
+#include "hw/registerfields.h"
184
+
185
+#include "trace.h"
186
+
187
+static const char *imx7_src_reg_name(uint32_t reg)
188
+{
189
+ static char unknown[20];
190
+
191
+ switch (reg) {
192
+ case SRC_SCR:
193
+ return "SRC_SCR";
194
+ case SRC_A7RCR0:
195
+ return "SRC_A7RCR0";
196
+ case SRC_A7RCR1:
197
+ return "SRC_A7RCR1";
198
+ case SRC_M4RCR:
199
+ return "SRC_M4RCR";
200
+ case SRC_ERCR:
201
+ return "SRC_ERCR";
202
+ case SRC_HSICPHY_RCR:
203
+ return "SRC_HSICPHY_RCR";
204
+ case SRC_USBOPHY1_RCR:
205
+ return "SRC_USBOPHY1_RCR";
206
+ case SRC_USBOPHY2_RCR:
207
+ return "SRC_USBOPHY2_RCR";
208
+ case SRC_PCIEPHY_RCR:
209
+ return "SRC_PCIEPHY_RCR";
210
+ case SRC_SBMR1:
211
+ return "SRC_SBMR1";
212
+ case SRC_SRSR:
213
+ return "SRC_SRSR";
214
+ case SRC_SISR:
215
+ return "SRC_SISR";
216
+ case SRC_SIMR:
217
+ return "SRC_SIMR";
218
+ case SRC_SBMR2:
219
+ return "SRC_SBMR2";
220
+ case SRC_GPR1:
221
+ return "SRC_GPR1";
222
+ case SRC_GPR2:
223
+ return "SRC_GPR2";
224
+ case SRC_GPR3:
225
+ return "SRC_GPR3";
226
+ case SRC_GPR4:
227
+ return "SRC_GPR4";
228
+ case SRC_GPR5:
229
+ return "SRC_GPR5";
230
+ case SRC_GPR6:
231
+ return "SRC_GPR6";
232
+ case SRC_GPR7:
233
+ return "SRC_GPR7";
234
+ case SRC_GPR8:
235
+ return "SRC_GPR8";
236
+ case SRC_GPR9:
237
+ return "SRC_GPR9";
238
+ case SRC_GPR10:
239
+ return "SRC_GPR10";
240
+ default:
241
+ sprintf(unknown, "%u ?", reg);
242
+ return unknown;
243
+ }
244
+}
245
+
246
+static const VMStateDescription vmstate_imx7_src = {
247
+ .name = TYPE_IMX7_SRC,
248
+ .version_id = 1,
249
+ .minimum_version_id = 1,
250
+ .fields = (VMStateField[]) {
251
+ VMSTATE_UINT32_ARRAY(regs, IMX7SRCState, SRC_MAX),
252
+ VMSTATE_END_OF_LIST()
253
+ },
254
+};
255
+
256
+static void imx7_src_reset(DeviceState *dev)
257
+{
258
+ IMX7SRCState *s = IMX7_SRC(dev);
259
+
260
+ memset(s->regs, 0, sizeof(s->regs));
261
+
262
+ /* Set reset values */
263
+ s->regs[SRC_SCR] = 0xA0;
264
+ s->regs[SRC_SRSR] = 0x1;
265
+ s->regs[SRC_SIMR] = 0x1F;
266
+}
267
+
268
+static uint64_t imx7_src_read(void *opaque, hwaddr offset, unsigned size)
269
+{
270
+ uint32_t value = 0;
271
+ IMX7SRCState *s = (IMX7SRCState *)opaque;
272
+ uint32_t index = offset >> 2;
273
+
274
+ if (index < SRC_MAX) {
275
+ value = s->regs[index];
276
+ } else {
277
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
278
+ HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset);
279
+ }
280
+
281
+ trace_imx7_src_read(imx7_src_reg_name(index), value);
282
+
283
+ return value;
284
+}
285
+
286
+
287
+/*
288
+ * The reset is asynchronous so we need to defer clearing the reset
289
+ * bit until the work is completed.
290
+ */
291
+
292
+struct SRCSCRResetInfo {
293
+ IMX7SRCState *s;
294
+ uint32_t reset_bit;
295
+};
296
+
297
+static void imx7_clear_reset_bit(CPUState *cpu, run_on_cpu_data data)
298
+{
299
+ struct SRCSCRResetInfo *ri = data.host_ptr;
300
+ IMX7SRCState *s = ri->s;
301
+
302
+ assert(qemu_mutex_iothread_locked());
303
+
304
+ s->regs[SRC_A7RCR0] = deposit32(s->regs[SRC_A7RCR0], ri->reset_bit, 1, 0);
305
+
306
+ trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]);
307
+
308
+ g_free(ri);
309
+}
310
+
311
+static void imx7_defer_clear_reset_bit(uint32_t cpuid,
312
+ IMX7SRCState *s,
313
+ uint32_t reset_shift)
314
+{
315
+ struct SRCSCRResetInfo *ri;
316
+ CPUState *cpu = arm_get_cpu_by_id(cpuid);
317
+
318
+ if (!cpu) {
319
+ return;
320
+ }
321
+
322
+ ri = g_new(struct SRCSCRResetInfo, 1);
323
+ ri->s = s;
324
+ ri->reset_bit = reset_shift;
325
+
326
+ async_run_on_cpu(cpu, imx7_clear_reset_bit, RUN_ON_CPU_HOST_PTR(ri));
327
+}
328
+
329
+
330
+static void imx7_src_write(void *opaque, hwaddr offset, uint64_t value,
331
+ unsigned size)
332
+{
333
+ IMX7SRCState *s = (IMX7SRCState *)opaque;
334
+ uint32_t index = offset >> 2;
335
+ long unsigned int change_mask;
336
+ uint32_t current_value = value;
337
+
338
+ if (index >= SRC_MAX) {
339
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
340
+ HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset);
341
+ return;
342
+ }
343
+
344
+ trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]);
345
+
346
+ change_mask = s->regs[index] ^ (uint32_t)current_value;
347
+
348
+ switch (index) {
349
+ case SRC_A7RCR0:
350
+ if (FIELD_EX32(change_mask, CORE0, RST)) {
351
+ arm_reset_cpu(0);
352
+ imx7_defer_clear_reset_bit(0, s, R_CORE0_RST_SHIFT);
353
+ }
354
+ if (FIELD_EX32(change_mask, CORE1, RST)) {
355
+ arm_reset_cpu(1);
356
+ imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT);
357
+ }
358
+ s->regs[index] = current_value;
359
+ break;
360
+ case SRC_A7RCR1:
361
+ /*
362
+ * On real hardware when the system reset controller starts a
363
+ * secondary CPU it runs through some boot ROM code which reads
364
+ * the SRC_GPRX registers controlling the start address and branches
365
+ * to it.
366
+ * Here we are taking a short cut and branching directly to the
367
+ * requested address (we don't want to run the boot ROM code inside
368
+ * QEMU)
369
+ */
370
+ if (FIELD_EX32(change_mask, CORE1, ENABLE)) {
371
+ if (FIELD_EX32(current_value, CORE1, ENABLE)) {
372
+ /* CORE 1 is brought up */
373
+ arm_set_cpu_on(1, s->regs[SRC_GPR3], s->regs[SRC_GPR4],
374
+ 3, false);
375
+ } else {
376
+ /* CORE 1 is shut down */
377
+ arm_set_cpu_off(1);
378
+ }
379
+ /* We clear the reset bits as the processor changed state */
380
+ imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT);
381
+ clear_bit(R_CORE1_RST_SHIFT, &change_mask);
382
+ }
383
+ s->regs[index] = current_value;
384
+ break;
385
+ default:
386
+ s->regs[index] = current_value;
387
+ break;
388
+ }
389
+}
390
+
391
+static const struct MemoryRegionOps imx7_src_ops = {
392
+ .read = imx7_src_read,
393
+ .write = imx7_src_write,
394
+ .endianness = DEVICE_NATIVE_ENDIAN,
395
+ .valid = {
396
+ /*
397
+ * Our device would not work correctly if the guest was doing
398
+ * unaligned access. This might not be a limitation on the real
399
+ * device but in practice there is no reason for a guest to access
400
+ * this device unaligned.
401
+ */
402
+ .min_access_size = 4,
403
+ .max_access_size = 4,
404
+ .unaligned = false,
405
+ },
406
+};
407
+
408
+static void imx7_src_realize(DeviceState *dev, Error **errp)
409
+{
410
+ IMX7SRCState *s = IMX7_SRC(dev);
411
+
412
+ memory_region_init_io(&s->iomem, OBJECT(dev), &imx7_src_ops, s,
413
+ TYPE_IMX7_SRC, 0x1000);
414
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
415
+}
416
+
417
+static void imx7_src_class_init(ObjectClass *klass, void *data)
418
+{
419
+ DeviceClass *dc = DEVICE_CLASS(klass);
420
+
421
+ dc->realize = imx7_src_realize;
422
+ dc->reset = imx7_src_reset;
423
+ dc->vmsd = &vmstate_imx7_src;
424
+ dc->desc = "i.MX6 System Reset Controller";
425
+}
426
+
427
+static const TypeInfo imx7_src_info = {
428
+ .name = TYPE_IMX7_SRC,
429
+ .parent = TYPE_SYS_BUS_DEVICE,
430
+ .instance_size = sizeof(IMX7SRCState),
431
+ .class_init = imx7_src_class_init,
432
+};
433
+
434
+static void imx7_src_register_types(void)
435
+{
436
+ type_register_static(&imx7_src_info);
437
+}
438
+
439
+type_init(imx7_src_register_types)
440
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
441
index XXXXXXX..XXXXXXX 100644
442
--- a/hw/misc/meson.build
443
+++ b/hw/misc/meson.build
444
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_IMX', if_true: files(
445
'imx6_src.c',
446
'imx6ul_ccm.c',
447
'imx7_ccm.c',
448
+ 'imx7_src.c',
449
'imx7_gpr.c',
450
'imx7_snvs.c',
451
'imx_ccm.c',
452
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
453
index XXXXXXX..XXXXXXX 100644
454
--- a/hw/misc/trace-events
455
+++ b/hw/misc/trace-events
456
@@ -XXX,XX +XXX,XX @@ ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d"
457
ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32
458
ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32
459
460
+# imx7_src.c
461
+imx7_src_read(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32
462
+imx7_src_write(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32
463
+
464
# iotkit-sysinfo.c
465
iotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
466
iotkit_sysinfo_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
26
--
467
--
27
2.20.1
468
2.34.1
28
29
diff view generated by jsdifflib
New patch
[PULL 17/24] target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS
1
The architecture requires (R_TYTWB) that an attempt to return from EL3
2
when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This
3
enforces that the CPU can't ever be executing below EL3 with the
4
NSE,NS bits indicating an invalid security state.)
1
5
6
We were missing this check; add it.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20230807150618.101357-1-peter.maydell@linaro.org
11
---
12
target/arm/tcg/helper-a64.c | 9 +++++++++
13
1 file changed, 9 insertions(+)
14
15
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/tcg/helper-a64.c
18
+++ b/target/arm/tcg/helper-a64.c
19
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
20
spsr &= ~PSTATE_SS;
21
}
22
23
+ /*
24
+ * FEAT_RME forbids return from EL3 with an invalid security state.
25
+ * We don't need an explicit check for FEAT_RME here because we enforce
26
+ * in scr_write() that you can't set the NSE bit without it.
27
+ */
28
+ if (cur_el == 3 && (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) == SCR_NSE) {
29
+ goto illegal_return;
30
+ }
31
+
32
new_el = el_from_spsr(spsr);
33
if (new_el == -1) {
34
goto illegal_return;
35
--
36
2.34.1
diff view generated by jsdifflib
[PULL 13/21] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic
[PULL 18/24] hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()
1
From: Bin Meng <bin.meng@windriver.com>
1
In the m48t59 device we almost always use 64-bit arithmetic when
2
dealing with time_t deltas. The one exception is in set_alarm(),
3
which currently uses a plain 'int' to hold the difference between two
4
time_t values. Switch to int64_t instead to avoid any possible
5
overflow issues.
2
6
3
For the ECSPIx_CONREG register BURST_LENGTH field, the manual says:
4
5
0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in second word.
6
0x021 A SPI burst contains the 2 LSB in first word and all 32 bits in second word.
7
8
Current logic uses either s->burst_length or 32, whichever smaller,
9
to determine how many bits it should read from the tx fifo each time.
10
For example, for a 48 bit burst length, current logic transfers the
11
first 32 bit from the first word in the tx fifo, followed by a 16
12
bit from the second word in the tx fifo, which is wrong. The correct
13
logic should be: transfer the first 16 bit from the first word in
14
the tx fifo, followed by a 32 bit from the second word in the tx fifo.
15
16
With this change, SPI flash can be successfully probed by U-Boot on
17
imx6 sabrelite board.
18
19
=> sf probe
20
SF: Detected sst25vf016b with page size 256 Bytes, erase size 4 KiB, total 2 MiB
21
22
Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller")
23
Signed-off-by: Bin Meng <bin.meng@windriver.com>
24
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
25
Message-id: 20210129132323.30946-10-bmeng.cn@gmail.com
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
27
---
9
---
28
hw/ssi/imx_spi.c | 2 +-
10
hw/rtc/m48t59.c | 2 +-
29
1 file changed, 1 insertion(+), 1 deletion(-)
11
1 file changed, 1 insertion(+), 1 deletion(-)
30
12
31
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
13
diff --git a/hw/rtc/m48t59.c b/hw/rtc/m48t59.c
32
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/ssi/imx_spi.c
15
--- a/hw/rtc/m48t59.c
34
+++ b/hw/ssi/imx_spi.c
16
+++ b/hw/rtc/m48t59.c
35
@@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
17
@@ -XXX,XX +XXX,XX @@ static void alarm_cb (void *opaque)
36
18
37
DPRINTF("data tx:0x%08x\n", tx);
19
static void set_alarm(M48t59State *NVRAM)
38
20
{
39
- tx_burst = MIN(s->burst_length, 32);
21
- int diff;
40
+ tx_burst = (s->burst_length % 32) ? : 32;
22
+ int64_t diff;
41
23
if (NVRAM->alrm_timer != NULL) {
42
rx = 0;
24
timer_del(NVRAM->alrm_timer);
43
25
diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
44
--
26
--
45
2.20.1
27
2.34.1
46
28
47
29
diff view generated by jsdifflib
[PULL 14/21] hw/ssi: imx_spi: Correct tx and rx fifo endianness
[PULL 19/24] hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec
1
From: Bin Meng <bin.meng@windriver.com>
1
In the twl92230 device, use int64_t for the two state fields
2
sec_offset and alm_sec, because we set these to values that
3
are either time_t or differences between two time_t values.
2
4
3
The endianness of data exchange between tx and rx fifo is incorrect.
5
These fields aren't saved in vmstate anywhere, so we can
4
Earlier bytes are supposed to show up on MSB and later bytes on LSB,
6
safely widen them.
5
ie: in big endian. The manual does not explicitly say this, but the
6
U-Boot and Linux driver codes have a swap on the data transferred
7
to tx fifo and from rx fifo.
8
7
9
With this change, U-Boot read from / write to SPI flash tests pass.
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
---
11
hw/rtc/twl92230.c | 4 ++--
12
1 file changed, 2 insertions(+), 2 deletions(-)
10
13
11
=> sf test 1ff000 1000
14
diff --git a/hw/rtc/twl92230.c b/hw/rtc/twl92230.c
12
SPI flash test:
13
0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps
14
1 check: 3 ticks, 1333 KiB/s 10.664 Mbps
15
2 write: 235 ticks, 17 KiB/s 0.136 Mbps
16
3 read: 2 ticks, 2000 KiB/s 16.000 Mbps
17
Test passed
18
0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps
19
1 check: 3 ticks, 1333 KiB/s 10.664 Mbps
20
2 write: 235 ticks, 17 KiB/s 0.136 Mbps
21
3 read: 2 ticks, 2000 KiB/s 16.000 Mbps
22
23
Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller")
24
Signed-off-by: Bin Meng <bin.meng@windriver.com>
25
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
26
Message-id: 20210129132323.30946-11-bmeng.cn@gmail.com
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
---
29
hw/ssi/imx_spi.c | 7 ++-----
30
1 file changed, 2 insertions(+), 5 deletions(-)
31
32
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
33
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/ssi/imx_spi.c
16
--- a/hw/rtc/twl92230.c
35
+++ b/hw/ssi/imx_spi.c
17
+++ b/hw/rtc/twl92230.c
36
@@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
18
@@ -XXX,XX +XXX,XX @@ struct MenelausState {
37
19
struct tm tm;
38
while (!fifo32_is_empty(&s->tx_fifo)) {
20
struct tm new;
39
int tx_burst = 0;
21
struct tm alm;
40
- int index = 0;
22
- int sec_offset;
41
23
- int alm_sec;
42
if (s->burst_length <= 0) {
24
+ int64_t sec_offset;
43
s->burst_length = imx_spi_burst_length(s);
25
+ int64_t alm_sec;
44
@@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
26
int next_comp;
45
rx = 0;
27
} rtc;
46
28
uint16_t rtc_next_vmstate;
47
while (tx_burst > 0) {
48
- uint8_t byte = tx & 0xff;
49
+ uint8_t byte = tx >> (tx_burst - 8);
50
51
DPRINTF("writing 0x%02x\n", (uint32_t)byte);
52
53
@@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
54
55
DPRINTF("0x%02x read\n", (uint32_t)byte);
56
57
- tx = tx >> 8;
58
- rx |= (byte << (index * 8));
59
+ rx = (rx << 8) | byte;
60
61
/* Remove 8 bits from the actual burst */
62
tx_burst -= 8;
63
s->burst_length -= 8;
64
- index++;
65
}
66
67
DPRINTF("data rx:0x%08x\n", rx);
68
--
29
--
69
2.20.1
30
2.34.1
70
31
71
32
diff view generated by jsdifflib
[PULL 05/21] hw/ssi: imx_spi: Use a macro for number of chip selects supported
[PULL 20/24] hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference
1
From: Bin Meng <bin.meng@windriver.com>
1
In the aspeed_rtc device we store a difference between two time_t
2
values in an 'int'. This is not really correct when time_t could
3
be 64 bits. Enlarge the field to 'int64_t'.
2
4
3
Avoid using a magic number (4) everywhere for the number of chip
5
This is a migration compatibility break for the aspeed boards.
4
selects supported.
6
While we are changing the vmstate, remove the accidental
7
duplicate of the offset field.
5
8
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Juan Quintela <quintela@redhat.com>
10
Message-id: 20210129132323.30946-2-bmeng.cn@gmail.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Cédric Le Goater <clg@kaod.org>
12
---
11
---
13
include/hw/ssi/imx_spi.h | 5 ++++-
12
include/hw/rtc/aspeed_rtc.h | 2 +-
14
hw/ssi/imx_spi.c | 4 ++--
13
hw/rtc/aspeed_rtc.c | 5 ++---
15
2 files changed, 6 insertions(+), 3 deletions(-)
14
2 files changed, 3 insertions(+), 4 deletions(-)
16
15
17
diff --git a/include/hw/ssi/imx_spi.h b/include/hw/ssi/imx_spi.h
16
diff --git a/include/hw/rtc/aspeed_rtc.h b/include/hw/rtc/aspeed_rtc.h
18
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/ssi/imx_spi.h
18
--- a/include/hw/rtc/aspeed_rtc.h
20
+++ b/include/hw/ssi/imx_spi.h
19
+++ b/include/hw/rtc/aspeed_rtc.h
21
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ struct AspeedRtcState {
22
23
#define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH)
24
25
+/* number of chip selects supported */
26
+#define ECSPI_NUM_CS 4
27
+
28
#define TYPE_IMX_SPI "imx.spi"
29
OBJECT_DECLARE_SIMPLE_TYPE(IMXSPIState, IMX_SPI)
30
31
@@ -XXX,XX +XXX,XX @@ struct IMXSPIState {
32
33
qemu_irq irq;
21
qemu_irq irq;
34
22
35
- qemu_irq cs_lines[4];
23
uint32_t reg[0x18];
36
+ qemu_irq cs_lines[ECSPI_NUM_CS];
24
- int offset;
37
25
+ int64_t offset;
38
SSIBus *bus;
26
39
27
};
40
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
28
29
diff --git a/hw/rtc/aspeed_rtc.c b/hw/rtc/aspeed_rtc.c
41
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/ssi/imx_spi.c
31
--- a/hw/rtc/aspeed_rtc.c
43
+++ b/hw/ssi/imx_spi.c
32
+++ b/hw/rtc/aspeed_rtc.c
44
@@ -XXX,XX +XXX,XX @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
33
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_rtc_ops = {
45
34
46
/* We are in master mode */
35
static const VMStateDescription vmstate_aspeed_rtc = {
47
36
.name = TYPE_ASPEED_RTC,
48
- for (i = 0; i < 4; i++) {
37
- .version_id = 1,
49
+ for (i = 0; i < ECSPI_NUM_CS; i++) {
38
+ .version_id = 2,
50
qemu_set_irq(s->cs_lines[i],
39
.fields = (VMStateField[]) {
51
i == imx_spi_selected_channel(s) ? 0 : 1);
40
VMSTATE_UINT32_ARRAY(reg, AspeedRtcState, 0x18),
52
}
41
- VMSTATE_INT32(offset, AspeedRtcState),
53
@@ -XXX,XX +XXX,XX @@ static void imx_spi_realize(DeviceState *dev, Error **errp)
42
- VMSTATE_INT32(offset, AspeedRtcState),
54
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
43
+ VMSTATE_INT64(offset, AspeedRtcState),
55
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
44
VMSTATE_END_OF_LIST()
56
57
- for (i = 0; i < 4; ++i) {
58
+ for (i = 0; i < ECSPI_NUM_CS; ++i) {
59
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]);
60
}
45
}
61
46
};
62
--
47
--
63
2.20.1
48
2.34.1
64
49
65
50
diff view generated by jsdifflib
[PULL 06/21] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset()
[PULL 21/24] rtc: Use time_t for passing and returning time offsets
1
From: Bin Meng <bin.meng@windriver.com>
1
The functions qemu_get_timedate() and qemu_timedate_diff() take
2
and return a time offset as an integer. Coverity points out that
3
means that when an RTC device implementation holds an offset
4
as a time_t, as the m48t59 does, the time_t will get truncated.
5
(CID 1507157, 1517772).
2
6
3
Usually the approach is that the device on the other end of the line
7
The functions work with time_t internally, so make them use that type
4
is going to reset its state anyway, so there's no need to actively
8
in their APIs.
5
signal an irq line change during the reset hook.
6
9
7
Move imx_spi_update_irq() out of imx_spi_reset(), to a new function
10
Note that this won't help any Y2038 issues where either the device
8
imx_spi_soft_reset() that is called when the controller is disabled.
11
model itself is keeping the offset in a 32-bit integer, or where the
12
hardware under emulation has Y2038 or other rollover problems. If we
13
missed any cases of the former then hopefully Coverity will warn us
14
about them since after this patch we'd be truncating a time_t in
15
assignments from qemu_timedate_diff().)
9
16
10
Signed-off-by: Bin Meng <bin.meng@windriver.com>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20210129132323.30946-3-bmeng.cn@gmail.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
---
19
---
15
hw/ssi/imx_spi.c | 14 ++++++++++----
20
include/sysemu/rtc.h | 4 ++--
16
1 file changed, 10 insertions(+), 4 deletions(-)
21
softmmu/rtc.c | 4 ++--
22
2 files changed, 4 insertions(+), 4 deletions(-)
17
23
18
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
24
diff --git a/include/sysemu/rtc.h b/include/sysemu/rtc.h
19
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/ssi/imx_spi.c
26
--- a/include/sysemu/rtc.h
21
+++ b/hw/ssi/imx_spi.c
27
+++ b/include/sysemu/rtc.h
22
@@ -XXX,XX +XXX,XX @@ static void imx_spi_reset(DeviceState *dev)
28
@@ -XXX,XX +XXX,XX @@
23
imx_spi_rxfifo_reset(s);
29
* The behaviour of the clock whose value this function returns will
24
imx_spi_txfifo_reset(s);
30
* depend on the -rtc command line option passed by the user.
25
31
*/
26
- imx_spi_update_irq(s);
32
-void qemu_get_timedate(struct tm *tm, int offset);
27
-
33
+void qemu_get_timedate(struct tm *tm, time_t offset);
28
s->burst_length = 0;
34
35
/**
36
* qemu_timedate_diff: Return difference between a struct tm and the RTC
37
@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset);
38
* a timestamp one hour further ahead than the current RTC time
39
* then this function will return 3600.
40
*/
41
-int qemu_timedate_diff(struct tm *tm);
42
+time_t qemu_timedate_diff(struct tm *tm);
43
44
#endif
45
diff --git a/softmmu/rtc.c b/softmmu/rtc.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/softmmu/rtc.c
48
+++ b/softmmu/rtc.c
49
@@ -XXX,XX +XXX,XX @@ static time_t qemu_ref_timedate(QEMUClockType clock)
50
return value;
29
}
51
}
30
52
31
+static void imx_spi_soft_reset(IMXSPIState *s)
53
-void qemu_get_timedate(struct tm *tm, int offset)
32
+{
54
+void qemu_get_timedate(struct tm *tm, time_t offset)
33
+ imx_spi_reset(DEVICE(s));
34
+
35
+ imx_spi_update_irq(s);
36
+}
37
+
38
static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
39
{
55
{
40
uint32_t value = 0;
56
time_t ti = qemu_ref_timedate(rtc_clock);
41
@@ -XXX,XX +XXX,XX @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
57
42
s->regs[ECSPI_CONREG] = value;
58
@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset)
43
59
}
44
if (!imx_spi_is_enabled(s)) {
60
}
45
- /* device is disabled, so this is a reset */
61
46
- imx_spi_reset(DEVICE(s));
62
-int qemu_timedate_diff(struct tm *tm)
47
+ /* device is disabled, so this is a soft reset */
63
+time_t qemu_timedate_diff(struct tm *tm)
48
+ imx_spi_soft_reset(s);
64
{
49
+
65
time_t seconds;
50
return;
51
}
52
66
53
--
67
--
54
2.20.1
68
2.34.1
55
69
56
70
diff view generated by jsdifflib
[PULL 04/21] hw/arm/smmuv3: Fix addr_mask for range-based invalidation
[PULL 22/24] target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init
1
From: Zenghui Yu <yuzenghui@huawei.com>
1
Where architecturally one ARM_FEATURE_X flag implies another
2
2
ARM_FEATURE_Y, we allow the CPU init function to only set X, and then
3
When handling guest range-based IOTLB invalidation, we should decode the TG
3
set Y for it. Currently we do this in two places -- we set a few
4
field into the corresponding translation granule size so that we can pass
4
flags in arm_cpu_post_init() because we need them to decide which
5
the correct invalidation range to backend. Set @granule to (tg * 2 + 10) to
5
properties to create on the CPU object, and then we do the rest in
6
properly emulate the architecture.
6
arm_cpu_realizefn(). However, this is fragile, because it's easy to
7
7
add a new property and not notice that this means that an X-implies-Y
8
Fixes: d52915616c05 ("hw/arm/smmuv3: Get prepared for range invalidation")
8
check now has to move from realize to post-init.
9
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
9
10
Acked-by: Eric Auger <eric.auger@redhat.com>
10
As a specific example, the pmsav7-dregion property is conditional
11
Message-id: 20210130043220.1345-1-yuzenghui@huawei.com
11
on ARM_FEATURE_PMSA && ARM_FEATURE_V7, which means it won't appear
12
on the Cortex-M33 and -M55, because they set ARM_FEATURE_V8 and
13
rely on V8-implies-V7, which doesn't happen until the realizefn.
14
15
Move all of these X-implies-Y checks into a new function, which
16
we call at the top of arm_cpu_post_init(), so the feature bits
17
are available at that point.
18
19
This does now give us the reverse issue, that if there's a feature
20
bit which is enabled or disabled by the setting of a property then
21
then X-implies-Y features that are dependent on that property need to
22
be in realize, not in this new function. But the only one of those
23
is the "EL3 implies VBAR" which is already in the right place, so
24
putting things this way round seems better to me.
25
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
28
Message-id: 20230724174335.2150499-2-peter.maydell@linaro.org
13
---
29
---
14
hw/arm/smmuv3.c | 4 +++-
30
target/arm/cpu.c | 179 +++++++++++++++++++++++++----------------------
15
1 file changed, 3 insertions(+), 1 deletion(-)
31
1 file changed, 97 insertions(+), 82 deletions(-)
16
32
17
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
33
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
18
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/smmuv3.c
35
--- a/target/arm/cpu.c
20
+++ b/hw/arm/smmuv3.c
36
+++ b/target/arm/cpu.c
21
@@ -XXX,XX +XXX,XX @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr,
37
@@ -XXX,XX +XXX,XX @@ unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
38
NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
39
}
40
41
+static void arm_cpu_propagate_feature_implications(ARMCPU *cpu)
42
+{
43
+ CPUARMState *env = &cpu->env;
44
+ bool no_aa32 = false;
45
+
46
+ /*
47
+ * Some features automatically imply others: set the feature
48
+ * bits explicitly for these cases.
49
+ */
50
+
51
+ if (arm_feature(env, ARM_FEATURE_M)) {
52
+ set_feature(env, ARM_FEATURE_PMSA);
53
+ }
54
+
55
+ if (arm_feature(env, ARM_FEATURE_V8)) {
56
+ if (arm_feature(env, ARM_FEATURE_M)) {
57
+ set_feature(env, ARM_FEATURE_V7);
58
+ } else {
59
+ set_feature(env, ARM_FEATURE_V7VE);
60
+ }
61
+ }
62
+
63
+ /*
64
+ * There exist AArch64 cpus without AArch32 support. When KVM
65
+ * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
66
+ * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
67
+ * As a general principle, we also do not make ID register
68
+ * consistency checks anywhere unless using TCG, because only
69
+ * for TCG would a consistency-check failure be a QEMU bug.
70
+ */
71
+ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
72
+ no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
73
+ }
74
+
75
+ if (arm_feature(env, ARM_FEATURE_V7VE)) {
76
+ /*
77
+ * v7 Virtualization Extensions. In real hardware this implies
78
+ * EL2 and also the presence of the Security Extensions.
79
+ * For QEMU, for backwards-compatibility we implement some
80
+ * CPUs or CPU configs which have no actual EL2 or EL3 but do
81
+ * include the various other features that V7VE implies.
82
+ * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
83
+ * Security Extensions is ARM_FEATURE_EL3.
84
+ */
85
+ assert(!tcg_enabled() || no_aa32 ||
86
+ cpu_isar_feature(aa32_arm_div, cpu));
87
+ set_feature(env, ARM_FEATURE_LPAE);
88
+ set_feature(env, ARM_FEATURE_V7);
89
+ }
90
+ if (arm_feature(env, ARM_FEATURE_V7)) {
91
+ set_feature(env, ARM_FEATURE_VAPA);
92
+ set_feature(env, ARM_FEATURE_THUMB2);
93
+ set_feature(env, ARM_FEATURE_MPIDR);
94
+ if (!arm_feature(env, ARM_FEATURE_M)) {
95
+ set_feature(env, ARM_FEATURE_V6K);
96
+ } else {
97
+ set_feature(env, ARM_FEATURE_V6);
98
+ }
99
+
100
+ /*
101
+ * Always define VBAR for V7 CPUs even if it doesn't exist in
102
+ * non-EL3 configs. This is needed by some legacy boards.
103
+ */
104
+ set_feature(env, ARM_FEATURE_VBAR);
105
+ }
106
+ if (arm_feature(env, ARM_FEATURE_V6K)) {
107
+ set_feature(env, ARM_FEATURE_V6);
108
+ set_feature(env, ARM_FEATURE_MVFR);
109
+ }
110
+ if (arm_feature(env, ARM_FEATURE_V6)) {
111
+ set_feature(env, ARM_FEATURE_V5);
112
+ if (!arm_feature(env, ARM_FEATURE_M)) {
113
+ assert(!tcg_enabled() || no_aa32 ||
114
+ cpu_isar_feature(aa32_jazelle, cpu));
115
+ set_feature(env, ARM_FEATURE_AUXCR);
116
+ }
117
+ }
118
+ if (arm_feature(env, ARM_FEATURE_V5)) {
119
+ set_feature(env, ARM_FEATURE_V4T);
120
+ }
121
+ if (arm_feature(env, ARM_FEATURE_LPAE)) {
122
+ set_feature(env, ARM_FEATURE_V7MP);
123
+ }
124
+ if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
125
+ set_feature(env, ARM_FEATURE_CBAR);
126
+ }
127
+ if (arm_feature(env, ARM_FEATURE_THUMB2) &&
128
+ !arm_feature(env, ARM_FEATURE_M)) {
129
+ set_feature(env, ARM_FEATURE_THUMB_DSP);
130
+ }
131
+}
132
+
133
void arm_cpu_post_init(Object *obj)
22
{
134
{
23
SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu);
135
ARMCPU *cpu = ARM_CPU(obj);
24
IOMMUTLBEvent event;
136
25
- uint8_t granule = tg;
137
- /* M profile implies PMSA. We have to do this here rather than
26
+ uint8_t granule;
138
- * in realize with the other feature-implication checks because
27
139
- * we look at the PMSA bit to see if we should add some properties.
28
if (!tg) {
140
+ /*
29
SMMUEventInfo event = {.inval_ste_allowed = true};
141
+ * Some features imply others. Figure this out now, because we
30
@@ -XXX,XX +XXX,XX @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr,
142
+ * are going to look at the feature bits in deciding which
31
return;
143
+ * properties to add.
32
}
144
*/
33
granule = tt->granule_sz;
145
- if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
34
+ } else {
146
- set_feature(&cpu->env, ARM_FEATURE_PMSA);
35
+ granule = tg * 2 + 10;
147
- }
148
+ arm_cpu_propagate_feature_implications(cpu);
149
150
if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
151
arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
152
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
153
CPUARMState *env = &cpu->env;
154
int pagebits;
155
Error *local_err = NULL;
156
- bool no_aa32 = false;
157
158
/* Use pc-relative instructions in system-mode */
159
#ifndef CONFIG_USER_ONLY
160
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
161
cpu->isar.id_isar3 = u;
36
}
162
}
37
163
38
event.type = IOMMU_NOTIFIER_UNMAP;
164
- /* Some features automatically imply others: */
165
- if (arm_feature(env, ARM_FEATURE_V8)) {
166
- if (arm_feature(env, ARM_FEATURE_M)) {
167
- set_feature(env, ARM_FEATURE_V7);
168
- } else {
169
- set_feature(env, ARM_FEATURE_V7VE);
170
- }
171
- }
172
-
173
- /*
174
- * There exist AArch64 cpus without AArch32 support. When KVM
175
- * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
176
- * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
177
- * As a general principle, we also do not make ID register
178
- * consistency checks anywhere unless using TCG, because only
179
- * for TCG would a consistency-check failure be a QEMU bug.
180
- */
181
- if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
182
- no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
183
- }
184
-
185
- if (arm_feature(env, ARM_FEATURE_V7VE)) {
186
- /* v7 Virtualization Extensions. In real hardware this implies
187
- * EL2 and also the presence of the Security Extensions.
188
- * For QEMU, for backwards-compatibility we implement some
189
- * CPUs or CPU configs which have no actual EL2 or EL3 but do
190
- * include the various other features that V7VE implies.
191
- * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
192
- * Security Extensions is ARM_FEATURE_EL3.
193
- */
194
- assert(!tcg_enabled() || no_aa32 ||
195
- cpu_isar_feature(aa32_arm_div, cpu));
196
- set_feature(env, ARM_FEATURE_LPAE);
197
- set_feature(env, ARM_FEATURE_V7);
198
- }
199
- if (arm_feature(env, ARM_FEATURE_V7)) {
200
- set_feature(env, ARM_FEATURE_VAPA);
201
- set_feature(env, ARM_FEATURE_THUMB2);
202
- set_feature(env, ARM_FEATURE_MPIDR);
203
- if (!arm_feature(env, ARM_FEATURE_M)) {
204
- set_feature(env, ARM_FEATURE_V6K);
205
- } else {
206
- set_feature(env, ARM_FEATURE_V6);
207
- }
208
-
209
- /* Always define VBAR for V7 CPUs even if it doesn't exist in
210
- * non-EL3 configs. This is needed by some legacy boards.
211
- */
212
- set_feature(env, ARM_FEATURE_VBAR);
213
- }
214
- if (arm_feature(env, ARM_FEATURE_V6K)) {
215
- set_feature(env, ARM_FEATURE_V6);
216
- set_feature(env, ARM_FEATURE_MVFR);
217
- }
218
- if (arm_feature(env, ARM_FEATURE_V6)) {
219
- set_feature(env, ARM_FEATURE_V5);
220
- if (!arm_feature(env, ARM_FEATURE_M)) {
221
- assert(!tcg_enabled() || no_aa32 ||
222
- cpu_isar_feature(aa32_jazelle, cpu));
223
- set_feature(env, ARM_FEATURE_AUXCR);
224
- }
225
- }
226
- if (arm_feature(env, ARM_FEATURE_V5)) {
227
- set_feature(env, ARM_FEATURE_V4T);
228
- }
229
- if (arm_feature(env, ARM_FEATURE_LPAE)) {
230
- set_feature(env, ARM_FEATURE_V7MP);
231
- }
232
- if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
233
- set_feature(env, ARM_FEATURE_CBAR);
234
- }
235
- if (arm_feature(env, ARM_FEATURE_THUMB2) &&
236
- !arm_feature(env, ARM_FEATURE_M)) {
237
- set_feature(env, ARM_FEATURE_THUMB_DSP);
238
- }
239
240
/*
241
* We rely on no XScale CPU having VFP so we can use the same bits in the
39
--
242
--
40
2.20.1
243
2.34.1
41
42
diff view generated by jsdifflib
[PULL 10/21] hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled
[PULL 23/24] hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
M-profile CPUs generally allow configuration of the number of MPU
2
regions that they have. We don't currently model this, so our
3
implementations of some of the board models provide CPUs with the
4
wrong number of regions. RTOSes like Zephyr that hardcode the
5
expected number of regions may therefore not run on the model if they
6
are set up to run on real hardware.
2
7
3
When the block is disabled, only the ECSPI_CONREG register can
8
Add properties mpu-ns-regions and mpu-s-regions to the ARMV7M object,
4
be modified. Setting the EN bit enabled the device, clearing it
9
matching the ability of hardware to configure the number of Secure
5
"disables the block and resets the internal logic with the
10
and NonSecure regions separately. Our actual CPU implementation
6
exception of the ECSPI_CONREG" register.
11
doesn't currently support that, and it happens that none of the MPS
12
boards we model set the number of regions differently for Secure vs
13
NonSecure, so we provide an interface to the boards and SoCs that
14
won't need to change if we ever do add that functionality in future,
15
but make it an error to configure the two properties to different
16
values.
7
17
8
Ignore all other registers write except ECSPI_CONREG when the
18
(The property name on the CPU is the somewhat misnamed-for-M-profile
9
block is disabled.
19
"pmsav7-dregion", so we don't follow that naming convention for
20
the properties here. The TRM doesn't say what the CPU configuration
21
variable names are, so we pick something, and follow the lowercase
22
convention we already have for properties here.)
10
23
11
Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM),
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
chapter 21.7.3: Control Register (ECSPIx_CONREG)
25
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
26
Message-id: 20230724174335.2150499-3-peter.maydell@linaro.org
27
---
28
include/hw/arm/armv7m.h | 8 ++++++++
29
hw/arm/armv7m.c | 21 +++++++++++++++++++++
30
2 files changed, 29 insertions(+)
13
31
14
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
32
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
15
Signed-off-by: Bin Meng <bin.meng@windriver.com>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Message-id: 20210129132323.30946-7-bmeng.cn@gmail.com
18
Message-Id: <20210115153049.3353008-6-f4bug@amsat.org>
19
Signed-off-by: Bin Meng <bin.meng@windriver.com>
20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
23
hw/ssi/imx_spi.c | 13 +++++++++----
24
1 file changed, 9 insertions(+), 4 deletions(-)
25
26
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
27
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/ssi/imx_spi.c
34
--- a/include/hw/arm/armv7m.h
29
+++ b/hw/ssi/imx_spi.c
35
+++ b/include/hw/arm/armv7m.h
30
@@ -XXX,XX +XXX,XX @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
36
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M)
31
DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_spi_reg_name(index),
37
* + Property "vfp": enable VFP (forwarded to CPU object)
32
(uint32_t)value);
38
* + Property "dsp": enable DSP (forwarded to CPU object)
33
39
* + Property "enable-bitband": expose bitbanded IO
34
+ if (!imx_spi_is_enabled(s)) {
40
+ * + Property "mpu-ns-regions": number of Non-Secure MPU regions (forwarded
35
+ /* Block is disabled */
41
+ * to CPU object pmsav7-dregion property; default is whatever the default
36
+ if (index != ECSPI_CONREG) {
42
+ * for the CPU is)
37
+ /* Ignore access */
43
+ * + Property "mpu-s-regions": number of Secure MPU regions (default is
44
+ * whatever the default for the CPU is; must currently be set to the same
45
+ * value as mpu-ns-regions if the CPU implements the Security Extension)
46
* + Clock input "refclk" is the external reference clock for the systick timers
47
* + Clock input "cpuclk" is the main CPU clock
48
*/
49
@@ -XXX,XX +XXX,XX @@ struct ARMv7MState {
50
Object *idau;
51
uint32_t init_svtor;
52
uint32_t init_nsvtor;
53
+ uint32_t mpu_ns_regions;
54
+ uint32_t mpu_s_regions;
55
bool enable_bitband;
56
bool start_powered_off;
57
bool vfp;
58
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
59
index XXXXXXX..XXXXXXX 100644
60
--- a/hw/arm/armv7m.c
61
+++ b/hw/arm/armv7m.c
62
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
63
}
64
}
65
66
+ /*
67
+ * Real M-profile hardware can be configured with a different number of
68
+ * MPU regions for Secure vs NonSecure. QEMU's CPU implementation doesn't
69
+ * support that yet, so catch attempts to select that.
70
+ */
71
+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
72
+ s->mpu_ns_regions != s->mpu_s_regions) {
73
+ error_setg(errp,
74
+ "mpu-ns-regions and mpu-s-regions properties must have the same value");
75
+ return;
76
+ }
77
+ if (s->mpu_ns_regions != UINT_MAX &&
78
+ object_property_find(OBJECT(s->cpu), "pmsav7-dregion")) {
79
+ if (!object_property_set_uint(OBJECT(s->cpu), "pmsav7-dregion",
80
+ s->mpu_ns_regions, errp)) {
38
+ return;
81
+ return;
39
+ }
82
+ }
40
+ }
83
+ }
41
+
84
+
42
change_mask = s->regs[index] ^ value;
85
/*
43
86
* Tell the CPU where the NVIC is; it will fail realize if it doesn't
44
switch (index) {
87
* have one. Similarly, tell the NVIC where its CPU is.
45
@@ -XXX,XX +XXX,XX @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
88
@@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = {
46
TYPE_IMX_SPI, __func__);
89
false),
47
break;
90
DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true),
48
case ECSPI_TXDATA:
91
DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true),
49
- if (!imx_spi_is_enabled(s)) {
92
+ DEFINE_PROP_UINT32("mpu-ns-regions", ARMv7MState, mpu_ns_regions, UINT_MAX),
50
- /* Ignore writes if device is disabled */
93
+ DEFINE_PROP_UINT32("mpu-s-regions", ARMv7MState, mpu_s_regions, UINT_MAX),
51
- break;
94
DEFINE_PROP_END_OF_LIST(),
52
- } else if (fifo32_is_full(&s->tx_fifo)) {
95
};
53
+ if (fifo32_is_full(&s->tx_fifo)) {
96
54
/* Ignore writes if queue is full */
55
break;
56
}
57
--
97
--
58
2.20.1
98
2.34.1
59
99
60
100
diff view generated by jsdifflib
[PULL 02/21] hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled
[PULL 24/24] hw/arm: Set number of MPU regions correctly for an505, an521, an524
1
From: Iris Johnson <iris@modwiz.com>
1
The IoTKit, SSE200 and SSE300 all default to 8 MPU regions. The
2
2
MPS2/MPS3 FPGA images don't override these except in the case of
3
Currently the Exynos 4210 UART code always reports available FIFO space
3
AN547, which uses 16 MPU regions.
4
when the backend checks for buffer space. When the FIFO is disabled this
4
5
is behavior causes the backend chardev code to replace the data before the
5
Define properties on the ARMSSE object for the MPU regions (using the
6
guest can read it.
6
same names as the documented RTL configuration settings, and
7
7
following the pattern we already have for this device of using
8
This patch changes adds the logic to report the capacity properly when the
8
all-caps names as the RTL does), and set them in the board code.
9
FIFO is not being used.
9
10
10
We don't actually need to override the default except on AN547,
11
Buglink: https://bugs.launchpad.net/qemu/+bug/1913344
11
but it's simpler code to have the board code set them always
12
Signed-off-by: Iris Johnson <iris@modwiz.com>
12
rather than tracking which board subtypes want to set them to
13
Message-id: 20210128033655.1029577-1-iris@modwiz.com
13
a non-default value separately from what that value is.
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
15
Tho overall effect is that for mps2-an505, mps2-an521 and mps3-an524
16
we now correctly use 8 MPU regions, while mps3-an547 stays at its
17
current 16 regions.
18
19
It's possible some guest code wrongly depended on the previous
20
incorrectly modeled number of memory regions. (Such guest code
21
should ideally check the number of regions via the MPU_TYPE
22
register.) The old behaviour can be obtained with additional
23
-global arguments to QEMU:
24
25
For mps2-an521 and mps2-an524:
26
-global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 -global sse-200.CPU1_MPU_NS=16 -global sse-200.CPU1_MPU_S=16
27
28
For mps2-an505:
29
-global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16
30
31
NB that the way the implementation allows this use of -global
32
is slightly fragile: if the board code explicitly sets the
33
properties on the sse-200 object, this overrides the -global
34
command line option. So we rely on:
35
- the boards that need fixing all happen to use the SSE defaults
36
- we can write the board code to only set the property if it
37
is different from the default, rather than having all boards
38
explicitly set the property
39
- the board that does need to use a non-default value happens
40
to need to set it to the same value (16) we previously used
41
This works, but there are some kinds of refactoring of the
42
mps2-tz.c code that would break the support for -global here.
43
44
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1772
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
45
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
46
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
47
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
48
Message-id: 20230724174335.2150499-4-peter.maydell@linaro.org
16
---
49
---
17
hw/char/exynos4210_uart.c | 6 +++++-
50
include/hw/arm/armsse.h | 5 +++++
18
1 file changed, 5 insertions(+), 1 deletion(-)
51
hw/arm/armsse.c | 16 ++++++++++++++++
19
52
hw/arm/mps2-tz.c | 29 +++++++++++++++++++++++++++++
20
diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c
53
3 files changed, 50 insertions(+)
54
55
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
21
index XXXXXXX..XXXXXXX 100644
56
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/char/exynos4210_uart.c
57
--- a/include/hw/arm/armsse.h
23
+++ b/hw/char/exynos4210_uart.c
58
+++ b/include/hw/arm/armsse.h
24
@@ -XXX,XX +XXX,XX @@ static int exynos4210_uart_can_receive(void *opaque)
59
@@ -XXX,XX +XXX,XX @@
60
* (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an
61
* SSE-200 both are present; CPU0 in an SSE-200 has neither.
62
* Since the IoTKit has only one CPU, it does not have the CPU1_* properties.
63
+ * + QOM properties "CPU0_MPU_NS", "CPU0_MPU_S", "CPU1_MPU_NS" and "CPU1_MPU_S"
64
+ * which set the number of MPU regions on the CPUs. If there is only one
65
+ * CPU the CPU1 properties are not present.
66
* + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
67
* which are wired to its NVIC lines 32 .. n+32
68
* + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for
69
@@ -XXX,XX +XXX,XX @@ struct ARMSSE {
70
uint32_t exp_numirq;
71
uint32_t sram_addr_width;
72
uint32_t init_svtor;
73
+ uint32_t cpu_mpu_ns[SSE_MAX_CPUS];
74
+ uint32_t cpu_mpu_s[SSE_MAX_CPUS];
75
bool cpu_fpu[SSE_MAX_CPUS];
76
bool cpu_dsp[SSE_MAX_CPUS];
77
};
78
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/hw/arm/armsse.c
81
+++ b/hw/arm/armsse.c
82
@@ -XXX,XX +XXX,XX @@ static Property iotkit_properties[] = {
83
DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
84
DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
85
DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
86
+ DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
87
+ DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
88
DEFINE_PROP_END_OF_LIST()
89
};
90
91
@@ -XXX,XX +XXX,XX @@ static Property sse200_properties[] = {
92
DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false),
93
DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true),
94
DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true),
95
+ DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
96
+ DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
97
+ DEFINE_PROP_UINT32("CPU1_MPU_NS", ARMSSE, cpu_mpu_ns[1], 8),
98
+ DEFINE_PROP_UINT32("CPU1_MPU_S", ARMSSE, cpu_mpu_s[1], 8),
99
DEFINE_PROP_END_OF_LIST()
100
};
101
102
@@ -XXX,XX +XXX,XX @@ static Property sse300_properties[] = {
103
DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
104
DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
105
DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
106
+ DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
107
+ DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
108
DEFINE_PROP_END_OF_LIST()
109
};
110
111
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
112
return;
113
}
114
}
115
+ if (!object_property_set_uint(cpuobj, "mpu-ns-regions",
116
+ s->cpu_mpu_ns[i], errp)) {
117
+ return;
118
+ }
119
+ if (!object_property_set_uint(cpuobj, "mpu-s-regions",
120
+ s->cpu_mpu_s[i], errp)) {
121
+ return;
122
+ }
123
124
if (i > 0) {
125
memory_region_add_subregion_overlap(&s->cpu_container[i], 0,
126
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
127
index XXXXXXX..XXXXXXX 100644
128
--- a/hw/arm/mps2-tz.c
129
+++ b/hw/arm/mps2-tz.c
130
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass {
131
int uart_overflow_irq; /* number of the combined UART overflow IRQ */
132
uint32_t init_svtor; /* init-svtor setting for SSE */
133
uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */
134
+ uint32_t cpu0_mpu_ns; /* CPU0_MPU_NS setting for SSE */
135
+ uint32_t cpu0_mpu_s; /* CPU0_MPU_S setting for SSE */
136
+ uint32_t cpu1_mpu_ns; /* CPU1_MPU_NS setting for SSE */
137
+ uint32_t cpu1_mpu_s; /* CPU1_MPU_S setting for SSE */
138
const RAMInfo *raminfo;
139
const char *armsse_type;
140
uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */
141
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
142
#define MPS3_DDR_SIZE (2 * GiB)
143
#endif
144
145
+/* For cpu{0,1}_mpu_{ns,s}, means "leave at SSE's default value" */
146
+#define MPU_REGION_DEFAULT UINT32_MAX
147
+
148
static const uint32_t an505_oscclk[] = {
149
40000000,
150
24580000,
151
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
152
OBJECT(system_memory), &error_abort);
153
qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq);
154
qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor);
155
+ if (mmc->cpu0_mpu_ns != MPU_REGION_DEFAULT) {
156
+ qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_NS", mmc->cpu0_mpu_ns);
157
+ }
158
+ if (mmc->cpu0_mpu_s != MPU_REGION_DEFAULT) {
159
+ qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_S", mmc->cpu0_mpu_s);
160
+ }
161
+ if (object_property_find(OBJECT(iotkitdev), "CPU1_MPU_NS")) {
162
+ if (mmc->cpu1_mpu_ns != MPU_REGION_DEFAULT) {
163
+ qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_NS", mmc->cpu1_mpu_ns);
164
+ }
165
+ if (mmc->cpu1_mpu_s != MPU_REGION_DEFAULT) {
166
+ qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_S", mmc->cpu1_mpu_s);
167
+ }
168
+ }
169
qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
170
qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
171
qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
172
@@ -XXX,XX +XXX,XX @@ static void mps2tz_class_init(ObjectClass *oc, void *data)
25
{
173
{
26
Exynos4210UartState *s = (Exynos4210UartState *)opaque;
174
MachineClass *mc = MACHINE_CLASS(oc);
27
175
IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc);
28
- return fifo_empty_elements_number(&s->rx);
176
+ MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
29
+ if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
177
30
+ return fifo_empty_elements_number(&s->rx);
178
mc->init = mps2tz_common_init;
31
+ } else {
179
mc->reset = mps2_machine_reset;
32
+ return !(s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY);
180
iic->check = mps2_tz_idau_check;
33
+ }
181
+
182
+ /* Most machines leave these at the SSE defaults */
183
+ mmc->cpu0_mpu_ns = MPU_REGION_DEFAULT;
184
+ mmc->cpu0_mpu_s = MPU_REGION_DEFAULT;
185
+ mmc->cpu1_mpu_ns = MPU_REGION_DEFAULT;
186
+ mmc->cpu1_mpu_s = MPU_REGION_DEFAULT;
34
}
187
}
35
188
36
static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size)
189
static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc)
190
@@ -XXX,XX +XXX,XX @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data)
191
mmc->numirq = 96;
192
mmc->uart_overflow_irq = 48;
193
mmc->init_svtor = 0x00000000;
194
+ mmc->cpu0_mpu_s = mmc->cpu0_mpu_ns = 16;
195
mmc->sram_addr_width = 21;
196
mmc->raminfo = an547_raminfo;
197
mmc->armsse_type = TYPE_SSE300;
37
--
198
--
38
2.20.1
199
2.34.1
39
200
40
201
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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